From 2de97529a4c5a1922214ba0e6f0fb84cacbd0bc7 Mon Sep 17 00:00:00 2001 From: Luis Farias Date: Thu, 17 Mar 2022 20:01:53 -0700 Subject: [PATCH] O-RAN E Maintenance Release contribution for ODULOW Feature enhancements to 5G-FAPI TM, FHI Lib and wls_lib per FlexRan 21.03 This contribution is a joint collaboration of Intel and Tietoevry. Includes fixes for issues found during US Plugfest Nov 2021. More details in release notes. Documentation of the Front Haul Interface had the collaboration from Franciscus Bimi, Jonathan, Liao and Professor Ray Guang from National Taiwan University of Science and Technology (NTUST) Test Performed: Unit Tests using testmac and with odulow, FHI tests in loopback Issue-Id: ODULOW-17 Change-Id: I8ae58506e065068a3923711c18e5e8a66cc4c809 Signed-off-by: Luis Farias --- docs/Architecture-Overview_fh.rst | 286 +- docs/Assumptions_Dependencies.rst | 72 +- docs/Introduction_fh.rst | 3 +- docs/PTP-configuration_fh.rst | 575 +-- docs/Sample-Application_fh.rst | 130 +- docs/Setup-Configuration_fh.rst | 3940 +++++++++++++++-- ...d-ORAN-Fronthaul-Protocol-Implementation_fh.rst | 2290 +++++----- docs/build_prerequisite.rst | 15 +- docs/ecpri_ddp_profile.rst | 875 ++++ docs/fapi_5g_tm_build.rst | 93 +- docs/fapi_5g_tm_overview.rst | 12 +- docs/fapi_5g_tm_rel-notes.rst | 9 +- docs/images/5G-NR-L1app-Threads.jpg | Bin 0 -> 72626 bytes docs/images/O-RAN-FH-VNF.jpg | Bin 0 -> 182529 bytes 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.../cat_b/mu1_100mhz/119/config_file_o_ru.dat | 262 ++ .../usecase/cat_b/mu1_100mhz/119/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/119/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/2/config_file_o_du.dat | 2 +- .../cat_b/mu1_100mhz/2/config_file_o_ru.dat | 2 +- .../app/usecase/cat_b/mu1_100mhz/2/usecase_du.cfg | 68 + .../app/usecase/cat_b/mu1_100mhz/2/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/201/config_file_o_du.dat | 14 +- .../cat_b/mu1_100mhz/201/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/201/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/201/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/202/config_file_o_du.dat | 18 +- .../cat_b/mu1_100mhz/202/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/202/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/202/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/203/config_file_o_du.dat | 12 +- .../cat_b/mu1_100mhz/203/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/203/usecase_du.cfg | 68 + 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.../cat_b/mu1_100mhz/212/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/212/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/212/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/213/config_file_o_du.dat | 14 +- .../cat_b/mu1_100mhz/213/config_file_o_ru.dat | 4 +- .../usecase/cat_b/mu1_100mhz/213/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/213/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/214/config_file_o_du.dat | 14 +- .../cat_b/mu1_100mhz/214/config_file_o_ru.dat | 4 +- .../usecase/cat_b/mu1_100mhz/214/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/214/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/215/config_file_o_du.dat | 12 +- .../cat_b/mu1_100mhz/215/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/215/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/215/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/216/config_file_o_du.dat | 14 +- .../cat_b/mu1_100mhz/216/config_file_o_ru.dat | 2 +- .../usecase/cat_b/mu1_100mhz/216/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/216/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/221/config_file_o_du.dat | 212 + .../cat_b/mu1_100mhz/221/config_file_o_ru.dat | 229 + .../usecase/cat_b/mu1_100mhz/221/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/221/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/222/config_file_o_du.dat | 237 + .../cat_b/mu1_100mhz/222/config_file_o_ru.dat | 265 ++ .../usecase/cat_b/mu1_100mhz/222/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/222/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/223/config_file_o_du.dat | 226 + .../cat_b/mu1_100mhz/223/config_file_o_ru.dat | 260 ++ .../usecase/cat_b/mu1_100mhz/223/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/223/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/224/config_file_o_du.dat | 226 + .../cat_b/mu1_100mhz/224/config_file_o_ru.dat | 260 ++ .../usecase/cat_b/mu1_100mhz/224/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/224/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/225/config_file_o_du.dat | 228 + .../cat_b/mu1_100mhz/225/config_file_o_ru.dat | 262 ++ .../usecase/cat_b/mu1_100mhz/225/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/225/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/226/config_file_o_du.dat | 232 + .../cat_b/mu1_100mhz/226/config_file_o_ru.dat | 264 ++ .../usecase/cat_b/mu1_100mhz/226/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/226/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/231/config_file_o_du.dat | 212 + .../cat_b/mu1_100mhz/231/config_file_o_ru.dat | 229 + .../usecase/cat_b/mu1_100mhz/231/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/231/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/232/config_file_o_du.dat | 237 + .../cat_b/mu1_100mhz/232/config_file_o_ru.dat | 265 ++ .../usecase/cat_b/mu1_100mhz/232/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/232/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/233/config_file_o_du.dat | 226 + .../cat_b/mu1_100mhz/233/config_file_o_ru.dat | 260 ++ .../usecase/cat_b/mu1_100mhz/233/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/233/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/234/config_file_o_du.dat | 226 + .../cat_b/mu1_100mhz/234/config_file_o_ru.dat | 260 ++ .../usecase/cat_b/mu1_100mhz/234/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/234/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/235/config_file_o_du.dat | 228 + .../cat_b/mu1_100mhz/235/config_file_o_ru.dat | 262 ++ .../usecase/cat_b/mu1_100mhz/235/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/235/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/236/config_file_o_du.dat | 232 + .../cat_b/mu1_100mhz/236/config_file_o_ru.dat | 264 ++ .../usecase/cat_b/mu1_100mhz/236/usecase_du.cfg | 68 + .../usecase/cat_b/mu1_100mhz/236/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/3/config_file_o_du.dat | 230 + .../cat_b/mu1_100mhz/3/config_file_o_ru.dat | 237 + .../app/usecase/cat_b/mu1_100mhz/3/usecase_du.cfg | 68 + .../app/usecase/cat_b/mu1_100mhz/3/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/301/config_file_o_du.dat | 73 +- .../cat_b/mu1_100mhz/301/config_file_o_ru.dat | 198 +- .../usecase/cat_b/mu1_100mhz/301/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/301/usecase_du_icx.cfg | 59 + .../usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/302/config_file_o_du.dat | 76 +- .../cat_b/mu1_100mhz/302/config_file_o_ru.dat | 72 +- .../usecase/cat_b/mu1_100mhz/302/usecase_du.cfg | 54 + .../cat_b/mu1_100mhz/302/usecase_du_icx.cfg | 54 + .../usecase/cat_b/mu1_100mhz/302/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/303/config_file_o_du.dat | 79 +- .../cat_b/mu1_100mhz/303/config_file_o_ru.dat | 68 +- .../usecase/cat_b/mu1_100mhz/303/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/303/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/303/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/304/config_file_o_du.dat | 61 +- .../cat_b/mu1_100mhz/304/config_file_o_ru.dat | 46 +- .../usecase/cat_b/mu1_100mhz/304/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/304/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/304/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/305/config_file_o_du.dat | 74 +- .../cat_b/mu1_100mhz/305/config_file_o_ru.dat | 200 +- .../usecase/cat_b/mu1_100mhz/305/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/305/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/305/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/306/config_file_o_du.dat | 78 +- .../cat_b/mu1_100mhz/306/config_file_o_ru.dat | 63 +- .../usecase/cat_b/mu1_100mhz/306/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/306/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/306/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/311/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/311/config_file_o_ru.dat | 272 ++ .../usecase/cat_b/mu1_100mhz/311/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/311/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/311/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/312/config_file_o_du.dat | 206 + .../cat_b/mu1_100mhz/312/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/312/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/312/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/312/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/313/config_file_o_du.dat | 207 + .../cat_b/mu1_100mhz/313/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/313/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/313/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/313/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/314/config_file_o_du.dat | 217 + .../cat_b/mu1_100mhz/314/config_file_o_ru.dat | 264 ++ .../usecase/cat_b/mu1_100mhz/314/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/314/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/314/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/315/config_file_o_du.dat | 204 + .../cat_b/mu1_100mhz/315/config_file_o_ru.dat | 251 ++ .../usecase/cat_b/mu1_100mhz/315/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/315/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/315/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/316/config_file_o_du.dat | 208 + .../cat_b/mu1_100mhz/316/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/316/usecase_du.cfg | 55 + .../cat_b/mu1_100mhz/316/usecase_du_icx.cfg | 55 + .../usecase/cat_b/mu1_100mhz/316/usecase_ru.cfg | 51 + .../app/usecase/cat_b/mu1_100mhz/3301/avg_o_du.dat | 236 + .../cat_b/mu1_100mhz/3301/avg_o_du_tst377.dat | 241 ++ .../app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru.dat | 288 ++ .../cat_b/mu1_100mhz/3301/avg_o_ru_tst377.dat | 289 ++ .../mu1_100mhz/3301/avg_o_ru_tst377_dynamic.dat | 292 ++ .../cat_b/mu1_100mhz/3301/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3301/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3301/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3301/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3301/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3301/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3301/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3301/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3301/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3301/peak_o_du.dat | 247 ++ .../cat_b/mu1_100mhz/3301/peak_o_du_tst376.dat | 248 ++ .../usecase/cat_b/mu1_100mhz/3301/peak_o_ru.dat | 297 ++ .../cat_b/mu1_100mhz/3301/peak_o_ru_tst376.dat | 298 ++ .../mu1_100mhz/3301/peak_o_ru_tst376_dynamic.dat | 301 ++ .../cat_b/mu1_100mhz/3301/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3301/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3301/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3301/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3301/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3301/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3301/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg | 65 + .../cat_b/mu1_100mhz/3301/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg | 63 + .../cat_b/mu1_100mhz/3301/usecase_ru_csx.cfg | 61 + .../cat_b/mu1_100mhz/3301/usecase_ru_dynamic.cfg | 62 + .../app/usecase/cat_b/mu1_100mhz/3311/avg_o_du.dat | 236 + .../cat_b/mu1_100mhz/3311/avg_o_du_tst377.dat | 241 ++ .../app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru.dat | 288 ++ .../cat_b/mu1_100mhz/3311/avg_o_ru_tst377.dat | 289 ++ .../cat_b/mu1_100mhz/3311/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3311/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3311/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3311/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3311/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3311/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3311/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3311/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3311/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3311/peak_o_du.dat | 247 ++ .../cat_b/mu1_100mhz/3311/peak_o_du_tst376.dat | 248 ++ .../usecase/cat_b/mu1_100mhz/3311/peak_o_ru.dat | 297 ++ .../cat_b/mu1_100mhz/3311/peak_o_ru_tst376.dat | 298 ++ .../cat_b/mu1_100mhz/3311/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3311/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3311/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3311/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3311/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3311/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3311/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3311/usecase_du.cfg | 64 + .../cat_b/mu1_100mhz/3311/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3311/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3311/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3321/avg_o_du.dat | 236 + .../cat_b/mu1_100mhz/3321/avg_o_du_tst377.dat | 241 ++ .../app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru.dat | 288 ++ .../cat_b/mu1_100mhz/3321/avg_o_ru_tst377.dat | 289 ++ .../cat_b/mu1_100mhz/3321/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3321/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3321/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3321/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3321/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3321/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3321/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3321/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3321/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3321/peak_o_du.dat | 247 ++ .../cat_b/mu1_100mhz/3321/peak_o_du_tst376.dat | 248 ++ .../usecase/cat_b/mu1_100mhz/3321/peak_o_ru.dat | 297 ++ .../cat_b/mu1_100mhz/3321/peak_o_ru_tst376.dat | 298 ++ .../cat_b/mu1_100mhz/3321/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3321/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3321/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3321/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3321/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3321/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3321/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3321/usecase_du.cfg | 64 + .../cat_b/mu1_100mhz/3321/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3321/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3321/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3331/avg_o_du.dat | 236 + .../cat_b/mu1_100mhz/3331/avg_o_du_tst377.dat | 241 ++ .../app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru.dat | 288 ++ .../cat_b/mu1_100mhz/3331/avg_o_ru_tst377.dat | 289 ++ .../cat_b/mu1_100mhz/3331/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3331/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3331/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3331/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3331/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3331/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3331/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3331/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3331/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3331/peak_o_du.dat | 247 ++ .../cat_b/mu1_100mhz/3331/peak_o_du_tst376.dat | 248 ++ .../usecase/cat_b/mu1_100mhz/3331/peak_o_ru.dat | 297 ++ .../cat_b/mu1_100mhz/3331/peak_o_ru_tst376.dat | 298 ++ .../cat_b/mu1_100mhz/3331/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3331/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3331/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3331/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3331/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3331/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3331/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3331/usecase_du.cfg | 64 + .../cat_b/mu1_100mhz/3331/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3331/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3331/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3501/avg_o_du.dat | 265 ++ .../cat_b/mu1_100mhz/3501/avg_o_du_tst377.dat | 265 ++ .../app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru.dat | 315 ++ .../cat_b/mu1_100mhz/3501/avg_o_ru_tst377.dat | 315 ++ .../cat_b/mu1_100mhz/3501/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3501/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3501/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3501/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3501/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3501/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3501/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3501/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3501/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3501/peak_o_du.dat | 305 ++ .../cat_b/mu1_100mhz/3501/peak_o_du_tst376.dat | 305 ++ .../usecase/cat_b/mu1_100mhz/3501/peak_o_ru.dat | 353 ++ .../cat_b/mu1_100mhz/3501/peak_o_ru_tst376.dat | 353 ++ .../cat_b/mu1_100mhz/3501/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3501/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3501/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3501/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3501/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3501/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3501/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3501/usecase_du.cfg | 65 + .../cat_b/mu1_100mhz/3501/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3501/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3501/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3511/avg_o_du.dat | 265 ++ .../cat_b/mu1_100mhz/3511/avg_o_du_tst377.dat | 265 ++ .../app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru.dat | 315 ++ .../cat_b/mu1_100mhz/3511/avg_o_ru_tst377.dat | 315 ++ .../cat_b/mu1_100mhz/3511/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3511/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3511/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3511/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3511/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3511/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3511/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3511/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3511/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3511/peak_o_du.dat | 305 ++ .../cat_b/mu1_100mhz/3511/peak_o_du_tst376.dat | 305 ++ .../usecase/cat_b/mu1_100mhz/3511/peak_o_ru.dat | 353 ++ .../cat_b/mu1_100mhz/3511/peak_o_ru_tst376.dat | 353 ++ .../cat_b/mu1_100mhz/3511/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3511/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3511/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3511/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3511/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3511/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3511/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3511/usecase_du.cfg | 64 + .../cat_b/mu1_100mhz/3511/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3511/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3511/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3521/avg_o_du.dat | 265 ++ .../cat_b/mu1_100mhz/3521/avg_o_du_tst377.dat | 265 ++ .../app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru.dat | 315 ++ .../cat_b/mu1_100mhz/3521/avg_o_ru_tst377.dat | 315 ++ .../cat_b/mu1_100mhz/3521/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3521/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3521/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3521/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3521/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3521/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3521/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3521/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3521/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3521/peak_o_du.dat | 305 ++ .../cat_b/mu1_100mhz/3521/peak_o_du_tst376.dat | 305 ++ .../usecase/cat_b/mu1_100mhz/3521/peak_o_ru.dat | 353 ++ .../cat_b/mu1_100mhz/3521/peak_o_ru_tst376.dat | 353 ++ .../cat_b/mu1_100mhz/3521/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3521/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3521/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3521/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3521/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3521/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3521/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3521/usecase_du.cfg | 65 + .../cat_b/mu1_100mhz/3521/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3521/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3521/usecase_ru_csx.cfg | 61 + .../app/usecase/cat_b/mu1_100mhz/3531/avg_o_du.dat | 265 ++ .../cat_b/mu1_100mhz/3531/avg_o_du_tst377.dat | 265 ++ .../app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru.dat | 315 ++ .../cat_b/mu1_100mhz/3531/avg_o_ru_tst377.dat | 315 ++ .../cat_b/mu1_100mhz/3531/avg_rxconfig_0.cfg | 31 + .../cat_b/mu1_100mhz/3531/avg_rxconfig_1.cfg | 31 + .../cat_b/mu1_100mhz/3531/avg_rxconfig_2.cfg | 31 + .../cat_b/mu1_100mhz/3531/avg_rxconfig_3.cfg | 31 + .../cat_b/mu1_100mhz/3531/avg_txconfig_0.cfg | 32 + .../cat_b/mu1_100mhz/3531/avg_txconfig_1.cfg | 32 + .../cat_b/mu1_100mhz/3531/avg_txconfig_2.cfg | 32 + .../cat_b/mu1_100mhz/3531/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/3531/config_file_o_ru.dat | 274 ++ .../usecase/cat_b/mu1_100mhz/3531/peak_o_du.dat | 305 ++ .../cat_b/mu1_100mhz/3531/peak_o_du_tst376.dat | 305 ++ .../usecase/cat_b/mu1_100mhz/3531/peak_o_ru.dat | 353 ++ .../cat_b/mu1_100mhz/3531/peak_o_ru_tst376.dat | 353 ++ .../cat_b/mu1_100mhz/3531/peak_rxconfig_0.cfg | 34 + .../cat_b/mu1_100mhz/3531/peak_rxconfig_1.cfg | 34 + .../cat_b/mu1_100mhz/3531/peak_rxconfig_2.cfg | 34 + .../cat_b/mu1_100mhz/3531/peak_rxconfig_3.cfg | 34 + .../cat_b/mu1_100mhz/3531/peak_txconfig_0.cfg | 35 + .../cat_b/mu1_100mhz/3531/peak_txconfig_1.cfg | 35 + .../cat_b/mu1_100mhz/3531/peak_txconfig_2.cfg | 36 + .../usecase/cat_b/mu1_100mhz/3531/usecase_du.cfg | 64 + .../cat_b/mu1_100mhz/3531/usecase_du_csx.cfg | 63 + .../usecase/cat_b/mu1_100mhz/3531/usecase_ru.cfg | 62 + .../cat_b/mu1_100mhz/3531/usecase_ru_csx.cfg | 61 + .../cat_b/mu1_100mhz/4/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/4/config_file_o_ru.dat | 260 ++ .../app/usecase/cat_b/mu1_100mhz/4/usecase_du.cfg | 68 + .../app/usecase/cat_b/mu1_100mhz/4/usecase_ru.cfg | 68 + .../cat_b/mu1_100mhz/401/config_file_o_du.dat | 232 + .../cat_b/mu1_100mhz/401/config_file_o_ru.dat | 268 ++ .../usecase/cat_b/mu1_100mhz/401/usecase_du.cfg | 69 + .../usecase/cat_b/mu1_100mhz/401/usecase_ru.cfg | 55 + .../cat_b/mu1_100mhz/411/config_file_o_du.dat | 232 + .../cat_b/mu1_100mhz/411/config_file_o_ru.dat | 268 ++ .../usecase/cat_b/mu1_100mhz/411/usecase_du.cfg | 69 + .../usecase/cat_b/mu1_100mhz/411/usecase_ru.cfg | 55 + .../cat_b/mu1_100mhz/501/config_file_o_du.dat | 281 ++ .../cat_b/mu1_100mhz/501/config_file_o_ru.dat | 328 ++ .../usecase/cat_b/mu1_100mhz/501/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/501/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/501/usecase_ru.cfg | 57 + .../cat_b/mu1_100mhz/502/config_file_o_du.dat | 240 + .../cat_b/mu1_100mhz/502/config_file_o_ru.dat | 289 ++ .../usecase/cat_b/mu1_100mhz/502/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/502/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/502/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/503/config_file_o_du.dat | 241 ++ .../cat_b/mu1_100mhz/503/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/503/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/503/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/503/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/504/config_file_o_du.dat | 240 + .../cat_b/mu1_100mhz/504/config_file_o_ru.dat | 290 ++ .../usecase/cat_b/mu1_100mhz/504/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/504/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/504/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/505/config_file_o_du.dat | 241 ++ .../cat_b/mu1_100mhz/505/config_file_o_ru.dat | 285 ++ .../usecase/cat_b/mu1_100mhz/505/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/505/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/505/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/506/config_file_o_du.dat | 242 ++ .../cat_b/mu1_100mhz/506/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/506/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/506/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/506/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/511/config_file_o_du.dat | 281 ++ .../cat_b/mu1_100mhz/511/config_file_o_ru.dat | 328 ++ .../usecase/cat_b/mu1_100mhz/511/usecase_du.cfg | 59 + .../cat_b/mu1_100mhz/511/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/511/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/512/config_file_o_du.dat | 240 + .../cat_b/mu1_100mhz/512/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/512/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/512/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/512/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/513/config_file_o_du.dat | 241 ++ .../cat_b/mu1_100mhz/513/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/513/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/513/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/513/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/514/config_file_o_du.dat | 240 + .../cat_b/mu1_100mhz/514/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/514/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/514/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/514/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/515/config_file_o_du.dat | 241 ++ .../cat_b/mu1_100mhz/515/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/515/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/515/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/515/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/516/config_file_o_du.dat | 242 ++ .../cat_b/mu1_100mhz/516/config_file_o_ru.dat | 284 ++ .../usecase/cat_b/mu1_100mhz/516/usecase_du.cfg | 58 + .../cat_b/mu1_100mhz/516/usecase_du_icx.cfg | 58 + .../usecase/cat_b/mu1_100mhz/516/usecase_ru.cfg | 56 + .../cat_b/mu1_100mhz/601/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/601/config_file_o_ru.dat | 272 ++ .../usecase/cat_b/mu1_100mhz/601/usecase_du.cfg | 58 + .../usecase/cat_b/mu1_100mhz/601/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/602/config_file_o_du.dat | 206 + .../cat_b/mu1_100mhz/602/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/602/usecase_du.cfg | 54 + .../usecase/cat_b/mu1_100mhz/602/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/603/config_file_o_du.dat | 207 + .../cat_b/mu1_100mhz/603/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/603/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/603/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/604/config_file_o_du.dat | 217 + .../cat_b/mu1_100mhz/604/config_file_o_ru.dat | 264 ++ .../usecase/cat_b/mu1_100mhz/604/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/604/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/605/config_file_o_du.dat | 204 + .../cat_b/mu1_100mhz/605/config_file_o_ru.dat | 251 ++ .../usecase/cat_b/mu1_100mhz/605/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/605/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/606/config_file_o_du.dat | 208 + .../cat_b/mu1_100mhz/606/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/606/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/606/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/611/config_file_o_du.dat | 223 + .../cat_b/mu1_100mhz/611/config_file_o_ru.dat | 272 ++ .../usecase/cat_b/mu1_100mhz/611/usecase_du.cfg | 58 + .../usecase/cat_b/mu1_100mhz/611/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/612/config_file_o_du.dat | 206 + .../cat_b/mu1_100mhz/612/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/612/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/612/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/613/config_file_o_du.dat | 207 + .../cat_b/mu1_100mhz/613/config_file_o_ru.dat | 250 ++ .../usecase/cat_b/mu1_100mhz/613/usecase_du.cfg | 55 + .../usecase/cat_b/mu1_100mhz/613/usecase_ru.cfg | 51 + .../cat_b/mu1_100mhz/614/config_file_o_du.dat | 217 + .../cat_b/mu1_100mhz/614/config_file_o_ru.dat | 264 ++ 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fhi_lib/lib/api/xran_pkt_up.h | 28 +- fhi_lib/lib/api/xran_sync_api.h | 2 +- fhi_lib/lib/api/xran_timer.h | 17 +- fhi_lib/lib/api/xran_transport.h | 4 +- fhi_lib/lib/api/xran_up_api.h | 8 +- fhi_lib/lib/ethernet/ethdi.c | 404 +- fhi_lib/lib/ethernet/ethdi.h | 80 +- fhi_lib/lib/ethernet/ethernet.c | 278 +- fhi_lib/lib/ethernet/ethernet.h | 103 +- fhi_lib/lib/src/xran_app_frag.c | 111 +- fhi_lib/lib/src/xran_app_frag.h | 12 +- fhi_lib/lib/src/xran_bfp_byte_packing_utils.hpp | 714 +++ fhi_lib/lib/src/xran_bfp_cplane16.cpp | 3 +- fhi_lib/lib/src/xran_bfp_cplane16_snc.cpp | 403 ++ fhi_lib/lib/src/xran_bfp_cplane32.cpp | 3 +- fhi_lib/lib/src/xran_bfp_cplane32_snc.cpp | 432 ++ fhi_lib/lib/src/xran_bfp_cplane64.cpp | 3 +- fhi_lib/lib/src/xran_bfp_cplane64_snc.cpp | 431 ++ fhi_lib/lib/src/xran_bfp_cplane8.cpp | 3 +- fhi_lib/lib/src/xran_bfp_cplane8_snc.cpp | 452 ++ fhi_lib/lib/src/xran_bfp_ref.cpp | 2 +- fhi_lib/lib/src/xran_bfp_uplane.cpp | 435 ++ fhi_lib/lib/src/xran_bfp_uplane_9b16rb.cpp | 164 + fhi_lib/lib/src/xran_bfp_uplane_snc.cpp | 432 ++ fhi_lib/lib/src/xran_bfp_utils.hpp | 339 +- fhi_lib/lib/src/xran_cb_proc.c | 628 +++ fhi_lib/lib/src/xran_cb_proc.h | 49 + fhi_lib/lib/src/xran_common.c | 892 +++- fhi_lib/lib/src/xran_common.h | 326 +- fhi_lib/lib/src/xran_compression.cpp | 512 +-- fhi_lib/lib/src/xran_compression_snc.cpp | 270 ++ fhi_lib/lib/src/xran_cp_api.c | 1451 +++++-- fhi_lib/lib/src/xran_cp_proc.c | 584 +++ fhi_lib/lib/src/xran_cp_proc.h | 336 ++ fhi_lib/lib/src/xran_delay_measurement.c | 1418 ++++++ fhi_lib/lib/src/xran_dev.c | 480 ++ fhi_lib/lib/src/xran_dev.h | 334 ++ fhi_lib/lib/src/xran_ecpri_owd_measurements.h | 79 + fhi_lib/lib/src/xran_frame_struct.c | 124 +- fhi_lib/lib/src/xran_frame_struct.h | 18 +- fhi_lib/lib/src/xran_main.c | 4565 +++++++++----------- fhi_lib/lib/src/xran_main.h | 65 + fhi_lib/lib/src/xran_mem_mgr.c | 185 + fhi_lib/lib/src/xran_mem_mgr.h | 48 + fhi_lib/lib/src/xran_mod_compression.cpp | 941 ++++ fhi_lib/lib/src/xran_mod_compression.h | 97 + fhi_lib/lib/src/xran_prach_cfg.h | 109 + fhi_lib/lib/src/xran_printf.h | 15 +- fhi_lib/lib/src/xran_rx_proc.c | 454 ++ fhi_lib/lib/src/xran_rx_proc.h | 108 + fhi_lib/lib/src/xran_sync_api.c | 4 +- fhi_lib/lib/src/xran_timer.c | 58 +- fhi_lib/lib/src/xran_transport.c | 65 +- fhi_lib/lib/src/xran_tx_proc.c | 1573 +++++++ fhi_lib/lib/src/xran_tx_proc.h | 90 + fhi_lib/lib/src/xran_ul_tables.c | 4 +- fhi_lib/lib/src/xran_up_api.c | 132 +- fhi_lib/test/common/common.cpp | 15 +- fhi_lib/test/common/common.hpp | 15 +- fhi_lib/test/common/common_typedef_xran.h | 15 +- fhi_lib/test/common/xran_lib_wrap.hpp | 462 +- fhi_lib/test/common/xranlib_unit_test_main.cc | 16 +- fhi_lib/test/master.py | 641 ++- fhi_lib/test/test_xran/Makefile | 146 +- fhi_lib/test/test_xran/c_plane_tests.cc | 581 ++- fhi_lib/test/test_xran/chain_tests.cc | 22 +- fhi_lib/test/test_xran/compander_functional.cc | 547 ++- fhi_lib/test/test_xran/conf.json | 383 +- fhi_lib/test/test_xran/init_sys_functional.cc | 22 +- .../test/test_xran/mod_compression_unit_test.cc | 85 + fhi_lib/test/test_xran/prach_functional.cc | 10 +- fhi_lib/test/test_xran/prach_performance.cc | 12 +- fhi_lib/test/test_xran/u_plane_functional.cc | 17 +- fhi_lib/test/test_xran/u_plane_performance.cc | 133 +- fhi_lib/test/test_xran/unittests.cc | 2 +- wls_lib/Makefile | 149 +- wls_lib/build.sh | 6 +- wls_lib/syslib.c | 2 +- wls_lib/syslib.h | 2 +- wls_lib/test/bin/fapi/fapi.sh | 18 +- wls_lib/test/bin/mac/mac.sh | 18 +- wls_lib/test/bin/phy/phy.sh | 18 +- wls_lib/test/fapi/fapi_main.c | 17 +- wls_lib/test/fapi/makefile | 30 +- wls_lib/test/mac/mac_main.c | 3 +- wls_lib/test/mac/mac_wls.c | 20 +- wls_lib/test/mac/mac_wls.h | 4 +- wls_lib/test/mac/makefile | 39 +- wls_lib/test/phy/makefile | 33 +- wls_lib/test/phy/phy_main.c | 15 +- wls_lib/testapp/Makefile | 157 +- wls_lib/testapp/pool.c | 2 +- wls_lib/testapp/pool.h | 2 +- wls_lib/testapp/testapp.c | 423 +- wls_lib/testapp/wls_test.sh | 38 +- wls_lib/ttypes.h | 2 +- wls_lib/wls.h | 55 +- wls_lib/wls_lib.h | 15 +- wls_lib/wls_lib_dpdk.c | 265 +- 1004 files changed, 124692 insertions(+), 14478 deletions(-) create mode 100644 docs/ecpri_ddp_profile.rst create mode 100644 docs/images/5G-NR-L1app-Threads.jpg create mode 100644 docs/images/O-RAN-FH-VNF.jpg create mode 100644 docs/images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3-for.jpg create mode 100644 docs/images/ecpri-one-way-delay-measurement-message.jpg create mode 100644 fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_add_remove_core_msg.c create mode 100644 fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_uci_ind.c create mode 100644 fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_vendor_p7_msgs.c create mode 100644 fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c create mode 100644 fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.c create mode 100644 fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.h create mode 100644 fapi_5g/source/include/nr5g_fapi_snr_conversion.h create mode 100644 fapi_5g/source/utils/nr5g_fapi_snr_conversion.c create mode 100644 fhi_lib/app/src/app_io_fh_xran.c create mode 100644 fhi_lib/app/src/app_io_fh_xran.h create mode 100644 fhi_lib/app/src/app_profile_xran.c create mode 100644 fhi_lib/app/src/app_profile_xran.h rename fhi_lib/app/usecase/{ => cat_a}/mu0_10mhz/12/config_file_o_du.dat (61%) create mode 100644 fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu0_10mhz/config_file_o_du.dat (61%) rename fhi_lib/app/usecase/{ => cat_a}/mu0_10mhz/config_file_o_ru.dat (59%) create mode 100644 fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu0_20mhz/12/config_file_o_du.dat (61%) create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_0.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_1.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_0.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_1.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_ru.cfg rename fhi_lib/app/usecase/{mu0_20mhz => cat_a/mu0_20mhz/23}/config_file_o_du.dat (76%) rename fhi_lib/app/usecase/{mu0_20mhz => cat_a/mu0_20mhz/23}/config_file_o_ru.dat (76%) create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu0_5mhz/config_file_o_du.dat (81%) rename fhi_lib/app/usecase/{ => cat_a}/mu0_5mhz/config_file_o_ru.dat (78%) create mode 100644 fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/101/config_file_o_du.dat (84%) rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/101/config_file_o_ru.dat (75%) create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/102/config_file_o_du.dat (84%) rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/102/config_file_o_ru.dat (75%) create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/2/config_file_o_du.dat (83%) rename fhi_lib/app/usecase/{ => cat_a}/mu1_100mhz/2/config_file_o_ru.dat (73%) create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_ru.cfg rename fhi_lib/app/usecase/{mu1_100mhz/config_file_o_ru.dat => cat_a/mu1_100mhz/config_file_o_du.dat} (71%) create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu3_100mhz/1/config_file_o_du.dat (83%) rename fhi_lib/app/usecase/{ => cat_a}/mu3_100mhz/1/config_file_o_ru.dat (73%) create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_ru.cfg rename fhi_lib/app/usecase/{ => cat_a}/mu3_100mhz/101/config_file_o_du.dat (79%) rename fhi_lib/app/usecase/{ => cat_a}/mu3_100mhz/101/config_file_o_ru.dat (68%) create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_ru.cfg rename fhi_lib/app/usecase/{mu1_100mhz/config_file_o_du.dat => cat_a/mu3_100mhz/201/mu1_config_file_o_du.dat} (80%) create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_ru.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_du.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_ru.cfg create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_du.dat create mode 100644 fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_ru.dat create mode 100644 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create mode 100644 fhi_lib/lib/src/xran_main.h create mode 100644 fhi_lib/lib/src/xran_mem_mgr.c create mode 100644 fhi_lib/lib/src/xran_mem_mgr.h create mode 100644 fhi_lib/lib/src/xran_mod_compression.cpp create mode 100644 fhi_lib/lib/src/xran_mod_compression.h create mode 100644 fhi_lib/lib/src/xran_prach_cfg.h create mode 100644 fhi_lib/lib/src/xran_rx_proc.c create mode 100644 fhi_lib/lib/src/xran_rx_proc.h create mode 100644 fhi_lib/lib/src/xran_tx_proc.c create mode 100644 fhi_lib/lib/src/xran_tx_proc.h create mode 100644 fhi_lib/test/test_xran/mod_compression_unit_test.cc diff --git a/docs/Architecture-Overview_fh.rst b/docs/Architecture-Overview_fh.rst index 3538e69..72476b2 100644 --- a/docs/Architecture-Overview_fh.rst +++ b/docs/Architecture-Overview_fh.rst @@ -12,9 +12,6 @@ .. See the License for the specific language governing permissions and .. limitations under the License. -.. |br| raw:: html - -
Architecture Overview ===================== @@ -23,18 +20,24 @@ Architecture Overview :depth: 3 :local: -This section provides an overview of the xRAN architecture. +This section provides an overview of the O-RAN architecture. .. _introduction-1: Introduction ------------ -The front haul interface, according to the ORAN Fronthaul specification, -performs communication between O-RAN Distributed Unit (O-DU) and O-RAN -Radio Unit (O-RU) and consists of multiple HW and SW components. +The front haul interface, according to the O-RAN Fronthaul +specification, is part of the 5G NR L1 reference implementation provided +with the FlexRAN software package. It performs communication between +O-RAN Distributed Unit (O-DU) and O-RAN Radio Unit (O-RU) and consists +of multiple HW and SW components. + +The logical representation of HW and SW components is shown in *Figure +1*. -The logical representation of HW and SW components is shown in Figure 1. +The same architecture design is applicable for LTE; however, the FH +library is not integrated with the PHY pipeline for FlexRAN LTE. .. image:: images/Architecture-Block-Diagram.jpg :width: 600 @@ -42,8 +45,8 @@ The logical representation of HW and SW components is shown in Figure 1. Figure 1. Architecture Block Diagram -|br| -|br| + + From the hardware perspective, two networking ports are used to communicate to the Front Haul and Back (Mid) Haul network as well as to @@ -52,68 +55,77 @@ receive PTP synchronization. The system timer is used to provide a From the software perspective, the following components are used: -* Linux PTP provides synchronization of system timer to GPS time: +* Linux\* PTP provides synchronization of system timer to GPS time: + - ptp4l is used to synchronize oscillator on Network Interface Controller (NIC) to PTP GM. + - phc2sys is used to synchronize system timer to oscillator on NIC. - - Ptp4l is used to synchronize oscillator on Network Interface - Controller (NIC) to PTP GM. +* The DPDK to provide the interface to the Ethernet port. - - Phc2sys is used to synchronize system timer to oscillator on NIC. +* O-RAN library is built on top of DPDK to perform U-plane and C-plane functionality according to the O-RAN Fronthaul specification. -* DPDK to provide the interface to the Ethernet port. +* 5GNR reference PHY uses the O-RAN library to access interface to O-RU. The interface between the library and PHY is defined to communicate TTI event, symbol time, C-plane information as well as IQ sample data. -* xRAN library is built on top of DPDK to perform U-plane and C-plane - functionality according to the ORAN Fronthaul specification. +* 5G NR PHY communicates with the L2 application using the set of MAC/PHY APIs and the shared memory interface defined as WLS. -* 5GNR reference PHY uses the xRAN library to access interface to O-RU. - The interface between the library and PHY is defined to communicate - TTI event, symbol time, C-plane information as well as IQ sample - data. +* L2, in turn, can use Back (Mid) Haul networking port to connect to the CU unit in the context of 3GPP specification. -* 5G NR PHY communicates with the L2 application using the set of - MAC/PHY APIs and the shared memory interface defined as WLS. +In this document, we focus on details of the design and implementation +of the O-RAN library for providing Front Haul functionality for both +mmWave and Sub-6 scenarios as well as LTE. -* L2, in turn, can use Back (Mid) Haul networking port to connect to - the CU unit in the context of 3GPP specification. - -In this document, we focus on the details of the design and -implementation of the xRAN library with respect to providing Front Haul -functionality for both mmWave and Sub-6 scenarios. - -The xRAN M-plane is not implemented and is outside of the scope of this +The O-RAN M-plane is not implemented and is outside of the scope of this description. Configuration files are used to specify selected M-plane level parameters. -ORAN FH Threads ---------------- +5G NR L1 Application Threads +---------------------------- + +The specifics of the L1 application design and configuration for the +given scenario can be found in document 603577, *FlexRAN 5G NR Reference +Solution RefPHY* (Doxygen) (refer to *Table 2*) Only information +relevant to front haul is presented in this section. + +Configuration of l1app with O-RAN interface for Front Haul is illustrated +acting as an O-DU in *Figure 2*. -ORAN FH Thread Performs: +.. image:: images/5G-NR-L1app-Threads.jpg + :width: 600 + :alt: Figure 2. 5G NR L1app Threads + +Figure 2. 5G NR L1app Threads + +In this configuration of L1app, the base architecture of 5G NR L1 is not +changed. The original Front Haul FPGA interface was updated with the +O-RAN fronthaul interface abstracted via the O-RAN library. + +O-RAN FH Thread Performs: -- Symbol base “time event” to the rest of the system based on System - Clock synchronized to GPS time via PTP. +- Symbol base “time event” to the rest of the system based on System Clock synchronized to GPS time via PTP -- Baseline polling mode driver performing TX and RX of Ethernet packets. +- Baseline polling mode driver performing TX and RX of Ethernet packets -- Most of the packet processing such as Transport header, Application - header, Data section header and interactions with the rest of the PHY - processing pipeline. +- Most of the packet processing such as Transport header, Application header, Data section header, and interactions with the rest of the PHY processing pipeline. -- Polling of other call back function that was registered. +- Polling of BBDev for FEC on PAC N3000 acceleration card -ORAN FH thread created the independent of usage of xRAN as an interface -to the Radio. +The other threads are standard for the L1app and created the independent +usage of O-RAN as an interface to the Radio. -Communication between L1 and xRAN layer is performed using a set of -callback functions where L1 assigned callback and xRAN layer executes +Communication between L1 and O-RAN layer is performed using a set of +callback functions where L1 assigned callback and O-RAN layer executes those functions at a particular event or time moment. Detailed -information on callback function options and setting as well as design, +information on callback function options and setting, as well as design, can be found in the sections below. +Design and installation of the l1app do not depend on the Host, VM, or +container environment and the same for all cases. + Sample Application Thread Model ------------------------------- -Configuration of a sample application for both O-DU and O-RU follows the -model of 5G NR l1app application in the section of xRAN only. No BBU or -FEC related threads are needed as minimal xRAN functionality is used +Configuration of a sample application for both the O-DU and O-RU follows +the model of 5G NR l1app application in *Figure 2*, but no BBU or FEC +related threads are needed as minimal O-RAN FH functionality is used only. .. image:: images/Sample-Application-Threads.jpg @@ -122,17 +134,15 @@ only. Figure 3. Sample Application Threads -|br| -|br| - In this scenario, the main thread is used only for initializing and closing the application. No execution happens on core 0 during run time. Functional Split ---------------- -Figure 1 corresponds to the O-RU part of the xRAN split. Implementation -of the RU side of the xRAN protocol is not covered in this document. +Figure 1 corresponds to the O-RU part of the O-RAN split. +Implementation of the RU side of the O-RAN protocol is not covered in +this document. .. image:: images/eNB-gNB-Architecture-with-O-DU-and-RU.jpg :width: 600 @@ -140,16 +150,17 @@ of the RU side of the xRAN protocol is not covered in this document. Figure 4. eNB/gNB Architecture with O-DU and RU -|br| -|br| + + More than one RU can be supported with the same implementation of the -xRAN library and depends on the configuration of gNB in general. In this -document, we address details of implementation for single O-DU – O-RU +O-RAN library and depends on the configuration of gNB in general. In this +document, we address details of implementation for a single O-DU – O-RU connection. -The ORAN Fronthaul specification provides two categories of the split of -Layer 1 functionality between O-DU and O‑RU: Category A and Category B. +The O-RAN Fronthaul specification provides two categories of the split +of Layer 1 functionality between O-DU and O-RU: Category A and Category +B. .. image:: images/Functional-Split.jpg :width: 600 @@ -157,24 +168,24 @@ Layer 1 functionality between O-DU and O‑RU: Category A and Category B. Figure 5. Functional Split -|br| + Data Flow --------- -|br| + Table 3 lists the data flows supported for a single RU with a single Component Carrier. -|br| -|br| + + Table 3. Supported Data Flow +---------+----+-----------------+-----------------+----------------+ | Plane | ID | Name | Contents | Periodicity | -+---------+----+-----------------+-----------------+----------------+ ++=========+====+=================+=================+================+ | U-Plane | 1a | DL Frequency | DL user data | symbol | | | | Domain IQ Data | (PDSCH), | | | | | | control channel | | @@ -199,39 +210,31 @@ Table 3. Supported Data Flow | | | | PRACH | | | | | | scheduling | | +---------+----+-----------------+-----------------+----------------+ -| S-Plane | S | Timing and | IEEE 1588 PTP | | +| S-Plane | S | Timing and | IEEE 1588 PTP | - | | | | Synchronization | packets | | +---------+----+-----------------+-----------------+----------------+ -|br| -|br| - .. image:: images/Data-Flows.jpg :width: 600 :alt: Figure 6. Data Flows Figure 6. Data Flows -|br| -|br| + + Information on specific features of C-Plane and U-plane provided in -Section 6.0. Configuration of S-plane used on test setup for simulation -is provided in Appendix Appendix 2. +Sample Application Section Configuration of S-plane used on +test setup for simulation is provided in Appendix 2. Data flow separation is based on VLAN (applicable when layer 2 or layer 3 is used for the C/U-plane transport.) -#. The mechanism for assigning VLAN ID to U-Plane and C-Plane is assumed -to be via the M-Plane. +* The mechanism for assigning VLAN ID to U-Plane and C-Plane is assumed to be via the M-Plane. -VLAN Tag is configurable via the standard Linux IP tool (refer to -Appendix Appendix 1). +* VLAN Tag is configurable via the standard Linux IP tool, refer to Appendix A, Setup Configuration. -No Quality of Service (QoS) is supported. - -|br| -|br| +* No Quality of Service (QoS) is implemented as part of O-RAN library. Standard functionality of ETH port can be used to implement QoS. .. image:: images/C-plane-and-U-plane-Packet-Exchange.jpg :width: 600 @@ -239,157 +242,151 @@ No Quality of Service (QoS) is supported. Figure 7. C-plane and U-plane Packet Exchange -|br| -|br| + + Timing, Latency, and Synchronization to GPS ------------------------------------------- -The ORAN Fronthaul specification defines the latency model of the front -haul interface and interaction between O-DU and O-RU. This -implementation of the xRAN library supports only the category with fixed -timing advance and Defined Transport method. It determines O-DU transmit -and receive windows based on pre-defined transport network characteristics, and the delay characteristics of the RUs within the +The O-RAN Fronthaul specification defines the latency model of the front +haul interface and interaction between O-DU and 0-RU. This +implementation of the O-RAN library supports only the category with fixed +timing advance and Defined Transport methods. It determines O-DU +transmit and receive windows based on pre-defined transport network +characteristics, and the delay characteristics of the RUs within the timing domain. Table 4 below provides default values used for the implementation of -O-DU – O-RU simulation with mmWave scenario. Table 5 and Table 6 below +O-DU – O-RU simulation with mmWave scenario. Table 5 and *Table 6* below provide default values used for the implementation of O-DU – O-RU simulation with numerology 0 and numerology 1 for Sub6 scenarios. -Configuration can be adjusted via configuration files for sample |br| -application and reference PHY. However, simulation of the different -range of the settings was not performed, and additional implementation changes might be required as well as testing with actual O-RU. The -parameters for the front haul network are out of scope as a direct connection between O-DU and 0-RU is used for simulation. +Configuration can be adjusted via configuration files for sample +application and reference PHY. -|br| -|br| +However, simulation of the different range of the settings was not +performed, and additional implementation changes might be required as +well as testing with actual O-RU. The parameters for the front haul +network are out of scope as a direct connection between O-DU and 0-RU +is used for simulation. Table 4. Front Haul Interface Latency (numerology 3 - mmWave) +------+------------+-------------------+-------------------+----------------+------------+ -| | Model | C-Plane | U-Plane | | | -| | Parameters | | | | | -+------+------------+-------------------+-------------------+----------------+------------+ +| | Model | C-Plane | U-Plane | +| | Parameters | | | ++ + +-------------------+-------------------+----------------+------------+ | | | DL | UL | DL | UL | +------+------------+-------------------+-------------------+----------------+------------+ | O-RU | T2amin | T2a_min_cp_dl=50 | T2a_min_cp_ul=50 | T2a_min_up=25 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | T2amax | T2a_max_cp_dl=140 | T2a_max_cp_ul=140 | T2a_max_up=140 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | |   | Tadv_cp_dl | NA | NA | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta3min | NA | NA | NA | Ta3_min=20 | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta3max | NA | NA | NA | Ta3_max=32 | +------+------------+-------------------+-------------------+----------------+------------+ | O-DU | T1amin | T1a_min_cp_dl=70 | T1a_min_cp_ul=60 | T1a_min_up=35 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | T1amax | T1a_max_cp_dl=100 | T1a_max_cp_ul=70 | T1a_max_up=50 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta4min | NA | NA | NA | Ta4_min=0 | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta4max | NA | NA | NA | Ta4_max=45 | +------+------------+-------------------+-------------------+----------------+------------+ -|br| -|br| -|br| - Table 5. Front Haul Interface Latency (numerology 0 - Sub6) +------+----------+----------+----------+----------+----------+ -| | Model | C-Plane | U-Plane | | | +| | Model | C-Plane | | U-Plane | | | | Pa | | | | | | | rameters | | | | | -+------+----------+----------+----------+----------+----------+ ++ + +----------+----------+----------+----------+ | | | DL | UL | DL | UL | +------+----------+----------+----------+----------+----------+ | O-RU | T2amin | T | T | T2a_mi | NA | | | | 2a_min_c | 2a_min_c | n_up=200 | | | | | p_dl=400 | p_ul=400 | | | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | T2amax | T2 | T2 | T2a_max | NA | | | | a_max_cp | a_max_cp | _up=1120 | | | | | _dl=1120 | _ul=1120 | | | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | |   | Ta | NA | NA | NA | | | | dv_cp_dl | | | | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | Ta3min | NA | NA | NA | Ta3 | | | | | | | _min=160 | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | Ta3max | NA | NA | NA | Ta3 | | | | | | | _max=256 | +------+----------+----------+----------+----------+----------+ | O-DU | T1amin | T | T | T1a_mi | NA | | | | 1a_min_c | 1a_min_c | n_up=280 | | | | | p_dl=560 | p_ul=480 | | | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | T1amax | T | T | T1a_ma | NA | | | | 1a_max_c | 1a_max_c | x_up=400 | | | | | p_dl=800 | p_ul=560 | | | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | Ta4min | NA | NA | NA | T | | | | | | | a4_min=0 | -+------+----------+----------+----------+----------+----------+ ++ +----------+----------+----------+----------+----------+ | | Ta4max | NA | NA | NA | Ta4 | | | | | | | _max=360 | +------+----------+----------+----------+----------+----------+ -|br| -|br| -|br| + + + Table 6. Front Haul Interface Latency (numerology 1 - Sub6) +------+------------+-------------------+-------------------+----------------+------------+ | | Model | C-Plane | U-Plane | | | | | Parameters | | | | | -+------+------------+-------------------+-------------------+----------------+------------+ ++ + +-------------------+-------------------+----------------+------------+ | | | DL | UL | DL | UL | +------+------------+-------------------+-------------------+----------------+------------+ | O-RU | T2amin | T2a_min_cp_dl=285 | T2a_min_cp_ul=285 | T2a_min_up=71 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | T2amax | T2a_max_cp_dl=429 | T2a_max_cp_ul=429 | T2a_max_up=428 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | |   | Tadv_cp_dl | NA | NA | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta3min | NA | NA | NA | Ta3_min=20 | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta3max | NA | NA | NA | Ta3_max=32 | +------+------------+-------------------+-------------------+----------------+------------+ | O-DU | T1amin | T1a_min_cp_dl=285 | T1a_min_cp_ul=285 | T1a_min_up=96 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | T1amax | T1a_max_cp_dl=429 | T1a_max_cp_ul=300 | T1a_max_up=196 | NA | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta4min | NA | NA | NA | Ta4_min=0 | -+------+------------+-------------------+-------------------+----------------+------------+ ++ +------------+-------------------+-------------------+----------------+------------+ | | Ta4max | NA | NA | NA | Ta4_max=75 | +------+------------+-------------------+-------------------+----------------+------------+ -|br| -|br| -|br| + + + IEEE 1588 protocol and PTP for Linux\* implementations are used to synchronize local time to GPS time. Details of the configuration used -are provided in Appendix Appendix 2. Local time is used to get Top of -the Second (ToS) as a 1pps event for SW implementation. Timing event is -obtained by performing polling of local time using clock_gettime(CLOCK_REALTIME,..) +are provided in Appendix B, PTP Configuration. Local time is used to get +Top of the Second (ToS) as a 1 PPS event for SW implementation. Timing +event is obtained by performing polling of local time using +clock_gettime(CLOCK_REALTIME,..) -All-time intervals are specified with respect to GPS time which +All-time intervals are specified concerning the GPS time, which corresponds to OTA time. -|br| -|br| -|br| - Virtualization and Container-Based Usage ---------------------------------------- -xRAN implementation is deployment agnostic and does not require special -changes to be used in virtualized or |br| -container-based deployment options. +O-RAN implementation is deployment agnostic and does not require special +changes to be used in virtualized or container-based deployment options. The only requirement is to provide one SRIOV base virtual port for C-plane and one port for U-plane traffic per O-DU instance. This can be achieved with the default Virtual Infrastructure Manager (VIM) as well @@ -397,3 +394,6 @@ as using standard container networking. +To configure the networking ports, refer to the FlexRAN and Mobile Edge +Compute (MEC) Platform Setup Guide (*Table 2*) and readme.md in O-RAN +library or Appendix A. diff --git a/docs/Assumptions_Dependencies.rst b/docs/Assumptions_Dependencies.rst index 29aae62..f34ba5e 100644 --- a/docs/Assumptions_Dependencies.rst +++ b/docs/Assumptions_Dependencies.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -12,52 +12,88 @@ .. See the License for the specific language governing permissions and .. limitations under the License. -.. |br| raw:: html -
- - -Assumptions and Dependencies -=============================== +Assumptions, Dependencies, and Constraints +========================================== .. contents:: :depth: 3 :local: -This chapter contains the assumptions, requirements and dependencies for the O-DU Low current implementation. +This chapter contains limitations on the scope of the document. Assumptions ----------- An L1 with a proprietary interface and a testmac supporting the FAPI interface are available through the Open Source Community(OSC) github in binary blob form and with the reference -files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU +files that support the tests required for the current O-RAN Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU High to check network functionality are available from the same site. The L1 App and Testmac repository is at https://github.com/intel/FlexRAN/ + Requirements ------------ -* Only Xeon® series Processor with Intel Architecture are supported and the platform should be |br| - either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency. +* Only Xeon® series Processor with Intel Architecture are supported and the platform should be either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency. * FPGA/ASIC card for FEC acceleration that is compliant with the BBDev framework and interface. Only needed to run high throughput cases with the HW FEC card assistance. * Bios setting steps and options may have differences, however at least you should have the same Bios setting as decribed in the README.md file available at https://github.com/intel/FlexRAN Bios settings section. * Running with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization. + Dependencies ------------ -* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries). +O-RAN library implementation depends on the Data Plane Development Kit +(DPDK v20.11). + +DPDK v20.11 should be patched with corresponding DPDK patch provided +with FlexRAN release (see *Table 1*, FlexRAN Reference Solution Software +Release Notes) + +Intel® C++ Compiler v19.0.3 is used. + +- Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64). + +Constraints +----------- + +This release has been designed and implemented to support the following +numerologies defined in the 3GPP specifications for LTE and 5GNR (refer +to *Table 2*): + +5G NR +~~~~~ + +Category A support: + +- Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells in 2x2 antenna configuration +- Numerology 0 with bandwidth 40 MHz with 1 cell. + +- Numerology 1 with bandwidth 20/40 MHz with 1 cell and URLLC use cases for 40 MHz +- Numerology 1 with bandwidth 100 MHz with up to 16 cells + +- Numerology 3 with bandwidth 100 MHz with up to 3 cells + +Category B support: -* RT Kernel kernel-rt-3.10.0-1062.12.1.rt56.1042 +Numerology 1 with bandwidth 100 MHz where the antenna panel is up to +64T64R with up to 3 cells. -* Data Plane Development Kit (DPDK v19.11) with corresponding DPDK patch according to |br| O-RAN FH setup configuration section. +LTE +~~~ -* FEC SDK lib which is needed when you run the FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules +Category A support: -* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you get is always the latest ICC version, the verification for that version might not have been performed yet, please feedback through O-DU Low WIKI page if you meet any issues. - https://software.intel.com/en-us/system-studio/choose-download +Bandwidth 5/10/20 MHz with up to 12 cells -* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App. Only needed to run the sample APP for O-RAN FHI. +Category B support: +Bandwidth 5/10/20 MHz for 1 cell +The feature set of O-RAN protocol should be aligned with Radio Unit +(O-RU) implementation. Inter-operability testing (IoT) is required to +confirm the correctness of functionality on both sides. The exact +feature set supported is described in Chapter *4.0* *Transport Layer and +O-RAN Fronthaul Protocol Implementation* of this document. +- diff --git a/docs/Introduction_fh.rst b/docs/Introduction_fh.rst index 06861aa..ca8d8b1 100644 --- a/docs/Introduction_fh.rst +++ b/docs/Introduction_fh.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -26,6 +26,7 @@ O-RAN FH Lib Introduction Sample-Application_fh.rst Setup-Configuration_fh.rst PTP-configuration_fh.rst + ecpri_ddp_profile.rst diff --git a/docs/PTP-configuration_fh.rst b/docs/PTP-configuration_fh.rst index 52e35ce..52d5135 100644 --- a/docs/PTP-configuration_fh.rst +++ b/docs/PTP-configuration_fh.rst @@ -12,23 +12,21 @@ .. See the License for the specific language governing permissions and .. limitations under the License. -.. |br| raw:: html -
- -PTP configuration +PTP Configuration ================= -A.5 PTP Synchronization ------------------------ +PTP Synchronization +=================== + Precision Time Protocol (PTP) provides an efficient way to synchronize -time on the network nodes. This protocol uses Primary-Slave architecture. -Main Reference Clock (Primary) is a reference clock for the other nodes, -which adapt their clocks to the Primary. +time on the network nodes. This protocol uses Master-Slave architecture. +Grandmaster Clock (Master) is a reference clock for the other nodes, +which adapt their clocks to the master. -Using Physical Hardware Clock (PHC) from the Main Reference Clock, NIC port -precision timestamp packets can be served for other network nodes. Secondary -nodes adjust their PHC to the Primary following the IEEE 1588 +Using Physical Hardware Clock (PHC) from the Grandmaster Clock, NIC port +precision timestamp packets can be served for other network nodes. Slave +nodes adjust their PHC to the master following the IEEE 1588 specification. There are existing implementations of PTP protocol that are widely used @@ -37,16 +35,16 @@ providing necessary PTP functionality. There is no need to re-implement the 1588 protocol because PTP for Linux is precise and efficient enough to be used out of the box. -To meet xRAN requirements, two tools from PTP for Linux package are +To meet O-RAN requirements, two tools from PTP for Linux package are required: ptp4l and phc2sys. PTP for Linux\* Requirements ----------------------------- +============================ PTP for Linux\* introduces some software and hardware requirements. The machine on which the tools will be run needs to use at least a 3.10 -Kernel version (built-in PTP support). There are several Kernel options -that need to be enabled in Kernel configuration: +Kernel version (built-in PTP support). Several Kernel options need to be +enabled in Kernel configuration: - CONFIG_PPS @@ -57,143 +55,104 @@ that need to be enabled in Kernel configuration: Be sure that the Kernel is compiled with these options. For the best precision, PTP uses hardware timestamping. NIC has its own -clock, called Physical Hardware Clock (PHC) to read current time just a +clock, called Physical Hardware Clock (PHC), to read current time just a moment before the packet is sent to minimalize the delays added by the Kernel processing the packet. Not every NIC supports that feature. To confirm that currently attached NIC support Hardware Timestamps, use -ethtool with the command: +ethtool with the command:: ethtool -T eth0 -where eth0 is the potential PHC port. The output from the command should -say that there is Hardware Timestamps support. +Where the eth0 is the potential PHC port. The output from the command +should say that there is Hardware Timestamps support. To set up PTP for Linux*: 1.Download source code:: git clone http://git.code.sf.net/p/linuxptp/code linuxptp - git checkout v2.0 -2.Apply patch (this is required to work around issue with some of the -GM PTP packet size.):: +*Note* Apply patch (this is required to work around an issue with some of the GM PTP packet sizes.) :: diff --git a/msg.c b/msg.c - old mode 100644 - new mode 100755 - index d1619d4..40d1538 - --- a/msg.c - +++ b/msg.c - - @@ -399,9 +399,11 @@ int msg_post_recv(struct ptp_message \*m, int cnt) - + @@ -399,9 +399,11 @@ int msg_post_recv(struct ptp_message *m, int cnt) port_id_post_recv(&m->pdelay_resp.requestingPortIdentity); - break; - case FOLLOW_UP: - + cnt -= 4; - timestamp_post_recv(m, &m->follow_up.preciseOriginTimestamp); - break; - case DELAY_RESP: - + cnt -= 4; - timestamp_post_recv(m, &m->delay_resp.receiveTimestamp); - port_id_post_recv(&m->delay_resp.requestingPortIdentity); - break; -3.Build and install ptp41:: +2. Build and install ptp41. :: # make && make install -4.Modify configs/default.cfg to control frequency of Sync interval to -0.0625s:: +22. Modify configs/default.cfg to control frequency of Sync interval to 0.0625 s. :: logSyncInterval -4 ptp4l ----------- +===== This tool handles all PTP traffic on the provided NIC port and updated -PHC. It also determines the Primary Reference Clock and tracks synchronization +PHC. It also determines the Grandmaster Clock and tracks synchronization status. This tool can be run as a daemon or as a regular Linux\* application. When the synchronization is reached, it gives output on the screen for precision tracking. The configuration file of ptp4l contains many options that can be set to get the best synchronization precision. -Although, even with default.cfg the synchronization quality is good. +Although, even with default.cfg the synchronization quality is +excellent. To start the synchronization process run:: cd linuxptp - ./ptp4l -f ./configs/default.cfg -2 -i -m -The output below shows what the output on non-Primary node should look +The output below shows what the output on non-master node should look like when synchronization is started. This means that PHC on this -machine is synchronized to the Primary PHC:: +machine is synchronized to the master PHC. :: ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE - ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE - - ptp4l[1434166.384]: port 1: new foreign primary fcaf6a.fffe.029708-1 - - ptp4l[1434170.352]: selected best primary clock fcaf6a.fffe.029708 - + ptp4l[1434166.384]: port 1: new foreign master fcaf6a.fffe.029708-1 + ptp4l[1434170.352]: selected best master clock fcaf6a.fffe.029708 ptp4l[1434170.352]: updating UTC offset to 37 - ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE - - ptp4l[1434171.763]: primary offset -5873 s0 freq -18397 path delay 2778 - - ptp4l[1434172.763]: primary offset -6088 s2 freq -18612 path delay 2778 - - ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on - MASTER_CLOCK_SELECTED - - ptp4l[1434173.763]: primary offset -5886 s2 freq -24498 path delay 2732 - - ptp4l[1434174.763]: primary offset 221 s2 freq -20157 path delay 2728 - - ptp4l[1434175.763]: primary offset 1911 s2 freq -18401 path delay 2724 - - ptp4l[1434176.763]: primary offset 1774 s2 freq -17964 path delay 2728 - - ptp4l[1434177.763]: primary offset 1198 s2 freq -18008 path delay 2728 - - ptp4l[1434178.763]: primary offset 746 s2 freq -18101 path delay 2755 - - ptp4l[1434179.763]: primary offset 218 s2 freq -18405 path delay 2792 - - ptp4l[1434180.763]: primary offset 103 s2 freq -18454 path delay 2792 - - ptp4l[1434181.763]: primary offset -13 s2 freq -18540 path delay 2813 - - ptp4l[1434182.763]: primary offset 9 s2 freq -18521 path delay 2813 - - ptp4l[1434183.763]: primary offset 11 s2 freq -18517 path delay 2813 + ptp4l[1434171.763]: master offset -5873 s0 freq -18397 path delay 2778 + ptp4l[1434172.763]: master offset -6088 s2 freq -18612 path delay 2778 + ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED + ptp4l[1434173.763]: master offset -5886 s2 freq -24498 path delay 2732 + ptp4l[1434174.763]: master offset 221 s2 freq -20157 path delay 2728 + ptp4l[1434175.763]: master offset 1911 s2 freq -18401 path delay 2724 + ptp4l[1434176.763]: master offset 1774 s2 freq -17964 path delay 2728 + ptp4l[1434177.763]: master offset 1198 s2 freq -18008 path delay 2728 + ptp4l[1434178.763]: master offset 746 s2 freq -18101 path delay 2755 + ptp4l[1434179.763]: master offset 218 s2 freq -18405 path delay 2792 + ptp4l[1434180.763]: master offset 103 s2 freq -18454 path delay 2792 + ptp4l[1434181.763]: master offset -13 s2 freq -18540 path delay 2813 + ptp4l[1434182.763]: master offset 9 s2 freq -18521 path delay 2813 + ptp4l[1434183.763]: master offset 11 s2 freq -18517 path delay 2813 phc2sys ------------ +======= The PHC clock is independent from the system clock. Synchronizing only -PHC does not make the system clock exactly the same as the primary. The +PHC does not make the system clock exactly the same as the master. The xRAN library requires use of the system clock to determine a common point in time on two machines (O-DU and RU) to start transmission at the -same moment and keep time frames defined by ORAN Fronthaul specification. +same moment and keep time frames defined by O-RAN Fronthaul +specification. This application keeps the system clock updated to PHC. It makes it possible to use POSIX timers as a time reference in xRAN application. @@ -201,396 +160,214 @@ possible to use POSIX timers as a time reference in xRAN application. Run phc2sys with the command:: cd linuxptp - ./phc2sys -s enp25s0f0 -w -m -R 8 Command output will look like:: ptp4l[1434165.342]: selected /dev/ptp4 as PTP - - phc2sys[1434344.651]: CLOCK_REALTIME phc offset 450 s2 freq -39119 delay - 1354 - - phc2sys[1434344.776]: CLOCK_REALTIME phc offset 499 s2 freq -38620 delay - 1344 - - phc2sys[1434344.902]: CLOCK_REALTIME phc offset 485 s2 freq -38484 delay - 1347 - - phc2sys[1434345.027]: CLOCK_REALTIME phc offset 476 s2 freq -38348 delay - 1346 - - phc2sys[1434345.153]: CLOCK_REALTIME phc offset 392 s2 freq -38289 delay - 1340 - - phc2sys[1434345.278]: CLOCK_REALTIME phc offset 319 s2 freq -38244 delay - 1340 - - phc2sys[1434345.404]: CLOCK_REALTIME phc offset 278 s2 freq -38190 delay - 1349 - - phc2sys[1434345.529]: CLOCK_REALTIME phc offset 221 s2 freq -38163 delay - 1343 - - phc2sys[1434345.654]: CLOCK_REALTIME phc offset 97 s2 freq -38221 delay - 1342 - - phc2sys[1434345.780]: CLOCK_REALTIME phc offset 67 s2 freq -38222 delay - 1344 - - phc2sys[1434345.905]: CLOCK_REALTIME phc offset 68 s2 freq -38201 delay - 1341 - - phc2sys[1434346.031]: CLOCK_REALTIME phc offset 104 s2 freq -38144 delay - 1340 - - phc2sys[1434346.156]: CLOCK_REALTIME phc offset 58 s2 freq -38159 delay - 1340 - - phc2sys[1434346.281]: CLOCK_REALTIME phc offset 12 s2 freq -38188 delay - 1343 - - phc2sys[1434346.407]: CLOCK_REALTIME phc offset -36 s2 freq -38232 delay - 1342 - - phc2sys[1434346.532]: CLOCK_REALTIME phc offset -103 s2 freq -38310 - delay 1348 + phc2sys[1434344.651]: CLOCK_REALTIME phc offset 450 s2 freq -39119 delay 1354 + phc2sys[1434344.776]: CLOCK_REALTIME phc offset 499 s2 freq -38620 delay 1344 + phc2sys[1434344.902]: CLOCK_REALTIME phc offset 485 s2 freq -38484 delay 1347 + phc2sys[1434345.027]: CLOCK_REALTIME phc offset 476 s2 freq -38348 delay 1346 + phc2sys[1434345.153]: CLOCK_REALTIME phc offset 392 s2 freq -38289 delay 1340 + phc2sys[1434345.278]: CLOCK_REALTIME phc offset 319 s2 freq -38244 delay 1340 + phc2sys[1434345.404]: CLOCK_REALTIME phc offset 278 s2 freq -38190 delay 1349 + phc2sys[1434345.529]: CLOCK_REALTIME phc offset 221 s2 freq -38163 delay 1343 + phc2sys[1434345.654]: CLOCK_REALTIME phc offset 97 s2 freq -38221 delay 1342 + phc2sys[1434345.780]: CLOCK_REALTIME phc offset 67 s2 freq -38222 delay 1344 + phc2sys[1434345.905]: CLOCK_REALTIME phc offset 68 s2 freq -38201 delay 1341 + phc2sys[1434346.031]: CLOCK_REALTIME phc offset 104 s2 freq -38144 delay 1340 + phc2sys[1434346.156]: CLOCK_REALTIME phc offset 58 s2 freq -38159 delay 1340 + phc2sys[1434346.281]: CLOCK_REALTIME phc offset 12 s2 freq -38188 delay 1343 + phc2sys[1434346.407]: CLOCK_REALTIME phc offset -36 s2 freq -38232 delay 1342 + phc2sys[1434346.532]: CLOCK_REALTIME phc offset -103 s2 freq -38310 delay 1348 Configuration C3 ------------------- +================ Configuration C3 27 can be simulated for O-DU using a separate server acting as Fronthaul Network and O-RU at the same time. O-RU server can -be configured to relay PTP and act as PTP primary for O-DU. Settings +be configured to relay PTP and act as PTP master for O-DU. Settings below can be used to instantiate this scenario. The difference is that on the O-DU side, the Fronthaul port can be used as the source of PTP as well as for U-plane and C-plane traffic. -1.Follow the steps in Section A.6.1 to install PTP on the O-RU server. +1. Follow the steps in Appendix *B.1.1,* *PTP for Linux\* Requirements* +to install PTP on the O-RU server. 2.Copy configs/default.cfg to configs/default_slave.cfg and modify the -copied file as below:: +Copied file as below:: diff --git a/configs/default.cfg b/configs/default.cfg - old mode 100644 - new mode 100755 - index e23dfd7..f1ecaf1 - --- a/configs/default.cfg - +++ b/configs/default.cfg - @@ -3,26 +3,26 @@ - # Default Data Set - # - twoStepFlag 1 - -slaveOnly 0 - +slaveOnly 1 - priority1 128 - -priority2 128 - +priority2 255 - domainNumber 0 - #utc_offset 37 - -clockClass 248 - +clockClass 255 - clockAccuracy 0xFE - offsetScaledLogVariance 0xFFFF - free_running 0 - freq_est_interval 1 - dscp_event 0 - dscp_general 0 - -dataset_comparison ieee1588 - +dataset_comparison G.8275.x - G.8275.defaultDS.localPriority 128 - maxStepsRemoved 255 - # - # Port Data Set - # - logAnnounceInterval 1 - -logSyncInterval 0 - +logSyncInterval -4 - operLogSyncInterval 0 - logMinDelayReqInterval 0 - logMinPdelayReqInterval 0 - @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128 - asCapable auto - BMCA ptp - inhibit_announce 0 - -inhibit_pdelay_req 0 - +#inhibit_pdelay_req 0 - ignore_source_id 0 - # - # Run time options -1.Start secondary port toward PTP GM:: + +3. Start slave port toward PTP GM:: ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 –m Example of output:: ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 -m - ptp4l[3904470.256]: selected /dev/ptp6 as PTP clock - ptp4l[3904470.274]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE - ptp4l[3904470.275]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE - - ptp4l[3904471.085]: port 1: new foreign primary fcaf6a.fffe.029708-1 - - ptp4l[3904475.053]: selected best primary clock fcaf6a.fffe.029708 - + ptp4l[3904471.085]: port 1: new foreign master fcaf6a.fffe.029708-1 + ptp4l[3904475.053]: selected best master clock fcaf6a.fffe.029708 ptp4l[3904475.053]: updating UTC offset to 37 - ptp4l[3904475.053]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE + ptp4l[3904477.029]: master offset 196 s0 freq -18570 path delay 1109 + ptp4l[3904478.029]: master offset 212 s2 freq -18554 path delay 1109 + ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED + ptp4l[3904479.029]: master offset 86 s2 freq -18468 path delay 1109 + ptp4l[3904480.029]: master offset 23 s2 freq -18505 path delay 1124 + ptp4l[3904481.029]: master offset 3 s2 freq -18518 path delay 1132 + ptp4l[3904482.029]: master offset -169 s2 freq -18689 path delay 1141 - ptp4l[3904477.029]: primary offset 196 s0 freq -18570 path delay 1109 - - ptp4l[3904478.029]: primary offset 212 s2 freq -18554 path delay 1109 - - ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on - MASTER_CLOCK_SELECTED - - ptp4l[3904479.029]: primary offset 86 s2 freq -18468 path delay 1109 - - ptp4l[3904480.029]: primary offset 23 s2 freq -18505 path delay 1124 - - ptp4l[3904481.029]: primary offset 3 s2 freq -18518 path delay 1132 - - ptp4l[3904482.029]: primary offset -169 s2 freq -18689 path delay 1141 - -2.Synchronize local timer clock on O-RU for sample application:: +4. Synchronize local timer clock on O-RU for sample application :: ./phc2sys -s enp25s0f0 -w -m -R 8 Example of output:: ./phc2sys -s enp25s0f0 -w -m -R 8 - - phc2sys[3904510.892]: CLOCK_REALTIME phc offset 343 s0 freq -38967 delay - 1530 - - phc2sys[3904511.017]: CLOCK_REALTIME phc offset 368 s2 freq -38767 delay - 1537 - - phc2sys[3904511.142]: CLOCK_REALTIME phc offset 339 s2 freq -38428 delay - 1534 - - phc2sys[3904511.267]: CLOCK_REALTIME phc offset 298 s2 freq -38368 delay - 1532 - - phc2sys[3904511.392]: CLOCK_REALTIME phc offset 239 s2 freq -38337 delay - 1534 - - phc2sys[3904511.518]: CLOCK_REALTIME phc offset 145 s2 freq -38360 delay - 1530 - - phc2sys[3904511.643]: CLOCK_REALTIME phc offset 106 s2 freq -38355 delay - 1527 - - phc2sys[3904511.768]: CLOCK_REALTIME phc offset -30 s2 freq -38459 delay - 1534 - - phc2sys[3904511.893]: CLOCK_REALTIME phc offset -92 s2 freq -38530 delay - 1530 - - phc2sys[3904512.018]: CLOCK_REALTIME phc offset -173 s2 freq -38639 - delay 1528 - - phc2sys[3904512.143]: CLOCK_REALTIME phc offset -246 s2 freq -38764 - delay 1530 - - phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892 - delay 1532 - -3. Modify configs/default.cfg as shown below to run PTP primary on -Fronthaul of O-RU:: + phc2sys[3904510.892]: CLOCK_REALTIME phc offset 343 s0 freq -38967 delay 1530 + phc2sys[3904511.017]: CLOCK_REALTIME phc offset 368 s2 freq -38767 delay 1537 + phc2sys[3904511.142]: CLOCK_REALTIME phc offset 339 s2 freq -38428 delay 1534 + phc2sys[3904511.267]: CLOCK_REALTIME phc offset 298 s2 freq -38368 delay 1532 + phc2sys[3904511.392]: CLOCK_REALTIME phc offset 239 s2 freq -38337 delay 1534 + phc2sys[3904511.518]: CLOCK_REALTIME phc offset 145 s2 freq -38360 delay 1530 + phc2sys[3904511.643]: CLOCK_REALTIME phc offset 106 s2 freq -38355 delay 1527 + phc2sys[3904511.768]: CLOCK_REALTIME phc offset -30 s2 freq -38459 delay 1534 + phc2sys[3904511.893]: CLOCK_REALTIME phc offset -92 s2 freq -38530 delay 1530 + phc2sys[3904512.018]: CLOCK_REALTIME phc offset -173 s2 freq -38639 delay 1528 + phc2sys[3904512.143]: CLOCK_REALTIME phc offset -246 s2 freq -38764 delay 1530 + phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892 delay 1532 + +5. Modify configs/default.cfg as shown below to run PTP master on Fronthaul of O-RU. :: diff --git a/configs/default.cfg b/configs/default.cfg - old mode 100644 - new mode 100755 - index e23dfd7..c9e9d4c - --- a/configs/default.cfg - +++ b/configs/default.cfg - @@ -15,14 +15,14 @@ free_running 0 - freq_est_interval 1 - dscp_event 0 - dscp_general 0 - -dataset_comparison ieee1588 - +dataset_comparison G.8275.x - G.8275.defaultDS.localPriority 128 - maxStepsRemoved 255 - # - # Port Data Set - # - logAnnounceInterval 1 - -logSyncInterval 0 - +logSyncInterval -4 - operLogSyncInterval 0 - logMinDelayReqInterval 0 - logMinPdelayReqInterval 0 - @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128 - asCapable auto - BMCA ptp - inhibit_announce 0 - -inhibit_pdelay_req 0 - +#inhibit_pdelay_req 0 - ignore_source_id 0 - # - # Run time options -4.Start PTP primary toward O-DU:: +6. Start PTP master toward O-DU:: ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 –m Example of output:: ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 -m - ptp4l[3903857.249]: selected /dev/ptp3 as PTP clock - ptp4l[3903857.266]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE - ptp4l[3903857.267]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE + ptp4l[3903863.734]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES + ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best master + ptp4l[3903863.734]: assuming the grand master role - ptp4l[3903863.734]: port 1: LISTENING to MASTER on - ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES - - ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best - primary - - ptp4l[3903863.734]: assuming the main reference role - -5.Synchronize local NIC PTP primary clock to local NIC PTP secondary clock:: +7. Synchronize local NIC PTP master clock to local NIC PTP slave clock. :: ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8 Example of output:: ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8 - - phc2sys[3904600.332]: enp175s0f1 phc offset 2042 s0 freq -2445 delay - 4525 - - phc2sys[3904600.458]: enp175s0f1 phc offset 2070 s2 freq -2223 delay - 4506 - + phc2sys[3904600.332]: enp175s0f1 phc offset 2042 s0 freq -2445 delay 4525 + phc2sys[3904600.458]: enp175s0f1 phc offset 2070 s2 freq -2223 delay 4506 phc2sys[3904600.584]: enp175s0f1 phc offset 2125 s2 freq -98 delay 4505 - phc2sys[3904600.710]: enp175s0f1 phc offset 1847 s2 freq +262 delay 4518 - phc2sys[3904600.836]: enp175s0f1 phc offset 1500 s2 freq +469 delay 4515 - phc2sys[3904600.961]: enp175s0f1 phc offset 1146 s2 freq +565 delay 4547 - phc2sys[3904601.086]: enp175s0f1 phc offset 877 s2 freq +640 delay 4542 - phc2sys[3904601.212]: enp175s0f1 phc offset 517 s2 freq +543 delay 4517 - phc2sys[3904601.337]: enp175s0f1 phc offset 189 s2 freq +370 delay 4510 - phc2sys[3904601.462]: enp175s0f1 phc offset -125 s2 freq +113 delay 4554 - phc2sys[3904601.587]: enp175s0f1 phc offset -412 s2 freq -212 delay 4513 - phc2sys[3904601.712]: enp175s0f1 phc offset -693 s2 freq -617 delay 4519 - - phc2sys[3904601.837]: enp175s0f1 phc offset -878 s2 freq -1009 delay - 4515 - - phc2sys[3904601.962]: enp175s0f1 phc offset -965 s2 freq -1360 delay - 4518 - - phc2sys[3904602.088]: enp175s0f1 phc offset -1048 s2 freq -1732 delay - 4510 - - phc2sys[3904602.213]: enp175s0f1 phc offset -1087 s2 freq -2086 delay - 4531 - - phc2sys[3904602.338]: enp175s0f1 phc offset -1014 s2 freq -2339 delay - 4528 - - phc2sys[3904602.463]: enp175s0f1 phc offset -1009 s2 freq -2638 delay - 4531 - -6. On O-DU Install PTP for Linux tools from source code the same way as + phc2sys[3904601.837]: enp175s0f1 phc offset -878 s2 freq -1009 delay 4515 + phc2sys[3904601.962]: enp175s0f1 phc offset -965 s2 freq -1360 delay 4518 + phc2sys[3904602.088]: enp175s0f1 phc offset -1048 s2 freq -1732 delay 4510 + phc2sys[3904602.213]: enp175s0f1 phc offset -1087 s2 freq -2086 delay 4531 + phc2sys[3904602.338]: enp175s0f1 phc offset -1014 s2 freq -2339 delay 4528 + phc2sys[3904602.463]: enp175s0f1 phc offset -1009 s2 freq -2638 delay 4531 + +8. On O-DU Install PTP for Linux tools from source code the same way as on O-RU above but no need to apply the patch for msg.c -7. Start secondary port toward PTP primary from O-RU using the same +9. Start slave port toward PTP master from O-RU using the same default_slave.cfg as on O-RU (see above):: ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 –m @@ -598,133 +375,59 @@ default_slave.cfg as on O-RU (see above):: Example of output:: ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 -m - ptp4l[809092.918]: selected /dev/ptp6 as PTP clock - ptp4l[809092.934]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE - ptp4l[809092.934]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE - - ptp4l[809092.949]: port 1: new foreign primary 3cfdfe.fffe.bd005d-1 - - ptp4l[809096.949]: selected best primary clock 3cfdfe.fffe.bd005d - + ptp4l[809092.949]: port 1: new foreign master 3cfdfe.fffe.bd005d-1 + ptp4l[809096.949]: selected best master clock 3cfdfe.fffe.bd005d ptp4l[809096.950]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE - - ptp4l[809098.363]: port 1: UNCALIBRATED to SLAVE on - MASTER_CLOCK_SELECTED - - ptp4l[809099.051]: rms 38643 max 77557 freq +719 +/- 1326 delay 1905 +/- - 0 - + ptp4l[809098.363]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED + ptp4l[809099.051]: rms 38643 max 77557 freq +719 +/- 1326 delay 1905 +/- 0 ptp4l[809100.051]: rms 1134 max 1935 freq -103 +/- 680 delay 1891 +/- 4 - ptp4l[809101.051]: rms 453 max 855 freq +341 +/- 642 delay 1888 +/- 0 - ptp4l[809102.052]: rms 491 max 772 freq +1120 +/- 752 delay 1702 +/- 0 - ptp4l[809103.052]: rms 423 max 654 freq +1352 +/- 653 delay 1888 +/- 0 - ptp4l[809104.052]: rms 412 max 579 freq +1001 +/- 672 delay 1702 +/- 0 - ptp4l[809105.053]: rms 441 max 672 freq +807 +/- 709 delay 1826 +/- 88 - ptp4l[809106.053]: rms 422 max 607 freq +1353 +/- 636 delay 1702 +/- 0 - ptp4l[809107.054]: rms 401 max 466 freq +946 +/- 646 delay 1702 +/- 0 - ptp4l[809108.055]: rms 401 max 502 freq +912 +/- 659 -8. Synchronize local clock on O-DU for sample application or l1 -application:: +10. Synchronize local clock on O-DU for sample application or l1 +Application. :: ./phc2sys -s enp181s0f0 -w -m -R 8 Example of output:: ./phc2sys -s enp181s0f0 -w -m -R 8 - - phc2sys[809127.123]: CLOCK_REALTIME phc offset 675 s0 freq -37379 delay - 1646 - - phc2sys[809127.249]: CLOCK_REALTIME phc offset 696 s2 freq -37212 delay - 1654 - - phc2sys[809127.374]: CLOCK_REALTIME phc offset 630 s2 freq -36582 delay - 1648 - - phc2sys[809127.500]: CLOCK_REALTIME phc offset 461 s2 freq -36562 delay - 1642 - - phc2sys[809127.625]: CLOCK_REALTIME phc offset 374 s2 freq -36510 delay - 1643 - - phc2sys[809127.751]: CLOCK_REALTIME phc offset 122 s2 freq -36650 delay - 1649 - - phc2sys[809127.876]: CLOCK_REALTIME phc offset 34 s2 freq -36702 delay - 1650 - - phc2sys[809128.002]: CLOCK_REALTIME phc offset -112 s2 freq -36837 delay - 1645 - - phc2sys[809128.127]: CLOCK_REALTIME phc offset -160 s2 freq -36919 delay - 1643 - - phc2sys[809128.252]: CLOCK_REALTIME phc offset -270 s2 freq -37077 delay - 1657 - - phc2sys[809128.378]: CLOCK_REALTIME phc offset -285 s2 freq -37173 delay - 1644 - - phc2sys[809128.503]: CLOCK_REALTIME phc offset -349 s2 freq -37322 delay - 1644 - - phc2sys[809128.629]: CLOCK_REALTIME phc offset -402 s2 freq -37480 delay - 1641 - - phc2sys[809128.754]: CLOCK_REALTIME phc offset -377 s2 freq -37576 delay - 1648 - - phc2sys[809128.879]: CLOCK_REALTIME phc offset -467 s2 freq -37779 delay - 1650 - - phc2sys[809129.005]: CLOCK_REALTIME phc offset -408 s2 freq -37860 delay - 1648 - - phc2sys[809129.130]: CLOCK_REALTIME phc offset -480 s2 freq -38054 delay - 1655 - - phc2sys[809129.256]: CLOCK_REALTIME phc offset -350 s2 freq -38068 delay - 1650 + phc2sys[809127.123]: CLOCK_REALTIME phc offset 675 s0 freq -37379 delay 1646 + phc2sys[809127.249]: CLOCK_REALTIME phc offset 696 s2 freq -37212 delay 1654 + phc2sys[809127.374]: CLOCK_REALTIME phc offset 630 s2 freq -36582 delay 1648 + phc2sys[809127.500]: CLOCK_REALTIME phc offset 461 s2 freq -36562 delay 1642 + phc2sys[809127.625]: CLOCK_REALTIME phc offset 374 s2 freq -36510 delay 1643 + phc2sys[809127.751]: CLOCK_REALTIME phc offset 122 s2 freq -36650 delay 1649 + phc2sys[809127.876]: CLOCK_REALTIME phc offset 34 s2 freq -36702 delay 1650 + phc2sys[809128.002]: CLOCK_REALTIME phc offset -112 s2 freq -36837 delay 1645 + phc2sys[809128.127]: CLOCK_REALTIME phc offset -160 s2 freq -36919 delay 1643 + phc2sys[809128.252]: CLOCK_REALTIME phc offset -270 s2 freq -37077 delay 1657 + phc2sys[809128.378]: CLOCK_REALTIME phc offset -285 s2 freq -37173 delay 1644 + phc2sys[809128.503]: CLOCK_REALTIME phc offset -349 s2 freq -37322 delay 1644 + phc2sys[809128.629]: CLOCK_REALTIME phc offset -402 s2 freq -37480 delay 1641 + phc2sys[809128.754]: CLOCK_REALTIME phc offset -377 s2 freq -37576 delay 1648 + phc2sys[809128.879]: CLOCK_REALTIME phc offset -467 s2 freq -37779 delay 1650 + phc2sys[809129.005]: CLOCK_REALTIME phc offset -408 s2 freq -37860 delay 1648 + phc2sys[809129.130]: CLOCK_REALTIME phc offset -480 s2 freq -38054 delay 1655 + phc2sys[809129.256]: CLOCK_REALTIME phc offset -350 s2 freq -38068 delay 1650 Support in xRAN Library ----------------------------- +======================= The xRAN library provides an API to check whether PTP for Linux is running correctly. There is a function called xran_is_synchronized(). It checks if ptp4l and phc2sys are running in the system by making PMC tool -requests for current port state and comparing it with the expected +requests for the current port state and comparing it with the expected value. This verification should be done before initialization. -*notes. “SECONDARY” is the only expected value in this release; only a -non-primary scenario is supported currently.* - -*notes1. Inclusive language terms were used except for the PTP traces where the source code has -not been updated to support the inclusive language terms yet.* - -.. |image0| image:: media/image3.png - :width: 2.52364in - :height: 3.77174in -.. |image1| image:: media/image8.png - :width: 6.258in - :height: 1.40538in -.. |image2| image:: media/image10.emf - :width: 6.18493in - :height: 0.53448in -.. |image3| image:: media/image15.png - :width: 6.27856in - :height: 2.672in -.. |image4| image:: media/image21.JPG - :width: 6.17708in - :height: 6.09375in +- “SLAVE” is the only expected value in this release; only a non-master scenario is supported currently. + diff --git a/docs/Sample-Application_fh.rst b/docs/Sample-Application_fh.rst index 3df722e..3b24a9f 100644 --- a/docs/Sample-Application_fh.rst +++ b/docs/Sample-Application_fh.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -12,9 +12,6 @@ .. See the License for the specific language governing permissions and .. limitations under the License. -.. |br| raw:: html - -
Sample Application ================== @@ -23,31 +20,29 @@ Sample Application :depth: 3 :local: -Figure 25 illustrates a sample xRAN application. +Figure 26 illustrates a sample xRAN application. .. image:: images/Sample-Application.jpg :width: 600 - :alt: Figure 25. Sample Application + :alt: Figure 26. Sample Application -Figure 25. Sample Application +Figure 26. Sample Application The sample application was created to execute test scenarios with -features of the xRAN library and test external API as well as timing. +features of the O-RAN library and test external API as well as timing. The sample application is named sample-app, and depending on configuration file settings can act as O-DU or simplified simulation of O-RU. The first O-DU should be run on the machine that acts as O-DU and the second as O-RU. Both machines are connected via ETH. The sample -application on both sides executes using a constant configuration |br| +application on both sides executes using a constant configuration according to settings in corresponding config files -(./app/usecase/mu0_10mhz/config_file_o_du.dat and |br| +(./app/usecase/mu0_10mhz/config_file_o_du.dat and ./app/usecase/mu0_10mhz/config_file_o_ru.dat) and uses binary files -(ant.bin) with IQ samples as input. Multiple-use |br| -cases for different +(ant.bin) with IQ samples as input. Multiple-use cases for different numerologies and different BW are available as examples. Configuration -files provide descriptions of each |br| -parameter and in general, those are -related to M-plane level settings as per the ORAN Fronthaul -specification. +files provide descriptions of each parameter, and in general, those are +related to M-plane level settings as per the O-RAN Fronthaul +specification, refer to *Table 2*. From the start of the process, the application (O-DU) sends DL packets for the U-plane and C-plane and receives U-plane UL packets. @@ -56,17 +51,17 @@ Synchronization of O-DU and O-RU sides is achieved via IEEE 1588. U-plane packets for UL and DL direction are constructed the same way except for the direction field. -The several default configurations used with the sample app for v20.02 -release are: +Examples of default configurations used with the sample application for +v21.03 release provided below: 1 Cell mmWave 100MHz TDD DDDS: - +------------------------------ - Numerology 3 (mmWave) - TTI period 125 µs -- 100 Mhz Bandwidth: 792 subcarriers (all 66 RB utilized at all times) +- 100 MHz Bandwidth: 792 subcarriers (all 66 RB utilized at all times) - 4x4 MIMO @@ -79,13 +74,13 @@ release are: - Front haul throughput ~11.5 Gbps. 12 Cells Sub6 10MHz FDD: - +------------------------ - Numerology 0 (Sub-6) - TTI period 1000 µs -- 10Mhz Bandwidth: 624 subcarriers (all 52 RB utilized at all times) +- 10 MHz Bandwidth: 624 subcarriers (all 52 RB utilized at all times) - 4x4 MIMO @@ -97,14 +92,14 @@ release are: - Front haul throughput ~13.7Gbps. -1 Cell Sub6 100MHz TDD: - +1 Cell Sub6 100 MHz TDD +----------------------- - Numerology 1 (Sub-6) -- TTI period 500us +- TTI period 500 µs -- 100Mhz Bandwidth: 3276 subcarriers (all 273RB utilized at all times) +- 100 MHz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times) - 4x4 MIMO @@ -116,17 +111,14 @@ release are: - Front haul throughput ~11.7 Gbps. -.. _cell-sub6-100mhz-tdd-1: - -1 Cell Sub6 100MHz TDD: - +1 Cell Sub6 100 MHz TDD (Category B): +------------------------------------- - Numerology 1 (Sub-6) - TTI period 500 µs -- 100 Mhz Bandwidth: 3276 subcarriers (all 273RB utilized at all - times). 8 UEs per TTI per layer +- 100 MHz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times). 8 UEs per TTI per layer - 8DL /4UL MIMO Layers @@ -138,8 +130,78 @@ release are: - Front haul throughput ~23.5 Gbps. -Other configurations can be constructed by modifying config files -(please see app/usecase/) +3 Cell Sub6 100MHz TDD Massive MIMO (Category B): +------------------------------------------------- + +- Numerology 1 (Sub-6) + +- TTI period 500 µs + +- 100 Mhz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times). 8 UEs per TTI per layer + +- 16DL /8UL MIMO Layers + +- Digital beamforming with 64T64R + +- 1 Component carrier for each Cell + +- Jumbo Frame for Ethernet (up to 9728 bytes) + +- Front haul throughput ~44 Gbps. + +Other configurations can be constructed by modifying the config files +(see app/usecase/) + +One_way Delay Measurements: +--------------------------- + +There are 4 usecases defined that are based on cat a, numerology 0 and +20 MHz Bw: + +Common to all cases the following parameters are needed in the +usecase_xu.cfg files where x=r for ORU and x=d for ODU. + +oXuOwdmNumSamps=8 # Run 8 samples per port + +oXuOwdmFltrType=0 # Simple average + +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns (Currently not +enforced) + +oXuOwdmMeasState=0 # Measurement state is INIT + +oXuOwdmMeasId=0 # Measurement Id seed + +oXuOwdmEnabled=1 # Measurements are enabled + +oXuOwdmPlLength= n # with 40 <= n <= 1400 bytes + +For the ORU + +oXuOwdmInitEn=0 #O-RU is always the recipient + +For the ODU + +oXuOwdmInitEn=1 #O-DU is always initiator + +20 Corresponds to the Request/Response usecase with Payload Size 40 +bytes + +oXuOwdmMeasMeth=0 # Measurement Method REQUEST + +21 Corresponds to the Remote Request usecase with Payload Size 512 bytes + +oXuOwdmMeasMeth=1 # Measurement Method REM_REQ + +22 Corresponds to the Request with Follow Up usecase with Payload Size +1024 bytes + +oXuOwdmMeasMeth=2 # Measurement Method REQUESTwFUP + +23 Corresponds to the Remote Request with Follow Up usecase with default +Payload Size +oXuOwdmMeasMeth=3 # Measurement Method REM_REQ_WFUP +- diff --git a/docs/Setup-Configuration_fh.rst b/docs/Setup-Configuration_fh.rst index 3a93e81..9e463a2 100644 --- a/docs/Setup-Configuration_fh.rst +++ b/docs/Setup-Configuration_fh.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -22,9 +22,9 @@ Setup Configuration A.1 Setup Configuration ----------------------- The configuration shown in Figure 26 shows how to set up a test -environment to execute xRAN scenarios where O-DU and 0-RU are simulated +environment to execute O-RAN scenarios where O-DU and 0-RU are simulated using the sample application. This setup allows development and -prototyping as well as testing of xRAN specific functionality. The O-DU +prototyping as well as testing of O-RAN specific functionality. The O-DU side can be instantiated with a full 5G NR L1 reference as well. The configuration differences of the 5G NR l1app configuration are provided below. Steps for running the sample application on the O-DU side and @@ -33,15 +33,15 @@ different. .. image:: images/Setup-for-xRAN-Testing.jpg :width: 400 - :alt: Figure 26. Setup for xRAN Testing + :alt: Figure 26. Setup for O-RAN Testing -Figure 26. Setup for xRAN Testing +Figure 26. Setup for O-RAN Testing .. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg :width: 400 - :alt: Figure 27. Setup for xRAN Testing with PHY and Configuration C3 + :alt: Figure 27. Setup for O-RAN Testing with PHY and Configuration C3 -Figure 27. Setup for xRAN Testing with PHY and Configuration C3 +Figure 27. Setup for O-RAN Testing with PHY and Configuration C3 A.2 Prerequisites ----------------- @@ -53,31 +53,40 @@ Each server in Figure 26 requires the following: - BIOS settings: -- Intel(R) Virtualization Technology Enabled + - Intel® Virtualization Technology Enabled -- Intel(R) VT for Directed I/O - Enabled + - Intel® VT for Directed I/O - Enabled -- ACS Control - Enabled + - ACS Control - Enabled -- Coherency Support - Disabled + - Coherency Support - Disabled - Front Haul networking cards: -- Intel® Ethernet Converged Network Adapter XL710-QDA2 + - Intel® Ethernet Converged Network Adapter XL710-QDA2 -- Intel® Ethernet Converged Network Adapter XXV710-DA2 + - Intel® Ethernet Converged Network Adapter XXV710-DA2 -- Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 + - Intel® Ethernet Converged Network Adapter E810-CQDA2 -**The Front Haul NIC requires support for PTP HW timestamping.** + - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000 -The recommended configuration for NICs is:: +- Back (Mid) Haul networking card can be either: + + - Intel® Ethernet Connection X722 for 10GBASE-T + + - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection + + - Other networking cards capable of HW timestamping for PTP synchronization. + + - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping. +The recommended configuration for NICs is:: ethtool -i enp33s0f0 driver: i40e - version: 2.10.19.82 - firmware-version: 7.20 0x80007949 1.2585.0 + version: 2.14.13 + firmware-version: 8.20 0x80009bd4 1.2879.0 expansion-rom-version: bus-info: 0000:21:00.0 supports-statistics: yes @@ -88,213 +97,205 @@ The recommended configuration for NICs is:: ethtool -T enp33s0f0 Time stamping parameters for enp33s0f0: Capabilities: - hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE) - software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE) - hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE) - software-receive (SOF_TIMESTAMPING_RX_SOFTWARE) + hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE) + software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE) + hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE) + software-receive (SOF_TIMESTAMPING_RX_SOFTWARE) software-system-clock (SOF_TIMESTAMPING_SOFTWARE) - hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE) + hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE) PTP Hardware Clock: 4 Hardware Transmit Timestamp Modes: - off (HWTSTAMP_TX_OFF) - on (HWTSTAMP_TX_ON) + off (HWTSTAMP_TX_OFF) + on (HWTSTAMP_TX_ON) Hardware Receive Filter Modes: - none (HWTSTAMP_FILTER_NONE) - ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC) - ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) - ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT) - ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC) - ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) - ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT) - ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC) - ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) - ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT) - ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC) - ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) - - -A PTP Main Reference Clock is required to be available in the network to provide + none (HWTSTAMP_FILTER_NONE) + ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC) + ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) + ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT) + ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC) + ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) + ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT) + ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC) + ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) + ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT) + ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC) + ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) + +The recommended configuration for Columbiaville NICs (base on Intel® +Ethernet 800 Series (Columbiaville) CVL 2.3 release is:: + + ethtool -i enp81s0f0 + driver: ice + version: 1.3.2 + firmware-version: 2.3 0x80005D18 + expansion-rom-version: + bus-info: 0000:51:00.0 + supports-statistics: yes + supports-test: yes + supports-eeprom-access: yes + supports-register-dump: yes + supports-priv-flags: yes + ethtool -T enp81s0f0 + Time stamping parameters for enp81s0f0: + Capabilities: + hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE) + software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE) + hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE) + software-receive (SOF_TIMESTAMPING_RX_SOFTWARE) + software-system-clock (SOF_TIMESTAMPING_SOFTWARE) + hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE) + PTP Hardware Clock: 1 + Hardware Transmit Timestamp Modes: + off (HWTSTAMP_TX_OFF) + on (HWTSTAMP_TX_ON) + Hardware Receive Filter Modes: + none (HWTSTAMP_FILTER_NONE) + all (HWTSTAMP_FILTER_ALL) + + Recommended version of + iavf driver 4.0.2 + ICE COMMS Package version 1.3.24.0 + +*Note*. If your firmware version does not match with the ones in the output +images, you can download the correct version from the Intel Download +Center. It is Intel's repository for the latest software and drivers +for Intel products. The NVM Update Packages for Windows*, Linux*, +ESX*, FreeBSD*, and EFI/EFI2 are located at: + +.. + +https://downloadcenter.intel.com/download/24769 (700 series) + +https://downloadcenter.intel.com/download/29736 (E810 series) + +PTP Grand Master is required to be available in the network to provide synchronization of both O-DU and RU to GPS time. -1.Installing Intel® C++ Compiler v19.0.3 is preferred. or you could get -Intel® C++ Compiler through below link with community license, -however the version you could get is always latest version, the -verification for that version might not be performed yet, please -feedback through O-DU Low project WIKI page if you meet an issue. |br| -`https://software.intel.com/en-us/system-studio/choose-download `__ - -2.Download DPDK 19.11. - -3.Change DPDK files according to below diff information which relevant to O-RAN FH:: - - diff --git a/drivers/net/i40e/i40e_ethdev.c - b/drivers/net/i40e/i40e_ethdev.c - - index 85a6a86..236fbe0 100644 - - --- a/drivers/net/i40e/i40e_ethdev.c - - +++ b/drivers/net/i40e/i40e_ethdev.c - - @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct - i40e_hw \*hw) - - /\* Map queues with MSIX interrupt \*/ - - main_vsi->nb_used_qps = dev->data->nb_rx_queues - - - pf->nb_cfg_vmdq_vsi \* RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; - - - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); - - + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE); - - i40e_vsi_enable_queues_intr(main_vsi); - - /\* Map VMDQ VSI queues with MSIX interrupt \*/ - - @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct - i40e_hw \*hw) - - i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); - - } - - + i40e_aq_debug_write_global_register(hw, - - + 0x0012A504, - - + 0, NULL); - - + - - /\* enable FDIR MSIX interrupt \*/ - - if (pf->fdir.fdir_vsi) { - - i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, - - diff --git a/drivers/net/i40e/i40e_ethdev_vf.c - b/drivers/net/i40e/i40e_ethdev_vf.c - - index 001c301..6f9ffdb 100644 - - --- a/drivers/net/i40e/i40e_ethdev_vf.c - - +++ b/drivers/net/i40e/i40e_ethdev_vf.c - - @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off { - - map_info = (struct virtchnl_irq_map_info \*)cmd_buffer; - - map_info->num_vectors = 1; - - - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT; - - + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE; - - map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id; - - /\* Alway use default dynamic MSIX interrupt \*/ - - map_info->vecmap[0].vector_id = vector_id; - - diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c - b/drivers/net/ixgbe/ixgbe_ethdev.c - - index 26b1927..018eb8f 100644 - - --- a/drivers/net/ixgbe/ixgbe_ethdev.c - - +++ b/drivers/net/ixgbe/ixgbe_ethdev.c - - @@ -3705,7 +3705,7 @@ static int - ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev \*dev, - - \* except for 82598EB, which remains constant. - - \*/ - - if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && - - - hw->mac.type != ixgbe_mac_82598EB) - - + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != - ixgbe_mac_82599EB) - - dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; - - } - - dev_info->min_rx_bufsize = 1024; /\* cf BSIZEPACKET in SRRCTL register - \*/ - - diff --git a/lib/librte_eal/common/include/rte_dev.h - b/lib/librte_eal/common/include/rte_dev.h - - old mode 100644 - - new mode 100755 +The software package includes Linux\* CentOS\* operating system and RT +patch according to FlexRAN Reference Solution Cloud-Native Setup +document (refer to Table 2). Only real-time HOST is required. + +1. Install Intel® C++ Compiler v19.0.3 + +2. Download DPDK v20.11 + +3. Patch DPDK with FlexRAN BBDev patch as per given release. + +4. Double check that FlexRAN DPDK patch includes changes below relevant +to O-RAN Front haul:: + + For Fortville: + diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c + index 85a6a86..236fbe0 100644 + --- a/drivers/net/i40e/i40e_ethdev.c + +++ b/drivers/net/i40e/i40e_ethdev.c + @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) + /* Map queues with MSIX interrupt */ + main_vsi->nb_used_qps = dev->data->nb_rx_queues - + pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM; + - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT); + + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE); + i40e_vsi_enable_queues_intr(main_vsi); + + /* Map VMDQ VSI queues with MSIX interrupt */ + @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw) + i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi); + } + + i40e_aq_debug_write_global_register(hw, + + 0x0012A504, + + 0, NULL); + + + /* enable FDIR MSIX interrupt */ + if (pf->fdir.fdir_vsi) { + i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi, + diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c + index 001c301..6f9ffdb 100644 + --- a/drivers/net/i40e/i40e_ethdev_vf.c + +++ b/drivers/net/i40e/i40e_ethdev_vf.c + @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off { + + map_info = (struct virtchnl_irq_map_info *)cmd_buffer; + map_info->num_vectors = 1; + - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT; + + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE; + map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id; + /* Alway use default dynamic MSIX interrupt */ + map_info->vecmap[0].vector_id = vector_id; + diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c + index 26b1927..018eb8f 100644 + --- a/drivers/net/ixgbe/ixgbe_ethdev.c + +++ b/drivers/net/ixgbe/ixgbe_ethdev.c + @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, + * except for 82598EB, which remains constant. + */ + if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && + - hw->mac.type != ixgbe_mac_82598EB) + + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB) + dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; + } + dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ + diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h + old mode 100644 + new mode 100755 + + for Columbiaville + diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c + index de189daba..d9aff341c 100644 + --- a/drivers/net/ice/ice_ethdev.c + +++ b/drivers/net/ice/ice_ethdev.c + @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect, + + PMD_DRV_LOG(INFO, "queue %d is binding to vect %d", + base_queue + i, msix_vect); + - /* set ITR0 value */ + - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10); + + /* set ITR0 value + + * Empirical configuration for optimal real time latency + + * reduced interrupt throttling to 2 ms + + * Columbiaville pre-PRQ : local patch subject to change + + */ + + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1); + + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M); + ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val); + ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx); + } 5.Build and install DPDK:: - [root@xran dpdk]# ./usertools/dpdk-setup.sh - - select [39] x86_64-native-linuxapp-icc - - select [46] Insert VFIO module - - exit [62] Exit Script + See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html 6.Make below file changes in dpdk that assure i40e to get best latency of packet processing:: - --- i40e.h 2018-11-30 11:27:00.000000000 +0000 - - +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000 - - @@ -451,7 +451,7 @@ - - #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \\ - - (I40E_QINT_RQCTL_CAUSE_ENA_MASK \| \\ - - - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) \| \\ - - + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) \| \\ - - ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) \| \\ - - ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) \| \\ - - (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) - - --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000 - - +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000 - - @@ -15296,6 +15296,9 @@ - - pf->hw_features \|= I40E_HW_HAVE_CRT_RETIMER; - - /\* print a string summarizing features \*/ - - i40e_print_features(pf); - - + - - + /\* write to this register to clear rx descriptor \*/ - - + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL); - - return 0; - + --- i40e.h 2018-11-30 11:27:00.000000000 +0000 + +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000 + @@ -451,7 +451,7 @@ + + #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \ + (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \ + - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ + + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \ + ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \ + ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \ + (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)) + + --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000 + +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000 + @@ -15296,6 +15296,9 @@ + pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER; + /* print a string summarizing features */ + i40e_print_features(pf); + + + + /* write to this register to clear rx descriptor */ + + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL); + + return 0; + A.3 Configuration of System --------------------------- 1.Boot Linux with the following arguments:: cat /proc/cmdline - BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0 @@ -302,174 +303,253 @@ A.3 Configuration of System hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20 nohz_full=1-19,21-39 - -2.Download from Intel Website and install updated version of i40e -driver if needed. The current recommended version of i40e is 2.10.19.82. -However, any latest version of i40e after x2.9.21 expected to be functional for ORAN FH. -3.Identify PCIe Bus address of the Front Haul NIC:: +2. Boot Linux with the following arguments for Icelake CPU:: + + cat /proc/cmdline + BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64 + root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root + rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1 + selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0 + intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G + hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G + isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0 + nohz_full=1-23,25-47 + +3. Download from Intel Website and install updated version of i40e +driver if needed. The current recommended version of i40e is 2.14.13. +However, any latest version of i40e after 2.9.21 expected to be +functional for O-RAN FH. + +4. For Columbiaville download Intel® Ethernet 800 Series (Columbiaville) +CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer +Content Library. The current recommended version of ICE driver is +1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended +version 4.0.2 + +5. Identify PCIe Bus address of the Front Haul NIC (Fortville):: + + lspci|grep Eth + 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + +6. Identify PCIe Bus address of the Front Haul NIC (Columbiaville):: - lspci |grep Eth - 19:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02) - 19:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02) - 1d:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02) - 1d:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02) - 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) - 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) - 67:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722 for 10GBASE-T (rev 09) + lspci \|grep Eth + 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02) + 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02) - -4.Identify the Ethernet device name:: +7. Identify the Ethernet device name:: ethtool -i enp33s0f0 driver: i40e - version: 2.10.19.82 - firmware-version: 7.20 0x80007949 1.2585.0 + version: 2.14.13 + firmware-version: 8.20 0x80009bd4 1.2879.0 expansion-rom-version: bus-info: 0000:21:00.0 supports-statistics: yes supports-test: yes supports-eeprom-access: yes supports-register-dump: yes - supports-priv-flags: yes - Enable + supports-priv-flags: yesEnable + +or :: + + ethtool -i enp81s0f0 + driver: ice + version: 1.3.2 + firmware-version: 2.3 0x80005D18 + expansion-rom-version: + bus-info: 0000:51:00.0 + supports-statistics: yes + supports-test: yes + supports-eeprom-access: yes + supports-register-dump: yes + supports-priv-flags: yes + +8. Enable 3 virtual functions (VFs) on the each of two ports of each +NIC:: + + #!/bin/bash + + echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs + echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs + + echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs + echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs + + modprobe -r iavf + modprobe iavf + + echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs + echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs + + echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs + echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs + + a=8 + + if [ -z "$1" ] + then + b=0 + elif [ $1 -lt $a ] + then + b=$1 + else + echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided" + exit 1 + fi + + #O-DU + ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b + ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b + + ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b + ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b + + ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b + ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b + + #O-RU + ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b + ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b + + ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b + ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b + + ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b + ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b + +where output is next:: + + ip link show + ... + 9: enp134s0f0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 + link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff + vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off + vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off + vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off + 11: enp134s0f1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 + link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff + vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off + vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off + vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off + 12: enp136s0f0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 + link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff + vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off + vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off + vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off + 14: enp136s0f1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 + link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff + vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off + vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off + vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off + ... -5.Enable two virtual functions (VF) on the device:: - echo 2 > /sys/class/net/enp33s0f0/device/sriov_numvfs More information about VFs supported by Intel NICs can be found at https://doc.dpdk.org/guides/nics/intel_vf.html. -The resulting configuration can look like the listing below, where two -new VFs were added:: +The resulting configuration can look like the listing below, where six +new VFs were added for each O-DU and O-RU port::: lspci|grep Eth - - 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) - 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) - 21:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) - 21:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) - - -6.Configure MAC address and VLAN settings for VFs for XRAN, based on -requirements for xRAN scenario and assignment of VLAN ID using IP -tool perform configuration of VF. - - Example where O-DU and O-RU simulation run on the same sytem:: - - #!/bin/bash - - echo 2 > /sys/bus/pci/devices/0000\:21\:00.0/sriov_numvfs - ip link set enp33s0f0 vf 1 mac 00:11:22:33:44:66 vlan 1 - ip link set enp33s0f0 vf 0 mac 00:11:22:33:44:66 vlan 2 - echo 2 > /sys/bus/pci/devices/0000\:21\:00.1/sriov_numvfs - ip link set enp33s0f1 vf 1 mac 00:11:22:33:44:55 vlan 1 - ip link set enp33s0f1 vf 0 mac 00:11:22:33:44:55 vlan 2 - - where output is next:: - - [root@xran app]# ip link show - - 1: lo: mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 - - link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 - - 2: enp25s0f0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 64:4c:36:10:1f:30 brd ff:ff:ff:ff:ff:ff - - 3: enp25s0f1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 64:4c:36:10:1f:31 brd ff:ff:ff:ff:ff:ff - - 4: enp29s0f0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 64:4c:36:10:1f:34 brd ff:ff:ff:ff:ff:ff - - 5: enp29s0f1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 64:4c:36:10:1f:35 brd ff:ff:ff:ff:ff:ff - - 6: enp33s0f0: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff - - vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto, trust off - - vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto, trust off - - 7: enp33s0f1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff - - vf 0 MAC 00:11:22:33:44:55, vlan 2, spoof checking on, link-state auto, trust off - - vf 1 MAC 00:11:22:33:44:55, vlan 1, spoof checking on, link-state auto, trust off - - 8: eno1: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether a4:bf:01:3e:1f:be brd ff:ff:ff:ff:ff:ff - - 9: eno2: mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000 - - link/ether a4:bf:01:3e:1f:bf brd ff:ff:ff:ff:ff:ff - - 10: npacf0g0l0: mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000 - - link/generic - - 11: npacf0g0l1: mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000 - - link/generic - - 12: npacf0g0l2: mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000 - - link/generic - - 13: npacf0g0l3: mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000 - - link/generic - -After this step FH NIC is configured. - -O-DU - -VF for C-plane is VF1 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is 21d8:02.1 - -VF for U-plane is VF0 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is 21d8:02.0 - -O-RU - -VF for C-plane is VF1 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 1. PCIe Bus address is VF1 is 21:0a.1 - -VF for U-plane is VF0 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 2. PCIe Bus address is VF1 is 21:0a.0 - - -A.4 Install and Configure Sample Application --------------------------------------------- + 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02) + 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) + +9. Example where O-DU and O-RU simulation run on the same system: + +O-DU::: + + cat ./run_o_du.sh + #! /bin/bash + + ulimit -c unlimited + echo 1 > /proc/sys/kernel/core_uses_pid + + ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \ + --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \ + --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \ + --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2" + + +O-RU:: + + cat ./run_o_ru.sh + #! /bin/bash + ulimit -c unlimited + echo 1 > /proc/sys/kernel/core_uses_pid + + ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \ + --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \ + --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \ + --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2" + + +Install and Configure Sample Application +======================================== + To install and configure the sample application: -1. Set up the environment: +1. Set up the environment:: + + For Skylake and Cascadelake + export GTEST_ROOT=pwd/gtest-1.7.0 + export RTE_SDK=pwd/dpdk-20.11 + export RTE_TARGET=x86_64-native-linuxapp-icc + export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk + export WIRELESS_SDK_TARGET_ISA=avx512 + export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc + export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD} + export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog + export XRAN_DIR=pwd/flexran_xran - export GTEST_ROOT=`pwd`/gtest-1.7.0 - - export RTE_SDK=`pwd`/dpdk-19.11 - - export RTE_TARGET=x86_64-native-linuxapp-icc - - export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog - - export XRAN_DIR=`pwd`/flexran_xran + for Icelake + export GTEST_ROOT=pwd/gtest-1.7.0 + export RTE_SDK=pwd/dpdk-20.11 + export RTE_TARGET=x86_64-native-linuxapp-icc + export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk + export WIRELESS_SDK_TARGET_ISA=snc + export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc + export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD} + export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog + export XRAN_DIR=pwd/flexran_xran -2. Compile xRAN library and test the application: +2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library:: - [turner@xran home]$ cd $XRAN_DIR - - [turner@xran xran]$ ./build.sh - -3. Configure the sample app. + [turner@xran home]$ cd $MLOG_DIR + [turner@xran xran]$ ./build.sh + +3. Compile O-RAN library and test the application:: + + [turner@xran home]$ cd $XRAN_DIR + [turner@xran xran]$ ./build.sh + +4. Configure the sample app. IQ samples can be generated using Octave\* and script libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64 @@ -481,15 +561,3161 @@ example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms = 3548160 bytes per antenna. Refer to comments in gen_test.m to correctly specify the configuration for IQ test vector generation. +Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration +for your scenario. + Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable configuration for your scenario. Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1 -used for U-plane and C-plane correspondingly:: - - ./build/sample-app -c ./usecase/mu0_10mhz/config_file_o_du.dat -p 2 0000:21d8:02.0 0000:21d8:02.1 - -4. Run application using run_o_du.sh (run_o_ru.sh). - - - +used for U-plane and C-plane correspondingly. + +5. Run the application using run_o_du.sh (run_o_ru.sh). + +Install and Configure FlexRAN 5G NR L1 Application +================================================== + +The 5G NR layer 1 application can be used for executing the scenario for +mmWave with either the RU sample application or just the O-DU side. The +current release supports the constant configuration of the slot pattern +and RB allocation on the PHY side. The build process follows the same +basic steps as for the sample application above and is similar to +compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the +general build process in the FlexRAN 5G NR Reference Solution L1 User +Guide (refer to *Table 2*.) + +1. O-RAN library is enabled by default l1 application: + +2. Build the 5G NR L1 application using the command:: + + ./flexran_build.sh -r 5gnr_mmw -i avx512 -m sdk -m fb -m mlog –m wls -m + 5gnr_l1app_mmw -m xran -m 5gnr_testmac + +3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and +xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). :: + + + 20.08 + + 1 + + 25 + + 1 + + + 0000:51:01.0 + 0000:51:01.1 + 0000:51:01.2 + 0000:51:01.3 + + + 0000:51:01.4 + 0000:51:01.5 + 0000:51:01.6 + 0000:51:01.7 + + + 0000:51:02.0 + 0000:51:02.1 + 0000:51:02.2 + 0000:51:02.3 + + + 0000:00:00.0 + 0000:00:00.0 + 0000:00:00.0 + 0000:00:00.0 + + + 00:11:22:33:00:01 + 00:11:22:33:00:11 + + 00:11:22:33:00:21 + 00:11:22:33:00:31 + + + 00:11:22:33:01:01 + 00:11:22:33:01:11 + + 00:11:22:33:01:21 + 00:11:22:33:01:31 + + + 00:11:22:33:02:01 + 00:11:22:33:02:11 + + 00:11:22:33:02:21 + 00:11:22:33:02:31 + + + 00:11:22:33:03:01 + 00:11:22:33:03:11 + + 00:11:22:33:03:21 + 00:11:22:33:03:31 + + + 1 + + 0 + + 1 + + 2 + + 3 + + 4 + + 5 + + 6 + + 7 + + 8 + + 9 + + 10 + + 11 + + + 1 + + 1 + + 1 + + 2 + + 3 + + + 1 + + 2 + + 1 + + 2 + + 3 + + + 19, 96, 0 + + + 0x0, 96, 0 + + 0 + + + 0 + + + + 25 + + 50 + 140 + + 50 + 140 + + 25 + 140 + + 20 + 32 + + + + 9600 + + 1 + 2 + + + 70 + 100 + + 60 + 70 + + 35 + 50 + + 0 + 45 + + + 1 + + 0 + + 0 + 0 + + 0 + + 0 + + 0 + + 0 + + + 0 + + 1 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 96,48,0,14,3,1,1,9,1,0,0 + 144,48,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + 1 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 72,36,0,14,3,1,1,9,1,0,0 + 108,36,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + +4. Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). :: + + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1 + +5. Use configuration of test mac per:: + + /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg + phystart 4 0 40200 + + TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg + + +6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter:: + + [root@xran flexran] cd ./bin/nr5g/gnb/l1 + [root@xran l1]#./l1.sh –xran + +where output corresponding L1 is:: + + [root@sc12-xran-sub6 l1]# ./l1.sh -xranmmw + Radio mode with XRAN - mmWave 100Mhz + DPDK WLS MODE + kernel.sched_rt_runtime_us = -1 + kernel.shmmax = 2147483648 + kernel.shmall = 2147483648 + Note: Forwarding request to 'systemctl disable irqbalance.service'. + using configuration file phycfg_xran_mmw.xml + >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran_mmw.xml + FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY# + FlexRAN SDK bblib_layermapping_5gnr version #DIRTY# + FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY# + FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_llr_demapping version #DIRTY# + FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY# + FlexRAN SDK bblib_reed_muller version #DIRTY# + FlexRAN SDK bblib_lte_modulation version #DIRTY# + FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY# + FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY# + FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY# + FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY# + FlexRAN SDK bblib_fd_correlation version #DIRTY# + FlexRAN SDK bblib_scramble_5gnr version #DIRTY# + FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY# + FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY# + FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY# + FlexRAN SDK bblib_prach_5gnr version #DIRTY# + FlexRAN SDK bblib_fft_ifft version #DIRTY# + FlexRAN SDK bblib_pucch_5gnr version #DIRTY# + FlexRAN SDK bblib_common version #DIRTY# + FlexRAN SDK bblib_lte_crc version #DIRTY# + FlexRAN SDK bblib_lte_dft_idft version #DIRTY# + FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY# + FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY# + FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_zf_matrix_gen version #DIRTY# + FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY# + ========================= + 5GNR PHY Application + ========================= + --------------------------- + PhyCfg.xml Version: 20.04 + --------------------------- + --version=20.04 + --successiveNoApi=15 + --wls_dev_name=wls0 + --wlsMemorySize=0x3F600000 + --dlIqLog=0 + --ulIqLog=0 + --iqLogDumpToFile=0x0 + --phyMlog=1 + --phyStats=1 + --dpdkMemorySize=8192 + --dpdkIovaMode=0 + --dpdkBasebandFecMode=1 + --dpdkBasebandDevice=0000:1f:00.1 + --radioEnable=4 + --ferryBridgeMode=1 + --ferryBridgeEthPort=1 + --ferryBridgeSyncPorts=0 + --ferryBridgeOptCableLoopback=0 + --radioCfg0PCIeEthDev=0000:19:00.0 + --radioCfg0DpdkRx=1 + --radioCfg0DpdkTx=2 + --radioCfg0TxAnt=2 + --radioCfg0RxAnt=2 + --radioCfg0RxAgc=0 + --radioCfg0NumCell=1 + --radioCfg0Cell0PhyId=0 + --radioCfg0Cell1PhyId=1 + --radioCfg0Cell2PhyId=2 + --radioCfg0Cell3PhyId=3 + --radioCfg0Cell4PhyId=4 + --radioCfg0Cell5PhyId=5 + --radioCfg0riuMac=11:22:33:44:55:66 + --radioCfg1PCIeEthDev=0000:03:00.1 + --radioCfg1DpdkRx=1 + --radioCfg1DpdkTx=1 + --radioCfg1TxAnt=4 + --radioCfg1RxAnt=4 + --radioCfg1RxAgc=0 + --radioCfg1NumCell=1 + --radioCfg1Cell0PhyId=2 + --radioCfg1Cell1PhyId=3 + --radioCfg1Cell2PhyId=2 + --radioCfg1Cell3PhyId=3 + --radioCfg1riuMac=ac:1f:6b:2c:9f:07 + --radioCfg2PCIeEthDev=0000:05:00.0 + --radioCfg2DpdkRx=10 + --radioCfg2DpdkTx=11 + --radioCfg2TxAnt=4 + --radioCfg2RxAnt=4 + --radioCfg2RxAgc=0 + --radioCfg2NumCell=2 + --radioCfg2Cell0PhyId=4 + --radioCfg2Cell1PhyId=5 + --radioCfg2Cell2PhyId=2 + --radioCfg2Cell3PhyId=3 + --radioCfg2riuMac=ac:1f:6b:2c:9f:07 + --radioCfg3PCIeEthDev=0000:05:00.1 + --radioCfg3DpdkRx=12 + --radioCfg3DpdkTx=13 + --radioCfg3TxAnt=4 + --radioCfg3RxAnt=4 + --radioCfg3RxAgc=0 + --radioCfg3NumCell=2 + --radioCfg3Cell0PhyId=6 + --radioCfg3Cell1PhyId=7 + --radioCfg3Cell2PhyId=2 + --radioCfg3Cell3PhyId=3 + --radioCfg3riuMac=ac:1f:6b:2c:9f:07 + --radioCfg4PCIeEthDev=0000:00:08.0 + --radioCfg4DpdkRx=14 + --radioCfg4DpdkTx=15 + --radioCfg4TxAnt=4 + --radioCfg4RxAnt=4 + --radioCfg4RxAgc=0 + --radioCfg4NumCell=2 + --radioCfg4Cell0PhyId=8 + --radioCfg4Cell1PhyId=9 + --radioCfg4Cell2PhyId=2 + --radioCfg4Cell3PhyId=3 + --radioCfg4riuMac=ac:1f:6b:2c:9f:07 + --radioCfg5PCIeEthDev=0000:08:00.0 + --radioCfg5DpdkRx=16 + --radioCfg5DpdkTx=16 + --radioCfg5TxAnt=4 + --radioCfg5RxAnt=4 + --radioCfg5RxAgc=0 + --radioCfg5NumCell=2 + --radioCfg5Cell0PhyId=10 + --radioCfg5Cell1PhyId=11 + --radioCfg5Cell2PhyId=2 + --radioCfg5Cell3PhyId=3 + --radioCfg5riuMac=ac:1f:6b:2c:9f:07 + --radioCfg6PCIeEthDev=0000:00:05.0 + --radioCfg6DpdkRx=16 + --radioCfg6DpdkTx=16 + --radioCfg6TxAnt=4 + --radioCfg6RxAnt=4 + --radioCfg1RxAgc=0 + --radioCfg6NumCell=2 + --radioCfg6Cell0PhyId=12 + --radioCfg6Cell1PhyId=13 + --radioCfg6Cell2PhyId=2 + --radioCfg6Cell3PhyId=3 + --radioCfg6riuMac=ac:1f:6b:2c:9f:07 + --radioCfg7PCIeEthDev=0000:00:06.0 + --radioCfg7DpdkRx=16 + --radioCfg7DpdkTx=16 + --radioCfg7TxAnt=4 + --radioCfg7RxAnt=4 + --radioCfg7RxAgc=0 + --radioCfg7NumCell=2 + --radioCfg7Cell0PhyId=14 + --radioCfg7Cell1PhyId=15 + --radioCfg7Cell2PhyId=2 + --radioCfg7Cell3PhyId=3 + --radioCfg7riuMac=ac:1f:6b:2c:9f:07 + --radioPort0=0 + --radioPort1=1 + --radioPort2=2 + --radioPort3=3 + --radioPort4=4 + --radioPort5=5 + --radioPort6=6 + --radioPort7=7 + --PdschSymbolSplit=0 + --PdschDlWeightSplit=0 + --FecEncSplit=4 + --PuschChanEstSplit=0 + --PuschMmseSplit=0 + --PuschLlrRxSplit=0 + --PuschUlWeightSplit=0 + --FecDecEarlyTermDisable=0 + --FecDecNumIter=0 + --FecDecSplit=4 + --llrOutDecimalDigit=2 + --IrcEnableThreshold=-10 + --CEInterpMethod=0 + --PucchSplit=0 + --SrsCeSplit=0 + --prachDetectThreshold=10000 + --MlogSubframes=128 + --MlogCores=20 + --MlogSize=3084 + --systemThread=0, 0, 0 + --timerThread=0, 96, 0 + --xRANThread=4, 96, 0 + --xRANWorker=0x0, 96, 0 + --FpgaDriverCpuInfo=2, 96, 0 + --FrontHaulCpuInfo=3, 96, 0 + --radioDpdkMaster=2, 99, 0 + --BbuPoolSleepEnable=1 + --BbuPoolThreadCorePriority=94 + --BbuPoolThreadCorePolicy=0 + --BbuPoolThreadDefault_0_63=0x68 + --BbuPoolThreadDefault_64_127=0x0 + --BbuPoolThreadSrs_0_63=0x0 + --BbuPoolThreadSrs_64_127=0x0 + --BbuPoolThreadDlbeam_0_63=0x0 + --BbuPoolThreadDlbeam_64_127=0x0 + --BbuPoolThreadUrllc=8 + --FrontHaulTimeAdvance=9450 + --nEthPorts=459523 + --nPhaseCompFlag=1 + --nFecFpgaVersionMu3=0xFC101800 + --nFecFpgaVersionMu0_1=0x0319d420 + --nFhFpgaVersionMu3=0x8001000F + --nFhFpgaVersionMu0_1=0x90010008 + --dpdkXranDeviceCP=0000:21:02.1 + --dpdkXranDeviceUP=0000:21:02.0 + --DuMac=00:11:22:33:44:66 + --RuMac=00:11:22:33:44:55 + --Category=0 + --xranPmdSleep=0 + --Tadv_cp_dl=25 + --T2a_min_cp_dl=50 + --T2a_max_cp_dl=140 + --T2a_min_cp_ul=50 + --T2a_max_cp_ul=140 + --T2a_min_up=25 + --T2a_max_up=140 + --Ta3_min=20 + --Ta3_max=32 + --MTU=9600 + --c_plane_vlan_tag=1 + --u_plane_vlan_tag=2 + --T1a_min_cp_dl=70 + --T1a_max_cp_dl=100 + --T1a_min_cp_ul=60 + --T1a_max_cp_ul=70 + --T1a_min_up=35 + --T1a_max_up=50 + --Ta4_min=0 + --Ta4_max=45 + --DynamicSectionEna=0 + --xRANSFNWrap=0 + --xRANNumDLPRBs=0 + --xRANNumULPRBs=0 + --Gps_Alpha=0 + --Gps_Beta=0 + --xranCompMethod=0 + --nPrbElemDl=0 + --PrbElemDl0=0,48,0,14,1,1,1,9,1 + --PrbElemDl1=48,48,0,14,2,1,1,9,1 + --PrbElemDl2=96,48,0,14,3,1,1,9,1 + --PrbElemDl3=144,48,0,14,4,1,1,9,1 + --PrbElemDl4=144,36,0,14,5,1,1,9,1 + --PrbElemDl5=180,36,0,14,6,1,1,9,1 + --PrbElemDl6=216,36,0,14,7,1,1,9,1 + --PrbElemDl7=252,21,0,14,8,1,1,9,1 + --nPrbElemUl=0 + --PrbElemUl0=0,48,0,14,1,1,1,9,1 + --PrbElemUl1=48,48,0,14,2,1,1,9,1 + --PrbElemUl2=72,36,0,14,3,1,1,9,1 + --PrbElemUl3=108,36,0,14,4,1,1,9,1 + --PrbElemUl4=144,36,0,14,5,1,1,9,1 + --PrbElemUl5=180,36,0,14,6,1,1,9,1 + --PrbElemUl6=216,36,0,14,7,1,1,9,1 + --PrbElemUl7=252,21,0,14,8,1,1,9,1 + --StreamStats=0 + --StreamIp=127.0.0.1 + --StreamPort=2000 + + wls_dev_filename: wls0 + phycfg_apply: Initialize Radio Interface with XRAN library + Setting FecEncSplit to 1 to run on HW accelerator + Setting FecDecSplit to 1 to run on HW accelerator + + timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596249953 [Hz] + Ticks per usec 1596 + MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(20), mlogSize(3084) mlog_mask (-1) + mlogSubframes (128), mlogCores(20), mlogSize(3084) + localMLogTimerInit + System clock (rdtsc) resolution 1596250020 [Hz] + Ticks per us 1596 + MLog Storage: 0x7f6e5b0e3100 -> 0x7f6e5b86b52c [ 7898156 bytes ] + localMLogFreqReg: 1596. Storing: 1596 + Mlog Open successful + + di_xran_init + di_xran_cfg_setup successful + xran_init: MTU 9600 + BBDEV_FEC_ACCL_NR5G + hw-accelerated bbdev 0000:1f:00.1 + total cores 40 c_mask 0x14 core 4 [id] system_core 2 [id] pkt_proc_core 0x0 [mask] pkt_aux_core 0 [id] timing_core 4 [id] + xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x14 -n2 --iova-mode=pa --socket-mem=8192 --socket-limit=8192 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:1f:00.1 + EAL: Detected 40 lcore(s) + EAL: Detected 1 NUMA nodes + EAL: Auto-detected process type: PRIMARY + EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket + EAL: Selected IOVA mode 'PA' + EAL: No available hugepages reported in hugepages-2048kB + EAL: Probing VFIO support... + EAL: VFIO support initialized + EAL: PCI device 0000:1f:00.1 on NUMA socket 0 + EAL: probe driver: 8086:d90 intel_fpga_5gnr_fec_vf + EAL: using IOMMU type 1 (Type 1) + EAL: PCI device 0000:21:02.0 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + initializing port 0 for TX, drv=net_i40e_vf + Port 0 MAC: 00 11 22 33 44 66 + Port 0: nb_rxd 4096 nb_txd 4096 + + Checking link status portid [0] EAL: PCI device 0000:21:02.1 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + initializing port 1 for TX, drv=net_i40e_vf + Port 1 MAC: 00 11 22 33 44 66 + Port 1: nb_rxd 4096 nb_txd 4096 + Checking link status portid [1] vf 0 local SRC MAC: 00 11 22 33 44 66 + vf 0 remote DST MAC: 00 11 22 33 44 55 + vf 1 local SRC MAC: 00 11 22 33 44 66 + vf 1 remote DST MAC: 00 11 22 33 44 55 + xran_init successful, pHandle = 0x5581f440 + bbdev_init: + Socket ID: 0 + FEC is accelerated through BBDEV: 0000:1f:00.1 + wls_layer_init[wls0] nWlsMemorySize[1063256064] + wls_lib: Open wls0 (DPDK memzone) + wls_lib: WLS_Open 0x2bf600000 + wls_lib: link: 0 <-> 1 + wls_lib: Mode 0 + wls_lib: WLS shared management memzone: wls0 + wls_lib: hugePageSize on the system is 1073741824 + wls_lib: WLS_Alloc [1063256064] bytes + + + =========================================================================================================== + PHY VERSION + =========================================================================================================== + Version: #DIRTY# + IMG-date: Apr 27 2020 + IMG-time: 12:54:54 + =========================================================================================================== + DEPENDENCIES VERSIONS + =========================================================================================================== + FlexRAN BBU pooling version #DIRTY# + FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY# + FlexRAN SDK bblib_layermapping_5gnr version #DIRTY# + FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY# + FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_llr_demapping version #DIRTY# + FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY# + FlexRAN SDK bblib_reed_muller version #DIRTY# + FlexRAN SDK bblib_lte_modulation version #DIRTY# + FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY# + FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY# + FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY# + FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY# + FlexRAN SDK bblib_fd_correlation version #DIRTY# + FlexRAN SDK bblib_scramble_5gnr version #DIRTY# + FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY# + FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY# + FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY# + FlexRAN SDK bblib_prach_5gnr version #DIRTY# + FlexRAN SDK bblib_fft_ifft version #DIRTY# + FlexRAN SDK bblib_pucch_5gnr version #DIRTY# + FlexRAN SDK bblib_lte_crc version #DIRTY# + FlexRAN SDK bblib_common version #DIRTY# + =========================================================================================================== + + =========================================================================================================== + Non BBU threads in application + =========================================================================================================== + nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 112583] binding on [CPU 0] [PRIO: 0] [POLICY: 1] + wls_rx_handler (non-rt): [PID: 112587] binding on [CPU 0] + =========================================================================================================== + PHY>welcome to application console + PHY>Received MSG_TYPE_PHY_UL_IQ_SAMPLES + Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0 + phydi_read_write_iq_samples: direction[1] nNumerologyMult[8] fftSize[1024, 11088, SRS: 792] numSubframe[80] numAntenna[2] numPorts[2] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/mu3_100mhz/2/../../../ul/mu3_100mhz/1/uliq00_tst1.bin] filename_in_prach_iq[] + Received MSG_TYPE_PHY_CONFIG_REQ: 0 + Processing MSG_TYPE_PHY_CONFIG_REQ: 0 + phy_bbupool_set_config: Using cores: 0x0000000000000068 for BBU Pool nBbuPoolSleepEnable: 1 + BBU Pooling: queueId = 0, the according nCoreNum = 3, the according cpuSetMask = 0x68 + BBU Pooling: gCoreIdxMap[0] = 3 is available! + BBU Pooling: gCoreIdxMap[1] = 5 is available! + BBU Pooling: gCoreIdxMap[2] = 6 is available! + BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered + BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered + BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered + BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered + BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered + BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered + BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered + BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered + BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered + BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered + BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered + BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered + BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered + BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered + BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered + BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered + BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered + BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered + BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered + BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered + BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered + BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS + BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A + + BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX + BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST + BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX + BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST + BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST + BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR + BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE + BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A + + BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST + BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST + BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST + BBU Pooling: next taskList of UL_L1_SRS: UL_L1_POST + BBU Pooling: next taskList of DL_L1_POST: N/A + + BBU Pooling: next taskList of UL_L1_POST: N/A + + enter RtThread Launch + 3 thread associated with queue 0:coreIdx 0 1 2 + Leave RtThread Launch + launching Thread 0 Queue 0 uCoreIdx 0 CoreId 3 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + bbupool_core_main: the server's coreNum = 40, the nCore = 3,nRtCoreMask = 0x68, the nFeIfCore = 0,nFeIfCoreMask = 0x0 + bbupool_core_main pthread_setaffinity_np succeed: coreId = 0, result = 0 + nr5g_gnb_mac2phy_api_proc_print_phy_init [0]: + nCarrierIdx: 0 + nDMRSTypeAPos: 2 + nPhyCellId: 100 + nDLAbsFrePointA: 27968160 + nULAbsFrePointA: 27968160 + nDLBandwidth: 100 + nULBandwidth: 100 + nDLFftSize: 1024 + nULFftSize: 1024 + nSSBPwr: 0 + nSSBAbsFre: 0 + nSSBPeriod: 2 + nSSBSubcSpacing: 3 + nSSBSubcOffset: 0 + nSSBPrbOffset: 0 + nMIB[0]: 255 + nMIB[1]: 255 + nMIB[2]: 255 + nDLK0: 0 + nULK0: 0 + nSSBMask[0]: 63 + nSSBMask[1]: 0 + nNrOfTxAnt: 2 + nNrOfRxAnt: 2 + nNrOfDLPorts: 2 + nNrOfULPorts: 2 + nCarrierAggregationLevel: 0 + nFrameDuplexType: 1 + nSubcCommon: 3 + nTddPeriod: 5 (TDD) + SlotConfig: + Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13 + 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + + nPrachConfIdx: 81 + nPrachSubcSpacing: 3 + nPrachZeroCorrConf: 2 + nPrachRestrictSet: 0 + nPrachRootSeqIdx: 0 + nPrachFreqStart: 0 + nPrachFdm: 1 + nPrachSsbRach: 0 + nPrachNrofRxRU: 2 + nCyclicPrefix: 0 + nGroupHopFlag: 0 + nSequenceHopFlag: 0 + nHoppingId: 0 + read_table: File table/common/pss_table.bin of size 381 read_size: 381 + read_table: File table/common/sss_table.bin of size 128016 read_size: 128016 + read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916 + read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040 + read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216 + read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216 + BBU Pooling Info: maximum period length was configured, preMaxSF = 8000, postMasSF = 8000 + set_slot_type SlotPattern: + Slot: 0 1 2 3 4 + 0 DL DL DL SP UL + + PHYDI-INIT[from 0] PhyInstance: 0 + + --------------------------------------------------------- + Global Variables: + --------------------------------------------------------- + gCarrierAggLevel: 0 + gCarrierAggLevelInit: 1 + gSupportedAVX2 1 + --------------------------------------------------------- + + Received MSG_TYPE_PHY_START_REQ: 0 + Processing MSG_TYPE_PHY_START_REQ: 0 + + xran_max_frame 99 + XRAN_UP_VF: 0x0000 + XRAN_CP_VF: 0x0001 + xran_timing_source_thread [CPU 4] [PID: 112582] + O-DU: thread_run start time: 04/27/20 20:20:33.000000010 UTC [125] + Start C-plane DL 25 us after TTI [trigger on sym 3] + Start C-plane UL 55 us after TTI [trigger on sym 7] + Start U-plane DL 50 us before OTA [offset in sym -5] + Start U-plane UL 45 us OTA [offset in sym 6] + C-plane to U-plane delay 25 us after TTI + Start Sym timer 8928 ns + interval_us 125 + PHYDI-START[from 0] PhyInstance: 0, Mode: 4, Count: 100040207, Period: 0, NumSlotPerSfn: 80 + gnb_start_xran: gxRANStarted[0] CC 1 Ant 4 AntElm 0 + XRAN front haul xran_mm_init + xran_sector_get_instances [0]: CC 0 handle 0x7f6e397307c0 + Handle: 0x1994ce00 Instance: 0x7f6e397307c0 + gnb_start_xran [0]: CC 0 handle 0x7f6e397307c0 + Sucess xran_mm_init Instance 0x7f6e397307c0 + nSectorNum 1 + ru_0_cc_0_idx_0: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 0] nNumberOfBuffers 2240 nBufferSize 5856 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2e817b900 + ru_0_cc_0_idx_1: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 1] nNumberOfBuffers 35840 nBufferSize 24 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x2e7266c40 + ru_0_cc_0_idx_2: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 2] nNumberOfBuffers 2240 nBufferSize 48416 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x2e5cb4600 + ru_0_cc_0_idx_3: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 3] nNumberOfBuffers 2240 nBufferSize 5856 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x2df2872c0 + ru_0_cc_0_idx_4: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 4] nNumberOfBuffers 35840 nBufferSize 24 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x2de372600 + ru_0_cc_0_idx_5: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 5] nNumberOfBuffers 2240 nBufferSize 48416 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x2dcdbffc0 + ru_0_cc_0_idx_6: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 6] nNumberOfBuffers 2240 nBufferSize 8192 + CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x2d6392c80 + gnb_init_xran_cp + init xran successfully + ---------------------------------------------------------------------------- + mem_mgr_display_size: + Num Memory Alloc: 5,186 + Total Memory Size: 4,389,524,920 + ---------------------------------------------------------------------------- + + + BBU Pooling: enter multicell Activate! + BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 547270377116554 at sf=0 with queue 0 successfully + BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 1 + BBU Pooling: multiCell Activate sucessfully! + BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 3 at 547270377104408 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 547270377117634 at sf=0 with queue 0 successfully + phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[80] + ==== l1app Time: 5001 ms NumCarrier: 1 NumBbuCores: 3 rxPcktCnt: 93621 rachPcktCnt 46811 Total Proc Time: [ 62.00.. 98.39..209.00] usces==== + ==== [o-du][rx 619683 pps 123936 kbps 2621619][tx 1996407 pps 399281 kbps 9181862] [on_time 619683 early 0 late 0 corrupt 0 pkt_dupl 16 Total 619683] IO Util: 79.61 % + + +7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter:: + + [root@xran flexran] cd ./bin/nr5g/gnb/testmac + + +8. To execute test case type:: + + ./l2.sh + --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg + + +where output corresponding to Test MAC:: + + [root@sc12-xran-sub6 testmac]# ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg + kernel.sched_rt_runtime_us = -1 + kernel.shmmax = 2147483648 + kernel.shmall = 2147483648 + Note: Forwarding request to 'systemctl disable irqbalance.service'. + start 5GNR Test MAC + ========================= + 5GNR Testmac Application + ========================= + testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml + --------------------------- + TestMacCfg.xml Version: 20.04 + --------------------------- + --version=20.04 + --wls_dev_name=wls0 + --wlsMemorySize=0x3F600000 + --dpdkIovaMode=0 + --PhyStartMode=1 + --PhyStartPeriod=40 + --PhyStartCount=0 + --MlogSubframes=128 + --MlogCores=3 + --MlogSize=2048 + --wlsRxThread=1, 90, 0 + --systemThread=0, 0, 0 + --runThread=0, 89, 0 + --urllcThread=19, 90, 0 + + wls_dev_filename: wls0 + sys_reg_signal_handler:[err] signal handler in NULL + sys_reg_signal_handler:[err] signal handler in NULL + timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596245684 [Hz] + Ticks per usec 1596 + MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1) + mlogSubframes (128), mlogCores(3), mlogSize(2048) + localMLogTimerInit + System clock (rdtsc) resolution 1596250375 [Hz] + Ticks per us 1596 + MLog Storage: 0x7f84cae86100 -> 0x7f84caf46920 [ 788512 bytes ] + localMLogFreqReg: 1596. Storing: 1596 + Mlog Open successful + Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa + EAL: Detected 40 lcore(s) + EAL: Detected 1 NUMA nodes + EAL: Auto-detected process type: SECONDARY + EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_112640_1f1baf0a9b316 + EAL: Selected IOVA mode 'PA' + EAL: Probing VFIO support... + EAL: VFIO support initialized + EAL: PCI device 0000:19:00.0 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:19:00.1 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:1d:00.0 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:1d:00.1 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:21:00.0 on NUMA socket 0 + EAL: probe driver: 8086:158b net_i40e + EAL: PCI device 0000:21:00.1 on NUMA socket 0 + EAL: probe driver: 8086:158b net_i40e + EAL: PCI device 0000:21:02.0 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + EAL: using IOMMU type 1 (Type 1) + EAL: PCI device 0000:21:02.1 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + EAL: PCI device 0000:21:0a.0 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + EAL: 0000:21:0a.0 cannot find TAILQ entry for PCI device! + EAL: Requested device 0000:21:0a.0 cannot be used + EAL: PCI device 0000:21:0a.1 on NUMA socket 0 + EAL: probe driver: 8086:154c net_i40e_vf + EAL: 0000:21:0a.1 cannot find TAILQ entry for PCI device! + EAL: Requested device 0000:21:0a.1 cannot be used + EAL: PCI device 0000:67:00.0 on NUMA socket 0 + EAL: probe driver: 8086:37d2 net_i40e + EAL: PCI device 0000:67:00.1 on NUMA socket 0 + EAL: probe driver: 8086:37d2 net_i40e + wls_lib: Open wls0 (DPDK memzone) + wls_lib: WLS_Open 0x2bf600000 + wls_lib: link: 1 <-> 0 + wls_lib: Mode 1 + wls_lib: WLS shared management memzone: wls0 + wls_lib: hugePageSize on the system is 1073741824 + wls_lib: WLS_Alloc [1063256064] bytes + wls_lib: Connecting to remote peer ... + wls_lib: Connected to remote peer + wls_mac_create_mem_array: pMemArray[0xf3500f0] pMemArrayMemory[0x280000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056] + WLS_EnqueueBlock [1] + WLS inited ok [383] + =========================================================================================================== + TESTMAC VERSION + =========================================================================================================== + $Version: #DIRTY# $ (x86) + IMG-date: Apr 27 2020 + IMG-time: 12:55:58 + =========================================================================================================== + =========================================================================================================== + Testmac threads in application + =========================================================================================================== + testmac_run_thread: [PID: 112644] binding on [CPU 0] [PRIO: 89] [POLICY: 1] + wls_mac_rx_task: [PID: 112643] binding on [CPU 1] [PRIO: 90] [POLICY: 1] + =========================================================================================================== + + testmac_set_phy_start: mode[1], period[40], count[0] + + testmac_run_load_files: + Loading DL Config Files: + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg + Loading UL Config Files: + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg + Loading FD Config Files: + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg + + TESTMAC DL TESTS: + Numerology[0] Bandwidth[5] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[0] Bandwidth[10] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[0] Bandwidth[20] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[1] Bandwidth[100] + 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211 + 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 + 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241 + 1242 1243 1244 1245 1250 1251 1252 1300 1301 1302 + 1303 1304 1305 1402 1404 1408 1416 1500 1501 1502 + 1503 1504 1505 1506 2213 2214 2215 2217 2218 2219 + 2223 2224 2225 2227 2228 2229 2500 2501 2502 2503 + 2504 3213 3214 3215 3217 3218 3219 3223 3224 3225 + 3227 3228 3229 + Numerology[3] Bandwidth[100] + 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011 + 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031 + 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003 + 3030 + + TESTMAC UL TESTS: + Numerology[0] Bandwidth[5] + 1001 1002 1003 + Numerology[0] Bandwidth[10] + 1001 1002 + Numerology[0] Bandwidth[20] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[1] Bandwidth[100] + 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038 + 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074 + 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092 + 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105 + 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117 + 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132 + 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 + 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160 + 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 + 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206 + 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 + 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233 + 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421 + 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 + 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504 + 1505 1506 1507 1508 1511 1512 1513 1514 1515 1516 + 1540 1541 1542 1563 1564 1565 1566 1567 1568 1569 + 1570 1571 1572 1573 1574 1600 1601 1602 1603 1604 + 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 + 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 + 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 + 1635 1636 1637 1638 1639 1640 1641 1642 1700 1701 + 2236 2237 3236 3237 + Numerology[3] Bandwidth[100] + 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012 + 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026 + 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 + 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051 + 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065 + 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084 + 1085 1086 2001 2002 2003 3001 3002 3003 + + TESTMAC FD TESTS: + Numerology[0] Bandwidth[5] + 1001 6001 8001 10001 12001 + Numerology[0] Bandwidth[10] + 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002 + 6002 8002 10002 12002 1003 + Numerology[0] Bandwidth[20] + 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021 + 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201 + 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221 + 1222 1223 1224 1225 1226 1227 1228 + Numerology[1] Bandwidth[40] + 1001 1002 1003 + Numerology[1] Bandwidth[100] + 1001 1200 1201 1202 1203 1204 1205 1206 1207 1208 + 1209 1210 1300 1301 1302 1303 1304 1305 1306 1307 + 1308 1350 1351 1352 1353 1354 1355 1356 1357 1358 + 1370 1371 1372 1373 1401 1402 1403 1404 1405 1406 + 1411 1412 1490 1494 1500 1501 1502 1503 1504 1510 + 1511 1512 1513 1514 1515 1520 1521 1522 1523 1524 + 1525 1526 1527 1528 1529 1530 1531 1532 1540 1541 + 1700 1701 1702 2520 2521 2522 2523 2524 2525 2526 + 2527 2528 2529 2530 2531 2532 3524 3525 3526 3527 + 3528 3529 3530 3531 3532 4524 4525 4526 4527 4528 + 4529 4530 4531 4532 + Numerology[3] Bandwidth[100] + 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011 + 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080 + 1081 1082 2001 3001 + testmac_run_parse_file Parsing config file: ./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg + testmac_set_phy_start: mode[4], period[0], count[100040200] + Adding Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ + Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg + ---------------------------------------------------------------------------------------- + Running Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ + Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg + TESTMAC>welcome to application console + + MLogRestart + MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1) + mlogSubframes (128), mlogCores(3), mlogSize(2048) + localMLogTimerInit + System clock (rdtsc) resolution 1596249901 [Hz] + Ticks per us 1596 + MLog Storage: 0x7f84bc000900 -> 0x7f84bc0c1120 [ 788512 bytes ] + localMLogFreqReg: 1596. Storing: 1596 + Mlog Open successful + + testmac_mac2phy_set_num_cells: Setting Max Cells: 1 + testmac_config_parse: test_num[1002] test_type[2] numcarrier[1] + host_config_set_int Error(nPrachSsbRach, 3): Out of range: [min(0), max(1)] + Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0) + Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0) + Queueing MSG_TYPE_PHY_CONFIG_REQ(0) and sending list + Received MSG_TYPE_PHY_CONFIG_RESP(0) + Queueing MSG_TYPE_PHY_START_REQ(0) and sending list + Received MSG_TYPE_PHY_START_RESP(0) + ==== testmac Time: 5000 ms NumCarrier: 1 Total Proc Time: [ 0.00.. 4.11.. 14.00] usces==== + Core Utilization [Core: 1] [Util %: 2.97%] + ==== testmac Time: 10000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 13.00] usces==== + Core Utilization [Core: 1] [Util %: 4.81%] + ==== testmac Time: 15000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 6.00] usces==== + + +Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies +==================================================================================== + +The 5G NR layer 1 application can be used for executing the scenario for +multiple cells with multiple numerologies. The current release supports +the constant configuration of different numerologies on different O-RU +ports. It is required that the first O-RU (O-RU0) to be configured with +highest numerology. The configuration procedure is similar as described +in above section. Please refer to the configuration file located in +bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml + +Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO +===================================================================== + +The 5G NR layer 1 application can be used for executing the scenario for +Massive-MIMO with either the RU sample application or just the O-DU +side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake +system with Columbiavile NIC. The current release supports the constant +configuration of the slot pattern and RB allocation on the PHY side. +Please follow the general build process in the FlexRAN 5G NR Reference +Solution L1 User Guide (refer to Table 2.) + +1. O-RAN library is enabled by default l1 application + +2. Build the 5G NR L1 application using the command:: + + ./flexran_build.sh -r 5gnr_l1app_sub6 -i snc -m sdk -m fb -m mlog –m wls + -m 5gnr_l1app_mmw -m xran -m 5gnr_testmac + +3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml. :: + + + 20.08 + + 3 + + 25 + + 2 + + 1 + + + 0000:51:01.0 + 0000:51:01.1 + 0000:51:01.2 + 0000:51:01.3 + + + 0000:51:01.2 + 0000:51:01.3 + 0000:51:01.6 + 0000:51:01.7 + + + 0000:51:01.4 + 0000:51:01.5 + 0000:51:02.2 + 0000:51:02.3 + + + 0000:00:00.0 + 0000:00:00.0 + 0000:00:00.0 + 0000:00:00.0 + + + 00:11:22:33:00:01 + 00:11:22:33:00:11 + + 00:11:22:33:00:21 + 00:11:22:33:00:31 + + + 00:11:22:33:01:01 + 00:11:22:33:01:11 + + 00:11:22:33:01:21 + 00:11:22:33:01:31 + + + 00:11:22:33:02:01 + 00:11:22:33:02:11 + + 00:11:22:33:02:21 + 00:11:22:33:02:31 + + + 00:11:22:33:03:01 + 00:11:22:33:03:11 + + 00:11:22:33:03:21 + 00:11:22:33:03:31 + + + 1 + + 0 + + 1 + + 2 + + 3 + + + 1 + + 1 + + 1 + + 2 + + 3 + + + 1 + + 2 + + 1 + + 2 + + 3 + + + 22, 96, 0 + + + 0x3800000, 96, 0 + + 1 + + + 0 + + + 25 + + 285 + 429 + + 285 + 429 + + 71 + 428 + + 20 + 32 + + + + 9600 + + 1 + 2 + + + 258 + 429 + + 285 + 300 + + 96 + 196 + + 0 + 75 + + + 1 + + 0 + + 0 + 1 + + 0 + + 0 + + 0 + + 0 + + + 1 + + 6 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 96,48,0,14,2,1,1,9,1,0,0 + 144,48,0,14,4,1,1,9,1,0,0 + 192,48,0,14,5,1,1,9,1,0,0 + 240,33,0,14,6,1,1,9,1,0,0 + 240,33,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,17,0,0,9,1 + + 6 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 96,48,0,14,2,1,1,9,1,0,0 + 144,48,0,14,4,1,1,9,1,0,0 + 192,48,0,14,5,1,1,9,1,0,0 + 240,33,0,14,6,1,1,9,1,0,0 + 240,33,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,24,0,0,9,1 + 2,17,0,0,9,1 + + 1 + + + 0,273,0,14,1,1,1,9,1,0,0 + + 2 + + + 0,48,0,14,0,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 96,48,0,14,3,1,1,9,1,0,0 + 144,48,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + + 2 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 72,36,0,14,3,1,1,9,1,0,0 + 108,36,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + + 1 + + + 0,273,0,14,1,1,1,9,1,0,0 + + 2 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 96,48,0,14,3,1,1,9,1,0,0 + 144,48,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + + 2 + + + 0,48,0,14,1,1,1,9,1,0,0 + 48,48,0,14,2,1,1,9,1,0,0 + 72,36,0,14,3,1,1,9,1,0,0 + 108,36,0,14,4,1,1,9,1,0,0 + 144,36,0,14,5,1,1,9,1,0,0 + 180,36,0,14,6,1,1,9,1,0,0 + 216,36,0,14,7,1,1,9,1,0,0 + 252,21,0,14,8,1,1,9,1,0,0 + + + 2,24,0,0,9,1 + 2,24,0,0,9,1 + + 1 + + + 0,273,0,14,1,1,1,9,1,0,0 + + + + +4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). :: + + ethDevice0=0000:51:01.0 + ethDevice1=0000:51:01.1 + ethDevice2=0000:51:01.2 + ethDevice3=0000:51:01.3 + ethDevice4=0000:51:01.4 + ethDevice5=0000:51:01.5 + ethDevice6= + ethDevice7= + ethDevice8= + ethDevice9= + ethDevice10= + ethDevice11= + fecDevice0=0000:92:00.0 + +5. Use configuration of test mac per:: + + /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg + phystart 4 0 100200 + TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg, + fd/mu1_100mhz/377/fd_testconfig_tst377.cfg, + fd/mu1_100mhz/377/fd_testconfig_tst377.cfg + +6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter:: + + [root@xran flexran] cd ./bin/nr5g/gnb/l1 + ./l1.sh -xranmmimo + Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB) + DPDK WLS MODE + kernel.sched_rt_runtime_us = -1 + kernel.shmmax = 2147483648 + kernel.shmall = 2147483648 + Note: Forwarding request to 'systemctl disable irqbalance.service'. + using configuration file phycfg_xran.xml + using configuration file xrancfg_sub6_mmimo.xml + >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran.xml --xranfile=xrancfg_sub6_mmimo.xml + FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY# + FlexRAN SDK bblib_layermapping_5gnr version #DIRTY# + FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY# + FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_llr_demapping version #DIRTY# + FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY# + FlexRAN SDK bblib_reed_muller version #DIRTY# + FlexRAN SDK bblib_lte_modulation version #DIRTY# + FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY# + FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY# + FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY# + FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY# + FlexRAN SDK bblib_fd_correlation version #DIRTY# + FlexRAN SDK bblib_scramble_5gnr version #DIRTY# + FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY# + FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY# + FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY# + FlexRAN SDK bblib_prach_5gnr version #DIRTY# + FlexRAN SDK bblib_fft_ifft version #DIRTY# + FlexRAN SDK bblib_pucch_5gnr version #DIRTY# + FlexRAN SDK bblib_lte_ldpc_decoder version #DIRTY# + FlexRAN SDK bblib_lte_ldpc_encoder version #DIRTY# + FlexRAN SDK bblib_lte_LDPC_ratematch version #DIRTY# + FlexRAN SDK bblib_lte_rate_dematching_5gnr version #DIRTY# + FlexRAN SDK bblib_common version #DIRTY# + FlexRAN SDK bblib_lte_crc version #DIRTY# + FlexRAN SDK bblib_lte_dft_idft version #DIRTY# + FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY# + FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY# + FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_zf_matrix_gen version #DIRTY# + FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY# + ========================= + 5GNR PHY Application + ========================= + + + -------------------------------------------------------- + File[phycfg_xran.xml] Version: 20.08 + -------------------------------------------------------- + --version=20.08 + --successiveNoApi=15 + --wls_dev_name=wls0 + --wlsMemorySize=0x3F600000 + --dlIqLog=0 + --ulIqLog=0 + --iqLogDumpToFile=0 + --phyMlog=1 + --phyStats=1 + --dpdkMemorySize=18432 + --dpdkIovaMode=0 + --dpdkBasebandFecMode=1 + --dpdkBasebandDevice=0000:92:00.0 + --radioEnable=4 + --ferryBridgeMode=1 + --ferryBridgeEthPort=1 + --ferryBridgeSyncPorts=0 + --ferryBridgeOptCableLoopback=0 + --radioCfg0PCIeEthDev=0000:19:00.0 + --radioCfg0DpdkRx=1 + --radioCfg0DpdkTx=2 + --radioCfg0TxAnt=2 + --radioCfg0RxAnt=2 + --radioCfg0RxAgc=0 + --radioCfg0NumCell=1 + --radioCfg0Cell0PhyId=0 + --radioCfg0Cell1PhyId=1 + --radioCfg0Cell2PhyId=2 + --radioCfg0Cell3PhyId=3 + --radioCfg0Cell4PhyId=4 + --radioCfg0Cell5PhyId=5 + --radioCfg0riuMac=11:22:33:44:55:66 + --radioCfg1PCIeEthDev=0000:03:00.1 + --radioCfg1DpdkRx=1 + --radioCfg1DpdkTx=1 + --radioCfg1TxAnt=4 + --radioCfg1RxAnt=4 + --radioCfg1RxAgc=0 + --radioCfg1NumCell=1 + --radioCfg1Cell0PhyId=2 + --radioCfg1Cell1PhyId=3 + --radioCfg1Cell2PhyId=2 + --radioCfg1Cell3PhyId=3 + --radioCfg1riuMac=ac:1f:6b:2c:9f:07 + --radioCfg2PCIeEthDev=0000:05:00.0 + --radioCfg2DpdkRx=10 + --radioCfg2DpdkTx=11 + --radioCfg2TxAnt=4 + --radioCfg2RxAnt=4 + --radioCfg2RxAgc=0 + --radioCfg2NumCell=2 + --radioCfg2Cell0PhyId=4 + --radioCfg2Cell1PhyId=5 + --radioCfg2Cell2PhyId=2 + --radioCfg2Cell3PhyId=3 + --radioCfg2riuMac=ac:1f:6b:2c:9f:07 + --radioCfg3PCIeEthDev=0000:05:00.1 + --radioCfg3DpdkRx=12 + --radioCfg3DpdkTx=13 + --radioCfg3TxAnt=4 + --radioCfg3RxAnt=4 + --radioCfg3RxAgc=0 + --radioCfg3NumCell=2 + --radioCfg3Cell0PhyId=6 + --radioCfg3Cell1PhyId=7 + --radioCfg3Cell2PhyId=2 + --radioCfg3Cell3PhyId=3 + --radioCfg3riuMac=ac:1f:6b:2c:9f:07 + --radioCfg4PCIeEthDev=0000:00:08.0 + --radioCfg4DpdkRx=14 + --radioCfg4DpdkTx=15 + --radioCfg4TxAnt=4 + --radioCfg4RxAnt=4 + --radioCfg4RxAgc=0 + --radioCfg4NumCell=2 + --radioCfg4Cell0PhyId=8 + --radioCfg4Cell1PhyId=9 + --radioCfg4Cell2PhyId=2 + --radioCfg4Cell3PhyId=3 + --radioCfg4riuMac=ac:1f:6b:2c:9f:07 + --radioCfg5PCIeEthDev=0000:08:00.0 + --radioCfg5DpdkRx=16 + --radioCfg5DpdkTx=16 + --radioCfg5TxAnt=4 + --radioCfg5RxAnt=4 + --radioCfg5RxAgc=0 + --radioCfg5NumCell=2 + --radioCfg5Cell0PhyId=10 + --radioCfg5Cell1PhyId=11 + --radioCfg5Cell2PhyId=2 + --radioCfg5Cell3PhyId=3 + --radioCfg5riuMac=ac:1f:6b:2c:9f:07 + --radioCfg6PCIeEthDev=0000:00:05.0 + --radioCfg6DpdkRx=16 + --radioCfg6DpdkTx=16 + --radioCfg6TxAnt=4 + --radioCfg6RxAnt=4 + --radioCfg1RxAgc=0 + --radioCfg6NumCell=2 + --radioCfg6Cell0PhyId=12 + --radioCfg6Cell1PhyId=13 + --radioCfg6Cell2PhyId=2 + --radioCfg6Cell3PhyId=3 + --radioCfg6riuMac=ac:1f:6b:2c:9f:07 + --radioCfg7PCIeEthDev=0000:00:06.0 + --radioCfg7DpdkRx=16 + --radioCfg7DpdkTx=16 + --radioCfg7TxAnt=4 + --radioCfg7RxAnt=4 + --radioCfg7RxAgc=0 + --radioCfg7NumCell=2 + --radioCfg7Cell0PhyId=14 + --radioCfg7Cell1PhyId=15 + --radioCfg7Cell2PhyId=2 + --radioCfg7Cell3PhyId=3 + --radioCfg7riuMac=ac:1f:6b:2c:9f:07 + --radioPort0=0 + --radioPort1=1 + --radioPort2=2 + --radioPort3=3 + --radioPort4=4 + --radioPort5=5 + --radioPort6=6 + --radioPort7=7 + --PdschSymbolSplit=0 + --PdschDlWeightSplit=0 + --FecEncSplit=4 + --PuschChanEstSplit=0 + --PuschMmseSplit=0 + --PuschLlrRxSplit=0 + --PuschUlWeightSplit=0 + --FecDecEarlyTermDisable=0 + --FecDecNumIter=12 + --FecDecSplit=4 + --llrOutDecimalDigit=2 + --IrcEnableThreshold=-10 + --PuschNoiseScale=2 + --CEInterpMethod=0 + --PucchSplit=0 + --SrsCeSplit=0 + --prachDetectThreshold=0 + --MlogSubframes=128 + --MlogCores=40 + --MlogSize=10000 + --systemThread=2, 0, 0 + --timerThread=0, 96, 0 + --FpgaDriverCpuInfo=3, 96, 0 + --FrontHaulCpuInfo=3, 96, 0 + --radioDpdkMaster=2, 99, 0 + --BbuPoolSleepEnable=1 + --BbuPoolThreadCorePriority=94 + --BbuPoolThreadCorePolicy=0 + --BbuPoolThreadDefault_0_63=0xF0 + --BbuPoolThreadDefault_64_127=0x0 + --BbuPoolThreadSrs_0_63=0x0 + --BbuPoolThreadSrs_64_127=0x0 + --BbuPoolThreadDlbeam_0_63=0x0 + --BbuPoolThreadDlbeam_64_127=0x0 + --BbuPoolThreadUrllc=0x100 + --FrontHaulTimeAdvance=7450 + --nEthPorts=462607 + --nPhaseCompFlag=0 + --nFecFpgaVersionMu3=0x20010900 + --nFecFpgaVersionMu0_1=0x0423D420 + --nFhFpgaVersionMu3=0x8001000F + --nFhFpgaVersionMu0_1=0x90010008 + --StreamStats=0 + --StreamIp=10.255.83.5 + --StreamPort=4010 + + wls_dev_filename: wls0 + phycfg_apply: Initialize Radio Interface with XRAN library + Setting FecEncSplit to 1 to run on HW accelerator + Setting FecDecSplit to 1 to run on HW accelerator + + + + -------------------------------------------------------- + File[xrancfg_sub6_mmimo.xml] Version: 20.08 + -------------------------------------------------------- + --version=20.08 + --oRuNum=3 + --oRuEthLinkSpeed=25 + --oRuLinesNumber=2 + --oRuCUon1Vf=1 + --PciBusAddoRu0Vf0=0000:51:01.0 + --PciBusAddoRu0Vf1=0000:51:01.1 + --PciBusAddoRu0Vf2=0000:51:01.2 + --PciBusAddoRu0Vf3=0000:51:01.3 + --PciBusAddoRu1Vf0=0000:51:01.2 + --PciBusAddoRu1Vf1=0000:51:01.3 + --PciBusAddoRu1Vf2=0000:51:01.6 + --PciBusAddoRu1Vf3=0000:51:01.7 + --PciBusAddoRu2Vf0=0000:51:01.4 + --PciBusAddoRu2Vf1=0000:51:01.5 + --PciBusAddoRu2Vf2=0000:51:02.2 + --PciBusAddoRu2Vf3=0000:51:02.3 + --PciBusAddoRu3Vf0=0000:00:00.0 + --PciBusAddoRu3Vf1=0000:00:00.0 + --PciBusAddoRu3Vf2=0000:00:00.0 + --PciBusAddoRu3Vf3=0000:00:00.0 + --oRuRem0Mac0=00:11:22:33:00:01 + --oRuRem0Mac1=00:11:22:33:00:11 + --oRuRem0Mac2=00:11:22:33:00:21 + --oRuRem0Mac3=00:11:22:33:00:31 + --oRuRem1Mac0=00:11:22:33:01:01 + --oRuRem1Mac1=00:11:22:33:01:11 + --oRuRem1Mac2=00:11:22:33:01:21 + --oRuRem1Mac3=00:11:22:33:01:31 + --oRuRem2Mac0=00:11:22:33:02:01 + --oRuRem2Mac1=00:11:22:33:02:11 + --oRuRem2Mac2=00:11:22:33:02:21 + --oRuRem2Mac3=00:11:22:33:02:31 + --oRuRem3Mac0=00:11:22:33:03:01 + --oRuRem3Mac1=00:11:22:33:03:11 + --oRuRem3Mac2=00:11:22:33:03:21 + --oRuRem3Mac3=00:11:22:33:03:31 + --oRu0NumCc=1 + --oRu0Cc0PhyId=0 + --oRu0Cc1PhyId=1 + --oRu0Cc2PhyId=2 + --oRu0Cc3PhyId=3 + --oRu1NumCc=1 + --oRu1Cc0PhyId=1 + --oRu1Cc1PhyId=1 + --oRu1Cc2PhyId=2 + --oRu1Cc3PhyId=3 + --oRu2NumCc=1 + --oRu2Cc0PhyId=2 + --oRu2Cc1PhyId=1 + --oRu2Cc2PhyId=2 + --oRu2Cc3PhyId=3 + --xRANThread=22, 96, 0 + --xRANWorker=0x3800000, 96, 0 + --Category=1 + --xranPmdSleep=0 + --Tadv_cp_dl=25 + --T2a_min_cp_dl=285 + --T2a_max_cp_dl=429 + --T2a_min_cp_ul=285 + --T2a_max_cp_ul=429 + --T2a_min_up=71 + --T2a_max_up=428 + --Ta3_min=20 + --Ta3_max=32 + --MTU=9600 + --c_plane_vlan_tag=1 + --u_plane_vlan_tag=2 + --T1a_min_cp_dl=258 + --T1a_max_cp_dl=429 + --T1a_min_cp_ul=285 + --T1a_max_cp_ul=300 + --T1a_min_up=96 + --T1a_max_up=196 + --Ta4_min=0 + --Ta4_max=75 + --EnableCp=1 + --DynamicSectionEna=0 + --DynamicSectionEnaUL=0 + --xRANSFNWrap=1 + --xRANNumDLPRBs=0 + --xRANNumULPRBs=0 + --Gps_Alpha=0 + --Gps_Beta=0 + --xranCompMethod=1 + --oRu0nPrbElemDl=6 + --oRu0PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0 + --oRu0PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu0PrbElemDl2=96,48,0,14,2,1,1,9,1,0,0 + --oRu0PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0 + --oRu0PrbElemDl4=192,48,0,14,5,1,1,9,1,0,0 + --oRu0PrbElemDl5=240,33,0,14,6,1,1,9,1,0,0 + --oRu0PrbElemDl6=240,33,0,14,7,1,1,9,1,0,0 + --oRu0PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu0ExtBfwDl0=2,24,0,0,9,1 + --oRu0ExtBfwDl1=2,24,0,0,9,1 + --oRu0ExtBfwDl2=2,24,0,0,9,1 + --oRu0ExtBfwDl3=2,24,0,0,9,1 + --oRu0ExtBfwDl4=2,24,0,0,9,1 + --oRu0ExtBfwDl5=2,17,0,0,9,1 + --oRu0nPrbElemUl=6 + --oRu0PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0 + --oRu0PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu0PrbElemUl2=96,48,0,14,2,1,1,9,1,0,0 + --oRu0PrbElemUl3=144,48,0,14,4,1,1,9,1,0,0 + --oRu0PrbElemUl4=192,48,0,14,5,1,1,9,1,0,0 + --oRu0PrbElemUl5=240,33,0,14,6,1,1,9,1,0,0 + --oRu0PrbElemUl6=240,33,0,14,7,1,1,9,1,0,0 + --oRu0PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu0ExtBfwUl0=2,24,0,0,9,1 + --oRu0ExtBfwUl1=2,24,0,0,9,1 + --oRu0ExtBfwUl2=2,24,0,0,9,1 + --oRu0ExtBfwUl3=2,24,0,0,9,1 + --oRu0ExtBfwUl4=2,24,0,0,9,1 + --oRu0ExtBfwUl5=2,17,0,0,9,1 + --oRu0nPrbElemSrs=1 + --oRu0PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0 + --oRu1nPrbElemDl=2 + --oRu1PrbElemDl0=0,48,0,14,0,1,1,9,1,0,0 + --oRu1PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu1PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0 + --oRu1PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0 + --oRu1PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0 + --oRu1PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0 + --oRu1PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0 + --oRu1PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu1ExtBfwDl0=2,24,0,0,9,1 + --oRu1ExtBfwDl1=2,24,0,0,9,1 + --oRu1nPrbElemUl=2 + --oRu1PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0 + --oRu1PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu1PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0 + --oRu1PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0 + --oRu1PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0 + --oRu1PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0 + --oRu1PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0 + --oRu1PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu1ExtBfwUl0=2,24,0,0,9,1 + --oRu1ExtBfwUl1=2,24,0,0,9,1 + --oRu1nPrbElemSrs=1 + --oRu1PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0 + --oRu2nPrbElemDl=2 + --oRu2PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0 + --oRu2PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu2PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0 + --oRu2PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0 + --oRu2PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0 + --oRu2PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0 + --oRu2PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0 + --oRu2PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu2ExtBfwDl0=2,24,0,0,9,1 + --oRu2ExtBfwDl1=2,24,0,0,9,1 + --oRu2nPrbElemUl=2 + --oRu2PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0 + --oRu2PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0 + --oRu2PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0 + --oRu2PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0 + --oRu2PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0 + --oRu2PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0 + --oRu2PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0 + --oRu2PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0 + --oRu2ExtBfwUl0=2,24,0,0,9,1 + --oRu2ExtBfwUl1=2,24,0,0,9,1 + --oRu2nPrbElemSrs=1 + --oRu2PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0 + + + timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496526035 [Hz] + Ticks per usec 1496 + MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(40), mlogSize(10000) mlog_mask (-1) + mlogSubframes (128), mlogCores(40), mlogSize(10000) + localMLogTimerInit + System clock (rdtsc) resolution 1496525824 [Hz] + Ticks per us 1496 + MLog Storage: 0x7f7403835100 -> 0x7f740690b830 [ 51210032 bytes ] + localMLogFreqReg: 1496. Storing: 1496 + Mlog Open successful + + gnb_io_xran_init + num_o_ru 3 EthLinesNumber 2 where VFs 1 per EthLine + VF[0] 0000:51:01.0 [C+U Plane] + VF[1] 0000:51:01.1 [C+U Plane] + VF[2] 0000:51:01.2 [C+U Plane] + VF[3] 0000:51:01.3 [C+U Plane] + VF[4] 0000:51:01.4 [C+U Plane] + VF[5] 0000:51:01.5 [C+U Plane] + oRu0nPrbElemDl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemDl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemDl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemDl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemDl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemDl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemUl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu0nPrbElemSrs0: oRu0: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + oRu1nPrbElemDl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 0, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu1nPrbElemDl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu1nPrbElemUl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu1nPrbElemUl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu1nPrbElemSrs0: oRu1: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + oRu2nPrbElemDl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu2nPrbElemDl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu2nPrbElemUl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu2nPrbElemUl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1 + oRu2nPrbElemSrs0: oRu2: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0 + gnb_io_xran_cfg_setup successful + xran_init: MTU 9600 + xran_init: MTU 9600 + xran_init: MTU 9600 + PF Eth line speed 25G + PF Eth lines per O-xU port 2 + BBDEV_FEC_ACCL_NR5G + hw-accelerated bbdev 0000:92:00.0 + total cores 48 c_mask 0x3c00004 core 22 [id] system_core 2 [id] pkt_proc_core 0x3800000 [mask] pkt_aux_core 0 [id] timing_core 22 [id] + xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x3c00004 -n2 --iova-mode=pa --socket-mem=18432 --socket-limit=18432 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:92:00.0 + EAL: Detected 48 lcore(s) + EAL: Detected 1 NUMA nodes + EAL: Auto-detected process type: PRIMARY + EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket + EAL: Selected IOVA mode 'PA' + EAL: No available hugepages reported in hugepages-2048kB + EAL: Probing VFIO support... + EAL: PCI device 0000:92:00.0 on NUMA socket 0 + EAL: probe driver: 8086:d8f intel_fpga_5gnr_fec_pf + xran_init_mbuf_pool: socket 0 + EAL: PCI device 0000:51:01.0 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 0 for TX, drv=net_iavf + Port 0 MAC: 00 11 22 33 00 00 + Port 0: nb_rxd 4096 nb_txd 4096 + [0] mempool_rx__0 + [0] mempool_small__0 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [0] ... done + Port 0 Link Up - speed 100000 Mbps - full-duplex + EAL: PCI device 0000:51:01.1 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 1 for TX, drv=net_iavf + Port 1 MAC: 00 11 22 33 00 10 + Port 1: nb_rxd 4096 nb_txd 4096 + [1] mempool_rx__1 + [1] mempool_small__1 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [1] ... done + Port 1 Link Up - speed 100000 Mbps - full-duplex + EAL: PCI device 0000:51:01.2 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 2 for TX, drv=net_iavf + Port 2 MAC: 00 11 22 33 01 00 + Port 2: nb_rxd 4096 nb_txd 4096 + [2] mempool_rx__2 + [2] mempool_small__2 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [2] ... done + Port 2 Link Up - speed 100000 Mbps - full-duplex + EAL: PCI device 0000:51:01.3 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 3 for TX, drv=net_iavf + Port 3 MAC: 00 11 22 33 01 10 + Port 3: nb_rxd 4096 nb_txd 4096 + [3] mempool_rx__3 + [3] mempool_small__3 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [3] ... done + Port 3 Link Up - speed 100000 Mbps - full-duplex + EAL: PCI device 0000:51:01.4 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 4 for TX, drv=net_iavf + Port 4 MAC: 00 11 22 33 02 00 + Port 4: nb_rxd 4096 nb_txd 4096 + [4] mempool_rx__4 + [4] mempool_small__4 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [4] ... done + Port 4 Link Up - speed 100000 Mbps - full-duplex + EAL: PCI device 0000:51:01.5 on NUMA socket 0 + EAL: probe driver: 8086:1889 net_iavf + initializing port 5 for TX, drv=net_iavf + Port 5 MAC: 00 11 22 33 02 10 + Port 5: nb_rxd 4096 nb_txd 4096 + [5] mempool_rx__5 + [5] mempool_small__5 + iavf_init_rss(): RSS is enabled by PF by default + + Checking link status portid [5] ... done + Port 5 Link Up - speed 100000 Mbps - full-duplex + [ 0] vf 0 local SRC MAC: 00 11 22 33 00 00 + [ 0] vf 0 remote DST MAC: 00 11 22 33 00 01 + [ 0] vf 1 local SRC MAC: 00 11 22 33 00 10 + [ 0] vf 1 remote DST MAC: 00 11 22 33 00 11 + [ 1] vf 2 local SRC MAC: 00 11 22 33 01 00 + [ 1] vf 2 remote DST MAC: 00 11 22 33 01 01 + [ 1] vf 3 local SRC MAC: 00 11 22 33 01 10 + [ 1] vf 3 remote DST MAC: 00 11 22 33 01 11 + [ 2] vf 4 local SRC MAC: 00 11 22 33 02 00 + [ 2] vf 4 remote DST MAC: 00 11 22 33 02 01 + [ 2] vf 5 local SRC MAC: 00 11 22 33 02 10 + [ 2] vf 5 remote DST MAC: 00 11 22 33 02 11 + created dl_gen_ring_up_0 + created dl_gen_ring_up_1 + created dl_gen_ring_up_2 + xran_init successful, pHandle = 0x7f7393b23040 + + + bbdev_init: + Socket ID: 0 + FEC is accelerated through BBDEV: 0000:92:00.0 + wls_layer_init[wls0] nWlsMemorySize[1063256064] + wls_lib: Open wls0 (DPDK memzone) + wls_lib: WLS_Open 0x43f600000 + wls_lib: link: 0 <-> 1 + wls_lib: Mode 0 + wls_lib: WLS shared management memzone: wls0 + wls_lib: hugePageSize on the system is 1073741824 + wls_lib: WLS_Alloc [1063256064] bytes + + + =========================================================================================================== + PHY VERSION + =========================================================================================================== + Version: #DIRTY# + IMG-date: Aug 5 2020 + IMG-time: 18:31:18 + =========================================================================================================== + DEPENDENCIES VERSIONS + =========================================================================================================== + FlexRAN BBU pooling version #DIRTY# + FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY# + FlexRAN SDK bblib_layermapping_5gnr version #DIRTY# + FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY# + FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY# + FlexRAN SDK bblib_llr_demapping version #DIRTY# + FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY# + FlexRAN SDK bblib_reed_muller version #DIRTY# + FlexRAN SDK bblib_lte_modulation version #DIRTY# + FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY# + FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY# + FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY# + FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY# + FlexRAN SDK bblib_fd_correlation version #DIRTY# + FlexRAN SDK bblib_scramble_5gnr version #DIRTY# + FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY# + FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY# + FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY# + FlexRAN SDK bblib_prach_5gnr version #DIRTY# + FlexRAN SDK bblib_fft_ifft version #DIRTY# + FlexRAN SDK bblib_pucch_5gnr version #DIRTY# + FlexRAN SDK bblib_lte_crc version #DIRTY# + FlexRAN SDK bblib_common version #DIRTY# + =========================================================================================================== + + =========================================================================================================== + Non BBU threads in application + =========================================================================================================== + nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 29438] binding on [CPU 2] [PRIO: 0] [POLICY: 1] + wls_rx_handler (non-rt): [PID: 29445] binding on [CPU 2] + =========================================================================================================== + + PHY>welcome to application console + + + PHY> + PHY> + PHY>Received MSG_TYPE_PHY_ADD_REMOVE_CORE + Processing MSG_TYPE_PHY_ADD_REMOVE_CORE + phy_bbupool_set_core[0] (add): 137170526192 [0x0000001ff0001ff0] Current: 0 [0x0000000000000000] + nr5g_gnb_mac2phy_api_set_options: PDSCH_SPLIT[4] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: PDSCH_DL_WEIGHT_SPLIT[4] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: PUSCH_CHANEST_SPLIT[2] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: PUSCH_MMSE_SPLIT[4] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: PUSCH_LLR_RX_SPLIT[2] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: PUSCH_UL_WEIGHT_SPLIT[2] nCellMask[0x00000001] + nr5g_gnb_mac2phy_api_set_options: FEC_DEC_NUM_ITER[3] nCellMask[0x00ffffff] + Received MSG_TYPE_PHY_UL_IQ_SAMPLES + Received MSG_TYPE_PHY_UL_IQ_SAMPLES + Received MSG_TYPE_PHY_UL_IQ_SAMPLES + Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0 + phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/376/uliq00_tst376.bin] filename_in_prach_iq[] + Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 1 + phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[1] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[] + Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 2 + phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[2] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[] + Received MSG_TYPE_PHY_CONFIG_REQ: 0 + Received MSG_TYPE_PHY_CONFIG_REQ: 1 + Received MSG_TYPE_PHY_CONFIG_REQ: 2 + Processing MSG_TYPE_PHY_CONFIG_REQ: 0 + phy_bbupool_init: Changing Core Mask0 [0xf0] to [0x1ff0001ff0] + phy_bbupool_set_config: Using cores: 0x0000001ff0001ff0 for BBU Pool nBbuPoolSleepEnable: 1 + BBU Pooling: queueId = 0, the according nCoreNum = 18, the according cpuSetMask = 0x1ff0001ff0 + BBU Pooling: gCoreIdxMap[0] = 4 is available! + BBU Pooling: gCoreIdxMap[1] = 5 is available! + BBU Pooling: gCoreIdxMap[2] = 6 is available! + BBU Pooling: gCoreIdxMap[3] = 7 is available! + BBU Pooling: gCoreIdxMap[4] = 8 is available! + BBU Pooling: gCoreIdxMap[5] = 9 is available! + BBU Pooling: gCoreIdxMap[6] = 10 is available! + BBU Pooling: gCoreIdxMap[7] = 11 is available! + BBU Pooling: gCoreIdxMap[8] = 12 is available! + BBU Pooling: gCoreIdxMap[9] = 28 is available! + BBU Pooling: gCoreIdxMap[10] = 29 is available! + BBU Pooling: gCoreIdxMap[11] = 30 is available! + BBU Pooling: gCoreIdxMap[12] = 31 is available! + BBU Pooling: gCoreIdxMap[13] = 32 is available! + BBU Pooling: gCoreIdxMap[14] = 33 is available! + BBU Pooling: gCoreIdxMap[15] = 34 is available! + BBU Pooling: gCoreIdxMap[16] = 35 is available! + BBU Pooling: gCoreIdxMap[17] = 36 is available! + phy_bbupool_init: Changing SrsCore Mask0 [(nil)] to [0x10000010] + phy_bbupool_init: Changing DlbeamCore Mask0 [(nil)] to [0x7e0] + Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoSrsCoresMask[0x10000010] nTotalSrsCores[2] + Setting aside core[4] for SRS + Setting aside core[28] for SRS + Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoDlbeamCoresMask[0x7e0] nTotalDlbeamCores[6] + Setting aside core[5] for DL beam + Setting aside core[6] for DL beam + Setting aside core[7] for DL beam + Setting aside core[8] for DL beam + Setting aside core[9] for DL beam + Setting aside core[10] for DL beam + BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered + BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered + BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered + BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered + BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered + BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered + BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered + BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered + BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered + BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered + BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered + BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered + BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered + BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered + BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered + BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered + BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered + BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered + BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered + BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered + BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered + BBU Pooling: taskId = 21 taskName = DL_L1_BEAM_WEIGHT_GEN is registered + BBU Pooling: taskId = 22 taskName = DL_L1_BEAM_WEIGHT_TX is registered + BBU Pooling: taskId = 23 taskName = UL_L1_BEAM_WEIGHT_GEN is registered + BBU Pooling: taskId = 24 taskName = UL_L1_BEAM_WEIGHT_TX is registered + BBU Pooling: taskId = 25 taskName = UL_L1_SRS_CE is registered + BBU Pooling: taskId = 26 taskName = UL_L1_SRS_REPORT is registered + BBU Pooling: taskId = 27 taskName = UL_L1_PUSCH_CE0_PRE is registered + BBU Pooling: taskId = 28 taskName = UL_L1_PUSCH_CE7_PRE is registered + BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS + BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A + + BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX + BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST + BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX + BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST + BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST UL_L1_BEAM_WEIGHT_GEN + BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7 + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR + BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR + BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE + BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A + + BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST + BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST + BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST + BBU Pooling: next taskList of UL_L1_SRS: UL_L1_SRS_CE + BBU Pooling: next taskList of DL_L1_POST: N/A + + BBU Pooling: next taskList of UL_L1_POST: N/A + + BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_GEN: DL_L1_BEAM_WEIGHT_TX + BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_TX: DL_L1_POST + BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_GEN: UL_L1_BEAM_WEIGHT_TX + BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_TX: UL_L1_POST + BBU Pooling: next taskList of UL_L1_SRS_CE: UL_L1_SRS_REPORT + BBU Pooling: next taskList of UL_L1_SRS_REPORT: N/A + + BBU Pooling: next taskList of UL_L1_PUSCH_CE0_PRE: UL_L1_PUSCH_CE0 UL_L1_PUSCH_CE7 + BBU Pooling: next taskList of UL_L1_PUSCH_CE7_PRE: UL_L1_PUSCH_CE7 + enter RtThread Launch + Allocated gpThreadWorker[coreIdx: 0][CoreNum: 4]: [0x7f738c000b70] + Allocated gpThreadWorker[coreIdx: 1][CoreNum: 5]: [0x7f738c000e20] + Allocated gpThreadWorker[coreIdx: 2][CoreNum: 6]: [0x7f738c0010d0] + Allocated gpThreadWorker[coreIdx: 3][CoreNum: 7]: [0x7f738c001380] + Allocated gpThreadWorker[coreIdx: 4][CoreNum: 8]: [0x7f738c001630] + Allocated gpThreadWorker[coreIdx: 5][CoreNum: 9]: [0x7f738c0018e0] + launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 0 Queue 0 uCoreIdx 0 CoreId 4 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 3 Queue 0 uCoreIdx 3 CoreId 7 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 6][CoreNum: 10]: [0x7f738c001b90] + launching Thread 4 Queue 0 uCoreIdx 4 CoreId 8 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 5 Queue 0 uCoreIdx 5 CoreId 9 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 7][CoreNum: 11]: [0x7f738c001e40] + Allocated gpThreadWorker[coreIdx: 8][CoreNum: 12]: [0x7f738c0020f0] + bbupool_core_main: the server's coreNum = 48, the nCore = 18,nRtCoreMask = 0x1ff0001ff0, the nFeIfCore = 0,nFeIfCoreMask = 0x0 + bbupool_core_main pthread_setaffinity_np succeed: coreId = 2, result = 0 + Allocated gpThreadWorker[coreIdx: 9][CoreNum: 28]: [0x7f738c0023a0] + launching Thread 6 Queue 0 uCoreIdx 6 CoreId 10 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 10][CoreNum: 29]: [0x7f738c002650] + launching Thread 7 Queue 0 uCoreIdx 7 CoreId 11 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 11][CoreNum: 30]: [0x7f738c002900] + launching Thread 8 Queue 0 uCoreIdx 8 CoreId 12 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 9 Queue 0 uCoreIdx 9 CoreId 28 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 12][CoreNum: 31]: [0x7f738c002bb0] + Allocated gpThreadWorker[coreIdx: 13][CoreNum: 32]: [0x7f738c002e60] + launching Thread 10 Queue 0 uCoreIdx 10 CoreId 29 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 11 Queue 0 uCoreIdx 11 CoreId 30 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 14][CoreNum: 33]: [0x7f738c003110] + Allocated gpThreadWorker[coreIdx: 15][CoreNum: 34]: [0x7f738c0033c0] + launching Thread 12 Queue 0 uCoreIdx 12 CoreId 31 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 16][CoreNum: 35]: [0x7f738c003670] + launching Thread 13 Queue 0 uCoreIdx 13 CoreId 32 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + Allocated gpThreadWorker[coreIdx: 17][CoreNum: 36]: [0x7f738c003920] + 18 thread associated with queue 0:coreIdx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 + Leave RtThread Launch + launching Thread 14 Queue 0 uCoreIdx 14 CoreId 33 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 15 Queue 0 uCoreIdx 15 CoreId 34 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 16 Queue 0 uCoreIdx 16 CoreId 35 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + launching Thread 17 Queue 0 uCoreIdx 17 CoreId 36 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1 + + nr5g_gnb_mac2phy_api_proc_print_phy_init [0]: + nCarrierIdx: 0 + nDMRSTypeAPos: 2 + nPhyCellId: 50 + nDLAbsFrePointA: 3500000 + nULAbsFrePointA: 3500000 + nDLBandwidth: 100 + nULBandwidth: 100 + nDLFftSize: 4096 + nULFftSize: 4096 + nSSBPwr: 0 + nSSBAbsFre: 0 + nSSBPeriod: 4 + nSSBSubcSpacing: 1 + nSSBSubcOffset: 0 + nSSBPrbOffset: 0 + nMIB[0]: 255 + nMIB[1]: 255 + nMIB[2]: 255 + nDLK0: 0 + nULK0: 0 + nSSBMask[0]: 0 + nSSBMask[1]: 0 + nNrOfTxAnt: 64 + nNrOfRxAnt: 64 + nNrOfDLPorts: 16 + nNrOfULPorts: 8 + nCarrierAggregationLevel: 2 + nFrameDuplexType: 1 + nSubcCommon: 1 + nTddPeriod: 10 (TDD) + SlotConfig: + Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13 + 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + + nPrachConfIdx: 100 + nPrachSubcSpacing: 1 + nPrachZeroCorrConf: 1 + nPrachRestrictSet: 0 + nPrachRootSeqIdx: 0 + nPrachFreqStart: 100 + nPrachFdm: 1 + nPrachSsbRach: 0 + nPrachNrofRxRU: 4 + nCyclicPrefix: 0 + nGroupHopFlag: 0 + nSequenceHopFlag: 0 + nHoppingId: 0 + nUrllcCapable: 0 + nUrllcMiniSlotMask: 1 (0x00000001) + read_table: File table/common/pss_table.bin of size 381 read_size: 381 + read_table: File table/common/sss_table.bin of size 128016 read_size: 128016 + read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916 + read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040 + read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216 + read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216 + BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480 + set_slot_type SlotPattern: + Slot: 0 1 2 3 4 5 6 7 8 9 + 0 DL DL DL SP UL DL DL DL SP UL + + PHYDI-INIT[from 2] PhyInstance: 0 + Processing MSG_TYPE_PHY_CONFIG_REQ: 1 + nr5g_gnb_mac2phy_api_proc_print_phy_init [1]: + nCarrierIdx: 1 + nDMRSTypeAPos: 2 + nPhyCellId: 50 + nDLAbsFrePointA: 3500000 + nULAbsFrePointA: 3500000 + nDLBandwidth: 100 + nULBandwidth: 100 + nDLFftSize: 4096 + nULFftSize: 4096 + nSSBPwr: 0 + nSSBAbsFre: 0 + nSSBPeriod: 4 + nSSBSubcSpacing: 1 + nSSBSubcOffset: 0 + nSSBPrbOffset: 0 + nMIB[0]: 255 + nMIB[1]: 255 + nMIB[2]: 255 + nDLK0: 0 + nULK0: 0 + nSSBMask[0]: 0 + nSSBMask[1]: 0 + nNrOfTxAnt: 64 + nNrOfRxAnt: 64 + nNrOfDLPorts: 16 + nNrOfULPorts: 8 + nCarrierAggregationLevel: 2 + nFrameDuplexType: 1 + nSubcCommon: 1 + nTddPeriod: 10 (TDD) + SlotConfig: + Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13 + 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + + nPrachConfIdx: 100 + nPrachSubcSpacing: 1 + nPrachZeroCorrConf: 1 + nPrachRestrictSet: 0 + nPrachRootSeqIdx: 0 + nPrachFreqStart: 100 + nPrachFdm: 1 + nPrachSsbRach: 0 + nPrachNrofRxRU: 4 + nCyclicPrefix: 0 + nGroupHopFlag: 0 + nSequenceHopFlag: 0 + nHoppingId: 0 + nUrllcCapable: 0 + nUrllcMiniSlotMask: 1 (0x00000001) + BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480 + set_slot_type SlotPattern: + Slot: 0 1 2 3 4 5 6 7 8 9 + 0 DL DL DL SP UL DL DL DL SP UL + + PHYDI-INIT[from 2] PhyInstance: 1 + Processing MSG_TYPE_PHY_CONFIG_REQ: 2 + nr5g_gnb_mac2phy_api_proc_print_phy_init [2]: + nCarrierIdx: 2 + nDMRSTypeAPos: 2 + nPhyCellId: 50 + nDLAbsFrePointA: 3500000 + nULAbsFrePointA: 3500000 + nDLBandwidth: 100 + nULBandwidth: 100 + nDLFftSize: 4096 + nULFftSize: 4096 + nSSBPwr: 0 + nSSBAbsFre: 0 + nSSBPeriod: 4 + nSSBSubcSpacing: 1 + nSSBSubcOffset: 0 + nSSBPrbOffset: 0 + nMIB[0]: 255 + nMIB[1]: 255 + nMIB[2]: 255 + nDLK0: 0 + nULK0: 0 + nSSBMask[0]: 0 + nSSBMask[1]: 0 + nNrOfTxAnt: 64 + nNrOfRxAnt: 64 + nNrOfDLPorts: 16 + nNrOfULPorts: 8 + nCarrierAggregationLevel: 2 + nFrameDuplexType: 1 + nSubcCommon: 1 + nTddPeriod: 10 (TDD) + SlotConfig: + Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13 + 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL + 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL + 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL + + nPrachConfIdx: 100 + nPrachSubcSpacing: 1 + nPrachZeroCorrConf: 1 + nPrachRestrictSet: 0 + nPrachRootSeqIdx: 0 + nPrachFreqStart: 100 + nPrachFdm: 1 + nPrachSsbRach: 0 + nPrachNrofRxRU: 4 + nCyclicPrefix: 0 + nGroupHopFlag: 0 + nSequenceHopFlag: 0 + nHoppingId: 0 + nUrllcCapable: 0 + nUrllcMiniSlotMask: 1 (0x00000001) + BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480 + set_slot_type SlotPattern: + Slot: 0 1 2 3 4 5 6 7 8 9 + 0 DL DL DL SP UL DL DL DL SP UL + + PHYDI-INIT[from 2] PhyInstance: 2 + + --------------------------------------------------------- + Global Variables: + --------------------------------------------------------- + gCarrierAggLevel: 3 + gCarrierAggLevelInit: 3 + gSupportedAVX2 1 + --------------------------------------------------------- + + Received MSG_TYPE_PHY_START_REQ: 0 + Received MSG_TYPE_PHY_START_REQ: 1 + Received MSG_TYPE_PHY_START_REQ: 2 + Processing MSG_TYPE_PHY_START_REQ: 0 + di_open port 0 + + xran_init_vfs_mapping: p 0 vf 0 + xran_init_vfs_mapping: p 0 vf 1 + XRAN_UP_VF: 0x0000 + xran_timing_source_thread [CPU 22] [PID: 29437] + xran_open [CPU 2] [PID: 29437] + Waithing on Timing thread... + TTI interval 500 [us] + Start C-plane DL 71 us after TTI [trigger on sym 2] + Start C-plane UL 200 us after TTI [trigger on sym 6] + Start U-plane DL 196 us before OTA [offset in sym -5] + Start U-plane UL 75 us OTA [offset in sym 3] + C-plane to U-plane delay 125 us after TTI + Start Sym timer 35714 ns + di_open port 1 + + xran_init_vfs_mapping: p 1 vf 2 + xran_init_vfs_mapping: p 1 vf 3 + Start C-plane DL 71 us after TTI [trigger on sym 2] + Start C-plane UL 200 us after TTI [trigger on sym 6] + Start U-plane DL 196 us before OTA [offset in sym -5] + Start U-plane UL 75 us OTA [offset in sym 3] + C-plane to U-plane delay 125 us after TTI + Start Sym timer 35714 ns + xran_open [CPU 2] [PID: 29437] + Waithing on Timing thread... + di_open port 2 + + xran_init_vfs_mapping: p 2 vf 4 + xran_init_vfs_mapping: p 2 vf 5 + Start C-plane DL 71 us after TTI [trigger on sym 2] + Start C-plane UL 200 us after TTI [trigger on sym 6] + Start U-plane DL 196 us before OTA [offset in sym -5] + Start U-plane UL 75 us OTA [offset in sym 3] + C-plane to U-plane delay 125 us after TTI + Start Sym timer 35714 ns + O-XU 0 + HW 1 + Num cores 4 + Num ports 3 + O-RU Cat 1 + O-RU CC 3 + O-RU eAxC 16 + p:0 XRAN_JOB_TYPE_CP_DL worker id 1 + p:0 XRAN_JOB_TYPE_CP_UL worker id 1 + p:1 XRAN_JOB_TYPE_CP_DL worker id 1 + p:1 XRAN_JOB_TYPE_CP_UL worker id 1 + p:2 XRAN_JOB_TYPE_CP_DL worker id 1 + p:2 XRAN_JOB_TYPE_CP_UL worker id 1 + p:1 XRAN_JOB_TYPE_CP_DL worker id 2 + p:1 XRAN_JOB_TYPE_CP_UL worker id 2 + p:2 XRAN_JOB_TYPE_CP_DL worker id 2 + p:2 XRAN_JOB_TYPE_CP_UL worker id 2 + xran_generic_worker_thread [CPU 23] [PID: 29437] + spawn worker 0 core 23 + xran_generic_worker_thread [CPU 24] [PID: 29437] + spawn worker 1 core 24 + xran_generic_worker_thread [CPU 25] [PID: 29437] + spawn worker 2 core 25 + xran_open [CPU 2] [PID: 29437] + Waithing on Timing thread... + ---------------------------------------------------------------------------- + mem_mgr_display_size: + Num Memory Alloc: 38,294 + Total Memory Size: 20,049,968,118 + ---------------------------------------------------------------------------- + + + PHYDI-START[from 2] PhyInstance: 0, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20 + PHYDI-START[from 2] PhyInstance: 1, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20 + PHYDI-START[from 2] PhyInstance: 2, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20 + Setting nMultiCellModeDelay: 40000 + nr5g_gnb_urllc_register_call_backs: nTimerMode[0] nUrllcMiniSlotMask[0] + port [0] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8] + port 0 has 1 CCs + port 0 cc_id 0 is phy id 0 + XRAN front haul xran_mm_init + xran_sector_get_instances [0]: CC 0 handle 0x7f6fe7383280 + Handle: 0xee1c8e0 Instance: 0x7f6fe7383280 + gnb_io_xran_start [0]: CC 0 handle 0x7f6fe7383280 + Sucess xran_mm_init Instance 0x7f6fe7383280 + nSectorNum 1 + ru_0_cc_0_idx_0: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x44c493480 + ru_0_cc_0_idx_1: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x444381640 + ru_0_cc_0_idx_2: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x443dff2c0 + ru_0_cc_0_idx_3: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x443c5cf40 + ru_0_cc_0_idx_4: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x443ababc0 + ru_0_cc_0_idx_5: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x443538840 + ru_0_cc_0_idx_6: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x4433964c0 + ru_0_cc_0_idx_7: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 7] mb pool 0x4431f4140 + ru_0_cc_0_idx_8: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 8] mb pool 0x442ff1dc0 + ru_0_cc_0_idx_9: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560 + CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 9] mb pool 0x441e6fa40 + port [0] gnb_io_xran_init_cp + port [0] init xran successfully + port [1] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8] + port 1 has 1 CCs + port 1 cc_id 0 is phy id 1 + XRAN front haul xran_mm_init + xran_sector_get_instances [1]: CC 0 handle 0x7f6fe7383380 + Handle: 0xee1c940 Instance: 0x7f6fe7383380 + gnb_io_xran_start [1]: CC 0 handle 0x7f6fe7383380 + Sucess xran_mm_init Instance 0x7f6fe7383280 + nSectorNum 1 + ru_1_cc_0_idx_0: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2a1525740 + ru_1_cc_0_idx_1: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 1] mb pool 0x299413900 + ru_1_cc_0_idx_2: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 2] mb pool 0x28f1112c0 + ru_1_cc_0_idx_3: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 3] mb pool 0x287f4fb80 + ru_1_cc_0_idx_4: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 4] mb pool 0x27fe3dd40 + ru_1_cc_0_idx_5: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 5] mb pool 0x275b3b700 + ru_1_cc_0_idx_6: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 6] mb pool 0x26e979fc0 + ru_1_cc_0_idx_7: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 7] mb pool 0x269ce9980 + ru_1_cc_0_idx_8: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32 + O-DU: thread_run start time: 08/11/20 23:05:24.000000001 UTC [500] + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 8] mb pool 0x249d33b40 + ru_1_cc_0_idx_9: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560 + CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 9] mb pool 0x2215b1500 + port [1] gnb_io_xran_init_cp + port [1] init xran successfully + port [2] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8] + port 2 has 1 CCs + port 2 cc_id 0 is phy id 2 + XRAN front haul xran_mm_init + xran_sector_get_instances [2]: CC 0 handle 0x7f6fe7383440 + Handle: 0xee1c9a0 Instance: 0x7f6fe7383440 + gnb_io_xran_start [2]: CC 0 handle 0x7f6fe7383440 + Sucess xran_mm_init Instance 0x7f6fe7383280 + nSectorNum 1 + ru_2_cc_0_idx_0: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 0] mb pool 0x203b7bdc0 + ru_2_cc_0_idx_1: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 1] mb pool 0x1fba69f80 + ru_2_cc_0_idx_2: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 2] mb pool 0x1f1767940 + ru_2_cc_0_idx_3: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 3] mb pool 0x1ea5a6200 + ru_2_cc_0_idx_4: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 4] mb pool 0x1e24943c0 + ru_2_cc_0_idx_5: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 5] mb pool 0x1d8191d80 + ru_2_cc_0_idx_6: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 6] mb pool 0x1d0fd0640 + ru_2_cc_0_idx_7: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 7] mb pool 0x1cc340000 + ru_2_cc_0_idx_8: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 8] mb pool 0x1ac38a1c0 + ru_2_cc_0_idx_9: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560 + CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 9] mb pool 0x183c07b80 + port [2] gnb_io_xran_init_cp + port [2] init xran successfully + O-DU: XRAN start time: 08/11/20 23:05:24.384220762 UTC [500] + BBU Pooling: enter multicell Activate! + BBU Pooling Info: bbupool rt thread start on CoreIdx 14 coreId 33 at 118352443946329 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 118352443939667 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 11 coreId 30 at 118352443942535 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 8 coreId 12 at 118352443944575 at sf=0 with queue 0 successfully + BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 3 + BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 118352443929961 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 15 coreId 34 at 118352443933301 at sf=0 with queue 0 successfully + BBU Pooling: multiCell Activate sucessfully! + BBU Pooling Info: bbupool rt thread start on CoreIdx 13 coreId 32 at 118352443935245 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 4 coreId 8 at 118352443936745 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 6 coreId 10 at 118352443936883 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 3 coreId 7 at 118352443936747 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 12 coreId 31 at 118352443938019 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 5 coreId 9 at 118352443939937 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 9 coreId 28 at 118352443941217 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 16 coreId 35 at 118352443944465 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 17 coreId 36 at 118352443937701 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 4 at 118352443926969 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 10 coreId 29 at 118352443928691 at sf=0 with queue 0 successfully + BBU Pooling Info: bbupool rt thread start on CoreIdx 7 coreId 11 at 118352443931713 at sf=0 with queue 0 successfully + phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[20] + ==== l1app Time: 5002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces + ==== [o-du0][rx 3807776 pps 761555 kbps 4744396][tx 10937607 pps 2187521 kbps 26031486] [on_time 3807776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3807776] + Pusch[ 439372 439372 439372 439372 439372 439372 439372 439372] SRS[ 292800] + ==== [o-du1][rx 1469469 pps 293893 kbps 2684928][tx 3649817 pps 729963 kbps 9156812] [on_time 1469469 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469469] + Pusch[ 146964 146956 146964 146956 146964 146956 146964 146956] SRS[ 293788] + ==== [o-du2][rx 1469463 pps 293892 kbps 2684960][tx 3648883 pps 729776 kbps 9152795] [on_time 1469463 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469463] + Pusch[ 146956 146956 146956 146956 146956 146956 146956 146956] SRS[ 293815] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 0 0 / 0 0.00% + 1 (Kbps) 0 0 / 0 0.00% + 2 (Kbps) 0 0 / 0 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 0 4 2 4 4 2 3 13 17 0 13 15 14 16 14 17 15 14 9.28 + Xran Id: 22 23 24 25 Master Core Util: 85 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 10002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces + ==== [o-du0][rx 5472406 pps 332926 kbps 4744396][tx 21871698 pps 2186818 kbps 26038405] [on_time 5472406 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5472406] + Pusch[ 192084 192078 192078 192078 192078 192078 192078 192078] SRS[ 128000] + ==== [o-du1][rx 2109680 pps 128042 kbps 2684917][tx 7297930 pps 729622 kbps 9156922] [on_time 2109680 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109680] + Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128004] + ==== [o-du2][rx 2109682 pps 128043 kbps 2684993][tx 7296833 pps 729590 kbps 9156258] [on_time 2109682 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109682] + Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128011] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,894,368 576,420 / 576,492 0.00% + 1 (Kbps) 0 0 / 0 0.00% + 2 (Kbps) 0 0 / 0 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 15 30 34 29 26 28 26 46 50 0 40 40 43 42 44 42 48 50 35.17 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 15003 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces + ==== [o-du0][rx 7136544 pps 332827 kbps 4744396][tx 32806663 pps 2186993 kbps 26042173] [on_time 7136544 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7136544] + Pusch[ 192012 192018 192018 192018 192018 192018 192018 192018] SRS[ 128000] + ==== [o-du1][rx 2749728 pps 128009 kbps 2684895][tx 10945622 pps 729538 kbps 9155645] [on_time 2749728 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749728] + Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000] + ==== [o-du2][rx 2749730 pps 128009 kbps 2684840][tx 10944272 pps 729487 kbps 9154660] [on_time 2749730 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749730] + Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,780 / 576,780 0.00% + 1 (Kbps) 539,740 65,260 / 65,260 0.00% + 2 (Kbps) 0 0 / 0 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 27 33 40 38 38 35 34 56 56 26 50 47 48 47 51 48 57 57 43.78 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Setting MLogMask because nMLogDelay == 0 + ==== l1app Time: 20002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [480.00..500.23..516.00] usces + ==== [o-du0][rx 8799776 pps 332646 kbps 4744396][tx 43740623 pps 2186792 kbps 26042944] [on_time 8799776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 8799776] + Pusch[ 191904 191904 191904 191904 191904 191904 191904 191904] SRS[ 128000] + ==== [o-du1][rx 3389472 pps 127948 kbps 2684982][tx 14591619 pps 729199 kbps 9154093] [on_time 3389472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389472] + Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000] + ==== [o-du2][rx 3389474 pps 127948 kbps 2684873][tx 14589997 pps 729145 kbps 9152608] [on_time 3389474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389474] + Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,780 / 576,780 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 43 47 46 43 42 43 41 61 60 27 57 56 58 57 55 56 64 62 51.00 + Xran Id: 22 23 24 25 Master Core Util: 96 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 25002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [442.00..500.12..562.00] usces + ==== [o-du0][rx 10463824 pps 332809 kbps 4744396][tx 54675513 pps 2186978 kbps 26044150] [on_time 10463824 early 0 late 0 corrupt 0 pkt_dupl 144 Total 10463824] + Pusch[ 192006 192006 192006 192006 192006 192006 192006 192006] SRS[ 128000] + ==== [o-du1][rx 4029487 pps 128003 kbps 2684928][tx 18237287 pps 729133 kbps 9150163] [on_time 4029487 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029487] + Pusch[ 64002 64002 64002 64002 64002 64002 64002 64001] SRS[ 128000] + ==== [o-du2][rx 4029474 pps 128000 kbps 2684873][tx 18235338 pps 729068 kbps 9148513] [on_time 4029474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029474] + Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,492 / 576,492 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 44 48 46 46 44 41 43 62 61 27 58 59 55 56 56 58 61 62 51.50 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 30002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [435.00..500.12..562.00] usces + ==== [o-du0][rx 12127888 pps 332812 kbps 4744396][tx 65610457 pps 2186988 kbps 26044065] [on_time 12127888 early 0 late 0 corrupt 0 pkt_dupl 144 Total 12127888] + Pusch[ 192012 192006 192012 192006 192010 192006 192006 192006] SRS[ 128000] + ==== [o-du1][rx 4669504 pps 128003 kbps 2685058][tx 21883550 pps 729252 kbps 9152750] [on_time 4669504 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669504] + Pusch[ 64002 64002 64002 64002 64002 64002 64002 64003] SRS[ 128000] + ==== [o-du2][rx 4669498 pps 128004 kbps 2684993][tx 21881293 pps 729191 kbps 9151846] [on_time 4669498 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669498] + Pusch[ 64004 64004 64004 64004 64002 64002 64002 64002] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 577,069 / 577,069 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 44 47 45 47 43 43 42 63 63 27 56 56 56 55 58 55 65 62 51.50 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 35002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [434.00..500.12..554.00] usces + ==== [o-du0][rx 13792256 pps 332873 kbps 4744892][tx 76545521 pps 2187012 kbps 26042901] [on_time 13792256 early 0 late 0 corrupt 0 pkt_dupl 144 Total 13792256] + Pusch[ 192042 192048 192042 192048 192044 192048 192048 192048] SRS[ 128000] + ==== [o-du1][rx 5309632 pps 128025 kbps 2685102][tx 25528867 pps 729063 kbps 9151639] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632] + Pusch[ 64016 64016 64016 64016 64016 64016 64016 64016] SRS[ 128000] + ==== [o-du2][rx 5309632 pps 128026 kbps 2685102][tx 25526238 pps 728989 kbps 9150147] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632] + Pusch[ 64016 64016 64016 64016 64018 64018 64017 64017] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,780 / 576,780 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 43 48 45 47 43 41 42 66 61 27 57 57 55 56 57 56 64 62 51.50 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 40002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [440.00..500.12..553.00] usces + ==== [o-du0][rx 15455740 pps 332696 kbps 4744396][tx 87479892 pps 2186874 kbps 26042995] [on_time 15455740 early 0 late 0 corrupt 0 pkt_dupl 144 Total 15455740] + Pusch[ 191940 191940 191940 191940 191940 191940 191940 191940] SRS[ 127964] + ==== [o-du1][rx 5949408 pps 127955 kbps 2684764][tx 29174424 pps 729111 kbps 9150009] [on_time 5949408 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949408] + Pusch[ 63980 63980 63980 63980 63980 63980 63980 63980] SRS[ 127936] + ==== [o-du2][rx 5949410 pps 127955 kbps 2684840][tx 29171380 pps 729028 kbps 9148386] [on_time 5949410 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949410] + Pusch[ 63980 63980 63980 63980 63980 63980 63981 63981] SRS[ 127936] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,780 / 576,780 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 44 48 44 45 42 42 43 63 63 27 57 56 55 58 56 56 64 62 51.39 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 45002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..556.00] usces + ==== [o-du0][rx 17119776 pps 332807 kbps 4743900][tx 98415119 pps 2187045 kbps 26043843] [on_time 17119776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 17119776] + Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128036] + ==== [o-du1][rx 6589472 pps 128012 kbps 2684753][tx 32820214 pps 729158 kbps 9154170] [on_time 6589472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589472] + Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064] + ==== [o-du2][rx 6589474 pps 128012 kbps 2684753][tx 32816780 pps 729080 kbps 9152613] [on_time 6589474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589474] + Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,780 / 576,780 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 44 47 46 47 43 42 42 61 63 27 56 58 56 56 58 57 63 65 51.72 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + ==== l1app Time: 50002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..551.00] usces + ==== [o-du0][rx 18783776 pps 332800 kbps 4744396][tx 109350065 pps 2186989 kbps 26043142] [on_time 18783776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 18783776] + Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128000] + ==== [o-du1][rx 7229472 pps 128000 kbps 2684928][tx 36466505 pps 729258 kbps 18302595] [on_time 7229472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229472] + Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000] + ==== [o-du2][rx 7229474 pps 128000 kbps 2684895][tx 36462749 pps 729193 kbps 9148265] [on_time 7229474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229474] + Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000] + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Cell DL Tput UL Tput UL BLER + 0 (Kbps) 6,896,256 576,492 / 576,492 0.00% + 1 (Kbps) 539,814 65,260 / 65,260 0.00% + 2 (Kbps) 539,814 65,260 / 65,260 0.00% + ------------------------------------------------------------------------------------------------------------------------------------------------------- + Core Utilization [18 BBU core(s)]: + Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg + Util %: 43 47 45 47 43 41 41 62 63 27 57 55 57 56 55 57 62 66 51.33 + Xran Id: 22 23 24 25 Master Core Util: 95 % + ------------------------------------------------------------------------------------------------------------------------------------------------------- + +7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter:: + + [root@xran flexran] cd ./bin/nr5g/gnb/testmac + +8. To execute test case type:: + + ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg + +where output corresponding to Test MAC:: + + root@icelake-scs1-1 testmac]# ./l2.sh --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg + kernel.sched_rt_runtime_us = -1 + kernel.shmmax = 2147483648 + kernel.shmall = 2147483648 + Note: Forwarding request to 'systemctl disable irqbalance.service'. + start 5GNR Test MAC + ========================= + 5GNR Testmac Application + ========================= + testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml + + + --------------------------- + TestMacCfg.xml Version: 20.08 + --------------------------- + + --version=20.08 + --wls_dev_name=wls0 + --wlsMemorySize=0x3F600000 + --dpdkIovaMode=0 + --PhyStartMode=1 + --PhyStartPeriod=40 + --PhyStartCount=0 + --MlogSubframes=128 + --MlogCores=3 + --MlogSize=2048 + --latencyTest=0 + --wlsRxThread=1, 90, 0 + --systemThread=0, 0, 0 + --runThread=0, 89, 0 + --urllcThread=16, 90, 0 + + wls_dev_filename: wls0 + sys_reg_signal_handler:[err] signal handler in NULL + sys_reg_signal_handler:[err] signal handler in NULL + timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496523032 [Hz] + Ticks per usec 1496 + MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1) + mlogSubframes (128), mlogCores(3), mlogSize(2048) + localMLogTimerInit + System clock (rdtsc) resolution 1496526140 [Hz] + Ticks per us 1496 + MLog Storage: 0x7f821905d100 -> 0x7f821911d920 [ 788512 bytes ] + localMLogFreqReg: 1496. Storing: 1496 + Mlog Open successful + + Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa + EAL: Detected 48 lcore(s) + EAL: Detected 1 NUMA nodes + EAL: Auto-detected process type: SECONDARY + EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_29473_6b9e031eaf8b + EAL: Selected IOVA mode 'PA' + EAL: Probing VFIO support... + EAL: PCI device 0000:01:00.0 on NUMA socket 0 + EAL: probe driver: 8086:1533 net_e1000_igb + EAL: PCI device 0000:18:00.0 on NUMA socket 0 + EAL: probe driver: 8086:1563 net_ixgbe + EAL: PCI device 0000:18:00.1 on NUMA socket 0 + EAL: probe driver: 8086:1563 net_ixgbe + EAL: PCI device 0000:8c:00.0 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:8c:00.1 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:90:00.0 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + EAL: PCI device 0000:90:00.1 on NUMA socket 0 + EAL: probe driver: 8086:d58 net_i40e + wls_lib: Open wls0 (DPDK memzone) + wls_lib: WLS_Open 0x43f600000 + wls_lib: link: 1 <-> 0 + wls_lib: Mode 1 + wls_lib: WLS shared management memzone: wls0 + wls_lib: hugePageSize on the system is 1073741824 + wls_lib: WLS_Alloc [1063256064] bytes + wls_lib: Connecting to remote peer ... + wls_lib: Connected to remote peer + wls_mac_create_mem_array: pMemArray[0xf354350] pMemArrayMemory[0x400000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056] + WLS_EnqueueBlock [1] + WLS inited ok [383] + + + =========================================================================================================== + TESTMAC VERSION + =========================================================================================================== + + $Version: #DIRTY# $ (x86) + IMG-date: Aug 5 2020 + IMG-time: 18:32:53 + =========================================================================================================== + + + =========================================================================================================== + Testmac threads in application + =========================================================================================================== + testmac_run_thread: [PID: 29477] binding on [CPU 0] [PRIO: 89] [POLICY: 1] + wls_mac_rx_task: [PID: 29476] binding on [CPU 1] [PRIO: 90] [POLICY: 1] + =========================================================================================================== + + testmac_set_phy_start: mode[1], period[40], count[0] + + testmac_run_load_files: + Loading DL Config Files: + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg + Loading UL Config Files: + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_40mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg + Loading FD Config Files: + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg + testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg + + TESTMAC DL TESTS: + Numerology[0] Bandwidth[5] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[0] Bandwidth[10] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[0] Bandwidth[20] + 1001 1002 1003 1004 1005 1006 1007 1008 + Numerology[1] Bandwidth[100] + 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211 + 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 + 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241 + 1242 1243 1244 1245 1250 1251 1252 1260 1261 1262 + 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 + 1300 1301 1302 1303 1304 1305 1402 1404 1408 1416 + 1500 1501 1502 1503 1504 1505 1506 2213 2214 2215 + 2217 2218 2219 2223 2224 2225 2227 2228 2229 2500 + 2501 2502 2503 2504 3213 3214 3215 3217 3218 3219 + 3223 3224 3225 3227 3228 3229 + Numerology[3] Bandwidth[100] + 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011 + 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031 + 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003 + 3030 + + TESTMAC UL TESTS: + Numerology[0] Bandwidth[5] + 1001 1002 1003 1069 1070 1071 1072 1073 1074 1075 + 1076 1077 + Numerology[0] Bandwidth[10] + 1001 1002 1069 1070 1071 1072 1073 1074 1075 1076 + 1077 + Numerology[0] Bandwidth[20] + 1001 1002 1003 1004 1005 1006 1007 1008 1069 1070 + 1071 1072 1073 1074 1075 1076 1077 + Numerology[1] Bandwidth[10] + 1069 1070 1071 1072 1073 1074 1075 1076 1077 + Numerology[1] Bandwidth[20] + 1069 1070 1071 1072 1073 1074 1075 1076 1077 + Numerology[1] Bandwidth[40] + 1069 1070 1071 1072 1073 1074 1075 1076 1077 + Numerology[1] Bandwidth[100] + 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038 + 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074 + 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092 + 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105 + 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117 + 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132 + 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 + 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160 + 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 + 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206 + 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 + 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233 + 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421 + 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 + 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504 + 1505 1506 1507 1508 1512 1513 1514 1515 1516 1540 + 1541 1542 1563 1564 1565 1566 1567 1568 1569 1570 + 1571 1572 1573 1574 1575 1576 1577 1600 1601 1602 + 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 + 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 + 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 + 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 + 1700 1701 1702 1969 1970 1971 1972 1973 1974 1975 + 1976 1977 2236 2237 3236 3237 + Numerology[3] Bandwidth[100] + 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012 + 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026 + 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 + 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051 + 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065 + 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084 + 1085 1086 2001 2002 2003 3001 3002 3003 + + TESTMAC FD TESTS: + Numerology[0] Bandwidth[5] + 1001 6001 8001 10001 12001 + Numerology[0] Bandwidth[10] + 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002 + 6002 8002 10002 12002 1003 + Numerology[0] Bandwidth[20] + 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021 + 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201 + 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221 + 1222 1223 1224 1225 1226 1227 1228 + Numerology[1] Bandwidth[40] + 1001 1002 1003 + Numerology[1] Bandwidth[100] + 1001 1002 1200 1201 1202 1203 1204 1205 1206 1207 + 1208 1209 1210 1300 1301 1302 1303 1304 1305 1306 + 1307 1308 1350 1351 1352 1353 1354 1355 1356 1357 + 1358 1359 1370 1371 1372 1373 1374 1375 1376 1377 + 1378 1401 1402 1403 1404 1405 1406 1411 1412 1490 + 1494 1500 1501 1502 1503 1504 1510 1511 1512 1513 + 1514 1515 1520 1521 1522 1523 1524 1525 1526 1527 + 1528 1529 1530 1531 1532 1540 1541 1700 1701 1702 + 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 + 2530 2531 2532 3524 3525 3526 3527 3528 3529 3530 + 3531 3532 4524 4525 4526 4527 4528 4529 4530 4531 + 4532 + Numerology[3] Bandwidth[100] + 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011 + 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080 + 1081 1082 2001 3001 + testmac_run_parse_file Parsing config file: ./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg + testmac_set_phy_start: mode[4], period[0], count[100200] + Adding setoption pdsch_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104] + Adding setoption pdsch_dl_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104] + Adding setoption pusch_chan_est_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102] + Adding setoption pusch_mmse_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104] + Adding setoption pusch_llr_rx_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102] + Adding setoption pusch_ul_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102] + Adding setoption timer_multi_cell [numTests: 0] [nCellMask: 0xffffffff] [nOption: 10000] [pMacOptions: 10000 / 0x00002710] + Adding setoption fec_dec_num_iter [numTests: 0] [nCellMask: 0xffffffff] [nOption: 3] [pMacOptions: -253 / 0xffffff03] + Adding SetCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[137170526192 / 0x0000001ff0001ff0] + Adding SetDlbeamCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[2016 / 0x00000000000007e0] + Adding SetSrsCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[268435472 / 0x0000000010000010] + Setting Testmac System Core: 2 + Setting Testmac Run Core: 2 + Setting Testmac Wls Core: 3 + Adding Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ + Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg + Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg + Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg + + testmac_set_multi_cell_timer: 10000 + + + + + ---------------------------------------------------------------------------------------- + Running Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ + Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg + Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg + Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg + TESTMAC>welcome to application console + + MLogRestart + MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1) + mlogSubframes (128), mlogCores(3), mlogSize(2048) + localMLogTimerInit + System clock (rdtsc) resolution 1496525908 [Hz] + Ticks per us 1496 + MLog Storage: 0x7f8208000900 -> 0x7f82080c1120 [ 788512 bytes ] + localMLogFreqReg: 1496. Storing: 1496 + Mlog Open successful + + testmac_mac2phy_set_num_cells: Setting Max Cells: 3 + testmac_config_parse: test_num[3370] test_type[2] numcarrier[3] + Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0) + Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(1) + Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(2) + Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0) + Queueing MSG_TYPE_PHY_CONFIG_REQ(0) + Received MSG_TYPE_PHY_UL_IQ_SAMPLES(1) + Queueing MSG_TYPE_PHY_CONFIG_REQ(1) + Received MSG_TYPE_PHY_UL_IQ_SAMPLES(2) + Queueing MSG_TYPE_PHY_CONFIG_REQ(2) and sending list + Received MSG_TYPE_PHY_CONFIG_RESP(0) + Queueing MSG_TYPE_PHY_START_REQ(0) + Received MSG_TYPE_PHY_CONFIG_RESP(1) + Queueing MSG_TYPE_PHY_START_REQ(1) + Received MSG_TYPE_PHY_CONFIG_RESP(2) + Queueing MSG_TYPE_PHY_START_REQ(2) and sending list + Received MSG_TYPE_PHY_START_RESP(0) + Received MSG_TYPE_PHY_START_RESP(1) + Received MSG_TYPE_PHY_START_RESP(2) + ==== testmac Time: 5000 ms NumCarrier: 3 Total Proc Time: [ 0.00.. 6.30.. 19.00] usces==== + Core Utilization [Core: 3] [Util %: 0.42%] + ==== testmac Time: 10000 ms NumCarrier: 3 Total Proc Time: [ 6.00..116.80..206.00] usces==== + Core Utilization [Core: 3] [Util %: 27.86%] + ==== testmac Time: 20000 ms NumCarrier: 3 Total Proc Time: [ 10.00..156.33..260.00] usces==== + Core Utilization [Core: 3] [Util %: 32.31%] + ==== testmac Time: 25000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.33..260.00] usces==== + Core Utilization [Core: 3] [Util %: 32.30%] + ==== testmac Time: 30000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.44..256.00] usces==== + Core Utilization [Core: 3] [Util %: 32.32%] + ==== testmac Time: 35000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.42..258.00] usces==== + Core Utilization [Core: 3] [Util %: 32.32%] + ==== testmac Time: 40000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.45..258.00] usces==== + Core Utilization [Core: 3] [Util %: 32.33%] + ==== testmac Time: 45000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.40..282.00] usces==== + Core Utilization [Core: 3] [Util %: 32.32%] + + TESTMAC>==== testmac Time: 50000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.39..260.00] usces==== + Core Utilization [Core: 3] [Util %: 32.31%] + Received MSG_TYPE_PHY_STOP_RESP(0) + Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(0) + Received MSG_TYPE_PHY_STOP_RESP(1) + Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(1) + Received MSG_TYPE_PHY_STOP_RESP(2) + Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(2) and sending list + Received MSG_TYPE_PHY_SHUTDOWN_RESP(2) + Received MSG_TYPE_PHY_SHUTDOWN_RESP(0) + Received MSG_TYPE_PHY_SHUTDOWN_RESP(1) + MLogPrint: ext_filename((null).bin) + Opening MLog File: testmac-mlog-c0.bin + MLog file testmac-mlog-c0.bin closed + Mlog Print successful + Test[FD_mu1_100mhz_3370] Completed + wls_mac_free_list_all: + nTotalBlocks[4056] nAllocBlocks[1010] nFreeBlocks[3046] + nTotalAllocCnt[4538427] nTotalFreeCnt[4537417] Diff[1010] + nDlBufAllocCnt[3609068] nDlBufFreeCnt[3609068] Diff[0] + nUlBufAllocCnt[929359] nUlBufFreeCnt[928349] Diff[1010] + + All Tests Completed, Total run 1 Tests, PASS 1 Tests, and FAIL 0 Tests diff --git a/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst b/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst index 1a64844..67c8159 100644 --- a/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst +++ b/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -16,14 +16,14 @@
-Transport Layer and ORAN Fronthaul Protocol Implementation -========================================================== +Transport Layer and O-RAN Fronthaul Protocol Implementation +=========================================================== .. contents:: :depth: 3 :local: -This chapter describes how the transport layer and ORAN Fronthaul +This chapter describes how the transport layer and O-RAN Fronthaul protocol are implemented. .. _introduction-2: @@ -31,29 +31,29 @@ protocol are implemented. Introduction ------------ -Figure 8 presents an overview of the ORAN Fronthaul process. +Figure 8 presents an overview of the O-RAN Fronthaul process. .. image:: images/ORAN-Fronthaul-Process.jpg :width: 600 - :alt: Figure 8. ORAN Fronthaul Process + :alt: Figure 8. O-RAN Fronthaul Process -Figure 8. ORAN Fronthaul Process +Figure 8. O-RAN Fronthaul Process -The XRAN library provides support for transporting In-band and -Quadrature (IQ) samples between the O-DU and O-RU within the xRAN +The O-RAN library provides support for transporting In-band and +Quadrature (IQ) samples between the O-DU and O-RU within the O-RAN architecture based on functional split 7.2x. The library defines the -xRAN packet formats to be used to transport radio samples within Front -Haul according to the ORAN Fronthaul specification. It provides -functionality for generating xRAN packets, appending IQ samples in the -packet payload, and extracting IQ samples from xRAN packets. +O-RAN packet formats to be used to transport radio samples within Front +Haul according to the O-RAN Fronthaul specification. It provides +functionality for generating O-RAN packets, appending IQ samples in the +packet payload, and extracting IQ samples from O-RAN packets. -Note: The Bronze release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment. +Note: The E Miantenance release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment. Note: Regarding the clock model and synchronization topology, configurations C1 and C3 of the connection between O-DU and O-RU are the only -configurations supported in this release of the xRAN implementation. +configurations supported in this release of the O-RAN implementation. -Note: Quality of PTP synchronization with respect to S-plane of ORAN +Note: Quality of PTP synchronization with respect to S-plane of O-RAN Fronthaul requirements as defined for O-RU is out of the scope of this document. PTP primary and PTP secondary configuration are expected to satisfy only the O-DU side of requirements and provide the “best-effort” PTP primary for @@ -79,14 +79,14 @@ Figure 10. Configuration C3 Supported Feature Set --------------------- -The ORAN Fronthaul specification defines a list of mandatory +The O-RAN Fronthaul specification defines a list of mandatory functionality. Not all features defined as Mandatory for O-DU are currently supported to fully extended. The following tables contain information on what is available and the level of validation performed for this release. Note. Cells with a red background are listed as mandatory in the -specification but not supported in this implementation of xRAN. +specification but not supported in this implementation of O-RAN. Table 7. ORAN Mandatory and Optional Feature Support @@ -94,1049 +94,1164 @@ Table 7. ORAN Mandatory and Optional Feature Support | Category | Feature | O-DU | Support | | | | Support | | +=================+=================+===========+================+ -| RU Category | Support for | Mandatory | Y | -| | CAT-A RU (up to | | | -| | 8 spatial | | | -| | streams) | | | -+-----------------+-----------------+-----------+----------------+ -| | Support for |   | Y | -| | CAT-A RU (> 8 | | | -| | spatial | | | -| | streams) | | | -+-----------------+-----------------+-----------+----------------+ -| | Support for | Mandatory | Y | -| | CAT-B RU | | | -| | (precoding in | | | -| | RU) | | | -+-----------------+-----------------+-----------+----------------+ -| Beamforming | Beam Index | Mandatory | Y | -| | based | | | -+-----------------+-----------------+-----------+----------------+ -| | Real-time BF | Mandatory | Y | -| | Weights | | | -+-----------------+-----------------+-----------+----------------+ -| | Real-Time |   | N | -| | Beamforming | | | -| | Attributes | | | +| RU Category || Support for | Mandatory | Y | +| || CAT-A RU (up to| | | +| || 8 spatial | | | +| || streams) | | | +| +-----------------+-----------+----------------+ +| || Support for | | Y | +| || CAT-A RU (> 8 | | | +| || spatial | | | +| || streams) | | | +| +-----------------+-----------+----------------+ +| || Support for | Mandatory | Y | +| || CAT-B RU | | | +| || (precoding in | | | +| || RU) | | | +-----------------+-----------------+-----------+----------------+ +| Beamforming || Beam Index | Mandatory | Y | +| || based | | | +| +-----------------+-----------+----------------+ +| || Real-time BF | Mandatory | Y | +| || Weights | | | +| +-----------------+-----------+----------------+ +| || Real-Time |   | N | +| || Beamforming | | | +| || Attributes | | | +| +-----------------+-----------+----------------+ | | UE Channel Info |   | N | +-----------------+-----------------+-----------+----------------+ -| Bandwidth | Programmable | Mandatory | Y | -| Saving | static-bit-width| | | -| | Fixed Point IQ | | | -+-----------------+-----------------+-----------+----------------+ -| | Real-time | | Y | -| | variable-bit | | | -| | -width | | | -+-----------------+-----------------+-----------+----------------+ +| Bandwidth || Programmable | Mandatory | Y | +| Saving || staticbitwidth | | | +| || Fixed Point IQ | | | +| +-----------------+-----------+----------------+ +| || Real-time | | Y | +| || variable-bit | | | +| || -width | | | +| +-----------------+-----------+----------------+ | | Compressed IQ |   | Y | +| +-----------------+-----------+----------------+ +| || Block floating |   | Y | +| || point | | | +| || compression | | | +| +-----------------+-----------+----------------+ +| || Block scaling |   | N | +| || compression | | | +| +-----------------+-----------+----------------+ +| || u-law |   | N | +| || compression | | | +| +-----------------+-----------+----------------+ +| || modulation |   | Y | +| || compression | | | +| +-----------------+-----------+----------------+ +| || beamspace |   | Y | +| || compression | | | +| +-----------------+-----------+----------------+ +| || Variable Bit |   | Y | +| || Width per | | | +| || Channel (per | | | +| || data section) | | | +| +-----------------+-----------+----------------+ +| || Static |   | N | +| || configuration | | | +| || of U-Plane IQ | | | +| || format and | | | +| || compression | | | +| || header | | | +| +-----------------+-----------+----------------+ +| || Use of symInc |   | N | +| || flag to allow | | | +| || multiple | | | +| || symbols in a | | | +| || C-Plane section| | | +-----------------+-----------------+-----------+----------------+ -| | Block floating |   | Y | -| | point | | | -| | compression | | | -+-----------------+-----------------+-----------+----------------+ -| | Block scaling |   | N | -| | compression | | | -+-----------------+-----------------+-----------+----------------+ -| | u-law |   | N | -| | compression | | | -+-----------------+-----------------+-----------+----------------+ -| | modulation |   | N | -| | compression | | | -+-----------------+-----------------+-----------+----------------+ -| | beamspace |   | N | -| | compression | | | -+-----------------+-----------------+-----------+----------------+ -| | Variable Bit |   | Y | -| | Width per | | | -| | Channel (per | | | -| | data section) | | | +| Energy Saving || Transmission |   | N | +| || blanking | | | +-----------------+-----------------+-----------+----------------+ -| | Static |   | N | -| | configuration | | | -| | of U-Plane IQ | | | -| | format and | | | -| | compression | | | -| | header | | | -+-----------------+-----------------+-----------+----------------+ -| | Use of “symInc” |   | N | -| | flag to allow | | | -| | multiple | | | -| | symbols in a | | | -| | C-Plane section | | | -+-----------------+-----------------+-----------+----------------+ -| Energy Saving | Transmission |   | N | -| | blanking | | | -+-----------------+-----------------+-----------+----------------+ -| O-DU - RU | Pre-configured | Mandatory | Y | -| Timing | Transport Delay | | | -| | Method | | | -+-----------------+-----------------+-----------+----------------+ -| | Measured |   | N | -| | Transport | | | -| | Method (eCPRI | | | -| | Msg 5) | | | +| O-DU - RU || Pre-configured | Mandatory | Y | +| Timing || Transport Delay| | | +| || Method | | | +| +-----------------+-----------+----------------+ +| || Measured |   | N | +| || Transport | | | +| || Method (eCPRI | | | +| || Msg 5) | | | +-----------------+-----------------+-----------+----------------+ | Synchronization | G.8275.1 | Mandatory | Y (C3 only)| | | | | | -+-----------------+-----------------+-----------+----------------+ +| +-----------------+-----------+----------------+ | | G.8275.2 |   | N | -+-----------------+-----------------+-----------+----------------+ +| +-----------------+-----------+----------------+ | | GNSS based sync |   | N | -+-----------------+-----------------+-----------+----------------+ +| +-----------------+-----------+----------------+ | | SyncE |   | N | +-----------------+-----------------+-----------+----------------+ | Transport | L2 : Ethernet | Mandatory | Y | | Features | | | | -+-----------------+-----------------+-----------+----------------+ -| | L3 : IPv4, IPv6 |   | N | -| | (CUS Plane) | | | -+-----------------+-----------------+-----------+----------------+ -| | QoS over | Mandatory | N | -| | Fronthaul | | | -+-----------------+-----------------+-----------+----------------+ -| | Prioritization |   | N | -| | of different | | | -| | U-plane traffic | | | -| | types | | | -+-----------------+-----------------+-----------+----------------+ -| | Support of |   | N | -| | Jumbo Ethernet | | | -| | frames | | | -+-----------------+-----------------+-----------+----------------+ -| | eCPRI | Mandatory | Y | -+-----------------+-----------------+-----------+----------------+ -| | support of |   | N | -| | eCPRI | | | -| | concatenation | | | -+-----------------+-----------------+-----------+----------------+ +| +-----------------+-----------+----------------+ +| || L3 : IPv4, IPv6|   | N | +| || (CUS Plane) | | | +| +-----------------+-----------+----------------+ +| || QoS over | Mandatory | Y | +| || Fronthaul | | | +| +-----------------+-----------+----------------+ +| || Prioritization |   | N | +| || of different | | | +| || U-plane traffic| | | +| || types | | | +| +-----------------+-----------+----------------+ +| || Support of |   | N | +| || Jumbo Ethernet | | | +| || frames | | | +| +-----------------+-----------+----------------+ +| || eCPRI | Mandatory | Y | +| +-----------------+-----------+----------------+ +| || support of |   | N | +| || eCPRI | | | +| || concatenation | | | +| +-----------------+-----------+----------------+ | | IEEE 1914.3 |   | N | +| +-----------------+-----------+----------------+ +| || Application | Mandatory | Y | +| || fragmentation | | | +| +-----------------+-----------+----------------+ +| || Transport |   | N | +| || fragmentation | | | +-----------------+-----------------+-----------+----------------+ -| | Application | Mandatory | Y | -| | fragmentation | | | -+-----------------+-----------------+-----------+----------------+ -| | Transport |   | N | -| | fragmentation | | | -+-----------------+-----------------+-----------+----------------+ -| Other | LAA LBT O-DU |   | N | -| | Congestion | | | -| | Window mgmt | | | -+-----------------+-----------------+-----------+----------------+ -| | LAA LBT RU |   | N | -| | Congestion | | | -| | Window mgmt | | | +| Other || LAA LBT O-DU |   | N | +| || Congestion | | | +| || Window mgmt | | | +| +-----------------+-----------+----------------+ +| || LAA LBT RU |   | N | +| || Congestion | | | +| || Window mgm | | | +-----------------+-----------------+-----------+----------------+ -Details on the subset of xRAN functionality implemented are shown in +Details on the subset of O-RAN functionality implemented are shown in Table 8. Level of Validation Specified as: -- C: Completed code implementation for xRAN Library +- C: Completed code implementation for O-RAN Library - I: Integrated into Intel FlexRAN PHY - T: Tested end to end with O-RU -Table 8. Levels of Validation - -+------------+------------+------------+------------+-----+-----+---+ -| Category | Item | Q4 (20.04) | | | | | -+============+============+============+============+=====+=====+===+ -| | | Status | C | I | T | | -+------------+------------+------------+------------+-----+-----+---+ -| General | Radio | NR | N/A | N/A | N/A | | -| | access | | | | | | -| | technology | | | | | | -| | (LTE / NR) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Nominal | 15 | Y | Y | N | | -| | s\ | /30/120KHz | | | | | -| | ub-carrier | | | | | | -| | spacing | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | FFT size | 512/1024 | Y | Y | N | | -| | | /2048/4096 | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Channel | 5/10 | Y | Y | N | | -| | bandwidth | /20/100Mhz | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Number of | 12 | Y | Y | N | | -| | the | | | | | | -| | channel | | | | | | -| | (Component | | | | | | -| | Carrier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | RU | A | Y | Y | N | | -| | category | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | TDD Config | Supporte\ | Y | Y | N | | -| | | d/Flexible | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | FDD | Supported | Y | Y | N | | -| | Support | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Tx/Rx | Supported | Y | Y | N | | -| | switching | | | | | | -| | based on | | | | | | -| | 'data | | | | | | -| | Direction' | | | | | | -| | field of | | | | | | -| | C-plane | | | | | | -| | message | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | IP version | N/A | N/A | N/A | N/A | | -| | for | | | | | | -| | Management | | | | | | -| | traffic at | | | | | | -| | fronthaul | | | | | | -| | network | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| PRACH | One Type 3 | Supported | Y | Y | N | | -| | message | | | | | | -| | for all | | | | | | -| | repeated | | | | | | -| | PRACH | | | | | | -| | preambles | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Type 3 | 1 | Y | Y | N | | -| | message | | | | | | -| | per | | | | | | -| | repeated | | | | | | -| | PRACH | | | | | | -| | preambles | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | timeOffset | Supported | Y | Y | N | | -| | including | | | | | | -| | cpLength | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Supported | Supported | Y | Y | N | | -+------------+------------+------------+------------+-----+-----+---+ -| | PRACH | Supported | Y | Y | N | | -| | preamble | | | | | | -| | format / | | | | | | -| | index | | | | | | -| | number | | | | | | -| | (number of | | | | | | -| | the | | | | | | -| | occasion) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| Delay | Network | Supported | Y | Y | N | | -| management | delay | | | | | | -| | det\ | | | | | | -| | ermination | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | lls-CU | Supported | Y | Y | N | | -| | timing | | | | | | -| | advance | | | | | | -| | type | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Non-delay | Not | N | N | N | | -| | managed | supported | | | | | -| | U-plane | | | | | | -| | traffic | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| C/U-plane | Transport | Ethernet | Y | Y | N | | -| Transport | enc\ | | | | | | -| | apsulation | | | | | | -| | (Ethernet | | | | | | -| | / IP) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Jumbo | Supported | Y | Y | N | | -| | frames | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Transport | eCPRI | Y | Y | N | | -| | header | | | | | | -| | (eCPRI / | | | | | | -| | RoE) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | IP version | N/A | N/A | N/A | N/A | | -| | when | | | | | | -| | Transport | | | | | | -| | header is | | | | | | -| | IP/UDP | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | eCPRI | Not | N | N | N | | -| | Con\ | supported | | | | | -| | catenation | | | | | | -| | when | | | | | | -| | Transport | | | | | | -| | header is | | | | | | -| | eCPRI | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | eAxC ID | 4 \* | Y | Y | N | | -| | CU_Port_ID | | | | | | -| | bitwidth | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | eAxC ID | 4 \* | Y | Y | N | | -| | Ban\ | | | | | | -| | dSector_ID | | | | | | -| | bitwidth | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | eAxC ID | 4 \* | Y | Y | N | | -| | CC_ID | | | | | | -| | bitwidth | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | eAxC ID | 4 \* | Y | Y | N | | -| | RU_Port_ID | | | | | | -| | bitwidth | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Fra\ | Supported | Y | Y | N | | -| | gmentation | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Transport | N/A | N | N | N | | -| | prio\ | | | | | | -| | ritization | | | | | | -| | within | | | | | | -| | U-plane | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Separation | Supported | Y | Y | N | | -| | of | | | | | | -| | C/U-plane | | | | | | -| | and | | | | | | -| | M-plane | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Separation | VLAN ID | Y | Y | N | | -| | of C-plane | | | | | | -| | and | | | | | | -| | U-plane | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Max Number | 16 | Y | Y | N | | -| | of VLAN | | | | | | -| | per | | | | | | -| | physical | | | | | | -| | port | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| Reception | Rx_on_time | Supported | Y | Y | N | | -| Window | | | | | | | -| Monitoring | | | | | | | -| (Counters) | | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Rx_early | Supported | N | N | N | | -+------------+------------+------------+------------+-----+-----+---+ -| | Rx_late | Supported | N | N | N | | -+------------+------------+------------+------------+-----+-----+---+ -| | Rx_corrupt | Supported | N | N | N | | -+------------+------------+------------+------------+-----+-----+---+ -| | R\ | Supported | N | N | N | | -| | x_pkt_dupl | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Total | Supported | Y | N | N | | -| | _msgs_rcvd | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| B\ | RU | Index and | Y | Y | N | | -| eamforming | b\ | weights | | | | | -| | eamforming | | | | | | -| | type | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | B\ | C-plane | Y | N | N | | -| | eamforming | | | | | | -| | control | | | | | | -| | method | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Number of | No-re | Y | Y | N | | -| | beams | strictions | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| IQ | U-plane | Supported | Y | Y | Y | | -| c\ | data | | | | | | -| ompression | c\ | | | | | | -| | ompression | | | | | | -| | method | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | U-plane | BFP: | Y | Y | Y | | -| | data IQ | 8,9,12,14 | | | | | -| | bitwidth | bits | | | | | -| | (Before / | | | | | | -| | After | | | | | | -| | co | | | | | | -| | mpression) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Static | Supported | N | N | N | | -| | con\ | | | | | | -| | figuration | | | | | | -| | of U-plane | | | | | | -| | IQ format | | | | | | -| | and | | | | | | -| | c\ | | | | | | -| | ompression | | | | | | -| | header | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| eCPRI | ec\ | 001b | Y | Y | Y | | -| Header | priVersion | | | | | | -| Format | | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | ecp\ | Supported | Y | Y | Y | | -| | riReserved | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | ecpriCon\ | Not | N | N | N | | -| | catenation | supported | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | ec\ | U-plane | Supported | Y | Y | Y | -| | priMessage | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | C-plane | Supported | Y | Y | Y | -+------------+------------+------------+------------+-----+-----+---+ -| | | Delay | Not | N | N | N | -| | | m\ | supported | | | | -| | | easurement | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | ec\ | Supported | Y | Y | Y | | -| | priPayload | | | | | | -| | (payload | | | | | | -| | size in | | | | | | -| | bytes) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | ecpriRtcid | Supported | Y | Y | Y | | -| | /ecpriPcid | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | e\ | Supported | Y | Y | Y | | -| | cpriSeqid: | | | | | | -| | Sequence | | | | | | -| | ID | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | e\ | Supported | Y | Y | Y | | -| | cpriSeqid: | | | | | | -| | E bit | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | e\ | Not | N | N | N | | -| | cpriSeqid: | supported | | | | | -| | S\ | | | | | | -| | ubsequence | | | | | | -| | ID | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| C-plane | Section | Not | N | N | N | | -| Type | Type 0 | supported | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Section | Supported | Y | Y | Y | | -| | Type 1 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Section | Supported | Y | Y | Y | | -| | Type 3 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Section | Not | N | N | N | | -| | Type 5 | supported | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Section | Not | N | N | N | | -| | Type 6 | supported | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Section | Not | N | N | N | | -| | Type 7 | supported | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| C-plane | *Coding of | dat\ | Supported | Y | Y | N | -| Packet | I\ | aDirection | | | | | -| Format | nformation | (data | | | | | -| | Elements – | direction | | | | | -| | A\ | (gNB | | | | | -| | pplication | Tx/Rx)) | | | | | -| | Layer, | | | | | | -| | Common* | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | payl\ | 001b | Y | Y | N | -| | | oadVersion | | | | | -| | | (payload | | | | | -| | | version) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | f\ | Supported | Y | Y | N | -| | | ilterIndex | | | | | -| | | (filter | | | | | -| | | index) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | frameId | Supported | Y | Y | N | -| | | (frame | | | | | -| | | i\ | | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | subframeId | Supported | Y | Y | N | -| | | (subframe | | | | | -| | | i\ | | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | slotId | Supported | Y | Y | N | -| | | (slot | | | | | -| | | i\ | | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | sta\ | Supported | Y | Y | N | -| | | rtSymbolid | | | | | -| | | (start | | | | | -| | | symbol | | | | | -| | | i\ | | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | number | up to the | Y | Y | N | -| | | Ofsections | maximum | | | | -| | | (number of | number of | | | | -| | | sections) | PRBs | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | s\ | 1 and 3 | Y | Y | N | -| | | ectionType | | | | | -| | | (section | | | | | -| | | type) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | udCompHdr | Supported | Y | Y | N | -| | | (user data | | | | | -| | | c\ | | | | | -| | | ompression | | | | | -| | | header) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | n\ | Not | N | N | N | -| | | umberOfUEs | supported | | | | -| | | (number Of | | | | | -| | | UEs) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | timeOffset | Supported | Y | Y | N | -| | | (time | | | | | -| | | offset) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | fram\ | mu=0,1,3 | Y | Y | N | -| | | eStructure | | | | | -| | | (frame | | | | | -| | | structure) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | cpLength | Supported | Y | Y | N | -| | | (cyclic | | | | | -| | | prefix | | | | | -| | | length) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | *Coding of | sectionId | Supported | Y | Y | N | -| | I\ | (section | | | | | -| | nformation | i\ | | | | | -| | Elements – | dentifier) | | | | | -| | A\ | | | | | | -| | pplication | | | | | | -| | Layer, | | | | | | -| | Sections* | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | rb | 0 | Y | Y | N | -| | | (resource | | | | | -| | | block | | | | | -| | | indicator) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | symInc | 0 or 1 | Y | Y | N | -| | | (symbol | | | | | -| | | number | | | | | -| | | increment | | | | | -| | | command) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | startPrbc | Supported | Y | Y | N | -| | | (starting | | | | | -| | | PRB of | | | | | -| | | control | | | | | -| | | section) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | reMask | Supported | Y | Y | N | -| | | (resource | | | | | -| | | element | | | | | -| | | mask) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | numPrbc | Supported | Y | Y | N | -| | | (number of | | | | | -| | | contiguous | | | | | -| | | PRBs per | | | | | -| | | control | | | | | -| | | section) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | numSymbol | Supported | Y | Y | N | -| | | (number of | | | | | -| | | symbols) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | ef | Supported | Y | Y | N | -| | | (extension | | | | | -| | | flag) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | beamId | Support | Y | Y | N | -| | | (beam | | | | | -| | | i\ | | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | ueId (UE | Not | N | N | N | -| | | i\ | supported | | | | -| | | dentifier) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | freqOffset | Supported | Y | Y | N | -| | | (frequency | | | | | -| | | offset) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | regulariza\| Not | N | N | N | -| | | tionFactor | supported | | | | -| | | (regu\ | | | | | -| | | larization | | | | | -| | | Factor) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | ciIsample, | Not | N | N | N | -| | | ciQsample | supported | | | | -| | | (channel | | | | | -| | | i\ | | | | | -| | | nformation | | | | | -| | | I and Q | | | | | -| | | values) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | laaMsgType | Not | N | N | N | -| | | (LAA | supported | | | | -| | | message | | | | | -| | | type) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | laaMsgLen | Not | N | N | N | -| | | (LAA | supported | | | | -| | | message | | | | | -| | | length) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtHandle | Not | N | N | N | -| | | | supported | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtD\ | Not | N | N | N | -| | | eferFactor | supported | | | | -| | | (listen-b | | | | | -| | | efore-talk | | | | | -| | | defer | | | | | -| | | factor) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtBack | Not | N | N | N | -| | | offCounter | supported | | | | -| | | (listen-b\ | | | | | -| | | efore-talk | | | | | -| | | backoff | | | | | -| | | counter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtOffset | Not | N | N | N | -| | | (listen-b\ | supported | | | | -| | | efore-talk | | | | | -| | | offset) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | MCOT | Not | N | N | N | -| | | (maximum | supported | | | | -| | | channel | | | | | -| | | occupancy | | | | | -| | | time) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtMode | Not | N | N | N | -| | | (LBT Mode) | supported | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | l\ | Not | N | N | N | -| | | btPdschRes | supported | | | | -| | | (LBT PDSCH | | | | | -| | | Result) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | sfStatus | Not | N | N | N | -| | | (subframe | supported | | | | -| | | status) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtDrsRes | Not | N | N | N | -| | | (LBT DRS | supported | | | | -| | | Result) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | initia\ | Not | N | N | N | -| | | lPartialSF | supported | | | | -| | | (Initial | | | | | -| | | partial | | | | | -| | | SF) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtBufErr | Not | N | N | N | -| | | (LBT | supported | | | | -| | | Buffer | | | | | -| | | Error) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | sfnSf | Not | N | N | N | -| | | (SFN/SF | supported | | | | -| | | End) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbt | Not | N | N | N | -| | | CWConfig_H | supported | | | | -| | | (HARQ | | | | | -| | | Parameters | | | | | -| | | for | | | | | -| | | Congestion | | | | | -| | | Window | | | | | -| | | m | | | | | -| | | anagement) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbt | Not | N | N | N | -| | | CWConfig_T | supported | | | | -| | | (TB | | | | | -| | | Parameters | | | | | -| | | for | | | | | -| | | Congestion | | | | | -| | | Window | | | | | -| | | m | | | | | -| | | anagement) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtTr\ | Not | N | N | N | -| | | afficClass | supported | | | | -| | | (Traffic | | | | | -| | | class | | | | | -| | | priority | | | | | -| | | for | | | | | -| | | Congestion | | | | | -| | | Window | | | | | -| | | m | | | | | -| | | anagement) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | lbtCWR_Rst | Not | N | N | N | -| | | (No | supported | | | | -| | | tification | | | | | -| | | about | | | | | -| | | packet | | | | | -| | | reception | | | | | -| | | successful | | | | | -| | | or not) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | reserved | 0 | N | N | N | -| | | (reserved | | | | | -| | | for future | | | | | -| | | use) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | *Section |   |   |   |   | -| | | Extension | | | | | -| | | Commands* | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | extType | Supported | Y | Y | N | -| | | (extension | | | | | -| | | type) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | ef | Supported | Y | Y | N | -| | | (extension | | | | | -| | | flag) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | extLen | Supported | Y | Y | N | -| | | (extension | | | | | -| | | length) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Coding of |   |   |   |   | | -| | I\ | | | | | | -| | nformation | | | | | | -| | Elements – | | | | | | -| | A\ | | | | | | -| | pplication | | | | | | -| | Layer, | | | | | | -| | Section | | | | | | -| | E\ | | | | | | -| | xtensions | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | *ExtType=1:| bfwCompHdr | Supported | Y | Y | N | -| | B\ | (beam\ | | | | | -| | eamforming | forming | | | | | -| | Weights | weight | | | | | -| | Extension | c\ | | | | | -| | Type* | ompression | | | | | -| | | header) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bf | Supported | Y | Y | N | -| | | wCompParam | | | | | -| | | (b\ | | | | | -| | | eamforming | | | | | -| | | weight | | | | | -| | | c\ | | | | | -| | | ompression | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfwl | Supported | Y | Y | N | -| | | (b\ | | | | | -| | | eamforming | | | | | -| | | weight | | | | | -| | | in-phase | | | | | -| | | value) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfwQ | Supported | Y | Y | N | -| | | (b\ | | | | | -| | | eamforming | | | | | -| | | weight | | | | | -| | | quadrature | | | | | -| | | value) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfaCompHdr | Not | Y | N | N | -| | *ExtType=2:| (b\ | supported | | | | -| | B\ | eamforming | | | | | -| | eamforming | attributes | | | | | -| | Attributes | c\ | | | | | -| | Extension | ompression | | | | | -| | Type* | header) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfAzPt | Not | Y | N | N | -| | | (b\ | supported | | | | -| | | eamforming | | | | | -| | | azimuth | | | | | -| | | pointing | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfZePt | Not | Y | N | N | -| | | (b\ | supported | | | | -| | | eamforming | | | | | -| | | zenith | | | | | -| | | pointing | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfAz3dd | Not | Y | N | N | -| | | (b | supported | | | | -| | | eamforming | | | | | -| | | azimuth | | | | | -| | | beamwidth | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfZe3dd | Not | Y | N | N | -| | | (b\ | supported | | | | -| | | eamforming | | | | | -| | | zenith | | | | | -| | | beamwidth | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfAzSl | Not | Y | N | N | -| | | (b\ | supported | | | | -| | | eamforming | | | | | -| | | azimuth | | | | | -| | | sidelobe | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | bfZeSl | Not | Y | N | N | -| | | (b\ | supported | | | | -| | | eamforming | | | | | -| | | zenith | | | | | -| | | sidelobe | | | | | -| | | parameter) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | ze\ | Not | Y | N | N | -| | | ro-padding | supported | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | cod | Not | N | N | N | -| | *ExtType=3:| ebookIndex | supported | | | | -| | DL | (precoder | | | | | -| | Precoding | codebook | | | | | -| | Extension | used for | | | | | -| | Type* | tra | | | | | -| | | nsmission) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | layerID | Not | N | N | N | -| | | (Layer ID | supported | | | | -| | | for DL | | | | | -| | | tra\ | | | | | -| | | nsmission) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | txScheme | Not | N | N | N | -| | | (tr | supported | | | | -| | | ansmission | | | | | -| | | scheme) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | numLayers | Not | N | N | N | -| | | (number of | supported | | | | -| | | layers | | | | | -| | | used for | | | | | -| | | DL | | | | | -| | | tra\ | | | | | -| | | nsmission) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | crsReMask | Not | N | N | N | -| | | (CRS | supported | | | | -| | | resource | | | | | -| | | element | | | | | -| | | mask) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | c | Not | N | N | N | -| | | rsSyumINum | supported | | | | -| | | (CRS | | | | | -| | | symbol | | | | | -| | | number | | | | | -| | | i\ | | | | | -| | | ndication) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | crsShift | Not | N | N | N | -| | | (crsShift | supported | | | | -| | | used for | | | | | -| | | DL | | | | | -| | | tra\ | | | | | -| | | nsmission) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | beamIdAP1 | Not | N | N | N | -| | | (beam id | supported | | | | -| | | to be used | | | | | -| | | for | | | | | -| | | antenna | | | | | -| | | port 1) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | beamIdAP2 | Not | N | N | N | -| | | (beam id | supported | | | | -| | | to be used | | | | | -| | | for | | | | | -| | | antenna | | | | | -| | | port 2) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | beamIdAP3 | Not | N | N | N | -| | | (beam id | supported | | | | -| | | to be used | | | | | -| | | for | | | | | -| | | antenna | | | | | -| | | port 3) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | csf | Not | Y | N | N | -| | *ExtType=4:| (con\ | supported | | | | -| | Modulation | stellation | | | | | -| | C\ | shift | | | | | -| | ompression | flag) | | | | | -| | Parameters | | | | | | -| | Extension | | | | | | -| | Type* | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | mod | Not | Y | N | N | -| | | CompScaler | supported | | | | -| | | ( | | | | | -| | | modulation | | | | | -| | | c\ | | | | | -| | | ompression | | | | | -| | | scaler | | | | | -| | | value) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | mcS\ | Not | Y | N | N | -| | *ExtType=5:| caleReMask | supported | | | | -| | Modulation | ( | | | | | -| | C\ | modulation | | | | | -| | ompression | c\ | | | | | -| | Additional | ompression | | | | | -| | Parameters | power | | | | | -| | Extension | scale RE | | | | | -| | Type* | mask) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | csf | Not | Y | N | N | -| | | (con\ | supported | | | | -| | | stellation | | | | | -| | | shift | | | | | -| | | flag) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | | mcS | Not | Y | N | N | -| | | caleOffset | supported | | | | -| | | (scaling | | | | | -| | | value for | | | | | -| | | modulation | | | | | -| | | co\ | | | | | -| | | mpression) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| U-plane | dat | Supported | Y | Y | Y | | -| Packet | aDirection | | | | | | -| Format | (data | | | | | | -| | direction | | | | | | -| | (gNB | | | | | | -| | Tx/Rx)) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | payl\ | 001b | Y | Y | Y | | -| | oadVersion | | | | | | -| | (payload | | | | | | -| | version) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | f\ | Supported | Y | Y | Y | | -| | ilterIndex | | | | | | -| | (filter | | | | | | -| | index) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | frameId | Supported | Y | Y | Y | | -| | (frame | | | | | | -| | i\ | | | | | | -| | dentifier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | subframeId | Supported | Y | Y | Y | | -| | (subframe | | | | | | -| | i\ | | | | | | -| | dentifier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | slotId | Supported | Y | Y | Y | | -| | (slot | | | | | | -| | i | | | | | | -| | dentifier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | symbolId | Supported | Y | Y | Y | | -| | (symbol | | | | | | -| | i\ | | | | | | -| | dentifier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | sectionId | Supported | Y | Y | Y | | -| | (section | | | | | | -| | i\ | | | | | | -| | dentifier) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | rb | 0 | Y | Y | Y | | -| | (resource | | | | | | -| | block | | | | | | -| | indicator) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | symInc | 0 | Y | Y | Y | | -| | (symbol | | | | | | -| | number | | | | | | -| | increment | | | | | | -| | command) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | startPrbu | Supported | Y | Y | Y | | -| | (s\ | | | | | | -| | tartingPRB | | | | | | -| | of user | | | | | | -| | plane | | | | | | -| | section) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | numPrbu | Supported | Y | Y | Y | | -| | (number of | | | | | | -| | PRBs per | | | | | | -| | user plane | | | | | | -| | section) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | udCompHdr | Supported | Y | Y | N | | -| | (user data | | | | | | -| | c\ | | | | | | -| | ompression | | | | | | -| | header) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | reserved | 0 | Y | Y | Y | | -| | (reserved | | | | | | -| | for future | | | | | | -| | use) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | u\ | Supported | Y | Y | N | | -| | dCompParam | | | | | | -| | (user data | | | | | | -| | c\ | | | | | | -| | ompression | | | | | | -| | parameter) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | iSample | 16 | Y | Y | Y | | -| | (in-phase | | | | | | -| | sample) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | qSample | 16 | Y | Y | Y | | -| | ( | | | | | | -| | quadrature | | | | | | -| | sample) | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| S-plane | Topology | Supported | N | N | N | | -| | conf\ | | | | | | -| | iguration: | | | | | | -| | C1 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Topology | Supported | N | N | N | | -| | conf\ | | | | | | -| | iguration: | | | | | | -| | C2 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Topology | Supported | Y | Y | Y | | -| | conf\ | | | | | | -| | iguration: | | | | | | -| | C3 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | Topology | Supported | N | N | N | | -| | conf\ | | | | | | -| | iguration: | | | | | | -| | C4 | | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| | PTP | Full | Supported | Y | Y | N | -| | | Timing | | | | | -| | | Support | | | | | -| | | (G.8275.1) | | | | | -+------------+------------+------------+------------+-----+-----+---+ -| M-plane |   |   | Not | N | N | N | -| | | | supported | | | | -+------------+------------+------------+------------+-----+-----+---+ +Table 8. Levels of support + ++------------+------------+------------+------------+-----+-----+-----+ +| Category | Item | Status | C | I | T | ++============+============+============+============+=====+=====+=====+ +| General || Radio | NR | N/A | N/A | N/A | +| || access | | | | | +| || technology | | | | | +| || (LTE / NR) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || Nominal || 15 | Y | Y | N | +| || sub-carrier || /30/120KHz| | | | +| || spacing | | | | | +| +------------+------------+------------+-----+-----+-----+ +| | FFT size || 512/1024 | Y | Y | N | +| | || /2048/4096| | | | +| +------------+------------+------------+-----+-----+-----+ +| || Channel || 5/10 | Y | Y | N | +| || bandwidth || /20/100Mhz| | | | +| +------------+------------+------------+-----+-----+-----+ +| || Number of | 12 | Y | Y | N | +| || Cells | | | | | +| || (Component | | | | | +| || Carriers) | | | | | +| || | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || RU | A | Y | Y | N | +| || category | | | | | +| +------------+------------+------------+-----+-----+-----+ +| | TDD Config || Supported | Y | Y | N | +| | || Flexible | | | | +| +------------+------------+------------+-----+-----+-----+ +| || FDD | Supported | Y | Y | N | +| || Support | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || Tx/Rx | Supported | Y | Y | N | +| || switching | | | | | +| || based on | | | | | +| || 'data | | | | | +| || Direction' | | | | | +| || field of | | | | | +| || C-plane | | | | | +| || message | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || IP version | N/A | N/A | N/A | N/A | +| || for | | | | | +| || Management | | | | | +| || traffic at | | | | | +| || fronthaul | | | | | +| || network | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +| PRACH || One Type 3 | Supported | Y | Y | N | +| || message | | | | | +| || for all | | | | | +| || repeated | | | | | +| || PRACH | | | | | +| || preambles | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Type 3 | 1 | Y | Y | N | +| || message | | | | | +| || per | | | | | +| || repeated | | | | | +| || PRACH | | | | | +| || preambles | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || timeOffset | Supported | Y | Y | N | +| || including | | | | | +| || cpLength | | | | | +| +-------------------------+------------+-----+-----+-----+ +| | Supported | Supported | Y | Y | N | +| +-------------------------+------------+-----+-----+-----+ +| || PRACH | Supported | Y | Y | N | +| || preamble | | | | | +| || format | | | | | +| || index | | | | | +| || number | | | | | +| || (number of | | | | | +| || occasions) | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| Delay || Network | Supported | Y | Y | N | +|| management|| delay | | | | | +| || determination | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || lls-CU | Supported | Y | Y | N | +| || timing | | | | | +| || advance | | | | | +| || type | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Non-delay || Not | N | N | N | +| || managed || supported | | | | +| || U-plane | | | | | +| || traffic | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| C/U-plane || Transport | Ethernet | Y | Y | N | +|| Transport || encapsulation | | | | | +| || (Ethernet IP) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Jumbo | Supported | Y | Y | N | +| || frames | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Transport | eCPRI | Y | Y | N | +| || header | | | | | +| || (eCPRI RoE) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || IP version | N/A | N/A | N/A | N/A | +| || when | | | | | +| || Transport | | | | | +| || header is | | | | | +| || IP/UDP | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || eCPRI || Not | N | N | N | +| || Concatenation || supported | | | | +| || when | | | | | +| || Transport | | | | | +| || header is | | | | | +| || eCPRI | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || eAxC ID | 4 \* | Y | Y | N | +| || CU_Port_ID | | | | | +| || bitwidth | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || eAxC ID | 4 \* | Y | Y | N | +| || BandSector_ID | | | | | +| || bitwidth | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || eAxC ID | 4 \* | Y | Y | N | +| || CC_ID | | | | | +| || bitwidth | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || eAxC ID | 4 \* | Y | Y | N | +| || RU_Port_ID | | | | | +| || bitwidth | | | | | +| +-------------------------+------------+-----+-----+-----+ +| | Fragmentation | Supported | Y | Y | N | +| +-------------------------+------------+-----+-----+-----+ +| || Transport | N/A | N | N | N | +| || prioritization | | | | | +| || within | | | | | +| || U-plane | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Separation | Supported | Y | Y | N | +| || of | | | | | +| || C/U-plane | | | | | +| || and | | | | | +| || M-plane | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Separation || VLAN ID\ | Y | Y | N | +| || of C-plane || and/or | | | | +| || and || eCpri | | | | +| || U-plane || Messagge | | | | +| | || Type | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Max Number | 16 | Y | Y | N | +| || of VLAN | | | | | +| || per | | | | | +| || physical | | | | | +| || port | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| Reception | Rx_on_time | Supported | Y | Y | N | +|| Window | | | | | | +|| Monitoring| | | | | | +|| (Counters)| | | | | | +| +-------------------------+------------+-----+-----+-----+ +| | Rx_early | Supported | N | N | N | +| +-------------------------+------------+-----+-----+-----+ +| | Rx_late | Supported | N | N | N | +| +-------------------------+------------+-----+-----+-----+ +| | Rx_corrupt | Supported | N | N | N | +| +-------------------------+------------+-----+-----+-----+ +| || Rx_pkt_dupl | Supported | N | N | N | +| +-------------------------+------------+-----+-----+-----+ +| || Total_msgs_rcvd | Supported | Y | N | N | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| || RU || Index and | Y | Y | N | +|| Beam-\ || beamforming || weights | | | | +|| forming || type || | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Beamforming | C-plane | Y | N | N | +| || control | | | | | +| || method | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Number of || No res- | Y | Y | N | +| || beams || strictions| | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| IQ || U-plane | Supported | Y | Y | Y | +|| compre || data | | | | | +| ssion || compression | | | | | +| || method | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || U-plane || BFP: | Y | Y | Y | +| || data IQ || 8,9,12,14 | | | | +| || bitwidth || bits | | | | +| || (Before / || | | | | +| || After || | | | | +| || compression) || | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Static | Supported | N | N | N | +| || configuration | | | | | +| || of U-plane | | | | | +| || IQ format | | | | | +| || and | | | | | +| || compression | | | | | +| || header | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +|| eCPRI || ecpriVersion | 001b | Y | Y | Y | +|| Header || | | | | | +|| Format || | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || ecpriReserved | Supported | Y | Y | Y | +| +-------------------------+------------+-----+-----+-----+ +| || ecpriCon || Not | N | N | N | +| | catenation || supported | | | | +| +------------+------------+------------+-----+-----+-----+ +| || ecpri\ | U-plane | Supported | Y | Y | Y | +| || Message | | | | | | +| | +------------+------------+-----+-----+-----+ +| | | C-plane | Supported | Y | Y | Y | +| | +------------+------------+-----+-----+-----+ +| | || Delay | Supported | Y | Y | Y | +| | || measure | | | | | +| | | ment | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || ecpri\ | Supported | Y | Y | Y | +| || Payload | | | | | +| || (payload | | | | | +| || size in | | | | | +| || bytes) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || ecpriRtcid | Supported | Y | Y | Y | +| || /ecpriPcid | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || ecpri | Supported | Y | Y | Y | +| || Seqid: | | | | | +| || Sequence | | | | | +| || ID | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || ecpri\ | Supported | Y | Y | Y | +| || Seqid: | | | | | +| || E bit | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || ecpri\ || Not | N | N | N | +| || Seqid: || supported | | | | +| || Sub\ | | | | | +| || sequence | | | | | +| || ID | | | | | +| | | | | | | ++------------+------------+------------+------------+-----+-----+-----+ +|| C-plane || Section || Not | N | N | N | +|| Type || Type 0 || supported | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Section | Supported | Y | Y | Y | +| || Type 1 | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Section | Supported | Y | Y | Y | +| || Type 3 | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Section || Not | N | N | N | +| || Type 5 || supported | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Section || Not | N | N | N | +| || Type 6 || supported | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Section || Not | N | N | N | +| || Type 7 || supported | | | | +| | | | | | | ++------------+------------+------------+------------+-----+-----+-----+ +|| C-plane || *Coding*\ || data\ | Supported | Y | Y | N | +|| Packet || *of Infor*|| Direction | | | | | +|| Format | *mation* || (data | | | | | +| || *Elements*|| direction | | | | | +| || *Appli* || (gNB | | | | | +| | *cation* || Tx/Rx)) | | | | | +| || *Layer,*\ || | | | | | +| || *Common* || | | | | | +| | +------------+------------+-----+-----+-----+ +| | || payload || 001b | Y | Y | N | +| | | Version || | | | | +| | || (payload || | | | | +| | || version) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || filter | Supported | Y | Y | N | +| | | Index | | | | | +| | || (filter | | | | | +| | || index) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || frameId | Supported | Y | Y | N | +| | || (frame | | | | | +| | || iden | | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || subframeId| Supported | Y | Y | N | +| | || (subframe | | | | | +| | || iden | | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || slotId | Supported | Y | Y | N | +| | || (slot | | | | | +| | || iden | | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || start\ | Supported | Y | Y | N | +| | || Symbolid | | | | | +| | || (start | | | | | +| | || symbol | | | | | +| | || iden | | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || number || up to the | Y | Y | N | +| | || Ofsections|| maximum | | | | +| | || (number of|| number of | | | | +| | || sections) || PRBs | | | | +| | +------------+------------+-----+-----+-----+ +| | || section\ || 1 and 3 | Y | Y | N | +| | || Type || | | | | +| | || (section || | | | | +| | || type) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || udCompHdr | Supported | Y | Y | N | +| | || (user data| | | | | +| | || com | | | | | +| | | pression | | | | | +| | || header) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || number\ || Not | N | N | N | +| | || OfUEs || supported | | | | +| | || (number Of| | | | | +| | || UEs) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || timeOffset| Supported | Y | Y | N | +| | || (time | | | | | +| | || offset) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || frame\ | mu=0,1,3 | Y | Y | N | +| | || Structure | | | | | +| | || (frame | | | | | +| | || structure)| | | | | +| | +------------+------------+-----+-----+-----+ +| | || cpLength | Supported | Y | Y | N | +| | || (cyclic | | | | | +| | || prefix | | | | | +| | || length) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || *Coding* || sectionId | Supported | Y | Y | N | +| || *of Infor*|| (section | | | | | +| | *mation* || iden | | | | | +| || *Elements*| tifier) | | | | | +| || *Ap* | | | | | | +| | *plication*| | | | | | +| || *Layer,* | | | | | | +| || *Sections*| | | | | | +| | +------------+------------+-----+-----+-----+ +| | || rb | 0 | Y | Y | N | +| | || (resource | | | | | +| | || block | | | | | +| | || indicator)| | | | | +| | +------------+------------+-----+-----+-----+ +| | || symInc | 0 or 1 | Y | Y | N | +| | || (symbol | | | | | +| | || number | | | | | +| | || increment | | | | | +| | || command) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || startPrbc | Supported | Y | Y | N | +| | || (starting | | | | | +| | || PRB of | | | | | +| | || control | | | | | +| | || section) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || reMask | Supported | Y | Y | N | +| | || (resource | | | | | +| | || element | | | | | +| | || mask) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || numPrbc | Supported | Y | Y | N | +| | || (number of| | | | | +| | || contiguous| | | | | +| | || PRBs per | | | | | +| | || control | | | | | +| | || section) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || numSymbol | Supported | Y | Y | N | +| | || (number of| | | | | +| | || symbols) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || ef | Supported | Y | Y | N | +| | || (extension| | | | | +| | || flag) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || beamId | Support | Y | Y | N | +| | || (beam | | | | | +| | || iden | | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || ueId (UE || Not | N | N | N | +| | || iden || supported | | | | +| | | tifier) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || freqOffset| Supported | Y | Y | N | +| | || (frequency| | | | | +| | || offset) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || regulari || Not | N | N | N | +| | | zation\ || supported | | | | +| | || Factor || | | | | +| | || (regulari | | | | | +| | | zation | | | | | +| | || Factor) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || ciIsample,|| Not | N | N | N | +| | || ciQsample || supported | | | | +| | || (channel || | | | | +| | || infor | | | | | +| | | mation | | | | | +| | || I and Q | | | | | +| | || values) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || laaMsgType|| Not | N | N | N | +| | || (LAA || supported | | | | +| | || message || | | | | +| | || type) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || laaMsgLen || Not | N | N | N | +| | || (LAA || supported | | | | +| | || message | | | | | +| | || length) | | | | | +| | +------------+------------+-----+-----+-----+ +| | | lbtHandle || Not | N | N | N | +| | | || supported | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtDefer || Not | N | N | N | +| | || Factor || supported | | | | +| | || (listen || | | | | +| | || before || | | | | +| | || talk || | | | | +| | || defer || | | | | +| | || factor) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtBack || Not | N | N | N | +| | || offCounter|| supported | | | | +| | || (listen || | | | | +| | || before || | | | | +| | || talk || | | | | +| | || backoff || | | | | +| | || counter) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtOffset || Not | N | N | N | +| | || (listen- || supported | | | | +| | || before | | | | | +| | || talk || | | | | +| | || offset) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || MCOT || Not | N | N | N | +| | || (maximum || supported | | | | +| | || channel | | | | | +| | || occupancy | | | | | +| | || time) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtMode || Not | N | N | N | +| | || (LBT Mode)|| supported | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbt || Not | N | N | N | +| | | PdschRes || supported | | | | +| | || (LBT PDSCH|| | | | | +| | || Result) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || sfStatus || Not | N | N | N | +| | || (subframe || supported | | | | +| | || status) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtDrsRes || Not | N | N | N | +| | || (LBT DRS || supported | | | | +| | || Result) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || initial || Not | N | N | N | +| | | PartialSF || supported | | | | +| | || (Initial | | | | | +| | | partial | | | | | +| | | SF) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtBufErr || Not | N | N | N | +| | || (LBT || supported | | | | +| | | Buffer | | | | | +| | || Error) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || sfnSf || Not | N | N | N | +| | || (SFN/SF || supported | | | | +| | | End) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbt || Not | N | N | N | +| | || CWConfig_H|| supported | | | | +| | || (HARQ | | | | | +| | || Parameters| | | | | +| | || for | | | | | +| | || Congestion| | | | | +| | || Window | | | | | +| | || mana | | | | | +| | | gement) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbt || Not | N | N | N | +| | || CWConfig_T|| supported | | | | +| | || (TB | | | | | +| | | Parameters | | | | | +| | || for | | | | | +| | || Congestion| | | | | +| | || Window | | | | | +| | || mana | | | | | +| | | gement) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtTr || Not | N | N | N | +| | | afficClass || supported | | | | +| | || (Traffic | | | | | +| | || class | | | | | +| | || priority | | | | | +| | || for | | | | | +| | || Congestion| | | | | +| | || Window | | | | | +| | || mana | | | | | +| | | gement) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || lbtCWR_Rst|| Not | N | N | N | +| | || (Noti || supported | | | | +| | | cation | | | | | +| | || about | | | | | +| | || packet | | | | | +| | || reception | | | | | +| | || successful| | | | | +| | || or not) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || reserved | 0 | N | N | N | +| | || (reserved | | | | | +| | || for future| | | | | +| | || use) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || *Section* |   |   |   |   | +| | || *Exten* | | | | | +| | | *sion* | | | | | +| | || *Commands*| | | | | +| | +------------+------------+-----+-----+-----+ +| | || extType | Supported | Y | Y | N | +| | || (extension| | | | | +| | || type) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || ef | Supported | Y | Y | N | +| | | (extension | | | | | +| | || flag) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || extLen | Supported | Y | Y | N | +| | || (extension| | | | | +| | || length) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || Coding of |   |   |   |   | | +| || Infor | | | | | | +| | mation | | | | | | +| || Elements –| | | | | | +| || Appli | | | | | | +| | cation | | | | | | +| || Layer, | | | | | | +| || Section | | | | | | +| || Exten | | | | | | +| | sions | | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || | | | | | | +| || *Ext*\ | bfw | Supported | Y | Y | N | +| || *Type=1:* | CompHdr | | | | | +| | | | | | | | +| || *Beam* || \(bea | | | | | +| | | | | | | | +| || *forming* | forming | | | | | +| | | | | | | | +| || *Weights* || weight | | | | | +| || *Exten* || compre | | | | | +| | *sion* || ssion | | | | | +| || *Type* | header) | | | | | +| || +------------+------------+-----+-----+-----+ +| || || | | | | | +| || || bf | Supported | Y | Y | N | +| || | wCompParam | | | | | +| || || (beam | | | | | +| || | forming | | | | | +| || || weight | | | | | +| || || compre | | | | | +| || | ssion | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfwl | Supported | Y | Y | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || weight | | | | | +| || || in-phase | | | | | +| || || value) | | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfwQ | Supported | Y | Y | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || weight | | | | | +| || || quadrature| | | | | +| || || value) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || || bfaCompHdr| Supported | Y | N | N | +| || *ExtType*\|| | | | | | +| || *=2:* || (beam | | | | | +| || *Beam* | forming | | | | | +| | *forming* || attributes| | | | | +| || *Attribu* || compre | | | | | +| | *tes* | ssion | | | | | +| || *Exten* || header) | | | | | +| || *sion* | | | | | | +| || *Type* | | | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfAzPt | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || azimuth | | | | | +| || || pointing | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfZePt | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || zenith | | | | | +| || || pointing | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfAz3dd | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || azimuth | | | | | +| || || beamwidth | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfZe3dd | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || zenith | | | | | +| || || beamwidth | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfAzSl | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || azimuth | | | | | +| || || sidelobe | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || bfZeSl | Supported | Y | N | N | +| || || (beam | | | | | +| || | forming | | | | | +| || || zenith | | | | | +| || || sidelobe | | | | | +| || || parameter)| | | | | +| || +------------+------------+-----+-----+-----+ +| || || zero- | Supported | Y | N | N | +| || | padding | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || || code\ | Supported | Y | N | N | +| || *ExtType* || bookIndex | | | | | +| || *=3:* || | | | | | +| || *DL* || (precoder | | | | | +| || *Preco* || codebook | | | | | +| | *ding* || | | | | | +| || *Exten* || used for | | | | | +| | *sion* || trans | | | | | +| || *Type* | mission | | | | | +| | | | | | | | +| || +------------+------------+-----+-----+-----+ +| || || layerID | Supported | Y | N | N | +| || || (Layer ID | | | | | +| || || for DL | | | | | +| || || trans | | | | | +| || | mission) | | | | | +| || +------------+------------+-----+-----+-----+ +| || || txScheme | Supported | Y | N | N | +| || || (trans | | | | | +| || | mission | | | | | +| || || scheme) | | | | | +| || +------------+------------+-----+-----+-----+ +| || || numLayers | Supported | Y | N | N | +| || || (number of| | | | | +| || || layers | | | | | +| || || used for | | | | | +| || || DL | | | | | +| || || trans | | | | | +| || | mission) | | | | | +| || +------------+------------+-----+-----+-----+ +| || || crsReMask | Supported | Y | N | N | +| || || (CRS | | | | | +| || || resource | | | | | +| || || element | | | | | +| || || mask) | | | | | +| || +------------+------------+-----+-----+-----+ +| | || crs\ | Supported | Y | N | N | +| | || SyumINum | | | | | +| | || (CRS | | | | | +| | || symbol | | | | | +| | || number | | | | | +| | || indi | | | | | +| | | cation) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || crsShift | Supported | Y | N | N | +| | || (crsShift | | | | | +| | || used for | | | | | +| | || DL | | | | | +| | || trans | | | | | +| | | mission) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || beamIdAP1 | Supported | Y | N | N | +| | || (beam id | | | | | +| | || to be used| | | | | +| | || for | | | | | +| | || antenna | | | | | +| | || port 1) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || beamIdAP2 | Supported | Y | N | N | +| | || (beam id | | | | | +| | || to be used| | | | | +| | || for | | | | | +| | || antenna | | | | | +| | || port 2) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || beamIdAP3 | Supported | Y | N | N | +| | || (beam id | | | | | +| | || to be used| | | | | +| | || for | | | | | +| | || antenna | | | | | +| | || port 3) | | | | | +| | | | | | | | +| +------------+------------+------------+-----+-----+-----+ +| | || csf || Supported | Y | Y | N | +| || *ExtType*\|| (cons || | | | | +| || *=4:* | tellation || | | | | +| || *Modula* || shift | | | | | +| | *tion* || flag) | | | | | +| || *Compre* || | | | | | +| | *ssion* || | | | | | +| || *Parame* || | | | | | +| | *ters* || | | | | | +| || *Exten* || | | | | | +| | *sion* | | | | | | +| || *Type* || | | | | | +| | +------------+------------+-----+-----+-----+ +| | || mod || Supported | Y | Y | N | +| | || CompScaler|| | | | | +| | || ( || | | | | +| | || modulation|| | | | | +| | || compre || | | | | +| | | ssion || | | | | +| | || scaler || | | | | +| | | value) || | | | | +| +------------+------------+------------+-----+-----+-----+ +| || || mcScale\ || Supported | Y | N | N | +| || *ExtType*\|| ReMask || | | | | +| || *=5:* || ( || | | | | +| || *Modula* || modulation|| | | | | +| | *tion* || compre || | | | | +| || *Compre* | ssion || | | | | +| | *ssion* || power || | | | | +| || *Additio* || RE || | | | | +| || *Parame* || mask) || | | | | +| || *ters* | || | | | | +| || *Exten* || | | | | | +| | *sion* || | | | | | +| || Type* | || | | | | +| | +------------+------------+-----+-----+-----+ +| | || csf || Supported | Y | N | N | +| | || (cons || | | | | +| | | tellation || | | | | +| | || shift || | | | | +| | || flag) || | | | | +| | +------------+------------+-----+-----+-----+ +| | || mcScale\ | Supported | Y | N | N | +| | || Offset | | | | | +| | || (scaling | | | | | +| | || value for | | | | | +| | || modulation| | | | | +| | || compre | | | | | +| | | ssion) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || *E* || rbgSize | Supported | Y | N | N | +| | *xtType=6:*|| (resource | | | | | +| || *Non-con* || block | | | | | +| | *tiguous* || group | | | | | +| || *PRB* || size) | | | | | +| || *alloca* | | | | | | +| | *tion in* | | | | | | +| || *time and*| | | | | | +| || *frequen* | | | | | | +| | *cy domain*| | | | | | +| | +------------+------------+-----+-----+-----+ +| | || rbgMask | Supported | Y | N | N | +| | || (resource | | | | | +| | || block | | | | | +| | || group bit | | | | | +| | || mask) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || symbol\ | Supported | Y | N | N | +| | || Mask | | | | | +| | || (symbol | | | | | +| | || bit mask) | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || *Ext* | beam | Supported | Y | N | N | +| | *Type=10:* | GroupType | | | | | +| || *Section* | | | | | | +| || *des* | | | | | | +| | *cription* | | | | | | +| || *for gro* | | | | | | +| | *up* | | | | | | +| || *configu* | | | | | | +| | *ration of*| | | | | | +| || *multiple*| | | | | | +| || *ports* | | | | | | +| | | | | | | | +| | +------------+------------+-----+-----+-----+ +| | | numPortc | Supported | Y | N | N | +| | | | | | | | +| +------------+------------+------------+-----+-----+-----+ +| || *Ext* || b | Supported | Y | Y | N | +| | *Type=11:* | fwCompHdr | | | | | +| || *Flexible*|| (beam | | | | | +| || *Beam* | forming | | | | | +| | *forming* || weight | | | | | +| || *Weights* || compre | | | | | +| || *Exten* | ssion | | | | | +| | *sion* | | | | | | +| || *Type* || header) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || bfw | Supported | Y | Y | N | +| | || CompParam | | | | | +| | || for PRB | | | | | +| | || bundle x | | | | | +| | || (beam | | | | | +| | | forming | | | | | +| | || weight | | | | | +| | || compre | | | | | +| | | ssion | | | | | +| | || parameter)| | | | | +| | +------------+------------+-----+-----+-----+ +| | || numBund | Supported | Y | Y | N | +| | | Prb | | | | | +| | || (Number | | | | | +| | || of | | | | | +| | || bundled | | | | | +| | || PRBs per | | | | | +| | || beam | | | | | +| | | forming | | | | | +| | || weights) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || bfwI | Supported | Y | Y | N | +| | || (beam | | | | | +| | | forming | | | | | +| | || weight | | | | | +| | || in-phase | | | | | +| | || value) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || bfwQ | Supported | Y | Y | N | +| | || (beam | | | | | +| | | forming | | | | | +| | || weight | | | | | +| | || quadra | | | | | +| | | ture | | | | | +| | || value) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || disable\ | Supported | Y | Y | N | +| | || BFWs | | | | | +| | || (disable | | | | | +| | || beam | | | | | +| | | forming | | | | | +| | || weights) | | | | | +| | +------------+------------+-----+-----+-----+ +| | || RAD | Supported | Y | Y | N | +| | || (Reset | | | | | +| | || After PRB | | | | | +| | || Discon | | | | | +| | | tinuity) | | | | | +| | | | | | | | ++------------+------------+------------+------------+-----+-----+-----+ +|| U-plane || data\ | Supported | Y | Y | Y | +|| Packet || Direction | | | | | +|| Format || (data | | | | | +| || direction | | | | | +| || (gNB | | | | | +| || Tx/Rx)) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || payload\ | 001b | Y | Y | Y | +| || Version | | | | | +| || (payload | | | | | +| || version) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || filter\ | Supported | Y | Y | Y | +| || Index | | | | | +| || (filter | | | | | +| || index) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || frameId | Supported | Y | Y | Y | +| || (frame | | | | | +| || iden | | | | | +| | tifier) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || subframeId | Supported | Y | Y | Y | +| || (subframe | | | | | +| || iden | | | | | +| | tifier) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || slotId | Supported | Y | Y | Y | +| || (slot | | | | | +| || iden | | | | | +| | tifier) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || symbolId | Supported | Y | Y | Y | +| || (symbol | | | | | +| || iden | | | | | +| | tifier) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || sectionId | Supported | Y | Y | Y | +| || (section | | | | | +| || iden | | | | | +| | tifier) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || rb | 0 | Y | Y | Y | +| || (resource | | | | | +| || block | | | | | +| || indicator) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || symInc | 0 | Y | Y | Y | +| || (symbol | | | | | +| || number | | | | | +| || increment | | | | | +| || command) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || startPrbu | Supported | Y | Y | Y | +| || (startingPRB | | | | | +| || of user | | | | | +| || plane | | | | | +| || section) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || numPrbu | Supported | Y | Y | Y | +| || (number of | | | | | +| || PRBs per | | | | | +| || user plane | | | | | +| || section) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || udCompHdr | Supported | Y | Y | N | +| || (user data | | | | | +| || com | | | | | +| | pression | | | | | +| || header) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || reserved | 0 | Y | Y | Y | +| || (reserved | | | | | +| || for future | | | | | +| || use) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || udCompParam | Supported | Y | Y | N | +| || (user data | | | | | +| || compre | | | | | +| | ssion | | | | | +| || parameter) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || iSample | 16 | Y | Y | Y | +| || (in-phase | | | | | +| | sample) | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || qSample | 16 | Y | Y | Y | +| || ( | | | | | +| | quadrature | | | | | +| | sample) | | | | | +| | | | | | | ++------------+-------------------------+------------+-----+-----+-----+ +| S-plane || Topology | Supported | N | N | N | +| || confi | | | | | +| | guration: | | | | | +| || C1 | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Topology | Supported | N | N | N | +| || confi | | | | | +| | guration: | | | | | +| || C2 | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Topology | Supported | Y | Y | Y | +| || confi | | | | | +| | guration: | | | | | +| || C3 | | | | | +| +-------------------------+------------+-----+-----+-----+ +| || Topology | Supported | N | N | N | +| || confi | | | | | +| | guration: | | | | | +| || C4 | | | | | +| | | | | | | ++ +------------+------------+------------+-----+-----+-----+ +| | PTP || Full | Supported | Y | Y | N | +| | || Timing | | | | | +| | || Support | | | | | +| | || (G.8275.1)| | | | | +| | | | | | | | ++------------+------------+------------+------------+-----+-----+-----+ +| M-plane |   |   || Not | N | N | N | +| | | || supported | | | | +| | | | | | | | ++------------+------------+------------+------------+-----+-----+-----+ \* The bit width of each component in eAxC ID can be configurable. Transport Layer --------------- -ORAN Fronthaul data can be transported over Ethernet or IPv4/IPv6. In -the current implementation, the xRAN library supports only Ethernet with +O-RAN Fronthaul data can be transported over Ethernet or IPv4/IPv6. In +the current implementation, the O-RAN library supports only Ethernet with VLAN. .. image:: images/Native-Ethernet-Frame-with-VLAN.jpg @@ -1150,7 +1265,7 @@ Standard DPDK routines are used to perform Transport Layer functionality. VLAN tag functionality is offloaded to NIC as per the configuration of -VF (refer to Appendix Appendix 1). +VF (refer to Setup Configuration). The transport header is defined in the ORAN Fronthaul specification based on the eCPRI specification. @@ -1164,14 +1279,63 @@ Figure 12. eCPRI Header Field Definitions Only ECPRI_IQ_DATA = 0x00 and ECPRI_RT_CONTROL_DATA= 0x02 message types are supported. +For one-way delay measurements the eCPRI Header Field Definitions are +the same as above until the ecpriPayload. The one-delay measurement +message format is shown in the next figure. + +.. image:: images/ecpri-one-way-delay-measurement-message.jpg + :width: 600 + :alt: Figure 13. ecpri one-way delay measurement message + +Figure 13. ecpri one-way delay measurement message + +In addition, for the eCPRI one-delay measurement message there is a +requirement of dummy bytes insertion so the overall ethernet frame has +at least 64 bytes. + +The measurement ID is a one-byte value used by the sender of the request +to distinguish the response received between different measurements. + +The action type is a one-byte value defined in Table 8 of the eCPRI +Specification V2.0. + +Action Type 0x00 corresponds to a Request + +Action Type 0x01 corresponds to a Request with Follow Up + +Both values are used by an eCPRI node to initiate a one-way delay +measurement in the direction of its own node to another node. + +Action Type 0x02 corresponds to a Response + +Action Type 0x03 is a Remote Request + +Action Type 0x04 is a Remote Request with Follow Up + +Values 0x03 and 0x04 are used when an eCPRI node needs to know the +one-way delay from another node to itself. + +Action Type 0x05 is the Follow_Up message. + +The timestamp uses the IEEE-1588 Timestamp format with 8 bytes for the +seconds part and 4 bytes for the nanoseconds part. The timestamp is a +positive time with respect to the epoch. + +The compensation value is used with Action Types 0x00 (Request), 0x02 +(Response) or 0x05 (Follow_up) for all others this field contains zeros. +This value is the compensation time measured in nanoseconds and +multiplied by 2\ :sup:16 and follows the format for the +correctionField in the common message header specified by the IEE +1588-2008 clause 13.3. + Handling of ecpriRtcid/ecpriPcid Bit field size is configurable and can -be defined on the initialization stage of the xRAN library. +be defined on the initialization stage of the O-RAN library. .. image:: images/Bit-Allocations-of-ecpriRtcid-ecpriPcid.jpg :width: 600 - :alt: Figure 13. Bit Allocations of ecpriRtcid/ecpriPcid + :alt: Figure 14. Bit Allocations of ecpriRtcid/ecpriPcid -Figure 13. Bit Allocations of ecpriRtcid/ecpriPcid +Figure 14. Bit Allocations of ecpriRtcid/ecpriPcid For ecpriSeqid only, the support for a sequence number is implemented. The subsequent number is not supported. @@ -1179,24 +1343,24 @@ The subsequent number is not supported. U-plane ------- -The following diagrams show xRAN packet protocols’ headers and data +The following diagrams show O-RAN packet protocols’ headers and data arrangement with and without compression support. -XRAN packet meant for traffic with compression enabled has the +O-RAN packet meant for traffic with compression enabled has the Compression Header added after each Application Header. According to -ORAN Fronthaul's specification, the Compression Header is part of a -repeated Section Application Header. In the xRAN library implementation, +O-RAN Fronthaul's specification, the Compression Header is part of a +repeated Section Application Header. In the O-RAN library implementation, the header is implemented as a separate structure, following the Application Section Header. As a result, the Compression Header is not -included in the xRAN packet, if compression is not used. +included in the O-RAN packet, if compression is not used. -Figure 14 shows the components of an xRAN packet. +Figure 15 shows the components of an ORAN packet. .. image:: images/xRAN-Packet-Components.jpg :width: 600 - :alt: Figure 14. xRAN Packet Components + :alt: Figure 15. O-RAN Packet Components -Figure 14. xRAN Packet Components +Figure 15. O-RAN Packet Components Radio Application Header ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1205,9 +1369,9 @@ The next header is a common header used for time reference. .. image:: images/Radio-Application-Header.jpg :width: 600 - :alt: Figure 15. Radio Application Header + :alt: Figure 16. Radio Application Header -Figure 15. Radio Application Header +Figure 16. Radio Application Header The radio application header specific field values are implemented as follows: @@ -1227,13 +1391,13 @@ Data Section Application Data Header The Common Radio Application Header is followed by the Application Header that is repeated for each Data Section within the eCPRI message. -The relevant section of xRAN packet is shown in color. +The relevant section of O-RAN packet is shown in color. .. image:: images/Data-Section-Application-Data-Header.jpg :width: 600 - :alt: Figure 16. Data Section Application Data Header + :alt: Figure 17. Data Section Application Data Header -Figure 16. Data Section Application Data Header +Figure 17. Data Section Application Data Header A single section is used per one Ethernet packet with IQ samples @@ -1246,7 +1410,7 @@ startPrbu is equal to 0 and numPrbu is wqual to the number of RBs used: Data Payload ~~~~~~~~~~~~ -An xRAN packet data payload contains a number of PRBs. Each PRB is built +An O-RAN packet data payload contains a number of PRBs. Each PRB is built of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour. .. image:: images/Data-Payload.jpg @@ -1306,7 +1470,7 @@ Section extensions are not supported in this release. The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h and the fields are appropriately re-ordered in order to apply the conversion of network byte order after setting values. -The comments in source code of xRAN lib can be used to see more information on +The comments in source code of O-RAN lib can be used to see more information on implementation specifics of handling sections as well as particular fields. Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario. @@ -1331,9 +1495,9 @@ structure is shown in Figure 18. .. image:: images/Radio-Application-Common-Header.jpg :width: 600 - :alt: Figure 18. Radio Application Common Header + :alt: Figure 19. Radio Application Common Header -Figure 18. Radio Application Common Header +Figure 19. Radio Application Common Header This header is defined as the structure of xran_cp_radioapp_common_header in lib/api/xran_pkt_cp.h. @@ -1344,28 +1508,28 @@ XRAN_PAYLOAD_VER (defined as 1) in this release. Section Type 0 Structure ~~~~~~~~~~~~~~~~~~~~~~~~ -Figure 19 describes the structure of Section Type 0. +Figure 20 describes the structure of Section Type 0. .. image:: images/Section-Type-0-Structure.jpg :width: 600 - :alt: Figure 19. Section Type 0 Structure + :alt: Figure 20. Section Type 0 Structure -Figure 19. Section Type 0 Structure +Figure 20. Section Type 0 Structure -In Figure 18 through Figure 22, the color yellow means it is a transport +In Figure 19 through Figure 23, the color yellow means it is a transport header; the color pink is the radio application header; others are repeated sections. Section Type 1 Structure ~~~~~~~~~~~~~~~~~~~~~~~~ -Figure 20 describes the structure of Section Type 1. +Figure 21 describes the structure of Section Type 1. .. image:: images/Section-Type-1-Structure.jpg :width: 600 - :alt: Figure 20. Section Type 1 Structure + :alt: Figure 21. Section Type 1 Structure -Figure 20. Section Type 1 Structure +Figure 21. Section Type 1 Structure Section Type 1 message has two additional parameters in addition to radio application common header: @@ -1394,13 +1558,13 @@ Whole section type 1 message can be described in this summary: Section Type 3 Structure ~~~~~~~~~~~~~~~~~~~~~~~~ -Figure 21 describes the structure of Section Type 3. +Figure 22 describes the structure of Section Type 3. .. image:: images/Section-Type-3-Structure.jpg :width: 600 - :alt: Figure 21. Section Type 3 Structure + :alt: Figure 22. Section Type 3 Structure -Figure 21. Section Type 3 Structure +Figure 22. Section Type 3 Structure Section Type 3 message has below four additional parameters in addition to radio application common header. @@ -1434,23 +1598,23 @@ Whole section type 3 message can be described in this summary: Section Type 5 Structure ~~~~~~~~~~~~~~~~~~~~~~~~ -Figure 22 describes the structure of Section Type 5. +Figure 23 describes the structure of Section Type 5. .. image:: images/Section-Type-5-Structure.jpg :width: 600 - :alt: Figure 22. Section Type 5 Structure + :alt: Figure 23. Section Type 5 Structure -Figure 22. Section Type 5 Structure +Figure 23. Section Type 5 Structure Section Type 6 Structure ~~~~~~~~~~~~~~~~~~~~~~~~ -Figure 23 describes the structure of Section Type 6. +Figure 24 describes the structure of Section Type 6. .. image:: images/Section-Type-6-Structure.jpg :width: 600 - :alt: Figure 23. Section Type 6 Structure + :alt: Figure 24. Section Type 6 Structure -Figure 23. Section Type 6 Structure +Figure 24. Section Type 6 Structure diff --git a/docs/build_prerequisite.rst b/docs/build_prerequisite.rst index 411bb55..945d73e 100644 --- a/docs/build_prerequisite.rst +++ b/docs/build_prerequisite.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -65,10 +65,10 @@ Download and Build DPDK ----------------------- - download DPDK:: - #wget http://static.dpdk.org/rel/dpdk-19.11.tar.x - #tar -xf dpdk-19.11.tar.xz + #wget http://static.dpdk.org/rel/dpdk-20.11.tar.x + #tar -xf dpdk-20.11.tar.xz #export RTE_TARGET=x86_64-native-linuxapp-icc - #export RTE_SDK=Intallation_DIR/dpdk-19.11 + #export RTE_SDK=Intallation_DIR/dpdk-20.11 - patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to |br| O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites @@ -86,8 +86,8 @@ Download and Build DPDK - set DPDK path DPDK path is needed during build and run lib/app:: - #export RTE_SDK=Installation_DIR/dpdk-19.11 - #export DESTDIR=Installation_DIR/dpdk-19.11 + #export RTE_SDK=Installation_DIR/dpdk-20.11 + #export DESTDIR=Installation_DIR/dpdk-20.11 Install google test @@ -116,7 +116,8 @@ Download google test from https://github.com/google/googletest/releases Configure FEC card -------------------- -For the Bronze Release only a SW FEC is available so this step is not needed, for later releases the required information will be added to the document. +For the E Maintenance Release either a SW FEC, or an FPGA FEC (Vista Creek N3000) or an ASIC FEC (Mount Bryce ACC100) can be used. +The procedure to configure the HW based FECs is explained below. Customize a setup environment shell script ------------------------------------------ diff --git a/docs/ecpri_ddp_profile.rst b/docs/ecpri_ddp_profile.rst new file mode 100644 index 0000000..cc8ab17 --- /dev/null +++ b/docs/ecpri_ddp_profile.rst @@ -0,0 +1,875 @@ +.. Copyright (c) 2019-2022 Intel +.. +.. Licensed under the Apache License, Version 2.0 (the "License"); +.. you may not use this file except in compliance with the License. +.. You may obtain a copy of the License at +.. +.. http://www.apache.org/licenses/LICENSE-2.0 +.. +.. Unless required by applicable law or agreed to in writing, software +.. distributed under the License is distributed on an "AS IS" BASIS, +.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +.. See the License for the specific language governing permissions and +.. limitations under the License. + + +eCPRI DDP Profile for Columbiaville (Experimental Feature) +========================================================== + +.. _introduction-3: + +Introduction +============ + +The Intel® Ethernet 800 Series is the next generation of Intel® Ethernet +Controllers and Network Adapters. The Intel® Ethernet 800 Series is +designed with an enhanced programmable pipeline, allowing deeper and +more diverse protocol header processing. This on-chip capability is +called Dynamic Device Personalization (DDP). In the Intel® Ethernet 800 +Series, a DDP profile is loaded dynamically on driver load per device. + +A general-purpose DDP package is automatically installed with all +supported Intel® Ethernet 800 Series drivers on Windows*, ESX*, +FreeBSD*, and Linux\* operating systems, including those provided by the +Data Plane Development Kit (DPDK). This general-purpose DDP package is +known as the OS-default package. + +For more information on DDP technology in the Intel® Ethernet 800 Series +products and the OS-default package, refer to the Intel® Ethernet +Controller E810 Dynamic Device Personalization (DDP) Technology Guide, +published here: https://cdrdv2.intel.com/v1/dl/getContent/617015. + +This document describes an optional DDP package targeted towards the +needs of Wireless and Edge (Wireless Edge) customers. This Wireless Edge +DDP package (v1.3.22.101) adds support for eCPRI protocols in addition +to the protocols in the OS-default package. The Wireless Edge DDP +package is supported by DPDK. + +Starting from DPDK 21.02 drivers and in the future will also be +supported by the Intel® Ethernet 800 Series ice driver. on Linux +operating systems. The Wireless DDP Package can be loaded on all Intel® +Ethernet 800 Series devices, or different packages can be selected via +serial number per device. + +Software/Firmware Requirements +============================== + +The specific DDP package requires certain firmware and DPDK versions and +Intel® Ethernet 800 Series firmware/NVM versions. Support for eCPRI DDP +profile included starting from Columbiaville (CVL)release 2.4 or later. +The required DPDK version contains the support of loading the specific +Wireless Edge DDP package. + +- Intel® Ethernet 800 Series Linux Driver (ice) — 1.4.0 (or later) + +- Wireless Edge DDP Package version (ice_wireless_edge) — 1.3.22.101 + +- Intel® Ethernet 800 Series firmware version — 1.5.4.2 (or later) + +- Intel® Ethernet 800 Series NVM version — 2.4 (or later) + +- DPDK version— 21.02 (or later) + +- For FlexRAN release 21.03, corresponding support of CVL 2.4 driver pack and DPDK 21.02 is “experimental” and subject to additional testing and potential changes. + +DDP Package Setup +================= + +The Intel® Ethernet 800 Series Comms DDP package supports only +Linux-based operating systems currently. + +Currently, the eCPRI is fully supported only by DPDK 21.02. It can be +loaded either by DPDK or the Intel® Ethernet 800 Series Linux base +driver. + +Wireless Edge DDP Package +========================= + +For details on how to set up DPDK, refer to Intel® Ethernet Controller +E810 Data Plane Development Kit (DPDK) Configuration Guide (Doc ID: +633514). + +There are two methods where DDP package can be loaded and used under +DPDK (see Section C.3.2 and +Section C.3.2 ). For both methods, the +user must obtain the ice_wireless_edge-1.3.22.101.pkg or later from +Intel (please contact your Intel representative for more information) + +Option 1: *ice* Linux Base Driver +================================= + +The first option is to have the ice Linux base driver load the package. + +The *ice* Linux base driver looks for the symbolic link +*intel/ice/ddp/ice.pkg* under the default firmware search path, checking +the following folders in order: + +- */lib/firmware/updates/* + +- */lib/firmware/* + +To install the Comms package, copy the extracted .pkg file and its +symbolic link to */lib/firmware/updates/intel/ice/ddp* as follows, and +reload the ice driver:: + + # cp /usr/tmp/ice_wireless_edge-1.3.22.101.pkg /lib/firmware/updates/intel/ice/ddp/ + # ln -sf /lib/firmware/updates/intel/ice/ddp/ice_wireless_edge-1.3.22.101.pkg /lib/firmware/updates/intel/ice/ddp/ice.pkg + # modprobe -r irdma + # modprobe -r ice + # modprobe ice + + +The kernel message log (*dmesg*) indicates status of package loading in +the system. If the driver successfully finds and loads the DDP package, +*dmesg* indicates that the DDP package successfully loaded. If not, the +driver transitions to safe mode. + +Once the driver loads the package, the user can unbind the *ice* driver +from a desired port on the device so that DPDK can utilize the port. + +The following example unbinds Port 0 and Port 1 of device on Bus 6, +Device 0. Then, the port is bound to either igb_uio or vfio-pci. :: + + # ifdown + # dpdk-devbind -u 06:00.0 + # dpdk-devbind -u 06:00.1 + # dpdk-devbind -b igb_uio 06:00.0 06:00.1 + +Option 2: DPDK Driver Only +========================== + +The second method is if the system does not have the *ice* driver +installed. In this case, the user can download the DDP package from the +Intel download center and extract the zip file to obtain the package +(*.pkg*) file. Similar to the Linux base driver, the DPDK driver looks +for the *intel/ddp/ice.pkg* symbolic link in the kernel default firmware +search path */lib/firmware/updates and /lib/firmware/*. + +Copy the extracted DDP *.pkg* file and its symbolic link to +*/lib/firmware/intel/ice/ddp*, as follows. :: + + # cp /usr/tmp/ice_wireless_edge-1.3.22.101 /lib/firmware/intel/ice/ddp/ + # cp /usr/tmp/ice.pkg /lib/firmware/intel/ice/ddp/ + +When DPDK driver loads, it looks for *ice.pkg* to load. If the file +exists, the driver downloads it into the device. If not, the driver +transitions into safe mode. + +Loading DDP Package to a Specific Intel® Ethernet 800 Series Device +=================================================================== + +On a host system running with multiple Intel® Ethernet 800 Series +devices, there is sometimes a need to load a specific DDP package on a +selected device while loading a different package on the remaining +devices. + +The Intel® Ethernet 800 Series Linux base driver and DPDK driver can +both load a specific DDP package to a selected adapter based on the +device's serial number. The driver does this by looking for a specific +symbolic link package filename containing the selected device's serial +number. + +The following example illustrates how a user can load a specific package +(e.g., *ice_wireless_edge-1.3.22.101*) on the device of Bus 6. + +1. Find device serial number. + +.. + +To view bus, device, and function of all Intel® Ethernet 800 Series +Network Adapters in the system::: + + # lspci | grep -i Ethernet | grep -i Intel + 06:00.0 Ethernet controller: Intel Corporation Ethernet Controller E810-C for QSFP (rev 01) + 06:00.1 Ethernet controller: Intel Corporation Ethernet Controller E810-C for QSFP (rev 01) + 82:00.0 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01) + 82:00.1 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01) + 82:00.2 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01) + 82:00.3 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01) + +Use the **lspci** command to obtain the selected device serial +number::: + + # lspci -vv -s 06:00.0 \| grep -i Serial + Capabilities: [150 v1] Device Serial Number 35-11-a0-ff-ff-ca-05-68 + +Or, fully parsed without punctuation::: + + # lspci -vv -s 06:00.0 \|grep Serial \|awk '{print $7}'|sed s/-//g + 3511a0ffffca0568 + +2. Rename the package file with the device serial number in the name. + +.. + +Copy the specific package over to /lib/firmware/updates/intel/ice/ddp +(or /lib/firmware/intel/ice/ ddp) and create a symbolic link with the +serial number linking to the package, as shown. The specific symbolic +link filename starts with “ice-” followed by the device serial in +lower case without dash ('-'). :: + + # ln -s + /lib/firmware/updates/intel/ice/ddp/ice_wireless_edge-1.3.22.101.pkg + /lib/firmware/updates/intel/ice/ddp/ice-3511a0ffffca0568.pkg + +3. If using Linux kernel driver (*ice*), reload the base driver (not +required if using only DPDK driver). :: + + # rmmod ice + # modprobe ice + +The driver loads the specific package to the selected device and the +OS-default package to the remaining Intel® Ethernet 800 Series +devices in the system. + +4. Verify. + +For kernel driver: +================== + +Example of output of successful load of Wireless Edge Package to all +devices::: + + # dmesg | grep -i "ddp \| safe" + [606960.921404] ice 0000:18:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101 + [606961.672999] ice 0000:18:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + [606962.439067] ice 0000:18:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + [606963.198305] ice 0000:18:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + [606964.252076] ice 0000:51:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101 + [606965.017082] ice 0000:51:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + [606965.802115] ice 0000:51:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + [606966.576517] ice 0000:51:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101 + + +If using only DPDK driver: +========================== + +Verify using DPDK's **testpmd** application to indicate the status +And version of the loaded DDP package. + +Example of eCPRI config with dpdk-testpmd +----------------------------------------- + +16 O-RAN eCPRI IQ streams mapped to 16 independent HW queues each.:: + + #./dpdk-testpmd -l 22-25 -n 4 -a 0000:af:01.0 -- -i --rxq=16 --txq=16 --cmdline-file=/home/flexran_xran/ddp.txt + + cat /home/flexran_xran/ddp.txt + port stop 0 + port config mtu 0 9600 + port config 0 rx_offload vlan_strip on + port start 0 + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0000 / end actions queue index 0 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0001 / end actions queue index 1 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0002 / end actions queue index 2 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0003 / end actions queue index 3 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0004 / end actions queue index 4 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0005 / end actions queue index 5 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0006 / end actions queue index 6 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0007 / end actions queue index 7 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0008 / end actions queue index 8 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0009 / end actions queue index 9 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000a / end actions queue index 10 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000b / end actions queue index 11 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000c / end actions queue index 12 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000d / end actions queue index 13 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000e / end actions queue index 14 / mark / end + flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000f / end actions queue index 15 / mark / end + set fwd rxonly + start + show fwd stats all + + +O-RAN Front haul eCPRI +====================== + +Intel® Ethernet 800 Series DDP capabilities support several +functionalities important for the O-RAN FH. + +- RSS for packet steering based on ecpriMessage + +- RSS for packet steering based on ecpriRtcid/ecpriPcid + +- Queue mapping based on ecpriRtcid/ecpriPcid + +- Queue mapping based on ecpriMessage + +.. image:: images/O-RAN-FH-VNF.jpg + :width: 400 + :alt: Figure . O-RAN FH VNF + +Figure 30. O-RAN FH VNF + +Table 13. Patterns & Input Sets for Flow Director and RSS (DPDK 21.02) + +============================= ======================================== +Pattern Input Set +============================= ======================================== +ETH / VLAN / eCPRI ecpriMessage \| ecpriRtcid/ecpriPcid +ETH / VLAN /IPv4(6)/UDP/eCPRI ecpriMessage \| ecpriRtcid/ecpriPcid (*) +============================= ======================================== + +*Note:* \* IP/UDP is not used with FlexRAN + +Limitations +=========== + +DPDK 21.02 allows up to 1024 queues per VF and RSS across up to 64 +receive queues. + +RTE Flow API +============ + +The DPDK Generic flow API (rte_flow) will be used to the configure the +Intel® Ethernet 800 Series to match specific ingress traffic and forward +it to specified queues. + +For further information, please refer to section 11 of the DPDK +Programmers +guide . + +The specific ingress traffic is identified by a matching pattern which +is composed of one or more Pattern items (represented by struct +rte_flow_item). Once a match has been determined one or more associated +Actions (represented by struct rte_flow_action) will be performed. + +A number of flow rules can be combined such that one rule directs +traffic to a queue group based on *ecpriMessage/ ecpriRtcid/ecpriPcid* +etc. and a second rule distributes matching packets within that queue +group using RSS. + +The following subset of the RTE Flow API functions can be used to +validate, create and destroy RTE Flow rules. + +RTE Flow Rule Validation +======================== + +A RTE Flow rule is created via a call to the function +*rte_flow_validate*. This can be used to check the rule for correctness +and whether it would be accepted by the device given sufficient +resources.:: + + int rte_flow_validate(uint16_t port_id, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action *actions[] + struct rte_flow_error *error); + + +port_id : port identifier of Ethernet device + +attr : flow rule attributes(ingress/egress) + +pattern : pattern specification (list terminated by the END pattern +item). + +action : associated actions (list terminated by the END action). + +error : perform verbose error reporting if not NULL. + +0 is returned upon success, negative errno otherwise. + +RTE Flow Rule Creation +====================== + +A RTE Flow rule is created via a call to the function *rte_flow_create*.:: + + struct rte_flow * rte_flow_create(uint16_t port_id, + const struct rte_flow_attr *attr, + const struct rte_flow_item pattern[], + const struct rte_flow_action *actions[] + struct rte_flow_error *error); + +port_id : port identifier of Ethernet device + +attr : flow rule attributes(ingress/egress) + +pattern : pattern specification (list terminated by the END pattern +item). + +action : associated actions (list terminated by the END action). + +error : perform verbose error reporting if not NULL. + +A valid handle is returned upon success, NULL otherwise. + +RTE Flow Rule Destruction +========================= + +A RTE Flow rule is destroyed via a call to the function +*rte_flow_destroy*.:: + + int rte_flow_destroy(uint16_t port_id, + struct rte_flow \*flow, + struct rte_flow_error \*error); + +port_id : port identifier of Ethernet device + +flow : flow rule handle to destroy. + +error : perform verbose error reporting if not NULL. + +0 is returned upon success, negative errno otherwise. + +RTE Flow Flush +============== + +All flow rule handles associated with a port can be released using +*rte_flow_flush*. They are released as with successive calls to function +*rte_flow_destroy*.:: + + int rte_flow_flush(uint16_t port_id, + struct rte_flow_error \*error); + +port_id : port identifier of Ethernet device + +error : perform verbose error reporting if not NULL. + +0 is returned upon success, negative errno otherwise. + +RTE Flow Query +============== + +A RTE Flow rule is queried via a call to the function *rte_flow_query*.:: + + int rte_flow_query(uint16_t port_id, + struct rte_flow *flow, + const struct rte_flow_action *action, + void *data, + struct rte_flow_error *error); + +port_id : port identifier of Ethernet device + +flow : flow rule handle to query + +action : action to query, this must match prototype from flow rule. + +data : pointer to storage for the associated query data type + +error : perform verbose error reporting if not NULL. + +0 is returned upon success, negative errno otherwise. + +RTE Flow Rules +============== + +A flow rule is the combination of attributes with a matching pattern and +a list of actions. Each flow rules consists of: + +- **Attributes (represented by struct rte_flow_attr):** properties of a flow rule such as its direction (ingress or egress) and priority. + +- **Pattern Items (represented by struct rte_flow_item):** is part of a matching pattern that either matches specific packet data or traffic properties. + +- **Matching pattern:** traffic properties to look for, a combination of any number of items. + +- **Actions (represented by struct rte_flow_action):** operations to perform whenever a packet is matched by a pattern. + +Attributes +========== + +Flow rule patterns apply to inbound and/or outbound traffic. For the +purposes described in later sections the rules apply to ingress only. +For further information, please refer to section 11 of the DPDK +Programmers guide .:: + + *struct*\ rte_flow_attr \ *{* + *uint32_t*\ group \ *;* + *uint32_t*\ priority \ *;* + *uint32_t*\ ingress \ *:1;* + *uint32_t*\ egress \ *:1;* + *uint32_t*\ transfer \ *:1;* + *uint32_t*\ reserved \ *:29;* + *};* + +Pattern items +============= + +For the purposes described in later sections Pattern items are primarily +for matching protocol headers and packet data, usually associated with a +specification structure. These must be stacked in the same order as the +protocol layers to match inside packets, starting from the lowest. + +Item specification structures are used to match specific values among +protocol fields (or item properties). + +Up to three structures of the same type can be set for a given item: + +- **spec:** values to match (e.g. a given IPv4 address). + +- **last:** upper bound for an inclusive range with corresponding fields in spec. + +- **mask:** bit-mask applied to both spec and last whose purpose is to distinguish the values to take into account and/or partially mask them out (e.g. in order to match an IPv4 address prefix). + +Table 14. Example RTE FLOW Item Types + ++-------------+---------------------------------------+-------------------------+ +| Item Type\* | Description | Specification Structure | ++=============+=======================================+=========================+ +| END | End marker for item lists | None | ++-------------+---------------------------------------+-------------------------+ +| VOID | Used as a placeholder for convenience | None | ++-------------+---------------------------------------+-------------------------+ +| ETH | Matches an Ethernet header | rte_flow_item_eth | ++-------------+---------------------------------------+-------------------------+ +| VLAN | Matches an 802.1Q/ad VLAN tag. | rte_flow_item_vlan | ++-------------+---------------------------------------+-------------------------+ +| IPV4 | Matches an IPv4 header | rte_flow_item_ipv4 | ++-------------+---------------------------------------+-------------------------+ +| IPV6 | Matches an IPv6 header | rte_flow_item_ipv6 | ++-------------+---------------------------------------+-------------------------+ +| ICMP | Matches an ICMP header. | rte_flow_item_icmp | ++-------------+---------------------------------------+-------------------------+ +| UDP | Matches an UDP header. | rte_flow_item_udp | ++-------------+---------------------------------------+-------------------------+ +| TCP | Matches a TCP header. | rte_flow_item_tcp | ++-------------+---------------------------------------+-------------------------+ +| SCTP | Matches a SCTP header. | rte_flow_item_sctp | ++-------------+---------------------------------------+-------------------------+ +| VXLAN | Matches a VXLAN header. | rte_flow_item_vxlan | ++-------------+---------------------------------------+-------------------------+ +| NVGRE | Matches a NVGRE header. | rte_flow_item_nvgre | ++-------------+---------------------------------------+-------------------------+ +| ECPRI | Matches ECPRI Header | rte_flow_item_ecpri | ++-------------+---------------------------------------+-------------------------+ + +:: + + RTE_FLOW_ITEM_TYPE_ETH + + struct rte_flow_item_eth { + struct rte_ether_addr dst; /**< Destination MAC. */ + struct rte_ether_addr src; /**< Source MAC. > */ + rte_be16_t type; /**< EtherType or TPID.> */ + }; + + struct rte_ether_addr { + uint8_t addr_bytes[RTE_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */ + } + +:: + + RTE_FLOW_ITEM_TYPE_IPV4 + + struct rte_flow_item_ipv4 { + struct rte_ipv4_hdr hdr; /**< IPv4 header definition. */ + }; + + struct rte_ipv4_hdr { + uint8_t version_ihl; /**< version and header length */ + uint8_t type_of_service; /**< type of service */ + rte_be16_t total_length; /**< length of packet */ + rte_be16_t packet_id; /**< packet ID */ + rte_be16_t fragment_offset; /**< fragmentation offset */ + uint8_t time_to_live; /**< time to live */ + uint8_t next_proto_id; /**< protocol ID */ + rte_be16_t hdr_checksum; /**< header checksum */ + rte_be32_t src_addr; /**< source address */ + rte_be32_t dst_addr; /**< destination address */ + } + + RTE_FLOW_ITEM_TYPE_UDP + + struct rte_flow_item_udp { + struct rte_udp_hdr hdr; /**< UDP header definition. */ + }; + + struct rte_udp_hdr { + rte_be16_t src_port; /**< UDP source port. */ + rte_be16_t dst_port; /**< UDP destination port. */ + rte_be16_t dgram_len; /**< UDP datagram length */ + rte_be16_t dgram_cksum; /**< UDP datagram checksum */ + } + + RTE_FLOW_ITEM_TYPE_ECPRI + + struct rte_flow_item_ecpri { + struct rte_ecpri_combined_msg_hdr hdr; + }; + + struct rte_ecpri_combined_msg_hdr { + struct rte_ecpri_common_hdr common; + union { + struct rte_ecpri_msg_iq_data type0; + struct rte_ecpri_msg_bit_seq type1; + struct rte_ecpri_msg_rtc_ctrl type2; + struct rte_ecpri_msg_bit_seq type3; + struct rte_ecpri_msg_rm_access type4; + struct rte_ecpri_msg_delay_measure type5; + struct rte_ecpri_msg_remote_reset type6; + struct rte_ecpri_msg_event_ind type7; + rte_be32_t dummy[3]; + }; + }; + struct rte_ecpri_common_hdr { + union { + rte_be32_t u32; /**< 4B common header in BE */ + struct { + #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t size:16; /**< Payload Size */ + uint32_t type:8; /**< Message Type */ + uint32_t c:1; /**< Concatenation Indicator */ + uint32_t res:3; /**< Reserved */ + uint32_t revision:4; /**< Protocol Revision */ + #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint32_t revision:4; /**< Protocol Revision */ + uint32_t res:3; /**< Reserved */ + uint32_t c:1; /**< Concatenation Indicator */ + uint32_t type:8; /**< Message Type */ + uint32_t size:16; /**< Payload Size */ + #endif + }; + }; + }; + /** + * eCPRI Message Header of Type #0: IQ Data + */ + struct rte_ecpri_msg_iq_data { + rte_be16_t pc_id; /**< Physical channel ID */ + rte_be16_t seq_id; /**< Sequence ID */ + }; + + /** + * eCPRI Message Header of Type #1: Bit Sequence + */ + struct rte_ecpri_msg_bit_seq { + rte_be16_t pc_id; /**< Physical channel ID */ + rte_be16_t seq_id; /**< Sequence ID */ + }; + + /** + * eCPRI Message Header of Type #2: Real-Time Control Data + */ + struct rte_ecpri_msg_rtc_ctrl { + rte_be16_t rtc_id; /**< Real-Time Control Data ID */ + rte_be16_t seq_id; /**< Sequence ID */ + }; + + /** + * eCPRI Message Header of Type #3: Generic Data Transfer + */ + struct rte_ecpri_msg_gen_data { + rte_be32_t pc_id; /**< Physical channel ID */ + rte_be32_t seq_id; /**< Sequence ID */ + }; + + /** + * eCPRI Message Header of Type #4: Remote Memory Access + */ + RTE_STD_C11 + struct rte_ecpri_msg_rm_access { + #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t ele_id:16; /**< Element ID */ + uint32_t rr:4; /**< Req/Resp */ + uint32_t rw:4; /**< Read/Write */ + uint32_t rma_id:8; /**< Remote Memory Access ID */ + #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint32_t rma_id:8; /**< Remote Memory Access ID */ + uint32_t rw:4; /**< Read/Write */ + uint32_t rr:4; /**< Req/Resp */ + uint32_t ele_id:16; /**< Element ID */ + #endif + uint8_t addr[6]; /**< 48-bits address */ + rte_be16_t length; /**< number of bytes */ + }; + + /** + * eCPRI Message Header of Type #5: One-Way Delay Measurement + */ + struct rte_ecpri_msg_delay_measure { + uint8_t msr_id; /**< Measurement ID */ + uint8_t act_type; /**< Action Type */ + }; + + /** + * eCPRI Message Header of Type #6: Remote Reset + */ + struct rte_ecpri_msg_remote_reset { + rte_be16_t rst_id; /**< Reset ID */ + uint8_t rst_op; /**< Reset Code Op */ + }; + + /** + * eCPRI Message Header of Type #7: Event Indication + */ + struct rte_ecpri_msg_event_ind { + uint8_t evt_id; /**< Event ID */ + uint8_t evt_type; /**< Event Type */ + uint8_t seq; /**< Sequence Number */ + uint8_t number; /**< Number of Faults/Notif */ + }; + + +Matching Patterns +================= + +A matching pattern is formed by stacking items starting from the lowest +protocol layer to match. Patterns are terminated by END pattern item. + +Actions +------- + +Each possible action is represented by a type. An action can have an +associated configuration object. Actions are terminated by the END +action. + +Table 15. RTE FLOW Actions + ++----------+----------------------------+-------------------------+ +| Action\* | Description | Configuration Structure | ++==========+============================+=========================+ +| END | End marker for action | none | +| | lists | | ++----------+----------------------------+-------------------------+ +| VOID | Used as a placeholder for | none | +| | convenience | | ++----------+----------------------------+-------------------------+ +| PASSTHRU | Leaves traffic up for | none | +| | additional processing by | | +| | subsequent flow rules; | | +| | makes a flow rule | | +| | non-terminating. | | ++----------+----------------------------+-------------------------+ +| MARK | Attaches an integer value | rte_flow_action_mark | +| | to packets and sets | | +| | PKT_RX_FDIR and | | +| | PKT_RX_FDIR_ID mbuf flags | | ++----------+----------------------------+-------------------------+ +| QUEUE | Assigns packets to a given | rte_flow_action_queue | +| | queue index | | ++----------+----------------------------+-------------------------+ +| DROP | Drops packets | none | ++----------+----------------------------+-------------------------+ +| COUNT | Enables Counters for this | rte_flow_action_count | +| | flow rule | | ++----------+----------------------------+-------------------------+ +| RSS | Similar to QUEUE, except | rte_flow_action_rss | +| | RSS is additionally | | +| | performed on packets to | | +| | spread them among several | | +| | queues according to the | | +| | provided parameters. | | ++----------+----------------------------+-------------------------+ +| VF | Directs matching traffic | rte_flow_action_vf | +| | to a given virtual | | +| | function of the current | | +| | device | | ++----------+----------------------------+-------------------------+ + +Route to specific Queue id based on ecpriRtcid/ecpriPcid +======================================================== + +An RTE Flow Rule will be created to match an eCPRI packet with a +specific pc_id value and route it to specified queues. + +.. _pattern-items-1: + +Pattern Items +------------- + +Table 16. Pattern Items to match eCPRI packet with a Specific Physical +Channel ID (pc_id) + ++-------+----------+-----------------------+-----------------------+ +| Index | Item | Spec | Mask | ++=======+==========+=======================+=======================+ +| 0 | Ethernet | 0 | 0 | ++-------+----------+-----------------------+-----------------------+ +| 1 | eCPRI | hdr.common.type = | hdr.common.type = | +| | | RTE_EC | 0xff; | +| | | PRI_MSG_TYPE_IQ_DATA; | | +| | | | hdr.type0.pc_id = | +| | | hdr.type0.pc_id = | 0xffff; | +| | | pc_id; | | ++-------+----------+-----------------------+-----------------------+ +| 2 | END | 0 | 0 | ++-------+----------+-----------------------+-----------------------+ + +The following code sets up the *RTE_FLOW_ITEM_TYPE_ETH* and +*RTE_FLOW_ITEM_TYPE_ECPRI* Pattern Items. + +The *RTE_FLOW_ITEM_TYPE_ECPRI* Pattern is configured to match on the +pc_id value (in this case 8 converted to Big Endian byte order). + ++--------------------------------------------------------------------------+ +| uint8_t pc_id_be = 0x0800; | +| | +| #define MAX_PATTERN_NUM 3 | +| | +| struct rte_flow_item pattern[MAX_PATTERN_NUM]; | +| | +| struct rte_flow_action action[MAX_ACTION_NUM]; | +| | +| struct rte_flow_item_ecpri ecpri_spec; | +| | +| struct rte_flow_item_ecpri ecpri_mask; | +| | +| /\* Ethernet \*/ | +| | +| patterns[0].type = RTE_FLOW_ITEM_TYPE_ETH; | +| | +| patterns[0].spec = 0; | +| | +| patterns[0].mask = 0; | +| | +| /\* ECPRI \*/ | +| | +| ecpri_spec.hdr.common.type = RTE_ECPRI_MSG_TYPE_IQ_DATA; | +| | +| ecpri_spec.hdr.type0.pc_id = pc_id_be; | +| | +| ecpri_mask.hdr.common.type = 0xff; | +| | +| ecpri_mask.hdr.type0.pc_id = 0xffff; | +| | +| ecpri_spec.hdr.common.u32 = rte_cpu_to_be_32(ecpri_spec.hdr.common.u32); | +| | +| pattern[1].type = RTE_FLOW_ITEM_TYPE_ECPRI; | +| | +| pattern[1].spec = &ecpri_spec; | +| | +| pattern[1].mask = &ecpri_mask; | +| | +| /\* END the pattern array \*/ | +| | +| patterns[2].type = RTE_FLOW_ITEM_TYPE_END | ++--------------------------------------------------------------------------+ + +Action +------ + +Table 17. QUEUE action for given queue id + +===== ====== ====== ==================== ==================== +Index Action Fields Description Value +===== ====== ====== ==================== ==================== +0 QUEUE index queue indices to use Must be 0,1,2,3, etc +1 END +===== ====== ====== ==================== ==================== + +The following code sets up the action *RTE_FLOW_ACTION_TYPE_QUEUE* and +calls the *rte_flow_create* function to create the RTE Flow rule. + ++----------------------------------------------------------------------+ +| *#define MAX_ACTION_NUM 2* | +| | +| *uint16_t rx_q = 4;* | +| | +| *struct rte_flow_action_queue queue = { .index = rx_q };* | +| | +| *struct rte_flow \*handle;* | +| | +| *struct rte_flow_error err;* | +| | +| *struct rte_flow_action actions[MAX_ACTION_NUM];* | +| | +| *struct rte_flow_attr attributes = {.ingress = 1 };* | +| | +| *action[0].type = RTE_FLOW_ACTION_TYPE_QUEUE;* | +| | +| *action[0].conf = &queue;* | +| | +| *action[1].type = RTE_FLOW_ACTION_TYPE_END;* | +| | +| *handle = rte_flow_create (port_id, &attributes, patterns, actions, | +| &err);* | ++----------------------------------------------------------------------+ diff --git a/docs/fapi_5g_tm_build.rst b/docs/fapi_5g_tm_build.rst index 2cd1d7a..0590867 100644 --- a/docs/fapi_5g_tm_build.rst +++ b/docs/fapi_5g_tm_build.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019-2020 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -23,7 +23,7 @@ The 5G FAPI TM uses the wls library which uses DPDK as the basis for the shared and requires that DPDK be installed in the system since in the makefile it uses the RTE_SDK environment variable when building the library. |br| -The current release was tested using DPDK version 19.11 but it doesn't preclude the +The current release was tested using DPDK version 20.11 but it doesn't preclude the use of newer releases. |br| Also the 5G FAPI TM currently uses the Intel Compiler that is defined as part of the ODULOW documentation. @@ -68,8 +68,8 @@ Unit Test and validation --------------------------------- The unit test for the ORAN 5G FAPI TM requires the testmac and L1 binaries that are described -in a later section and that for the Bronze Release consists of 15 basic tests in timer mode -where the DL, UL and FD paths are exercised for different channel types and numerology 0 and 1. +in a later section and that for the O-RAN current Release consists of a suite of tests in timer mode +where the DL, UL and FD paths are exercised for different channel types and numerologies 0, 1 and 2. 1.Open SSH session and cd l1\bin\nr5g\gnb\l1 |br| 2.Issue l1.sh |br| @@ -101,62 +101,85 @@ Downlink Tx Sub6 Test Cases [mu = 0 (15khz) and 5Mhz] 2.Test case 1002 1 PUCCH Format 2 channel +Downlink Tx Sub6 Test Cases [mu = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +3.Test case 1201 4 antennas 1 PDSCH Spatial Multiplexing 144 RBs QAM 16 + +4.Test case 1204 4 antennas 1 PDSCH Spatial Multiplexing 272 RBs QAM64, DMRS Type 2 + +5.Test case 1250 SU-MIMO 8 Antennas 4 PDSCH Spatial Multiplexing, 6 D-slots Different RBs per slot + +6.Test case 1252 MU-MIMO 16 Antennas 16 PDSCH Spatial Multiplexing, 20 D-Slots Different RBs per slot + +Downlink Tx mWave Test Cases [mu=3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +7. Test case 1001 2 Antennas 1 PDSCH Spatial Multiplexing, 40 Slots QAM64, 66RBs + +8. Test case 1009 2 Antennas 1D and 1S PDSCH Spatial Multiplexing, 160 Slots, QAM64, 66RBs + Uplink Rx Sub6 Test Cases [mu = 0 (15khz) and 5Mhz] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -3.Test case 1001 1 PUSCH +9.Test case 1001 1 PUSCH -4.Test case 1002 1 PUCCH Format 2 +10.Test case 1002 1 PUCCH Format 2 Uplink Rx Sub6 Test Cases [mu = 0 (15khz) and 20Mhz] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -5.Test case 1002 1 PRACH +11.Test case 1002 1 PRACH + +12.Test case 1003 1 PRACH + +Uplink Rx Sub6 Test Cases [mu = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -6.Test case 1003 1 PRACH +13. Test case 1010 1 Antenna, 1 PUSCH Diversity, 1 Slot, QPSK, 272RBs +14. Test case 1018 2 Antennas, 1 PUSCH Spatial Multiplexing, 20 Slots, QAM256, 144RBs -PDSCH {QAM256, mcs28, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +15. Test case 1086 4 Antennas, 1 PUCCH Format 0, 1 S Slot -7.TEST_FD, 1300, 1, fd/mu1_100mhz/300/fd_testconfig_tst300.cfg +16. Test case 1542 MU-MIMO 4 Antennas, 2 PUSCH Spatial Multiplexing, 1 Slot, QAM64, 272 RBs -PDSCH {QAM64, mcs16, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Uplink Rx mmWave Test Case [mu = 3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +17. Test case 1040 2 Antennas, 1 PUSCH Spatial Multiplexing PTRS, QPSK, 1 S slot, 64 RBs + +Full Duplex Sub6 Test Case [mu=0 (15khz) and 20Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -8.TEST_FD, 1301, 1, fd/mu1_100mhz/301/fd_testconfig_tst301.cfg +18. Test case 1018 4 Antennas, 4 PDSCH and 8 PDCCH in D Slots and 1 SSB, 4 PUSCH and 58 PUCCH in U Slots Spatial Multiplexing, 40 D slots, 40 U Slots QAM16,16 RBs -PDSCH {QAM16, mcs9, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Full Duplex Sub6 Test Cases [u = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -9.TEST_FD, 1302, 1, fd/mu1_100mhz/302/fd_testconfig_tst302.cfg +19. Test Case 1300 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDDCH,189 PUCCH and PRACH -PDSCH {QAM256, mcs28, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +20. Test Case 1301 4 Antennas, 20 Slots, 16 PDSCH {QAM64, mcs16, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDSCH, 189 PUCCH. -10.TEST_FD, 1303, 1, fd/mu1_100mhz/303/fd_testconfig_tst303.cfg +21. Test Case 1302 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM64, mcs16, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +22. Test Case 1303 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -11.TEST_FD, 1304, 1, fd/mu1_100mhz/304/fd_testconfig_tst304.cfg +23. Test Case 1304 4 Antennas. 20 Slots, 16 PDSCH {QAM64, mcs16, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM16, mcs9, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +24. Test Case 1305 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 190rbs, 14symbols, 2Layers, 16UE/TTI},16 PDCCH, 189 PUCCH. -12.TEST_FD, 1305, 1, fd/mu1_100mhz/305/fd_testconfig_tst305.cfg +25. Test Case 1306 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM256, mcs28, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +26. Test Case 1307 4 Antennas, 20 Slots, 16 PDSCH {QAM64, mcs16, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -13.TEST_FD, 1306, 1, fd/mu1_100mhz/306/fd_testconfig_tst306.cfg +27. Test Case 1308 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM64, mcs16, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +28. Test Case 1004 2 antennas, 1 Slot, URRLC test case with URLLC in D slot starting at Sym0,3 and in U Slot at sym8,11 -14.TEST_FD, 1307, 1, fd/mu1_100mhz/307/fd_testconfig_tst307.cfg +29. Test Case 1350 32 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs27, 32rbs,12/10symbols, 4Layers}, 16 PUSCH {QAM64, mcs28, 32rbs, 13 symbols, 2Layers}, 16 PDCCH, 189 PUCCH, PRACH, SRS. -PDSCH {QAM16, mcs9, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Full Duplex mmWave Test Case [u = 3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -15.TEST_FD, 1308, 1, fd/mu1_100mhz/308/fd_testconfig_tst308.cfg \ No newline at end of file +30. Test Case 1001 2 Antennas, 80 Slots, 1 PDSCH {QAM64, mcs19, 66rbs, 2Layers}, 1 PUSCH {QAM64, mcs19, 2Layers}, \ No newline at end of file diff --git a/docs/fapi_5g_tm_overview.rst b/docs/fapi_5g_tm_overview.rst index bf32e4b..73bc7e2 100644 --- a/docs/fapi_5g_tm_overview.rst +++ b/docs/fapi_5g_tm_overview.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2020 Intel +.. Copyright (c) 2020-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -120,12 +120,12 @@ Table 2. Reference Documents | Document | Document | | | No./Location | +-------------------------------------+-------------------------------+ -| 1) FlexRAN 5G New Radio Reference | CDI 603575 Intel Corp. | -| Solution L1-L2 API Specification | | -| July 2019 | | +|| 1) FlexRAN 5G New Radio Reference | CDI 603575 Intel Corp. | +|| Solution L1-L2 API Specification| | +|| Rev 10.00 March 2021 | | +-------------------------------------+-------------------------------+ -| 2) 5G FAPI:PHY API Specification, | 222.10.02/ smallcellforum.org | -| Version 1.0.5, March 2020 | | +|| 2) 5G FAPI:PHY API Specification, | 222.10.02/ smallcellforum.org | +|| Version 2.0.0, March 2020 | | +-------------------------------------+-------------------------------+ diff --git a/docs/fapi_5g_tm_rel-notes.rst b/docs/fapi_5g_tm_rel-notes.rst index dbc5ecd..516c39d 100644 --- a/docs/fapi_5g_tm_rel-notes.rst +++ b/docs/fapi_5g_tm_rel-notes.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019-2020 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -20,6 +20,13 @@ ORAN 5G FAPI TM Release Notes ============================= +Version FAPI TM oran_e_maintenance_release_v1.0, Mar 2022 +--------------------------------------------------------- + +* Increased test coverage. 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Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -41,7 +41,7 @@ Build FAPI TM under folder phy/fapi_5g/build:: #./build.sh -For the Bronze release, the L1 only has a binary image as well as the testmac which is an L2 test application, details of the L1 and testmac application are in https://github.com/intel/FlexRAN +For the current O-RAN release, the L1 only has a binary image as well as the testmac which is an L2 test application, details of the L1 and testmac application are in https://github.com/intel/FlexRAN Download L1 and testmac ------------------------ @@ -67,7 +67,7 @@ In each console window, the environment needs to be set using a shell script und **Note** that the markups dpdkBasebandFecMode and dpdkBasebandDevice needs to be adjusted in the relevant phycfg.xml under folder FlexRAN/l1/bin/nr5g/gnb/l1 before starting L1. |br| dpdkBasebandFecMode = 0 for LDPC Encoder/Decoder in software. |br| - dpdkBasebandFecMode = 1 for LDPC Encoder/Decoder in FPGA. (Not supported in the Bronze Release for the Open Source Community) |br| + dpdkBasebandFecMode = 1 for LDPC Encoder/Decoder in FPGA. |br| * Run FAPI TM under folder phy/fapi_5g/bin:: @@ -92,7 +92,7 @@ Once the application comes up, you will see a ** prompt. The same Unit testnum is always a 4 digit number. First digit represents the number of carriers to run. For example, to run Test Case 5 for Uplink Rx mu=3, 100Mhz for 1 carrier, the command would be: run 1 3 100 1005 -All the pre-defined test cases for the Bronze Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test +All the pre-defined test cases for the current O-RAN Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test Cases section of this document. If the user wants to run more slots (than specified in test config file) or change the mode or change the TTI interval of the test, then the command phystart can be used as follows: diff --git a/docs/test_cases.rst b/docs/test_cases.rst index f393954..c999c43 100644 --- a/docs/test_cases.rst +++ b/docs/test_cases.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -24,79 +24,99 @@ Test Cases :depth: 3 :local: -This section describes the downlink, uplink and full duplex bit exact test cases that are present as part of the Bronze |br| +This section describes the downlink, uplink and full duplex bit exact test cases that are present as part of the E Maintenance Release |br| release. All the test config files, IQ samples and reference Inputs are placed under the FlexRAN/testcase folder. These test config files are used for testmac. -There are 3 kinds of tests: dl, ul, and fd. The following test cases are part of the Bronze Release and reside in the github repo mentioned earlier in this document. +There are 3 kinds of tests: dl, ul, and fd. The following test cases are part of the E Maintenance Release and reside in the github repo mentioned earlier in this document. + +The following DL, UL and PRACH test cases are used for validation. Downlink Tx Sub6 Test Cases [mu = 0 (15khz) and 5Mhz] -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1.Test case 1001 1 PDSCH and 1 Control symbol + +2.Test case 1002 1 PUCCH Format 2 channel + +Downlink Tx Sub6 Test Cases [mu = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +3.Test case 1201 4 antennas 1 PDSCH Spatial Multiplexing 144 RBs QAM 16 -**Test case 1001 1 PDSCH and 1 Control symbol** +4.Test case 1204 4 antennas 1 PDSCH Spatial Multiplexing 272 RBs QAM64, DMRS Type 2 -**Test case 1002 1 PUCCH Format 2 channel** +5.Test case 1250 SU-MIMO 8 Antennas 4 PDSCH Spatial Multiplexing, 6 D-slots Different RBs per slot + +6.Test case 1252 MU-MIMO 16 Antennas 16 PDSCH Spatial Multiplexing, 20 D-Slots Different RBs per slot + +Downlink Tx mWave Test Cases [mu=3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +7. Test case 1001 2 Antennas 1 PDSCH Spatial Multiplexing, 40 Slots QAM64, 66RBs + +8. Test case 1009 2 Antennas 1D and 1S PDSCH Spatial Multiplexing, 160 Slots, QAM64, 66RBs Uplink Rx Sub6 Test Cases [mu = 0 (15khz) and 5Mhz] -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Test case 1001 1 PUSCH** +9.Test case 1001 1 PUSCH -**Test case 1002 1 PUCCH Format 2** +10.Test case 1002 1 PUCCH Format 2 Uplink Rx Sub6 Test Cases [mu = 0 (15khz) and 20Mhz] -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -**Test case 1002 1 PRACH** +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Test case 1003 1 PRACH** +11.Test case 1002 1 PRACH -PDSCH {QAM256, mcs28, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +12.Test case 1003 1 PRACH -**TEST_FD, 1300, 1, fd/mu1_100mhz/300/fd_testconfig_tst300.cfg** +Uplink Rx Sub6 Test Cases [mu = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -PDSCH {QAM64, mcs16, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +13. Test case 1010 1 Antenna, 1 PUSCH Diversity, 1 Slot, QPSK, 272RBs -**TEST_FD, 1301, 1, fd/mu1_100mhz/301/fd_testconfig_tst301.cfg** +14. Test case 1018 2 Antennas, 1 PUSCH Spatial Multiplexing, 20 Slots, QAM256, 144RBs -PDSCH {QAM16, mcs9, 272rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +15. Test case 1086 4 Antennas, 1 PUCCH Format 0, 1 S Slot -**TEST_FD, 1302, 1, fd/mu1_100mhz/302/fd_testconfig_tst302.cfg** +16. Test case 1542 MU-MIMO 4 Antennas, 2 PUSCH Spatial Multiplexing, 1 Slot, QAM64, 272 RBs -PDSCH {QAM256, mcs28, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Uplink Rx mmWave Test Case [mu = 3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**TEST_FD, 1303, 1, fd/mu1_100mhz/303/fd_testconfig_tst303.cfg** +17. Test case 1040 2 Antennas, 1 PUSCH Spatial Multiplexing PTRS, QPSK, 1 S slot, 64 RBs -PDSCH {QAM64, mcs16, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Full Duplex Sub6 Test Case [mu=0 (15khz) and 20Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**TEST_FD, 1304, 1, fd/mu1_100mhz/304/fd_testconfig_tst304.cfg** +18. Test case 1018 4 Antennas, 4 PDSCH and 8 PDCCH in D Slots and 1 SSB, 4 PUSCH and 58 PUCCH in U Slots Spatial Multiplexing, 40 D slots, 40 U Slots QAM16,16 RBs -PDSCH {QAM16, mcs9, 190rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 189 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Full Duplex Sub6 Test Cases [u = 1 (30khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**TEST_FD, 1305, 1, fd/mu1_100mhz/305/fd_testconfig_tst305.cfg** +19. Test Case 1300 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDDCH,189 PUCCH and PRACH -PDSCH {QAM256, mcs28, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM64, mcs28, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +20. Test Case 1301 4 Antennas, 20 Slots, 16 PDSCH {QAM64, mcs16, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDSCH, 189 PUCCH. -**TEST_FD, 1306, 1, fd/mu1_100mhz/306/fd_testconfig_tst306.cfg** +21. Test Case 1302 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 272rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 248rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM64, mcs16, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QAM16, mcs16, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +22. Test Case 1303 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -**TEST_FD, 1307, 1, fd/mu1_100mhz/307/fd_testconfig_tst307.cfg** +23. Test Case 1304 4 Antennas. 20 Slots, 16 PDSCH {QAM64, mcs16, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 190rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. -PDSCH {QAM16, mcs9, 96rbs, 12symbols, 4Layers, 16UE/TTI}, PUSCH {QPSK, mcs9, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 94 PUCCH and PRACH -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +24. Test Case 1305 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 190rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 190rbs, 14symbols, 2Layers, 16UE/TTI},16 PDCCH, 189 PUCCH. -**TEST_FD, 1308, 1, fd/mu1_100mhz/308/fd_testconfig_tst308.cfg** +25. Test Case 1306 4 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs28, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM64, mcs28, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. +26. Test Case 1307 4 Antennas, 20 Slots, 16 PDSCH {QAM64, mcs16, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QAM16, mcs16, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. +27. Test Case 1308 4 Antennas, 20 Slots, 16 PDSCH {QAM16, mcs9, 96rbs, 12symbols, 4Layers, 16UE/TTI}, 16 PUSCH {QPSK, mcs9, 96rbs, 14symbols, 2Layers, 16UE/TTI}, 16 PDCCH, 189 PUCCH. +28. Test Case 1004 2 antennas, 1 Slot, URRLC test case with URLLC in D slot starting at Sym0,3 and in U Slot at sym8,11 +29. Test Case 1350 32 Antennas, 20 Slots, 16 PDSCH {QAM256, mcs27, 32rbs,12/10symbols, 4Layers}, 16 PUSCH {QAM64, mcs28, 32rbs, 13 symbols, 2Layers}, 16 PDCCH, 189 PUCCH, PRACH, SRS. +Full Duplex mmWave Test Case [u = 3 (120khz) and 100Mhz] +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +30. Test Case 1001 2 Antennas, 80 Slots, 1 PDSCH {QAM64, mcs19, 66rbs, 2Layers}, 1 PUSCH {QAM64, mcs19, 2Layers}, \ No newline at end of file diff --git a/docs/wls-lib-installation-guide.rst b/docs/wls-lib-installation-guide.rst index c1f98fd..0b555f8 100644 --- a/docs/wls-lib-installation-guide.rst +++ b/docs/wls-lib-installation-guide.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019-2020 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -22,7 +22,7 @@ Wls Lib Installation Guide The wls library uses DPDK as the basis for the shared memory operations and requires that DPDK be installed in the system since in the makefile it uses the RTE_SDK environment variable when building the library. |br| -The current release was tested using DPDK version 19.11 but it doesn't preclude the +The current release was tested using DPDK version 20.11 but it doesn't preclude the use of newer releases. |br| Also the library uses the Intel Compiler that is defined as part of the ODULOW documentation. diff --git a/docs/wls-lib-release-notes.rst b/docs/wls-lib-release-notes.rst index 8064a85..fbd2fc8 100644 --- a/docs/wls-lib-release-notes.rst +++ b/docs/wls-lib-release-notes.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019-2020 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -15,6 +15,11 @@ WLS Library Release Notes ========================= +Version WLS oran_e_maintenance_release_v1.0, Mar 2022 +----------------------------------------------------- + +* Minor changes to deal with initial shared memory management + Version WLS oran_release_bronze_v1.1, Aug 2020 -------------------------------------------------- * Second release of this library aligned with FlexRAN 20.04 diff --git a/docs/wls-lib.rst b/docs/wls-lib.rst index 9bf023c..77e254c 100644 --- a/docs/wls-lib.rst +++ b/docs/wls-lib.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2012 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. diff --git a/docs/xRAN-Library-Design_fh.rst b/docs/xRAN-Library-Design_fh.rst index 2e57169..3b77080 100644 --- a/docs/xRAN-Library-Design_fh.rst +++ b/docs/xRAN-Library-Design_fh.rst @@ -1,4 +1,4 @@ -.. Copyright (c) 2019 Intel +.. Copyright (c) 2019-2022 Intel .. .. Licensed under the Apache License, Version 2.0 (the "License"); .. you may not use this file except in compliance with the License. @@ -16,16 +16,16 @@
    -xRAN Library Design -=================== +O-RAN Library Design +==================== .. contents:: :depth: 3 :local: -The xRAN Library consists of multiple modules where different +The O-RAN Library consists of multiple modules where different functionality is encapsulated. The complete list of all \*.c and \*.h -files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: +files as well as Makefile for O-RAN (aka FHI Lib) release is: ├── app @@ -37,6 +37,14 @@ files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: │ ├── src +│ │ ├── app_io_fh_xran.c + +│ │ ├── app_io_fh_xran.h + +│ │ ├── app_profile_xran.c + +│ │ ├── app_profile_xran.h + │ │ ├── common.c │ │ ├── common.h @@ -53,24 +61,14 @@ files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: │ └── usecase +│ ├── cat_a + │ ├── cat_b │ ├── lte_a │ ├── lte_b -│ ├── mu0_10mhz - -│ ├── mu0_20mhz - -│ ├── mu0_5mhz - -│ ├── mu1_100mhz - -│ └── mu3_100mhz - -├── banner.txt - ├── build.sh ├── lib @@ -85,6 +83,8 @@ files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: │ │ ├── xran_fh_o_du.h +│ │ ├── xran_lib_mlog_tasks_id.h + │ │ ├── xran_mlog_lnx.h │ │ ├── xran_pkt_cp.h @@ -119,42 +119,96 @@ files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: │ ├── xran_app_frag.h +│ ├── xran_bfp_byte_packing_utils.hpp + +│ ├── xran_bfp_cplane8.cpp + +│ ├── xran_bfp_cplane8_snc.cpp + │ ├── xran_bfp_cplane16.cpp + ├── xran_bfp_cplane16_snc.cpp + │ ├── xran_bfp_cplane32.cpp +│ ├── xran_bfp_cplane32_snc.cpp + │ ├── xran_bfp_cplane64.cpp +│ ├── xran_bfp_cplane64_snc.cpp + │ ├── xran_bfp_cplane8.cpp │ ├── xran_bfp_ref.cpp +│ ├── xran_bfp_uplane.cpp + +│ ├── xran_bfp_uplane_9b16rb.cpp + +│ ├── xran_bfp_uplane_snc.cpp + │ ├── xran_bfp_utils.hpp +│ ├── xran_cb_proc.c + +│ ├── xran_cb_proc.h + │ ├── xran_common.c │ ├── xran_common.h │ ├── xran_compression.cpp +│ ├── xran_compression_snc.cpp + │ ├── xran_cp_api.c +│ ├── xran_cp_proc.c + +│ ├── xran_cp_proc.h + +│ ├── xran_delay_measurement.c + +│ ├── xran_dev.c + +│ ├── xran_dev.h + +│ ├── xran_ecpri_owd_measurements.h + │ ├── xran_frame_struct.c │ ├── xran_frame_struct.h -│ ├── xran_lib_mlog_tasks_id.h - │ ├── xran_main.c +│ ├── xran_main.h + +│ ├── xran_mem_mgr.c + +│ ├── xran_mem_mgr.h + +│ ├── xran_mod_compression.cpp + +│ ├── xran_mod_compression.h + +│ ├── xran_prach_cfg.h + │ ├── xran_printf.h +│ ├── xran_rx_proc.c + +│ ├── xran_rx_proc.h + │ ├── xran_sync_api.c │ ├── xran_timer.c │ ├── xran_transport.c +│ ├── xran_tx_proc.c + +│ ├── xran_tx_proc.h + │ ├── xran_ul_tables.c │ └── xran_up_api.c @@ -211,9 +265,9 @@ files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is: General Introduction -------------------- -The xRAN Library functionality is broken down into two main sections: +The O-RAN Library functionality is broken down into two main sections: -- XRAN specific packet handling (src) +- O-RAN specific packet handling (src) - Ethernet and supporting functionality (Ethernet) @@ -227,24 +281,24 @@ can be physical functions (PF) as well. This library is expected to be included in the project via xran_fh_o_du.h, statically compiled and linked with the L1 application -as well as DPDK libraries. The xRAN packet processing-specific +as well as DPDK libraries. The O-RAN packet processing-specific functionality is encapsulated into this library and not exposed to the rest of the 5G NR pipeline. -This way, xRAN specific changes are decoupled from the 5G NR L1 +This way, O-RAN specific changes are decoupled from the 5G NR L1 pipeline. As a result, the design and implementation of the 5G L1 -pipeline code and xRAN library can be done in parallel, provided the +pipeline code and O-RAN library can be done in parallel, provided the defined interface is not modified. Ethernet consists of two modules: -- Ethernet implements xRAN specific HW Ethernet initialization, close, +- Ethernet implements O-RAN specific HW Ethernet initialization, close, send and receive -- ethdi provides Ethernet level software primitives to handle xRAN +- ethdi provides Ethernet level software primitives to handle O-RAN packet exchange -The xRAN layer implements the next set of functionalities: +The O-RAN layer implements the next set of functionalities: - Common code specific for both C-plane and U-plane as well as TX and RX @@ -268,9 +322,9 @@ The xRAN layer implements the next set of functionalities: .. image:: images/Illustration-of-xRAN-Sublayers.jpg :width: 600 - :alt: Figure 24. Illustration of xRAN Sublayers + :alt: Figure 25. Illustration of O-RAN Sublayers -Figure 24. Illustration of xRAN Sublayers +Figure 25. Illustration of O-RAN Sublayers A detailed description of functions and input/output arguments, as well as key data structures, can be found in the Doxygen file for the FlexRAN @@ -285,11 +339,11 @@ application code. It consists of the following steps: 1.Setup structure struct xran_fh_init according to configuration. -2.Call xran_init() to instantiate the xRAN lib memory model and -threads. The function returns a pointer to xRAN handle which is used +2.Call xran_init() to instantiate the O-RAN lib memory model and +threads. The function returns a pointer to O-RAN handle which is used for consecutive configuration functions. -3.Initialize memory buffers used for L1 and xRAN exchange of +3.Initialize memory buffers used for L1 and O-RAN exchange of information. 4.Assign callback functions for (one) TTI event and for the reception @@ -297,11 +351,11 @@ of half of the slot of symbols (7 symbols) and Full slot of symbols 14 symbols). 5.Call xran_open() to initialize PRACH configuration, initialize DPDK, -and launch xRAN timing thread. +and launch O-RAN timing thread. -6.Call xran_start() to start processing xRAN packets for DL and UL. +6.Call xran_start() to start processing O-RAN packets for DL and UL. -After this is complete 5G L1 runs with xRAN Front haul interface. During +After this is complete 5G L1 runs with O-RAN Front haul interface. During run time for every TTI event, the corresponding call back is called. For packet reception on UL direction, the corresponding call back is called. OTA time information such as frame id, subframe id and slot id can be @@ -312,7 +366,7 @@ To stop and close the interface, perform this sequence of steps: 7.Call xran_stop() to stop the processing of DL and UL. -8.Call xran_close() to remove usage of xRAN resources. +8.Call xran_close() to remove usage of O-RAN resources. 9.Call xran_mm_destroy() to destroy memory management subsystem. @@ -323,7 +377,7 @@ sessions without a restart of the full L1 application. Configuration ~~~~~~~~~~~~~ -The xRAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config. +The O-RAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config. The sample application gives an example of a test configuration used for LTE and 5GNR mmWave and Sub 6. Sample application folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B) and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz). @@ -337,7 +391,7 @@ The following options are available: - Number of CC and corresponding settings for each -- Core allocation for xRAN +- Core allocation for O-RAN - Ethernet port allocation @@ -363,7 +417,7 @@ The following options are available: **From an implementation perspective:** -xran_init() performs init of the xRAN library and interface according to +xran_init() performs init of the O-RAN library and interface according to struct xran_fh_init information as per the start of application configuration.: @@ -379,7 +433,7 @@ configuration.: - ETH PMD (process_dpdk_io()) - - IO XRAN-PHY exchange (ring_processing_func()) + - IO O-RAN-PHY exchange (ring_processing_func()) **xran_open()** performs additional configuration as per run scenario: @@ -401,13 +455,13 @@ Data Exchange ~~~~~~~~~~~~~ Exchange of IQ samples, as well as C-plane specific information, is -performed using a set of buffers allocated by xRAN library from DPDK +performed using a set of buffers allocated by O-RAN library from DPDK memory and shared with the l1 application. Buffers are allocated as a standard mbuf structure and DPDK pools are used to manage the allocation and free resources. Shared buffers are allocated at the init stage and are expected to be reused within 80 TTIs (10 ms). -The xRAN protocol requires U-plane IQ data to be transferred in network +The O-RAN protocol requires U-plane IQ data to be transferred in network byte order, and the L1 application handles IQ sample data in CPU byte order, requiring a swap. The PHY BBU pooling tasks perform copy and byte order swap during packet processing. @@ -415,65 +469,117 @@ order swap during packet processing. C-plane Information Settings ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The interface between the xRAN library and PHY is defined via struct +The interface between the O-RAN library and PHY is defined via struct xran_prb_map and similar to the data plane. The same mbuf memory is used -to allocate memory map of PRBs for each TTI. +to allocate memory map of PRBs for each TTI.:: -/\* Beamforming waights for single stream for each PRBs given number of Antenna elements \*/ -struct xran_cp_bf_weight{ + /*\* Beamforming waights for single stream for each PRBs given number of + Antenna elements \*/ + struct xran_cp_bf_weight{ - int16_t nAntElmTRx; /\*< num TRX for this allocation \*/ - int8_t* p_ext_start; /\*< pointer to start of buffer for full C-plane packet \*/ - int8_t* p_ext_section; /\*< pointer to form extType \*/ - int16_t ext_section_sz; /\*< extType section size \*/ + int16_t nAntElmTRx; /**< num TRX for this allocation \*/ -/\* section descriptor for given number of PRBs used on U-plane packet creation \*/ -struct xran_section_desc { + int16_t ext_section_sz; /**< extType section size \*/ - uint16_t section_id; /\*< section id used for this element \*/ + int8_t\* p_ext_start; /**< pointer to start of buffer for full C-plane + packet \*/ - int16_t iq_buffer_offset; /\*< Offset in bytes for the content of IQs with in main symb buffer \*/ - int16_t iq_buffer_len; /\*< Length in bytes for the content of IQs with in main symb buffer \*/ + int8_t\* p_ext_section; /**< pointer to form extType \*/ - uint8_t \*pData; /\*< optional pointer to data buffer \*/ - void \*pCtrl; /\*< optional poitner to mbuf \*/ - -}; + /\* For ext 11 \*/ -struct xran_prb_elm { - int16_t nRBStart; /\*< start RB of RB allocation \*/ - int16_t nRBSize; /\*< number of RBs used \*/ - int16_t nStartSymb; /\*< start symbol ID \*/ - int16_t numSymb; /\\*< number of symbols \*/ - int16_t nBeamIndex; /\*< beam index for given PRB \*/ - int16_t bf_weight_update; /\* need to update beam weights or not \*/ - int16_t compMethod; /\*< compression index for given PRB \*/ - int16_t iqWidth; /\*< compression bit width for given PRB \*/ - int16_t BeamFormingType; /\*< index based, weights based or attribute based beam forming\*/ - - struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /\*< section desctiptors to U-plane data given RBs \*/ - struct xran_cp_bf_weight bf_weight; /\*< beam forming information relevant for given RBs \*/ - - union { - struct xran_cp_bf_attribute bf_attribute; - struct xran_cp_bf_precoding bf_precoding; - - }; - -/\* PRB map structure \*/ - -struct xran_prb_map { - uint8_t dir; /\*< DL or UL direction \*/ - uint8_t xran_port; /\*< xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/ - uint16_t band_id; /\*< xran band id \*/ - uint16_t cc_id; /\*< componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)] \*/ - uint16_t ru_port_id; /\*< RU device antenna port id [0 - (XRAN_MAX_ANTENNA_NR-1) \*/ - uint16_t tti_id; /\*< xRAN slot id [0 - (max tti-1)] \*/ - uint8_t start_sym_id; /\*< start symbol Id [0-13] \*/ - uint32_t nPrbElm; /\*< total number of PRB elements for given map [0- (XRAN_MAX_PRBS-1)] \*/ - struct xran_prb_elm prbMap[XRAN_MAX_PRBS]; - -}; + uint8_t bfwCompMeth; /\* Compression Method for BFW \*/ + + uint8_t bfwIqWidth; /\* Bitwidth of BFW \*/ + + uint8_t numSetBFWs; /\* Total number of beam forming weights set (L) \*/ + + uint8_t numBundPrb; /\* The number of bundled PRBs, 0 means to use ext1 + \*/ + + uint8_t RAD; + + uint8_t disableBFWs; + + int16_t maxExtBufSize; /\* Maximum space of external buffer \*/ + + struct xran_ext11_bfw_info bfw[XRAN_MAX_SET_BFWS] + + }; + + /*\* PRB element structure \*/ + + struct xran_prb_elm { + + int16_t nRBStart; /**< start RB of RB allocation \*/ + + int16_t nRBSize; /**< number of RBs used \*/ + + int16_t nStartSymb; /**< start symbol ID \*/ + + int16_t numSymb; /**< number of symbols \*/ + + int16_t nBeamIndex; /**< beam index for given PRB \*/ + + int16_t bf_weight_update; /*\* need to update beam weights or not \*/ + + int16_t compMethod; /**< compression index for given PRB \*/ + + int16_t iqWidth; /**< compression bit width for given PRB \*/ + + uint16_t ScaleFactor; /**< scale factor for modulation compression \*/ + + int16_t reMask; /**< 12-bit RE Mask for modulation compression \*/ + + int16_t BeamFormingType; /**< index based, weights based or attribute + based beam forming*/ + + int16_t nSecDesc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /**< number of section + descriptors per symbol \*/ + + struct xran_section_desc \* + p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_MAX_FRAGMENT]; /**< section + desctiptors to U-plane data given RBs \*/ + + struct xran_cp_bf_weight bf_weight; /**< beam forming information + relevant for given RBs \*/ + + union { + + struct xran_cp_bf_attribute bf_attribute; + + struct xran_cp_bf_precoding bf_precoding; + + }; + + }; + + /*\* PRB map structure \*/ + + struct xran_prb_map { + + uint8_t dir; /**< DL or UL direction \*/ + + uint8_t xran_port; /**< O-RAN id of given RU [0-(XRAN_PORTS_NUM-1)] \*/ + + uint16_t band_id; /**< O-RAN band id \*/ + + uint16_t cc_id; /**< component carrier id [0 - (XRAN_MAX_SECTOR_NR-1)] + \*/ + + uint16_t ru_port_id; /**< RU device antenna port id [0 - + (XRAN_MAX_ANTENNA_NR-1) \*/ + + uint16_t tti_id; /**< O-RAN slot id [0 - (max tti-1)] \*/ + + uint8_t start_sym_id; /**< start symbol Id [0-13] \*/ + + uint32_t nPrbElm; /**< total number of PRB elements for given map [0- + (XRAN_MAX_SECTIONS_PER_SLOT-1)] \*/ + + struct xran_prb_elm prbMap[XRAN_MAX_SECTIONS_PER_SLOT]; + + }; For the Bronze release C-plane sections are expected to be provided by L1 @@ -481,14 +587,14 @@ pipeline. If 100% of RBs always allocated single element of RB map is expected to be allocated across all symbols. Dynamic RB allocation is performed base on C-plane configuration. -The xRAN library will require that the content of the PRB map should be +The O-RAN library will require that the content of the PRB map should be sorted in increasing order of PRB first and then symbols. Memory Management ----------------- Memory used for the exchange of IQ data as well as control information, -is controlled by the xRAN library. L1 application at the init stage +is controlled by the O-RAN library. L1 application at the init stage performs: - init memory management subsystem @@ -503,7 +609,7 @@ performs: After the session is completed, the application can free buffers and destroy the memory management subsystem. -From an implementation perspective, the xRAN library uses a standard +From an implementation perspective, the O-RAN library uses a standard mbuf primitive and allocates a pool of buffers for each sector. This function is performed using rte_pktmbuf_pool_create(), rte_pktmbuf_alloc(), rte_pktmbuf_append() to allocate one buffer per @@ -514,150 +620,210 @@ In the current implementation, mbuf, the number of buffers shared with the L1 application is the same number of buffers used to send to and receive from the Ethernet port. Memory copy operations are not required if the packet size is smaller than or equal to MTU. Future versions of -the xRAN library are required to remove the memory copy requirement for +the O-RAN library are required to remove the memory copy requirement for packets where the size larger than MTU. External Interface Memory ~~~~~~~~~~~~~~~~~~~~~~~~~ -The xRAN library header file defines a set of structures to simplify -access to memory buffers used for IQ data. +The O-RAN library header file defines a set of structures to simplify +access to memory buffers used for IQ data.::: -struct xran_flat_buffer { + struct xran_flat_buffer { -uint32_t nElementLenInBytes; + uint32_t nElementLenInBytes; -uint32_t nNumberOfElements; + uint32_t nNumberOfElements; -uint32_t nOffsetInBytes; + uint32_t nOffsetInBytes; -uint32_t nIsPhyAddr; + uint32_t nIsPhyAddr; -uint8_t \*pData; + uint8_t \*pData; -void \*pCtrl; + void \*pCtrl; -}; + }; -struct xran_buffer_list { + struct xran_buffer_list { -uint32_t nNumBuffers; + uint32_t nNumBuffers; -struct xran_flat_buffer \*pBuffers; + struct xran_flat_buffer \*pBuffers; -void \*pUserData; + void \*pUserData; -void \*pPrivateMetaData; + void \*pPrivateMetaData; -}; + }; + + struct xran_io_buf_ctrl { + + /\* -1-this subframe is not used in current frame format + + 0-this subframe can be transmitted, i.e., data is ready + + 1-this subframe is waiting transmission, i.e., data is not ready + + 10 - DL transmission missing deadline. When FE needs this subframe data + but bValid is still 1, -typedef struct { + set bValid to 10. -int32_t bValid ; + \*/ -int32_t nSegToBeGen; + int32_t bValid ; // when UL rx, it is subframe index. -int32_t nSegGenerated; + int32_t nSegToBeGen; -int32_t nSegTransferred; + int32_t nSegGenerated; // how many date segment are generated by DL LTE + processing or received from FE -struct rte_mbuf \*pData[N_MAX_BUFFER_SEGMENT]; + // -1 means that DL packet to be transmitted is not ready in BS -struct xran_buffer_list sBufferList; + int32_t nSegTransferred; // number of data segments has been transmitted + or received -} BbuIoBufCtrlStruct; + struct rte_mbuf \*pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK + allocated memory pool + + struct xran_buffer_list sBufferList; + + }; There is no explicit requirement for user to organize a set of buffers in this particular way. From a compatibility |br| perspective it is useful to follow the existing design of the 5G NR l1app used for Front Haul FPGA -and define structures shared between l1 and xRAN lib as shown: +and define structures shared between l1 and O-RAN lib as shown: :: + + struct bbu_xran_io_if { + + void\* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /**< + instance per O-RAN port per CC \*/ + + uint32_t + nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; + /**< unique buffer pool \*/ + + uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC + \*/ + + uint16_t DynamicSectionEna; + + uint32_t nPhaseCompFlag; + + int32_t num_o_ru; + + int32_t num_cc_per_port[XRAN_PORTS_NUM]; + + int32_t map_cell_id2port[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + + struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU + port \*/ + + struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + + struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + + struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + + }; + + struct xran_io_shared_ctrl { -/\* io struct \*/ + /\* io struct \*/ -BbuIoBufCtrlStruct -sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]\ -[XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl + sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -BbuIoBufCtrlStruct -sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl + sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -BbuIoBufCtrlStruct -sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl + sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -BbuIoBufCtrlStruct -sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl + sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -BbuIoBufCtrlStruct -sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl + sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -/\* Cat B \*/ + /\* Cat B \*/ -BbuIoBufCtrlStruct -sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + struct xran_io_buf_ctrl + sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; -/\* buffers list \*/ + struct xran_io_buf_ctrl + sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; -struct xran_flat_buffer -sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + /\* buffers lists \*/ -struct xran_flat_buffer -sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer + sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; -struct xran_flat_buffer -sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer + sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -struct xran_flat_buffer -sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer + sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; -struct xran_flat_buffer -sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer + sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -/\* Cat B SRS buffers \*/ + struct xran_flat_buffer + sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; -struct xran_flat_buffer -sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; + /\* Cat B SRS buffers \*/ + + struct xran_flat_buffer + sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; + + struct xran_flat_buffer + sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + + }; Doxygen file and xran_fh_o_du.h provide more details on the definition and usage of these structures. -xRAN Specific Functionality ---------------------------- +O-RAN Specific Functionality +---------------------------- Front haul interface implementation in the general case is abstracted away using the interface defined in xran_fh_o_du.h -The L1 application is not required to access xRAN protocol primitives +The L1 application is not required to access O-RAN protocol primitives (eCPRI header, application header, and others) directly. It is recommended to use the interface to remove dependencies between -different software modules such as the l1 pipeline and xRAN library. +different software modules such as the l1 pipeline and O-RAN library. External API ~~~~~~~~~~~~ The U-plane and C-plane APIs can be used directly from the application if such an option is required. The set of header files can be exported -and called directly. +and called directly.:: -xran_fh_o_du.h – xRAN main header file for O-DU scenario + xran_fh_o_du.h – O-RAN main header file for O-DU scenario -xran_cp_api.h – Control plane functions + xran_cp_api.h – Control plane functions -xran_pkt_cp.h – xRAN control plane packet definition + xran_pkt_cp.h – O-RAN control plane packet definition -xran_pkt.h – xRAN packet definition + xran_pkt.h – O-RAN packet definition -xran_pkt_up.h – xRAN User plane packet definition + xran_pkt_up.h – O-RAN User plane packet definition -xran_sync_api.h – api functions to check PTP status + xran_sync_api.h – api functions to check PTP status -xran_timer.h – API for timing + xran_timer.h – API for timing -xran_transport.h – eCPRI transport layer definition and api + xran_transport.h – eCPRI transport layer definition and api -xran_up_api.h – user plane functions and definitions + xran_up_api.h – user plane functions and definitions -xran_compression.h – interface to compression/decompression functions + xran_compression.h – interface to compression/decompression functions Doxygen files provide detailed information on functions and structures available. @@ -681,20 +847,16 @@ The C-plane module contains: resources - code to prepare C-plane packet for TX (O-DU) - -- eCPRI header - -- append radio application header - -- append control section header - -- append control section + - eCPRI header + - append radio application header + - append control section header + - append control section - parser of C-plane packet for RX (O-RU emulation) - parses and checks Section 1 and Section 3 packet content -Sending and receiving packets is performed using xRAN ethdi sublayer +Sending and receiving packets is performed using O-RAN ethdi sublayer functions. Creating a C-Plane Packet @@ -703,13 +865,13 @@ Creating a C-Plane Packet API and Data Structures ''''''''''''''''''''''' -A C-Plane message can be composed using the following API: +A C-Plane message can be composed using the following API::: -int xran_prepare_ctrl_pkt(struct rte_mbuf \*mbuf, + int xran_prepare_ctrl_pkt(struct rte_mbuf \*mbuf, -struct xran_cp_gen_params \*params, + struct xran_cp_gen_params \*params, -uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id); + uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id); mbuf is the pointer of a DPDK packet buffer, which is allocated from the caller. @@ -724,26 +886,26 @@ seq_id is the sequence index for the message. params, the parameters to create a C-Plane message are defined as the structure of xran_cp_gen_params with an |br| -example given below: +example given below::: -struct xran_cp_gen_params { + struct xran_cp_gen_params { -uint8_t dir; + uint8_t dir; -uint8_t sectionType; + uint8_t sectionType; -uint16_t numSections; + uint16_t numSections; -struct xran_cp_header_params hdr; + struct xran_cp_header_params hdr; -struct xran_section_gen_info \*sections; + struct xran_section_gen_info \*sections; -}; + }; dir is the direction of the C-Plane message to be generated. Available parameters are defined as XRAN_DIR_UL and XRAN_DIR_DL. -sectionType is the section type for C-Plane message to generate, as ORAN +sectionType is the section type for C-Plane message to generate, as O-RAN specification defines all sections in a C-Plane message shall have the same section type. If different section types are required, they shall be sent with separate C-Plane messages. Available types of sections are @@ -757,8 +919,7 @@ hdr is the structure to hold the information to generate the radio application and section header in the C-Plane message. It is defined as the structure of xran_cp_header_params. Not all parameters in this structure are used for the generation, and the required parameters are -slightly different by the type of section, as described in Table 10 and -Table 11. +slightly different by the type of section, as described in Table 10. Table 10. struct xran_cp_header_params – Common Radio Application Header @@ -846,7 +1007,7 @@ Table 11. struct xran_cp_header_params – Section Specific Parameters | | are | | | | | | | | | | defined | | | | | | | | | | as | | | | | | | | -| | XRAN\ | | | | | | | | +| | O-RAN\ | | | | | | | | | | _COMPMET\| | | | | | | | | | HOD_xxxx | | | | | | | | +----------+----------+----------+---------+---+---+---+---+----------+ @@ -882,25 +1043,25 @@ Table 11. struct xran_cp_header_params – Section Specific Parameters **Only sections types 1 and 3 are supported in the current release.** Sections are the pointer to the array of structure which has the -parameters for section(s) and it is defined as below: +parameters for section(s) and it is defined as below::: -struct xran_section_gen_info { + struct xran_section_gen_info { -struct xran_section_info info; + struct xran_section_info info; -uint32_t exDataSize; + uint32_t exDataSize; -struct { + struct { -uint16_t type; + uint16_t type; -uint16_t len; + uint16_t len; -void \*data; + void \*data; -} exData[XRAN_MAX_NUM_EXTENSIONS]; + } exData[XRAN_MAX_NUM_EXTENSIONS]; -}; + }; info is the structure to hold the information to generate section and it is defined as the structure of xran_section_info. Like @@ -939,7 +1100,7 @@ Table 12. Parameters for Sections | | de\ | | | | | | | | | fined | | | | | | | | | as | | | | | | | -| | XRAN\ | | | | | | | +| | O-RAN\| | | | | | | | | _\ | | | | | | | | | RBI\ | | | | | | | | | ND_xx\| | | | | | | @@ -1094,106 +1255,165 @@ type 3 is excluded since it is not supported). exData.type is the type of section extension and exData.len is the length of structure of section extension parameter in exData.data. exData.data is the pointer to the structure of section extensions and different structures are used -by the type of section extensions like below. +by the type of section extensions like below.:: -struct xran_sectionext1_info { + struct xran_sectionext1_info { -uint16_t rbNumber; /* number RBs to ext1 chain \*/ + uint16_t rbNumber; /* number RBs to ext1 chain \*/ -uint16_t bfwNumber; /* number of bf weights in this section \*/ + uint16_t bfwNumber; /* number of bf weights in this section \*/ -uint8_t bfwiqWidth; + uint8_t bfwiqWidth; -uint8_t bfwCompMeth; + uint8_t bfwCompMeth; -int16_t \*p_bfwIQ; /* pointer to formed section extention \*/ + int16_t \*p_bfwIQ; /* pointer to formed section extention \*/ -int16_t bfwIQ_sz; /* size of buffer with section extention information -\*/ + int16_t bfwIQ_sz; /* size of buffer with section extention information + \*/ -union { + union { -uint8_t exponent; + uint8_t exponent; -uint8_t blockScaler; + uint8_t blockScaler; -uint8_t compBitWidthShift; + uint8_t compBitWidthShift; -uint8_t activeBeamspaceCoeffMask[XRAN_MAX_BFW_N]; /\* ceil(N/8)*8, -should be multiple of 8 \*/ + uint8_t activeBeamspaceCoeffMask[XRAN_MAX_BFW_N]; /\* ceil(N/8)*8, + should be multiple of 8 \*/ -} bfwCompParam; + } bfwCompParam; -}; + }; For section extension type 1, the structure of xran_sectionext1_info is -used. Please note that the xRAN library will use bfwIQ (beamforming -weight) as-is, i.e., xRAN library will not perform the compression, so -the user should provide proper data to bfwIQ. +used. Please note that the O-RAN library will use bfwIQ (beamforming +weight) as-is, i.e., O-RAN library will not perform the compression, so +the user should provide proper data to bfwIQ.:: -struct xran_sectionext2_info { + struct xran_sectionext2_info { -uint8_t bfAzPtWidth; + uint8_t bfAzPtWidth; -uint8_t bfAzPt; + uint8_t bfAzPt; -uint8_t bfZePtWidth; + uint8_t bfZePtWidth; -uint8_t bfZePt; + uint8_t bfZePt; -uint8_t bfAz3ddWidth; + uint8_t bfAz3ddWidth; -uint8_t bfAz3dd; + uint8_t bfAz3dd; -uint8_t bfZe3ddWidth; + uint8_t bfZe3ddWidth; -uint8_t bfZe3dd; + uint8_t bfZe3dd; -uint8_t bfAzSI; + uint8_t bfAzSI; -uint8_t bfZeSI; + uint8_t bfZeSI; -}; + }; For section extension type 2, the structure of xran_sectionext2_info is -used. Each parameter will be packed as specified bit width. +used. Each parameter will be packed as specified bit width.:: -struct xran_sectionext4_info { + struct xran_sectionext4_info { -uint8_t csf; + uint8_t csf; -uint8_t pad0; + uint8_t pad0; -uint16_t modCompScaler; + uint16_t modCompScaler; -}; + }; For section extension type 4, the structure of xran_sectionext4_info is -used. +used.:: -struct xran_sectionext5_info { + struct xran_sectionext5_info { -uint8_t num_sets; + uint8_t num_sets; -struct { + struct { -uint16_t csf; + uint16_t csf; -uint16_t mcScaleReMask; + uint16_t mcScaleReMask; -uint16_t mcScaleOffset; + uint16_t mcScaleOffset; -} mc[XRAN_MAX_MODCOMP_ADDPARMS]; + } mc[XRAN_MAX_MODCOMP_ADDPARMS]; -}; + }; For section extension type 5, the structure of xran_sectionext5_info is used. Please note that current implementation supports maximum two sets -of additional parameters. +of additional parameters.:: + + struct xran_sectionext6_info { + + uint8_t rbgSize; + + uint8_t pad; + + uint16_t symbolMask; + + uint32_t rbgMask; + + }; + + For section extension type 6, the structure of xran_sectionext6_info is + used. + + struct xran_sectionext10_info { + + uint8_t numPortc; -**Section extensions type 3 is not supported since it is LTE specific.** + uint8_t beamGrpType; -Section Extensions are not fully verified in this release. + uint16_t beamID[XRAN_MAX_NUMPORTC_EXT10]; + + }; + +For section extension type 10, the structure of xran_sectionext10_info +is used.:: + + struct xran_sectionext11_info { + + uint8_t RAD; + + uint8_t disableBFWs; + + uint8_t numBundPrb; + + uint8_t numSetBFWs; /\* Total number of beam forming weights set (L) \*/ + + uint8_t bfwCompMeth; + + uint8_t bfwIqWidth; + + int totalBfwIQLen; + + int maxExtBufSize; /\* Maximum space of external buffer \*/ + + uint8_t \*pExtBuf; /\* pointer to start of external buffer \*/ + + void \*pExtBufShinfo; /\* Pointer to rte_mbuf_ext_shared_info \*/ + + }; + +For section extension type 11, the structure of xran_sectionext11_info +is used. + +To minimize memory copy for beamforming weights, when section extension +11 is required to send beamforming weights(BFWs), external flat buffer +is being used in current release. If extension 11 is used, it will be +used instead of mbufs that pre-allocated external buffers which BFWs +have been prepared already. BFW can be prepared by +xran_cp_prepare_ext11_bfws() and the example usage can be found from +app_init_xran_iq_content() from sample-app.c. Detail Procedures in API '''''''''''''''''''''''' @@ -1283,18 +1503,17 @@ xran_cp_radioapp_section3_header) type from xran_append_section_extensions() and these functions will create extension field. -**Example Usage of API** -'''''''''''''''''''''''' +Example Usage of API +'''''''''''''''''''' -There are two reference usages of API to generate C-Plane message in -lib/src/xran_common.c +There are two reference usages of API to generate C-Plane messages: -- generate_cpmsg_dlul() +- xran_cp_create_and_send_section() in xran_main.c -- generate_cpmsg_prach() +- generate_cpmsg_prach() in xran_common.c -generate_cpmsg_dlul() is to generate the C-Plane message with section -type 1 for DL or UL symbol data scheduling. +The xran_cp_create_and_send_section() is to generate the C-Plane message +with section type 1 for DL or UL symbol data scheduling. This function has hardcoded values for some parameters such as: @@ -1306,19 +1525,23 @@ This function has hardcoded values for some parameters such as: - Resource Element Mask is fixed to 0xfff -The extension is not used. +If section extensions include extension 1 or 11, direct mbuf will not be +allocated/used and pre-allocated flat buffer will be attached to +indirect mbuf. This external buffer will be used to compose C-Plane +message and should have BFWs already by xran_cp_populate_section_ext_1() +or xran_cp_prepare_ext11_bfws(). -After C-Plane message generation, API send_cpmsg() is called. This -function also includes the implementation for these capabilities: +Since current implementation uses single section single C-Plane message, +if multi sections are present, this function will generate same amount +of C-Plane messages with the number of sections. -- Send the generated packet to the TX ring after adding an Ethernet - header. +After C-Plane message generation, it will send generated packet to TX +ring after adding an Ethernet header and also will add section +information of generated C-Plane packet to section database, to generate +U-plane message by C-Plane configuration. -- Add section information of generated C-Plane packet to section - database, to generate U-plane message by C-Plane configuration - -send_cpmsg_prach() is to generate the C-Plane message with section type -3 for PRACH scheduling. +The generate_cpmsg_prach()is to generate the C-Plane message with +section type 3 for PRACH scheduling. This functions also has some hardcoded values for the following parameters: @@ -1329,11 +1552,11 @@ parameters: - Resource Element Mask is fixed to 0xfff. -And similar to generate_cpmsg_dlul(), after this function generates the -message, send_cpmsg() sends the generated packet to the TX ring and adds -section information of the packet to the section database. Checking and -parsing received PRACH symbol data by section information from the -C-Plane are not implemented in this release. +This function does not send generated packet, send_cpmsg() should be +called after this function call. The example can be found from +tx_cp_ul_cb() in xran_main.c. Checking and parsing received PRACH symbol +data by section information from the C-Plane are not implemented in this +release. Example Configuration of C-Plane Messages ''''''''''''''''''''''''''''''''''''''''' @@ -1627,7 +1850,7 @@ These functions can be utilized to debug or RU emulation purposes. U-plane ~~~~~~~ -Single Section is the default mode of xRAN packet creation. It assumes +Single Section is the default mode of O-RAN packet creation. It assumes that there is only one section per packet, and all IQ samples are attached to it. Compression is not supported. @@ -1651,7 +1874,7 @@ The following list of functions is implemented for U-plane: - Append IQ samples to packet -- Prepare full symbol of xRAN data for single eAxC +- Prepare full symbol of O-RAN data for single eAxC - Process RX packet per symbol. @@ -1662,14 +1885,14 @@ according to Table 4. Supporting Code --------------- -The xRAN library has a set of functions used to assist in packet -processing and data exchange not directly used for xRAN packet +The O-RAN library has a set of functions used to assist in packet +processing and data exchange not directly used for O-RAN packet processing. Timing ~~~~~~ -The sense of time for the xRAN protocol is obtained from system time, +The sense of time for the O-RAN protocol is obtained from system time, where the system timer is synchronized to GPS time via PTP protocol using the Linux PHP package. On the software side, a simple polling loop is utilized to get time up to nanosecond precision and particular packet @@ -1739,8 +1962,8 @@ calls rte_timer_manage() in the loop, and the resulting execution of timer function happens right |br| after the timer was “armed”. -xRAN Ethernet -~~~~~~~~~~~~~ +O-RAN Ethernet +~~~~~~~~~~~~~~ xran_init_port() function performs initialization of DPDK ETH port. Standard port configuration is used as per reference example from DPDK. @@ -1759,19 +1982,19 @@ From an implementation perspective, modules provide functions to handle: - Send and Receive mbuf. -xRAN Ethdi -~~~~~~~~~~ +O-RAN Ethdi +~~~~~~~~~~~ Ethdi provides functionality to work with the content of an Ethernet -packet and dispatch processing to/from the xRAN layer. Ethdi +packet and dispatch processing to/from the O-RAN layer. Ethdi instantiates a main PMD driver thread and dispatches packets between the ring and RX/TX using rte_eth_rx_burst() and rte_eth_tx_burst() DPDK functions. For received packets, it maintains a set of handlers for ethertype -handlers and xRAN layer register one xRAN ethtype |br| +handlers and O-RAN layer register one O-RAN ethtype |br| 0xAEFE, resulting in -packets with this ethertype being routed to the xRAN processing +packets with this ethertype being routed to the O-RAN processing function. This function checks the message type of the eCPRI header and dispatches packet to either C-plane processing or U-plane processing. @@ -1779,6 +2002,84 @@ Initialization of memory pools, allocation and freeing of mbuf for Ethernet packets occur in this layer. +O-RAN One Way Delay Measurements +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The support for the eCPRI one- way delay measurements which are specified by +the O-RAN to be used with the Measured Transport support per Section 2.3.3.3 +of the O-RAN-WG4.CUS.0-v4.00 specification and section 3.2.4.6 of the eCPRI_v2.0 +specification is implemented in the file xran_delay_measurement.c. Structure +definitions used by the owd measurement functions are in the file xran_fh_o_du.h +for common data and port specific variables and parameters. + +The implementation of this feature has been done under the assumption that the requestor +is the O-DU and the recipient is the O-RU. All of the action_types per the eCPRI 2.0 have +been implemented. In the current version the timestamps are obtained using the linux +function clock_gettime using CLOCK_REALTIME as the clock_id argument. + +The implementation supports both the O-RU and the O-DU side in order to do the unit test +in loopback mode. + +The one-delay measurements are enabled at configuration time and run right after the +xran_start() function is executed. The total number of consecutive measurements per port +should be a power of 2 and in order to minimize the system startup it is advisable that +the number is 16 or below. + +The following functions can be found in the xran_delay_measurement.c: + +xran_ecpri_one_way_delay_measurement_transmitter() which is invoked from the +process_dpdk_io()function if the one-way delay measurements are enabled. This is +the main function for the owd transmitter. + +xran_generate_delay_meas() is a general function used by the transmitter to send the appropriate +messages based on actionType and filling up all the details for the ethernet and ecpri layers. + +Process_delay_meas() this function is invoked from the handle_ecpri_ethertype() function when +the ecpri message type is ECPRI_DELAY_MEASUREMENT. This is the main owd receiver function. + +From the Process_delay_meas() and depending on the message received we can execute one +of the following functions + +xran_process_delmeas_request() If we received a request message. + +xran_process_delmeas_request_w_fup() If we received a request with follow up message. + +xran_process_delmeas_response() If we received a response message. + +xran_process_delmeas_rem_request() If we received a remote request message + + +xran_delmeas_rem_request_w_fup() If we received a remote request with follow up message. + +All of the receiver functions also can generate the appropriate send message by using +the DPDK function rte_eth_tx_burst() to minimize the response delay. + +Additional utility functions used by the owd implementation for managing of timestamps +and time measurements are: + +xran_ptp_ts_to_ns() that takes a TimeStamp argument from a received owd ecpri packet and +places it in host order and returns the value in nanoseconds. + +xran_timespec_to_ns() that takes an argument in timespec format like the return value from the +linux function clock_gettime() and returns a value in nanoseconds. + +xran_ns_to_timespec() that takes an argument in nanoseconds and returns a value by +reference in timespec format. + +xran_compute_and_report_delay_estimate() This function takes an average of the computed one way +delay measurements and prints out the average value to the console expressed in nanoseconds. +Currently we exclude the first 2 measurements from the average. + +Utility functions in support of the owd ecpri packet formulation are: + +xran_build_owd_meas_ecpri_hdr() Builds the ecpri header with message type ECPRI_DELAY_MEASUREMENT +and writes the payload size in network order. +xran_add_at_and_measId_to_header() This function is used to write the action Type and +MeasurementID to the eCPRI owd header. +The current implementation of the one way delay measurements only supports a fixed +message size. The message is defined in the xran_pkt.h in the structure xran_ecpri_delay_meas_pl. +The one-way delay measurements have been tested with the sample-app for the Front Haul Interface +Library and have not yet been integrated with the L1 Layer functions. \ No newline at end of file diff --git a/fapi_5g/bin/oran_5g_fapi.cfg b/fapi_5g/bin/oran_5g_fapi.cfg index ac4b57d..a1f4101 100644 --- a/fapi_5g/bin/oran_5g_fapi.cfg +++ b/fapi_5g/bin/oran_5g_fapi.cfg @@ -22,18 +22,22 @@ ; Note: ; Schedule Policy [1: SCHED_FIFO 2: SCHED_RR] [MAC2PHY_WORKER] -core_id = 11 +core_id = 18 thread_sched_policy = 1 thread_priority = 89 [PHY2MAC_WORKER] -core_id = 12 +core_id = 19 thread_sched_policy = 1 thread_priority = 89 -[WLS_CFG] -device_name = /dev/wls0 +[URLLC_WORKER] +core_id = 19 +thread_sched_policy = 1 +thread_priority = 96 +[WLS_CFG] +device_name = wls_f0 shmem_size = 2126512128 ; Log level @@ -42,16 +46,11 @@ shmem_size = 2126512128 ; error ; trace [LOGGER] -level = info +level = none [DPDK] ; IOVA Mode ; 0 - PA ; 1 - VA dpdk_iova_mode = 0 - -; URRLC Not Supported -; [URLLC_WORKER] -; core_id = 12 -; thread_priority = 96 -; thread_sched_policy = 0 +dpdk_memory_zone = gnb_f0 diff --git a/fapi_5g/build/makefile b/fapi_5g/build/makefile index 9797590..800c016 100644 --- a/fapi_5g/build/makefile +++ b/fapi_5g/build/makefile @@ -41,15 +41,14 @@ endif ############################################################## # TARGET ############################################################## -ifeq ($(RTE_TARGET),) - RTE_TARGET :=x86_64-native-linuxapp-icc -endif -############################################################## -# DPDK -############################################################## ifeq ($(RTE_SDK),) -$(info Please make sure RTE_SDK points to DPDK folder (current version of DPDK is 18.08)) - RTE_SDK := /opt/dpdk-18.08 + $(error "Please define RTE_SDK environment variable") +endif + +ifeq ($(MESON_BUILD),0) +RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) endif ############################################################## @@ -65,26 +64,24 @@ oran_5g_fapi_dep_file = $(BUILDDIR)/oran_5g_fapi_dep APP := ../bin/oran_5g_fapi INC := \ - $(WLSDIR) \ - $(SRCDIR)/../include \ - $(SRCDIR)/common \ - $(SRCDIR)/include \ - $(SRCDIR)/framework/workers \ - $(SRCDIR)/framework/wls/fapi2mac \ - $(SRCDIR)/framework/wls/fapi2phy \ - $(SRCDIR)/framework/wls/lib \ - $(SRCDIR)/api/fapi2mac \ - $(SRCDIR)/api/fapi2phy \ - $(FLEXRANDIR)/source/nr5g/api \ - $(FLEXRANDIR)/source/common \ - $(RTE_SDK)/$(RTE_TARGET)/include \ - $(SRCDIR)/api/fapi2phy/p5 \ - $(SRCDIR)/api/fapi2phy/p7 \ - $(SRCDIR)/api/fapi2mac/p5 \ - $(SRCDIR)/api/fapi2mac/p7 \ - $(SRCDIR)/utils \ - -INC := $(addprefix -I,$(INC)) + -I$(WLSDIR) \ + -I$(SRCDIR)/../include \ + -I$(SRCDIR)/common \ + -I$(SRCDIR)/include \ + -I$(SRCDIR)/framework/workers \ + -I$(SRCDIR)/framework/wls/fapi2mac \ + -I$(SRCDIR)/framework/wls/fapi2phy \ + -I$(SRCDIR)/framework/wls/lib \ + -I$(SRCDIR)/api/fapi2mac \ + -I$(SRCDIR)/api/fapi2phy \ + -I$(FLEXRANDIR)/source/nr5g/api \ + -I$(FLEXRANDIR)/source/common \ + -I$(SRCDIR)/api/fapi2phy/p5 \ + -I$(SRCDIR)/api/fapi2phy/p7 \ + -I$(SRCDIR)/api/fapi2mac/p5 \ + -I$(SRCDIR)/api/fapi2mac/p7 \ + -I$(SRCDIR)/utils \ + $(RTE_INC) \ DEFS := USE_WO_LOCK _GNU_SOURCE @@ -109,8 +106,12 @@ CFLAGS := $(CFLAGS) -Werror endif #RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive -RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lmvec -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive -LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lmvec -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls +ifeq ($(MESON_BUILD),0) +RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +else +RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive +endif +LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls LINUX_ORAN_5G_FAPI_SRC := \ $(SRCDIR)/nr5g_fapi.c \ @@ -120,8 +121,10 @@ LINUX_ORAN_5G_FAPI_SRC := \ $(SRCDIR)/utils/nr5g_fapi_stats.c \ $(SRCDIR)/utils/nr5g_fapi_memory.c \ $(SRCDIR)/utils/nr5g_fapi_cmd.c \ + $(SRCDIR)/utils/nr5g_fapi_snr_conversion.c \ $(SRCDIR)/framework/workers/nr5g_fapi_mac2phy_thread.c \ $(SRCDIR)/framework/workers/nr5g_fapi_phy2mac_thread.c \ + $(SRCDIR)/framework/workers/nr5g_fapi_urllc_thread.c \ $(SRCDIR)/framework/nr5g_fapi_framework.c \ $(SRCDIR)/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c \ $(SRCDIR)/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c \ @@ -139,9 +142,12 @@ LINUX_ORAN_5G_FAPI_SRC := \ $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_crc_ind.c \ $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_rach_ind.c \ $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_ind.c \ + $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_uci_ind.c \ $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_srs_ind.c \ $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_uci_ind.c \ + $(SRCDIR)/api/fapi2mac/p7/nr5g_fapi_proc_vendor_p7_msgs.c \ $(SRCDIR)/api/fapi2phy/nr5g_fapi_fapi2phy_api.c \ + $(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c \ $(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c \ $(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c \ $(SRCDIR)/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c \ @@ -171,7 +177,7 @@ endif .PHONY: $(APP) $(APP): $(DIRLIST) echo_options $(GEN_DEP) $(OBJS) @echo [LD] $(APP) - @$(CC) -o $(APP) $(OBJS) $(RTE_LIBS) $(LDFLAGS) + @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS) # $(OBJDUMP) -d $(APP) > $(APP).asm .PHONY : echo_options diff --git a/fapi_5g/include/fapi_vendor_extension.h b/fapi_5g/include/fapi_vendor_extension.h index ba16e57..aa0069b 100644 --- a/fapi_5g/include/fapi_vendor_extension.h +++ b/fapi_5g/include/fapi_vendor_extension.h @@ -23,6 +23,10 @@ extern "C" { #endif +#include + +#include "fapi_interface.h" + #define FAPI_VENDOR_MESSAGE 0x10 #define FAPI_VENDOR_EXT_SHUTDOWN_REQUEST 0x11 #define FAPI_VENDOR_EXT_SHUTDOWN_RESPONSE 0x12 @@ -31,14 +35,27 @@ extern "C" { #define FAPI_VENDOR_EXT_DL_IQ_SAMPLES 0x13 #define FAPI_VENDOR_EXT_UL_IQ_SAMPLES 0x14 #define FAPI_VENDOR_EXT_START_RESPONSE 0x15 +#define FAPI_VENDOR_EXT_ADD_REMOVE_CORE 0x16 #endif +#define FAPI_VENDOR_EXT_P7_IND 0x17 + /* ----- WLS Operation --- */ #define FAPI_VENDOR_MSG_HEADER_IND 0x1A // PDSCH Payload #define FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ 0x1B +#define MAX_SNR_COUNT (255) +#define FAPI_VENDOR_MAX_RXRU_NUM 16 +#define FAPI_VENDOR_MAX_TXRU_NUM 4 +#define FAPI_VENDOR_MAX_SRS_PORT_PER_UE 2 +#define FAPI_VENDOR_MAX_NUM_ANT 64 + +enum { + USE_VENDOR_EPREXSSB = 1 +}; + // Linked list header present at the top of all messages typedef struct _fapi_api_queue_elem { struct _fapi_api_queue_elem *p_next; @@ -57,9 +74,13 @@ extern "C" { #define FAPI_MAX_IQ_SAMPLE_FILE_SIZE 576 #define FAPI_MAX_IQ_SAMPLE_DL_PORTS 16 #define FAPI_MAX_IQ_SAMPLE_UL_PORTS 2 -#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS 8 +#define FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS 16 #define FAPI_MAX_IQ_SAMPLE_UL_ANTENNA 64 #define FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE 4096 + +#define FAPI_MAX_NUM_SET_CORE_MASK ( 4 ) +#define FAPI_MAX_MASK_OPTIONS ( 4 ) +#define FAPI_NUM_SPLIT_OPTIONS ( 22 ) #endif typedef struct { @@ -68,7 +89,14 @@ extern "C" { uint8_t group_hop_flag; uint8_t sequence_hop_flag; // uint8_t nDMRS_type_A_pos; - uint8_t pad[3]; + uint8_t prach_nr_of_rx_ru; + uint8_t nr_of_dl_ports; + uint8_t nr_of_ul_ports; + uint16_t urllc_capable; + uint16_t urllc_mini_slot_mask; + uint8_t ssb_subc_spacing; + uint8_t use_vendor_EpreXSSB; // values: USE_VENDOR_EPREXSSB - use; else don't use + uint8_t pad[2]; } fapi_config_req_vendor_msg_t; typedef struct { @@ -86,11 +114,135 @@ extern "C" { uint16_t slot; } fapi_stop_req_vendor_msg_t; +// P7 vendor extensions + typedef struct { + uint8_t nr_of_antenna_ports; + uint8_t nr_of_rx_ru; + uint8_t pad[2]; + uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM]; + // open for extension for new fields from ULSCHPDUStruct + } fapi_vendor_ul_pusch_pdu_t; + + typedef struct { + uint8_t nr_of_rx_ru; + uint8_t pad[1]; + uint16_t group_id; + uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM]; + // open for extension for new fields from ULCCHUCIPDUStruct + } fapi_vendor_ul_pucch_pdu_t; + + typedef struct { + uint8_t nr_of_rx_ru; + uint8_t pad[3]; + uint8_t rx_ru_idx[FAPI_VENDOR_MAX_RXRU_NUM]; + // open for extension for new fields from SRSPDUStruct + } fapi_vendor_ul_srs_pdu_t; + + typedef struct { + uint16_t pdu_type; + uint16_t pad; + union { + fapi_vendor_ul_pusch_pdu_t pusch_pdu; + fapi_vendor_ul_pucch_pdu_t pucch_pdu; + fapi_vendor_ul_srs_pdu_t srs_pdu; + // open for extension for prach vendor type (as in fapi_ul_tti_req_pdu_t) + } pdu; + } fapi_vendor_ul_tti_req_pdu_t; + + typedef struct { + fapi_vendor_ul_tti_req_pdu_t ul_pdus[FAPI_MAX_NUMBER_UL_PDUS_PER_TTI]; + uint8_t num_ul_pdu; + uint8_t pad[3]; + uint32_t sym; + // open for extension for new fields from PULConfigRequestStruct + } fapi_vendor_ul_tti_req_t; + + typedef struct { + uint16_t epre_ratio_of_pdcch_to_ssb; + uint16_t epre_ratio_of_dmrs_to_ssb; + // open for extension for new fields from DCIPDUStruct + } fapi_vendor_dl_dci_t; + + typedef struct { + uint16_t num_dl_dci; + uint8_t pad[2]; + fapi_vendor_dl_dci_t dl_dci[FAPI_MAX_NUMBER_DL_DCI]; + } fapi_vendor_dl_pdcch_pdu_t; + + typedef struct { + uint16_t epre_ratio_of_pdsch_to_ssb; + uint16_t epre_ratio_of_dmrs_to_ssb; + uint8_t nr_of_antenna_ports; + uint8_t pad[3]; + uint8_t tx_ru_idx[FAPI_VENDOR_MAX_TXRU_NUM]; + // open for extension for new fields from DLSCHPDUStruct + } fapi_vendor_dl_pdsch_pdu_t; + + typedef struct { + uint16_t epre_ratio_to_ssb; + uint8_t pad[2]; + } fapi_vendor_csi_rs_pdu_t; + + typedef struct { + uint16_t pdu_type; + uint16_t pdu_size; + union { + fapi_vendor_dl_pdcch_pdu_t pdcch_pdu; + fapi_vendor_dl_pdsch_pdu_t pdsch_pdu; + fapi_vendor_csi_rs_pdu_t csi_rs_pdu; + // open for extension for ssb vendor types (as in fapi_dl_tti_req_pdu_t) + } pdu; + } fapi_vendor_dl_tti_req_pdu_t; + + typedef struct { + uint32_t sym; + uint16_t lte_crs_carrier_freq_dl; + uint8_t lte_crs_present; + uint8_t lte_crs_carrier_bandwidth_dl; + uint8_t lte_crs_nr_of_crs_ports; + uint8_t lte_crs_v_shift; + uint8_t pdcch_precoder_en; + uint8_t ssb_precoder_en; + uint8_t num_pdus; + uint8_t pad[3]; + fapi_vendor_dl_tti_req_pdu_t pdus[FAPI_MAX_PDUS_PER_SLOT]; + // open for extension for new fields from DLConfigRequestStruct + } fapi_vendor_dl_tti_req_t; + + typedef struct { + uint16_t pdu_type; + uint16_t pdu_size; + fapi_vendor_dl_pdcch_pdu_t pdcch_pdu_config; + } fapi_vendor_dci_pdu_t; + + typedef struct { + uint32_t sym; + uint8_t num_pdus; + uint8_t pad[3]; + fapi_vendor_dci_pdu_t pdus[FAPI_MAX_NUMBER_UCI_PDUS_PER_SLOT]; + // open for extension for new fields from ULDCIRequestStruct + } fapi_vendor_ul_dci_req_t; + + typedef struct { + uint32_t sym; + // open for extension for new fields from TXRequestStruct + } fapi_vendor_tx_data_req_t; + + typedef struct { + fapi_vendor_dl_tti_req_t dl_tti_req; + fapi_vendor_ul_tti_req_t ul_tti_req; + fapi_vendor_ul_dci_req_t ul_dci_req; + fapi_vendor_tx_data_req_t tx_data_req; + } fapi_vendor_p7_msg_t; + +// P7 vendor extensions end + typedef struct { fapi_msg_t header; fapi_config_req_vendor_msg_t config_req_vendor; fapi_start_req_vendor_msg_t start_req_vendor; fapi_stop_req_vendor_msg_t stop_req_vendor; + fapi_vendor_p7_msg_t p7_req_vendor; } fapi_vendor_msg_t; typedef struct { @@ -107,6 +259,58 @@ extern "C" { uint32_t nStatus; } fapi_vendor_ext_shutdown_res_t; + typedef struct { + int16_t nSNR[MAX_SNR_COUNT]; + int16_t pad; + } fapi_vendor_ext_snr_t; + + typedef struct { + uint8_t nr_of_port; + uint8_t nr_of_rx_ant; + uint16_t nr_of_rbs; + uint8_t is_chan_est_pres; + uint8_t pad[3]; + int16_t *p_srs_chan_est[FAPI_VENDOR_MAX_SRS_PORT_PER_UE] + [FAPI_VENDOR_MAX_NUM_ANT]; + } fapi_vendor_ext_srs_pdu_t; + + typedef struct { + uint8_t num_pdus; + uint8_t pad[3]; + fapi_vendor_ext_srs_pdu_t srs_pdus[FAPI_MAX_NUMBER_SRS_PDUS_PER_SLOT]; + } fapi_vendor_ext_srs_ind_t; + + typedef struct { + uint32_t carrier_idx; + uint32_t sym; + } fapi_vendor_ext_slot_ind_t; + + typedef struct { + uint32_t carrier_idx; + uint32_t sym; + } fapi_vendor_ext_rx_data_ind_t; + + typedef struct { + uint32_t carrier_idx; + uint32_t sym; + } fapi_vendor_ext_crc_ind_t; + + typedef struct { + uint32_t carrier_idx; + uint32_t sym; + } fapi_vendor_ext_uci_ind_t; + + typedef struct { + fapi_msg_t header; + fapi_vendor_ext_snr_t crc_snr; + fapi_vendor_ext_snr_t uci_snr; + fapi_vendor_ext_srs_ind_t srs_ind; + fapi_vendor_ext_slot_ind_t slot_ind; + fapi_vendor_ext_rx_data_ind_t rx_data_ind; + fapi_vendor_ext_crc_ind_t crc_ind; + fapi_vendor_ext_uci_ind_t uci_ind; + } fapi_vendor_p7_ind_msg_t; + #ifdef DEBUG_MODE typedef struct { uint32_t carrNum; @@ -119,6 +323,8 @@ extern "C" { uint32_t startSymNum; char filename_in_ul_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS] [FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; + char filename_in_ul_iq_compressed[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS] + [FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; char filename_in_prach_iq[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS] [FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; char filename_in_srs_iq[FAPI_MAX_IQ_SAMPLE_UL_ANTENNA] @@ -128,6 +334,19 @@ extern "C" { [FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; char filename_out_ul_beam[FAPI_MAX_IQ_SAMPLE_UL_VIRTUAL_PORTS] [FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; + char filename_out_dl_iq_compressed[FAPI_MAX_IQ_SAMPLE_FILE_SIZE]; + + /* DL Compression add */ + uint16_t nDLCompressionIdx; + uint16_t nDLCompiqWidth; + uint16_t nDLCompScaleFactor; + uint16_t nDLCompreMask; + + /*nULDecompressionIdx, determine the UL Decompression method, Value:0->4*/ + /*0:NONE, 1:BLKFLOAT, 2:BLKSCALE, 3:ULAW, 4:MODULATION*/ + uint16_t nULDecompressionIdx; + uint16_t nULDecompiqWidth; + uint8_t buffer[FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE]; } fapi_vendor_ext_iq_samples_info_t; @@ -147,6 +366,17 @@ extern "C" { typedef struct { fapi_msg_t header; } fapi_vendor_ext_start_response_t; + + typedef struct { + uint32_t eOption; + uint64_t nCoreMask[FAPI_MAX_MASK_OPTIONS][FAPI_MAX_NUM_SET_CORE_MASK]; + uint32_t nMacOptions[FAPI_NUM_SPLIT_OPTIONS]; + } fapi_vendor_ext_add_remove_core_info_t; + + typedef struct { + fapi_msg_t header; + fapi_vendor_ext_add_remove_core_info_t add_remove_core_info; + } fapi_vendor_ext_add_remove_core_msg_t; #endif #if defined(__cplusplus) diff --git a/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.c b/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.c index 9af8822..610f9a1 100644 --- a/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.c +++ b/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.c @@ -30,23 +30,26 @@ #include "nr5g_fapi_log.h" static nr5g_fapi_fapi2mac_queue_t fapi2mac_q[FAPI_MAX_PHY_INSTANCES]; +static nr5g_fapi_fapi2mac_queue_t fapi2mac_urllc_q[FAPI_MAX_PHY_INSTANCES]; + //------------------------------------------------------------------------------ /** @ingroup group_source_api_fapi2phy * - * @param[in] p_list_elem Pointer to the ListElement + * @param[in] phy_id Value of phy_id. + * @param[in] is_urllc True for urllc, false otherwise. * - * @return void + * @return Pointer to fapi2mac api queue. * - * @description This function adds a ListElement API to a Linked list which will - * be sent to L1 once all APIs for a TTI are added + * @description This function access proper instance of fapi2mac queue. * **/ //------------------------------------------------------------------------------ static inline p_nr5g_fapi_fapi2mac_queue_t nr5g_fapi_fapi2mac_queue( - uint8_t phy_id) + uint8_t phy_id, + bool is_urllc) { - return &fapi2mac_q[phy_id]; + return is_urllc ? &fapi2mac_urllc_q[phy_id] : &fapi2mac_q[phy_id]; } //------------------------------------------------------------------------------ @@ -63,7 +66,8 @@ static inline p_nr5g_fapi_fapi2mac_queue_t nr5g_fapi_fapi2mac_queue( //------------------------------------------------------------------------------ void nr5g_fapi_fapi2mac_add_api_to_list( uint8_t phy_id, - p_fapi_api_queue_elem_t p_list_elem) + p_fapi_api_queue_elem_t p_list_elem, + bool is_urllc) { p_nr5g_fapi_fapi2mac_queue_t queue = NULL; p_fapi_msg_header_t p_fapi_msg_hdr = NULL; @@ -72,7 +76,7 @@ void nr5g_fapi_fapi2mac_add_api_to_list( return; } - queue = nr5g_fapi_fapi2mac_queue(phy_id); + queue = nr5g_fapi_fapi2mac_queue(phy_id, is_urllc); if (pthread_mutex_lock((pthread_mutex_t *) & queue->lock)) { NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock fapi2mac aggregate list" "pthread mutex")); @@ -105,7 +109,7 @@ void nr5g_fapi_fapi2mac_add_api_to_list( **/ //------------------------------------------------------------------------------ void nr5g_fapi_fapi2mac_send_api_list( - ) + bool is_urllc) { uint8_t phy_id = 0; p_fapi_msg_header_t p_fapi_msg_hdr = NULL; @@ -114,7 +118,7 @@ void nr5g_fapi_fapi2mac_send_api_list( p_nr5g_fapi_fapi2mac_queue_t queue = NULL; for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) { - queue = nr5g_fapi_fapi2mac_queue(phy_id); + queue = nr5g_fapi_fapi2mac_queue(phy_id, is_urllc); if (pthread_mutex_lock((pthread_mutex_t *) & queue->lock)) { NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock fapi2mac aggregate list" "pthread mutex")); @@ -145,7 +149,7 @@ void nr5g_fapi_fapi2mac_send_api_list( } if (p_commit_list_head) - nr5g_fapi_fapi2mac_wls_send(p_commit_list_head); + nr5g_fapi_fapi2mac_wls_send(p_commit_list_head, is_urllc); } //------------------------------------------------------------------------------ @@ -203,7 +207,9 @@ void nr5g_fapi_fapi2mac_init_api_list( p_nr5g_fapi_fapi2mac_queue_t queue = NULL; for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) { - queue = nr5g_fapi_fapi2mac_queue(phy_id); + queue = nr5g_fapi_fapi2mac_queue(phy_id, false); + pthread_mutex_init((pthread_mutex_t *) & queue->lock, NULL); + queue = nr5g_fapi_fapi2mac_queue(phy_id, true); pthread_mutex_init((pthread_mutex_t *) & queue->lock, NULL); } } diff --git a/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.h b/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.h index 13aabe7..ec89d8e 100644 --- a/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.h +++ b/fapi_5g/source/api/fapi2mac/nr5g_fapi_fapi2mac_api.h @@ -43,11 +43,12 @@ p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_create_api_list_elem( uint32_t align_offset); void nr5g_fapi_fapi2mac_send_api_list( - ); + bool is_urllc); void nr5g_fapi_fapi2mac_add_api_to_list( uint8_t phy_id, - p_fapi_api_queue_elem_t p_list_elem); + p_fapi_api_queue_elem_t p_list_elem, + bool is_urllc); void nr5g_fapi_fapi2mac_init_api_list( ); diff --git a/fapi_5g/source/api/fapi2mac/nr5g_fapi_proc_error_ind.c b/fapi_5g/source/api/fapi2mac/nr5g_fapi_proc_error_ind.c index e51e851..9b39d0d 100644 --- a/fapi_5g/source/api/fapi2mac/nr5g_fapi_proc_error_ind.c +++ b/fapi_5g/source/api/fapi2mac/nr5g_fapi_proc_error_ind.c @@ -87,7 +87,7 @@ uint8_t nr5g_fapi_error_indication( // p_fapi_error_ind->message_id = ; // TODO message id is not supported in IAPI error indication p_fapi_error_ind->error_code = p_iapi_resp->nStatus; - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); // phyStats->iaL1ApiStats.errorInd++; //TODO NR5G_FAPI_LOG(INFO_LOG, ("[NR5G_FAPI][ERROR.indication][%d][%d,%d]", diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_fapi2mac_p5_proc.h b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_fapi2mac_p5_proc.h index 62ef586..bdccc6a 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_fapi2mac_p5_proc.h +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_fapi2mac_p5_proc.h @@ -29,10 +29,12 @@ #include "gnb_l1_l2_api.h" uint8_t nr5g_fapi_message_header( - p_nr5g_fapi_phy_ctx_t p_phy_ctx); + p_nr5g_fapi_phy_ctx_t p_phy_ctx, + bool is_urllc); uint8_t nr5g_fapi_message_header_per_phy( - uint8_t phy_id); + uint8_t phy_id, + bool is_urllc); uint8_t nr5g_fapi_config_response( p_nr5g_fapi_phy_ctx_t p_phy_ctx, diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_config_resp.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_config_resp.c index a7669ac..805cbe7 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_config_resp.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_config_resp.c @@ -66,7 +66,7 @@ uint8_t nr5g_fapi_config_response( } // Create FAPI message header if (FAPI_STATE_IDLE == p_phy_instance->state) - nr5g_fapi_message_header_per_phy(phy_id); + nr5g_fapi_message_header_per_phy(phy_id, false); p_stats = &p_phy_instance->stats; p_stats->iapi_stats.iapi_config_res++; @@ -97,7 +97,7 @@ uint8_t nr5g_fapi_config_response( p_fapi_resp->number_of_missing_tlvs = 0; // Add element to send list - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_config_res++; NR5G_FAPI_LOG(INFO_LOG, ("[CONFIG.response][%d]", phy_id)); diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_dl_iq_samples_resp.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_dl_iq_samples_resp.c index ac0ab4b..4b241e3 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_dl_iq_samples_resp.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_dl_iq_samples_resp.c @@ -83,7 +83,7 @@ uint8_t nr5g_fapi_dl_iq_samples_response( (uint16_t) sizeof(fapi_vendor_ext_dl_iq_samples_res_t); /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); NR5G_FAPI_LOG(INFO_LOG, ("[DL_IQ_SAMPLES.response][%d]", phy_id)); diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_fapi_msg_header.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_fapi_msg_header.c index 4a53560..458b181 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_fapi_msg_header.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_fapi_msg_header.c @@ -39,14 +39,15 @@ * **/ uint8_t nr5g_fapi_message_header( - p_nr5g_fapi_phy_ctx_t p_phy_ctx) + p_nr5g_fapi_phy_ctx_t p_phy_ctx, + bool is_urllc) { uint8_t phy_id = 0; for (phy_id = 0; phy_id < FAPI_MAX_PHY_INSTANCES; phy_id++) { if ((FAPI_STATE_CONFIGURED == p_phy_ctx->phy_instance[phy_id].state) || (FAPI_STATE_RUNNING == p_phy_ctx->phy_instance[phy_id].state)) { - nr5g_fapi_message_header_per_phy(phy_id); + nr5g_fapi_message_header_per_phy(phy_id, is_urllc); } } @@ -64,7 +65,8 @@ uint8_t nr5g_fapi_message_header( * **/ uint8_t nr5g_fapi_message_header_per_phy( - uint8_t phy_id) + uint8_t phy_id, + bool is_urllc) { p_fapi_api_queue_elem_t p_list_elem = NULL; p_fapi_msg_header_t p_fapi_msg_hdr = NULL; @@ -83,7 +85,7 @@ uint8_t nr5g_fapi_message_header_per_phy( p_fapi_msg_hdr->handle = phy_id; // Add element to send list - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); NR5G_FAPI_LOG(DEBUG_LOG, ("[FAPI MSG HDR] FAPI Message Header Added for PHY: %d", phy_id)); diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_shutdown_resp.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_shutdown_resp.c index 454b0cf..4626cd9 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_shutdown_resp.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_shutdown_resp.c @@ -100,7 +100,7 @@ uint8_t nr5g_fapi_shutdown_response( p_fapi_resp->nStatus = p_iapi_resp->nStatus; /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_vext_shutdown_res++; NR5G_FAPI_LOG(INFO_LOG, ("[SHUTDOWN.response][%d]", phy_id)); @@ -120,7 +120,7 @@ uint8_t nr5g_fapi_shutdown_response( p_stop_ind->header.length = sizeof(fapi_stop_ind_t); /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_stop_ind++; NR5G_FAPI_LOG(INFO_LOG, ("[STOP.Indication][%d]", phy_id)); @@ -137,8 +137,8 @@ uint8_t nr5g_fapi_shutdown_response( fapi_req.sfn = 0; fapi_req.slot = 0; fapi_req.test_type = p_phy_instance->shutdown_test_type; - nr5g_fapi_shutdown_request(p_phy_instance, &fapi_req); - nr5g_fapi_fapi2phy_send_api_list(); + nr5g_fapi_shutdown_request(0, p_phy_instance, &fapi_req); + nr5g_fapi_fapi2phy_send_api_list(0); } else { NR5G_FAPI_LOG(ERROR_LOG, ("[SHUTDOWN.response] Invalid status " "from PHY, hence triggering Error Indication")); @@ -162,7 +162,7 @@ uint8_t nr5g_fapi_shutdown_response( p_fapi_error_ind->error_code = p_iapi_resp->nStatus; /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_error_ind++; p_phy_instance->shutdown_retries = 0; NR5G_FAPI_LOG(INFO_LOG, ("[Error.Indication][%d]", phy_id)); diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_start_resp.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_start_resp.c index 3837958..ee48bec 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_start_resp.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_start_resp.c @@ -92,7 +92,7 @@ uint8_t nr5g_fapi_start_resp( (uint16_t) sizeof(fapi_vendor_ext_start_response_t); /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_vext_start_res++; NR5G_FAPI_LOG(INFO_LOG, ("[START.response][%d]", phy_id)); #endif @@ -116,7 +116,7 @@ uint8_t nr5g_fapi_start_resp( p_fapi_error_ind->error_code = p_iapi_resp->nStatus; /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_error_ind++; NR5G_FAPI_LOG(INFO_LOG, ("[ERROR.Indication][%d]", phy_id)); } else { diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_stop_ind.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_stop_ind.c index 9674f3f..a51e46d 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_stop_ind.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_stop_ind.c @@ -90,7 +90,7 @@ uint8_t nr5g_fapi_stop_indication( p_fapi_resp->header.msg_id = FAPI_STOP_INDICATION; p_fapi_resp->header.length = (uint16_t) sizeof(fapi_stop_ind_t); /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_stop_ind++; NR5G_FAPI_LOG(INFO_LOG, ("[STOP.indication][%d]", phy_id)); #else @@ -100,8 +100,8 @@ uint8_t nr5g_fapi_stop_indication( fapi_req.sfn = 0; fapi_req.slot = 0; fapi_req.test_type = 0; - nr5g_fapi_shutdown_request(p_phy_instance, &fapi_req); - nr5g_fapi_fapi2phy_send_api_list(); + nr5g_fapi_shutdown_request(0, p_phy_instance, &fapi_req); + nr5g_fapi_fapi2phy_send_api_list(0); #endif } else if (FAILURE == p_iapi_resp->nStatus) { p_list_elem = @@ -122,7 +122,7 @@ uint8_t nr5g_fapi_stop_indication( p_fapi_error_ind->message_id = FAPI_STOP_REQUEST; p_fapi_error_ind->error_code = p_iapi_resp->nStatus; /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_error_ind++; NR5G_FAPI_LOG(INFO_LOG, ("[STOP.indication][ERROR.indication][%d]", phy_id)); diff --git a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_ul_iq_samples_resp.c b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_ul_iq_samples_resp.c index eb21f34..fba54b4 100644 --- a/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_ul_iq_samples_resp.c +++ b/fapi_5g/source/api/fapi2mac/p5/nr5g_fapi_proc_ul_iq_samples_resp.c @@ -63,7 +63,7 @@ uint8_t nr5g_fapi_ul_iq_samples_response( p_phy_instance = &p_phy_ctx->phy_instance[phy_id]; // Create FAPI message header if (p_phy_instance->state == FAPI_STATE_IDLE) { - nr5g_fapi_message_header_per_phy(phy_id); + nr5g_fapi_message_header_per_phy(phy_id, false); } p_list_elem = @@ -81,9 +81,9 @@ uint8_t nr5g_fapi_ul_iq_samples_response( (uint16_t) sizeof(fapi_vendor_ext_ul_iq_samples_res_t); /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); - NR5G_FAPI_LOG(INFO_LOG, ("[UL_IQ_SAMPLES.response]%d]", phy_id)); + NR5G_FAPI_LOG(INFO_LOG, ("[UL_IQ_SAMPLES.response][%d]", phy_id)); return SUCCESS; } diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_proc.h b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_proc.h index aaaae0d..675e1b2 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_proc.h +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_proc.h @@ -26,22 +26,48 @@ #ifndef _NR5G_FAPI_FAP2MAC_P7_PROC_H_ #define _NR5G_FAPI_FAP2MAC_P7_PROC_H_ +typedef struct { + p_fapi_api_queue_elem_t vendor_ext[FAPI_MAX_PHY_INSTANCES]; +} fapi_api_stored_vendor_queue_elems, +*p_fapi_api_stored_vendor_queue_elems; + uint8_t nr5g_fapi_slot_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PSlotIndicationStruct p_iapi_resp); uint8_t nr5g_fapi_rach_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, PRXRACHIndicationStruct p_phy_rach_ind); uint8_t nr5g_fapi_crc_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PCRCIndicationStruct p_phy_crc_ind); uint8_t nr5g_fapi_rx_data_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXULSCHIndicationStruct p_phy_ulsch_ind); +uint8_t nr5g_fapi_rx_data_uci_indication( + bool is_urllc, + p_nr5g_fapi_phy_ctx_t p_phy_ctx, + PRXULSCHUCIIndicationStruct p_phy_rx_ulsch_uci_ind); uint8_t nr5g_fapi_uci_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXUCIIndicationStruct p_phy_uci_ind); uint8_t nr5g_fapi_srs_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXSRSIndicationStruct p_phy_srs_ind); +fapi_vendor_p7_ind_msg_t* nr5g_fapi_proc_vendor_p7_msg_get( + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, + uint8_t phy_id); +void nr5g_fapi_proc_vendor_p7_msgs_move_to_api_list( + bool is_urllc, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems); #endif //_NR5G_FAPI_FAP2MAC_P7_PROC_H_ diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_pvt_proc.h b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_pvt_proc.h index 121bafc..180bbcf 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_pvt_proc.h +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_fapi2mac_p7_pvt_proc.h @@ -27,29 +27,42 @@ #define _NR5G_FAPI_FAP2MAC_P7_PVT_PROC_H_ uint8_t nr5g_fapi_rach_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXRACHIndicationStruct p_phy_rach_ind, fapi_rach_indication_t * p_fapi_rach_ind); uint8_t nr5g_fapi_crc_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PCRCIndicationStruct p_phy_crc_ind, - fapi_crc_ind_t * p_fapi_crc_ind); + fapi_crc_ind_t * p_fapi_crc_ind, + fapi_vendor_ext_snr_t * p_fapi_snr); uint8_t nr5g_fapi_rx_data_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXULSCHIndicationStruct p_phy_rx_ulsch_ind, fapi_rx_data_indication_t * p_fapi_rx_data_ind); +uint8_t nr5g_fapi_rx_data_uci_indication_to_fapi_translation( + p_nr5g_fapi_phy_instance_t p_phy_instance, + PRXULSCHUCIIndicationStruct p_phy_rx_ulsch_uci_ind, + fapi_uci_indication_t * p_fapi_uci_ind); + uint8_t nr5g_fapi_uci_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXUCIIndicationStruct p_phy_uci_ind, - fapi_uci_indication_t * p_fapi_uci_ind); + fapi_uci_indication_t * p_fapi_uci_ind, + fapi_vendor_ext_snr_t * p_fapi_snr); uint8_t nr5g_fapi_srs_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXSRSIndicationStruct p_phy_srs_ind, - fapi_srs_indication_t * p_fapi_srs_ind); + fapi_srs_indication_t * p_fapi_srs_ind, + fapi_vendor_ext_srs_ind_t * p_fapi_vend_srs_ind); nr5g_fapi_pusch_info_t *nr5g_fapi_get_pusch_info( uint16_t ue_id, diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_add_remove_core_msg.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_add_remove_core_msg.c new file mode 100644 index 0000000..5164423 --- /dev/null +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_add_remove_core_msg.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#include "fapi_vendor_extension.h" +#include "gnb_l1_l2_api.h" +#include "nr5g_fapi_common_types.h" +#include "nr5g_fapi_fapi2phy_api.h" +#include "nr5g_fapi_log.h" + +/** + * @file + * This file consist of implementation of FAPI VENDOR ADD_REMOVE_CORE message. + * + **/ + +/** @ingroup group_source_api_p5_fapi2phy_proc + * + * @param[in] p_fapi_req Pointer to FAPI VENDOR ADD_REMOVE_CORE message structure. + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This is a timer mode specific message used to set options on bbupool cores. + * + */ +#ifdef DEBUG_MODE +uint8_t nr5g_fapi_add_remove_core_message( + bool is_urllc, + fapi_vendor_ext_add_remove_core_msg_t * p_fapi_req) +{ + uint32_t i, k; + PMAC2PHY_QUEUE_EL p_list_elem; + PADD_REMOVE_BBU_CORES p_add_remove_bbu_cores; + + /* Below print is for better logging on console in debug mode. */ + NR5G_FAPI_LOG(INFO_LOG, ("")); + + if (NULL == p_fapi_req) { + NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Invalid fapi message")); + return FAILURE; + } + + p_list_elem = nr5g_fapi_fapi2phy_create_api_list_elem( + (uint8_t)MSG_TYPE_PHY_ADD_REMOVE_CORE, 1, (uint32_t) sizeof(ADD_REMOVE_BBU_CORES)); + + if (!p_list_elem) { + NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Unable to create " + "list element. Out of memory!!!")); + return FAILURE; + } + + p_add_remove_bbu_cores = (PADD_REMOVE_BBU_CORES) (p_list_elem + 1); + p_add_remove_bbu_cores->sMsgHdr.nMessageType = MSG_TYPE_PHY_ADD_REMOVE_CORE; + p_add_remove_bbu_cores->sMsgHdr.nMessageLen = sizeof(ADD_REMOVE_BBU_CORES); + + for (i = 0; i < FAPI_MAX_NUM_SET_CORE_MASK; ++i) + { + for (k = 0; k < FAPI_MAX_MASK_OPTIONS; ++k) + { + p_add_remove_bbu_cores->nCoreMask[k][i] = p_fapi_req->add_remove_core_info.nCoreMask[k][i]; + } + } + for (i = 0; i < FAPI_NUM_SPLIT_OPTIONS; ++i) + { + p_add_remove_bbu_cores->nMacOptions[i] = p_fapi_req->add_remove_core_info.nMacOptions[i]; + } + p_add_remove_bbu_cores->eOption = (BBUPOOL_CORE_OPERATION)p_fapi_req->add_remove_core_info.eOption; + + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); + + NR5G_FAPI_LOG(INFO_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE.message]")); + + return SUCCESS; +} +#endif diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_crc_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_crc_ind.c index e151b65..9b1cd95 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_crc_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_crc_ind.c @@ -26,6 +26,7 @@ #include "nr5g_fapi_fapi2mac_api.h" #include "nr5g_fapi_fapi2mac_p7_proc.h" #include "nr5g_fapi_fapi2mac_p7_pvt_proc.h" +#include "nr5g_fapi_snr_conversion.h" /** @ingroup group_source_api_p7_fapi2mac_proc * @@ -39,7 +40,9 @@ * **/ uint8_t nr5g_fapi_crc_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PCRCIndicationStruct p_phy_crc_ind) { uint8_t phy_id; @@ -72,6 +75,7 @@ uint8_t nr5g_fapi_crc_indication( p_list_elem = nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_CRC_INDICATION, 1, sizeof(fapi_crc_ind_t)); + if (!p_list_elem) { NR5G_FAPI_LOG(ERROR_LOG, ("[CRC.indication] Unable to create " "list element. Out of memory!!!")); @@ -82,20 +86,31 @@ uint8_t nr5g_fapi_crc_indication( p_fapi_crc_ind->header.msg_id = FAPI_CRC_INDICATION; p_fapi_crc_ind->header.length = (uint16_t) sizeof(fapi_crc_ind_t); - if (nr5g_fapi_crc_indication_to_fapi_translation(p_phy_instance, - p_phy_crc_ind, p_fapi_crc_ind)) { + fapi_vendor_p7_ind_msg_t* p_fapi_vend_p7 = + nr5g_fapi_proc_vendor_p7_msg_get(vendor_extension_elems, phy_id); + fapi_vendor_ext_snr_t* p_fapi_snr = p_fapi_vend_p7 ? &p_fapi_vend_p7->crc_snr : NULL; + fapi_vendor_ext_crc_ind_t* p_fapi_vend_crc_ind = p_fapi_vend_p7 ? &p_fapi_vend_p7->crc_ind : NULL; + + if (p_fapi_vend_crc_ind) { + p_fapi_vend_crc_ind->carrier_idx = phy_id; + p_fapi_vend_crc_ind->sym = p_phy_crc_ind->sSFN_Slot.nSym; + } + + if (nr5g_fapi_crc_indication_to_fapi_translation(is_urllc, p_phy_instance, + p_phy_crc_ind, p_fapi_crc_ind, p_fapi_snr)) { NR5G_FAPI_LOG(ERROR_LOG, ("[CRC.indication] L1 to FAPI " "translation failed")); return FAILURE; } - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); p_stats->fapi_stats.fapi_crc_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[CRC.indication][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[CRC.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_phy_crc_ind->sSFN_Slot.nSFN, p_phy_crc_ind->sSFN_Slot.nSlot)); + p_phy_crc_ind->sSFN_Slot.nSFN, p_phy_crc_ind->sSFN_Slot.nSlot, + p_phy_crc_ind->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -114,13 +129,15 @@ uint8_t nr5g_fapi_crc_indication( * **/ uint8_t nr5g_fapi_crc_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PCRCIndicationStruct p_phy_crc_ind, - fapi_crc_ind_t * p_fapi_crc_ind) + fapi_crc_ind_t * p_fapi_crc_ind, + fapi_vendor_ext_snr_t * p_fapi_snr) { uint8_t num_crc, i; - uint8_t slot_no; - uint16_t frame_no; + uint8_t symbol_no; + uint16_t slot_no, frame_no; nr5g_fapi_pusch_info_t *p_pusch_info; fapi_crc_ind_info_t *p_fapi_crc_ind_info; @@ -132,13 +149,14 @@ uint8_t nr5g_fapi_crc_indication_to_fapi_translation( frame_no = p_fapi_crc_ind->sfn = p_phy_crc_ind->sSFN_Slot.nSFN; slot_no = p_fapi_crc_ind->slot = p_phy_crc_ind->sSFN_Slot.nSlot; + symbol_no = p_phy_crc_ind->sSFN_Slot.nSym; p_ul_slot_info = - nr5g_fapi_get_ul_slot_info(frame_no, slot_no, p_phy_instance); + nr5g_fapi_get_ul_slot_info(is_urllc, frame_no, slot_no, symbol_no, p_phy_instance); if (p_ul_slot_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, (" [CRC.indication] No Valid data available " - "for frame :%d and slot: %d", frame_no, slot_no)); + "for frame :%d, slot: %d, symbol: %d, urllc %u", frame_no, slot_no, symbol_no, is_urllc)); return FAILURE; } @@ -154,8 +172,8 @@ uint8_t nr5g_fapi_crc_indication_to_fapi_translation( if (p_pusch_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, (" [CRC.indication] No Valid data available " - "nUEId:%d, frame_no:%d, slot_no:%d", p_ul_crc_struct->nUEId, - frame_no, slot_no)); + "nUEId:%d, frame_no:%d, slot_no:%d, urllc %u", p_ul_crc_struct->nUEId, + frame_no, slot_no, is_urllc)); return FAILURE; } @@ -163,7 +181,11 @@ uint8_t nr5g_fapi_crc_indication_to_fapi_translation( p_fapi_crc_ind_info->rnti = p_ul_crc_struct->nRNTI; p_fapi_crc_ind_info->harqId = p_pusch_info->harq_process_id; p_fapi_crc_ind_info->tbCrcStatus = !(p_ul_crc_struct->nCrcFlag); - p_fapi_crc_ind_info->ul_cqi = (p_ul_crc_struct->nSNR + 64) * 2; + p_fapi_crc_ind_info->ul_cqi = nr5g_fapi_convert_snr_iapi_to_fapi(p_ul_crc_struct->nSNR); + if(p_fapi_snr) + { + p_fapi_snr->nSNR[i] = p_ul_crc_struct->nSNR; + } p_pusch_info->ul_cqi = p_fapi_crc_ind_info->ul_cqi; p_fapi_crc_ind_info->numCb = 0; diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rach_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rach_ind.c index bd40411..fd29b50 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rach_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rach_ind.c @@ -39,6 +39,7 @@ * **/ uint8_t nr5g_fapi_rach_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, PRXRACHIndicationStruct p_phy_rach_ind) { @@ -84,19 +85,20 @@ uint8_t nr5g_fapi_rach_indication( p_fapi_rach_ind->header.msg_id = FAPI_RACH_INDICATION; p_fapi_rach_ind->header.length = (uint16_t) sizeof(fapi_rach_indication_t); - if (nr5g_fapi_rach_indication_to_fapi_translation(p_phy_instance, + if (nr5g_fapi_rach_indication_to_fapi_translation(is_urllc, p_phy_instance, p_phy_rach_ind, p_fapi_rach_ind)) { NR5G_FAPI_LOG(ERROR_LOG, ("[RACH.indication] L1 to FAPI " "translation failed")); return FAILURE; } - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, false); p_stats->fapi_stats.fapi_rach_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[RACH.indication][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[RACH.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_phy_rach_ind->sSFN_Slot.nSFN, p_phy_rach_ind->sSFN_Slot.nSlot)); + p_phy_rach_ind->sSFN_Slot.nSFN, p_phy_rach_ind->sSFN_Slot.nSlot, + p_phy_rach_ind->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -154,15 +156,16 @@ uint8_t nr5g_fapi_start_slot_freq_idx_occ( * **/ uint8_t nr5g_fapi_rach_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXRACHIndicationStruct p_phy_rach_ind, fapi_rach_indication_t * p_fapi_rach_ind) { uint8_t num_preamble, num_pdus = 0, i; - uint8_t slot_no, preamble_no; + uint8_t symbol_no, preamble_no; uint8_t slot_freq_idx_entry; uint8_t slot_index, freq_index, symbol_index; - uint16_t frame_no; + uint16_t slot_no, frame_no; fapi_rach_pdu_t *p_fapi_rach_pdu; fapi_rach_pdu_t *p_fapi_rach_pdu_match; @@ -175,9 +178,10 @@ uint8_t nr5g_fapi_rach_indication_to_fapi_translation( frame_no = p_fapi_rach_ind->sfn = p_phy_rach_ind->sSFN_Slot.nSFN; slot_no = p_fapi_rach_ind->slot = p_phy_rach_ind->sSFN_Slot.nSlot; + symbol_no = p_phy_rach_ind->sSFN_Slot.nSym; p_ul_slot_info = - nr5g_fapi_get_ul_slot_info(frame_no, slot_no, p_phy_instance); + nr5g_fapi_get_ul_slot_info(is_urllc, frame_no, slot_no, symbol_no, p_phy_instance); if (p_ul_slot_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, ("[RACH.indication] No Valid data available " diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_ind.c index 666e811..3a1183a 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_ind.c @@ -40,11 +40,12 @@ * **/ uint8_t nr5g_fapi_rx_data_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXULSCHIndicationStruct p_phy_rx_ulsch_ind) { uint8_t phy_id; - fapi_rx_data_indication_t *p_fapi_rx_data_ind; p_fapi_api_queue_elem_t p_list_elem; p_nr5g_fapi_phy_instance_t p_phy_instance = NULL; @@ -72,9 +73,11 @@ uint8_t nr5g_fapi_rx_data_indication( p_stats = &p_phy_instance->stats; p_stats->iapi_stats.iapi_rx_data_ind++; + p_list_elem = nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_RX_DATA_INDICATION, 1, sizeof(fapi_rx_data_indication_t)); + if (!p_list_elem) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI][RX_DATA.indication] Unable to create " @@ -87,20 +90,30 @@ uint8_t nr5g_fapi_rx_data_indication( p_fapi_rx_data_ind->header.length = (uint16_t) sizeof(fapi_rx_data_indication_t); - if (nr5g_fapi_rx_data_indication_to_fapi_translation(p_phy_instance, + fapi_vendor_p7_ind_msg_t* p_fapi_vend_p7 = + nr5g_fapi_proc_vendor_p7_msg_get(vendor_extension_elems, phy_id); + fapi_vendor_ext_rx_data_ind_t* p_fapi_vend_rx_data_ind = + p_fapi_vend_p7 ? &p_fapi_vend_p7->rx_data_ind : NULL; + + if (p_fapi_vend_rx_data_ind) { + p_fapi_vend_rx_data_ind->carrier_idx = phy_id; + p_fapi_vend_rx_data_ind->sym = p_phy_rx_ulsch_ind->sSFN_Slot.nSym; + } + + if (nr5g_fapi_rx_data_indication_to_fapi_translation(is_urllc, p_phy_instance, p_phy_rx_ulsch_ind, p_fapi_rx_data_ind)) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI][RX_DATA.indication] L1 to FAPI " "translation failed")); return FAILURE; } - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); p_stats->fapi_stats.fapi_rx_data_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[NR5G_FAPI][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[RX_DATA.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_phy_rx_ulsch_ind->sSFN_Slot.nSFN, - p_phy_rx_ulsch_ind->sSFN_Slot.nSlot)); + p_phy_rx_ulsch_ind->sSFN_Slot.nSFN, p_phy_rx_ulsch_ind->sSFN_Slot.nSlot, + p_phy_rx_ulsch_ind->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -151,13 +164,14 @@ nr5g_fapi_pusch_info_t *nr5g_fapi_get_pusch_info( * **/ uint8_t nr5g_fapi_rx_data_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXULSCHIndicationStruct p_phy_rx_ulsch_ind, fapi_rx_data_indication_t * p_fapi_rx_data_ind) { uint8_t num_ulsch, i; - uint8_t slot_no; - uint16_t frame_no; + uint8_t symbol_no; + uint16_t slot_no, frame_no; nr5g_fapi_pusch_info_t *p_pusch_info; fapi_pdu_ind_info_t *p_fapi_pdu_ind_info; @@ -169,9 +183,10 @@ uint8_t nr5g_fapi_rx_data_indication_to_fapi_translation( frame_no = p_fapi_rx_data_ind->sfn = p_phy_rx_ulsch_ind->sSFN_Slot.nSFN; slot_no = p_fapi_rx_data_ind->slot = p_phy_rx_ulsch_ind->sSFN_Slot.nSlot; + symbol_no = p_phy_rx_ulsch_ind->sSFN_Slot.nSym; p_ul_slot_info = - nr5g_fapi_get_ul_slot_info(frame_no, slot_no, p_phy_instance); + nr5g_fapi_get_ul_slot_info(is_urllc, frame_no, slot_no, symbol_no, p_phy_instance); if (p_ul_slot_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, @@ -191,8 +206,8 @@ uint8_t nr5g_fapi_rx_data_indication_to_fapi_translation( if (p_pusch_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI] [RX_DATA.indication] No Valid data available " - "nUEId:%d, frame_no:%d, slot_no:%d", - p_rx_ulsch_pdu_data->nUEId, frame_no, slot_no)); + "nUEId:%d, frame_no:%d, slot_no:%d, urllc %u", + p_rx_ulsch_pdu_data->nUEId, frame_no, slot_no, is_urllc)); return FAILURE; } @@ -203,7 +218,10 @@ uint8_t nr5g_fapi_rx_data_indication_to_fapi_translation( p_fapi_pdu_ind_info->timingAdvance = p_pusch_info->timing_advance; p_fapi_pdu_ind_info->rssi = 880; p_fapi_pdu_ind_info->pdu_length = p_rx_ulsch_pdu_data->nPduLen; + if (p_fapi_pdu_ind_info->pdu_length > 0) + { p_fapi_pdu_ind_info->pduData = (void *)p_rx_ulsch_pdu_data->pPayload; + } p_stats->fapi_stats.fapi_rx_data_ind_pdus++; } diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_uci_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_uci_ind.c new file mode 100644 index 0000000..11d04ff --- /dev/null +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_rx_data_uci_ind.c @@ -0,0 +1,204 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @file + * This file consist of implementation of FAPI UCI.indication on PUSCH message. + * + **/ + +#include "nr5g_fapi_framework.h" +#include "gnb_l1_l2_api.h" +#include "nr5g_fapi_fapi2mac_api.h" +#include "nr5g_fapi_fapi2mac_p7_proc.h" +#include "nr5g_fapi_fapi2mac_p7_pvt_proc.h" +#include "nr5g_fapi_memory.h" + + /** @ingroup group_source_api_p7_fapi2mac_proc + * + * @param[in] p_phy_ctx Pointer to PHY Context. + * @param[in] p_phy_rx_ulsch_uci_ind Pointer to IAPI RX_ULSCH_UCI.indication message structure. + * + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This message includes UCI payload on PUSCH. + * +**/ +uint8_t nr5g_fapi_rx_data_uci_indication( + bool is_urllc, + p_nr5g_fapi_phy_ctx_t p_phy_ctx, + PRXULSCHUCIIndicationStruct p_phy_rx_ulsch_uci_ind) +{ + uint8_t phy_id; + + fapi_uci_indication_t *p_fapi_uci_ind; + p_fapi_api_queue_elem_t p_list_elem; + p_nr5g_fapi_phy_instance_t p_phy_instance = NULL; + nr5g_fapi_stats_t *p_stats; + + if (NULL == p_phy_ctx) { + NR5G_FAPI_LOG(ERROR_LOG, ("[UCI.indication on PUSCH] Invalid Phy " + "Context")); + return FAILURE; + } + + if (NULL == p_phy_rx_ulsch_uci_ind) { + NR5G_FAPI_LOG(ERROR_LOG, ("[UCI.indication on PUSCH] Invalid Phy " + "RX_ULSCH_UCI indication")); + return FAILURE; + } + + phy_id = p_phy_rx_ulsch_uci_ind->sSFN_Slot.nCarrierIdx; + p_phy_instance = &p_phy_ctx->phy_instance[phy_id]; + if (p_phy_instance->phy_id != phy_id) { + NR5G_FAPI_LOG(ERROR_LOG, ("[UCI.indication on PUSCH] Invalid Phy " + "instance")); + return FAILURE; + } + + p_stats = &p_phy_instance->stats; + p_stats->iapi_stats.iapi_uci_ind++; + + p_list_elem = + nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_UCI_INDICATION, 1, + sizeof(fapi_uci_indication_t)); + if (!p_list_elem) { + NR5G_FAPI_LOG(ERROR_LOG, ("[UCI.indication on PUSCH] Unable to create " + "list element. Out of memory!!!")); + return FAILURE; + } + + p_fapi_uci_ind = (fapi_uci_indication_t *) (p_list_elem + 1); + p_fapi_uci_ind->header.msg_id = FAPI_UCI_INDICATION; + p_fapi_uci_ind->header.length = sizeof(fapi_uci_indication_t); + + if (nr5g_fapi_rx_data_uci_indication_to_fapi_translation(p_phy_instance, + p_phy_rx_ulsch_uci_ind, p_fapi_uci_ind)) { + NR5G_FAPI_LOG(ERROR_LOG, + ("[UCI.indication on PUSCH] FAPI to L1 " "translation failed")); + return FAILURE; + } + + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); + + p_stats->fapi_stats.fapi_uci_ind++; + + NR5G_FAPI_LOG(DEBUG_LOG, ("[UCI.indication on PUSCH][%u][%u,%u,%u] is_urllc %u", + p_phy_instance->phy_id,p_phy_rx_ulsch_uci_ind->sSFN_Slot.nSFN, + p_phy_rx_ulsch_uci_ind->sSFN_Slot.nSlot, + p_phy_rx_ulsch_uci_ind->sSFN_Slot.nSym, is_urllc)); + + return SUCCESS; +} + +/** @ingroup group_source_api_p7_fapi2mac_proc + * + * @param[in] p_phy_instance Pointer to PHY instance. + * @param[in] p_phy_uci_ind Pointer to IAPI RX_ULSCH_UCI.indication structure. + * @param[out] p_fapi_uci_ind Pointer to FAPI UCI.indication structure. + * + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This function converts IAPI RX_ULSCH_UCI.indication to FAPI UCI.indication + * structure. + * +**/ +uint8_t nr5g_fapi_rx_data_uci_indication_to_fapi_translation( + p_nr5g_fapi_phy_instance_t p_phy_instance, + PRXULSCHUCIIndicationStruct p_phy_rx_ulsch_uci_ind, + fapi_uci_indication_t * p_fapi_uci_ind) +{ + uint8_t num_uci, i; + uint8_t nUciDetected, nUciCsiP1Detected, nUciCsiP2Detected; + + PULSCHUCIPDUDataStruct p_phy_uci_pdu_data_struct; + fapi_uci_pdu_info_t *p_fapi_uci_pdu_info; + fapi_uci_o_pusch_t *p_uci_push; + nr5g_fapi_stats_t *p_stats; + + p_stats = &p_phy_instance->stats; + + p_fapi_uci_ind->sfn = p_phy_rx_ulsch_uci_ind->sSFN_Slot.nSFN; + p_fapi_uci_ind->slot = p_phy_rx_ulsch_uci_ind->sSFN_Slot.nSlot; + + num_uci = p_fapi_uci_ind->numUcis = p_phy_rx_ulsch_uci_ind->nUlschUci; + + for (i = 0; i < num_uci; i++) { + p_stats->iapi_stats.iapi_uci_ind_pdus++; + + p_fapi_uci_pdu_info = &p_fapi_uci_ind->uciPdu[i]; + p_phy_uci_pdu_data_struct = + &p_phy_rx_ulsch_uci_ind->sULSCHUCIPDUDataStruct[i]; + + p_fapi_uci_pdu_info->pduType = 0; + p_fapi_uci_pdu_info->pduSize = sizeof(fapi_uci_o_pusch_t); + + p_uci_push = &p_fapi_uci_pdu_info->uci.uciPusch; + memset(p_uci_push, 0, sizeof(fapi_uci_o_pusch_t)); + + p_uci_push->handle = p_phy_uci_pdu_data_struct->nUEId; + p_uci_push->pduBitmap = 0; + p_uci_push->ul_cqi = 0xff; + p_uci_push->rnti = p_phy_uci_pdu_data_struct->nRNTI; + p_uci_push->timingAdvance = 0xffff; + p_uci_push->rssi = 0xffff; + + nUciDetected = p_phy_uci_pdu_data_struct->nUciDetected; + if (nUciDetected) { + p_uci_push->pduBitmap |= 0x02; + p_uci_push->harqInfo.harqCrc = p_phy_uci_pdu_data_struct->nUciCrc; + p_uci_push->harqInfo.harqBitLen = + p_phy_uci_pdu_data_struct->nPduUciAckLen; + NR5G_FAPI_MEMCPY(p_uci_push->harqInfo.harqPayload, + sizeof(uint8_t) * FAPI_MAX_HARQ_INFO_LEN_BYTES, + p_phy_uci_pdu_data_struct->nUciAckBits, + sizeof(uint8_t) * FAPI_MAX_HARQ_INFO_LEN_BYTES); + } + + nUciCsiP1Detected = p_phy_uci_pdu_data_struct->nUciCsiP1Detected; + if (nUciCsiP1Detected) { + p_uci_push->pduBitmap |= 0x04; + p_uci_push->csiPart1info.csiPart1Crc = + p_phy_uci_pdu_data_struct->nUciCsiP1Crc; + p_uci_push->csiPart1info.csiPart1BitLen = + p_phy_uci_pdu_data_struct->nPduUciCsiP1Len; + NR5G_FAPI_MEMCPY(p_uci_push->csiPart1info.csiPart1Payload, + sizeof(uint8_t) * FAPI_MAX_CSI_PART1_DATA_BYTES, + p_phy_uci_pdu_data_struct->nUciCsiP1Bits, + sizeof(uint8_t) * FAPI_MAX_CSI_PART1_DATA_BYTES); + } + + nUciCsiP2Detected = p_phy_uci_pdu_data_struct->nUciCsiP2Detected; + if (nUciCsiP2Detected) { + p_uci_push->pduBitmap |= 0x08; + p_uci_push->csiPart2info.csiPart2Crc = + p_phy_uci_pdu_data_struct->nUciCsiP2Crc; + p_uci_push->csiPart2info.csiPart2BitLen = + p_phy_uci_pdu_data_struct->nPduUciCsiP2Len; + NR5G_FAPI_MEMCPY(p_uci_push->csiPart2info.csiPart2Payload, + sizeof(uint8_t) * FAPI_MAX_CSI_PART2_DATA_BYTES, + p_phy_uci_pdu_data_struct->nUciCsiP2Bits, + sizeof(uint8_t) * FAPI_MAX_CSI_PART2_DATA_BYTES); + } + p_stats->fapi_stats.fapi_uci_ind_pdus++; + } + + return SUCCESS; +} \ No newline at end of file diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_slot_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_slot_ind.c index 61bbdb7..45bf69f 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_slot_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_slot_ind.c @@ -39,7 +39,9 @@ * **/ uint8_t nr5g_fapi_slot_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PSlotIndicationStruct p_iapi_resp) { uint8_t phy_id; @@ -76,6 +78,7 @@ uint8_t nr5g_fapi_slot_indication( p_list_elem = nr5g_fapi_fapi2mac_create_api_list_elem(FAPI_SLOT_INDICATION, 1, sizeof(fapi_slot_ind_t)); + if (!p_list_elem) { NR5G_FAPI_LOG(ERROR_LOG, ("[SLOT.indication] Unable to create " "list element. Out of memory!!!")); @@ -88,13 +91,23 @@ uint8_t nr5g_fapi_slot_indication( p_fapi_slot_ind->sfn = p_iapi_resp->sSFN_Slot.nSFN; p_fapi_slot_ind->slot = p_iapi_resp->sSFN_Slot.nSlot; + fapi_vendor_p7_ind_msg_t* p_fapi_vend_p7 = + nr5g_fapi_proc_vendor_p7_msg_get(vendor_extension_elems, phy_id); + fapi_vendor_ext_slot_ind_t* p_fapi_vend_slot_ind = p_fapi_vend_p7 ? &p_fapi_vend_p7->slot_ind : NULL; + + if (p_fapi_vend_slot_ind) { + p_fapi_vend_slot_ind->carrier_idx = p_iapi_resp->sSFN_Slot.nCarrierIdx; + p_fapi_vend_slot_ind->sym = p_iapi_resp->sSFN_Slot.nSym; + } + /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); p_stats->fapi_stats.fapi_slot_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[SLOT.indication][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[SLOT.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_iapi_resp->sSFN_Slot.nSFN, p_iapi_resp->sSFN_Slot.nSlot)); + p_iapi_resp->sSFN_Slot.nSFN, p_iapi_resp->sSFN_Slot.nSlot, + p_iapi_resp->sSFN_Slot.nSym, is_urllc)); } } return SUCCESS; diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_srs_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_srs_ind.c index 84f963d..b9310ec 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_srs_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_srs_ind.c @@ -27,6 +27,7 @@ #include "nr5g_fapi_fapi2mac_api.h" #include "nr5g_fapi_fapi2mac_p7_proc.h" #include "nr5g_fapi_fapi2mac_p7_pvt_proc.h" +#include "nr5g_fapi_memory.h" /** @ingroup group_source_api_p7_fapi2mac_proc * @@ -40,7 +41,9 @@ * **/ uint8_t nr5g_fapi_srs_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXSRSIndicationStruct p_phy_srs_ind) { uint8_t phy_id; @@ -48,6 +51,8 @@ uint8_t nr5g_fapi_srs_indication( p_fapi_api_queue_elem_t p_list_elem; p_nr5g_fapi_phy_instance_t p_phy_instance = NULL; nr5g_fapi_stats_t *p_stats; + fapi_vendor_p7_ind_msg_t *p_fapi_vend_p7; + fapi_vendor_ext_srs_ind_t *p_fapi_vend_srs_ind; if (NULL == p_phy_ctx) { NR5G_FAPI_LOG(ERROR_LOG, ("[SRS.indication] Invalid " "Phy Context")); @@ -83,20 +88,25 @@ uint8_t nr5g_fapi_srs_indication( p_fapi_srs_ind->header.msg_id = FAPI_SRS_INDICATION; p_fapi_srs_ind->header.length = (uint16_t) sizeof(fapi_srs_indication_t); - if (nr5g_fapi_srs_indication_to_fapi_translation(p_phy_instance, - p_phy_srs_ind, p_fapi_srs_ind)) { + p_fapi_vend_p7 = + nr5g_fapi_proc_vendor_p7_msg_get(vendor_extension_elems, phy_id); + p_fapi_vend_srs_ind = + p_fapi_vend_p7 ? &p_fapi_vend_p7->srs_ind : NULL; + if (nr5g_fapi_srs_indication_to_fapi_translation(is_urllc, p_phy_instance, + p_phy_srs_ind, p_fapi_srs_ind, p_fapi_vend_srs_ind)) { NR5G_FAPI_LOG(ERROR_LOG, ("[SRS.indication] L1 to FAPI " "translation failed")); return FAILURE; } /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); p_stats->fapi_stats.fapi_srs_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[SRS.indication][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[SRS.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_phy_srs_ind->sSFN_Slot.nSFN, p_phy_srs_ind->sSFN_Slot.nSlot)); + p_phy_srs_ind->sSFN_Slot.nSFN, p_phy_srs_ind->sSFN_Slot.nSlot, + p_phy_srs_ind->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -147,15 +157,17 @@ nr5g_fapi_srs_info_t *nr5g_fapi_get_srs_info( * **/ uint8_t nr5g_fapi_srs_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXSRSIndicationStruct p_phy_srs_ind, - fapi_srs_indication_t * p_fapi_srs_ind) + fapi_srs_indication_t * p_fapi_srs_ind, + fapi_vendor_ext_srs_ind_t * p_fapi_vend_srs_ind) { uint8_t num_srs_pdus, i; - uint8_t slot_no, num_rept_symbols, nr_of_symbols; - uint16_t frame_no, num_rbs, j, k; + uint8_t symbol_no, num_rept_symbols, nr_of_symbols; + uint16_t slot_no, frame_no, num_rbs, j, k; int8_t wideband_snr = 0, rb_snr; - int16_t temp = 0; + int16_t temp_sum_wideband_snr; nr5g_fapi_srs_info_t *p_srs_info; fapi_srs_pdu_t *p_fapi_srs_pdu; @@ -163,14 +175,16 @@ uint8_t nr5g_fapi_srs_indication_to_fapi_translation( nr5g_fapi_ul_slot_info_t *p_ul_slot_info; nr5g_fapi_stats_t *p_stats; ULSRSEstStruct *p_ul_srs_est_struct; + fapi_vendor_ext_srs_pdu_t *p_vend_srs_pdu; p_stats = &p_phy_instance->stats; frame_no = p_fapi_srs_ind->sfn = p_phy_srs_ind->sSFN_Slot.nSFN; slot_no = p_fapi_srs_ind->slot = p_phy_srs_ind->sSFN_Slot.nSlot; + symbol_no = p_phy_srs_ind->sSFN_Slot.nSym; p_ul_slot_info = - nr5g_fapi_get_ul_slot_info(frame_no, slot_no, p_phy_instance); + nr5g_fapi_get_ul_slot_info(is_urllc, frame_no, slot_no, symbol_no, p_phy_instance); if (p_ul_slot_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, ("[SRS.indication] No Valid data available " @@ -180,6 +194,7 @@ uint8_t nr5g_fapi_srs_indication_to_fapi_translation( num_srs_pdus = p_fapi_srs_ind->numPdus = p_phy_srs_ind->nNrOfSrs; for (i = 0; i < num_srs_pdus; i++) { + temp_sum_wideband_snr = 0; p_stats->iapi_stats.iapi_srs_ind_pdus++; p_fapi_srs_pdu = &p_fapi_srs_ind->srsPdus[i]; p_ul_srs_est_struct = &p_phy_srs_ind->sULSRSEstStruct[i]; @@ -200,9 +215,9 @@ uint8_t nr5g_fapi_srs_indication_to_fapi_translation( nr_of_symbols = p_fapi_srs_pdu->numSymbols = p_ul_srs_est_struct->nNrOfSymbols; for (j = 0; j < nr_of_symbols; j++) { - temp += p_ul_srs_est_struct->nWideBandSNR[j]; + temp_sum_wideband_snr += p_ul_srs_est_struct->nWideBandSNR[j]; } - wideband_snr = temp / nr_of_symbols; + wideband_snr = temp_sum_wideband_snr / nr_of_symbols; p_fapi_srs_pdu->wideBandSnr = (wideband_snr + 64) * 2; num_rept_symbols = p_fapi_srs_pdu->numReportedSymbols = 1; @@ -218,6 +233,20 @@ uint8_t nr5g_fapi_srs_indication_to_fapi_translation( } } p_stats->fapi_stats.fapi_srs_ind_pdus++; + + if(p_fapi_vend_srs_ind) { // Fill vendor ext + p_fapi_vend_srs_ind->num_pdus = p_phy_srs_ind->nNrOfSrs; + p_vend_srs_pdu = &p_fapi_vend_srs_ind->srs_pdus[i]; + p_vend_srs_pdu->nr_of_port = p_ul_srs_est_struct->nNrOfPort; + p_vend_srs_pdu->nr_of_rx_ant = p_ul_srs_est_struct->nNrOfRxAnt; + p_vend_srs_pdu->nr_of_rbs = p_ul_srs_est_struct->nNrOfRbs; + p_vend_srs_pdu->is_chan_est_pres = + p_ul_srs_est_struct->nIsChanEstPres; + NR5G_FAPI_MEMCPY(p_vend_srs_pdu->p_srs_chan_est, + sizeof(p_vend_srs_pdu->p_srs_chan_est), + p_ul_srs_est_struct->pSrsChanEst, + sizeof(p_ul_srs_est_struct->pSrsChanEst)); + } } return SUCCESS; diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_uci_ind.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_uci_ind.c index a4b59ee..793f9f3 100644 --- a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_uci_ind.c +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_uci_ind.c @@ -27,6 +27,7 @@ #include "nr5g_fapi_fapi2mac_p7_proc.h" #include "nr5g_fapi_fapi2mac_p7_pvt_proc.h" #include "nr5g_fapi_memory.h" +#include "nr5g_fapi_snr_conversion.h" /** @ingroup group_source_api_p7_fapi2mac_proc * @@ -40,7 +41,9 @@ * **/ uint8_t nr5g_fapi_uci_indication( + bool is_urllc, p_nr5g_fapi_phy_ctx_t p_phy_ctx, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, PRXUCIIndicationStruct p_phy_uci_ind) { uint8_t phy_id; @@ -83,19 +86,30 @@ uint8_t nr5g_fapi_uci_indication( p_fapi_uci_ind->header.msg_id = FAPI_UCI_INDICATION; p_fapi_uci_ind->header.length = (uint16_t) sizeof(fapi_uci_indication_t); - if (nr5g_fapi_uci_indication_to_fapi_translation(p_phy_instance, - p_phy_uci_ind, p_fapi_uci_ind)) { + fapi_vendor_p7_ind_msg_t* p_fapi_vend_p7 = + nr5g_fapi_proc_vendor_p7_msg_get(vendor_extension_elems, phy_id); + fapi_vendor_ext_snr_t* p_fapi_snr = p_fapi_vend_p7 ? &p_fapi_vend_p7->uci_snr : NULL; + fapi_vendor_ext_uci_ind_t* p_fapi_vend_uci_ind = p_fapi_vend_p7 ? &p_fapi_vend_p7->uci_ind : NULL; + + if (p_fapi_vend_uci_ind) { + p_fapi_vend_uci_ind->carrier_idx = phy_id; + p_fapi_vend_uci_ind->sym = p_phy_uci_ind->sSFN_Slot.nSym; + } + + if (nr5g_fapi_uci_indication_to_fapi_translation(is_urllc, p_phy_instance, + p_phy_uci_ind, p_fapi_uci_ind, p_fapi_snr)) { NR5G_FAPI_LOG(ERROR_LOG, ("[UCI.indication] FAPI to L1 " "translation failed")); return FAILURE; } /* Add element to send list */ - nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, p_list_elem, is_urllc); p_stats->fapi_stats.fapi_uci_ind++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[UCI.indication][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[UCI.indication][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_phy_uci_ind->sSFN_Slot.nSFN, p_phy_uci_ind->sSFN_Slot.nSlot)); + p_phy_uci_ind->sSFN_Slot.nSFN, p_phy_uci_ind->sSFN_Slot.nSlot, + p_phy_uci_ind->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -145,7 +159,8 @@ nr5g_fapi_pucch_info_t *nr5g_fapi_get_pucch_info( void nr5g_fapi_fill_uci_format_0_1( nr5g_fapi_pucch_info_t * p_pucch_info, ULUCIPDUDataStruct * p_uci_pdu_data_struct, - fapi_uci_pdu_info_t * p_fapi_uci_pdu_info) + fapi_uci_pdu_info_t * p_fapi_uci_pdu_info, + int16_t * p_fapi_snr) { uint8_t pucch_detected, num_harq, i; @@ -161,7 +176,12 @@ void nr5g_fapi_fill_uci_format_0_1( p_uci_pucch_f0_f1->pduBitmap = 0; p_uci_pucch_f0_f1->pucchFormat = p_pucch_info->pucch_format; - p_uci_pucch_f0_f1->ul_cqi = (p_uci_pdu_data_struct->nSNR + 64) * 2; + if(p_fapi_snr) + { + *p_fapi_snr = p_uci_pdu_data_struct->nSNR; + } + + p_uci_pucch_f0_f1->ul_cqi = nr5g_fapi_convert_snr_iapi_to_fapi(p_uci_pdu_data_struct->nSNR); p_uci_pucch_f0_f1->rnti = p_uci_pdu_data_struct->nRNTI; p_uci_pucch_f0_f1->timingAdvance = 31; p_uci_pucch_f0_f1->rssi = 880; @@ -215,7 +235,8 @@ void nr5g_fapi_fill_uci_format_0_1( void nr5g_fapi_fill_uci_format_2_3_4( nr5g_fapi_pucch_info_t * p_pucch_info, ULUCIPDUDataStruct * p_uci_pdu_data_struct, - fapi_uci_pdu_info_t * p_fapi_uci_pdu_info) + fapi_uci_pdu_info_t * p_fapi_uci_pdu_info, + int16_t * p_fapi_snr) { uint8_t pucch_detected; uint16_t num_uci_bits; @@ -227,10 +248,15 @@ void nr5g_fapi_fill_uci_format_2_3_4( p_uci_pucch_f2_f3_f4->handle = p_pucch_info->handle; p_uci_pucch_f2_f3_f4->pduBitmap = 0; p_uci_pucch_f2_f3_f4->pucchFormat = p_pucch_info->pucch_format; - p_uci_pucch_f2_f3_f4->ul_cqi = (p_uci_pdu_data_struct->nSNR + 64) * 2; + p_uci_pucch_f2_f3_f4->ul_cqi = nr5g_fapi_convert_snr_iapi_to_fapi(p_uci_pdu_data_struct->nSNR); p_uci_pucch_f2_f3_f4->rnti = p_uci_pdu_data_struct->nRNTI; p_uci_pucch_f2_f3_f4->timingAdvance = 31; + if(p_fapi_snr) + { + *p_fapi_snr = p_uci_pdu_data_struct->nSNR; + } + pucch_detected = p_uci_pdu_data_struct->pucchDetected; #ifdef DEBUG_MODE p_uci_pucch_f2_f3_f4->timingAdvance = p_uci_pdu_data_struct->nTA; @@ -272,13 +298,15 @@ void nr5g_fapi_fill_uci_format_2_3_4( * **/ uint8_t nr5g_fapi_uci_indication_to_fapi_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, PRXUCIIndicationStruct p_phy_uci_ind, - fapi_uci_indication_t * p_fapi_uci_ind) + fapi_uci_indication_t * p_fapi_uci_ind, + fapi_vendor_ext_snr_t * p_fapi_snr) { uint8_t num_uci, i; - uint8_t slot_no, pucch_format; - uint16_t frame_no; + uint8_t symbol_no, pucch_format; + uint16_t slot_no, frame_no; nr5g_fapi_pucch_info_t *p_pucch_info; fapi_uci_pdu_info_t *p_fapi_uci_pdu_info; @@ -290,9 +318,10 @@ uint8_t nr5g_fapi_uci_indication_to_fapi_translation( frame_no = p_fapi_uci_ind->sfn = p_phy_uci_ind->sSFN_Slot.nSFN; slot_no = p_fapi_uci_ind->slot = p_phy_uci_ind->sSFN_Slot.nSlot; + symbol_no = p_phy_uci_ind->sSFN_Slot.nSym; p_ul_slot_info = - nr5g_fapi_get_ul_slot_info(frame_no, slot_no, p_phy_instance); + nr5g_fapi_get_ul_slot_info(is_urllc, frame_no, slot_no, symbol_no, p_phy_instance); if (p_ul_slot_info == NULL) { NR5G_FAPI_LOG(ERROR_LOG, (" [UCI.indication] No Valid data available " @@ -317,6 +346,7 @@ uint8_t nr5g_fapi_uci_indication_to_fapi_translation( } pucch_format = p_pucch_info->pucch_format; + int16_t* p_fapi_snr_arr = p_fapi_snr ? &p_fapi_snr->nSNR[i] : NULL; switch (pucch_format) { case FAPI_PUCCH_FORMAT_TYPE_0: @@ -326,7 +356,7 @@ uint8_t nr5g_fapi_uci_indication_to_fapi_translation( p_fapi_uci_pdu_info->pduSize = sizeof(fapi_uci_o_pucch_f0f1_t); nr5g_fapi_fill_uci_format_0_1(p_pucch_info, - p_uci_pdu_data_struct, p_fapi_uci_pdu_info); + p_uci_pdu_data_struct, p_fapi_uci_pdu_info, p_fapi_snr_arr); } break; @@ -338,7 +368,7 @@ uint8_t nr5g_fapi_uci_indication_to_fapi_translation( p_fapi_uci_pdu_info->pduSize = sizeof(fapi_uci_o_pucch_f2f3f4_t); nr5g_fapi_fill_uci_format_2_3_4(p_pucch_info, - p_uci_pdu_data_struct, p_fapi_uci_pdu_info); + p_uci_pdu_data_struct, p_fapi_uci_pdu_info, p_fapi_snr_arr); } break; diff --git a/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_vendor_p7_msgs.c b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_vendor_p7_msgs.c new file mode 100644 index 0000000..812e225 --- /dev/null +++ b/fapi_5g/source/api/fapi2mac/p7/nr5g_fapi_proc_vendor_p7_msgs.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#include "nr5g_fapi_framework.h" +#include "gnb_l1_l2_api.h" +#include "nr5g_fapi_fapi2mac_api.h" +#include "nr5g_fapi_fapi2mac_p7_proc.h" + + +static inline p_fapi_api_queue_elem_t alloc_vendor_p7_msg() +{ + p_fapi_api_queue_elem_t p_vend_elem = nr5g_fapi_fapi2mac_create_api_list_elem( + FAPI_VENDOR_EXT_P7_IND, + 1, sizeof(fapi_vendor_p7_ind_msg_t)); + + if (p_vend_elem) + { + fapi_vendor_p7_ind_msg_t* p_vend_p7_ind = (fapi_vendor_p7_ind_msg_t*) (p_vend_elem + 1); + p_vend_p7_ind->header.msg_id = FAPI_VENDOR_EXT_P7_IND; + p_vend_p7_ind->header.length = (uint16_t) sizeof(fapi_vendor_p7_ind_msg_t); + } + else + { + NR5G_FAPI_LOG(ERROR_LOG, ("[VENDOR EXT indication] Unable to create " + "list element. Out of memory!!!")); + } + return p_vend_elem; +} + + +/** @ingroup group_source_api_p7_fapi2mac_proc + * + * @return Returns pointer to fapi_vendor_p7_ind_msg_t + * + * @description + * Used to access fapi_vendor_p7_ind_msg_t for filling. + * Allocates the message if it's not allocated yet. + * +**/ +fapi_vendor_p7_ind_msg_t* nr5g_fapi_proc_vendor_p7_msg_get( + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems, + uint8_t phy_id) +{ + if(phy_id >= FAPI_MAX_PHY_INSTANCES) + { + NR5G_FAPI_LOG(ERROR_LOG, ("[VENDOR EXT indication] Out of bounds" + "phy_id=%u", phy_id)); + return NULL; + } + + p_fapi_api_queue_elem_t p_vend_elem = vendor_extension_elems->vendor_ext[phy_id]; + if(!p_vend_elem) + { + NR5G_FAPI_LOG(DEBUG_LOG, ("[VENDOR EXT indication] No vendor element" + "for phy_id=%u yet. Creating new", phy_id)); + p_vend_elem = alloc_vendor_p7_msg(); + vendor_extension_elems->vendor_ext[phy_id] = p_vend_elem; + } + + return p_vend_elem ? (fapi_vendor_p7_ind_msg_t*) (p_vend_elem + 1) : NULL; +} + +/** @ingroup group_source_api_p7_fapi2mac_proc + * + * @return none + * + * @description + * Adds all cached vendor msgs to api list. + * Function shall be called after all other fapi msgs are added. + * +**/ +void nr5g_fapi_proc_vendor_p7_msgs_move_to_api_list( + bool is_urllc, + p_fapi_api_stored_vendor_queue_elems vendor_extension_elems) +{ + uint8_t phy_id; + for(phy_id=0; phy_idvendor_ext[phy_id]); + nr5g_fapi_fapi2mac_add_api_to_list(phy_id, *p_vend_elem, is_urllc); + *p_vend_elem = NULL; + } +} diff --git a/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.c b/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.c index fb8984b..9a3f1ae 100644 --- a/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.c +++ b/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.c @@ -31,6 +31,7 @@ #include "nr5g_fapi_log.h" nr5g_fapi_fapi2phy_queue_t fapi2phy_q; +nr5g_fapi_fapi2phy_queue_t fapi2phy_q_urllc; //------------------------------------------------------------------------------ /** @ingroup group_source_api_fapi2phy @@ -50,6 +51,12 @@ p_nr5g_fapi_fapi2phy_queue_t nr5g_fapi_fapi2phy_queue( return &fapi2phy_q; } +p_nr5g_fapi_fapi2phy_queue_t nr5g_fapi_fapi2phy_queue_urllc( + ) +{ + return &fapi2phy_q_urllc; +} + uint8_t nr5g_fapi_get_stats_location( uint8_t msg_type) { @@ -152,6 +159,7 @@ PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_create_api_list_elem( **/ //------------------------------------------------------------------------------ void nr5g_fapi_fapi2phy_add_to_api_list( + bool is_urllc, PMAC2PHY_QUEUE_EL p_list_elem) { p_nr5g_fapi_fapi2phy_queue_t queue = NULL; @@ -160,7 +168,9 @@ void nr5g_fapi_fapi2phy_add_to_api_list( return; } - queue = nr5g_fapi_fapi2phy_queue(); + queue = is_urllc ? nr5g_fapi_fapi2phy_queue_urllc() + : nr5g_fapi_fapi2phy_queue(); + if (queue->p_send_list_head && queue->p_send_list_tail) { queue->p_send_list_tail->pNext = p_list_elem; queue->p_send_list_tail = p_list_elem; @@ -181,17 +191,18 @@ void nr5g_fapi_fapi2phy_add_to_api_list( **/ //------------------------------------------------------------------------------ void nr5g_fapi_fapi2phy_send_api_list( - ) + bool is_urllc) { uint8_t ret = FAILURE; p_nr5g_fapi_fapi2phy_queue_t queue = NULL; - queue = nr5g_fapi_fapi2phy_queue(); + queue = is_urllc ? nr5g_fapi_fapi2phy_queue_urllc() + : nr5g_fapi_fapi2phy_queue(); if (queue->p_send_list_head) { NR5G_FAPI_LOG(TRACE_LOG, ("[NR5G_FAPI][FAPI2PHY] Sending API's to PHY")); - ret = nr5g_fapi_fapi2phy_wls_send(queue->p_send_list_head); + ret = nr5g_fapi_fapi2phy_wls_send(queue->p_send_list_head, is_urllc); if (FAILURE == ret) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI][FAPI2PHY] Error sending API's to PHY")); diff --git a/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.h b/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.h index 42ef246..c933be9 100644 --- a/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.h +++ b/fapi_5g/source/api/fapi2phy/nr5g_fapi_fapi2phy_api.h @@ -26,6 +26,7 @@ #define NR5G_FAPI_FAPI2PHY_API_H #include "gnb_l1_l2_api.h" +#include typedef struct _nr5g_fapi_fapi2phy_queue { PMAC2PHY_QUEUE_EL p_send_list_head; // list head to, send to PHY @@ -43,10 +44,11 @@ PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_create_api_list_elem( uint32_t align_offset); void nr5g_fapi_fapi2phy_add_to_api_list( + bool is_urllc, PMAC2PHY_QUEUE_EL p_list_elem); void nr5g_fapi_fapi2phy_send_api_list( - ); + bool is_urllc); void nr5g_fapi_fapi2phy_add_to_free_list( PMAC2PHY_QUEUE_EL p_list_elem); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_proc.h b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_proc.h index c7bbee3..a9bf7b4 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_proc.h +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_proc.h @@ -27,33 +27,38 @@ #define _NR5G_FAPI_FAP2PHY_P5_PROC_H_ uint8_t nr5g_fapi_config_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_config_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_start_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_start_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_stop_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_stop_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_shutdown_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_vendor_ext_shutdown_req_t * p_fapi_req); -uint8_t nr5g_fapi_shutdown_request( - p_nr5g_fapi_phy_instance_t p_phy_instance, - fapi_vendor_ext_shutdown_req_t * p_fapi_msg); - #ifdef DEBUG_MODE uint8_t nr5g_fapi_dl_iq_samples_request( + bool is_urllc, fapi_vendor_ext_iq_samples_req_t * p_fapi_req); uint8_t nr5g_fapi_ul_iq_samples_request( + bool is_urllc, fapi_vendor_ext_iq_samples_req_t * p_fapi_req); +uint8_t nr5g_fapi_add_remove_core_message( + bool is_urllc, + fapi_vendor_ext_add_remove_core_msg_t * p_fapi_req); #endif #endif //_NR5G_FAPI_FAP2PHY_P5_PROC_H_ diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_pvt_proc.h b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_pvt_proc.h index d9c00a5..7f7f4e9 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_pvt_proc.h +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_fapi2phy_p5_pvt_proc.h @@ -34,6 +34,9 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( fapi_config_req_t * p_fapi_req, PCONFIGREQUESTStruct p_ia_config_req); +uint8_t nr5g_fapi_config_req_fill_dependent_fields( + PCONFIGREQUESTStruct p_ia_config_req); + uint8_t nr5g_fapi_calc_phy_tdd_period( uint8_t fapi_tdd_period, uint8_t n_subc_common); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c new file mode 100644 index 0000000..5164423 --- /dev/null +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_add_remove_core_msg.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#include "fapi_vendor_extension.h" +#include "gnb_l1_l2_api.h" +#include "nr5g_fapi_common_types.h" +#include "nr5g_fapi_fapi2phy_api.h" +#include "nr5g_fapi_log.h" + +/** + * @file + * This file consist of implementation of FAPI VENDOR ADD_REMOVE_CORE message. + * + **/ + +/** @ingroup group_source_api_p5_fapi2phy_proc + * + * @param[in] p_fapi_req Pointer to FAPI VENDOR ADD_REMOVE_CORE message structure. + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This is a timer mode specific message used to set options on bbupool cores. + * + */ +#ifdef DEBUG_MODE +uint8_t nr5g_fapi_add_remove_core_message( + bool is_urllc, + fapi_vendor_ext_add_remove_core_msg_t * p_fapi_req) +{ + uint32_t i, k; + PMAC2PHY_QUEUE_EL p_list_elem; + PADD_REMOVE_BBU_CORES p_add_remove_bbu_cores; + + /* Below print is for better logging on console in debug mode. */ + NR5G_FAPI_LOG(INFO_LOG, ("")); + + if (NULL == p_fapi_req) { + NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Invalid fapi message")); + return FAILURE; + } + + p_list_elem = nr5g_fapi_fapi2phy_create_api_list_elem( + (uint8_t)MSG_TYPE_PHY_ADD_REMOVE_CORE, 1, (uint32_t) sizeof(ADD_REMOVE_BBU_CORES)); + + if (!p_list_elem) { + NR5G_FAPI_LOG(ERROR_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE] Unable to create " + "list element. Out of memory!!!")); + return FAILURE; + } + + p_add_remove_bbu_cores = (PADD_REMOVE_BBU_CORES) (p_list_elem + 1); + p_add_remove_bbu_cores->sMsgHdr.nMessageType = MSG_TYPE_PHY_ADD_REMOVE_CORE; + p_add_remove_bbu_cores->sMsgHdr.nMessageLen = sizeof(ADD_REMOVE_BBU_CORES); + + for (i = 0; i < FAPI_MAX_NUM_SET_CORE_MASK; ++i) + { + for (k = 0; k < FAPI_MAX_MASK_OPTIONS; ++k) + { + p_add_remove_bbu_cores->nCoreMask[k][i] = p_fapi_req->add_remove_core_info.nCoreMask[k][i]; + } + } + for (i = 0; i < FAPI_NUM_SPLIT_OPTIONS; ++i) + { + p_add_remove_bbu_cores->nMacOptions[i] = p_fapi_req->add_remove_core_info.nMacOptions[i]; + } + p_add_remove_bbu_cores->eOption = (BBUPOOL_CORE_OPERATION)p_fapi_req->add_remove_core_info.eOption; + + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); + + NR5G_FAPI_LOG(INFO_LOG, ("[FAPI_VENDOR_EXT_ADD_REMOVE_CORE.message]")); + + return SUCCESS; +} +#endif diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c index b21d50b..e6509f7 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_config_req.c @@ -45,6 +45,7 @@ * **/ uint8_t nr5g_fapi_config_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_config_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -110,6 +111,20 @@ uint8_t nr5g_fapi_config_request( p_fapi_vendor_msg->config_req_vendor.sequence_hop_flag; p_ia_config_req->nHoppingId = p_fapi_vendor_msg->config_req_vendor.hopping_id; + p_ia_config_req->nUrllcCapable = + p_fapi_vendor_msg->config_req_vendor.urllc_capable; + p_ia_config_req->nUrllcMiniSlotMask = + p_fapi_vendor_msg->config_req_vendor.urllc_mini_slot_mask; + p_ia_config_req->nPrachNrofRxRU = + p_fapi_vendor_msg->config_req_vendor.prach_nr_of_rx_ru; + p_ia_config_req->nNrOfDLPorts = + p_fapi_vendor_msg->config_req_vendor.nr_of_dl_ports; + p_ia_config_req->nNrOfULPorts = + p_fapi_vendor_msg->config_req_vendor.nr_of_ul_ports; + p_ia_config_req->nSSBSubcSpacing = + p_fapi_vendor_msg->config_req_vendor.ssb_subc_spacing; + p_phy_instance->phy_config.use_vendor_EpreXSSB = + p_fapi_vendor_msg->config_req_vendor.use_vendor_EpreXSSB; } p_ia_config_req->nDLFftSize = @@ -118,10 +133,9 @@ uint8_t nr5g_fapi_config_request( p_ia_config_req->nULFftSize = nr5g_fapi_calc_fft_size(p_ia_config_req->nSubcCommon, p_ia_config_req->nULBandwidth); - p_ia_config_req->nPrachNrofRxRU = p_ia_config_req->nNrOfRxAnt; /* Add element to send list */ - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_config_req++; NR5G_FAPI_LOG(INFO_LOG, ("[CONFIG.request][%d]", p_phy_instance->phy_id)); @@ -171,8 +185,6 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( case FAPI_NUM_TX_ANT_TAG: p_ia_config_req->nNrOfTxAnt = - GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length); - p_ia_config_req->nNrOfDLPorts = GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length); break; @@ -191,8 +203,6 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( case FAPI_NUM_RX_ANT_TAG: p_phy_instance->phy_config.n_nr_of_rx_ant = p_ia_config_req->nNrOfRxAnt = - GETVLFRM32B(tlvs[i].value, tlvs[i].tl.length); - p_ia_config_req->nNrOfULPorts = GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length); break; @@ -226,8 +236,9 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( case FAPI_SCS_COMMON_TAG: p_ia_config_req->nSubcCommon = + p_ia_config_req->nSSBSubcSpacing = + p_phy_instance->phy_config.sub_c_common = GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length); - p_ia_config_req->nSSBSubcSpacing = p_ia_config_req->nSubcCommon; break; /***** PRACH Config *****/ @@ -275,8 +286,6 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( p_ia_config_req->nSSBPrbOffset = GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length) / (pow(2, p_ia_config_req->nSubcCommon)); - p_phy_instance->phy_config.nSSBPrbOffset = - p_ia_config_req->nSSBPrbOffset; break; case FAPI_SSB_PERIOD_TAG: @@ -309,7 +318,7 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( break; case FAPI_BEAM_ID_TAG: - if (n_beamid_idx < 64) { + if (n_beamid_idx < MAX_NUM_ANT) { p_ia_config_req->nBeamId[n_beamid_idx++] = GETVLFRM32B(tlvs[i].value, tlvs[i++].tl.length); } @@ -350,6 +359,28 @@ uint8_t nr5g_fapi_config_req_to_phy_translation( break; } } + nr5g_fapi_config_req_fill_dependent_fields(p_ia_config_req); + return SUCCESS; +} + + /** @ingroup group_source_api_p5_fapi2phy_proc + * + * @param[in,out] p_ia_config_req Pointer to IAPI CONFIG.request structure. + * + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This function converts IAPI Config.request structure fields that depend on + * others. The order ofLV 5G FAPI 222.10.02 - 3.3.2.1 + * +**/ +uint8_t nr5g_fapi_config_req_fill_dependent_fields( + PCONFIGREQUESTStruct p_ia_config_req) +{ + if (0 == p_ia_config_req->nFrameDuplexType) { // FDD + p_ia_config_req->nTddPeriod = 0; + } + return SUCCESS; } diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_dl_iq_samples_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_dl_iq_samples_req.c index 8d747ee..07b722a 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_dl_iq_samples_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_dl_iq_samples_req.c @@ -41,6 +41,7 @@ **/ #ifdef DEBUG_MODE uint8_t nr5g_fapi_dl_iq_samples_request( + bool is_urllc, fapi_vendor_ext_iq_samples_req_t * p_fapi_req) { uint16_t num_ant; @@ -74,6 +75,14 @@ uint8_t nr5g_fapi_dl_iq_samples_request( p_file_info->startFrameNum = p_fapi_req->iq_samples_info.startFrameNum; p_file_info->startSlotNum = p_fapi_req->iq_samples_info.startSlotNum; p_file_info->startSymNum = p_fapi_req->iq_samples_info.startSymNum; + + p_file_info->nDLCompressionIdx = p_fapi_req->iq_samples_info.nDLCompressionIdx; + p_file_info->nDLCompiqWidth = p_fapi_req->iq_samples_info.nDLCompiqWidth; + p_file_info->nDLCompScaleFactor = p_fapi_req->iq_samples_info.nDLCompScaleFactor; + p_file_info->nDLCompreMask = p_fapi_req->iq_samples_info.nDLCompreMask; + p_file_info->nULDecompressionIdx = p_fapi_req->iq_samples_info.nULDecompressionIdx; + p_file_info->nULDecompiqWidth = p_fapi_req->iq_samples_info.nULDecompiqWidth; + if (FAILURE == NR5G_FAPI_MEMCPY(p_file_info->buffer, sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE, p_fapi_req->iq_samples_info.buffer, sizeof(CONFIGREQUESTStruct))) { @@ -89,6 +98,14 @@ uint8_t nr5g_fapi_dl_iq_samples_request( "failed!!!")); } + if (FAILURE == NR5G_FAPI_STRCPY(p_file_info->filename_out_dl_iq_compressed, + sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE, + p_fapi_req->iq_samples_info.filename_out_dl_iq_compressed, + sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE)) { + NR5G_FAPI_LOG(ERROR_LOG, ("[DL_IQ_Samples.request] compressed file name copy " + "failed!!!")); + } + for (num_ant = 0; num_ant < FAPI_MAX_IQ_SAMPLE_DL_PORTS; num_ant++) { if (FAILURE == NR5G_FAPI_STRCPY(p_file_info->filename_out_dl_beam[num_ant], @@ -113,7 +130,7 @@ uint8_t nr5g_fapi_dl_iq_samples_request( } } - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); NR5G_FAPI_LOG(INFO_LOG, ("[DL_IQ_Samples.request][%d]", p_fapi_req->iq_samples_info.carrNum)); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_shutdown_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_shutdown_req.c index 376f6f9..b0ada6c 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_shutdown_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_shutdown_req.c @@ -41,6 +41,7 @@ * **/ uint8_t nr5g_fapi_shutdown_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_vendor_ext_shutdown_req_t * p_fapi_req) { @@ -80,7 +81,7 @@ uint8_t nr5g_fapi_shutdown_request( p_fapi_req->test_type; /* Add element to send list */ - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_shutdown_req++; NR5G_FAPI_LOG(INFO_LOG, ("[SHUTDOWN.request][%d]", p_phy_instance->phy_id)); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c index 1a2e610..3a81acc 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_start_req.c @@ -54,6 +54,7 @@ * **/ uint8_t nr5g_fapi_start_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_start_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -118,7 +119,7 @@ uint8_t nr5g_fapi_start_request( #endif /* Add element to send list */ - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_start_req++; NR5G_FAPI_LOG(INFO_LOG, ("[START.request][%d]", p_phy_instance->phy_id)); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c index 30350bc..3852da3 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_stop_req.c @@ -46,6 +46,7 @@ * **/ uint8_t nr5g_fapi_stop_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_stop_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -88,7 +89,7 @@ uint8_t nr5g_fapi_stop_request( p_stop_req->sSFN_Slot.nCarrierIdx = p_phy_instance->phy_id; /* Add element to send list */ - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_stop_req++; NR5G_FAPI_LOG(INFO_LOG, ("[STOP.request][%d]", p_phy_instance->phy_id)); diff --git a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_ul_iq_samples_req.c b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_ul_iq_samples_req.c index b8e21ed..902ab90 100644 --- a/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_ul_iq_samples_req.c +++ b/fapi_5g/source/api/fapi2phy/p5/nr5g_fapi_proc_ul_iq_samples_req.c @@ -44,6 +44,7 @@ **/ #ifdef DEBUG_MODE uint8_t nr5g_fapi_ul_iq_samples_request( + bool is_urllc, fapi_vendor_ext_iq_samples_req_t * p_fapi_req) { uint16_t num_ant; @@ -51,9 +52,6 @@ uint8_t nr5g_fapi_ul_iq_samples_request( fapi_vendor_ext_iq_samples_info_t *p_file_info; PMAC2PHY_QUEUE_EL p_list_elem; - /* Below print is for better logging on console in debug mode. */ - NR5G_FAPI_LOG(INFO_LOG, ("")); - if (NULL == p_fapi_req) { NR5G_FAPI_LOG(ERROR_LOG, (" [UL_IQ_SAMPLES.request] Invalid fapi " "message")); @@ -80,6 +78,14 @@ uint8_t nr5g_fapi_ul_iq_samples_request( p_file_info->startFrameNum = p_fapi_req->iq_samples_info.startFrameNum; p_file_info->startSlotNum = p_fapi_req->iq_samples_info.startSlotNum; p_file_info->startSymNum = p_fapi_req->iq_samples_info.startSymNum; + + p_file_info->nDLCompressionIdx = p_fapi_req->iq_samples_info.nDLCompressionIdx; + p_file_info->nDLCompiqWidth = p_fapi_req->iq_samples_info.nDLCompiqWidth; + p_file_info->nDLCompScaleFactor = p_fapi_req->iq_samples_info.nDLCompScaleFactor; + p_file_info->nDLCompreMask = p_fapi_req->iq_samples_info.nDLCompreMask; + p_file_info->nULDecompressionIdx = p_fapi_req->iq_samples_info.nULDecompressionIdx; + p_file_info->nULDecompiqWidth = p_fapi_req->iq_samples_info.nULDecompiqWidth; + if (FAILURE == NR5G_FAPI_MEMCPY(p_file_info->buffer, sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_BUFFER_SIZE, p_fapi_req->iq_samples_info.buffer, sizeof(CONFIGREQUESTStruct))) { @@ -104,6 +110,15 @@ uint8_t nr5g_fapi_ul_iq_samples_request( NR5G_FAPI_LOG(ERROR_LOG, ("[UL_IQ_Samples.request] PRACH file name " "copy failed!!!")); } + + if (FAILURE == + NR5G_FAPI_STRCPY(p_file_info->filename_in_ul_iq_compressed[num_ant], + sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE, + p_fapi_req->iq_samples_info.filename_in_ul_iq_compressed[num_ant], + sizeof(uint8_t) * FAPI_MAX_IQ_SAMPLE_FILE_SIZE)) { + NR5G_FAPI_LOG(ERROR_LOG, + ("[UL_IQ_Samples.request] compressed file name copy failed!!!")); + } } for (num_ant = 0; num_ant < FAPI_MAX_IQ_SAMPLE_UL_ANTENNA; num_ant++) { @@ -117,7 +132,7 @@ uint8_t nr5g_fapi_ul_iq_samples_request( } } - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); NR5G_FAPI_LOG(INFO_LOG, ("[UL_IQ_SAMPLES.request][%d]", p_fapi_req->iq_samples_info.carrNum)); diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_proc.h b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_proc.h index 1d75608..a4568c8 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_proc.h +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_proc.h @@ -27,21 +27,25 @@ #define _NR5G_FAPI_FAP2PHY_P7_PROC_H_ uint8_t nr5g_fapi_dl_tti_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_dl_tti_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_ul_tti_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_tti_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_ul_dci_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_dci_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); uint8_t nr5g_fapi_tx_data_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_tx_data_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg); diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_pvt_proc.h b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_pvt_proc.h index 8706ff0..4f6b565 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_pvt_proc.h +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_fapi2phy_p7_pvt_proc.h @@ -29,12 +29,13 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_dl_tti_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PDLConfigRequestStruct p_ia_dl_config_req); -void nr5g_fapi_fill_dci_pdu( +void nr5g_fapi_dl_tti_req_to_phy_translation_vendor_ext( p_nr5g_fapi_phy_instance_t p_phy_instance, - fapi_dl_pdcch_pdu_t * p_pdcch_pdu, - PDCIPDUStruct p_dci_pdu); + fapi_vendor_msg_t * p_fapi_vendor_msg, + PDLConfigRequestStruct p_ia_dl_config_req); void nr5g_fapi_fill_dci_pdu( p_nr5g_fapi_phy_instance_t p_phy_instance, @@ -49,6 +50,12 @@ void nr5g_fapi_fill_pdsch_pdu( uint16_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB( uint8_t beta_pdcch_1_0); +uint16_t nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB( + uint8_t power_control_offset_ss); + +uint16_t nr5g_fapi_calculate_nEpreRatioOfPDSCHToSSB( + uint8_t power_control_offset); + void nr5g_fapi_fill_ssb_pdu( p_nr5g_fapi_phy_instance_t p_phy_instance, PBCHPDUStruct p_bch_pdu, @@ -56,8 +63,8 @@ void nr5g_fapi_fill_ssb_pdu( void nr5g_fapi_fill_csi_rs_pdu( p_nr5g_fapi_phy_instance_t p_phy_instance, - PCSIRSPDUStruct pCSIRSPdu, - fapi_dl_csi_rs_pdu_t * p_csi_rs_pdu); + fapi_dl_csi_rs_pdu_t * p_csi_rs_pdu, + PCSIRSPDUStruct pCSIRSPdu); // UL_TTI.req uint8_t nr5g_fapi_calc_n_rbg_size( @@ -67,15 +74,6 @@ uint32_t nr5g_fapi_calc_n_rbg_index_entry( uint8_t n_rbg_size, fapi_ul_pusch_pdu_t * p_pusch_pdu); -uint8_t nr5g_fapi_calc_alpha_scaling( - uint8_t fapi_alpha_scaling); - -void nr5g_fapi_pusch_to_phy_ulsch_translation( - p_nr5g_fapi_phy_instance_t p_phy_instance, - nr5g_fapi_pusch_info_t * pusch_info, - fapi_ul_pusch_pdu_t * p_pusch_pdu, - ULSCHPDUStruct * p_ul_data_chan); - void nr5g_fapi_pusch_data_to_phy_ulsch_translation( nr5g_fapi_pusch_info_t * p_pusch_info, fapi_pusch_data_t * p_pusch_data, @@ -107,8 +105,6 @@ void nr5g_fapi_pucch_to_phy_ulcch_uci_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, nr5g_fapi_pucch_info_t * p_pucch_info, fapi_ul_pucch_pdu_t * p_pucch_pdu, - uint8_t * num_groups, - nr5g_fapi_pucch_resources_t * p_pucch_resources, ULCCHUCIPDUStruct * p_ul_ctrl_chan); void nr5g_fapi_srs_to_phy_srs_translation( @@ -118,17 +114,40 @@ void nr5g_fapi_srs_to_phy_srs_translation( SRSPDUStruct * p_ul_srs_chan); uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_tti_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PULConfigRequestStruct p_ia_ul_config_req); +void nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext( + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULConfigRequestStruct p_ia_ul_config_req); + +uint8_t nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext_symbol_no( + bool is_urllc, + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULConfigRequestStruct p_ia_ul_config_req, + uint8_t* symbol_no); + uint8_t nr5g_fapi_ul_dci_req_to_phy_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_dci_req_t * p_fapi_req, PULDCIRequestStruct p_ia_ul_dci_req); +void nr5g_fapi_ul_dci_req_to_phy_translation_vendor_ext( + p_nr5g_fapi_phy_instance_t p_phy_instance, + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULDCIRequestStruct p_ia_ul_dci_req); + uint8_t nr5g_fapi_tx_data_req_to_phy_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_tx_data_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PTXRequestStruct p_ia_tx_req); + +void nr5g_fapi_tx_data_req_to_phy_translation_vendor_ext( + fapi_vendor_msg_t * p_fapi_vendor_msg, + PTXRequestStruct p_phy_req); + #endif //_NR5G_FAPI_FAP2PHY_P7_PVT_PROC_H_ diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_dl_tti_req.c b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_dl_tti_req.c index eb4d1cb..3898686 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_dl_tti_req.c +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_dl_tti_req.c @@ -43,6 +43,7 @@ * **/ uint8_t nr5g_fapi_dl_tti_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_dl_tti_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -50,12 +51,12 @@ uint8_t nr5g_fapi_dl_tti_request( PDLConfigRequestStruct p_ia_dl_config_req; PMAC2PHY_QUEUE_EL p_list_elem; nr5g_fapi_stats_t *p_stats; - UNUSED(p_fapi_vendor_msg); if (NULL == p_phy_instance) { NR5G_FAPI_LOG(ERROR_LOG, ("[DL_TTI.request] Invalid " "Phy Instance")); return FAILURE; } + p_stats = &p_phy_instance->stats; p_stats->fapi_stats.fapi_dl_tti_req++; @@ -75,7 +76,7 @@ uint8_t nr5g_fapi_dl_tti_request( p_ia_dl_config_req = (PDLConfigRequestStruct) (p_list_elem + 1); if (FAILURE == nr5g_fapi_dl_tti_req_to_phy_translation(p_phy_instance, - p_fapi_req, p_ia_dl_config_req)) { + p_fapi_req, p_fapi_vendor_msg, p_ia_dl_config_req)) { nr5g_fapi_fapi2phy_destroy_api_list_elem(p_list_elem); NR5G_FAPI_LOG(DEBUG_LOG, ("[DL_TTI.request][%d][%d,%d] Not Sent", p_phy_instance->phy_id, p_ia_dl_config_req->sSFN_Slot.nSFN, @@ -83,17 +84,18 @@ uint8_t nr5g_fapi_dl_tti_request( return FAILURE; } /* Add element to send list */ - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_dl_config_req++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[DL_TTI.request][%d][%d,%d]", - p_phy_instance->phy_id, p_ia_dl_config_req->sSFN_Slot.nSFN, - p_ia_dl_config_req->sSFN_Slot.nSlot)); + NR5G_FAPI_LOG(DEBUG_LOG, ("[DL_TTI.request][%u][%u,%u,%u] is_urllc %u", + p_phy_instance->phy_id, + p_ia_dl_config_req->sSFN_Slot.nSFN, p_ia_dl_config_req->sSFN_Slot.nSlot, + p_ia_dl_config_req->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } - /** @ingroup group_source_api_p5_fapi2phy_proc + /** @ingroup group_source_api_p7_fapi2phy_proc * * @param[in] p_fapi_req Pointer to FAPI DL_TTI.request structure. * @param[out] p_ia_dl_config_req Pointer to IAPI DL_TTI.request structure. @@ -108,6 +110,7 @@ uint8_t nr5g_fapi_dl_tti_request( uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_dl_tti_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PDLConfigRequestStruct p_phy_req) { int idx = 0, nDCI = 0, jdx = 0; @@ -143,10 +146,6 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( p_phy_req->sSFN_Slot.nSFN = p_fapi_req->sfn; p_phy_req->sSFN_Slot.nSlot = p_fapi_req->slot; - // setting to defaults - p_phy_req->nLte_CRS_carrierBandwidthDL = 100; - p_phy_req->nLte_CRS_nrofCRS_Ports = 2; - for (idx = 0; idx < p_phy_req->nGroup; ++idx) { p_ueGrpInfo = &p_fapi_req->ue_grp_info[idx]; pPDSCHGroupInfoStruct = &p_phy_req->sPDSCHGroupInfoStruct[idx]; @@ -184,8 +183,7 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( p_dlsch_pdu->sPDUHdr.nPDUType = DL_PDU_TYPE_DLSCH; p_dlsch_pdu->sPDUHdr.nPDUSize = pdsch_size; total_size += pdsch_size; - nr5g_fapi_fill_pdsch_pdu(p_phy_instance, p_pdsch_pdu, - p_dlsch_pdu); + nr5g_fapi_fill_pdsch_pdu(p_phy_instance, p_pdsch_pdu, p_dlsch_pdu); break; case FAPI_PBCH_PDU_TYPE: @@ -207,8 +205,7 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( pCSIRSPdu->sPDUHdr.nPDUType = DL_PDU_TYPE_CSIRS; pCSIRSPdu->sPDUHdr.nPDUSize = csirs_size; total_size += csirs_size; - nr5g_fapi_fill_csi_rs_pdu(p_phy_instance, pCSIRSPdu, - p_csi_rs_pdu); + nr5g_fapi_fill_csi_rs_pdu(p_phy_instance, p_csi_rs_pdu, pCSIRSPdu); break; default: @@ -223,9 +220,118 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( p_phy_req->nDCI = nDCI; p_phy_req->sMsgHdr.nMessageLen = total_size; + + if (NULL != p_fapi_vendor_msg) + { + nr5g_fapi_dl_tti_req_to_phy_translation_vendor_ext(p_phy_instance, + p_fapi_vendor_msg, + p_phy_req); + } + return SUCCESS; } + /** @ingroup group_source_api_p5_fapi2phy_proc + * + * @param[in] p_fapi_vendor_msg Pointer to FAPI DL_TTI.request vendor message. + * @param[out] p_ia_dl_config_req Pointer to IAPI DL_TTI.request structure. + * + * @return no return. + * + * @description + * This function fills fields for DL_TTI.request structure that come from + * a vendor extension. + * +**/ +void nr5g_fapi_dl_tti_req_to_phy_translation_vendor_ext( + p_nr5g_fapi_phy_instance_t p_phy_instance, + fapi_vendor_msg_t * p_fapi_vendor_msg, + PDLConfigRequestStruct p_phy_req) +{ + int idx = 0; + + fapi_vendor_dl_tti_req_t *p_vendor_dl_tti_req = NULL; + fapi_vendor_dl_pdcch_pdu_t *p_vendor_pdcch_pdu = NULL; + fapi_vendor_dl_pdsch_pdu_t *p_vendor_pdsch_pdu = NULL; + fapi_vendor_csi_rs_pdu_t *p_vendor_csi_rs_pdu = NULL; + + PPDUStruct pPduStruct = NULL; + PDCIPDUStruct p_dci_pdu = NULL; + PDLSCHPDUStruct p_dlsch_pdu = NULL; + PCSIRSPDUStruct p_CSIRS_pdu = NULL; + + p_vendor_dl_tti_req = &p_fapi_vendor_msg->p7_req_vendor.dl_tti_req; + + p_phy_req->sSFN_Slot.nSym = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.sym; + + p_phy_req->nLte_CRS_Present = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.lte_crs_present; + p_phy_req->nLte_CRS_carrierFreqDL = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.lte_crs_carrier_freq_dl; + p_phy_req->nLte_CRS_carrierBandwidthDL = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.lte_crs_carrier_bandwidth_dl; + p_phy_req->nLte_CRS_nrofCRS_Ports = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.lte_crs_nr_of_crs_ports; + p_phy_req->nLte_CRS_v_shift = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.lte_crs_v_shift; + p_phy_req->nPdcchPrecoderEn = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.pdcch_precoder_en; + p_phy_req->nSSBPrecoderEn = p_fapi_vendor_msg->p7_req_vendor.dl_tti_req.ssb_precoder_en; + + pPduStruct = p_phy_req->sDLPDU; + for (idx = 0; idx < p_phy_req->nPDU; ++idx) { + switch (pPduStruct->nPDUType) { + case DL_PDU_TYPE_DCI: + p_dci_pdu = (PDCIPDUStruct) pPduStruct; + p_vendor_pdcch_pdu = + &p_vendor_dl_tti_req->pdus[idx].pdu.pdcch_pdu; + + if (USE_VENDOR_EPREXSSB == p_phy_instance->phy_config.use_vendor_EpreXSSB) + { + p_dci_pdu->nEpreRatioOfPDCCHToSSB = + p_vendor_pdcch_pdu->dl_dci[0].epre_ratio_of_pdcch_to_ssb; + p_dci_pdu->nEpreRatioOfDmrsToSSB = + p_vendor_pdcch_pdu->dl_dci[0].epre_ratio_of_dmrs_to_ssb; + } + break; + + case DL_PDU_TYPE_DLSCH: + p_dlsch_pdu = (PDLSCHPDUStruct) pPduStruct; + p_vendor_pdsch_pdu = + &p_vendor_dl_tti_req->pdus[idx].pdu.pdsch_pdu; + + p_dlsch_pdu->nNrOfAntennaPorts = p_vendor_pdsch_pdu->nr_of_antenna_ports; + + if (USE_VENDOR_EPREXSSB == p_phy_instance->phy_config.use_vendor_EpreXSSB) + { + p_dlsch_pdu->nEpreRatioOfDmrsToSSB = + p_vendor_pdsch_pdu->epre_ratio_of_dmrs_to_ssb; + p_dlsch_pdu->nEpreRatioOfPDSCHToSSB = + p_vendor_pdsch_pdu->epre_ratio_of_pdsch_to_ssb; + } + + NR5G_FAPI_MEMCPY(p_dlsch_pdu->nTxRUIdx, sizeof(p_dlsch_pdu->nTxRUIdx), + p_vendor_pdsch_pdu->tx_ru_idx, sizeof(p_vendor_pdsch_pdu->tx_ru_idx)); + break; + + case DL_PDU_TYPE_PBCH: + // No vendor ext + break; + + case DL_PDU_TYPE_CSIRS: + p_CSIRS_pdu = (PCSIRSPDUStruct) pPduStruct; + p_vendor_csi_rs_pdu = &p_vendor_dl_tti_req->pdus[idx].pdu.csi_rs_pdu; + + if (USE_VENDOR_EPREXSSB == p_phy_instance->phy_config.use_vendor_EpreXSSB) + { + p_CSIRS_pdu->nEpreRatioToSSB = p_vendor_csi_rs_pdu->epre_ratio_to_ssb; + } + break; + + default: + NR5G_FAPI_LOG(ERROR_LOG, ("[DL_TTI] Invalid Pdu Type: %d", + pPduStruct->nPDUType)); + return; + } + pPduStruct = + (PDUStruct *) ((uint8_t *) pPduStruct + pPduStruct->nPDUSize); + } +} + /** @ingroup group_nr5g_test_config * * @param[in] p_pdcch_pdu @@ -234,7 +340,7 @@ uint8_t nr5g_fapi_dl_tti_req_to_phy_translation( * @return void * * @description - * This function fills FAPI PDCCH Pdu from IAPI DCIPdu + * This function fills IAPI DCIPdu from FAPI PDCCH Pdu * **/ void nr5g_fapi_fill_dci_pdu( @@ -273,11 +379,15 @@ void nr5g_fapi_fill_dci_pdu( p_dci_pdu->nRNTI = p_pdcch_pdu->dlDci[0].rnti; p_dci_pdu->nTotalBits = p_pdcch_pdu->dlDci[0].payloadSizeBits; + if (USE_VENDOR_EPREXSSB != p_phy_instance->phy_config.use_vendor_EpreXSSB) { p_dci_pdu->nEpreRatioOfPDCCHToSSB = nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(p_pdcch_pdu-> dlDci[0].beta_pdcch_1_0); p_dci_pdu->nEpreRatioOfDmrsToSSB = - p_pdcch_pdu->dlDci[0].powerControlOffsetSS; + nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB(p_pdcch_pdu-> + dlDci[0].powerControlOffsetSS); + } + if (FAILURE == NR5G_FAPI_MEMCPY(p_dci_pdu->nDciBits, sizeof(uint8_t) * MAX_DCI_BIT_BYTE_LEN, p_pdcch_pdu->dlDci[0].payload, @@ -330,7 +440,7 @@ void nr5g_fapi_fill_pdsch_pdu( } //p_dlsch_pdu->nNrOfAntennaPorts = p_phy_instance->phy_config.n_nr_of_rx_ant; p_dlsch_pdu->nNrOfLayers = p_pdsch_pdu->nrOfLayers; - p_dlsch_pdu->nNrOfAntennaPorts = p_pdsch_pdu->nrOfLayers; + p_dlsch_pdu->nNrOfAntennaPorts = p_dlsch_pdu->nNrOfLayers; p_dlsch_pdu->nTransmissionScheme = p_pdsch_pdu->transmissionScheme; p_dlsch_pdu->nDMRSConfigType = p_pdsch_pdu->dmrsConfigType; p_dlsch_pdu->nNIDnSCID = p_pdsch_pdu->dlDmrsScramblingId; @@ -355,6 +465,9 @@ void nr5g_fapi_fill_pdsch_pdu( p_dlsch_pdu->nResourceAllocType = p_pdsch_pdu->resourceAlloc; p_dlsch_pdu->nRBStart = p_pdsch_pdu->rbStart; p_dlsch_pdu->nRBSize = p_pdsch_pdu->rbSize; + p_dlsch_pdu->nPMI = (p_pdsch_pdu->preCodingAndBeamforming.numPrgs > 0) + ? p_pdsch_pdu->preCodingAndBeamforming.pmi_bfi[0].pmIdx + : 0; p_dlsch_pdu->nVRBtoPRB = p_pdsch_pdu->vrbToPrbMapping; p_dlsch_pdu->nStartSymbolIndex = p_pdsch_pdu->startSymbIndex; p_dlsch_pdu->nNrOfSymbols = p_pdsch_pdu->nrOfSymbols; @@ -368,8 +481,16 @@ void nr5g_fapi_fill_pdsch_pdu( p_dlsch_pdu->nPTRSFreqDensity = p_pdsch_pdu->ptrsFreqDensity; p_dlsch_pdu->nPTRSReOffset = p_pdsch_pdu->ptrsReOffset; p_dlsch_pdu->nEpreRatioOfPDSCHToPTRS = p_pdsch_pdu->nEpreRatioOfPdschToPtrs; - // Currently no mapping info available. - //p_dlsch_pdu->nEpreRatioOfPDSCHToSSB = 0x1170; + + if (USE_VENDOR_EPREXSSB != p_phy_instance->phy_config.use_vendor_EpreXSSB) { + p_dlsch_pdu->nEpreRatioOfDmrsToSSB = + nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB( + p_pdsch_pdu->powerControlOffsetSS); + p_dlsch_pdu->nEpreRatioOfPDSCHToSSB = + nr5g_fapi_calculate_nEpreRatioOfPDSCHToSSB( + p_pdsch_pdu->powerControlOffset); + } + // PTRS Information p_dlsch_pdu->nPTRSPresent = p_pdsch_pdu->pduBitMap & 0x0001; p_dlsch_pdu->nNrOfPTRSPorts = @@ -384,21 +505,19 @@ void nr5g_fapi_fill_pdsch_pdu( p_dlsch_pdu->nNrOfDMRSAssPTRS[1] = 0x1; p_dlsch_pdu->n1n2 = 0x201; - for (idx = 0; (idx < MAX_TXRU_NUM && idx < port_index); idx++) { - p_dlsch_pdu->nTxRUIdx[idx] = p_dlsch_pdu->nPortIndex[idx]; - } p_dlsch_pdu->nNrofTxRU = port_index; + p_stats->iapi_stats.iapi_dl_tti_pdsch_pdus++; } /** @ingroup group_nr5g_test_config * - * @param[in] nEpreRatioOfPDCCHToSSB + * @param[in] beta_pdcch_1_0 * - * @return uint8_t mapping + * @return uint16_t mapping * * @description - * This function maps IAPI to FAPI value range. + * This function maps FAPI to IAPI value range. * * * Please refer 5G FAPI-IAPI Translator Module SW Design Document for details on @@ -440,6 +559,133 @@ uint16_t nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB( } } +/** @ingroup group_nr5g_test_config + * + * @param[in] power_control_offset_ss + * + * @return uint16_t mapping + * + * @description + * This function maps FAPI to IAPI value range. + * + * + * nEpreRatioOfDmrsToSSB: 1->20000, 0.001dB step, -6dB to 14dB + * powerControlOffsetSS: 0->3, 3dB step, -3dB to 6dB + * |----------------------------------------------| + * | nEpreRatioOfDmrsToSSB | powerControlOffsetSS | + * |----------------------------------------------| + * | 3000 | 0 | + * | 6000 | 1 | + * | 9000 | 2 | + * | 12000 | 3 | + * |----------------------------------------------| + * +**/ +uint16_t nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB( + uint8_t power_control_offset_ss) +{ + switch(power_control_offset_ss) + { + case 0: + return 3000; + case 1: + return 6000; + case 2: + return 9000; + case 3: + return 12000; + default: + NR5G_FAPI_LOG(ERROR_LOG, + ("Unsupported value of power_control_offset_ss.")); + return 0; + } +} + + +/** @ingroup group_nr5g_test_config + * + * @param[in] power_control_offset + * + * @return uint16_t mapping + * + * @description + * This function maps FAPI to IAPI value range. + * + * + * nEpreRatioOfPDSCHToSSB: 1->20000, 0.001dB step, -6dB to 14dB + * powerControlOffset: 0->23, 1dB step, -8dB to 15dB + * |----------------------------------------------| + * | nEpreRatioOfPDSCHToSSB | powerControlOffset | + * |----------------------------------------------| + * | 1 | 0-2 | + * | 1000 | 3 | + * | 2000 | 4 | + * | 3000 | 5 | + * | 4000 | 6 | + * | 5000 | 7 | + * | 6000 | 8 | + * | 7000 | 9 | + * | 8000 | 10 | + * | 9000 | 11 | + * | 10000 | 12 | + * | 11000 | 13 | + * | 12000 | 14 | + * | 13000 | 15 | + * | 14000 | 16 | + * | 15000 | 17 | + * | 16000 | 18 | + * | 17000 | 19 | + * | 18000 | 20 | + * | 19000 | 21 | + * | 20000 | 22-23 | + * |----------------------------------------------| + * +**/ +uint16_t nr5g_fapi_calculate_nEpreRatioOfPDSCHToSSB(uint8_t power_control_offset) +{ + static const uint8_t MAPPING_SIZE = 24; + static const uint16_t power_control_offset_to_epre_ratio[MAPPING_SIZE] = { + // 0 1 2 3 4 5 6 7 + 1, 1, 1, 1000, 2000, 3000, 4000, 5000, + // 8 9 10 11 12 13 14 15 + 6000, 7000, 8000, 9000, 10000, 11000, 12000, 13000, + // 16 17 18 19 20 21 22 23 + 14000, 15000, 16000, 17000, 18000, 19000, 20000, 20000 + }; + + if(MAPPING_SIZE > power_control_offset) + { + return power_control_offset_to_epre_ratio[power_control_offset]; + } + else + { + NR5G_FAPI_LOG(ERROR_LOG, + ("Unsupported value of power_control_offset=%u.", + power_control_offset)); + return 0; + } +} + +/** @ingroup group_nr5g_test_config + * + * @param[in] ssb_offset_point_a + * @param[in] sub_c_common + * + * @return uint8_t nSSBPrbOffset + * + * @description + * This function maps FAPI to IAPI value range. + * + * Please refer 5G FAPI-IAPI Translator Module SW Design Document for details on + * the mapping. + * +**/ +uint8_t nr5g_fapi_calculate_nSSBPrbOffset( + uint16_t ssb_offset_point_a, uint8_t sub_c_common) +{ + return ssb_offset_point_a/pow(2, sub_c_common); +} + /** @ingroup group_nr5g_test_config * * @param[in] p_dlsch_pdu @@ -466,7 +712,9 @@ void nr5g_fapi_fill_ssb_pdu( p_stats = &p_phy_instance->stats; p_stats->fapi_stats.fapi_dl_tti_ssb_pdus++; p_bch_pdu->nSSBSubcOffset = p_ssb_pdu->ssbSubCarrierOffset; - p_bch_pdu->nSSBPrbOffset = p_phy_instance->phy_config.nSSBPrbOffset; + p_bch_pdu->nSSBPrbOffset = + nr5g_fapi_calculate_nSSBPrbOffset(p_ssb_pdu->ssbOffsetPointA, + p_phy_instance->phy_config.sub_c_common); p_stats->iapi_stats.iapi_dl_tti_ssb_pdus++; } @@ -483,30 +731,34 @@ void nr5g_fapi_fill_ssb_pdu( **/ void nr5g_fapi_fill_csi_rs_pdu( p_nr5g_fapi_phy_instance_t p_phy_instance, - PCSIRSPDUStruct pCSIRSPdu, - fapi_dl_csi_rs_pdu_t * p_csi_rs_pdu) + fapi_dl_csi_rs_pdu_t * p_csi_rs_pdu, + PCSIRSPDUStruct p_CSIRS_pdu) { nr5g_fapi_stats_t *p_stats; p_stats = &p_phy_instance->stats; p_stats->fapi_stats.fapi_dl_tti_csi_rs_pdus++; - pCSIRSPdu->nBWPSize = p_csi_rs_pdu->bwpSize; - pCSIRSPdu->nBWPStart = p_csi_rs_pdu->bwpStart; - pCSIRSPdu->nCDMType = p_csi_rs_pdu->cdmType; - pCSIRSPdu->nCSIType = p_csi_rs_pdu->csiType; - pCSIRSPdu->nCpType = p_csi_rs_pdu->cyclicPrefix; - pCSIRSPdu->nFreqDensity = p_csi_rs_pdu->freqDensity; - pCSIRSPdu->nFreqDomain = p_csi_rs_pdu->freqDomain; - pCSIRSPdu->nNrOfRBs = p_csi_rs_pdu->nrOfRbs; - pCSIRSPdu->nScrambId = p_csi_rs_pdu->scramId; - pCSIRSPdu->nStartRB = p_csi_rs_pdu->startRb; - pCSIRSPdu->nSubcSpacing = p_csi_rs_pdu->subCarrierSpacing; - pCSIRSPdu->nSymbL0 = p_csi_rs_pdu->symbL0; - pCSIRSPdu->nSymbL1 = p_csi_rs_pdu->symbL1; - pCSIRSPdu->nRow = p_csi_rs_pdu->row; + p_CSIRS_pdu->nBWPSize = p_csi_rs_pdu->bwpSize; + p_CSIRS_pdu->nBWPStart = p_csi_rs_pdu->bwpStart; + p_CSIRS_pdu->nCDMType = p_csi_rs_pdu->cdmType; + p_CSIRS_pdu->nCSIType = p_csi_rs_pdu->csiType; + p_CSIRS_pdu->nCpType = p_csi_rs_pdu->cyclicPrefix; + p_CSIRS_pdu->nFreqDensity = p_csi_rs_pdu->freqDensity; + p_CSIRS_pdu->nFreqDomain = p_csi_rs_pdu->freqDomain; + p_CSIRS_pdu->nNrOfRBs = p_csi_rs_pdu->nrOfRbs; + p_CSIRS_pdu->nScrambId = p_csi_rs_pdu->scramId; + p_CSIRS_pdu->nStartRB = p_csi_rs_pdu->startRb; + p_CSIRS_pdu->nSubcSpacing = p_csi_rs_pdu->subCarrierSpacing; + p_CSIRS_pdu->nSymbL0 = p_csi_rs_pdu->symbL0; + p_CSIRS_pdu->nSymbL1 = p_csi_rs_pdu->symbL1; + p_CSIRS_pdu->nRow = p_csi_rs_pdu->row; // Not mapping the beamforming parameters - // pCSIRSPdu->powerControlOffset = p_csi_rs_pdu->powerControlOffset; - // pCSIRSPdu->nEpreRatioToSSB = p_csi_rs_pdu->powerControlOffsetSs; + // p_CSIRS_pdu->powerControlOffset = p_csi_rs_pdu->powerControlOffset; + + if (USE_VENDOR_EPREXSSB != p_phy_instance->phy_config.use_vendor_EpreXSSB) { + p_CSIRS_pdu->nEpreRatioToSSB = nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB(p_csi_rs_pdu->powerControlOffsetSs); + } + p_stats->iapi_stats.iapi_dl_tti_csi_rs_pdus++; } diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_tx_data_req.c b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_tx_data_req.c index 1dda03d..dbb4bf4 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_tx_data_req.c +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_tx_data_req.c @@ -44,6 +44,7 @@ * **/ uint8_t nr5g_fapi_tx_data_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_tx_data_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -51,7 +52,6 @@ uint8_t nr5g_fapi_tx_data_request( PTXRequestStruct p_ia_tx_req; PMAC2PHY_QUEUE_EL p_list_elem; nr5g_fapi_stats_t *p_stats; - UNUSED(p_fapi_vendor_msg); if (NULL == p_phy_instance) { NR5G_FAPI_LOG(ERROR_LOG, ("[TX_Data.request] Invalid " "phy instance")); @@ -74,14 +74,14 @@ uint8_t nr5g_fapi_tx_data_request( } p_ia_tx_req = (PTXRequestStruct) (p_list_elem + 1); - nr5g_fapi_tx_data_req_to_phy_translation(p_phy_instance, p_fapi_req, - p_ia_tx_req); - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_tx_data_req_to_phy_translation(p_phy_instance, p_fapi_req, p_fapi_vendor_msg, p_ia_tx_req); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_tx_req++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[TX_Data.request][%d][%d,%d]", - p_phy_instance->phy_id, p_ia_tx_req->sSFN_Slot.nSFN, - p_ia_tx_req->sSFN_Slot.nSlot)); + NR5G_FAPI_LOG(DEBUG_LOG, ("[TX_Data.request][%u][%u,%u,%u] is_urllc %u", + p_phy_instance->phy_id, + p_ia_tx_req->sSFN_Slot.nSFN, p_ia_tx_req->sSFN_Slot.nSlot, + p_ia_tx_req->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -101,6 +101,7 @@ uint8_t nr5g_fapi_tx_data_request( uint8_t nr5g_fapi_tx_data_req_to_phy_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_tx_data_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PTXRequestStruct p_phy_req) { #define GATHER_SIZE 3 @@ -125,6 +126,12 @@ uint8_t nr5g_fapi_tx_data_req_to_phy_translation( p_phy_req->sSFN_Slot.nCarrierIdx = p_phy_instance->phy_id; p_phy_req->sSFN_Slot.nSFN = p_fapi_req->sfn; p_phy_req->sSFN_Slot.nSlot = p_fapi_req->slot; + + if (NULL != p_fapi_vendor_msg) { + nr5g_fapi_tx_data_req_to_phy_translation_vendor_ext(p_fapi_vendor_msg, + p_phy_req); + } + p_phy_req->nPDU = p_fapi_req->num_pdus; p_phy_pdu = (PDLPDUDataStruct) (p_phy_req + 1); @@ -193,3 +200,22 @@ uint8_t nr5g_fapi_tx_data_req_to_phy_translation( } return SUCCESS; } + + /** @ingroup group_source_api_p7_fapi2phy_proc + * + * @param[in] p_fapi_vendor_msg Pointer to FAPI TX_Data.request structure. + * @param[in] p_ia_tx_req Pointer to IAPI TX_Data.request structure. + * + * @return no return. + * + * @description + * This function fills fields for TX.Data structure that come from + * a vendor extension. + * +**/ +void nr5g_fapi_tx_data_req_to_phy_translation_vendor_ext( + fapi_vendor_msg_t * p_fapi_vendor_msg, + PTXRequestStruct p_phy_req) +{ + p_phy_req->sSFN_Slot.nSym = p_fapi_vendor_msg->p7_req_vendor.tx_data_req.sym; +} \ No newline at end of file diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_dci_req.c b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_dci_req.c index c9620c7..fde5569 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_dci_req.c +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_dci_req.c @@ -42,6 +42,7 @@ * **/ uint8_t nr5g_fapi_ul_dci_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_dci_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -49,7 +50,6 @@ uint8_t nr5g_fapi_ul_dci_request( PULDCIRequestStruct p_ia_ul_dci_req; PMAC2PHY_QUEUE_EL p_list_elem; nr5g_fapi_stats_t *p_stats; - UNUSED(p_fapi_vendor_msg); if (NULL == p_phy_instance) { NR5G_FAPI_LOG(ERROR_LOG, ("[UL_DCI.request] Invalid " "phy instance")); @@ -72,6 +72,8 @@ uint8_t nr5g_fapi_ul_dci_request( } p_ia_ul_dci_req = (PULDCIRequestStruct) (p_list_elem + 1); + NR5G_FAPI_MEMSET(p_ia_ul_dci_req, sizeof(PULDCIRequestStruct), 0, + sizeof(PULDCIRequestStruct)); p_ia_ul_dci_req->sMsgHdr.nMessageType = MSG_TYPE_PHY_UL_DCI_REQ; p_ia_ul_dci_req->sMsgHdr.nMessageLen = (uint16_t) sizeof(ULDCIRequestStruct); @@ -87,12 +89,21 @@ uint8_t nr5g_fapi_ul_dci_request( p_ia_ul_dci_req->sSFN_Slot.nSlot)); return FAILURE; } - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_ul_dci_req++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_DCI.request][%d][%d,%d]", + + + if (NULL != p_fapi_vendor_msg) { + nr5g_fapi_ul_dci_req_to_phy_translation_vendor_ext(p_phy_instance, + p_fapi_vendor_msg, + p_ia_ul_dci_req); + } + + NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_DCI.request][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_ia_ul_dci_req->sSFN_Slot.nSFN, p_ia_ul_dci_req->sSFN_Slot.nSlot)); + p_ia_ul_dci_req->sSFN_Slot.nSFN, p_ia_ul_dci_req->sSFN_Slot.nSlot, + p_ia_ul_dci_req->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -115,6 +126,7 @@ uint8_t nr5g_fapi_ul_dci_req_to_phy_translation( PULDCIRequestStruct p_ia_ul_dci_req) { int idx; + int ruidx; fapi_dci_pdu_t *p_fapi_dci_pdu; DCIPDUStruct *p_ia_dci_pdu; nr5g_fapi_stats_t *p_stats; @@ -169,10 +181,18 @@ uint8_t nr5g_fapi_ul_dci_req_to_phy_translation( p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].scramblingRnti; p_ia_dci_pdu->nTotalBits = p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].payloadSizeBits; + + + if (USE_VENDOR_EPREXSSB != p_phy_instance->phy_config.use_vendor_EpreXSSB) + { p_ia_dci_pdu->nEpreRatioOfPDCCHToSSB = - p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].powerControlOffsetSS; + nr5g_fapi_calculate_nEpreRatioOfPDCCHToSSB(p_fapi_dci_pdu-> + pdcchPduConfig.dlDci[0].beta_pdcch_1_0); p_ia_dci_pdu->nEpreRatioOfDmrsToSSB = - p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].beta_pdcch_1_0; + nr5g_fapi_calculate_nEpreRatioOfDmrsToSSB(p_fapi_dci_pdu-> + pdcchPduConfig.dlDci[0].powerControlOffsetSS); + } + p_ia_dci_pdu->nTotalBits = p_fapi_dci_pdu->pdcchPduConfig.dlDci[0].payloadSizeBits; if (FAILURE == NR5G_FAPI_MEMCPY(p_ia_dci_pdu->nDciBits, @@ -187,9 +207,54 @@ uint8_t nr5g_fapi_ul_dci_req_to_phy_translation( p_ia_dci_pdu->nID = p_ia_dci_pdu->nScid; p_ia_dci_pdu->nNrofTxRU = 0x0; p_ia_dci_pdu->nBeamId = 0x0; + + for (ruidx = 0; ruidx < MAX_TXRU_NUM; ruidx++) { + p_ia_dci_pdu->nTxRUIdx[ruidx] = 0; + } p_ia_curr += RUP32B(sizeof(DCIPDUStruct)); } p_stats->iapi_stats.iapi_ul_dci_pdus++; return SUCCESS; } + + /** @ingroup group_source_api_p7_fapi2phy_proc + * + * @param[in] p_fapi_vendor_msg Pointer to FAPI UL_DCI.request vendor message. + * @param[out] p_ia_ul_dci_req Pointer to IAPI UL_DCI.request structure. + * + * @return no return. + * + * @description + * This function fills fields for UL_DCI.request structure that come from + * a vendor extension. + * +**/ +void nr5g_fapi_ul_dci_req_to_phy_translation_vendor_ext( + p_nr5g_fapi_phy_instance_t p_phy_instance, + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULDCIRequestStruct p_ia_ul_dci_req) +{ + int idx = 0; + + fapi_vendor_dci_pdu_t *p_vendor_dci_pdu; + DCIPDUStruct *p_ia_dci_pdu; + uint8_t *p_ia_curr = NULL; + + p_ia_ul_dci_req->sSFN_Slot.nSym = p_fapi_vendor_msg->p7_req_vendor.ul_dci_req.sym; + + p_ia_curr = (uint8_t *) p_ia_ul_dci_req->sULDCIPDU; + + for (idx = 0; idx < p_ia_ul_dci_req->nDCI; idx++) { + p_ia_dci_pdu = (DCIPDUStruct *) p_ia_curr; + if (USE_VENDOR_EPREXSSB == p_phy_instance->phy_config.use_vendor_EpreXSSB) + { + p_vendor_dci_pdu = &p_fapi_vendor_msg->p7_req_vendor.ul_dci_req.pdus[idx]; + p_ia_dci_pdu->nEpreRatioOfPDCCHToSSB = p_vendor_dci_pdu-> + pdcch_pdu_config.dl_dci[0].epre_ratio_of_pdcch_to_ssb; + p_ia_dci_pdu->nEpreRatioOfDmrsToSSB = p_vendor_dci_pdu-> + pdcch_pdu_config.dl_dci[0].epre_ratio_of_dmrs_to_ssb; + } + p_ia_curr += RUP32B(sizeof(DCIPDUStruct)); + } +} \ No newline at end of file diff --git a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_tti_req.c b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_tti_req.c index 0f7795b..32aaa9f 100644 --- a/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_tti_req.c +++ b/fapi_5g/source/api/fapi2phy/p7/nr5g_fapi_proc_ul_tti_req.c @@ -31,6 +31,8 @@ #include "nr5g_fapi_memory.h" #include +#define NUM_UL_PTRS_PORT_INDEX (12) + /** @ingroup group_source_api_p7_fapi2phy_proc * * @param[in] p_phy_instance Pointer to PHY instance. @@ -43,6 +45,7 @@ * **/ uint8_t nr5g_fapi_ul_tti_request( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_tti_req_t * p_fapi_req, fapi_vendor_msg_t * p_fapi_vendor_msg) @@ -50,7 +53,6 @@ uint8_t nr5g_fapi_ul_tti_request( PULConfigRequestStruct p_ia_ul_config_req; PMAC2PHY_QUEUE_EL p_list_elem; nr5g_fapi_stats_t *p_stats; - UNUSED(p_fapi_vendor_msg); if (NULL == p_phy_instance) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI][UL_TTI.request] Invalid " @@ -83,8 +85,8 @@ uint8_t nr5g_fapi_ul_tti_request( p_ia_ul_config_req->sMsgHdr.nMessageLen = (uint16_t) sizeof(ULConfigRequestStruct); - if (FAILURE == nr5g_fapi_ul_tti_req_to_phy_translation(p_phy_instance, - p_fapi_req, p_ia_ul_config_req)) { + if (FAILURE == nr5g_fapi_ul_tti_req_to_phy_translation(is_urllc, p_phy_instance, + p_fapi_req, p_fapi_vendor_msg, p_ia_ul_config_req)) { nr5g_fapi_fapi2phy_destroy_api_list_elem(p_list_elem); NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_TTI.request][%d][%d,%d] Not Sent", p_phy_instance->phy_id, p_ia_ul_config_req->sSFN_Slot.nSFN, @@ -92,13 +94,13 @@ uint8_t nr5g_fapi_ul_tti_request( return FAILURE; } - nr5g_fapi_fapi2phy_add_to_api_list(p_list_elem); + nr5g_fapi_fapi2phy_add_to_api_list(is_urllc, p_list_elem); p_stats->iapi_stats.iapi_ul_config_req++; - NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_TTI.request][%d][%d,%d]", + NR5G_FAPI_LOG(DEBUG_LOG, ("[UL_TTI.request][%u][%u,%u,%u] is_urllc %u", p_phy_instance->phy_id, - p_ia_ul_config_req->sSFN_Slot.nSFN, - p_ia_ul_config_req->sSFN_Slot.nSlot)); + p_ia_ul_config_req->sSFN_Slot.nSFN, p_ia_ul_config_req->sSFN_Slot.nSlot, + p_ia_ul_config_req->sSFN_Slot.nSym, is_urllc)); return SUCCESS; } @@ -167,45 +169,6 @@ uint32_t nr5g_fapi_calc_n_rbg_index_entry( } /** @ingroup group_source_api_p7_fapi2phy_proc - * - * @param[in] fapi_alpha_scaling Variable holding the FAPI Alpha Scaling Value. - * - * @return Returns ::PHY equivalent Alpha Scaling Value. - * - * @description - * This functions derives the PHY equivalent Alpha Scaling value from FAPI Alpha Scaling Value. - * -**/ -uint8_t nr5g_fapi_calc_alpha_scaling( - uint8_t fapi_alpha_scaling) -{ - uint8_t alpha_scaling; - - switch (fapi_alpha_scaling) { - case 0: - alpha_scaling = 127; - break; - - case 1: - alpha_scaling = 166; - break; - - case 2: - alpha_scaling = 205; - break; - - case 3: - alpha_scaling = 255; - break; - - default: - alpha_scaling = 0; - break; - } - return alpha_scaling; -} - -/** @ingroup group_source_api_p7_fapi2phy_proc * * @param[in] p_pusch_data Pointer to FAPI Optional PUSCH Data structure. * @param[in] p_ul_data_chan Pointer to IAPI ULSCH PDU structure. @@ -247,12 +210,12 @@ void nr5g_fapi_pusch_uci_to_phy_ulsch_translation( ULSCHPDUStruct * p_ul_data_chan) { p_ul_data_chan->nAck = p_pusch_uci->harqAckBitLength; - //csiPart1BitLength and csiPart2BitLength are ignored as per design - p_ul_data_chan->nAlphaScaling = - nr5g_fapi_calc_alpha_scaling(p_pusch_uci->alphaScaling); - //p_ul_data_chan->nAlphaScaling = 0; + p_ul_data_chan->nAlphaScaling = p_pusch_uci->alphaScaling; p_ul_data_chan->nBetaOffsetACKIndex = p_pusch_uci->betaOffsetHarqAck; - //betaOffsetCsi1 and betaOffsetCsi2 are ignored as per design + p_ul_data_chan->nBetaOffsetCSIP1Index = p_pusch_uci->betaOffsetCsi1; + p_ul_data_chan->nBetaOffsetCSIP2Index = p_pusch_uci->betaOffsetCsi2; + p_ul_data_chan->nCSIPart1 = p_pusch_uci->csiPart1BitLength; + p_ul_data_chan->nCSIPart2 = p_pusch_uci->csiPart2BitLength; } /** @ingroup group_source_api_p7_fapi2phy_proc @@ -286,10 +249,13 @@ void nr5g_fapi_pusch_ptrs_to_phy_ulsch_translation( if (p_pusch_ptrs->numPtrsPorts > 0) { num_ptrs_ports = p_ul_data_chan->nNrOfPTRSPorts = 1; } - for (i = 0; (i < num_ptrs_ports && port_index < FAPI_MAX_PTRS_PORTS); i++) { + for (i = 0; i < num_ptrs_ports && i < FAPI_MAX_PTRS_PORTS; i++) { p_ptrs_info = &p_pusch_ptrs->ptrsInfo[i]; - if ((p_ptrs_info->ptrsPortIndex >> i) & 0x01) { - p_ul_data_chan->nPTRSPortIndex[port_index++] = i; + for (port_index = 0; port_index < NUM_UL_PTRS_PORT_INDEX; port_index++) + { + if ((p_ptrs_info->ptrsPortIndex >> port_index) & 0x01) { + p_ul_data_chan->nPTRSPortIndex[i] = port_index; + } } //PTRSDmrsPort is ignored as per Design p_ul_data_chan->nPTRSReOffset = p_ptrs_info->ptrsReOffset; @@ -411,57 +377,15 @@ void nr5g_fapi_pusch_to_phy_ulsch_translation( p_ul_data_chan->nPTRSPresent = 1; } p_ul_data_chan->nULType = 0; - p_ul_data_chan->nNrOfAntennaPorts = - p_phy_instance->phy_config.n_nr_of_rx_ant; p_ul_data_chan->nRBBundleSize = 0; p_ul_data_chan->nPMI = 0; p_ul_data_chan->nTransmissionScheme = 0; p_ul_data_chan->rsv1 = 0; - p_ul_data_chan->nNrofRxRU = p_phy_instance->phy_config.n_nr_of_rx_ant; - p_stats->iapi_stats.iapi_ul_tti_pusch_pdus++; -} - /** @ingroup group_source_api_p7_fapi2phy_proc - * - * @param[in] num_groups Variable holding the groups for which PUCCH resources - are unique - * @param[in] initial_cyclic_shift Variable holding the parameter initial_cyclic - shift to be verified against the already receieved pucch resources. - * @param[in] nr_of_layers Variable holding the parameter nr_of_symbols - to be verified against the already received pucch resources. - * @param[in] start_symbol_index Variable holding the parameter start_symbol_index - to be verified against the already received pucch resources. - * @param[in] time_domain_occ_idx Variable holding the parameter time_domain_occ_idx - to be verified against the already received pucch resources. - * @param[in] p_pucch_resources Pointer pointing to the received pucch resources. - -* @return group_id, if pucch_resources match with parameters passed. - * 0xFF, if pucch_resources not match with parameters passed. - * @description - * This function returns the group_id if parameters passed already available in - * pucch_resources received earlier. - * -**/ -uint8_t nr5g_get_pucch_resources_group_id( - uint8_t num_groups, - uint16_t initial_cyclic_shift, - uint8_t nr_of_symbols, - uint8_t start_symbol_index, - uint8_t time_domain_occ_idx, - nr5g_fapi_pucch_resources_t * p_pucch_resources) -{ - uint8_t i, group_id = 0xFF; - for (i = 0; i < num_groups; i++) { - if ((initial_cyclic_shift == p_pucch_resources[i].initial_cyclic_shift) - && (nr_of_symbols == p_pucch_resources[i].nr_of_symbols) - && (start_symbol_index == p_pucch_resources[i].start_symbol_index) - && (time_domain_occ_idx == - p_pucch_resources[i].time_domain_occ_idx)) { - group_id = p_pucch_resources[i].group_id; - break; - } - } - return group_id; + p_ul_data_chan->nNrOfAntennaPorts = 1; + p_ul_data_chan->nNrofRxRU = 1; + + p_stats->iapi_stats.iapi_ul_tti_pusch_pdus++; } /** @ingroup group_source_api_p7_fapi2phy_proc @@ -481,16 +405,9 @@ void nr5g_fapi_pucch_to_phy_ulcch_uci_translation( p_nr5g_fapi_phy_instance_t p_phy_instance, nr5g_fapi_pucch_info_t * p_pucch_info, fapi_ul_pucch_pdu_t * p_pucch_pdu, - uint8_t * num_group_ids, - nr5g_fapi_pucch_resources_t * p_pucch_resources, ULCCHUCIPDUStruct * p_ul_ctrl_chan) { - uint8_t group_id; nr5g_fapi_stats_t *p_stats; - uint8_t initial_cyclic_shift, nr_of_symbols; - uint8_t start_symbol_index, time_domain_occ_idx; - uint8_t num_groups = *num_group_ids; - p_stats = &p_phy_instance->stats; p_stats->fapi_stats.fapi_ul_tti_pucch_pdus++; NR5G_FAPI_MEMSET(p_ul_ctrl_chan, sizeof(ULCCHUCIPDUStruct), 0, @@ -515,42 +432,23 @@ void nr5g_fapi_pucch_to_phy_ulcch_uci_translation( } p_ul_ctrl_chan->nStartPRB = p_pucch_pdu->prbStart; p_ul_ctrl_chan->nPRBs = p_pucch_pdu->prbSize; - start_symbol_index = p_ul_ctrl_chan->nStartSymbolx = - p_pucch_pdu->startSymbolIndex; - nr_of_symbols = p_ul_ctrl_chan->nSymbols = p_pucch_pdu->nrOfSymbols; + p_ul_ctrl_chan->nStartSymbolx = p_pucch_pdu->startSymbolIndex; + p_ul_ctrl_chan->nSymbols = p_pucch_pdu->nrOfSymbols; p_ul_ctrl_chan->nFreqHopFlag = p_pucch_pdu->freqHopFlag; p_ul_ctrl_chan->n2ndHopPRB = p_pucch_pdu->secondHopPrb; - initial_cyclic_shift = p_ul_ctrl_chan->nM0 = - p_pucch_pdu->initialCyclicShift; + p_ul_ctrl_chan->nM0 = p_pucch_pdu->initialCyclicShift; p_ul_ctrl_chan->nID = p_pucch_pdu->dataScramblingId; - time_domain_occ_idx = p_ul_ctrl_chan->nFmt1OrthCCodeIdx = - p_pucch_pdu->timeDomainOccIdx; + p_ul_ctrl_chan->nFmt1OrthCCodeIdx = p_pucch_pdu->timeDomainOccIdx; p_ul_ctrl_chan->nFmt4OrthCCodeIdx = p_pucch_pdu->preDftOccIdx; p_ul_ctrl_chan->nFmt4OrthCCodeLength = p_pucch_pdu->preDftOccLen; p_ul_ctrl_chan->nAddDmrsFlag = p_pucch_pdu->addDmrsFlag; p_ul_ctrl_chan->nScramID = p_pucch_pdu->dmrsScramblingId; p_ul_ctrl_chan->nSRPriodAriv = p_pucch_pdu->srFlag; p_ul_ctrl_chan->nBitLenUci = p_pucch_pdu->bitLenHarq; - p_ul_ctrl_chan->nNrofRxRU = p_phy_instance->phy_config.n_nr_of_rx_ant; - - group_id = - nr5g_get_pucch_resources_group_id(num_groups, initial_cyclic_shift, - nr_of_symbols, start_symbol_index, time_domain_occ_idx, - p_pucch_resources); - if (group_id == 0xFF) { - p_pucch_resources[num_groups].group_id = num_groups; - p_pucch_resources[num_groups].initial_cyclic_shift = - initial_cyclic_shift; - p_pucch_resources[num_groups].nr_of_symbols = nr_of_symbols; - p_pucch_resources[num_groups].start_symbol_index = start_symbol_index; - p_pucch_resources[num_groups].time_domain_occ_idx = time_domain_occ_idx; - p_ul_ctrl_chan->nGroupId = num_groups; - num_groups++; - } else { - p_ul_ctrl_chan->nGroupId = group_id; - } - *num_group_ids = num_groups; + + p_ul_ctrl_chan->nNrofRxRU = 1; + p_stats->iapi_stats.iapi_ul_tti_pucch_pdus++; } @@ -613,7 +511,8 @@ void nr5g_fapi_srs_to_phy_srs_translation( p_ul_srs_chan->nTsrs = p_srs_pdu->tSrs; p_ul_srs_chan->nToffset = p_srs_pdu->tOffset; p_ul_srs_chan->nToffset = p_srs_pdu->tOffset; - p_ul_srs_chan->nNrofRxRU = p_phy_instance->phy_config.n_nr_of_rx_ant; + + p_ul_srs_chan->nNrofRxRU = 1; p_stats->iapi_stats.iapi_ul_tti_srs_pdus++; } @@ -631,14 +530,16 @@ void nr5g_fapi_srs_to_phy_srs_translation( * **/ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, fapi_ul_tti_req_t * p_fapi_req, + fapi_vendor_msg_t * p_fapi_vendor_msg, PULConfigRequestStruct p_ia_ul_config_req) { - uint8_t i, j, num_group_id = 0; - uint8_t num_fapi_pdus, num_groups, num_ue = 0; + uint8_t i, j; + uint8_t num_fapi_pdus, num_groups, num_ue = 0u; uint16_t frame_no; - uint8_t slot_no; + uint8_t slot_no, symbol_no; fapi_ul_tti_req_pdu_t *p_fapi_ul_tti_req_pdu; fapi_ue_info_t *p_fapi_ue_grp_info; @@ -649,7 +550,6 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( PDUStruct *p_pdu_head; nr5g_fapi_ul_slot_info_t *p_ul_slot_info; nr5g_fapi_stats_t *p_stats; - nr5g_fapi_pucch_resources_t pucch_resources[FAPI_MAX_NUM_PUCCH_PDU]; p_stats = &p_phy_instance->stats; @@ -657,9 +557,18 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( slot_no = p_ia_ul_config_req->sSFN_Slot.nSlot = p_fapi_req->slot; p_ia_ul_config_req->sSFN_Slot.nCarrierIdx = p_phy_instance->phy_id; + if (FAILURE == nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext_symbol_no(is_urllc, + p_fapi_vendor_msg, p_ia_ul_config_req, &symbol_no)) + { + return FAILURE; + } + p_ul_slot_info = - &p_phy_instance->ul_slot_info[(slot_no % MAX_UL_SLOT_INFO_COUNT)]; - nr5g_fapi_set_ul_slot_info(frame_no, slot_no, p_ul_slot_info); + &p_phy_instance->ul_slot_info[is_urllc] + [(slot_no % MAX_UL_SLOT_INFO_COUNT)] + [symbol_no % MAX_UL_SYMBOL_INFO_COUNT];// TODO: will be split in 2 in a separate MR, as non-urllc does not need symbol info + + nr5g_fapi_set_ul_slot_info(frame_no, slot_no, symbol_no, p_ul_slot_info); num_fapi_pdus = p_ia_ul_config_req->nPDU = p_fapi_req->nPdus; num_groups = p_ia_ul_config_req->nGroup = p_fapi_req->nGroup; @@ -672,11 +581,11 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( p_phy_instance->phy_config.phy_cell_id; } p_ia_ul_config_req->nUlsrs = 0; - for (i = 0; i < num_groups; i++) { + for (i = 0u; i < num_groups; i++) { p_pusch_grp_info = &p_ia_ul_config_req->sPUSCHGroupInfoStruct[i]; p_fapi_ue_grp_info = &p_fapi_req->ueGrpInfo[i]; num_ue = p_pusch_grp_info->nUE = p_fapi_ue_grp_info->nUe; - for (j = 0; j < num_ue; j++) { + for (j = 0u; j < num_ue; j++) { p_pusch_grp_info->nPduIdx[j] = p_fapi_ue_grp_info->pduIdx[j]; } } @@ -702,7 +611,8 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( p_ul_data_chan = (ULSCHPDUStruct *) p_pdu_head; nr5g_fapi_pusch_to_phy_ulsch_translation(p_phy_instance, &p_ul_slot_info->pusch_info[p_ul_slot_info->num_ulsch], - &p_fapi_ul_tti_req_pdu->pdu.pusch_pdu, p_ul_data_chan); + &p_fapi_ul_tti_req_pdu->pdu.pusch_pdu, + p_ul_data_chan); p_ul_slot_info->num_ulsch++; } break; @@ -712,8 +622,8 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( p_ul_ctrl_chan = (ULCCHUCIPDUStruct *) p_pdu_head; nr5g_fapi_pucch_to_phy_ulcch_uci_translation(p_phy_instance, &p_ul_slot_info->pucch_info[p_ul_slot_info->num_ulcch], - &p_fapi_ul_tti_req_pdu->pdu.pucch_pdu, &num_group_id, - pucch_resources, p_ul_ctrl_chan); + &p_fapi_ul_tti_req_pdu->pdu.pucch_pdu, + p_ul_ctrl_chan); p_ul_slot_info->num_ulcch++; } break; @@ -742,5 +652,134 @@ uint8_t nr5g_fapi_ul_tti_req_to_phy_translation( (PDUStruct *) ((uint8_t *) p_pdu_head + p_pdu_head->nPDUSize); p_stats->iapi_stats.iapi_ul_tti_pdus++; } + + if (NULL != p_fapi_vendor_msg) { + nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext(p_fapi_vendor_msg, + p_ia_ul_config_req); + } + return SUCCESS; } + + /** @ingroup group_source_api_p7_fapi2phy_proc + * + * @param[in] p_fapi_vendor_msg Pointer to FAPI UL_TTI.request vendor message. + * @param[in] p_ia_ul_config_req Pointer to IAPI UL_TTI.request structure. + * + * @return no return. + * + * @description + * This function fills fields for UL_TTI.request structure that come from + * a vendor extension. + * +**/ +void nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext( + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULConfigRequestStruct p_ia_ul_config_req) +{ + uint8_t i = 0u; + + fapi_vendor_ul_tti_req_t *p_vendor_ul_tti_req = NULL; + fapi_vendor_ul_tti_req_pdu_t *p_fapi_vendor_ul_tti_req_pdu = NULL; + fapi_vendor_ul_pusch_pdu_t *p_vendor_pusch_pdu = NULL; + fapi_vendor_ul_pucch_pdu_t *p_vendor_pucch_pdu = NULL; + fapi_vendor_ul_srs_pdu_t *p_vendor_srs_pdu = NULL; + + ULSCHPDUStruct *p_ul_data_chan; + ULCCHUCIPDUStruct *p_ul_ctrl_chan; + SRSPDUStruct *p_ul_srs_chan; + PDUStruct *p_pdu_head; + + p_vendor_ul_tti_req = &p_fapi_vendor_msg->p7_req_vendor.ul_tti_req; + + p_pdu_head = p_ia_ul_config_req->sULPDU; + + for (i = 0u; i < p_ia_ul_config_req->nPDU; i++) { + p_fapi_vendor_ul_tti_req_pdu = &p_vendor_ul_tti_req->ul_pdus[i]; + + switch (p_pdu_head->nPDUType) { + case UL_PDU_TYPE_PRACH: + // Not used + break; + + case UL_PDU_TYPE_ULSCH: + { + p_ul_data_chan = (ULSCHPDUStruct *) p_pdu_head; + p_vendor_pusch_pdu = &p_fapi_vendor_ul_tti_req_pdu->pdu.pusch_pdu; + + p_ul_data_chan->nNrOfAntennaPorts = p_vendor_pusch_pdu->nr_of_antenna_ports; + p_ul_data_chan->nNrofRxRU = p_vendor_pusch_pdu->nr_of_rx_ru; + NR5G_FAPI_MEMCPY(p_ul_data_chan->nRxRUIdx, sizeof(p_ul_data_chan->nRxRUIdx), + p_vendor_pusch_pdu->rx_ru_idx, sizeof(p_vendor_pusch_pdu->rx_ru_idx)); + } + break; + + case UL_PDU_TYPE_ULCCH_UCI: + { + p_ul_ctrl_chan = (ULCCHUCIPDUStruct *) p_pdu_head; + p_vendor_pucch_pdu = &p_fapi_vendor_ul_tti_req_pdu->pdu.pucch_pdu; + + p_ul_ctrl_chan->nNrofRxRU = p_vendor_pucch_pdu->nr_of_rx_ru; + p_ul_ctrl_chan->nGroupId = p_vendor_pucch_pdu->group_id; + NR5G_FAPI_MEMCPY(p_ul_ctrl_chan->nRxRUIdx, sizeof(p_ul_ctrl_chan->nRxRUIdx), + p_vendor_pucch_pdu->rx_ru_idx, sizeof(p_vendor_pucch_pdu->rx_ru_idx)); + } + break; + + case UL_PDU_TYPE_SRS: + { + p_ul_srs_chan = (SRSPDUStruct *) p_pdu_head; + p_vendor_srs_pdu = &p_fapi_vendor_ul_tti_req_pdu->pdu.srs_pdu; + + p_ul_srs_chan->nNrofRxRU = p_vendor_srs_pdu->nr_of_rx_ru; + NR5G_FAPI_MEMCPY(p_ul_srs_chan->nRxRUIdx, sizeof(p_ul_srs_chan->nRxRUIdx), + p_vendor_srs_pdu->rx_ru_idx, sizeof(p_vendor_srs_pdu->rx_ru_idx)); + } + break; + + default: + { + NR5G_FAPI_LOG(ERROR_LOG, + ("[NR5G_FAPI] [UL_TTI.request] Unknown PDU Type :%d", + p_ia_ul_config_req->sMsgHdr.nMessageType)); + return; + } + } + p_pdu_head = + (PDUStruct *) ((uint8_t *) p_pdu_head + p_pdu_head->nPDUSize); + } +} + + + /** @ingroup group_source_api_p7_fapi2phy_proc + * + * @param[in] p_fapi_vendor_msg Pointer to FAPI UL_TTI.request vendor message. + * @param[in] p_ia_ul_config_req Pointer to IAPI UL_TTI.request structure. + * + * @return Returns ::SUCCESS and ::FAILURE. + * + * @description + * This function fills symbol_no field for UL_TTI.request structure and fails if + * the mode is urllc and there is no associated vendor_msg. + * +**/ +uint8_t nr5g_fapi_ul_tti_req_to_phy_translation_vendor_ext_symbol_no( + bool is_urllc, + fapi_vendor_msg_t * p_fapi_vendor_msg, + PULConfigRequestStruct p_ia_ul_config_req, + uint8_t* symbol_no) +{ + // for non-urllc mode symbol_no is a don't care + *symbol_no = 0u; + if (is_urllc) + { + if (NULL == p_fapi_vendor_msg) + { + NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI][UL_TTI.request] No vendor ext for URLLC! " + "_vendor_ul_tti_req")); + return FAILURE; + } + *symbol_no = p_ia_ul_config_req->sSFN_Slot.nSym = p_fapi_vendor_msg->p7_req_vendor.ul_tti_req.sym; + } + return SUCCESS; +} \ No newline at end of file diff --git a/fapi_5g/source/framework/nr5g_fapi_framework.c b/fapi_5g/source/framework/nr5g_fapi_framework.c index 629435e..c65b64b 100644 --- a/fapi_5g/source/framework/nr5g_fapi_framework.c +++ b/fapi_5g/source/framework/nr5g_fapi_framework.c @@ -35,8 +35,8 @@ inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx( uint8_t nr5g_fapi_dpdk_init( p_nr5g_fapi_cfg_t p_cfg) { - printf("init dev name: %s\n", p_cfg->wls.device_name); - char *const file_prefix = basename(p_cfg->wls.device_name); + printf("init dev name: %s\n", p_cfg->dpdk.memory_zone); + char *const file_prefix = basename(p_cfg->dpdk.memory_zone); printf("init basename: %s\n", file_prefix); char whitelist[32], iova_mode[64]; uint8_t i; @@ -55,7 +55,7 @@ uint8_t nr5g_fapi_dpdk_init( int argc = RTE_DIM(argv); /* initialize EAL first */ - snprintf(whitelist, 32, "-w %s", "0000:00:06.0"); + snprintf(whitelist, 32, "-a%s", "0000:00:06.0"); if (p_cfg->dpdk.iova_mode == 0) snprintf(iova_mode, 64, "%s", "--iova-mode=pa"); @@ -88,36 +88,44 @@ uint8_t nr5g_fapi_dpdk_wait( #else pthread_join(p_cfg->mac2phy_thread_info.thread_id, NULL); pthread_join(p_cfg->phy2mac_thread_info.thread_id, NULL); + pthread_join(p_cfg->urllc_thread_info.thread_id, NULL); #endif return SUCCESS; } void nr5g_fapi_set_ul_slot_info( uint16_t frame_no, - uint8_t slot_no, + uint16_t slot_no, + uint8_t symbol_no, nr5g_fapi_ul_slot_info_t * p_ul_slot_info) { - NR5G_FAPI_MEMSET(p_ul_slot_info, sizeof(nr5g_fapi_ul_slot_info_t), 0, - sizeof(nr5g_fapi_ul_slot_info_t)); + NR5G_FAPI_MEMSET(p_ul_slot_info, sizeof(nr5g_fapi_ul_slot_info_t), 0, sizeof(nr5g_fapi_ul_slot_info_t)); + p_ul_slot_info->cookie = frame_no; p_ul_slot_info->slot_no = slot_no; + p_ul_slot_info->symbol_no = symbol_no; } nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info( + bool is_urllc, uint16_t frame_no, - uint8_t slot_no, + uint16_t slot_no, + uint8_t symbol_no, p_nr5g_fapi_phy_instance_t p_phy_instance) { - uint8_t i; + uint8_t i, j; nr5g_fapi_ul_slot_info_t *p_ul_slot_info; for (i = 0; i < MAX_UL_SLOT_INFO_COUNT; i++) { - p_ul_slot_info = &p_phy_instance->ul_slot_info[i]; + for(j = 0; j < MAX_UL_SYMBOL_INFO_COUNT; j++) { + p_ul_slot_info = &p_phy_instance->ul_slot_info[is_urllc][i][j]; if ((slot_no == p_ul_slot_info->slot_no) && - (frame_no == p_ul_slot_info->cookie)) { + (frame_no == p_ul_slot_info->cookie) && + (symbol_no == p_ul_slot_info->symbol_no)) { return p_ul_slot_info; } } + } return NULL; } @@ -125,7 +133,7 @@ uint8_t nr5g_fapi_framework_init( p_nr5g_fapi_cfg_t p_cfg) { p_nr5g_fapi_phy_ctx_t p_phy_ctx = nr5g_fapi_get_nr5g_fapi_phy_ctx(); - pthread_attr_t *p_mac2phy_attr, *p_phy2mac_attr; + pthread_attr_t *p_mac2phy_attr, *p_phy2mac_attr, *p_urllc_attr; struct sched_param param; nr5g_fapi_set_log_level(p_cfg->logger.level); @@ -138,6 +146,19 @@ uint8_t nr5g_fapi_framework_init( p_phy_ctx->phy2mac_worker_core_id = p_cfg->phy2mac_worker.core_id; p_phy_ctx->mac2phy_worker_core_id = p_cfg->mac2phy_worker.core_id; + p_phy_ctx->urllc_worker_core_id = p_cfg->urllc_worker.core_id; + + memset(&p_phy_ctx->urllc_sem_process, 0, sizeof(sem_t)); + memset(&p_phy_ctx->urllc_sem_done, 0, sizeof(sem_t)); + if (0 != sem_init(&p_phy_ctx->urllc_sem_process, 0, 0)) { + printf("Error: Unable to init urllc semaphore\n"); + return FAILURE; + } + if (0 != sem_init(&p_phy_ctx->urllc_sem_done, 0, 1)) { + printf("Error: Unable to init urllc_sem_done semaphore\n"); + return FAILURE; + } + p_phy2mac_attr = &p_cfg->phy2mac_thread_info.thread_attr; pthread_attr_init(p_phy2mac_attr); if (!pthread_attr_getschedparam(p_phy2mac_attr, ¶m)) { @@ -176,5 +197,26 @@ uint8_t nr5g_fapi_framework_init( pthread_setname_np(p_cfg->mac2phy_thread_info.thread_id, "nr5g_fapi_mac2phy_thread"); + p_urllc_attr = &p_cfg->urllc_thread_info.thread_attr; + pthread_attr_init(p_urllc_attr); + if (!pthread_attr_getschedparam(p_urllc_attr, ¶m)) { + param.sched_priority = p_cfg->urllc_worker.thread_sched_policy; + pthread_attr_setschedparam(p_urllc_attr, ¶m); + pthread_attr_setschedpolicy(p_urllc_attr, SCHED_FIFO); + } + + if (0 != pthread_create(&p_cfg->urllc_thread_info.thread_id, + p_urllc_attr, nr5g_fapi_urllc_thread_func, (void *) + p_phy_ctx)) { + printf("Error: Unable to create threads\n"); + if (p_urllc_attr) + pthread_attr_destroy(p_urllc_attr); + sem_destroy(&p_phy_ctx->urllc_sem_process); + sem_destroy(&p_phy_ctx->urllc_sem_done); + return FAILURE; + } + pthread_setname_np(p_cfg->urllc_thread_info.thread_id, + "nr5g_fapi_urllc_thread"); + return SUCCESS; } diff --git a/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c b/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c index cba45fc..3944551 100644 --- a/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c +++ b/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.c @@ -27,6 +27,7 @@ #include "gnb_l1_l2_api.h" #include "nr5g_fapi_fapi2mac_wls.h" #include "nr5g_fapi_log.h" +#include "nr5g_fapi_urllc_thread.h" static p_fapi_api_queue_elem_t p_fapi2mac_buffers; @@ -197,7 +198,7 @@ uint8_t nr5g_fapi_fapi2mac_wls_ready( * **/ //------------------------------------------------------------------------------ -static inline uint8_t nr5g_fapi_fapi2mac_wls_wait( +uint32_t nr5g_fapi_fapi2mac_wls_wait( ) { int ret = SUCCESS; @@ -269,7 +270,7 @@ uint64_t *nr5g_fapi_fapi2mac_wls_get( * **/ //------------------------------------------------------------------------------ -uint8_t nr5g_fapi_fapi2mac_wls_put( +inline uint8_t nr5g_fapi_fapi2mac_wls_put( p_fapi_api_queue_elem_t p_msg, uint32_t msg_size, uint16_t msg_type, @@ -300,12 +301,14 @@ uint8_t nr5g_fapi_fapi2mac_wls_put( **/ //------------------------------------------------------------------------------ uint8_t nr5g_fapi_fapi2mac_wls_send( - p_fapi_api_queue_elem_t p_list_elem) + p_fapi_api_queue_elem_t p_list_elem, + bool is_urllc) { uint8_t ret = SUCCESS; p_fapi_api_queue_elem_t p_curr_msg = NULL; fapi_msg_t *p_msg_header = NULL; uint16_t flags = 0; + uint16_t flags_urllc = (is_urllc ? WLS_TF_URLLC : 0); p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context(); uint64_t start_tick = __rdtsc(); @@ -317,7 +320,7 @@ uint8_t nr5g_fapi_fapi2mac_wls_send( } if (p_curr_msg && p_curr_msg->p_next) { - flags = WLS_SG_FIRST; + flags = WLS_SG_FIRST | flags_urllc; if (p_curr_msg->msg_type == FAPI_VENDOR_MSG_HEADER_IND) { if (SUCCESS != nr5g_fapi_fapi2mac_wls_put(p_curr_msg, p_curr_msg->msg_len + sizeof(fapi_api_queue_elem_t), @@ -331,7 +334,7 @@ uint8_t nr5g_fapi_fapi2mac_wls_send( return FAILURE; } p_curr_msg = p_curr_msg->p_next; - flags = WLS_SG_NEXT; + flags = WLS_SG_NEXT | flags_urllc; } while (p_curr_msg) { @@ -351,7 +354,7 @@ uint8_t nr5g_fapi_fapi2mac_wls_send( } p_curr_msg = p_curr_msg->p_next; } else { // LAST - flags = WLS_SG_LAST; + flags = WLS_SG_LAST | flags_urllc; if (SUCCESS != nr5g_fapi_fapi2mac_wls_put(p_curr_msg, p_curr_msg->msg_len + sizeof(fapi_api_queue_elem_t), p_msg_header->msg_id, flags)) { @@ -365,7 +368,7 @@ uint8_t nr5g_fapi_fapi2mac_wls_send( } p_curr_msg = NULL; } - flags = WLS_SG_NEXT; + flags = WLS_SG_NEXT | flags_urllc; } } @@ -400,9 +403,9 @@ p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv( uint32_t msg_size = 0; uint32_t num_elms = 0; uint64_t *p_msg = NULL; - p_fapi_api_queue_elem_t p_qelm_list = NULL; + p_fapi_api_queue_elem_t p_qelm_list = NULL, p_urllc_qelm_list = NULL; p_fapi_api_queue_elem_t p_qelm = NULL; - p_fapi_api_queue_elem_t p_tail_qelm = NULL; + p_fapi_api_queue_elem_t p_tail_qelm = NULL, p_urllc_tail_qelm = NULL; WLS_HANDLE h_wls = nr5g_fapi_fapi2mac_wls_instance(); uint64_t start_tick = 0; @@ -421,6 +424,19 @@ p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv( continue; } p_qelm->p_next = NULL; + + if (flags & WLS_TF_URLLC) + { + if (p_urllc_qelm_list) { + p_urllc_tail_qelm = p_urllc_qelm_list; + while (NULL != p_urllc_tail_qelm->p_next) { + p_urllc_tail_qelm = p_urllc_tail_qelm->p_next; + } + p_urllc_tail_qelm->p_next = p_qelm; + } else { + p_urllc_qelm_list = p_qelm; + } + } else { if (p_qelm_list) { p_tail_qelm = p_qelm_list; while (NULL != p_tail_qelm->p_next) { @@ -431,8 +447,14 @@ p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv( p_qelm_list = p_qelm; } } + } num_elms--; } while (num_elms && is_msg_present(flags)); + + if (p_urllc_qelm_list) { + nr5g_fapi_urllc_thread_callback(NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY, (void *) p_urllc_qelm_list); + } + tick_total_wls_get_per_tti_dl += __rdtsc() - start_tick; return p_qelm_list; diff --git a/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.h b/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.h index cd63248..b768f40 100644 --- a/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.h +++ b/fapi_5g/source/framework/wls/fapi2mac/nr5g_fapi_fapi2mac_wls.h @@ -32,13 +32,16 @@ uint8_t nr5g_fapi_fapi2mac_is_valid_wls_ptr( void *data); uint8_t nr5g_fapi_fapi2mac_wls_send( - p_fapi_api_queue_elem_t p_list_elem); + p_fapi_api_queue_elem_t p_list_elem, + bool is_urllc); p_fapi_api_queue_elem_t nr5g_fapi_fapi2mac_wls_recv( ); uint8_t nr5g_fapi_fapi2mac_wls_ready( ); +uint32_t nr5g_fapi_fapi2mac_wls_wait( + ); void *nr5g_fapi_fapi2mac_wls_alloc_buffer( ); diff --git a/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c b/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c index 92662e1..f9e0656 100644 --- a/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c +++ b/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.c @@ -27,12 +27,16 @@ #include "nr5g_fapi_wls.h" #include "nr5g_fapi_fapi2phy_wls.h" #include "nr5g_fapi_log.h" +#include "nr5g_fapi_urllc_thread.h" static uint32_t g_to_free_send_list_cnt[TO_FREE_SIZE] = { 0 }; static uint64_t g_to_free_send_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} }; static uint32_t g_to_free_recv_list_cnt[TO_FREE_SIZE] = { 0 }; static uint64_t g_to_free_recv_list[TO_FREE_SIZE][TOTAL_FREE_BLOCKS] = { {0L} }; +static uint32_t g_to_free_send_list_cnt_urllc[TO_FREE_SIZE_URLLC] = { 0 }; +static uint64_t g_to_free_send_list_urllc[TO_FREE_SIZE_URLLC][TOTAL_FREE_BLOCKS] = { {0L} }; + //------------------------------------------------------------------------------ /** @ingroup nr5g_fapi_source_framework_wls_fapi2phy_group * @@ -91,7 +95,7 @@ static inline WLS_HANDLE nr5g_fapi_fapi2phy_wls_instance( * **/ //---------------------------------------------------------------------------------- -static inline uint64_t *nr5g_fapi_fapi2phy_wls_get( +inline uint64_t *nr5g_fapi_fapi2phy_wls_get( uint32_t * msg_size, uint16_t * msg_type, uint16_t * flags) @@ -125,7 +129,7 @@ static inline uint64_t *nr5g_fapi_fapi2phy_wls_get( * **/ //---------------------------------------------------------------------------------- -static inline uint8_t nr5g_fapi_fapi2phy_wls_put( +inline uint8_t nr5g_fapi_fapi2phy_wls_put( uint64_t p_msg, uint32_t msg_size, uint16_t msg_type, @@ -154,7 +158,7 @@ static inline uint8_t nr5g_fapi_fapi2phy_wls_put( * **/ //---------------------------------------------------------------------------------- -static inline uint8_t nr5g_fapi_fapi2phy_wls_wait( +inline uint32_t nr5g_fapi_fapi2phy_wls_wait( ) { int ret = SUCCESS; @@ -203,9 +207,9 @@ PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv( uint32_t num_elms = 0; uint64_t *p_msg = NULL; static uint32_t g_free_recv_idx = 0; - PMAC2PHY_QUEUE_EL p_qelm_list = NULL; + PMAC2PHY_QUEUE_EL p_qelm_list = NULL, p_urllc_qelm_list = NULL; PMAC2PHY_QUEUE_EL p_qelm = NULL; - PMAC2PHY_QUEUE_EL p_tail_qelm = NULL; + PMAC2PHY_QUEUE_EL p_tail_qelm = NULL, p_urllc_tail_qelm = NULL; uint64_t start_tick = 0; num_elms = nr5g_fapi_fapi2phy_wls_wait(); @@ -225,6 +229,17 @@ PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv( continue; } p_qelm->pNext = NULL; + + if (flags & WLS_TF_URLLC) + { + if (p_urllc_qelm_list) { + p_urllc_tail_qelm->pNext = p_qelm; + p_urllc_tail_qelm = p_qelm; + } else { + p_urllc_qelm_list = p_qelm; + p_urllc_tail_qelm = p_qelm; + } + } else { if (p_qelm_list) { p_tail_qelm->pNext = p_qelm; p_tail_qelm = p_qelm; @@ -233,9 +248,24 @@ PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv( p_tail_qelm = p_qelm; } } + + } num_elms--; } while (num_elms && is_msg_present(flags)); + if (p_urllc_qelm_list) { + wls_fapi_add_recv_apis_to_free(p_urllc_qelm_list, g_free_recv_idx); + g_free_recv_idx++; + if (g_free_recv_idx >= TO_FREE_SIZE) { + g_free_recv_idx = 0; + } + // Free 10 TTIs Later + wls_fapi_free_recv_free_list(g_free_recv_idx); + + wls_fapi_add_blocks_to_ul(); + nr5g_fapi_urllc_thread_callback(NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC, (void *) p_urllc_qelm_list); + } + if (p_qelm_list) { wls_fapi_add_recv_apis_to_free(p_qelm_list, g_free_recv_idx); g_free_recv_idx++; @@ -315,6 +345,7 @@ uint32_t nr5g_fapi_fapi2phy_send_zbc_blocks( PDLPDUDataStruct p_dl_pdu_data = (PDLPDUDataStruct) (p_dl_sdu_req + 1); uint32_t i, j, is_last, is_last1, msg_type; uint16_t list_flags = flags; + uint16_t flags_urllc = (flags & WLS_TF_URLLC) ? WLS_TF_URLLC : 0; for (i = 0; i < p_dl_sdu_req->nPDU; i++) { is_last = (i == (p_dl_sdu_req->nPDU - 1)); @@ -337,9 +368,9 @@ uint32_t nr5g_fapi_fapi2phy_send_zbc_blocks( is_last1 = (((j == 0) && (p_dl_pdu_data->pPayload2 == 0)) || (j == (MAX_DL_PER_UE_CODEWORD_NUM - 1))); if ((list_flags & WLS_TF_FIN) && is_last && is_last1) { - flags = WLS_SG_LAST; + flags = WLS_SG_LAST | flags_urllc; } else { - flags = WLS_SG_NEXT; + flags = WLS_SG_NEXT | flags_urllc; } WLS_HANDLE h_phy_wls = nr5g_fapi_fapi2phy_wls_instance(); @@ -369,18 +400,22 @@ uint32_t nr5g_fapi_fapi2phy_send_zbc_blocks( **/ //------------------------------------------------------------------------------ uint8_t nr5g_fapi_fapi2phy_wls_send( - void *data) + void *data, + bool is_urllc) { p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context(); PMAC2PHY_QUEUE_EL p_curr_msg = NULL; PL1L2MessageHdr p_msg_header; uint16_t flags = 0; + uint16_t flags_urllc = (is_urllc ? WLS_TF_URLLC : 0); uint8_t ret = SUCCESS; int n_zbc_blocks = 0, is_zbc = 0, count = 0; static uint32_t g_free_send_idx = 0; + static uint32_t g_free_send_idx_urllc = 0; p_curr_msg = (PMAC2PHY_QUEUE_EL) data; - wls_fapi_add_send_apis_to_free(p_curr_msg, g_free_send_idx); + is_urllc ? wls_fapi_add_send_apis_to_free_urllc(p_curr_msg, g_free_send_idx_urllc) + : wls_fapi_add_send_apis_to_free(p_curr_msg, g_free_send_idx); if (pthread_mutex_lock((pthread_mutex_t *) & p_wls_ctx->fapi2phy_lock_send)) { NR5G_FAPI_LOG(ERROR_LOG, ("unable to lock send pthread mutex")); @@ -388,7 +423,7 @@ uint8_t nr5g_fapi_fapi2phy_wls_send( } if (p_curr_msg->pNext) { - flags = WLS_SG_FIRST; + flags = WLS_SG_FIRST | flags_urllc; while (p_curr_msg) { // only batch mode count++; @@ -419,11 +454,11 @@ uint8_t nr5g_fapi_fapi2phy_wls_send( p_curr_msg = p_curr_msg->pNext; } else { /* p_curr_msg->Next */ // LAST - flags = WLS_SG_LAST; + flags = WLS_SG_LAST | flags_urllc; is_zbc = 0; if (nr5g_fapi_fapi2phy_is_sdu_zbc_block(p_msg_header, &n_zbc_blocks)) { - flags = WLS_SG_NEXT; + flags = WLS_SG_NEXT | flags_urllc; is_zbc = 1; } if (nr5g_fapi_fapi2phy_wls_put((uint64_t) p_curr_msg, @@ -440,7 +475,7 @@ uint8_t nr5g_fapi_fapi2phy_wls_send( if (is_zbc) { // ZBC blocks if (nr5g_fapi_fapi2phy_send_zbc_blocks(p_msg_header, - WLS_SG_LAST) != SUCCESS) { + WLS_SG_LAST | flags_urllc) != SUCCESS) { printf("Error\n"); if (pthread_mutex_unlock((pthread_mutex_t *) & p_wls_ctx->fapi2phy_lock_send)) { @@ -452,7 +487,7 @@ uint8_t nr5g_fapi_fapi2phy_wls_send( } p_curr_msg = NULL; } /* p_curr_msg->Next */ - flags = WLS_SG_NEXT; + flags = WLS_SG_NEXT | flags_urllc; } } else { // one block count++; @@ -480,12 +515,19 @@ uint8_t nr5g_fapi_fapi2phy_wls_send( } if (count > 1) { + if(is_urllc) { + g_free_send_idx_urllc++; + if (g_free_send_idx_urllc >= TO_FREE_SIZE_URLLC) + g_free_send_idx_urllc = 0; + } else { g_free_send_idx++; if (g_free_send_idx >= TO_FREE_SIZE) g_free_send_idx = 0; + } - // Free 10 TTIs Later - wls_fapi_free_send_free_list(g_free_send_idx); + // Free some TTIs Later + is_urllc ? wls_fapi_free_send_free_list_urllc(g_free_send_idx_urllc) + : wls_fapi_free_send_free_list(g_free_send_idx); } if (pthread_mutex_unlock((pthread_mutex_t *) & @@ -571,8 +613,10 @@ void wls_fapi_add_recv_apis_to_free( PMAC2PHY_QUEUE_EL pNextMsg = NULL; L1L2MessageHdr *p_msg_header = NULL; PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL; - int count, i; + PULSCHPDUDataStruct p_ulsch_pdu = NULL; uint8_t *ptr = NULL; + uint32_t count; + uint8_t i; WLS_HANDLE h_wls; p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context(); @@ -592,13 +636,21 @@ void wls_fapi_add_recv_apis_to_free( p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1); if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) { p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header; - for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) { - ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload; - ptr = (uint8_t *) nr5g_fapi_wls_pa_to_va(h_wls, (uint64_t) ptr); + for (i = 0u; i < p_phy_rx_ulsch_ind->nUlsch; i++) { + p_ulsch_pdu = &(p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i]); + if(p_ulsch_pdu->nPduLen > 0) { + ptr = (uint8_t *) nr5g_fapi_wls_pa_to_va(h_wls, + (uint64_t) p_ulsch_pdu->pPayload); if (ptr) { g_to_free_recv_list[idx][count++] = (uint64_t) ptr; } + } else { + NR5G_FAPI_LOG(DEBUG_LOG, ("%s: Payload for" + "MSG_TYPE_PHY_RX_ULSCH_IND ulsch pdu (%u/%u) is NULL." + "Skip adding to free list.", + __func__, i, p_phy_rx_ulsch_ind->nUlsch)); + } } } pNextMsg = pNextMsg->pNext; @@ -666,10 +718,7 @@ void wls_fapi_add_send_apis_to_free( uint32_t idx) { PMAC2PHY_QUEUE_EL pNextMsg = NULL; - L1L2MessageHdr *p_msg_header = NULL; - PRXULSCHIndicationStruct p_phy_rx_ulsch_ind = NULL; - int count, i; - uint8_t *ptr = NULL; + uint32_t count; count = g_to_free_send_list_cnt[idx]; pNextMsg = pListElem; @@ -682,16 +731,6 @@ void wls_fapi_add_send_apis_to_free( } g_to_free_send_list[idx][count++] = (uint64_t) pNextMsg; - p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1); - if (p_msg_header->nMessageType == MSG_TYPE_PHY_RX_ULSCH_IND) { - p_phy_rx_ulsch_ind = (PRXULSCHIndicationStruct) p_msg_header; - for (i = 0; i < p_phy_rx_ulsch_ind->nUlsch; i++) { - ptr = p_phy_rx_ulsch_ind->sULSCHPDUDataStruct[i].pPayload; - if (ptr) { - g_to_free_send_list[idx][count++] = (uint64_t) ptr; - } - } - } pNextMsg = pNextMsg->pNext; } @@ -741,3 +780,84 @@ void wls_fapi_free_send_free_list( return; } + +//------------------------------------------------------------------------------ +/** @ingroup nr5g_fapi_source_framework_wls_lib_group + * + * @param[in] pListElem Pointer to List element header + * @param[in] idx Subframe Number + * + * @return Number of blocks freed + * + * @description This function Frees all the blocks in a List Element Linked + * List coming from L1 by storing them into an array to be + * freed at a later point in time. Used by urllc thread. +**/ +//------------------------------------------------------------------------------ +void wls_fapi_add_send_apis_to_free_urllc( + PMAC2PHY_QUEUE_EL pListElem, + uint32_t idx) +{ + PMAC2PHY_QUEUE_EL pNextMsg = NULL; + uint32_t count; + + count = g_to_free_send_list_cnt_urllc[idx]; + pNextMsg = pListElem; + while (pNextMsg) { + if (count >= TOTAL_FREE_BLOCKS) { + NR5G_FAPI_LOG(ERROR_LOG, ("%s: Reached max capacity of free list.\n" + "\t\t\t\tlist index: %d list count: %d max list count: %d", + __func__, idx, count, TOTAL_FREE_BLOCKS)); + return; + } + + g_to_free_send_list_urllc[idx][count++] = (uint64_t) pNextMsg; + pNextMsg = pNextMsg->pNext; + } + + g_to_free_send_list_urllc[idx][count] = 0L; + g_to_free_send_list_cnt_urllc[idx] = count; + + NR5G_FAPI_LOG(DEBUG_LOG, ("To Free %d\n", count)); +} + +//------------------------------------------------------------------------------ +/** @ingroup nr5g_fapi_source_framework_wls_lib_group + * + * @param[in] idx subframe Number + * + * @return Number of blocks freed + * + * @description This function frees all blocks that have been added to the + * free array. Used by urllc thread. +**/ +//------------------------------------------------------------------------------ +void wls_fapi_free_send_free_list_urllc( + uint32_t idx) +{ + PMAC2PHY_QUEUE_EL pNextMsg = NULL; + L1L2MessageHdr *p_msg_header = NULL; + int count = 0, loc = 0; + + if (idx >= TO_FREE_SIZE_URLLC) { + NR5G_FAPI_LOG(ERROR_LOG, ("%s: list index: %d\n", __func__, idx)); + return; + } + + pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[idx][count]; + while (pNextMsg) { + p_msg_header = (PL1L2MessageHdr) (pNextMsg + 1); + loc = get_stats_location(p_msg_header->nMessageType); + wls_fapi_free_buffer(pNextMsg, loc); + g_to_free_send_list_urllc[idx][count++] = 0L; + if (g_to_free_send_list_urllc[idx][count]) + pNextMsg = (PMAC2PHY_QUEUE_EL) g_to_free_send_list_urllc[idx][count]; + else + pNextMsg = 0L; + } + + NR5G_FAPI_LOG(DEBUG_LOG, ("Free %d\n", count)); + g_to_free_send_list_cnt_urllc[idx] = 0; + + return; +} diff --git a/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.h b/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.h index 6a57368..61b96a3 100644 --- a/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.h +++ b/fapi_5g/source/framework/wls/fapi2phy/nr5g_fapi_fapi2phy_wls.h @@ -30,14 +30,22 @@ uint8_t nr5g_fapi_fapi2phy_is_valid_wls_ptr( void *data); uint8_t nr5g_fapi_fapi2phy_wls_send( - void *data); + void *data, + bool is_urllc); PMAC2PHY_QUEUE_EL nr5g_fapi_fapi2phy_wls_recv( ); +inline uint32_t nr5g_fapi_fapi2phy_wls_wait( + ); void wls_fapi_add_send_apis_to_free( PMAC2PHY_QUEUE_EL pListElem, uint32_t idx); void wls_fapi_free_send_free_list( uint32_t idx); +void wls_fapi_add_send_apis_to_free_urllc( + PMAC2PHY_QUEUE_EL pListElem, + uint32_t idx); +void wls_fapi_free_send_free_list_urllc( + uint32_t idx); void wls_fapi_add_recv_apis_to_free( PMAC2PHY_QUEUE_EL pListElem, uint32_t idx); diff --git a/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.c b/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.c index 2370511..16890e0 100644 --- a/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.c +++ b/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.c @@ -28,6 +28,8 @@ #include "nr5g_fapi_log.h" #include "nr5g_fapi_memory.h" +#define WLS_HUGE_DEF_PAGE_SIZEA 0x40000000LL + nr5g_fapi_wls_context_t g_wls_ctx; static uint8_t alloc_track[ALLOC_TRACK_SIZE]; @@ -226,10 +228,10 @@ void *nr5g_fapi_wls_pa_to_va( * **/ //------------------------------------------------------------------------------ -uint8_t wls_fapi_add_blocks_to_ul( +uint32_t wls_fapi_add_blocks_to_ul( void) { - int num_blocks = 0; + uint32_t num_blocks = 0; p_nr5g_fapi_wls_context_t pWls = nr5g_fapi_wls_context(); WLS_HANDLE h_wls = pWls->h_wls[NR5G_FAPI2PHY_WLS_INST]; @@ -268,8 +270,10 @@ uint8_t wls_fapi_add_blocks_to_ul( uint8_t nr5g_fapi_wls_init( p_nr5g_fapi_cfg_t cfg) { + uint64_t mac_shmem_size = 0; + uint64_t phy_shmem_size = 0; + p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context(); - const char *dev_name = "wls0"; if (p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST] && p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST]) { @@ -277,10 +281,12 @@ uint8_t nr5g_fapi_wls_init( return FAILURE; } - p_wls_ctx->shmem_size = cfg->wls.shmem_size; p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST] = - WLS_Open_Dual(dev_name, WLS_SLAVE_CLIENT, - cfg->wls.shmem_size, &p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]); + WLS_Open_Dual(basename(cfg->wls.device_name), WLS_SLAVE_CLIENT, + &mac_shmem_size, &phy_shmem_size, &p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]); + + cfg->wls.shmem_size = mac_shmem_size + phy_shmem_size; + p_wls_ctx->shmem_size = cfg->wls.shmem_size; if ((NULL == p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]) && (NULL == p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST])) { NR5G_FAPI_LOG(ERROR_LOG, ("[NR5G_FAPI_ WLS] WLS Open Dual Failed.")); @@ -298,7 +304,7 @@ uint8_t nr5g_fapi_wls_init( p_wls_ctx->shmem = WLS_Alloc(p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST], p_wls_ctx->shmem_size); p_wls_ctx->pWlsMemBase = p_wls_ctx->shmem; - p_wls_ctx->nTotalMemorySize = p_wls_ctx->shmem_size; + p_wls_ctx->nTotalMemorySize = mac_shmem_size; if (NULL == p_wls_ctx->shmem) { printf("Unable to alloc WLS Memory\n"); return FAILURE; @@ -420,16 +426,34 @@ uint32_t wls_fapi_create_mem_array( uint8_t wls_fapi_create_partition( p_nr5g_fapi_wls_context_t pWls) { -#define WLS_HUGE_DEF_PAGE_SIZEA 0x40000000LL - static long hugePageSize = WLS_HUGE_DEF_PAGE_SIZEA; - // NR5G_FAPI_MEMSET(pWls->pWlsMemBase , 0xCC, pWls->nTotalMemorySize); // This is done by the Master Only - pWls->pPartitionMemBase = - (void *)(((uint8_t *) pWls->pWlsMemBase) + hugePageSize); - pWls->nPartitionMemSize = (pWls->nTotalMemorySize - hugePageSize); - - pWls->nTotalBlocks = pWls->nPartitionMemSize / MSG_MAXSIZE; + uint64_t nWlsMemBaseUsable; + uint64_t nTotalMemorySizeUsable; + uint64_t nBalance, nBlockSize, nBlockSizeMask, nHugepageSizeMask; + + nBlockSize = MSG_MAXSIZE; + nWlsMemBaseUsable = (uint64_t)pWls->pWlsMemBase; + nTotalMemorySizeUsable = pWls->nTotalMemorySize - WLS_HUGE_DEF_PAGE_SIZEA; + nBlockSizeMask = nBlockSize-1; + + // Align Starting Location + nWlsMemBaseUsable = (nWlsMemBaseUsable + nBlockSizeMask) & (~nBlockSizeMask); + nBalance = nWlsMemBaseUsable - (uint64_t)pWls->pWlsMemBase; + nTotalMemorySizeUsable -= nBalance; + + // Align Ending Location + nBalance = nTotalMemorySizeUsable % nBlockSize; + nTotalMemorySizeUsable -= nBalance; + + // Move start location to the next hugepage boundary + nHugepageSizeMask = WLS_HUGE_DEF_PAGE_SIZEA-1; + nWlsMemBaseUsable = (nWlsMemBaseUsable + WLS_HUGE_DEF_PAGE_SIZEA) & (~nHugepageSizeMask); + + + pWls->pPartitionMemBase = (void *)nWlsMemBaseUsable; + pWls->nPartitionMemSize = nTotalMemorySizeUsable; + pWls->nTotalBlocks = pWls->nPartitionMemSize / nBlockSize; return wls_fapi_create_mem_array(&pWls->sWlsStruct, pWls->pPartitionMemBase, - pWls->nPartitionMemSize, MSG_MAXSIZE); + pWls->nPartitionMemSize, nBlockSize); } //------------------------------------------------------------------------------ @@ -702,7 +726,7 @@ void wls_fapi_free_buffer( uint8_t nr5g_fapi_wls_memory_init( ) { - int nBlocks = 0; + uint32_t nBlocks = 0; p_nr5g_fapi_wls_context_t p_wls = nr5g_fapi_wls_context(); if (FAILURE == wls_fapi_create_partition(p_wls)) diff --git a/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.h b/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.h index e98455b..c34052c 100644 --- a/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.h +++ b/fapi_5g/source/framework/wls/lib/nr5g_fapi_wls.h @@ -43,8 +43,9 @@ typedef void *WLS_HANDLE; #define MIN_UL_BUF_LOCATIONS (MAX_DL_BUF_LOCATIONS) /* Used for stats collection 0-10 */ #define MAX_UL_BUF_LOCATIONS (MIN_UL_BUF_LOCATIONS + MAX_NUM_LOCATIONS) -#define TO_FREE_SIZE ( 10 ) -#define TOTAL_FREE_BLOCKS ( 50 * FAPI_MAX_PHY_INSTANCES) /* To hold both send and recv blocks on PHY side wls */ +#define TO_FREE_SIZE ( 5 ) +#define TO_FREE_SIZE_URLLC ( MAX_NUM_OF_SYMBOL_PER_SLOT * TO_FREE_SIZE ) // TR 38.912 8.1 mini-slot may be 1 symbol long +#define TOTAL_FREE_BLOCKS ( 100 * FAPI_MAX_PHY_INSTANCES) /* To hold both send and recv blocks on PHY side wls */ #define ALLOC_TRACK_SIZE ( 16384 ) #define MSG_MAXSIZE (16*16384 ) @@ -92,11 +93,11 @@ typedef struct _nr5g_fapi_wls_context { extern nr5g_fapi_wls_context_t g_wls_ctx; -p_nr5g_fapi_wls_context_t nr5g_fapi_wls_context( +inline p_nr5g_fapi_wls_context_t nr5g_fapi_wls_context( ); -uint8_t nr5g_fapi_fapi2phy_wls_ready( +inline uint8_t nr5g_fapi_fapi2phy_wls_ready( ); -uint8_t nr5g_fapi_fapi2mac_wls_ready( +inline uint8_t nr5g_fapi_fapi2mac_wls_ready( ); uint8_t nr5g_fapi_wls_init( ); @@ -127,7 +128,7 @@ uint64_t nr5g_fapi_wls_va_to_pa( void *nr5g_fapi_wls_pa_to_va( WLS_HANDLE h_wls, uint64_t ptr); -uint8_t wls_fapi_add_blocks_to_ul( +uint32_t wls_fapi_add_blocks_to_ul( void); void nr5g_fapi_wls_show_data( void *ptr, diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.c b/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.c index 41c29c7..dc98de3 100644 --- a/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.c +++ b/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.c @@ -42,6 +42,7 @@ void *nr5g_fapi_mac2phy_thread_func( pthread_t thread; p_fapi_api_queue_elem_t p_msg_list = NULL; p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config; + uint64_t start_tick; NR5G_FAPI_LOG(INFO_LOG, ("[MAC2PHY] Thread %s launched LWP:%ld on " "Core: %d\n", __func__, pthread_self(), @@ -56,7 +57,12 @@ void *nr5g_fapi_mac2phy_thread_func( while (!p_phy_ctx->process_exit) { p_msg_list = nr5g_fapi_fapi2mac_wls_recv(); if (p_msg_list) - nr5g_fapi_mac2phy_api_recv_handler(config, p_msg_list); + nr5g_fapi_mac2phy_api_recv_handler(false, config, p_msg_list); + + start_tick = __rdtsc(); + NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY..")); + nr5g_fapi_fapi2phy_send_api_list(0); + tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick; } pthread_exit(NULL); } @@ -74,6 +80,7 @@ void *nr5g_fapi_mac2phy_thread_func( **/ //------------------------------------------------------------------------------ void nr5g_fapi_mac2phy_api_recv_handler( + bool is_urllc, void *config, p_fapi_api_queue_elem_t p_msg_list) { @@ -99,18 +106,18 @@ void nr5g_fapi_mac2phy_api_recv_handler( if (num_apis > 0 && p_msg_list->p_next) { // likely p_per_carr_api_list = p_per_carr_api_list->p_next; p_msg_list = p_per_carr_api_list; - NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] PHY_ID: %d NUM APIs: %d\n", + NR5G_FAPI_LOG(TRACE_LOG, ("\n[MAC2PHY] PHY_ID: %d NUM APIs: %d\n", phy_id, num_apis)); } else { // unlikely // skip to next carrier list. since current fapi message hearder // has no apis if (p_msg_list->p_next) { - NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] No APIs for PHY_ID: %d." + NR5G_FAPI_LOG(TRACE_LOG, ("\n[MAC2PHY] No APIs for PHY_ID: %d." " Skip...\n", phy_id)); p_msg_list = p_msg_list->p_next; continue; } else { - NR5G_FAPI_LOG(ERROR_LOG, ("[MAC2PHY] PHY_ID: %d NUM APIs: %d\n", + NR5G_FAPI_LOG(ERROR_LOG, ("\n[MAC2PHY] PHY_ID: %d NUM APIs: %d\n", phy_id, num_apis)); return; } @@ -140,7 +147,8 @@ void nr5g_fapi_mac2phy_api_recv_handler( if (p_per_carr_api_list) { p_fapi_msg = (fapi_msg_t *) (p_per_carr_api_list + 1); #ifdef DEBUG_MODE - if ((p_fapi_msg->msg_id != FAPI_VENDOR_EXT_UL_IQ_SAMPLES)) { + if ((p_fapi_msg->msg_id != FAPI_VENDOR_EXT_UL_IQ_SAMPLES) && + (p_fapi_msg->msg_id != FAPI_VENDOR_EXT_ADD_REMOVE_CORE)) { #endif p_phy_instance = &p_phy_ctx->phy_instance[phy_id]; if (FAPI_STATE_IDLE == p_phy_instance->state) { @@ -155,18 +163,13 @@ void nr5g_fapi_mac2phy_api_recv_handler( #ifdef DEBUG_MODE } #endif - nr5g_fapi_mac2phy_api_processing_handler(p_phy_instance, + + nr5g_fapi_mac2phy_api_processing_handler(is_urllc, p_phy_instance, p_per_carr_api_list); p_per_carr_api_list = NULL; } } tick_total_parse_per_tti_dl += __rdtsc() - start_tick; - start_tick = __rdtsc(); - - // Send to PHY - NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY..")); - nr5g_fapi_fapi2phy_send_api_list(); - tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick; } //------------------------------------------------------------------------------ @@ -182,6 +185,7 @@ void nr5g_fapi_mac2phy_api_recv_handler( **/ //------------------------------------------------------------------------------ void nr5g_fapi_mac2phy_api_processing_handler( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, p_fapi_api_queue_elem_t p_msg_list) { @@ -206,7 +210,7 @@ void nr5g_fapi_mac2phy_api_processing_handler( return; } p_vendor_msg = (fapi_vendor_msg_t *) p_fapi_msg; - NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Vendor Msg: %p\n", + NR5G_FAPI_LOG(DEBUG_LOG, ("[MAC2PHY] P7 Vendor Msg: %p", p_vendor_msg)); // disconnect the vendor element from the api list p_prev_elm->p_next = NULL; @@ -249,20 +253,24 @@ void nr5g_fapi_mac2phy_api_processing_handler( switch (p_fapi_msg->msg_id) { /* P5 Vendor Message Processing */ #ifdef DEBUG_MODE + case FAPI_VENDOR_EXT_ADD_REMOVE_CORE: + nr5g_fapi_add_remove_core_message(is_urllc, + (fapi_vendor_ext_add_remove_core_msg_t *) p_fapi_msg); + break; case FAPI_VENDOR_EXT_UL_IQ_SAMPLES: - nr5g_fapi_ul_iq_samples_request( + nr5g_fapi_ul_iq_samples_request(is_urllc, (fapi_vendor_ext_iq_samples_req_t *) p_fapi_msg); break; case FAPI_VENDOR_EXT_DL_IQ_SAMPLES: - nr5g_fapi_dl_iq_samples_request( + nr5g_fapi_dl_iq_samples_request(is_urllc, (fapi_vendor_ext_iq_samples_req_t *) p_fapi_msg); break; #endif case FAPI_VENDOR_EXT_SHUTDOWN_REQUEST: { - nr5g_fapi_shutdown_request(p_phy_instance, + nr5g_fapi_shutdown_request(is_urllc, p_phy_instance, (fapi_vendor_ext_shutdown_req_t *) p_fapi_msg); nr5g_fapi_statistic_info_print(); if (g_statistic_start_flag == 1) @@ -273,7 +281,7 @@ void nr5g_fapi_mac2phy_api_processing_handler( /* P5 Message Processing */ case FAPI_CONFIG_REQUEST: { - nr5g_fapi_config_request(p_phy_instance, + nr5g_fapi_config_request(is_urllc, p_phy_instance, (fapi_config_req_t *) p_fapi_msg, p_vendor_msg); nr5g_fapi_statistic_info_init(); @@ -282,13 +290,13 @@ void nr5g_fapi_mac2phy_api_processing_handler( break; case FAPI_START_REQUEST: - nr5g_fapi_start_request(p_phy_instance, (fapi_start_req_t *) + nr5g_fapi_start_request(is_urllc, p_phy_instance, (fapi_start_req_t *) p_fapi_msg, p_vendor_msg); break; case FAPI_STOP_REQUEST: { - nr5g_fapi_stop_request(p_phy_instance, (fapi_stop_req_t *) + nr5g_fapi_stop_request(is_urllc, p_phy_instance, (fapi_stop_req_t *) p_fapi_msg, p_vendor_msg); nr5g_fapi_statistic_info_print(); if (g_statistic_start_flag == 1) @@ -299,7 +307,7 @@ void nr5g_fapi_mac2phy_api_processing_handler( /* P7 Message Processing */ case FAPI_DL_TTI_REQUEST: { - nr5g_fapi_dl_tti_request(p_phy_instance, + nr5g_fapi_dl_tti_request(is_urllc, p_phy_instance, (fapi_dl_tti_req_t *) p_fapi_msg, p_vendor_msg); if (g_statistic_start_flag == 0) @@ -308,22 +316,24 @@ void nr5g_fapi_mac2phy_api_processing_handler( break; case FAPI_UL_TTI_REQUEST: - nr5g_fapi_ul_tti_request(p_phy_instance, (fapi_ul_tti_req_t *) + nr5g_fapi_ul_tti_request(is_urllc, p_phy_instance, (fapi_ul_tti_req_t *) p_fapi_msg, p_vendor_msg); break; case FAPI_UL_DCI_REQUEST: - nr5g_fapi_ul_dci_request(p_phy_instance, (fapi_ul_dci_req_t *) + nr5g_fapi_ul_dci_request(is_urllc, p_phy_instance, (fapi_ul_dci_req_t *) p_fapi_msg, p_vendor_msg); break; case FAPI_TX_DATA_REQUEST: - nr5g_fapi_tx_data_request(p_phy_instance, (fapi_tx_data_req_t *) + nr5g_fapi_tx_data_request(is_urllc, p_phy_instance, (fapi_tx_data_req_t *) p_fapi_msg, p_vendor_msg); p_msg_list->p_tx_data_elm_list = NULL; break; default: + NR5G_FAPI_LOG(ERROR_LOG, ("[MAC2PHY THREAD] Received Unknown Message: [msg_id = 0x%x]", + p_fapi_msg->msg_id)); break; } p_msg_list = p_msg_list->p_next; diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.h b/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.h index 29833c1..7352abf 100644 --- a/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.h +++ b/fapi_5g/source/framework/workers/nr5g_fapi_mac2phy_thread.h @@ -23,10 +23,12 @@ #include "fapi_vendor_extension.h" void nr5g_fapi_mac2phy_api_recv_handler( + bool is_urllc, void *config, p_fapi_api_queue_elem_t p_msg_list); void nr5g_fapi_mac2phy_api_processing_handler( + bool is_urllc, p_nr5g_fapi_phy_instance_t p_phy_instance, p_fapi_api_queue_elem_t p_msg_list); diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.c b/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.c index c663767..46d7bb8 100644 --- a/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.c +++ b/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.c @@ -57,9 +57,9 @@ void *nr5g_fapi_phy2mac_thread_func( while (!p_phy_ctx->process_exit) { p_msg_list = nr5g_fapi_fapi2phy_wls_recv(); if (p_msg_list) - nr5g_fapi_phy2mac_api_recv_handler(config, p_msg_list); + nr5g_fapi_phy2mac_api_recv_handler(false, config, p_msg_list); - nr5g_fapi_fapi2mac_send_api_list(); + nr5g_fapi_fapi2mac_send_api_list(false); } pthread_exit(NULL); } @@ -77,16 +77,18 @@ void *nr5g_fapi_phy2mac_thread_func( **/ //------------------------------------------------------------------------------ void nr5g_fapi_phy2mac_api_recv_handler( + bool is_urllc, void *config, PMAC2PHY_QUEUE_EL p_msg_list) { PMAC2PHY_QUEUE_EL p_curr_msg; PL1L2MessageHdr p_msg_header = NULL; uint64_t start_tick = __rdtsc(); - + fapi_api_stored_vendor_queue_elems vendor_extension_elems; NR5G_FAPI_LOG(TRACE_LOG, ("[PHY2MAC] %s:", __func__)); - nr5g_fapi_message_header((p_nr5g_fapi_phy_ctx_t) config); + memset(&vendor_extension_elems, 0, sizeof(vendor_extension_elems)); + nr5g_fapi_message_header((p_nr5g_fapi_phy_ctx_t) config, is_urllc); p_curr_msg = (PMAC2PHY_QUEUE_EL) p_msg_list; while (p_curr_msg) { @@ -140,48 +142,61 @@ void nr5g_fapi_phy2mac_api_recv_handler( /* P7 Message Processing */ case MSG_TYPE_PHY_RX_ULSCH_IND: { - nr5g_fapi_rx_data_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_rx_data_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + &vendor_extension_elems, (PRXULSCHIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_RX_ULSCH_UCI_IND: { - //Not Supported + nr5g_fapi_rx_data_uci_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + (PRXULSCHUCIIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_CRC_IND: { - nr5g_fapi_crc_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_crc_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + &vendor_extension_elems, (PCRCIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_UCI_IND: { - nr5g_fapi_uci_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_uci_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + &vendor_extension_elems, (PRXUCIIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_RX_RACH_IND: { - nr5g_fapi_rach_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_rach_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, (PRXRACHIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_RX_SRS_IND: { - nr5g_fapi_srs_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_srs_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + &vendor_extension_elems, (PRXSRSIndicationStruct) p_msg_header); } break; case MSG_TYPE_PHY_SLOT_IND: { - nr5g_fapi_slot_indication((p_nr5g_fapi_phy_ctx_t) config, + nr5g_fapi_slot_indication(is_urllc, + (p_nr5g_fapi_phy_ctx_t) config, + &vendor_extension_elems, (PSlotIndicationStruct) p_msg_header); nr5g_fapi_statistic_info_set_all(); } @@ -193,12 +208,14 @@ void nr5g_fapi_phy2mac_api_recv_handler( break; default: - printf("%s: Unknown Message type: %x\n", __func__, - p_msg_header->nMessageType); + NR5G_FAPI_LOG(ERROR_LOG, ("[PHY2MAC THREAD] Received Unknown Message: [nMessageType = 0x%x]", + p_msg_header->nMessageType)); break; } p_curr_msg = p_curr_msg->pNext; } + nr5g_fapi_proc_vendor_p7_msgs_move_to_api_list(is_urllc, &vendor_extension_elems); + tick_total_parse_per_tti_ul += __rdtsc() - start_tick; } diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.h b/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.h index 79e20b3..30f5fc4 100644 --- a/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.h +++ b/fapi_5g/source/framework/workers/nr5g_fapi_phy2mac_thread.h @@ -21,6 +21,7 @@ #include "gnb_l1_l2_api.h" void nr5g_fapi_phy2mac_api_recv_handler( + bool is_urllc, void *config, PMAC2PHY_QUEUE_EL p_msg_list); diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.c b/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.c new file mode 100644 index 0000000..ee83d7a --- /dev/null +++ b/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.c @@ -0,0 +1,92 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ +#include "nr5g_fapi_std.h" +#include "nr5g_fapi_framework.h" +#include "nr5g_fapi_urllc_thread.h" +#include "nr5g_fapi_phy2mac_thread.h" +#include "nr5g_fapi_mac2phy_thread.h" +#include "nr5g_fapi_fapi2mac_api.h" +#include "nr5g_fapi_fapi2phy_api.h" + +static nr5g_fapi_urllc_msg_dir_t urllc_msg_dir = NR5G_FAPI_URLLC_MSG_DIR_LAST; +static void *p_urllc_list_elem = NULL; +static pthread_mutex_t lock = PTHREAD_MUTEX_INITIALIZER; + +void nr5g_fapi_urllc_thread_callback( + nr5g_fapi_urllc_msg_dir_t msg_dir, + void *p_list_elem) +{ + p_nr5g_fapi_phy_ctx_t p_phy_ctx = nr5g_fapi_get_nr5g_fapi_phy_ctx(); + sem_wait(&p_phy_ctx->urllc_sem_done); + pthread_mutex_lock(&lock); + p_urllc_list_elem = p_list_elem; + urllc_msg_dir = msg_dir; + pthread_mutex_unlock(&lock); + sem_post(&p_phy_ctx->urllc_sem_process); +} + +void *nr5g_fapi_urllc_thread_func( + void *config) +{ + cpu_set_t cpuset; + pthread_t thread; + p_nr5g_fapi_phy_ctx_t p_phy_ctx = (p_nr5g_fapi_phy_ctx_t) config; + uint64_t start_tick; + + NR5G_FAPI_LOG(INFO_LOG, ("[URLLC] Thread %s launched LWP:%ld on " + "Core: %d\n", __func__, pthread_self(), + p_phy_ctx->urllc_worker_core_id)); + + thread = p_phy_ctx->urllc_tid = pthread_self(); + + CPU_ZERO(&cpuset); + CPU_SET(p_phy_ctx->urllc_worker_core_id, &cpuset); + pthread_setaffinity_np(thread, sizeof(cpu_set_t), &cpuset); + + usleep(1000); + while (!p_phy_ctx->process_exit) { + sem_wait(&p_phy_ctx->urllc_sem_process); + pthread_mutex_lock(&lock); + if (p_urllc_list_elem) + { + switch (urllc_msg_dir) { + case NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY: + nr5g_fapi_mac2phy_api_recv_handler(true, config, (p_fapi_api_queue_elem_t) p_urllc_list_elem); + start_tick = __rdtsc(); + NR5G_FAPI_LOG(TRACE_LOG, ("[MAC2PHY] Send to PHY urllc..")); + nr5g_fapi_fapi2phy_send_api_list(true); + tick_total_wls_send_per_tti_dl += __rdtsc() - start_tick; + break; + case NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC: + nr5g_fapi_phy2mac_api_recv_handler(true, config, (PMAC2PHY_QUEUE_EL) p_urllc_list_elem); + nr5g_fapi_fapi2mac_send_api_list(true); + break; + default: + NR5G_FAPI_LOG(ERROR_LOG, ("[URLLC]: Invalid URLLC message direction.\n")); + break; + } + + p_urllc_list_elem = NULL; + urllc_msg_dir = NR5G_FAPI_URLLC_MSG_DIR_LAST; + } + pthread_mutex_unlock(&lock); + sem_post(&p_phy_ctx->urllc_sem_done); + } + + pthread_exit(NULL); +} diff --git a/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.h b/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.h new file mode 100644 index 0000000..a3076bf --- /dev/null +++ b/fapi_5g/source/framework/workers/nr5g_fapi_urllc_thread.h @@ -0,0 +1,33 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ +#ifndef _NR5G_FAPI_URLLC_THREAD_H_ +#define _NR5G_FAPI_URLLC_THREAD_H_ + +#include "gnb_l1_l2_api.h" + +typedef enum nr5g_fapi_urllc_msg_dir_e { + NR5G_FAPI_URLLC_MSG_DIR_MAC2PHY = 0, + NR5G_FAPI_URLLC_MSG_DIR_PHY2MAC, + NR5G_FAPI_URLLC_MSG_DIR_LAST +} nr5g_fapi_urllc_msg_dir_t; + +void nr5g_fapi_urllc_thread_callback( + nr5g_fapi_urllc_msg_dir_t msg_dir, + void *p_list_elem); + +#endif diff --git a/fapi_5g/source/include/nr5g_fapi_config_loader.h b/fapi_5g/source/include/nr5g_fapi_config_loader.h index ead9ffb..af97e60 100644 --- a/fapi_5g/source/include/nr5g_fapi_config_loader.h +++ b/fapi_5g/source/include/nr5g_fapi_config_loader.h @@ -30,6 +30,7 @@ #include "nr5g_fapi_log.h" #define NR5G_FAPI_DEVICE_NAME_LEN 512 +#define NR5G_FAPI_MEMORY_ZONE_NAME_LEN 512 enum { DPDK_IOVA_PA_MODE = 0, @@ -55,6 +56,7 @@ typedef struct _nr5g_fapi_config_wls_cfg { typedef struct nr5g_fapi_config_dpdk_cfg_t { uint8_t iova_mode; /*0 - PA mode, 1 - VA mode */ + char memory_zone[NR5G_FAPI_MEMORY_ZONE_NAME_LEN]; } nr5g_fapi_config_dpdk_cft_t; typedef struct _nr5g_fapi_config_log_cfg { @@ -70,6 +72,7 @@ typedef struct _nr5g_fapi_cfg { nr5g_fapi_config_log_cfg_t logger; nr5g_fapi_thread_info_t mac2phy_thread_info; nr5g_fapi_thread_info_t phy2mac_thread_info; + nr5g_fapi_thread_info_t urllc_thread_info; nr5g_fapi_config_dpdk_cft_t dpdk; } nr5g_fapi_cfg_t, *p_nr5g_fapi_cfg_t; diff --git a/fapi_5g/source/include/nr5g_fapi_framework.h b/fapi_5g/source/include/nr5g_fapi_framework.h index c33a28b..63cb237 100644 --- a/fapi_5g/source/include/nr5g_fapi_framework.h +++ b/fapi_5g/source/include/nr5g_fapi_framework.h @@ -34,9 +34,11 @@ // FAPI CONFIG.request parameters typedef struct _nr5g_fapi_phy_config { - uint8_t n_nr_of_rx_ant; uint16_t phy_cell_id; - uint8_t nSSBPrbOffset; + uint8_t n_nr_of_rx_ant; + uint8_t use_vendor_EpreXSSB; + uint8_t sub_c_common; + uint8_t pad[3]; } nr5g_fapi_phy_config_t, *pnr5g_fapi_phy_config_t; @@ -64,6 +66,7 @@ typedef struct _nr5g_fapi_ul_slot_info { uint16_t cookie; //set this to frame_no at UL_TTI.Request and compare the //same during uplink indications. uint8_t slot_no; + uint8_t symbol_no; uint8_t num_ulsch; uint8_t num_ulcch; uint8_t num_srs; @@ -179,7 +182,7 @@ typedef struct _nr5g_fapi_phy_instance { nr5g_fapi_phy_config_t phy_config; // place holder to store, // parameters from config request nr5g_fapi_stats_t stats; - nr5g_fapi_ul_slot_info_t ul_slot_info[MAX_UL_SLOT_INFO_COUNT]; + nr5g_fapi_ul_slot_info_t ul_slot_info[FAPI_MAX_SLOT_INFO_URLLC][MAX_UL_SLOT_INFO_COUNT][MAX_UL_SYMBOL_INFO_COUNT]; } nr5g_fapi_phy_instance_t, *p_nr5g_fapi_phy_instance_t; @@ -188,15 +191,19 @@ typedef struct _nr5g_fapi_phy_context { uint8_t num_phy_instance; uint8_t mac2phy_worker_core_id; uint8_t phy2mac_worker_core_id; + uint8_t urllc_worker_core_id; pthread_t phy2mac_tid; pthread_t mac2phy_tid; + pthread_t urllc_tid; + sem_t urllc_sem_process; + sem_t urllc_sem_done; volatile uint64_t process_exit; nr5g_fapi_phy_instance_t phy_instance[FAPI_MAX_PHY_INSTANCES]; } nr5g_fapi_phy_ctx_t, *p_nr5g_fapi_phy_ctx_t; // Function Declarations -p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx( +inline p_nr5g_fapi_phy_ctx_t nr5g_fapi_get_nr5g_fapi_phy_ctx( ); uint8_t nr5g_fapi_framework_init( ); @@ -212,12 +219,17 @@ void *nr5g_fapi_phy2mac_thread_func( void *config); void *nr5g_fapi_mac2phy_thread_func( void *config); +void *nr5g_fapi_urllc_thread_func( + void *config); nr5g_fapi_ul_slot_info_t *nr5g_fapi_get_ul_slot_info( + bool is_urllc, uint16_t frame_no, - uint8_t slot_no, + uint16_t slot_no, + uint8_t symbol_no, p_nr5g_fapi_phy_instance_t p_phy_instance); void nr5g_fapi_set_ul_slot_info( uint16_t frame_no, - uint8_t slot_no, + uint16_t slot_no, + uint8_t symbol_no, nr5g_fapi_ul_slot_info_t * p_ul_slot_info); #endif // _NR5G_FAPI_FRAMEWORK_H_ diff --git a/fapi_5g/source/include/nr5g_fapi_internal.h b/fapi_5g/source/include/nr5g_fapi_internal.h index 6a1f42b..a1d72c2 100644 --- a/fapi_5g/source/include/nr5g_fapi_internal.h +++ b/fapi_5g/source/include/nr5g_fapi_internal.h @@ -27,12 +27,15 @@ #include "fapi_interface.h" #include "nr5g_fapi_common_types.h" -#define MAX_UL_SLOT_INFO_COUNT 10 //Maximum no of Slots for which UL_TTI.request info has to +#define MAX_UL_SLOT_INFO_COUNT 20 //Maximum no of Slots for which UL_TTI.request info has to +#define MAX_UL_SYMBOL_INFO_COUNT FAPI_MAX_NR_OF_SYMBOLS +//Maximum no of symbols which may be configured with separate UL_TTI.request (URLLC) #define FAPI_MAX_NUM_PUSCH_PDU 255 //as per Table 3-44 #define FAPI_MAX_NUM_PUCCH_PDU 255 //as per Table 3-44 #define FAPI_MAX_NUM_SRS_PDU 255 //as per Table 3-73 #define FAPI_MAX_NUM_RACH_PDU 255 //as per Table 3-74 -#define FAPI_MAX_PHY_INSTANCES 12 +#define FAPI_MAX_PHY_INSTANCES 24 +#define FAPI_MAX_SLOT_INFO_URLLC 2 // CONFIGURATION INFORMATION CARRIER CONFIGURATION BANDWIDTH #define FAPI_BANDWIDTH_5_MHZ 5 diff --git a/fapi_5g/source/include/nr5g_fapi_log.h b/fapi_5g/source/include/nr5g_fapi_log.h index 678648d..bc6901e 100644 --- a/fapi_5g/source/include/nr5g_fapi_log.h +++ b/fapi_5g/source/include/nr5g_fapi_log.h @@ -24,6 +24,8 @@ #ifndef NR5G_FAPI_LOG_H_ #define NR5G_FAPI_LOG_H_ +#include + #define NR5G_FAPI_STATS_FNAME "FapiStats.txt" typedef enum _nr5g_fapi_log_types_t { diff --git a/fapi_5g/source/include/nr5g_fapi_memory.h b/fapi_5g/source/include/nr5g_fapi_memory.h index 2d5713c..0b877df 100644 --- a/fapi_5g/source/include/nr5g_fapi_memory.h +++ b/fapi_5g/source/include/nr5g_fapi_memory.h @@ -28,17 +28,17 @@ #define NR5G_FAPI_MEMSET(s, x, c, n) nr5g_fapi_memset_bound_check(s, x, c, n) #define NR5G_FAPI_STRCPY(d, x, s, n) nr5g_fapi_strcpy_bound_check(d, x, s, n) -uint8_t nr5g_fapi_memcpy_bound_check( +inline uint8_t nr5g_fapi_memcpy_bound_check( void *d, size_t x, const void *s, size_t n); -uint8_t nr5g_fapi_memset_bound_check( +inline uint8_t nr5g_fapi_memset_bound_check( void *s, size_t x, const int32_t c, size_t n); -uint8_t nr5g_fapi_strcpy_bound_check( +inline uint8_t nr5g_fapi_strcpy_bound_check( char *d, size_t x, const char *s, diff --git a/fapi_5g/source/include/nr5g_fapi_snr_conversion.h b/fapi_5g/source/include/nr5g_fapi_snr_conversion.h new file mode 100644 index 0000000..95ebac9 --- /dev/null +++ b/fapi_5g/source/include/nr5g_fapi_snr_conversion.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @file This file consist of SNR converter from IntelAPI to FAPI. + * + **/ + +#ifndef NR5G_FAPI_SNR_CONVERSION_H_ +#define NR5G_FAPI_SNR_CONVERSION_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +uint8_t nr5g_fapi_convert_snr_iapi_to_fapi(const int16_t snr); + +#ifdef __cplusplus +} +#endif + +#endif // NR5G_FAPI_SNR_CONVERSION_H_ diff --git a/fapi_5g/source/include/nr5g_fapi_stats.h b/fapi_5g/source/include/nr5g_fapi_stats.h index 471c6f8..41e0516 100644 --- a/fapi_5g/source/include/nr5g_fapi_stats.h +++ b/fapi_5g/source/include/nr5g_fapi_stats.h @@ -32,9 +32,9 @@ void nr5g_fapi_print_phy_instance_stats( p_nr5g_fapi_phy_instance_t p_phy_instance); -int nr5g_fapi_check_for_file_link( +inline int nr5g_fapi_check_for_file_link( char *fname); -int nr5g_fapi_change_file_permission( +inline int nr5g_fapi_change_file_permission( int fd, mode_t mode); diff --git a/fapi_5g/source/include/nr5g_fapi_std.h b/fapi_5g/source/include/nr5g_fapi_std.h index c4ac117..a93b154 100644 --- a/fapi_5g/source/include/nr5g_fapi_std.h +++ b/fapi_5g/source/include/nr5g_fapi_std.h @@ -31,6 +31,7 @@ #include #include #include -//#include +#include +#include #endif diff --git a/fapi_5g/source/nr5g_fapi.c b/fapi_5g/source/nr5g_fapi.c index bfcb606..78133e3 100644 --- a/fapi_5g/source/nr5g_fapi.c +++ b/fapi_5g/source/nr5g_fapi.c @@ -54,6 +54,7 @@ int main( nr5g_fapi_dpdk_wait(config); pthread_attr_destroy(&config->phy2mac_thread_info.thread_attr); pthread_attr_destroy(&config->mac2phy_thread_info.thread_attr); + pthread_attr_destroy(&config->urllc_thread_info.thread_attr); free(config); return 0; } diff --git a/fapi_5g/source/utils/nr5g_fapi_config_loader.c b/fapi_5g/source/utils/nr5g_fapi_config_loader.c index a6fa6bd..e79b602 100644 --- a/fapi_5g/source/utils/nr5g_fapi_config_loader.c +++ b/fapi_5g/source/utils/nr5g_fapi_config_loader.c @@ -32,7 +32,7 @@ p_nr5g_fapi_cfg_t nr5g_fapi_config_loader( struct rte_cfgfile *cfg_file; p_nr5g_fapi_cfg_t cfg; const char *entry; - size_t dev_name_len; + size_t dev_name_len, mem_zone_name_len; unsigned int num_cpus = 0; char check_core_count[255], *max_core; FILE *fp = NULL; @@ -86,8 +86,8 @@ p_nr5g_fapi_cfg_t nr5g_fapi_config_loader( cfg->mac2phy_worker.thread_sched_policy = (uint8_t) atoi(entry); if (cfg->mac2phy_worker.thread_sched_policy != SCHED_FIFO && cfg->mac2phy_worker.thread_sched_policy != SCHED_RR) { - printf("Thread Poicy valid range is Schedule Policy [0: SCHED_FIFO" - " 1: SCHED_RR]: configured: %d\n", + printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO" + " 2: SCHED_RR]: configured: %d\n", cfg->mac2phy_worker.thread_sched_policy); exit(-1); } @@ -126,8 +126,8 @@ p_nr5g_fapi_cfg_t nr5g_fapi_config_loader( cfg->phy2mac_worker.thread_sched_policy = (uint8_t) atoi(entry); if (cfg->phy2mac_worker.thread_sched_policy != SCHED_FIFO && cfg->phy2mac_worker.thread_sched_policy != SCHED_RR) { - printf("Thread Poicy valid range is Schedule Policy [0: SCHED_FIFO" - " 1: SCHED_RR] configured: %d\n", + printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO" + " 2: SCHED_RR] configured: %d\n", cfg->phy2mac_worker.thread_sched_policy); exit(-1); } @@ -145,6 +145,41 @@ p_nr5g_fapi_cfg_t nr5g_fapi_config_loader( } } + entry = rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "core_id"); + if (entry) { + cfg->urllc_worker.core_id = (uint8_t) atoi(entry); + if (cfg->urllc_worker.core_id >= (uint8_t) num_cpus) { + printf("Core Id is not in the range 0 to %d configured: %d\n", + num_cpus, cfg->urllc_worker.core_id); + exit(-1); + } + } + + entry = + rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "thread_sched_policy"); + if (entry) { + cfg->urllc_worker.thread_sched_policy = (uint8_t) atoi(entry); + if (cfg->urllc_worker.thread_sched_policy != SCHED_FIFO && + cfg->urllc_worker.thread_sched_policy != SCHED_RR) { + printf("Thread Policy valid range is Schedule Policy [1: SCHED_FIFO" + " 2: SCHED_RR] configured: %d\n", + cfg->urllc_worker.thread_sched_policy); + exit(-1); + } + } + + entry = + rte_cfgfile_get_entry(cfg_file, "URLLC_WORKER", "thread_priority"); + if (entry) { + cfg->urllc_worker.thread_priority = (uint8_t) atoi(entry); + if (cfg->urllc_worker.thread_priority < min_prio && + cfg->urllc_worker.thread_priority > max_prio) { + printf("Thread priority valid range is %d to %d configured: %d\n", + min_prio, max_prio, cfg->urllc_worker.thread_priority); + exit(-1); + } + } + entry = rte_cfgfile_get_entry(cfg_file, "WLS_CFG", "device_name"); if (entry) { dev_name_len = (strlen(entry) > (NR5G_FAPI_DEVICE_NAME_LEN)) ? @@ -184,6 +219,13 @@ p_nr5g_fapi_cfg_t nr5g_fapi_config_loader( } } + entry = rte_cfgfile_get_entry(cfg_file, "DPDK", "dpdk_memory_zone"); + if (entry) { + mem_zone_name_len = (strlen(entry) > (NR5G_FAPI_MEMORY_ZONE_NAME_LEN)) ? + (NR5G_FAPI_MEMORY_ZONE_NAME_LEN) : strlen(entry); + rte_strlcpy(cfg->dpdk.memory_zone, entry, mem_zone_name_len + 1); + } + return cfg; } diff --git a/fapi_5g/source/utils/nr5g_fapi_memory.c b/fapi_5g/source/utils/nr5g_fapi_memory.c index 92815fc..fd14581 100644 --- a/fapi_5g/source/utils/nr5g_fapi_memory.c +++ b/fapi_5g/source/utils/nr5g_fapi_memory.c @@ -26,7 +26,7 @@ #include #include "nr5g_fapi_wls.h" -uint8_t nr5g_fapi_memcpy_bound_check( +inline uint8_t nr5g_fapi_memcpy_bound_check( void *d, size_t x, const void *s, @@ -61,7 +61,7 @@ uint8_t nr5g_fapi_memcpy_bound_check( return SUCCESS; } -uint8_t nr5g_fapi_memset_bound_check( +inline uint8_t nr5g_fapi_memset_bound_check( void *s, size_t x, int32_t c, @@ -78,7 +78,7 @@ uint8_t nr5g_fapi_memset_bound_check( return SUCCESS; } -uint8_t nr5g_fapi_strcpy_bound_check( +inline uint8_t nr5g_fapi_strcpy_bound_check( char *d, size_t x, const char *s, diff --git a/fapi_5g/source/utils/nr5g_fapi_snr_conversion.c b/fapi_5g/source/utils/nr5g_fapi_snr_conversion.c new file mode 100644 index 0000000..0cd07ac --- /dev/null +++ b/fapi_5g/source/utils/nr5g_fapi_snr_conversion.c @@ -0,0 +1,38 @@ +/****************************************************************************** +* +* Copyright (c) 2021 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @file This file consist of SNR converter from IntelAPI to FAPI. + * + **/ + +#include "nr5g_fapi_snr_conversion.h" + +#include + +#include "gnb_l1_l2_api.h" + +uint8_t nr5g_fapi_convert_snr_iapi_to_fapi(const int16_t snr) +{ + double temp = (double)snr / SINR_STEP_SIZE; + if (temp < 0) + { + return 2 * ((uint8_t)floor(temp) & 0x003F); + } + return (2 * ((uint8_t)ceil(temp) & 0x003F)) + 128; +} diff --git a/fhi_lib/app/Makefile b/fhi_lib/app/Makefile index c42d1ff..7678ad4 100644 --- a/fhi_lib/app/Makefile +++ b/fhi_lib/app/Makefile @@ -1,6 +1,6 @@ #/****************************************************************************** #* -#* Copyright (c) 2019 Intel. +#* Copyright (c) 2020 Intel. #* #* Licensed under the Apache License, Version 2.0 (the "License"); #* you may not use this file except in compliance with the License. @@ -51,9 +51,11 @@ ifeq ($(RTE_SDK),) endif RTE_TARGET ?= x86_64-native-linuxapp-gcc -RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include + +RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk) API_DIR := $(XRAN_DIR)/lib/api +OWD_DIR := $(XRAN_DIR)/lib/src SRC_DIR := $(PROJECT_DIR)/src ifeq ($(MLOG),1) @@ -63,8 +65,10 @@ endif endif CC_SRC = $(SRC_DIR)/common.c \ - $(SRC_DIR)/sample-app.c \ - $(SRC_DIR)/config.c + $(SRC_DIR)/config.c \ + $(SRC_DIR)/app_io_fh_xran.c \ + $(SRC_DIR)/app_profile_xran.c \ + $(SRC_DIR)/sample-app.c CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -fdata-sections \ @@ -72,14 +76,14 @@ CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -g \ -Wall \ -Wimplicit-function-declaration \ - -g -O3 -wd1786 + -g -O3 -wd1786 -mcmodel=large CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \ -no-prec-div -fp-model fast=2\ -no-prec-sqrt -falign-functions=16 -fast-transcendentals \ -Werror -Wno-unused-variable -std=c++11 -mcmodel=large -INC := -I$(API_DIR) -I$(RTE_INC) +INC := -I$(API_DIR) -I$(RTE_INC) -I$(OWD_DIR) DEF := ifeq ($(MLOG),1) @@ -89,10 +93,12 @@ else DEF += -UMLOG_ENABLED endif + XRAN_LIB_DIR=$(XRAN_DIR)/lib/build LD_FLAGS += -L$(XRAN_LIB_DIR) -lxran -RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,-lrte_flow_classify -Wl,--whole-archive -Wl,-lrte_pipeline -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_table -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_port -Wl,--no-whole-archive -Wl,-lrte_pdump -Wl,-lrte_distributor -Wl,-lrte_ip_frag -Wl,-lrte_meter -Wl,-lrte_lpm -Wl,--whole-archive -Wl,-lrte_acl -Wl,--no-whole-archive -Wl,-lrte_jobstats -Wl,-lrte_metrics -Wl,-lrte_bitratestats -Wl,-lrte_latencystats -Wl,-lrte_power -Wl,-lrte_efd -Wl,-lrte_bpf -Wl,--whole-archive -Wl,-lrte_cfgfile -Wl,-lrte_gro -Wl,-lrte_gso -Wl,-lrte_hash -Wl,-lrte_member -Wl,-lrte_vhost -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_net -Wl,-lrte_ethdev -Wl,-lrte_bbdev -Wl,-lrte_cryptodev -Wl,-lrte_security -Wl,-lrte_compressdev -Wl,-lrte_eventdev -Wl,-lrte_rawdev -Wl,-lrte_timer -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_pci -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_reorder -Wl,-lrte_sched -Wl,-lrte_kni -Wl,-lrte_common_octeontx -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_bus_dpaa -Wl,-lrte_common_dpaax -Wl,-lrte_stack -Wl,-lrte_bus_fslmc -Wl,-lrte_mempool_bucket -Wl,-lrte_mempool_stack -Wl,-lrte_mempool_dpaa -Wl,-lrte_mempool_dpaa2 -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_ark -Wl,-lrte_pmd_iavf -Wl,-lrte_pmd_avp -Wl,-lrte_pmd_axgbe -Wl,-lrte_pmd_bnxt -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_dpaa -Wl,-lrte_pmd_dpaa2 -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ena -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_failsafe -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_kni -Wl,-lrte_pmd_lio -Wl,-lrte_pmd_nfp -Wl,-lrte_pmd_null -Wl,-lrte_pmd_qede -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_softnic -Wl,-lrte_pmd_tap -Wl,-lrte_pmd_thunderx_nicvf -Wl,-lrte_pmd_vdev_netvsc -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_vhost -Wl,-lrte_pmd_ifc -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_bus_vmbus -Wl,-lrte_pmd_netvsc -Wl,-lrte_pmd_bbdev_null -Wl,-lrte_pmd_null_crypto -Wl,-lrte_pmd_crypto_scheduler -Wl,-lrte_pmd_dpaa2_sec -Wl,-lrte_pmd_dpaa_sec -Wl,-lrte_pmd_virtio_crypto -Wl,-lrte_pmd_octeontx_zip -Wl,-lrte_pmd_qat -Wl,-lrte_pmd_skeleton_event -Wl,-lrte_pmd_sw_event -Wl,-lrte_pmd_octeontx_ssovf -Wl,-lrte_pmd_dpaa_event -Wl,-lrte_pmd_dpaa2_event -Wl,-lrte_mempool_octeontx -Wl,-lrte_pmd_octeontx -Wl,-lrte_pmd_opdl_event -Wl,-lrte_rawdev_skeleton -Wl,-lrte_rawdev_dpaa2_cmdif -Wl,-lrte_rawdev_dpaa2_qdma -Wl,-lrte_bus_ifpga -Wl,--no-whole-archive -Wl,-lrt -Wl,-lm -Wl,-lnuma -Wl,-ldl -Wl, +RTE_LIBS = $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk) + LD_FLAGS += $(RTE_LIBS) ifeq ($(MLOG),1) diff --git a/fhi_lib/app/dpdk.sh b/fhi_lib/app/dpdk.sh index 6fc02be..5ef548a 100755 --- a/fhi_lib/app/dpdk.sh +++ b/fhi_lib/app/dpdk.sh @@ -2,7 +2,7 @@ #/****************************************************************************** #* -#* Copyright (c) 2019 Intel. +#* Copyright (c) 2020 Intel. #* #* Licensed under the Apache License, Version 2.0 (the "License"); #* you may not use this file except in compliance with the License. @@ -140,8 +140,18 @@ if [ ${VM_DETECT} == 'HOST' ]; then #HOST $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.0 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.1 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:02.2 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.0 $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.1 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:19:0a.2 + + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.0 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.1 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:02.2 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.0 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.1 + $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:af:0a.2 + else #VM $RTE_SDK/usertools/dpdk-devbind.py --bind=igb_uio 0000:00:04.0 diff --git a/fhi_lib/app/gen_test.m b/fhi_lib/app/gen_test.m index a4cf79a..179a5b4 100644 --- a/fhi_lib/app/gen_test.m +++ b/fhi_lib/app/gen_test.m @@ -1,6 +1,19 @@ %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % -% +% Copyright (c) 2021 Intel. +% +% Licensed under the Apache License, Version 2.0 (the "License"); +% you may not use this file except in compliance with the License. +% You may obtain a copy of the License at +% +% http://www.apache.org/licenses/LICENSE-2.0 +% +% Unless required by applicable law or agreed to in writing, software +% distributed under the License is distributed on an "AS IS" BASIS, +% WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +% See the License for the specific language governing permissions and +% limitations under the License. +% % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -70,11 +83,11 @@ trx_all = ... ] path_to_usecase_all = ... [ - "./usecase/mu0_5mhz/"; - "./usecase/mu0_10mhz/"; - "./usecase/mu0_20mhz/"; - "./usecase/mu1_100mhz/"; - "./usecase/mu3_100mhz/"; + "./usecase/cat_a/mu0_5mhz/"; + "./usecase/cat_a/mu0_10mhz/"; + "./usecase/cat_a/mu0_20mhz/"; + "./usecase/cat_a/mu1_100mhz/"; + "./usecase/cat_a/mu3_100mhz/"; "./usecase/cat_b/mu1_100mhz/"; "./usecase/lte_a/mu0_20mhz/"; "./usecase/lte_a/mu0_10mhz/"; @@ -88,7 +101,7 @@ path_to_usecase_all = cellstr(path_to_usecase_all) nSlots_all = ... [ - 40,40,40,40,40,10,40,40,40,10,10,10 + 20,20,20,20,20,20,20,20,20,10,10,10 ] %select mu and bw to generate test files @@ -278,3 +291,51 @@ for test_num =(1:1:tests_total) end end end + +%% generate IQ file with valid constellation, for DL modulation compression +% only in mu1_100mhz +%constellation = [4096, -4096]; +%constellation = [2590, 7770, -7770, -2590]; +%constellation = [633, 1897, 3161, 4425, -4424, -3160, -1897, -633]; +constellation_all = [628, 1885, 3141, 4398, 5654, 6911, 8167, 9424, -9424, -8167, -6911, -5654, -4398, -3141, -1885, -628; + 633, 1897, 3161, 4425, -4424, -3160, -1897, -633, 633, 1897, 3161, 4425, -4424, -3160, -1897, -633; + 2590, 7770, -7770, -2590, 2590, 7770, -7770, -2590, 2590, 7770, -7770, -2590, 2590, 7770, -7770, -2590; + 4096, -4096, 4096, -4096, 4096, -4096, 4096, -4096, 4096, -4096, 4096, -4096, 4096, -4096, 4096, -4096; + ]; + +numRBs = 273 +nSlots = 20 +path_all = ... + [ + "./usecase/cat_a/mu1_100mhz/"; + "./usecase/cat_b/mu1_100mhz/"; + "./usecase/cat_b/mu1_100mhz/"; + "./usecase/cat_b/mu1_100mhz/"; + ] +path_all = cellstr(path_all) +modtype_all = ... + [ + "256qam_ant_"; + "64qam_ant_"; + "16qam_ant_"; + "qpsk_ant_"; + ] +modtype_all = cellstr(modtype_all) + +for test_num = 1:4 + path = path_all(test_num); + constellation=constellation_all(test_num,:); + modtype = modtype_all(test_num); + for ant = 1:4 + ant_in = rand(2*12*numRBs*14*nSlots,1); % random constellation + ant_in = 1+round(15 * ant_in); + ant_out = constellation(ant_in); + file_name = strcat(path,modtype, num2str(ant-1),".bin"); + disp(file_name) + fileID = fopen(file_name,'w'); + fwrite(fileID, ant_out, 'int16'); + fclose(fileID); + end +end + + diff --git a/fhi_lib/app/run_o_du.sh b/fhi_lib/app/run_o_du.sh index fbee0f0..0467d78 100755 --- a/fhi_lib/app/run_o_du.sh +++ b/fhi_lib/app/run_o_du.sh @@ -21,12 +21,7 @@ ulimit -c unlimited echo 1 > /proc/sys/kernel/core_uses_pid - -#40G -#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1 - -#25G - - -./build/sample-app -c ./usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat -p 2 0000:21:02.0 0000:21:02.1 -#./build/sample-app ./usecase/mu1_100mhz/config_file_o_du.dat 0000:18:02.0 0000:18:02.1 +./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg --num_eth_vfs 6 \ +--vf_addr_o_xu_a "0000:51:01.0,0000:51:09.0" \ +--vf_addr_o_xu_b "0000:51:11.0,0000:51:19.0" \ +--vf_addr_o_xu_c "0000:18:01.0,0000:18:09.0" diff --git a/fhi_lib/app/run_o_ru.sh b/fhi_lib/app/run_o_ru.sh index 946be88..924a1b6 100755 --- a/fhi_lib/app/run_o_ru.sh +++ b/fhi_lib/app/run_o_ru.sh @@ -21,11 +21,7 @@ ulimit -c unlimited echo 1 > /proc/sys/kernel/core_uses_pid - -#40G -#./build/sample-app ./usecase/mu3_100mhz/config_file_o_du.dat 0000:d8:02.0 0000:d8:02.1 - -#25G - -./build/sample-app -c ./usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat -p 2 0000:21:0a.0 0000:21:0a.1 -#./build/sample-app ./usecase/mu1_100mhz/config_file_o_ru.dat 0000:18:0a.0 0000:18:0a.1 +./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg --num_eth_vfs 6 \ +--vf_addr_o_xu_a "0000:17:01.0,0000:17:09.0" \ +--vf_addr_o_xu_b "0000:17:11.0,0000:17:19.0" \ +--vf_addr_o_xu_c "0000:65:01.0,0000:65:09.0" diff --git a/fhi_lib/app/src/app_io_fh_xran.c b/fhi_lib/app/src/app_io_fh_xran.c new file mode 100644 index 0000000..9ebec1a --- /dev/null +++ b/fhi_lib/app/src/app_io_fh_xran.c @@ -0,0 +1,2269 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief This module provides interface implementation to ORAN FH from Application side + * @file app_iof_fh_xran.c + * @ingroup xran + * @author Intel Corporation + * + **/ + +#include +#include +#include +#include +#include "common.h" +#include "config.h" +#include "xran_mlog_lnx.h" + +#include "xran_fh_o_du.h" +#include "xran_compression.h" +#include "xran_cp_api.h" +#include "xran_sync_api.h" +#include "xran_mlog_task_id.h" +#include "app_io_fh_xran.h" + +/* buffers size */ +uint32_t nFpgaToSW_FTH_RxBufferLen; +uint32_t nFpgaToSW_PRACH_RxBufferLen; +uint32_t nSW_ToFpga_FTH_TxBufferLen; + +static struct bbu_xran_io_if *p_app_io_xran_if; + +void * app_io_xran_handle = NULL; +struct xran_fh_init app_io_xran_fh_init; +struct xran_fh_config app_io_xran_fh_config[XRAN_PORTS_NUM]; + +void app_io_xran_fh_rx_callback(void *pCallbackTag, int32_t status); +void app_io_xran_fh_rx_prach_callback(void *pCallbackTag, int32_t status); +void app_io_xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status); + +struct bbu_xran_io_if * +app_io_xran_if_alloc(void) +{ + void *ptr = 0; + + ptr = _mm_malloc(sizeof(struct bbu_xran_io_if), 256); + if (ptr == NULL) { + rte_panic("_mm_malloc: Can't allocate %lu bytes\n", sizeof(struct bbu_xran_io_if)); + } + p_app_io_xran_if = (struct bbu_xran_io_if *)ptr; + return p_app_io_xran_if; +} + +struct bbu_xran_io_if * +app_io_xran_if_get(void) +{ + return p_app_io_xran_if; +} + +void +app_io_xran_if_free(void) +{ + if (p_app_io_xran_if == NULL) { + rte_panic("_mm_free: Can't free p_app_io_xran_if\n"); + } + _mm_free(p_app_io_xran_if); + return; +} + +struct xran_io_shared_ctrl * +app_io_xran_if_ctrl_get(uint32_t o_xu_id) +{ + if(o_xu_id >= 0 && o_xu_id < XRAN_PORTS_NUM) { + return &p_app_io_xran_if->ioCtrl[o_xu_id]; + } else { + return NULL; + } +} + +int32_t +app_io_xran_sfidx_get(uint8_t nNrOfSlotInSf) +{ + int32_t nSfIdx = -1; + uint32_t nFrameIdx; + uint32_t nSubframeIdx; + uint32_t nSlotIdx; + uint64_t nSecond; + + uint32_t nXranTime = xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf + + nSubframeIdx*nNrOfSlotInSf + + nSlotIdx; +#if 0 + printf("\nxranTime is %d, return is %d, radio frame is %d, subframe is %d slot is %d tsc is %llu us", + nXranTime, + nSfIdx, + nFrameIdx, + nSubframeIdx, + nSlotIdx, + __rdtsc()/CPU_HZ); +#endif + + return nSfIdx; +} + +void +app_io_xran_fh_rx_callback(void *pCallbackTag, xran_status_t status) +{ + uint64_t t1 = MLogTick(); + uint32_t mlogVar[10]; + uint32_t mlogVarCnt = 0; + uint8_t Numerlogy = app_io_xran_fh_config[0].frame_conf.nNumerology; + uint8_t nNrOfSlotInSf = 1<cellId; + nSlotIdx = pTag->slotiId; ///((status >> 16) & 0xFFFF); /** TTI aka slotIdx */ + sym = pTag->symbol & 0xFF; /* sym */ + + { + mlogVar[mlogVarCnt++] = 0xbcbcbcbc; + mlogVar[mlogVarCnt++] = nCellIdx; + mlogVar[mlogVarCnt++] = sym; + mlogVar[mlogVarCnt++] = nSlotIdx; + //mlogVar[mlogVarCnt++] = nSlotIdx % gNumSlotPerSfn[nCellIdx]; + //mlogVar[mlogVarCnt++] = get_slot_type(nCellIdx, nSlotIdx, SLOT_TYPE_UL); + + MLogAddVariables(mlogVarCnt, mlogVar, mlog_start); + } + + rte_pause(); + + MLogTask(PID_GNB_SYM_CB, t1, MLogTick()); + return; +} + +void +app_io_xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status) +{ + uint64_t t1 = MLogTick(); + uint32_t mlogVar[10]; + uint32_t mlogVarCnt = 0; + + mlogVar[mlogVarCnt++] = 0xDDDDDDDD; + mlogVar[mlogVarCnt++] = status >> 16; /* tti */ + mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */ + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + rte_pause(); + + MLogTask(PID_GNB_PRACH_CB, t1, MLogTick()); +} + +void +app_io_xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status) +{ + uint64_t t1 = MLogTick(); + uint32_t mlogVar[10]; + uint32_t mlogVarCnt = 0; + + mlogVar[mlogVarCnt++] = 0xCCCCCCCC; + mlogVar[mlogVarCnt++] = status >> 16; /* tti */ + mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */ + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + rte_pause(); + + MLogTask(PID_GNB_SRS_CB, t1, MLogTick()); +} + + +int32_t +app_io_xran_dl_tti_call_back(void * param) +{ + uint64_t t1 = MLogTick(); + rte_pause(); + MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); + return 0; +} + +int32_t +app_io_xran_ul_half_slot_call_back(void * param) +{ + uint64_t t1 = MLogTick(); + rte_pause(); + MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); + return 0; +} + +int32_t +app_io_xran_ul_full_slot_call_back(void * param) +{ + uint64_t t1 = MLogTick(); + rte_pause(); + MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); + return 0; +} + +int32_t +app_io_xran_ul_custom_sym_call_back(void * param, struct xran_sense_of_time* time) +{ + uint64_t t1 = MLogTick(); + uint32_t mlogVar[15]; + uint32_t mlogVarCnt = 0; + uint32_t sym_idx = 0; + + mlogVar[mlogVarCnt++] = 0xDEADDEAD; + if(time) { + mlogVar[mlogVarCnt++] = time->type_of_event; + mlogVar[mlogVarCnt++] = time->nSymIdx; + mlogVar[mlogVarCnt++] = time->tti_counter; + mlogVar[mlogVarCnt++] = time->nFrameIdx; + mlogVar[mlogVarCnt++] = time->nSubframeIdx; + mlogVar[mlogVarCnt++] = time->nSlotIdx; + mlogVar[mlogVarCnt++] = (uint32_t)(time->nSecond); + mlogVar[mlogVarCnt++] = (uint32_t)(time->nSecond >> 32); + sym_idx = time->nSymIdx; + } + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + + rte_pause(); + MLogTask(PID_GNB_SYM_CB + sym_idx, t1, MLogTick()); + return 0; +} + +int32_t +app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg) +{ + xran_status_t status; + struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get(); + struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id); + int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; + int32_t nSectorNum; + int32_t i, j, k, m, z; + + void *ptr; + void *mb; + uint32_t *u32dptr; + uint16_t *u16dptr; + uint8_t *u8dptr; + uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc); + uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr); + uint32_t xran_max_sections_per_slot = RTE_MAX(p_o_xu_cfg->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT); + uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm)*(xran_max_sections_per_slot - 1); + + SWXRANInterfaceTypeEnum eInterfaceType; + + struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxRachBufferDecomp[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxSrsPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN]; + + if(psBbuIo == NULL) + rte_panic("psBbuIo == NULL\n"); + + if(psIoCtrl == NULL) + rte_panic("psIoCtrl == NULL\n"); + + for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) + { + nSectorIndex[nSectorNum] = nSectorNum; + } + + nSectorNum = p_o_xu_cfg->numCC; + printf ("XRAN front haul xran_mm_init \n"); + status = xran_mm_init (app_io_xran_handle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN); + if (status != XRAN_STATUS_SUCCESS) + { + printf ("Failed at XRAN front haul xran_mm_init \n"); + exit(-1); + } + + psBbuIo->nInstanceNum[o_xu_id] = p_o_xu_cfg->numCC; + if (o_xu_id < XRAN_PORTS_NUM) { + status = xran_sector_get_instances (o_xu_id, app_io_xran_handle, psBbuIo->nInstanceNum[o_xu_id], &psBbuIo->nInstanceHandle[o_xu_id][0]); + if (status != XRAN_STATUS_SUCCESS) { + printf ("get sector instance failed %d for XRAN nInstanceNum[%d] %d\n",k, psBbuIo->nInstanceNum[o_xu_id], o_xu_id); + exit(-1); + } + for (i = 0; i < psBbuIo->nInstanceNum[o_xu_id]; i++) { + printf("%s [%d]: CC %d handle %p\n", __FUNCTION__, k, i, psBbuIo->nInstanceHandle[o_xu_id][i]); + } + } else { + printf ("Failed at XRAN front haul xran_mm_init \n"); + exit(-1); + } + + printf("Sucess xran_mm_init \n"); + printf("nSectorNum %d\n", nSectorNum); + printf("xran_max_sections_per_slot %d\n", xran_max_sections_per_slot); + + /* Init Memory */ + for(i = 0; i < nSectorNum; i++) + { + eInterfaceType = XRANFTHTX_OUT; + printf("nSectorIndex[%d] = %d\n",i, nSectorIndex[i]); + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init , status %d\n", status); + } + for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) + { + for(z = 0; z < xran_max_antenna_nr; z++){ + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulTxBuffers[j][i][z][0]; + + for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) + { + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status){ + rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); + } + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; + + if(ptr){ + u32dptr = (uint32_t*)(ptr); + memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen); + // ptr_temp[0] = j; // TTI + // ptr_temp[1] = i; // Sec + // ptr_temp[2] = z; // Ant + // ptr_temp[3] = k; // sym + } + } + } + } + + /* C-plane DL */ + eInterfaceType = XRANFTHTX_SEC_DESC_OUT; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*xran_max_sections_per_slot*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc)); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init , status %d\n", status); + } + + printf("size_of_prb_map %d\n", size_of_prb_map); + + eInterfaceType = XRANFTHTX_PRB_MAP_OUT; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init , status %d\n", status); + } + + for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) + { + for(z = 0; z < xran_max_antenna_nr; z++){ + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulTxPrbMapBuffers[j][i][z]; + + { + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); + } + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; + + if(ptr){ + void *sd_ptr; + void *sd_mb; + int32_t elm_id; + struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; + if (p_o_xu_cfg->appMode == APP_O_DU) { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapDl, size_of_prb_map); + } + } else { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapUl, size_of_prb_map); + } + } + + for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){ + struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; + for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ + for(m = 0; m < XRAN_MAX_FRAGMENT; m++){ + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT],&sd_ptr, &sd_mb); + if(XRAN_STATUS_SUCCESS != status){ + rte_panic("SD Failed at DESC_OUT xran_bm_allocate_buffer , m %d k %d elm_id %d\n",m,k, elm_id); + } + pPrbElem->p_sec_desc[k][m] = sd_ptr; + memset(sd_ptr,0,sizeof(struct xran_section_desc)); + } + } + } + } + } + } + } + } + + for(i = 0; inInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); + if(XRAN_STATUS_SUCCESS != status) + { + printf("Failed at xran_bm_init, status %d\n", status); + iAssert(status == XRAN_STATUS_SUCCESS); + } + + for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) + { + for(z = 0; z < xran_max_antenna_nr; z++){ + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulRxBuffers[j][i][z][0]; + for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) + { + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nFpgaToSW_FTH_RxBufferLen; // 1 symbols 3200bytes + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); + } + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb; + if(ptr){ + u32dptr = (uint32_t*)(ptr); + uint8_t *ptr_temp = (uint8_t *)ptr; + memset(u32dptr, 0x0, nFpgaToSW_FTH_RxBufferLen); + // ptr_temp[0] = j; // TTI + // ptr_temp[1] = i; // Sec + // ptr_temp[2] = z; // Ant + // ptr_temp[3] = k; // sym + } + } + } + } + + /* C-plane */ + eInterfaceType = XRANFTHTX_SEC_DESC_IN; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*xran_max_sections_per_slot*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc)); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init , status %d\n", status); + } + eInterfaceType = XRANFTHRX_PRB_MAP_IN; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init, status %d\n", status); + } + + for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) { + for(z = 0; z < xran_max_antenna_nr; z++){ + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulRxPrbMapBuffers[j][i][z]; + { + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); + } + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; + if(ptr){ + void *sd_ptr; + void *sd_mb; + int32_t elm_id; + struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; + + if (p_o_xu_cfg->appMode == APP_O_DU) { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_UL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapUl, size_of_prb_map); + } + } else { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapDl, size_of_prb_map); + } + } + + for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){ + struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; + for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ + for(m = 0; m < XRAN_MAX_FRAGMENT; m++){ + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN],&sd_ptr, &sd_mb); + if(XRAN_STATUS_SUCCESS != status){ + rte_panic("SD Failed at DESC_IN xran_bm_allocate_buffer , m %d k %d\n",m,k); + } + pPrbElem->p_sec_desc[k][m] = sd_ptr; + memset(sd_ptr,0,sizeof(struct xran_section_desc)); + } + } + } + } + } + } + } + } + + // add prach rx buffer + for(i = 0; inInstanceHandle[o_xu_id][i],&psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, PRACH_PLAYBACK_BUFFER_BYTES); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init, status %d\n", status); + } + for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) + { + for(z = 0; z < xran_max_antenna_nr; z++){ + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; // ant number. + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHPrachRxBuffers[j][i][z][0]; + psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHPrachRxBuffersDecomp[j][i][z][0]; + for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) + { + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = PRACH_PLAYBACK_BUFFER_BYTES; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + + if (p_o_xu_cfg->appMode == APP_O_RU) { + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status); + } + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; + if(ptr){ + u32dptr = (uint32_t*)(ptr); + memset(u32dptr, 0x0, PRACH_PLAYBACK_BUFFER_BYTES); + } + psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList.pBuffers[k].pData= (uint8_t *)ptr; + } + } + } + } + } + + /* add SRS rx buffer */ + printf("%s:%d: xran_max_ant_array_elm_nr %d\n", __FUNCTION__, __LINE__, xran_max_ant_array_elm_nr); + for(i = 0; inInstanceHandle[o_xu_id][i],&psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); + + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init, status %d\n", status); + } + for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) { + for(z = 0; z < xran_max_ant_array_elm_nr; z++){ + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_ant_array_elm_nr; /* ant number */ + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHSrsRxBuffers[j][i][z][0]; + for(k = 0; k < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; k++) + { + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status); + } + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; + if(ptr){ + u32dptr = (uint32_t*)(ptr); + memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen); + } + } + } + } + + /* SRS C-plane */ + eInterfaceType = XRANSRS_SEC_DESC_IN; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*xran_max_sections_per_slot*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc)); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init , status %d\n", status); + } + eInterfaceType = XRANSRS_PRB_MAP_IN; + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], &psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, size_of_prb_map); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_init, status %d\n", status); + } + + for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) { + for(z = 0; z < xran_max_ant_array_elm_nr; z++) { + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHSrsRxPrbMapBuffers[j][i][z]; + { + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = size_of_prb_map; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][eInterfaceType],&ptr, &mb); + if(XRAN_STATUS_SUCCESS != status) { + rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); + } + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; + psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; + + if(ptr) { + void *sd_ptr; + void *sd_mb; + int32_t elm_id; + struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; + + if (p_o_xu_cfg->appMode == APP_O_DU) { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSrsSlotPrbMap[XRAN_DIR_UL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapSrs, size_of_prb_map); + } + } else { + if(p_o_xu_cfg->RunSlotPrbMapEnabled) { + memcpy(ptr, p_o_xu_cfg->p_RunSrsSlotPrbMap[XRAN_DIR_DL][j][i][z], size_of_prb_map); + } else { + memcpy(ptr, p_o_xu_cfg->p_PrbMapSrs, size_of_prb_map); + } + } + + for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){ + struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; + for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ + for(m = 0; m < XRAN_MAX_FRAGMENT; m++){ + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][nSectorIndex[i]][XRANSRS_SEC_DESC_IN],&sd_ptr, &sd_mb); + if(XRAN_STATUS_SUCCESS != status){ + rte_panic("SD Failed at SRS_SEC_DESC_IN xran_bm_allocate_buffer , m %d k %d\n",m,k); + } + pPrbElem->p_sec_desc[k][m] = sd_ptr; + memset(sd_ptr,0,sizeof(struct xran_section_desc)); + } + } + } + } + } + } + } + } + + for(i=0; isFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList); + pFthTxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxRachBuffer[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxRachBufferDecomp[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList); + } + + for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR && xran_max_ant_array_elm_nr; z++){ + pFthRxSrsBuffer[i][z][j] = &(psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxSrsPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); + } + } + } + + if(NULL != psBbuIo->nInstanceHandle[o_xu_id]) + { + /* add pusch callback */ + for (i = 0; iRxCbTag[o_xu_id][i].cellId = i; + psBbuIo->RxCbTag[o_xu_id][i].symbol = 0; + psBbuIo->RxCbTag[o_xu_id][i].slotiId = 0; + xran_5g_fronthault_config (psBbuIo->nInstanceHandle[o_xu_id][i], + pFthTxBuffer[i], + pFthTxPrbMapBuffer[i], + pFthRxBuffer[i], + pFthRxPrbMapBuffer[i], + app_io_xran_fh_rx_callback, &psBbuIo->RxCbTag[o_xu_id][i]); + } + /* add prach callback here */ + for (i = 0; iPrachCbTag[o_xu_id][i].cellId = i; + psBbuIo->PrachCbTag[o_xu_id][i].symbol = 0; + psBbuIo->PrachCbTag[o_xu_id][i].slotiId = 0; + xran_5g_prach_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxRachBuffer[i],pFthRxRachBufferDecomp[i], + app_io_xran_fh_rx_prach_callback,&psBbuIo->PrachCbTag[o_xu_id][i]); + } + + /* add SRS callback here */ + for (i = 0; iSrsCbTag[o_xu_id][i].cellId = i; + psBbuIo->SrsCbTag[o_xu_id][i].symbol = 0; + psBbuIo->SrsCbTag[o_xu_id][i].slotiId = 0; + xran_5g_srs_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxSrsBuffer[i], pFthRxSrsPrbMapBuffer[i], + app_io_xran_fh_rx_srs_callback,&psBbuIo->SrsCbTag[o_xu_id][i]); + } + } + + return status; +} + +int32_t +app_io_xran_ext_type11_populate(struct xran_prb_elm* p_pRbMapElm, int16_t *p_tx_dl_bfw_buffer, uint32_t mtu) +{ + xran_status_t status = XRAN_STATUS_SUCCESS; + + int32_t i; + uint8_t *extbuf; + int32_t n_max_set_bfw; + + p_pRbMapElm->bf_weight.maxExtBufSize = mtu; /* MAX_RX_LEN; */ /* Maximum space of external buffer */ + extbuf = (uint8_t*)xran_malloc(p_pRbMapElm->bf_weight.maxExtBufSize); + if(extbuf == NULL) + rte_panic("xran_malloc return NULL\n"); + + /* Check BFWs can be fit with MTU size */ + n_max_set_bfw = xran_cp_estimate_max_set_bfws(p_pRbMapElm->bf_weight.nAntElmTRx, + p_pRbMapElm->bf_weight.bfwIqWidth, + p_pRbMapElm->bf_weight.bfwCompMeth, + mtu); + + if(p_pRbMapElm->bf_weight.numSetBFWs > n_max_set_bfw) { + /* PRB elm doesn't fit into packet MTU size */ + rte_panic("BFWs are too large with MTU %d! (cfg:%d / max:%d)\n", + mtu, p_pRbMapElm->bf_weight.numSetBFWs, n_max_set_bfw); + + } + + /* Configure source buffer and beam ID of BFWs */ + for(i = 0; i < p_pRbMapElm->bf_weight.numSetBFWs; i++) { + p_pRbMapElm->bf_weight.bfw[i].pBFWs = (uint8_t *)(p_tx_dl_bfw_buffer + p_pRbMapElm->bf_weight.nAntElmTRx*2*i); + p_pRbMapElm->bf_weight.bfw[i].beamId = 0x7000+i; + } + + n_max_set_bfw = xran_cp_prepare_ext11_bfws(p_pRbMapElm->bf_weight.numSetBFWs, + p_pRbMapElm->bf_weight.nAntElmTRx, + p_pRbMapElm->bf_weight.bfwIqWidth, + p_pRbMapElm->bf_weight.bfwCompMeth, + extbuf, + p_pRbMapElm->bf_weight.maxExtBufSize, + p_pRbMapElm->bf_weight.bfw); + if(n_max_set_bfw > 0) { + p_pRbMapElm->bf_weight.ext_section_sz = n_max_set_bfw; + p_pRbMapElm->bf_weight.p_ext_start = (int8_t *)extbuf; + } else + rte_panic("Fail to prepare BFWs for extension 11!\n"); + + return status; +} + +int32_t +app_io_xran_iq_content_init_cp_rb_map(struct xran_prb_map* pRbMap, + enum xran_pkt_dir dir, int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, uint16_t nRBs) +{ + pRbMap->dir = dir; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = cc_id; + pRbMap->ru_port_id = ant_id; + pRbMap->tti_id = tti; + pRbMap->start_sym_id = 0; + pRbMap->nPrbElm = 1; + pRbMap->prbMap[0].nRBStart = 0; + pRbMap->prbMap[0].nRBSize = nRBs; + pRbMap->prbMap[0].nStartSymb = 0; + pRbMap->prbMap[0].numSymb = 14; + pRbMap->prbMap[0].p_sec_desc[sym_id][0]->iq_buffer_offset = 0; + pRbMap->prbMap[0].p_sec_desc[sym_id][0]->iq_buffer_len = nRBs *4L; + pRbMap->prbMap[0].nBeamIndex = 0; + pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; + + return 0; +} + +/** c-plane DL */ +int32_t +app_io_xran_iq_content_init_cp_tx(uint8_t appMode, struct xran_fh_config *pXranConf, + struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq, + int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId) +{ + int32_t status = 0; + struct xran_prb_map* pRbMap = NULL; + + if(p_iq->p_tx_play_buffer[flowId]) { + pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + if(pRbMap) { + if (pXranConf->DynamicSectionEna == 0) { + app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_DL, cc_id, ant_id, sym_id, tti, pXranConf->nDLRBs); + } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B + && appMode == APP_O_DU + && sym_id == 0) { /* BFWs are per slot */ + + int32_t idxElm = 0; + char* dl_bfw_pos = ((char*)p_iq->p_tx_dl_bfw_buffer[flowId]) + p_iq->tx_dl_bfw_buffer_position[flowId]; + struct xran_prb_elm* p_pRbMapElm = NULL; + + for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) { + p_pRbMapElm = &pRbMap->prbMap[idxElm]; + p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx; + + if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update) { + if(p_pRbMapElm->bf_weight.numBundPrb == 0) { + /* No bundled PRB, using extension 1 */ + int16_t ext_len = 9600; + int16_t ext_sec_total = 0; + int8_t * ext_buf =(int8_t*) xran_malloc(ext_len); + int8_t * ext_buf_start = ext_buf; + if(ext_buf) { + ext_buf += (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + ext_len -= (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf, + ext_len, + (int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4), + p_pRbMapElm->nRBSize, + p_pRbMapElm->bf_weight.nAntElmTRx, + p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod); + if(ext_sec_total > 0) { + p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start; + p_pRbMapElm->bf_weight.p_ext_section = ext_buf; + p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total; + } else + rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total); + } else { + rte_panic("xran_malloc return NULL\n"); + } + } else { + app_io_xran_ext_type11_populate(p_pRbMapElm, p_iq->p_tx_dl_bfw_buffer[flowId], app_io_xran_fh_init.mtu); + } + } + } + } + } else { + printf("DL pRbMap ==NULL\n"); + exit(-1); + } + + if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B && appMode == APP_O_DU && sym_id == 0) { + p_iq->tx_dl_bfw_buffer_position[flowId] += (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4; + if(p_iq->tx_dl_bfw_buffer_position[flowId] >= p_iq->tx_dl_bfw_buffer_size[flowId]) + p_iq->tx_dl_bfw_buffer_position[flowId] = 0; + } + } else { + //printf("flowId %d\n", flowId); + } + + return status; +} + +/** C-plane UL */ +int32_t +app_io_xran_iq_content_init_cp_rx(uint8_t appMode, struct xran_fh_config *pXranConf, + struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq, + int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId) +{ + int32_t status = 0; + struct xran_prb_map* pRbMap = NULL; + char *pos = NULL; + void *ptr = NULL; + + pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + if(pRbMap) { + if (pXranConf->DynamicSectionEna == 0) { + app_io_xran_iq_content_init_cp_rb_map(pRbMap, XRAN_DIR_UL, cc_id, ant_id, sym_id, tti, pXranConf->nULRBs); + } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B + && appMode == APP_O_DU + && sym_id == 0) { + int32_t idxElm = 0; + char * ul_bfw_pos = ((char*)p_iq->p_tx_ul_bfw_buffer[flowId]) + p_iq->tx_ul_bfw_buffer_position[flowId]; + struct xran_prb_elm* p_pRbMapElm = NULL; + + for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) { + p_pRbMapElm = &pRbMap->prbMap[idxElm]; + p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx; + + if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update) { + if(p_pRbMapElm->bf_weight.numBundPrb == 0) { + /* No bundled PRB, using extension 1 */ + + int16_t ext_len = 9600; + int16_t ext_sec_total = 0; + int8_t * ext_buf =(int8_t*) xran_malloc(ext_len); + int8_t * ext_buf_start = ext_buf; + int32_t idRb = 0; + int16_t *ptr = NULL; + int32_t i; + if(ext_buf) { + ext_buf += (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + ext_len -= (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4); + ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf, + ext_len, + (int16_t *) (ul_bfw_pos + (p_pRbMapElm->nRBStart*p_pRbMapElm->bf_weight.nAntElmTRx)*4), + p_pRbMapElm->nRBSize, + p_pRbMapElm->bf_weight.nAntElmTRx, + p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod); + if(ext_sec_total > 0) { + p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start; + p_pRbMapElm->bf_weight.p_ext_section = ext_buf; + p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total; + } else { + rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total); + } + } else { + rte_panic("xran_malloc return NULL\n"); + } + } else { + app_io_xran_ext_type11_populate(p_pRbMapElm, p_iq->p_tx_ul_bfw_buffer[flowId], app_io_xran_fh_init.mtu); + } + } + } + } + p_iq->tx_ul_bfw_buffer_position[flowId] += (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4; + if(p_iq->tx_ul_bfw_buffer_position[flowId] >= p_iq->tx_ul_bfw_buffer_size[flowId]) + p_iq->tx_ul_bfw_buffer_position[flowId] = 0; + } else { + rte_panic("DL pRbMap ==NULL\n"); + } + + return 0; +} + +int32_t +app_io_xran_iq_content_init_up_tx(uint8_t appMode, struct xran_fh_config *pXranConf, + struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq, + int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId) +{ + char *pos = NULL; + void *ptr = NULL; + uint8_t* u8dptr = NULL; + struct xran_prb_map* pRbMap = NULL; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; + + if (pXranConf != NULL) + { + staticEn = pXranConf->ru_conf.xranCompHdrType; + + + pRbMap = (struct xran_prb_map *) psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + pos = ((char*)p_iq->p_tx_play_buffer[flowId]) + p_iq->tx_play_buffer_position[flowId]; + ptr = psIoCtrl->sFrontHaulTxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + + if(ptr && pos) { + int32_t idxElm = 0; + u8dptr = (uint8_t*)ptr; + int16_t payload_len = 0; + + uint8_t *dst = (uint8_t *)u8dptr; + uint8_t *src = (uint8_t *)pos; + struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm]; + dst = xran_add_hdr_offset(dst, ((staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE)); + + for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) { + struct xran_section_desc *p_sec_desc = NULL; + p_prbMapElm = &pRbMap->prbMap[idxElm]; + p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0]; + + if(p_sec_desc == NULL) { + rte_panic ("p_sec_desc == NULL\n"); + } + + /* skip, if not scheduled */ + if(sym_id < p_prbMapElm->nStartSymb || sym_id >= p_prbMapElm->nStartSymb + p_prbMapElm->numSymb){ + p_sec_desc->iq_buffer_offset = 0; + p_sec_desc->iq_buffer_len = 0; + continue; + } + + src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L); + + if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) { + payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; + memcpy(dst, src, payload_len); + + } else if ((p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT) || (p_prbMapElm->compMethod == XRAN_COMPMETHOD_MODULATION)) { + struct xranlib_compress_request bfp_com_req; + struct xranlib_compress_response bfp_com_rsp; + + memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request)); + memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response)); + + bfp_com_req.data_in = (int16_t*)src; + bfp_com_req.numRBs = p_prbMapElm->nRBSize; + bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; + bfp_com_req.compMethod = p_prbMapElm->compMethod; + bfp_com_req.iqWidth = p_prbMapElm->iqWidth; + bfp_com_req.ScaleFactor= p_prbMapElm->ScaleFactor; + bfp_com_req.reMask = p_prbMapElm->reMask; + + bfp_com_rsp.data_out = (int8_t*)dst; + bfp_com_rsp.len = 0; + + xranlib_compress(&bfp_com_req, &bfp_com_rsp); + payload_len = bfp_com_rsp.len; + + } else { + printf ("p_prbMapElm->compMethod == %d is not supported\n", + p_prbMapElm->compMethod); + exit(-1); + } + + /* update RB map for given element */ + p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr); + p_sec_desc->iq_buffer_len = payload_len; + + /* add headroom for ORAN headers between IQs for chunk of RBs*/ + dst += payload_len; + dst = xran_add_hdr_offset(dst, ((staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE)); + } + + p_iq->tx_play_buffer_position[flowId] += pXranConf->nDLRBs*N_SC_PER_PRB*4; + if(p_iq->tx_play_buffer_position[flowId] >= p_iq->tx_play_buffer_size[flowId]) + p_iq->tx_play_buffer_position[flowId] = 0; + } else { + rte_panic("ptr ==NULL\n"); + } + } + + return 0; +} + +int32_t +app_io_xran_iq_content_init_up_prach(uint8_t appMode, struct xran_fh_config *pXranConf, + struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq, + int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId) +{ + char *pos = NULL; + void *ptr = NULL; + uint32_t* u32dptr = NULL; + + if(p_iq->p_tx_prach_play_buffer[flowId]) { + pos = ((char*)p_iq->p_tx_prach_play_buffer[flowId]); + ptr = psIoCtrl->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + + if(ptr && pos) { + int32_t compMethod = pXranConf->ru_conf.compMeth; + + if(compMethod == XRAN_COMPMETHOD_NONE) { + u32dptr = (uint32_t*)(ptr); + memcpy(u32dptr, pos, RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, p_iq->tx_prach_play_buffer_size[flowId])); + } else if((compMethod == XRAN_COMPMETHOD_BLKFLOAT) + || (compMethod == XRAN_COMPMETHOD_MODULATION)) { + struct xranlib_compress_request comp_req; + struct xranlib_compress_response comp_rsp; + + memset(&comp_req, 0, sizeof(struct xranlib_compress_request)); + memset(&comp_rsp, 0, sizeof(struct xranlib_compress_response)); + + /* compress whole playback data */ + comp_req.data_in = (int16_t *)pos; + comp_req.len = RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, p_iq->tx_prach_play_buffer_size[flowId]); + comp_req.numRBs = comp_req.len / 12 / 4; /* 12RE, 4bytes */ + comp_req.compMethod = compMethod; + comp_req.iqWidth = pXranConf->ru_conf.iqWidth; + comp_req.ScaleFactor = 0; /* TODO */ + comp_req.reMask = 0xfff; /* TODO */ + + comp_rsp.data_out = (int8_t *)ptr; + comp_rsp.len = 0; + + xranlib_compress(&comp_req, &comp_rsp); + } else { + printf ("p_prbMapElm->compMethod == %d is not supported\n", compMethod); + exit(-1); + } + } else { /* if(ptr && pos) */ + printf("prach ptr ==NULL\n"); + exit(-1); + } + } /* if(p_iq->p_tx_prach_play_buffer[flowId]) */ + + return 0; +} + +int32_t +app_io_xran_iq_content_init_up_srs(uint8_t appMode, struct xran_fh_config *pXranConf, + struct bbu_xran_io_if *psBbuIo, struct xran_io_shared_ctrl *psIoCtrl, struct o_xu_buffers * p_iq, + int32_t cc_id, int32_t ant_id, int32_t sym_id, int32_t tti, int32_t flowId) +{ + struct xran_prb_map * pRbMap = NULL; + char *pos = NULL; + void *ptr = NULL; + uint8_t* u8dptr = NULL; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; + + if (pXranConf != NULL) + { + staticEn = pXranConf->ru_conf.xranCompHdrType; + + + if(p_iq->p_tx_srs_play_buffer[flowId]) { + pos = ((char*)p_iq->p_tx_srs_play_buffer[flowId]) + p_iq->tx_srs_play_buffer_position[flowId];; + ptr = psIoCtrl->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + + if(ptr && pos && pRbMap) { + int32_t idxElm = 0; + u8dptr = (uint8_t*)ptr; + int16_t payload_len = 0; + + uint8_t *dst = (uint8_t *)u8dptr; + uint8_t *src = (uint8_t *)pos; + struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm]; + dst = xran_add_hdr_offset(dst, (staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE); + for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) { + struct xran_section_desc *p_sec_desc = NULL; + p_prbMapElm = &pRbMap->prbMap[idxElm]; + p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0]; + + if(p_sec_desc == NULL){ + rte_panic ("p_sec_desc == NULL\n"); + } + + /* skip, if not scheduled */ + if(sym_id < p_prbMapElm->nStartSymb || sym_id >= p_prbMapElm->nStartSymb + p_prbMapElm->numSymb) { + p_sec_desc->iq_buffer_offset = 0; + p_sec_desc->iq_buffer_len = 0; + continue; + } + + src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L); + + if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) { + payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; + memcpy(dst, src, payload_len); + + } else if (p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT + || (p_prbMapElm->compMethod == XRAN_COMPMETHOD_MODULATION)) { + struct xranlib_compress_request bfp_com_req; + struct xranlib_compress_response bfp_com_rsp; + + memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request)); + memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response)); + + bfp_com_req.data_in = (int16_t*)src; + bfp_com_req.numRBs = p_prbMapElm->nRBSize; + bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; + bfp_com_req.compMethod = p_prbMapElm->compMethod; + bfp_com_req.iqWidth = p_prbMapElm->iqWidth; + bfp_com_req.ScaleFactor= p_prbMapElm->ScaleFactor; + bfp_com_req.reMask = p_prbMapElm->reMask; + + bfp_com_rsp.data_out = (int8_t*)dst; + bfp_com_rsp.len = 0; + + xranlib_compress(&bfp_com_req, &bfp_com_rsp); + payload_len = bfp_com_rsp.len; + } else { + rte_panic ("p_prbMapElm->compMethod == %d is not supported\n", p_prbMapElm->compMethod); + } + + /* update RB map for given element */ + p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr); + p_sec_desc->iq_buffer_len = payload_len; + + /* add headroom for ORAN headers between IQs for chunk of RBs*/ + dst += payload_len; + dst = xran_add_hdr_offset(dst, (staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC) ? p_prbMapElm->compMethod : XRAN_COMPMETHOD_NONE); + } + } else { + rte_panic("[%d %d %d] %p %p %p ==NULL\n",tti, ant_id, sym_id, ptr, pos, pRbMap); + } + + p_iq->tx_srs_play_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; + if(p_iq->tx_srs_play_buffer_position[flowId] >= p_iq->tx_srs_play_buffer_size[flowId]) + p_iq->tx_srs_play_buffer_position[flowId] = 0; + } + } + + return 0; +} + +int32_t +app_io_xran_iq_content_init(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg) +{ + xran_status_t status; + + struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get(); + struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id); + int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; + int32_t nSectorNum; + int32_t cc_id, ant_id, sym_id, tti; + int32_t flowId; + + uint8_t frame_id = 0; + uint8_t subframe_id = 0; + uint8_t slot_id = 0; + uint8_t sym = 0; + + void *ptr; + uint32_t *u32dptr; + uint16_t *u16dptr; + uint8_t *u8dptr; + + struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id]; + struct xran_fh_init *pXranInit = &app_io_xran_fh_init; + struct o_xu_buffers * p_iq = NULL; + + uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc); + uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr); + + char *pos = NULL; + struct xran_prb_map *pRbMap = NULL; + + if(psBbuIo == NULL){ + rte_panic("psBbuIo == NULL\n"); + } + + if(psIoCtrl == NULL){ + rte_panic("psIoCtrl == NULL\n"); + } + + for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) { + nSectorIndex[nSectorNum] = nSectorNum; + } + nSectorNum = p_o_xu_cfg->numCC; + printf ("app_io_xran_iq_content_init\n"); + + if(p_o_xu_cfg->p_buff) { + p_iq = p_o_xu_cfg->p_buff; + } else { + rte_panic("Error p_o_xu_cfg->p_buff\n"); + } + + /* Init Memory */ + for(cc_id = 0; cc_id < nSectorNum; cc_id++) { + for(tti = 0; tti < XRAN_N_FE_BUF_LEN; tti ++) { + for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++){ + for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { + if(p_o_xu_cfg->appMode == APP_O_DU) { + flowId = p_o_xu_cfg->numAxc * cc_id + ant_id; + } else { + flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id; + } + + if ((status = app_io_xran_iq_content_init_cp_tx(p_o_xu_cfg->appMode, pXranConf, + psBbuIo, psIoCtrl, p_iq, + cc_id, ant_id, sym_id, tti, flowId)) != 0) { + rte_panic("app_io_xran_iq_content_init_cp_tx"); + } + if ((status = app_io_xran_iq_content_init_up_tx(p_o_xu_cfg->appMode, pXranConf, + psBbuIo, psIoCtrl, p_iq, + cc_id, ant_id, sym_id, tti, flowId)) != 0) { + rte_panic("app_io_xran_iq_content_init_up_tx"); + } + if ((status = app_io_xran_iq_content_init_cp_rx(p_o_xu_cfg->appMode, pXranConf, + psBbuIo, psIoCtrl, p_iq, + cc_id, ant_id, sym_id, tti, flowId)) != 0) { + rte_panic("app_io_xran_iq_content_init_cp_rx"); + } + + } + } + + /* prach TX for RU only */ + if(p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enablePrach) { + for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) { + for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { + flowId = p_o_xu_cfg->numAxc*cc_id + ant_id; + if ((status = app_io_xran_iq_content_init_up_prach(p_o_xu_cfg->appMode, pXranConf, + psBbuIo, psIoCtrl, p_iq, + cc_id, ant_id, sym_id, tti, flowId)) != 0) { + rte_panic("app_io_xran_iq_content_init_cp_tx"); + } + } + } + #if 0 + for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { + char fname[32]; + snprintf(fname, sizeof(fname), "./logs/aftercomp-%d.bin", sym_id); + sys_save_buf_to_file(fname, + "Compressed PRACH IQ Samples in binary format", + psIoCtrl->sFHPrachRxBbuIoBufCtrl[0][0][0].sBufferList.pBuffers[sym_id].pData, + RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, p_iq->tx_prach_play_buffer_size[0]), + 1); + snprintf(fname, sizeof(fname), "./logs/aftercomp-%d.txt", sym_id); + sys_save_buf_to_file_txt(fname, + "Compressed PRACH IQ Samples in human readable format", + psIoCtrl->sFHPrachRxBbuIoBufCtrl[0][0][0].sBufferList.pBuffers[sym_id].pData, + RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, p_iq->tx_prach_play_buffer_size[0]), + 1); + } + #endif + } + /* SRS TX for RU only */ + if(p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enableSrs) { + for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) { + for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) { + flowId = p_o_xu_cfg->antElmTRx*cc_id + ant_id; + if ((status = app_io_xran_iq_content_init_up_srs(p_o_xu_cfg->appMode, pXranConf, + psBbuIo, psIoCtrl, p_iq, + cc_id, ant_id, sym_id, tti, flowId)) != 0){ + rte_panic("app_io_xran_iq_content_init_cp_tx"); + } + } + } + } + } + } + + return 0; +} + +void app_io_xran_if_stop(void) +{ + xran_status_t status = 0; + SWXRANInterfaceTypeEnum eInterfaceType; + + status += xran_mm_destroy(app_io_xran_handle)*2; + + if(XRAN_STATUS_SUCCESS != status) { + printf("Failed at xran_mm_destroy, status %d\n",status); + iAssert(status == XRAN_STATUS_SUCCESS); + } +} + +int32_t +app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg) +{ + struct bbu_xran_io_if *psBbuIo = app_io_xran_if_get(); + struct xran_io_shared_ctrl *psIoCtrl = app_io_xran_if_ctrl_get(o_xu_id); + xran_status_t status; + int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; + int32_t nSectorNum; + int32_t cc_id, ant_id, sym_id, tti; + int32_t flowId; + + uint8_t frame_id = 0; + uint8_t subframe_id = 0; + uint8_t slot_id = 0; + uint8_t sym = 0; + uint16_t idxDesc = 0; + + void *ptr; + uint32_t *u32dptr; + uint16_t *u16dptr; + uint8_t *u8dptr; + + struct xran_fh_config *pXranConf = &app_io_xran_fh_config[o_xu_id]; + + uint32_t xran_max_antenna_nr = RTE_MAX(p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc); + uint32_t xran_max_ant_array_elm_nr = RTE_MAX(p_o_xu_cfg->antElmTRx, xran_max_antenna_nr); + + char *pos = NULL; + struct o_xu_buffers *p_iq = NULL; + + if(psBbuIo == NULL) + rte_panic("psBbuIo == NULL\n"); + + if(psIoCtrl == NULL) + rte_panic("psIoCtrl == NULL\n"); + + for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) { + nSectorIndex[nSectorNum] = nSectorNum; + } + + nSectorNum = p_o_xu_cfg->numCC; + printf ("app_io_xran_iq_content_get\n"); + + if(p_o_xu_cfg->p_buff) { + p_iq = p_o_xu_cfg->p_buff; + } else { + printf("Error p_o_xu_cfg->p_buff\n"); + exit(-1); + } + + for(cc_id = 0; cc_id sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + if(pRbMap == NULL){ + printf("pRbMap == NULL\n"); + exit(-1); + } + if(p_o_xu_cfg->appMode == APP_O_RU) + flowId = p_o_xu_cfg->numAxc * cc_id + ant_id; + else + flowId = p_o_xu_cfg->numUlAxc * cc_id + ant_id; + + for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { + pRbElm = &pRbMap->prbMap[0]; + if(pRbMap->nPrbElm == 1){ + if(p_iq->p_rx_log_buffer[flowId]) { + pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId]; + uint32_t one_rb_size = (((pRbElm->iqWidth == 0) || (pRbElm->iqWidth == 16)) ? (N_SC_PER_PRB*2*2) : (3 * pRbElm->iqWidth + 1)); + if (app_io_xran_fh_init.mtu < pRbElm->nRBSize * one_rb_size) + { + ptr = psIoCtrl->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + if(ptr){ + int32_t payload_len = 0; + u32dptr = (uint32_t*)(ptr); + if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){ + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + int32_t parm_size; + + memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + + switch(pRbElm->compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: + parm_size = 1; + break; + case XRAN_COMPMETHOD_MODULATION: + parm_size = 0; + break; + default: + parm_size = 0; + } + + bfp_decom_req.data_in = (int8_t *)u32dptr; + bfp_decom_req.numRBs = pRbElm->nRBSize; + bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size) * pRbElm->nRBSize; + bfp_decom_req.compMethod = pRbElm->compMethod; + bfp_decom_req.iqWidth = pRbElm->iqWidth; + bfp_decom_req.reMask = pRbElm->reMask; + bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor; + + bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); + bfp_decom_rsp.len = 0; + + xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp); + payload_len = bfp_decom_rsp.len; + + } else { + u32dptr = (uint32_t*)(ptr); + memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L); + } + }else { + printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id); + } + } + else + { + p_sec_desc = pRbElm->p_sec_desc[sym_id][0]; + if(p_iq->p_rx_log_buffer[flowId] && p_sec_desc){ + if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){ + pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId]; + ptr = p_sec_desc->pData; + if(ptr){ + int32_t payload_len = 0; + u32dptr = (uint32_t*)(ptr); + if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){ + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + int32_t parm_size; + + memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + switch(pRbElm->compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: + parm_size = 1; + break; + case XRAN_COMPMETHOD_MODULATION: + parm_size = 0; + break; + default: + parm_size = 0; + } + + bfp_decom_req.data_in = (int8_t *)u32dptr; + bfp_decom_req.numRBs = pRbElm->nRBSize; + bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize; + bfp_decom_req.compMethod = pRbElm->compMethod; + bfp_decom_req.iqWidth = pRbElm->iqWidth; + bfp_decom_req.reMask = pRbElm->reMask; + bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor; + + bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); + bfp_decom_rsp.len = 0; + + xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp); + payload_len = bfp_decom_rsp.len; + + } + else { + memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4); + } + } + else { + printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id); + } + } + } + else + printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId); + } + } + } else { + for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) { + pRbElm = &pRbMap->prbMap[idxElm]; + p_sec_desc = pRbElm->p_sec_desc[sym_id][0]; + if(p_iq->p_rx_log_buffer[flowId] && p_sec_desc){ + if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){ + pos = ((char*)p_iq->p_rx_log_buffer[flowId]) + p_iq->rx_log_buffer_position[flowId]; + ptr = p_sec_desc->pData; + if(ptr){ + int32_t payload_len = 0; + u32dptr = (uint32_t*)(ptr); + if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){ + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + int32_t parm_size; + + memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + switch(pRbElm->compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: + parm_size = 1; + break; + case XRAN_COMPMETHOD_MODULATION: + parm_size = 0; + break; + default: + parm_size = 0; + } + + bfp_decom_req.data_in = (int8_t *)u32dptr; + bfp_decom_req.numRBs = pRbElm->nRBSize; + bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize; + bfp_decom_req.compMethod = pRbElm->compMethod; + bfp_decom_req.iqWidth = pRbElm->iqWidth; + bfp_decom_req.reMask = pRbElm->reMask; + bfp_decom_req.ScaleFactor= pRbElm->ScaleFactor; + + bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); + bfp_decom_rsp.len = 0; + + xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp); + payload_len = bfp_decom_rsp.len; + + } else { + memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4); + } + } + else { + // printf("%s:%d [%d][%d][%d][%d]ptr ==NULL\n", __FUNCTION__, __LINE__, tti,cc_id,ant_id, sym_id); + } + } + } + else + printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId); + } + } + p_iq->rx_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; + + if(p_iq->rx_log_buffer_position[flowId] >= p_iq->rx_log_buffer_size[flowId]) + p_iq->rx_log_buffer_position[flowId] = 0; + } + + + flowId = p_o_xu_cfg->numAxc * cc_id + ant_id; + prach_len = (3 * pXranConf->ru_conf.iqWidth_PRACH) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/ + for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { + + if(p_iq->p_prach_log_buffer[flowId]) { + pos = ((char*)p_iq->p_prach_log_buffer[flowId]) + p_iq->prach_log_buffer_position[flowId]; + ptr = psIoCtrl->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + if(ptr) { + int32_t compMethod = pXranConf->ru_conf.compMeth_PRACH; + + if(compMethod == XRAN_COMPMETHOD_NONE) { + memcpy(pos, (uint32_t *)(ptr), prach_len); + } + else { + struct xranlib_decompress_request decomp_req; + struct xranlib_decompress_response decomp_rsp; + int32_t parm_size; + + memset(&decomp_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&decomp_rsp, 0, sizeof(struct xranlib_decompress_response)); + + switch(compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + + decomp_req.data_in = (int8_t *)ptr; + decomp_req.numRBs = pXranConf->prach_conf.numPrbc; + decomp_req.len = (3 * pXranConf->ru_conf.iqWidth_PRACH + parm_size) * pXranConf->prach_conf.numPrbc; /* 12RE*2pairs/8bits (12*2/8=3)*/ + decomp_req.compMethod = compMethod; + decomp_req.iqWidth = pXranConf->ru_conf.iqWidth_PRACH; + decomp_req.ScaleFactor = 0; /* TODO */ + decomp_req.reMask = 0xfff; /* TODO */ + + decomp_rsp.data_out = (int16_t *)pos; + decomp_rsp.len = 0; + + xranlib_decompress(&decomp_req, &decomp_rsp); + } + } + + p_iq->prach_log_buffer_position[flowId] += prach_len; + + if(p_iq->prach_log_buffer_position[flowId] >= p_iq->prach_log_buffer_size[flowId]) + p_iq->prach_log_buffer_position[flowId] = 0; + } /* if(p_iq->p_prach_log_buffer[flowId]) */ + } /* for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) */ + } /* for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++) */ + + /* SRS RX for O-DU only */ + if(p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) { + for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++) { + int32_t idxElm = 0; + struct xran_prb_map *pRbMap = NULL; + struct xran_prb_elm *pRbElm = NULL; + struct xran_section_desc *p_sec_desc = NULL; + pRbMap = (struct xran_prb_map *) psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + if(pRbMap == NULL) { + printf("pRbMap == NULL\n"); + exit(-1); + } + flowId = p_o_xu_cfg->antElmTRx*cc_id + ant_id; + if(p_iq->p_srs_log_buffer[flowId]) { + for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) { + pRbElm = &pRbMap->prbMap[0]; + /*if(pRbMap->nPrbElm == 1) { + if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb) { + pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + p_iq->srs_log_buffer_position[flowId]; + ptr = psIoCtrl->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + if(ptr){ + int32_t payload_len = 0; + u32dptr = (uint32_t*)(ptr); + if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){ + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + int32_t parm_size; + + memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + switch(pRbElm->compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: + parm_size = 1; + break; + case XRAN_COMPMETHOD_MODULATION: + parm_size = 0; + break; + default: + parm_size = 0; + } + + bfp_decom_req.data_in = (int8_t *)u32dptr; + bfp_decom_req.numRBs = pRbElm->nRBSize; + bfp_decom_req.len = (3* pRbElm->iqWidth + parm_size)*pRbElm->nRBSize; + bfp_decom_req.compMethod = pRbElm->compMethod; + bfp_decom_req.iqWidth = pRbElm->iqWidth; + + bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); + bfp_decom_rsp.len = 0; + + xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp); + payload_len = bfp_decom_rsp.len; + + } else { + u32dptr = (uint32_t*)(ptr); + memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L); + } + }else { + printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id); + } + } + } else*/ { + for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) { + pRbElm = &pRbMap->prbMap[idxElm]; + p_sec_desc = pRbElm->p_sec_desc[sym_id][0]; + if(p_iq->p_srs_log_buffer[flowId] && p_sec_desc) { + if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb) { + pos = ((char*)p_iq->p_srs_log_buffer[flowId]) + p_iq->srs_log_buffer_position[flowId]; + ptr = p_sec_desc->pData; + if(ptr) { + int32_t payload_len = 0; + u32dptr = (uint32_t*)(ptr); + if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE) { + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + int32_t parm_size; + + memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + switch(pRbElm->compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: + parm_size = 1; + break; + case XRAN_COMPMETHOD_MODULATION: + parm_size = 0; + break; + default: + parm_size = 0; + } + + bfp_decom_req.data_in = (int8_t *)u32dptr; + bfp_decom_req.numRBs = pRbElm->nRBSize; + bfp_decom_req.len = (3 * pRbElm->iqWidth + parm_size)*pRbElm->nRBSize; + bfp_decom_req.compMethod = pRbElm->compMethod; + bfp_decom_req.iqWidth = pRbElm->iqWidth; + + bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); + bfp_decom_rsp.len = 0; + + xranlib_decompress(&bfp_decom_req, &bfp_decom_rsp); + payload_len = bfp_decom_rsp.len; + + } else { + memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4); + } + } + } + } else { + printf("(%d : %d : %d) flowid %d, p_sec_desc is empty\n", tti, sym_id, ant_id,flowId); + } + } + } + p_iq->srs_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; + + if(p_iq->srs_log_buffer_position[flowId] >= p_iq->srs_log_buffer_size[flowId]) + p_iq->srs_log_buffer_position[flowId] = 0; + } + } + } + } + } + } + + return 0; +} + +int32_t +app_io_xran_eAxCid_conf_set(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg) +{ + int32_t shift; + uint16_t mask; + + if(p_s_cfg->DU_Port_ID_bitwidth && p_s_cfg->BandSector_ID_bitwidth && p_s_cfg->CC_ID_bitwidth + && p_s_cfg->RU_Port_ID_bitwidth && + (p_s_cfg->DU_Port_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + + p_s_cfg->RU_Port_ID_bitwidth) == 16 /* eAxC ID subfields are 16 bits */ + ){ /* bit mask provided */ + + mask = 0; + p_eAxC_cfg->bit_ruPortId = 0; + for (shift = 0; shift < p_s_cfg->RU_Port_ID_bitwidth; shift++){ + mask |= 1 << shift; + } + p_eAxC_cfg->mask_ruPortId = mask; + + p_eAxC_cfg->bit_ccId = p_s_cfg->RU_Port_ID_bitwidth; + mask = 0; + for (shift = p_s_cfg->RU_Port_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift++){ + mask |= 1 << shift; + } + p_eAxC_cfg->mask_ccId = mask; + + + p_eAxC_cfg->bit_bandSectorId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; + mask = 0; + for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; shift++){ + mask |= 1 << shift; + } + p_eAxC_cfg->mask_bandSectorId = mask; + + p_eAxC_cfg->bit_cuPortId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; + mask = 0; + for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; + shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->DU_Port_ID_bitwidth; shift++){ + mask |= 1 << shift; + } + p_eAxC_cfg->mask_cuPortId = mask; + + + } else { /* bit mask config is not provided */ + switch (p_s_cfg->xranCat){ + case XRAN_CATEGORY_A: { + p_eAxC_cfg->mask_cuPortId = 0xf000; + p_eAxC_cfg->mask_bandSectorId = 0x0f00; + p_eAxC_cfg->mask_ccId = 0x00f0; + p_eAxC_cfg->mask_ruPortId = 0x000f; + p_eAxC_cfg->bit_cuPortId = 12; + p_eAxC_cfg->bit_bandSectorId = 8; + p_eAxC_cfg->bit_ccId = 4; + p_eAxC_cfg->bit_ruPortId = 0; + break; + } + case XRAN_CATEGORY_B: { + p_eAxC_cfg->mask_cuPortId = 0xf000; + p_eAxC_cfg->mask_bandSectorId = 0x0c00; + p_eAxC_cfg->mask_ccId = 0x0300; + p_eAxC_cfg->mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */ + p_eAxC_cfg->bit_cuPortId = 12; + p_eAxC_cfg->bit_bandSectorId = 10; + p_eAxC_cfg->bit_ccId = 8; + p_eAxC_cfg->bit_ruPortId = 0; + break; + } + default: + rte_panic("Incorrect Category\n"); + } + } + + if(p_s_cfg->xranCat == XRAN_CATEGORY_A) + p_s_cfg->numUlAxc = p_s_cfg->numAxc; + + printf("bit_cuPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_cuPortId, p_eAxC_cfg->mask_cuPortId); + printf("bit_bandSectorId %2d mask 0x%04x\n",p_eAxC_cfg->bit_bandSectorId, p_eAxC_cfg->mask_bandSectorId); + printf("bit_ccId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ccId, p_eAxC_cfg->mask_ccId); + printf("ruPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ruPortId, p_eAxC_cfg->mask_ruPortId); + + return 0; +} + +int32_t +app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init, struct xran_fh_config* p_xran_fh_cfg) +{ + int32_t ret = 0; + int32_t i = 0; + int32_t o_xu_id = 0; + uint32_t nCenterFreq = 0; + struct xran_prb_map* pRbMap = NULL; + + memset(p_xran_fh_cfg, 0, sizeof(struct xran_fh_config)); + + o_xu_id = p_o_xu_cfg->o_xu_id; + + p_xran_fh_cfg->nDLRBs = app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA); + p_xran_fh_cfg->nULRBs = app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA); + + if(p_o_xu_cfg->DynamicSectionEna == 0){ + pRbMap = p_o_xu_cfg->p_PrbMapDl; + + pRbMap->dir = XRAN_DIR_DL; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = 0; + pRbMap->ru_port_id = 0; + pRbMap->tti_id = 0; + pRbMap->start_sym_id = 0; + pRbMap->nPrbElm = 1; + pRbMap->prbMap[0].nStartSymb = 0; + pRbMap->prbMap[0].numSymb = 14; + pRbMap->prbMap[0].nRBStart = 0; + pRbMap->prbMap[0].nRBSize = p_xran_fh_cfg->nDLRBs; + pRbMap->prbMap[0].nBeamIndex = 0; + pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; + pRbMap->prbMap[0].iqWidth = 16; + + pRbMap = p_o_xu_cfg->p_PrbMapUl; + pRbMap->dir = XRAN_DIR_UL; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = 0; + pRbMap->ru_port_id = 0; + pRbMap->tti_id = 0; + pRbMap->start_sym_id = 0; + pRbMap->nPrbElm = 1; + pRbMap->prbMap[0].nStartSymb = 0; + pRbMap->prbMap[0].numSymb = 14; + pRbMap->prbMap[0].nRBStart = 0; + pRbMap->prbMap[0].nRBSize = p_xran_fh_cfg->nULRBs; + pRbMap->prbMap[0].nBeamIndex = 0; + pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; + pRbMap->prbMap[0].iqWidth = 16; + } else { + pRbMap = p_o_xu_cfg->p_PrbMapDl; + + pRbMap->dir = XRAN_DIR_DL; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = 0; + pRbMap->ru_port_id = 0; + pRbMap->tti_id = 0; + pRbMap->start_sym_id = 0; + + pRbMap = p_o_xu_cfg->p_PrbMapUl; + pRbMap->dir = XRAN_DIR_UL; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = 0; + pRbMap->ru_port_id = 0; + pRbMap->tti_id = 0; + pRbMap->start_sym_id = 0; + + pRbMap = p_o_xu_cfg->p_PrbMapSrs; + pRbMap->dir = XRAN_DIR_UL; + pRbMap->xran_port = 0; + pRbMap->band_id = 0; + pRbMap->cc_id = 0; + pRbMap->ru_port_id = 0; + pRbMap->tti_id = 0; + pRbMap->start_sym_id = 0; + } + + p_xran_fh_cfg->sector_id = 0; + p_xran_fh_cfg->dpdk_port = o_xu_id; + p_xran_fh_cfg->nCC = p_o_xu_cfg->numCC; + p_xran_fh_cfg->neAxc = p_o_xu_cfg->numAxc; + p_xran_fh_cfg->neAxcUl = p_o_xu_cfg->numUlAxc; + p_xran_fh_cfg->nAntElmTRx = p_o_xu_cfg->antElmTRx; + + p_xran_fh_cfg->frame_conf.nFrameDuplexType = p_o_xu_cfg->nFrameDuplexType; + p_xran_fh_cfg->frame_conf.nNumerology = p_o_xu_cfg->mu_number; + p_xran_fh_cfg->frame_conf.nTddPeriod = p_o_xu_cfg->nTddPeriod; + + for (i = 0; i < p_o_xu_cfg->nTddPeriod; i++){ + p_xran_fh_cfg->frame_conf.sSlotConfig[i] = p_o_xu_cfg->sSlotConfig[i]; + } + + p_xran_fh_cfg->prach_conf.nPrachSubcSpacing = p_o_xu_cfg->mu_number; + p_xran_fh_cfg->prach_conf.nPrachFreqStart = 0; + p_xran_fh_cfg->prach_conf.nPrachFilterIdx = XRAN_FILTERINDEX_PRACH_ABC; + p_xran_fh_cfg->prach_conf.nPrachConfIdx = p_o_xu_cfg->prachConfigIndex; + p_xran_fh_cfg->prach_conf.nPrachFreqOffset = -792; + + p_xran_fh_cfg->srs_conf.symbMask = p_o_xu_cfg->srsSymMask; + p_xran_fh_cfg->srs_conf.eAxC_offset = 2 * p_o_xu_cfg->numAxc; /* PUSCH, PRACH, SRS */ + + p_xran_fh_cfg->ru_conf.xranTech = p_o_xu_cfg->xranTech; + p_xran_fh_cfg->ru_conf.xranCompHdrType = p_o_xu_cfg->CompHdrType; + p_xran_fh_cfg->ru_conf.xranCat = p_o_xu_cfg->xranCat; + p_xran_fh_cfg->ru_conf.iqWidth = p_o_xu_cfg->p_PrbMapDl->prbMap[0].iqWidth; + + if (p_o_xu_cfg->compression == 0) + p_xran_fh_cfg->ru_conf.compMeth = XRAN_COMPMETHOD_NONE; + else + p_xran_fh_cfg->ru_conf.compMeth = XRAN_COMPMETHOD_BLKFLOAT; + + p_xran_fh_cfg->ru_conf.compMeth_PRACH = p_o_xu_cfg->prachCompMethod; + if (p_o_xu_cfg->prachCompMethod == 0) + p_o_xu_cfg->prachiqWidth = 16; + p_xran_fh_cfg->ru_conf.iqWidth_PRACH = p_o_xu_cfg->prachiqWidth; + + + p_xran_fh_cfg->ru_conf.fftSize = 0; + while (p_o_xu_cfg->nULFftSize >>= 1) + ++p_xran_fh_cfg->ru_conf.fftSize; + + p_xran_fh_cfg->ru_conf.byteOrder = (p_o_xu_cfg->nebyteorderswap == 1) ? XRAN_NE_BE_BYTE_ORDER : XRAN_CPU_LE_BYTE_ORDER ; + p_xran_fh_cfg->ru_conf.iqOrder = (p_o_xu_cfg->iqswap == 1) ? XRAN_Q_I_ORDER : XRAN_I_Q_ORDER; + + printf("FFT Order %d\n", p_xran_fh_cfg->ru_conf.fftSize); + + nCenterFreq = p_o_xu_cfg->nDLAbsFrePointA + (((p_xran_fh_cfg->nDLRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(p_o_xu_cfg->mu_number)); + p_xran_fh_cfg->nDLCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq); + printf("DL center freq %d DL NR-ARFCN %d\n", nCenterFreq, p_xran_fh_cfg->nDLCenterFreqARFCN); + + nCenterFreq = p_o_xu_cfg->nULAbsFrePointA + (((p_xran_fh_cfg->nULRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(p_o_xu_cfg->mu_number)); + p_xran_fh_cfg->nULCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq); + printf("UL center freq %d UL NR-ARFCN %d\n", nCenterFreq, p_xran_fh_cfg->nULCenterFreqARFCN); + + p_xran_fh_cfg->bbdev_dec = NULL; + p_xran_fh_cfg->bbdev_enc = NULL; + + p_xran_fh_cfg->log_level = 1; + + p_xran_fh_cfg->max_sections_per_slot = RTE_MAX(p_o_xu_cfg->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT); + p_xran_fh_cfg->max_sections_per_symbol = RTE_MAX(p_o_xu_cfg->max_sections_per_symbol, XRAN_MIN_SECTIONS_PER_SLOT); + + printf("Max Sections: %d per symb %d per slot\n", p_xran_fh_cfg->max_sections_per_slot, p_xran_fh_cfg->max_sections_per_symbol); + if(p_o_xu_cfg->maxFrameId) + p_xran_fh_cfg->ru_conf.xran_max_frame = p_o_xu_cfg->maxFrameId; + + p_xran_fh_cfg->Tadv_cp_dl = p_o_xu_cfg->Tadv_cp_dl; + p_xran_fh_cfg->T2a_min_cp_dl = p_o_xu_cfg->T2a_min_cp_dl; + p_xran_fh_cfg->T2a_max_cp_dl = p_o_xu_cfg->T2a_max_cp_dl; + p_xran_fh_cfg->T2a_min_cp_ul = p_o_xu_cfg->T2a_min_cp_ul; + p_xran_fh_cfg->T2a_max_cp_ul = p_o_xu_cfg->T2a_max_cp_ul; + p_xran_fh_cfg->T2a_min_up = p_o_xu_cfg->T2a_min_up; + p_xran_fh_cfg->T2a_max_up = p_o_xu_cfg->T2a_max_up; + p_xran_fh_cfg->Ta3_min = p_o_xu_cfg->Ta3_min; + p_xran_fh_cfg->Ta3_max = p_o_xu_cfg->Ta3_max; + p_xran_fh_cfg->T1a_min_cp_dl = p_o_xu_cfg->T1a_min_cp_dl; + p_xran_fh_cfg->T1a_max_cp_dl = p_o_xu_cfg->T1a_max_cp_dl; + p_xran_fh_cfg->T1a_min_cp_ul = p_o_xu_cfg->T1a_min_cp_ul; + p_xran_fh_cfg->T1a_max_cp_ul = p_o_xu_cfg->T1a_max_cp_ul; + p_xran_fh_cfg->T1a_min_up = p_o_xu_cfg->T1a_min_up; + p_xran_fh_cfg->T1a_max_up = p_o_xu_cfg->T1a_max_up; + p_xran_fh_cfg->Ta4_min = p_o_xu_cfg->Ta4_min; + p_xran_fh_cfg->Ta4_max = p_o_xu_cfg->Ta4_max; + + p_xran_fh_cfg->enableCP = p_o_xu_cfg->enableCP; + p_xran_fh_cfg->prachEnable = p_o_xu_cfg->enablePrach; + p_xran_fh_cfg->srsEnable = p_o_xu_cfg->enableSrs; + p_xran_fh_cfg->puschMaskEnable = p_o_xu_cfg->puschMaskEnable; + p_xran_fh_cfg->puschMaskSlot = p_o_xu_cfg->puschMaskSlot; + p_xran_fh_cfg->debugStop = p_o_xu_cfg->debugStop; + p_xran_fh_cfg->debugStopCount = p_o_xu_cfg->debugStopCount; + p_xran_fh_cfg->DynamicSectionEna = p_o_xu_cfg->DynamicSectionEna; + p_xran_fh_cfg->GPS_Alpha = p_o_xu_cfg->GPS_Alpha; + p_xran_fh_cfg->GPS_Beta = p_o_xu_cfg->GPS_Beta; + + p_xran_fh_cfg->cp_vlan_tag = p_o_xu_cfg->cp_vlan_tag; + p_xran_fh_cfg->up_vlan_tag = p_o_xu_cfg->up_vlan_tag; + + return ret; + +} + +int32_t +app_io_xran_fh_init_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init) +{ + int32_t ret = 0; + int32_t i = 0; + int32_t o_xu_id = 0; + int32_t pf_link_id = 0; + int32_t num_vfs_cu_p = 2; + void * ptr = NULL; + + memset(p_xran_fh_init, 0, sizeof(struct xran_fh_init)); + + if(p_o_xu_cfg->appMode == APP_O_DU) { + printf("set O-DU\n"); + p_xran_fh_init->io_cfg.id = 0;/* O-DU */ + p_xran_fh_init->io_cfg.core = p_use_cfg->io_core; + p_xran_fh_init->io_cfg.system_core = p_use_cfg->system_core; + p_xran_fh_init->io_cfg.pkt_proc_core = p_use_cfg->io_worker; /* do not start */ + p_xran_fh_init->io_cfg.pkt_proc_core_64_127 = p_use_cfg->io_worker_64_127; + p_xran_fh_init->io_cfg.pkt_aux_core = 0; /* do not start*/ + p_xran_fh_init->io_cfg.timing_core = p_use_cfg->io_core; + p_xran_fh_init->io_cfg.dpdkIoVaMode = p_use_cfg->iova_mode; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].initiator_en = p_use_cfg->owdmInitEn; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].measMethod = p_use_cfg->owdmMeasMeth; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].numberOfSamples = p_use_cfg->owdmNumSamps; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].filterType = p_use_cfg->owdmFltType; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].responseTo = p_use_cfg->owdmRspTo; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].measState = p_use_cfg->owdmMeasState; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].measId = p_use_cfg->owdmMeasId; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].owdm_enable = p_use_cfg->owdmEnable; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_DU].owdm_PlLength = p_use_cfg->owdmPlLength; + + } else { + printf("set O-RU\n"); + p_xran_fh_init->io_cfg.id = 1; /* O-RU*/ + p_xran_fh_init->io_cfg.core = p_use_cfg->io_core; + p_xran_fh_init->io_cfg.system_core = p_use_cfg->system_core; + p_xran_fh_init->io_cfg.pkt_proc_core = p_use_cfg->io_worker; /* do not start */ + p_xran_fh_init->io_cfg.pkt_aux_core = 0; /* do not start */ + p_xran_fh_init->io_cfg.timing_core = p_use_cfg->io_core; + p_xran_fh_init->io_cfg.dpdkIoVaMode = p_use_cfg->iova_mode; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].initiator_en = p_use_cfg->owdmInitEn; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].measMethod = p_use_cfg->owdmMeasMeth; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].numberOfSamples = p_use_cfg->owdmNumSamps; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].filterType = p_use_cfg->owdmFltType; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].responseTo = p_use_cfg->owdmRspTo; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].measState = p_use_cfg->owdmMeasState; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].measId = p_use_cfg->owdmMeasId; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].owdm_enable = p_use_cfg->owdmEnable; + p_xran_fh_init->io_cfg.eowd_cmn[APP_O_RU].owdm_PlLength = p_use_cfg->owdmPlLength; + } + + p_xran_fh_init->io_cfg.io_sleep = p_use_cfg->io_sleep; + p_xran_fh_init->io_cfg.dpdkMemorySize = p_use_cfg->dpdk_mem_sz; + p_xran_fh_init->io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED; + + p_xran_fh_init->xran_ports = p_use_cfg->oXuNum; + p_xran_fh_init->io_cfg.nEthLinePerPort = p_use_cfg->EthLinesNumber; + p_xran_fh_init->io_cfg.nEthLineSpeed = p_use_cfg->EthLinkSpeed; + + app_io_xran_eAxCid_conf_set(&p_xran_fh_init->eAxCId_conf, p_o_xu_cfg); + i = 0; + + if(p_use_cfg->one_vf_cu_plane == 1){ + num_vfs_cu_p = 1; + } + + for(o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum; o_xu_id++ ) { /* all O-XU */ + for(pf_link_id = 0; pf_link_id < p_use_cfg->EthLinesNumber && pf_link_id < XRAN_ETH_PF_LINKS_NUM; pf_link_id++ ) { /* all PF ports for each O-XU */ + if(num_vfs_cu_p*i < (XRAN_VF_MAX - 1)) { + p_xran_fh_init->io_cfg.dpdk_dev[num_vfs_cu_p*i] = &p_use_cfg->o_xu_pcie_bus_addr[o_xu_id][num_vfs_cu_p*pf_link_id][0]; /* U-Plane */ + rte_ether_addr_copy(&p_use_cfg->remote_o_xu_addr[o_xu_id][num_vfs_cu_p*pf_link_id], &p_use_cfg->remote_o_xu_addr_copy[num_vfs_cu_p*i]); + printf("VF[%d] %s\n",num_vfs_cu_p*i, p_xran_fh_init->io_cfg.dpdk_dev[num_vfs_cu_p*i]); + if(p_use_cfg->one_vf_cu_plane == 0){ + p_xran_fh_init->io_cfg.dpdk_dev[num_vfs_cu_p*i+1] = &p_use_cfg->o_xu_pcie_bus_addr[o_xu_id][num_vfs_cu_p*pf_link_id+1][0]; /* C-Plane */ + rte_ether_addr_copy(&p_use_cfg->remote_o_xu_addr[o_xu_id][num_vfs_cu_p*pf_link_id+1], &p_use_cfg->remote_o_xu_addr_copy[num_vfs_cu_p*i+1]); + printf("VF[%d] %s\n",num_vfs_cu_p*i+1, p_xran_fh_init->io_cfg.dpdk_dev[num_vfs_cu_p*i+1]); + } + i++; + } else { + break; + } + } + } + + p_xran_fh_init->io_cfg.one_vf_cu_plane = p_use_cfg->one_vf_cu_plane; + + if(p_xran_fh_init->io_cfg.one_vf_cu_plane) { + p_use_cfg->num_vfs = i; + } else { + p_use_cfg->num_vfs = 2*i; + } + printf("p_use_cfg->num_vfs %d\n", p_use_cfg->num_vfs); + printf("p_use_cfg->num_rxq %d\n", p_use_cfg->num_rxq); + + p_xran_fh_init->io_cfg.num_vfs = p_use_cfg->num_vfs; + p_xran_fh_init->io_cfg.num_rxq = p_use_cfg->num_rxq; + p_xran_fh_init->mtu = p_o_xu_cfg->mtu; + if(p_use_cfg->appMode == APP_O_DU){ + p_xran_fh_init->p_o_du_addr = (int8_t *)p_o_xu_cfg->o_du_addr; + p_xran_fh_init->p_o_ru_addr = (int8_t *)p_use_cfg->remote_o_xu_addr_copy; + } else { + p_xran_fh_init->p_o_du_addr = (int8_t *)p_use_cfg->remote_o_xu_addr_copy; + p_xran_fh_init->p_o_ru_addr = (int8_t *)p_o_xu_cfg->o_ru_addr; + } + + snprintf(p_use_cfg->prefix_name, sizeof(p_use_cfg->prefix_name), "wls_%d",p_use_cfg->instance_id); + p_xran_fh_init->filePrefix = p_use_cfg->prefix_name; + p_xran_fh_init->totalBfWeights = p_o_xu_cfg->totalBfWeights; + + + for(o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum && o_xu_id < XRAN_PORTS_NUM; o_xu_id++ ) { /* all O-XU */ + if(p_o_xu_buff[o_xu_id] == NULL) { + ptr = _mm_malloc(sizeof(struct o_xu_buffers), 256); + if (ptr == NULL) { + rte_panic("_mm_malloc: Can't allocate %lu bytes\n", sizeof(struct o_xu_buffers)); + } + p_o_xu_buff[o_xu_id] = (struct o_xu_buffers*)ptr; + } + + p_o_xu_cfg->p_buff = p_o_xu_buff[o_xu_id]; + p_o_xu_cfg++; + } + + return ret; +} + +int32_t +app_io_xran_buffers_max_sz_set (RuntimeConfig* p_o_xu_cfg) +{ + uint32_t xran_max_sections_per_slot = RTE_MAX(p_o_xu_cfg->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT); + + if (p_o_xu_cfg->mu_number <= 1){ + if (p_o_xu_cfg->mtu > XRAN_MTU_DEFAULT) { + nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/ + nFpgaToSW_PRACH_RxBufferLen = 8192; + nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */ + xran_max_sections_per_slot* (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + } else { + nFpgaToSW_FTH_RxBufferLen = XRAN_MTU_DEFAULT; /* 273*12*4 + 64*/ + nFpgaToSW_PRACH_RxBufferLen = XRAN_MTU_DEFAULT; + nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */ + xran_max_sections_per_slot* (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + } + } else if (p_o_xu_cfg->mu_number == 3) { + if (p_o_xu_cfg->mtu > XRAN_MTU_DEFAULT) { + nFpgaToSW_FTH_RxBufferLen = 3328; + nFpgaToSW_PRACH_RxBufferLen = 8192; + nSW_ToFpga_FTH_TxBufferLen = 3328 + + xran_max_sections_per_slot * (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + } else { + nFpgaToSW_FTH_RxBufferLen = XRAN_MTU_DEFAULT; + nFpgaToSW_PRACH_RxBufferLen = XRAN_MTU_DEFAULT; + nSW_ToFpga_FTH_TxBufferLen = 3328 + + xran_max_sections_per_slot * (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + } + } else { + printf("given numerology is not supported %d\n", p_o_xu_cfg->mu_number); + exit(-1); + } + printf("nSW_ToFpga_FTH_TxBufferLen %d\n", nSW_ToFpga_FTH_TxBufferLen); + return 0; +} diff --git a/fhi_lib/app/src/app_io_fh_xran.h b/fhi_lib/app/src/app_io_fh_xran.h new file mode 100644 index 0000000..652db55 --- /dev/null +++ b/fhi_lib/app/src/app_io_fh_xran.h @@ -0,0 +1,166 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief Header file to interface implementation to ORAN FH from Application side + * @file app_iof_fh_xran.h + * @ingroup xran + * @author Intel Corporation + * + **/ + +#ifndef _APP_IO_FH_H_ +#define _APP_IO_FH_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include "config.h" + +#include "xran_fh_o_du.h" +#include "xran_pkt_up.h" + +#define MAX_PKT_BURST (448+4) /* 4x14x8 */ +#define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST + +#define NUM_OF_SUBFRAME_PER_FRAME (10) + +#define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024 +#define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024 +#define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024 +#define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192) + +extern void* app_io_xran_handle; +extern struct xran_fh_init app_io_xran_fh_init; +extern struct xran_fh_config app_io_xran_fh_config[XRAN_PORTS_NUM]; + +typedef struct +{ + uint32_t phaseFlag :1; + uint32_t NRARFCN :22; + uint32_t SULFreShift :1; + uint32_t SULFlag :1; + uint32_t rsv :7; +} FPGAPhaseCompCfg; + +typedef enum { + XRANFTHTX_OUT = 0, + XRANFTHTX_PRB_MAP_OUT, + XRANFTHTX_SEC_DESC_OUT, + XRANFTHRX_IN, + XRANFTHRX_PRB_MAP_IN, + XRANFTHTX_SEC_DESC_IN, + XRANFTHRACH_IN, + XRANSRS_IN, + XRANSRS_PRB_MAP_IN, + XRANSRS_SEC_DESC_IN, + MAX_SW_XRAN_INTERFACE_NUM +} SWXRANInterfaceTypeEnum; + +struct xran_io_buf_ctrl { + /* -1-this subframe is not used in current frame format + 0-this subframe can be transmitted, i.e., data is ready + 1-this subframe is waiting transmission, i.e., data is not ready + 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1, + set bValid to 10. + */ + int32_t bValid ; // when UL rx, it is subframe index. + int32_t nSegToBeGen; + int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE + // -1 means that DL packet to be transmitted is not ready in BS + int32_t nSegTransferred; // number of data segments has been transmitted or received + struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool + struct xran_buffer_list sBufferList; +}; + +struct xran_io_shared_ctrl { + /* io struct */ + struct xran_io_buf_ctrl sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrlDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + + /* Cat B */ + struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + + /* buffers lists */ + struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + + /* Cat B SRS buffers */ + struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; +}; + +struct bbu_xran_io_if { + void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /**< instance per ORAN port per CC */ + uint32_t nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; /**< unique buffer pool */ + uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC */ + + uint16_t DynamicSectionEna; + uint32_t nPhaseCompFlag; + + int32_t num_o_ru; + int32_t num_cc_per_port[XRAN_PORTS_NUM]; + int32_t map_cell_id2port[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + + struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU port */ + + struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; + struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; +}; + +struct bbu_xran_io_if* app_io_xran_if_alloc(void); +struct bbu_xran_io_if* app_io_xran_if_get(void); +void app_io_xran_if_free(void); +struct xran_io_shared_ctrl * app_io_xran_if_ctrl_get(uint32_t o_xu_id); +int32_t app_io_xran_sfidx_get(uint8_t nNrOfSlotInSf); + +int32_t app_io_xran_interface(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg, UsecaseConfig* p_use_cfg); +int32_t app_io_xran_iq_content_init(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg); +int32_t app_io_xran_iq_content_get(uint32_t o_xu_id, RuntimeConfig *p_o_xu_cfg); +int32_t app_io_xran_eAxCid_conf_set(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg); +int32_t app_io_xran_fh_config_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init, struct xran_fh_config* p_xran_fh_cfg); +int32_t app_io_xran_fh_init_init(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init); +int32_t app_io_xran_buffers_max_sz_set (RuntimeConfig* p_o_xu_cfg); + +int32_t app_io_xran_dl_tti_call_back(void * param); +int32_t app_io_xran_ul_half_slot_call_back(void * param); +int32_t app_io_xran_ul_full_slot_call_back(void * param); +int32_t app_io_xran_ul_custom_sym_call_back(void * param, struct xran_sense_of_time* time); + +void app_io_xran_if_stop(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _APP_IO_FH_H_ */ + diff --git a/fhi_lib/app/src/app_profile_xran.c b/fhi_lib/app/src/app_profile_xran.c new file mode 100644 index 0000000..377aa86 --- /dev/null +++ b/fhi_lib/app/src/app_profile_xran.c @@ -0,0 +1,374 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include "common.h" +#include "xran_fh_o_du.h" +#include "xran_pkt.h" +#include "xran_pkt_up.h" +#include "xran_cp_api.h" +#include "xran_up_api.h" + +#include "xran_mlog_lnx.h" +#include "app_profile_xran.h" +#include "xran_timer.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_mlog_task_id.h" + +#define XRAN_REPORT_FILE "xran_mlog_stats" + +int32_t xran_init_mlog_stats(char *file, uint64_t nTscFreq); +int32_t xran_get_mlog_stats(char *, UsecaseConfig *, RuntimeConfig *[], struct xran_mlog_times *); + +struct xran_mlog_times mlog_times = {0}; +struct xran_mlog_stats tmp; +uint64_t xran_total_ticks = 0, xran_mlog_time; +uint64_t tWake, tWakePrev = 0; + +extern UsecaseConfig* p_usecaseConfiguration; +extern RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM]; + +#ifdef MLOG_ENABLED +/* + * Covert a test case path into a test case name + * with the last two basenames in the path. + */ +int32_t +test_path_to_name(char *path, char *name) +{ + if (path == NULL || name == NULL) + { + print_err("Null path(%#p) or name(%#p)", path, name); + return -1; + } + + char *dir, *base, *np = strdup(path); + int num=0; + + if (np) + { + base = basename(np); + if (isdigit(*base)) + { + num = atoi(base); + *--base = '\0'; /* trim the last basename */ + base = basename(np); + } + + dir = dirname(np); + sprintf(name, "%s-%s-%d", basename(dir), base, num); + free(np); + return 0; + } + + return -1; +} + + + + +//------------------------------------------------------------------------------------------- +/** @ingroup group_source_flexran_xran + * + * @param[in] nTscFreq Frequency of the Time Stamp Counter (TSC) that the CPU currently is + * programmed with + * @return 0 if SUCCESS + * + * @description + * This function dumps current CPU information onto the XRAN_REPORT_FILE file which is used + * for automation of report generation + * +**/ +//------------------------------------------------------------------------------------------- +int32_t +xran_init_mlog_stats(char *file, uint64_t nTscFreq) +{ + char command[1024]; + FILE *pFile= NULL; + + pFile = fopen(file, "w"); + if (pFile == NULL) + { + printf("1: Cannot open %s to write in phydi_init_mlog_stats\n", file); + return -1; + } + fprintf(pFile, "------------------------------------------------------------------------------------------------------------\n"); + fprintf(pFile, "SYSTEM_PARAMS:\n"); + fprintf(pFile, "TSC_FREQ: %ld\n", nTscFreq); + +#ifdef BBDEV_FEC_ACCL_NR5G + PPHYCFG_VARS pPhyCfgVars = phycfg_get_ctx(); + + if (pPhyCfgVars->dpdkBasebandFecMode == 0) + { + fprintf(pFile, "FEC_OFFLOAD: SOFT_LDPC\n"); + } + else + { + uint32_t nRet = phy_gnb_check_bbdev_hw_type(); + + if (nRet == BBDEV_DEV_NAME_MOUNT_BRYCE) + fprintf(pFile, "FEC_OFFLOAD: MOUNT_BRYCE\n"); + else if (nRet == BBDEV_DEV_NAME_VISTA_CREEK) + fprintf(pFile, "FEC_OFFLOAD: VISTA_CREEK\n"); + else if (nRet == BBDEV_DEV_NAME_SW_LDPC) + fprintf(pFile, "FEC_OFFLOAD: SOFT_LDPC\n"); + else + fprintf(pFile, "FEC_OFFLOAD: UNKNOWN\n"); + } +#else + fprintf(pFile, "FEC_OFFLOAD: TERASIC\n"); +#endif + + fclose(pFile); + pFile = NULL; + usleep(100000); + sprintf(command, "lscpu >> %s", file); + system(command); + usleep(100000); + + pFile = fopen(file, "a"); + if (pFile == NULL) + { + printf("2: Cannot open %s to write in %s\n", file, __FUNCTION__); + return -1; + } + fprintf(pFile, "------------------------------------------------------------------------------------------------------------\n"); + fprintf(pFile, "COMMAND_LINE:\n"); + fclose(pFile); + + usleep(100000); + sprintf(command, "cat /proc/cmdline >> %s", file); + system(command); + usleep(100000); + + pFile = fopen(file, "a"); + if (pFile == NULL) + { + printf("3: Cannot open %s to write in %s\n", file, __FUNCTION__); + return -1; + } + fprintf(pFile, "------------------------------------------------------------------------------------------------------------\n"); + fprintf(pFile, "MEMORY_INFO:\n"); + fclose(pFile); + pFile = NULL; + + usleep(100000); + sprintf(command, "dmidecode -t memory >> %s", file); + system(command); + usleep(100000); + + pFile = fopen(file, "a"); + if (pFile == NULL) + { + printf("4: Cannot open %s to write in %s\n", file, __FUNCTION__); + return -1; + } + fprintf(pFile, "------------------------------------------------------------------------------------------------------------\n"); + fprintf(pFile, "TURBOSTAT_INFO:\n"); + fclose(pFile); + pFile = NULL; + usleep(100000); + sprintf(command, "turbostat --num_iterations 1 --interval 1 -q >> %s", file); + + system(command); + usleep(100000); + + pFile = fopen(file, "a"); + if (pFile == NULL) + { + printf("5: Cannot open %s to write in %s\n", file, __FUNCTION__); + return -1; + } + fprintf(pFile, "---------------------------------------------------------------------------\n"); + fflush(pFile); + fclose(pFile); + + return 0; +} + +int32_t +xran_get_mlog_stats(char *usecase, UsecaseConfig *puConf, RuntimeConfig *psConf[], struct xran_mlog_times *mlog_times_p) +{ + int i, ret=0; + FILE *pFile= NULL; + char stats_file[512]={0}; + struct xran_mlog_stats tti, tmp; + uint32_t ttiDuration = 1000; + + printf("%s: Usecase: %s\n", __FUNCTION__, usecase); + if (puConf == NULL || psConf == NULL || mlog_times_p == NULL) { + print_err("Null puConf(%p), psConf(%p), or mlog_times(%p)!", + puConf, psConf, mlog_times_p); + ret = -1; + goto exit; + } + + MLogPrint((char *)MLogGetFileName()); + + MLogGetStats(PID_TTI_TIMER, &tti.cnt, &tti.max, &tti.min, &tti.avg); + if (tti.cnt != 0) { + sprintf(stats_file, "%s-%s-%s\0", XRAN_REPORT_FILE, (puConf->appMode == APP_O_DU)? "o-du" : "o-ru", usecase); + printf("xran report file: %s\n", stats_file); + ret = xran_init_mlog_stats(stats_file, mlog_times_p->ticks_per_usec); + if (ret != 0) + { + print_err("xran_init_mlog_stats(%s) returned %d!!", stats_file, ret); + ret = -2; + goto exit; + } + + pFile = fopen(stats_file, "a"); + if (pFile == NULL) + { + print_err("Cannot create %s!!", stats_file); + ret = -2; + goto exit; + } + + for (i = 0; i < psConf[0]->mu_number; i++) + ttiDuration = ttiDuration >> 1; + + fprintf(pFile, "All data in this sheet are presented in usecs\n"); + fprintf(pFile, "ORANTest: %s-%s (Num Cells: %d) (Num TTI: %d) (nNumerology: %d) (ttiDuration: %d usecs) (testStats: %d %ld %ld)\n", + (puConf->appMode == APP_O_DU)? "O-DU" : "O-RU", usecase, puConf->oXuNum * psConf[0]->numCC, tti.cnt, psConf[0]->mu_number, ttiDuration, puConf->appMode, mlog_times_p->xran_total_time, mlog_times_p->mlog_total_time); + + double xran_task_type_sum[XRAN_TASK_TYPE_MAX] = {0, 0, 0, 0, 0, 0}; + char * xran_task_type_name[XRAN_TASK_TYPE_MAX] = + { "GNB", "BBDEV", "Timer", "Radio", "CP", "UP" }; +#define NUM_GNB_TASKS (5) +#define NUM_BBDEV_TASKS (4) +#define NUM_TIMER_TASKS (7) +#define NUM_RADIO_TASKS (2) +#define NUM_CP_TASKS (7) +#define NUM_UP_TASKS (5) +#define NUM_ALL_TASKS (NUM_GNB_TASKS+NUM_BBDEV_TASKS+NUM_TIMER_TASKS+NUM_RADIO_TASKS+NUM_CP_TASKS+NUM_UP_TASKS) + struct xran_mlog_taskid xranTasks[NUM_ALL_TASKS] = { + {PID_GNB_PROC_TIMING, XRAN_TASK_TYPE_GNB, "GNB_PROCC_TIMING \0"}, + {PID_GNB_PROC_TIMING_TIMEOUT, XRAN_TASK_TYPE_GNB, "GNB_PROCC_TIMING_TIMEOUT \0"}, + {PID_GNB_SYM_CB, XRAN_TASK_TYPE_GNB, "GNB_SYM_CB \0"}, + {PID_GNB_PRACH_CB, XRAN_TASK_TYPE_GNB, "GNB_PRACH_CB \0"}, + {PID_GNB_SRS_CB, XRAN_TASK_TYPE_GNB, "GNB_SRS_CB \0"}, + + {PID_XRAN_BBDEV_DL_POLL, XRAN_TASK_TYPE_BBDEV, "BBDEV_DL_POLL \0"}, + {PID_XRAN_BBDEV_DL_POLL_DISPATCH, XRAN_TASK_TYPE_BBDEV,"BBDEV_DL_POLL_DISPATCH \0"}, + {PID_XRAN_BBDEV_UL_POLL, XRAN_TASK_TYPE_BBDEV, "BBDEV_UL_POLL \0"}, + {PID_XRAN_BBDEV_UL_POLL_DISPATCH, XRAN_TASK_TYPE_BBDEV,"BBDEV_UL_POLL_DISPATCH \0"}, + + {PID_TTI_TIMER, XRAN_TASK_TYPE_TIMER, "TTI_TIMER \0"}, + {PID_TTI_CB, XRAN_TASK_TYPE_TIMER, "TTI_CB \0"}, + {PID_TIME_SYSTIME_POLL, XRAN_TASK_TYPE_TIMER, "TIME_SYSTIME_POLL \0"}, + {PID_TIME_SYSTIME_STOP, XRAN_TASK_TYPE_TIMER, "TIME_SYSTIME_STOP \0"}, + {PID_TIME_ARM_TIMER, XRAN_TASK_TYPE_TIMER, "TIME_ARM_TIMER \0"}, + {PID_TIME_ARM_TIMER_DEADLINE, XRAN_TASK_TYPE_TIMER, "TIME_ARM_TIMER_DEADLINE \0"}, + {PID_TIME_ARM_USER_TIMER_DEADLINE, XRAN_TASK_TYPE_TIMER,"TIME_ARM_USER_TIMER_DEADLINE \0"}, + + {PID_RADIO_ETH_TX_BURST, XRAN_TASK_TYPE_RADIO, "RADIO_ETH_TX_BURST \0"}, + {PID_RADIO_RX_VALIDATE, XRAN_TASK_TYPE_RADIO, "RADIO_RX_VALIDATE \0"}, + + {PID_PROCESS_TX_SYM, XRAN_TASK_TYPE_CP, "PROCESS_TX_SYM \0"}, + {PID_DISPATCH_TX_SYM, XRAN_TASK_TYPE_CP, "PID_DISPATCH_TX_SYM \0"}, + {PID_CP_DL_CB, XRAN_TASK_TYPE_CP, "PID_CP_DL_CB \0"}, + {PID_CP_UL_CB, XRAN_TASK_TYPE_CP, "PID_CP_UL_CB \0"}, + {PID_SYM_OTA_CB, XRAN_TASK_TYPE_CP, "SYM_OTA_CB \0"}, + {PID_TTI_CB_TO_PHY, XRAN_TASK_TYPE_CP, "TTI_CB_TO_PHY \0"}, + {PID_PROCESS_CP_PKT, XRAN_TASK_TYPE_CP, "PROCESS_CP_PKT \0"}, + + {PID_UP_UL_HALF_DEAD_LINE_CB, XRAN_TASK_TYPE_UP, "UP_UL_HALF_DEAD_LINE_CB \0"}, + {PID_UP_UL_FULL_DEAD_LINE_CB, XRAN_TASK_TYPE_UP, "UP_UL_FULL_DEAD_LINE_CB \0"}, + {PID_UP_UL_USER_DEAD_LINE_CB, XRAN_TASK_TYPE_UP, "UP_UL_USER_DEAD_LINE_CB \0"}, + {PID_PROCESS_UP_PKT, XRAN_TASK_TYPE_UP, "PROCESS_UP_PKT \0"}, + {PID_PROCESS_UP_PKT_SRS, XRAN_TASK_TYPE_UP, "PROCESS_UP_PKT_SRS \0"}, + }; + +#if 1 + fprintf(pFile, "mlog_times: core used/total %lu/%lu, xran %lu(us)\n", + mlog_times_p->core_used_time, mlog_times_p->core_total_time, + mlog_times_p->xran_total_time); +#endif + + fprintf(pFile, "---------------------------------------------------------------------------\n"); + fprintf(pFile, "All task breakdown\n"); + for (i=0; i < NUM_ALL_TASKS; i++) { + struct xran_mlog_taskid *p; + + p = &xranTasks[i]; + MLogGetStats(p->taskId, &tmp.cnt, &tmp.max, &tmp.min, &tmp.avg); + fprintf(pFile, "%4u:%s\t\t:\t%5.2f\n", + p->taskId, p->taskName, tmp.avg); + if (p->taskId != PID_TIME_SYSTIME_POLL) /* Skip TIME_SYSTIME_POLL */ + xran_task_type_sum[p->taskType] += tmp.avg * tmp.cnt; + } + fprintf(pFile, "---------------------------------------------------------------------------\n"); + fprintf(pFile, "Task type breakdown:\t\ttotal time\t(busy %%)\n"); + for (i=0; i < XRAN_TASK_TYPE_MAX; i++) { + char name[32] ={' '}; + + sprintf(name,"%5s tasks", xran_task_type_name[i]); + name[31]='\0'; + fprintf(pFile, "%s:\t\t\t\t\t%7.2f\t(%5.2f%%)\n", + name, xran_task_type_sum[i] / tti.cnt, + xran_task_type_sum[i] * 100 / mlog_times_p->xran_total_time); + } + fprintf(pFile, "---------------------------------------------------------------------------\n\n"); + fprintf(pFile, "====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~====~~~~~~~~====~~~~====~~~~"); + } + +exit: + if (pFile) + { + fflush(pFile); + printf("Closing [%s] ...\n", stats_file); + fclose(pFile); + pFile = NULL; + } + printf("%s: exit: %d\n", __FUNCTION__, ret); + return ret; +} + +int32_t +app_profile_xran_print_mlog_stats(char *usecase_file) +{ + int32_t ret = 0; + char filename[512]; + + printf("core_total_time\t\t%lu,\tcore_used_time\t\t%lu,\t%5.2f%% busy\n", + mlog_times.core_total_time, mlog_times.core_used_time, + ((float)mlog_times.core_used_time * 100.0) / (float)mlog_times.core_total_time); + mlog_times.xran_total_time = xran_total_ticks / MLogGetFreq(); + printf("xran_total_ticks %lu (%lu usec)\n", xran_total_ticks, mlog_times.xran_total_time); + + MLogGetStats(PID_XRAN_MAIN, &tmp.cnt, &tmp.max, &tmp.min, &tmp.avg); + mlog_times.mlog_total_time = tmp.cnt * (uint64_t)tmp.avg; + printf("xran_mlog_time: %lu usec\n", mlog_times.mlog_total_time); + + MLogSetMask(0); /* Turned off MLOG */ + test_path_to_name(usecase_file, filename); + printf("test cases: %s\n", filename); + ret = xran_get_mlog_stats(filename, p_usecaseConfiguration, p_startupConfiguration, &mlog_times); + + return ret; +} + +#endif /* MLOG_ENABLED */ diff --git a/fhi_lib/app/src/app_profile_xran.h b/fhi_lib/app/src/app_profile_xran.h new file mode 100644 index 0000000..dd245a5 --- /dev/null +++ b/fhi_lib/app/src/app_profile_xran.h @@ -0,0 +1,86 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#ifndef _APP_PROFILE_XRAN_H_ +#define _APP_PROFILE_XRAN_H_ + +#include "config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct xran_mlog_times +{ + uint64_t ticks_per_usec; + uint64_t core_total_time; /* in us */ + uint64_t core_used_time; /* in us */ + uint64_t xran_total_time; /* in us */ + uint64_t mlog_total_time; /* in us */ +}; + +struct xran_mlog_stats +{ + uint32_t cnt; + uint32_t max; + uint32_t min; + float avg; +}; + +struct xran_mlog_taskid +{ + uint16_t taskId; + uint16_t taskType; + char taskName[80]; +}; + +enum xran_mlog_task_type { + XRAN_TASK_TYPE_GNB = 0, + XRAN_TASK_TYPE_BBDEV, + XRAN_TASK_TYPE_TIMER, + XRAN_TASK_TYPE_RADIO, + XRAN_TASK_TYPE_CP, + XRAN_TASK_TYPE_UP, + XRAN_TASK_TYPE_MAX, /* The last entry : total# of types */ +}; + +#define XRAN_REPORT_FILE "xran_mlog_stats" + +#ifdef MLOG_ENABLED +int32_t app_profile_xran_print_mlog_stats(char *usecase_file); +#else +#define app_profile_xran_print_mlog_stats(a) +#endif + +#ifndef WIN32 +#ifdef PRINTF_ERR_OK +#define print_err(fmt, args...) printf("%s:[err] " fmt "\n", __FUNCTION__, ## args) +#else /* PRINTF_LOG_OK */ +#define print_err(fmt, args...) +#endif /* PRINTF_LOG_OK */ +#else +#define print_err(fmt, ...) printf("%s:[err] " fmt "\n", __FUNCTION__, __VA_ARGS__) +#endif + +#ifdef __cplusplus +} +#endif + +extern struct xran_mlog_times mlog_times; + +#endif /* _APP_PROFILE_XRAN_ */ diff --git a/fhi_lib/app/src/common.c b/fhi_lib/app/src/common.c index e365cc4..f165ef4 100644 --- a/fhi_lib/app/src/common.c +++ b/fhi_lib/app/src/common.c @@ -21,7 +21,7 @@ #include #include #include - +#include #include "common.h" #include "xran_fh_o_du.h" #include "xran_pkt.h" @@ -32,70 +32,7 @@ #include "xran_mlog_lnx.h" extern enum app_state state; - -int iq_playback_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES; -int iq_playback_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES; - -int iq_bfw_buffer_size_dl = IQ_PLAYBACK_BUFFER_BYTES; -int iq_bfw_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES; - -int iq_srs_buffer_size_ul = IQ_PLAYBACK_BUFFER_BYTES; - -uint8_t numCCPorts = 1; -/* Number of antennas supported by front-end */ - -uint8_t num_eAxc = 4; -/* Number of CPRI ports supported by front-end */ - -int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -int16_t *p_tx_srs_play_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -int32_t tx_srs_play_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -int32_t tx_srs_play_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; - -int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -int16_t *p_srs_log_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -int32_t srs_log_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -int32_t srs_log_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; - -int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; - -int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; - -/* beamforming weights for UL (O-DU) */ -int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -/* beamforming weights for UL (O-DU) */ -int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -/* beamforming weights for UL (O-RU) */ -int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - -/* beamforming weights for UL (O-RU) */ -int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; +struct o_xu_buffers* p_o_xu_buff[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL}; // F1 Tables 38.101-1 Table 5.3.2-1. Maximum transmission bandwidth configuration NRB uint16_t nLteNumRbsPerSymF1[1][4] = diff --git a/fhi_lib/app/src/common.h b/fhi_lib/app/src/common.h index 2ba2fe5..7508117 100644 --- a/fhi_lib/app/src/common.h +++ b/fhi_lib/app/src/common.h @@ -28,7 +28,7 @@ #include #include -#define VERSIONX "oran_bronze_release_v1.1" +#define VERSIONX "oran_e_maintenance_release_v1.0" #define APP_O_DU 0 #define APP_O_RU 1 @@ -52,12 +52,15 @@ enum nRChBwOptions #define MAX_ANT_CARRIER_SUPPORTED_CAT_B (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR) #define SUBFRAME_DURATION_US 1000 -//#define SLOTNUM_PER_SUBFRAME 8 #define SUBFRAMES_PER_SYSTEMFRAME 10 #define IQ_PLAYBACK_BUFFER_BYTES (XRAN_NUM_OF_SLOT_IN_TDD_LOOP*N_SYM_PER_SLOT*XRAN_MAX_PRBS*N_SC_PER_PRB*4L) -/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 839 samples for long sequence or 144*14 (max) for short sequence. The payload length is 3356 octets.*/ -#define PRACH_PLAYBACK_BUFFER_BYTES (144*14*4L) +/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 840 samples for long sequence or 144 for short sequence. The payload length is 840*16*2/8 octets.*/ +#ifdef FCN_1_2_6_EARLIER +#define PRACH_PLAYBACK_BUFFER_BYTES (144*4L) +#else +#define PRACH_PLAYBACK_BUFFER_BYTES (840*4L) +#endif #ifdef _DEBUG #define iAssert(p) if(!(p)){fprintf(stderr,\ @@ -67,73 +70,72 @@ enum nRChBwOptions #define iAssert(p) #endif /* _DEBUG */ -extern int iq_playback_buffer_size_dl; -extern int iq_playback_buffer_size_ul; +/**< all the buffers allocated for O-XU */ +struct o_xu_buffers { + int iq_playback_buffer_size_dl; + int iq_playback_buffer_size_ul; -extern int iq_bfw_buffer_size_dl; -extern int iq_bfw_buffer_size_ul; + int iq_bfw_buffer_size_dl; + int iq_bfw_buffer_size_ul; -extern int iq_srs_buffer_size_ul; + int iq_srs_buffer_size_ul; -extern uint8_t numCCPorts; -/* Number of antennas supported by front-end */ + int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; -extern uint8_t num_eAxc; -/* Number of antennas supported by front-end */ -extern int16_t *p_tx_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; -extern int16_t *p_tx_prach_play_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_prach_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_prach_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_tx_srs_play_buffer[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; + int32_t tx_srs_play_buffer_size[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; + int32_t tx_srs_play_buffer_position[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; -extern int16_t *p_tx_srs_play_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -extern int32_t tx_srs_play_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -extern int32_t tx_srs_play_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; + int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; -/* Number of antennas supported by front-end */ -extern int16_t *p_rx_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; -extern int16_t *p_prach_log_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t prach_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t prach_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_srs_log_buffer[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; + int32_t srs_log_buffer_size[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; + int32_t srs_log_buffer_position[MAX_ANT_CARRIER_SUPPORTED_CAT_B]; -extern int16_t *p_srs_log_buffer[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -extern int32_t srs_log_buffer_size[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; -extern int32_t srs_log_buffer_position[XRAN_MAX_SECTOR_NR*XRAN_MAX_ANT_ARRAY_ELM_NR]; - -extern int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; - -extern int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_tx_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_rx_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; /* beamforming weights for UL (O-DU) */ -extern int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; /* beamforming weights for UL (O-DU) */ -extern int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; /* beamforming weights for UL (O-RU) */ -extern int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_rx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; /* beamforming weights for UL (O-RU) */ -extern int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; -extern int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; + int16_t *p_rx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; + int32_t rx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; +}; + +extern struct o_xu_buffers* p_o_xu_buff[XRAN_PORTS_NUM]; void sys_save_buf_to_file_txt(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num); void sys_save_buf_to_file(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num); int sys_load_file_to_buff(char *filename, char *bufname, unsigned char *pBuffer, unsigned int size, unsigned int buffers_num); + uint32_t app_xran_get_scs(uint8_t nMu); uint16_t app_xran_get_num_rbs(uint8_t ranTech, uint32_t nNumerology, uint32_t nBandwidth, uint32_t nAbsFrePointA); uint32_t app_xran_cal_nrarfcn(uint32_t nCenterFreq); @@ -141,6 +143,4 @@ int32_t app_xran_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexTyp uint32_t nTddPeriod, struct xran_slot_config *psSlotConfig); uint32_t app_xran_get_tti_interval(uint8_t nMu); - - #endif /*_XRAN_APP_COMMON_H_*/ diff --git a/fhi_lib/app/src/config.c b/fhi_lib/app/src/config.c index deec5a1..71406d0 100644 --- a/fhi_lib/app/src/config.c +++ b/fhi_lib/app/src/config.c @@ -23,6 +23,8 @@ * @author Intel Corporation **/ +#include +#include #include "rte_common.h" #include "config.h" #include "common.h" @@ -54,6 +56,20 @@ #define KEY_SSLOTCONFIG "sSlotConfig" +#define KEY_XU_NUM "oXuNum" +#define KEY_XU_ETH_LINK_SPD "oXuEthLinkSpeed" +#define KEY_XU_ETH_LINE_NUM "oXuLinesNumber" +#define KEY_XU_CP_ON_ONE_VF "oXuCPon1Vf" +#define KEY_XU_RXQ_VF "oXuRxqNumber" +#define KEY_OWDM_INIT_EN "oXuOwdmInitEn" +#define KEY_OWDM_MEAS_METH "oXuOwdmMeasMeth" +#define KEY_OWDM_NUM_SAMPS "oXuOwdmNumSamps" +#define KEY_OWDM_FLTR_TYPE "oXuOwdmFltrType" +#define KEY_OWDM_RSP_TO "oXuOwdmRespTimeOut" +#define KEY_OWDM_MEAS_ST "oXuOwdmMeasState" +#define KEY_OWDM_MEAS_ID "oXuOwdmMeasId" +#define KEY_OWDM_EN "oXuOwdmEnabled" +#define KEY_OWDM_PL_LENGTH "oXuOwdmPlLength" #define KEY_CC_PER_PORT_NUM "ccNum" #define KEY_ANT_NUM "antNum" #define KEY_UL_ANT_NUM "antNumUL" @@ -66,17 +82,24 @@ #define KEY_FILE_DLBFWUE "DlBfwUe" #define KEY_FILE_ULBFWUE "UlBfwUe" +#define KEY_FILE_O_XU_CFG "oXuCfgFile" +#define KEY_O_XU_PCIE_BUS "PciBusAddoXu" +#define KEY_O_XU_REM_MAC "oXuRem" + #define KEY_FILE_ULSRS "antSrsC" #define KEY_TTI_PERIOD "ttiPeriod" #define KEY_MTU_SIZE "MTUSize" +#define KEY_MAIN_CORE "mainCore" #define KEY_IO_CORE "ioCore" #define KEY_IO_WORKER "ioWorker" +#define KEY_IO_WORKER_64_127 "ioWorker_64_127" #define KEY_IO_SLEEP "ioSleep" #define KEY_SYSTEM_CORE "systemCore" #define KEY_IOVA_MODE "iovaMode" +#define KEY_DPDK_MEM_SZ "dpdkMemorySize" #define KEY_INSTANCE_ID "instanceId" @@ -87,8 +110,13 @@ #define KEY_FILE_AxC "antC" #define KEY_FILE_PRACH_AxC "antPrachC" +#define KEY_FILE_SLOT_TX "SlotNumTx" +#define KEY_FILE_SLOT_RX "SlotNumRx" + #define KEY_PRACH_ENABLE "rachEanble" #define KEY_SRS_ENABLE "srsEanble" +#define KEY_PUSCH_MASK_ENABLE "puschMaskEnable" +#define KEY_PUSCH_MASK_SLOT "puschMaskSlot" #define KEY_PRACH_CFGIDX "prachConfigIndex" #define KEY_SRS_SYM_IDX "srsSym" @@ -100,6 +128,8 @@ #define KEY_HTONS_SWAP "nebyteorderswap" #define KEY_COMPRESSION "compression" #define KEY_COMP_TYPE "compType" +#define KEY_PRACH_COMPMETH "prachCompMethod" +#define KEY_PRACH_IQ "prachiqWidth" #define KEY_BFW_NUM "totalBFWeights" @@ -135,10 +165,27 @@ #define KEY_NPRBELEM_DL "nPrbElemDl" #define KEY_PRBELEM_DL "PrbElemDl" +#define KEY_PRBELEM_DL_CC_M "PrbElemDlCCMask" +#define KEY_PRBELEM_DL_ANT_M "PrbElemDlAntCMask" +#define KEY_EXTBFW_DL "ExtBfwDl" #define KEY_NPRBELEM_UL "nPrbElemUl" #define KEY_PRBELEM_UL "PrbElemUl" +#define KEY_PRBELEM_UL_CC_M "PrbElemUlCCMask" +#define KEY_PRBELEM_UL_ANT_M "PrbElemUlAntCMask" +#define KEY_EXTBFW_UL "ExtBfwUl" +#define KEY_NPRBELEM_SRS "nPrbElemSrs" +#define KEY_PRBELEM_SRS "PrbElemSrs" +#define KEY_MAX_SEC_SYM "max_sections_per_symbol" +#define KEY_MAX_SEC_SLOT "max_sections_per_slot" + +typedef int (*fillConfigStruct_fn)(void* cbPram, const char *key, const char *value); +struct slot_cfg_to_pars { + RuntimeConfig *config; + int32_t direction; + int32_t slot_idx; +}; /** * Set runtime configuration parameters to their defaults. @@ -150,6 +197,9 @@ static void init_config(RuntimeConfig* config) memset(config , 0, sizeof(RuntimeConfig)); } +static int32_t +parseFileViaCb (char *filename, fillConfigStruct_fn cbFn, void* cbParm); + /** - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - **/ static void trim(char* input) @@ -160,10 +210,13 @@ static void trim(char* input) input[i] = '\0'; } + static int fillConfigStruct(RuntimeConfig *config, const char *key, const char *value) { int32_t parse_res = 0; - static unsigned int section_idx_dl = 0, section_idx_ul; + static uint32_t section_idx_dl = 0; + static uint32_t section_idx_ul = 0; + static uint32_t section_idx_srs = 0; if (strcmp(key, KEY_APP_MODE) == 0){ config->appMode = atoi(value); @@ -269,6 +322,10 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * config->compression = atoi(value); } else if (strcmp(key, KEY_COMP_TYPE) == 0) { config->CompHdrType = atoi(value); + } else if (strcmp(key, KEY_PRACH_COMPMETH) == 0) { + config->prachCompMethod = atoi(value); + } else if (strcmp(key, KEY_PRACH_IQ) == 0) { + config->prachiqWidth = atoi(value); } else if (strcmp(key, KEY_MTU_SIZE) == 0) { config->mtu = atoi(value); printf("mtu %d\n", config->mtu); @@ -278,9 +335,15 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * } else if (strcmp(key, KEY_IO_CORE) == 0) { config->io_core = atoi(value); printf("io_core %d [core id]\n", config->io_core); + } else if (strcmp(key, KEY_MAIN_CORE) == 0) { + config->io_core = atoi(value); + printf("io_core %d [core id]\n", config->io_core); } else if (strcmp(key, KEY_IO_WORKER) == 0) { config->io_worker = strtoll(value, NULL, 0); printf("io_worker 0x%lx [mask]\n", config->io_worker); + } else if (strcmp(key, KEY_IO_WORKER_64_127) == 0) { + config->io_worker_64_127 = strtoll(value, NULL, 0); + printf("io_worker_64_127 0x%lx [mask]\n", config->io_worker_64_127); } else if (strcmp(key, KEY_SYSTEM_CORE) == 0) { config->system_core = atoi(value); printf("system core %d [core id]\n", config->system_core); @@ -376,6 +439,28 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * strncpy(&config->ul_srs_file[srs_ant][0], value, strlen(value)); printf("antSrsC%d: %s\n",srs_ant, config->ul_srs_file[srs_ant]); } + } else if (strncmp(key, KEY_FILE_SLOT_TX, strlen(KEY_FILE_SLOT_TX)) == 0) { + unsigned int slot_num = 0; + unsigned int direction = XRAN_DIR_DL; + sscanf(key,"SlotNumTx%02u",&slot_num); + if (slot_num >= XRAN_N_FE_BUF_LEN) { + printf("SlotNumTx%d exceeds max slots supported\n",slot_num); + } else { + config->SlotNum_fileEnabled = 1; + strncpy(&config->SlotNum_file[direction][slot_num][0], value, strlen(value)); + printf("SlotNumTx%d: %s\n",slot_num, config->SlotNum_file[direction][slot_num]); + } + }else if (strncmp(key, KEY_FILE_SLOT_RX, strlen(KEY_FILE_SLOT_RX)) == 0) { + unsigned int slot_num = 0; + unsigned int direction = XRAN_DIR_UL; + sscanf(key,"SlotNumRx%02u",&slot_num); + if (slot_num >= XRAN_N_FE_BUF_LEN) { + printf("SlotNumRx%d exceeds max slots supported\n",slot_num); + } else { + config->SlotNum_fileEnabled = 1; + strncpy(&config->SlotNum_file[direction][slot_num][0], value, strlen(value)); + printf("SlotNumRx%d: %s\n",slot_num, config->SlotNum_file[direction][slot_num]); + } } else if (strcmp(key, KEY_PRACH_ENABLE) == 0) { config->enablePrach = atoi(value); printf("Prach enable: %d\n",config->enablePrach); @@ -384,7 +469,13 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * printf("maxFrameId: %d\n",config->maxFrameId); } else if (strcmp(key, KEY_SRS_ENABLE) == 0) { config->enableSrs = atoi(value); - printf("Srs enable: %d\n",config->enablePrach); + printf("Srs enable: %d\n",config->enableSrs); + } else if (strcmp(key, KEY_PUSCH_MASK_ENABLE) == 0) { + config->puschMaskEnable = atoi(value); + printf("PUSCH mask enable: %d\n",config->puschMaskEnable); + } else if (strcmp(key, KEY_PUSCH_MASK_SLOT) == 0) { + config->puschMaskSlot = atoi(value); + printf("PUSCH mask enable: %d\n",config->puschMaskSlot); } else if (strcmp(key, KEY_PRACH_CFGIDX) == 0) { config->prachConfigIndex = atoi(value); printf("Prach config index: %d\n",config->prachConfigIndex); @@ -485,21 +576,27 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * } else if (strcmp(key, KEY_UP_VTAG ) == 0) { config->up_vlan_tag = atoi(value); printf("up_vlan_tag: %d\n",config->up_vlan_tag); + } else if (strcmp(key, KEY_MAX_SEC_SYM ) == 0) { + config->max_sections_per_symbol = atoi(value); + printf("max_sections_per_symbol: %d\n",config->max_sections_per_symbol); + } else if (strcmp(key, KEY_MAX_SEC_SLOT ) == 0) { + config->max_sections_per_slot = atoi(value); + printf("max_sections_per_slot: %d\n",config->max_sections_per_slot); } else if (strcmp(key, KEY_NPRBELEM_UL ) == 0) { - config->PrbMapUl.nPrbElm = atoi(value); - if (config->PrbMapUl.nPrbElm > XRAN_MAX_PRBS) + config->p_PrbMapUl->nPrbElm = atoi(value); + if (config->p_PrbMapUl->nPrbElm > XRAN_MAX_SECTIONS_PER_SLOT) { printf("nTddPeriod is larger than max allowed, invalid!\n"); - config->PrbMapUl.nPrbElm = XRAN_MAX_PRBS; + config->p_PrbMapUl->nPrbElm = XRAN_MAX_SECTIONS_PER_SLOT; } - printf("nPrbElemUl: %d\n",config->PrbMapUl.nPrbElm); + printf("nPrbElemUl: %d\n",config->p_PrbMapUl->nPrbElm); } else if (strncmp(key, KEY_PRBELEM_UL, strlen(KEY_PRBELEM_UL)) == 0) { sscanf(key,"PrbElemUl%u",§ion_idx_ul); - if (section_idx_ul >= config->PrbMapUl.nPrbElm){ + if (section_idx_ul >= config->p_PrbMapUl->nPrbElm){ printf("section_idx %d exceeds nPrbElemUl\n",section_idx_ul); } else{ - struct xran_prb_elm *pPrbElem = &config->PrbMapUl.prbMap[section_idx_ul]; + struct xran_prb_elm *pPrbElem = &config->p_PrbMapUl->prbMap[section_idx_ul]; sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd", (int16_t*)&pPrbElem->nRBStart, (int16_t*)&pPrbElem->nRBSize, @@ -514,21 +611,87 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n", pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType); } + } else if(strncmp(key, KEY_EXTBFW_UL, strlen(KEY_EXTBFW_UL)) == 0) { + sscanf(key, "ExtBfwUl%u", §ion_idx_ul); + if(section_idx_ul >= config->p_PrbMapUl->nPrbElm) { + printf("section_idx %d of bfw exceeds nPrbElemUl\n",section_idx_ul); + } + else{ + struct xran_prb_elm *pPrbElem = &config->p_PrbMapUl->prbMap[section_idx_ul]; + sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", + (uint8_t*)&pPrbElem->bf_weight.numBundPrb, + (uint8_t*)&pPrbElem->bf_weight.numSetBFWs, + (uint8_t*)&pPrbElem->bf_weight.RAD, + (uint8_t*)&pPrbElem->bf_weight.disableBFWs, + (uint8_t*)&pPrbElem->bf_weight.bfwIqWidth, + (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth); + printf(KEY_EXTBFW_UL"%d: ", section_idx_ul); + printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n", + pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth); + } }else if (strcmp(key, KEY_NPRBELEM_DL ) == 0) { - config->PrbMapDl.nPrbElm = atoi(value); - if (config->PrbMapDl.nPrbElm > XRAN_MAX_PRBS) + config->p_PrbMapDl->nPrbElm = atoi(value); + if (config->p_PrbMapDl->nPrbElm > XRAN_MAX_SECTIONS_PER_SLOT) { - printf("nTddPeriod is larger than max allowed, invalid!\n"); - config->PrbMapDl.nPrbElm = XRAN_MAX_PRBS; + printf("nPrbElm is larger than max allowed, invalid!\n"); + config->p_PrbMapDl->nPrbElm = XRAN_MAX_SECTIONS_PER_SLOT; } - printf("nPrbElemDl: %d\n",config->PrbMapDl.nPrbElm); + printf("nPrbElemDl: %d\n",config->p_PrbMapDl->nPrbElm); } else if (strncmp(key, KEY_PRBELEM_DL, strlen(KEY_PRBELEM_DL)) == 0) { sscanf(key,"PrbElemDl%u",§ion_idx_dl); - if (section_idx_dl >= config->PrbMapDl.nPrbElm){ + if (section_idx_dl >= config->p_PrbMapDl->nPrbElm){ printf("section_idx %d exceeds nPrbElemDl\n",section_idx_dl); } else{ - struct xran_prb_elm *pPrbElem = &config->PrbMapDl.prbMap[section_idx_dl]; + struct xran_prb_elm *pPrbElem = &config->p_PrbMapDl->prbMap[section_idx_dl]; + sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd", + (int16_t*)&pPrbElem->nRBStart, + (int16_t*)&pPrbElem->nRBSize, + (int16_t*)&pPrbElem->nStartSymb, + (int16_t*)&pPrbElem->numSymb, + (int16_t*)&pPrbElem->nBeamIndex, + (int16_t*)&pPrbElem->bf_weight_update, + (int16_t*)&pPrbElem->compMethod, + (int16_t*)&pPrbElem->iqWidth, + (int16_t*)&pPrbElem->BeamFormingType, + (int16_t*)&pPrbElem->ScaleFactor, + (int16_t*)&pPrbElem->reMask); + printf("nPrbElemDl%d: ",section_idx_dl); + printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d ScaleFactor %d reMask %d\n", + pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType, pPrbElem->ScaleFactor, pPrbElem->reMask); + } + } else if(strncmp(key, KEY_EXTBFW_DL, strlen(KEY_EXTBFW_DL)) == 0) { + sscanf(key, "ExtBfwDl%u", §ion_idx_dl); + if(section_idx_dl >= config->p_PrbMapDl->nPrbElm) { + printf("section_idx %d of bfw exceeds nPrbElemUl\n",section_idx_dl); + } + else{ + struct xran_prb_elm *pPrbElem = &config->p_PrbMapDl->prbMap[section_idx_dl]; + sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", + (uint8_t*)&pPrbElem->bf_weight.numBundPrb, + (uint8_t*)&pPrbElem->bf_weight.numSetBFWs, + (uint8_t*)&pPrbElem->bf_weight.RAD, + (uint8_t*)&pPrbElem->bf_weight.disableBFWs, + (uint8_t*)&pPrbElem->bf_weight.bfwIqWidth, + (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth); + printf(KEY_EXTBFW_DL"%d: ", section_idx_dl); + printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n", + pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth); + } + } else if (strcmp(key, KEY_NPRBELEM_SRS ) == 0) { + config->p_PrbMapSrs->nPrbElm = atoi(value); + if (config->p_PrbMapSrs->nPrbElm > XRAN_MAX_SECTIONS_PER_SLOT) + { + printf("nPrbElm is larger than max allowed, invalid!\n"); + config->p_PrbMapSrs->nPrbElm = XRAN_MAX_SECTIONS_PER_SLOT; + } + printf("nPrbElemSrs: %d\n",config->p_PrbMapSrs->nPrbElm); + } else if (strncmp(key, KEY_PRBELEM_SRS, strlen(KEY_PRBELEM_SRS)) == 0) { + sscanf(key,"PrbElemSrs%u",§ion_idx_srs); + if (section_idx_srs >= config->p_PrbMapSrs->nPrbElm) { + printf("section_idx %d exceeds nPrbElemSrs\n",section_idx_srs); + }else { + struct xran_prb_elm *pPrbElem = &config->p_PrbMapSrs->prbMap[section_idx_srs]; sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd", (int16_t*)&pPrbElem->nRBStart, (int16_t*)&pPrbElem->nRBSize, @@ -539,10 +702,140 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * (int16_t*)&pPrbElem->compMethod, (int16_t*)&pPrbElem->iqWidth, (int16_t*)&pPrbElem->BeamFormingType); - printf("nPrbElemDl%d: ",section_idx_dl); + printf("nPrbElemSrs%d: ",section_idx_srs); printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n", pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType); } + }else { + printf("Unsupported configuration key [%s]\n", key); + return -1; + } + + return 0; +} + +static int +fillUsecaseStruct(UsecaseConfig *config, const char *key, const char *value) +{ + int32_t parse_res = 0; + if (strcmp(key, KEY_APP_MODE) == 0){ + config->appMode = atoi(value); + printf("appMode %d \n", config->appMode); + } else if (strcmp(key, KEY_XU_NUM) == 0){ + config->oXuNum = atoi(value); + printf("oXuNum %d \n", config->oXuNum); + } else if (strcmp(key, KEY_XU_ETH_LINK_SPD) == 0){ + config->EthLinkSpeed = atoi(value); + printf("EthLinkSpeed %d \n", config->EthLinkSpeed); + } else if (strcmp(key, KEY_XU_ETH_LINE_NUM) == 0){ + config->EthLinesNumber = atoi(value); + printf("EthLinkSpeed %d \n", config->EthLinesNumber); + } else if (strcmp(key, KEY_XU_RXQ_VF) == 0){ + config->num_rxq = atoi(value); + printf("oXuRxqNumber %d \n", config->num_rxq); + } else if (strcmp(key, KEY_XU_CP_ON_ONE_VF) == 0) { + config->one_vf_cu_plane = atoi(value); + printf("oXuCPon1Vf %d \n", config->one_vf_cu_plane); + } else if (strcmp(key, KEY_IO_SLEEP) == 0) { + config->io_sleep = atoi(value); + printf("io_sleep %d \n", config->io_sleep); + } else if (strcmp(key, KEY_IO_CORE) == 0) { + config->io_core = atoi(value); + printf("io_core %d [core id]\n", config->io_core); + } else if (strcmp(key, KEY_MAIN_CORE) == 0) { + config->main_core = atoi(value); + printf("main_core %d [core id]\n", config->main_core); + } else if (strcmp(key, KEY_IO_WORKER) == 0) { + config->io_worker = strtoll(value, NULL, 0); + printf("io_worker 0x%lx [mask]\n", config->io_worker); + } else if (strcmp(key, KEY_IO_WORKER_64_127) == 0) { + config->io_worker_64_127 = strtoll(value, NULL, 0); + printf("io_worker_64_127 0x%lx [mask]\n", config->io_worker_64_127); + } else if (strcmp(key, KEY_SYSTEM_CORE) == 0) { + config->system_core = atoi(value); + printf("system core %d [core id]\n", config->system_core); + } else if (strcmp(key, KEY_IOVA_MODE) == 0) { + config->iova_mode = atoi(value); + printf("iova_mode %d\n", config->iova_mode); + } else if (strcmp(key, KEY_DPDK_MEM_SZ) == 0) { + config->dpdk_mem_sz = atoi(value); + printf("dpdk_mem_sz %d\n", config->dpdk_mem_sz); + } else if (strcmp(key, KEY_INSTANCE_ID) == 0) { + config->instance_id = atoi(value); + printf("instance_id %d\n", config->instance_id); + }else if (strncmp(key, KEY_FILE_O_XU_CFG, strlen(KEY_FILE_O_XU_CFG)) == 0) { + unsigned int o_xu_id = 0; + sscanf(key,"oXuCfgFile%02u",&o_xu_id); + if (o_xu_id >= XRAN_PORTS_NUM) { + printf("oXuCfgFile%d exceeds max O-XU supported\n",o_xu_id); + } else { + strncpy(&config->o_xu_cfg_file[o_xu_id][0], value, strlen(value)); + printf("oXuCfgFile%d: %s\n",o_xu_id, config->o_xu_cfg_file[o_xu_id]); + } + } else if (strncmp(key, KEY_OWDM_INIT_EN, strlen(KEY_OWDM_INIT_EN)) == 0) { + config->owdmInitEn = atoi(value); + printf("owdmInitEn %d\n", config->owdmInitEn); + } else if (strncmp(key, KEY_OWDM_MEAS_METH, strlen(KEY_OWDM_MEAS_METH)) == 0) { + config->owdmMeasMeth = atoi(value); + printf("owdmMeasMeth %d\n", config->owdmMeasMeth); + } else if (strncmp(key, KEY_OWDM_NUM_SAMPS, strlen(KEY_OWDM_NUM_SAMPS)) == 0) { + config->owdmNumSamps = atoi(value); + printf("owdmNumSamps %d\n", config->owdmNumSamps); + } else if (strncmp(key, KEY_OWDM_FLTR_TYPE, strlen(KEY_OWDM_FLTR_TYPE)) == 0) { + config->owdmFltType = atoi(value); + printf("owdmFltType %d\n", config->owdmFltType); + } else if (strncmp(key, KEY_OWDM_RSP_TO, strlen(KEY_OWDM_RSP_TO)) == 0) { + config->owdmRspTo = atol(value); + printf("owdmRspTo %lu\n", config->owdmRspTo); + } else if (strncmp(key, KEY_OWDM_MEAS_ID, strlen(KEY_OWDM_MEAS_ID)) == 0) { + config->owdmMeasId = atoi(value); + printf("owdmMeasId %d\n", config->owdmMeasId); + } else if (strncmp(key, KEY_OWDM_EN, strlen(KEY_OWDM_EN)) == 0) { + config->owdmEnable = atoi(value); + printf("owdmEnable %d\n", config->owdmEnable); + } else if (strncmp(key, KEY_OWDM_PL_LENGTH, strlen(KEY_OWDM_PL_LENGTH)) == 0) { + config->owdmPlLength = atoi(value); + printf("owdmPlLength %d\n", config->owdmPlLength); + } else if (strncmp(key, KEY_OWDM_MEAS_ST, strlen(KEY_OWDM_MEAS_ST)) == 0) { + config->owdmMeasState = atoi(value); + printf("owdmMeasState %d\n", config->owdmMeasState); + } else if (strncmp(key, KEY_O_XU_PCIE_BUS, strlen(KEY_O_XU_PCIE_BUS)) == 0) { + unsigned int o_xu_id = 0; + unsigned int vf_num = 0; + sscanf(key,"PciBusAddoXu%02uVf%02u",&o_xu_id, &vf_num); + if (o_xu_id >= XRAN_PORTS_NUM || vf_num >= XRAN_VF_MAX){ + printf("PciBusAddoXu%dVf%d exceeds max O-XU supported\n",o_xu_id, vf_num); + } else { + strncpy(&config->o_xu_pcie_bus_addr[o_xu_id][vf_num][0], value, strlen(value)); + printf("PciBusAddoXu%dVf%d: %s\n",o_xu_id, vf_num, &config->o_xu_pcie_bus_addr[o_xu_id][vf_num][0]); + } + } else if (strncmp(key, KEY_O_XU_REM_MAC, strlen(KEY_O_XU_REM_MAC)) == 0) { + unsigned int xu_num = 0; + unsigned int vf_num = 0; + + sscanf(key,"oXuRem%02uMac%02u",&xu_num, &vf_num); + + if (xu_num >= XRAN_PORTS_NUM || vf_num >= XRAN_VF_MAX) { + printf("oXuRem%02uMac%02u exceeds max supported\n",xu_num, vf_num); + } else { + printf("oXuRem%02uMac%02u: %s\n",xu_num, vf_num, value); + sscanf(value, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[0], + (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[1], + (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[2], + (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[3], + (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[4], + (uint8_t*)&config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[5]); + + printf("[xu %d vf %d]RU MAC address: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx\n", + xu_num, + vf_num, + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[0], + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[1], + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[2], + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[3], + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[4], + config->remote_o_xu_addr[xu_num][vf_num].addr_bytes[5]); + } } else { printf("Unsupported configuration key [%s]\n", key); return -1; @@ -551,7 +844,203 @@ static int fillConfigStruct(RuntimeConfig *config, const char *key, const char * return 0; } -int parseConfigFile(char *filename, RuntimeConfig *config) +static int +fillSlotStructAsCb(void* cbParam, const char *key, const char *value) +{ + struct slot_cfg_to_pars *p_slot_cfg = (struct slot_cfg_to_pars*) cbParam; + RuntimeConfig *config = p_slot_cfg->config; + int32_t direction = p_slot_cfg->direction; + int32_t slot_idx = p_slot_cfg->slot_idx; + uint32_t section_idx = 0; + + //printf("Dir %d slot %d\n", direction, slot_idx); + + if (strcmp(key, KEY_NPRBELEM_UL ) == 0) { + config->p_SlotPrbMap[direction][slot_idx]->nPrbElm = atoi(value); + if (config->p_SlotPrbMap[direction][slot_idx]->nPrbElm > XRAN_MAX_SECTIONS_PER_SLOT) + { + printf("nTddPeriod is larger than max allowed, invalid!\n"); + config->p_SlotPrbMap[direction][slot_idx]->nPrbElm = XRAN_MAX_SECTIONS_PER_SLOT; + } + printf("nPrbElemUl: %d\n",config->p_SlotPrbMap[direction][slot_idx]->nPrbElm ); + } else if (strncmp(key, KEY_PRBELEM_UL_ANT_M, strlen(KEY_PRBELEM_UL_ANT_M)) == 0) { + sscanf(key,"PrbElemUlAntCMask%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm){ + printf("section_idx %d exceeds nPrbElemul\n",section_idx); + } + else{ + sscanf(value, "%lx",(uint64_t*)&config->SlotPrbAntCMask[direction][slot_idx][section_idx]); + printf("%s%u 0x%lx\n",KEY_PRBELEM_UL_ANT_M, section_idx, config->SlotPrbAntCMask[direction][slot_idx][section_idx]); + } + } else if (strncmp(key, KEY_PRBELEM_UL_CC_M, strlen(KEY_PRBELEM_UL_CC_M)) == 0) { + sscanf(key,"PrbElemUlCCMask%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm){ + printf("section_idx %d exceeds nPrbElemUL\n",section_idx); + } + else{ + sscanf(value, "%02hx",(uint16_t*)&config->SlotPrbCCmask[direction][slot_idx][section_idx]); + printf("%s%u 0x%02x\n",KEY_PRBELEM_UL_CC_M, section_idx, config->SlotPrbCCmask[direction][slot_idx][section_idx]); + } + } else if (strncmp(key, KEY_PRBELEM_UL, strlen(KEY_PRBELEM_UL)) == 0) { + sscanf(key,"PrbElemUl%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm) { + printf("section_idx %d exceeds nPrbElemUl\n",section_idx); + } + else { + struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx]; + sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd", + (int16_t*)&pPrbElem->nRBStart, + (int16_t*)&pPrbElem->nRBSize, + (int16_t*)&pPrbElem->nStartSymb, + (int16_t*)&pPrbElem->numSymb, + (int16_t*)&pPrbElem->nBeamIndex, + (int16_t*)&pPrbElem->bf_weight_update, + (int16_t*)&pPrbElem->compMethod, + (int16_t*)&pPrbElem->iqWidth, + (int16_t*)&pPrbElem->BeamFormingType); + printf("nPrbElemUl%d: ",section_idx); + printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n", + pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType); + } + } else if(strncmp(key, KEY_EXTBFW_UL, strlen(KEY_EXTBFW_UL)) == 0) { + sscanf(key, "ExtBfwUl%u", §ion_idx); + if(section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm) { + printf("section_idx %d of bfw exceeds nPrbElemUl\n",section_idx); + }else{ + struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx]; + sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", + (uint8_t*)&pPrbElem->bf_weight.numBundPrb, + (uint8_t*)&pPrbElem->bf_weight.numSetBFWs, + (uint8_t*)&pPrbElem->bf_weight.RAD, + (uint8_t*)&pPrbElem->bf_weight.disableBFWs, + (uint8_t*)&pPrbElem->bf_weight.bfwIqWidth, + (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth); + printf(KEY_EXTBFW_UL"%d: ", section_idx); + printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n", + pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth); + } + }else if (strcmp(key, KEY_NPRBELEM_DL ) == 0) { + config->p_SlotPrbMap[direction][slot_idx]->nPrbElm = atoi(value); + if (config->p_SlotPrbMap[direction][slot_idx]->nPrbElm > XRAN_MAX_SECTIONS_PER_SLOT) + { + printf("nTddPeriod is larger than max allowed, invalid!\n"); + config->p_SlotPrbMap[direction][slot_idx]->nPrbElm = XRAN_MAX_SECTIONS_PER_SLOT; + } + printf("nPrbElemDl: %d\n",config->p_SlotPrbMap[direction][slot_idx]->nPrbElm); + } else if (strncmp(key, KEY_PRBELEM_DL_ANT_M, strlen(KEY_PRBELEM_DL_ANT_M)) == 0) { + sscanf(key,"PrbElemDlAntCMask%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm){ + printf("section_idx %d exceeds nPrbElemDl\n",section_idx); + } + else{ + sscanf(value, "%lx",(uint64_t*)&config->SlotPrbAntCMask[direction][slot_idx][section_idx]); + printf("%s%u 0x%lx\n",KEY_PRBELEM_DL_ANT_M, section_idx, config->SlotPrbAntCMask[direction][slot_idx][section_idx]); + } + } else if (strncmp(key, KEY_PRBELEM_DL_CC_M, strlen(KEY_PRBELEM_DL_CC_M)) == 0) { + sscanf(key,"PrbElemDlCCMask%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm){ + printf("section_idx %d exceeds nPrbElemDl\n",section_idx); + } + else{ + sscanf(value, "%02hx",(uint16_t*)&config->SlotPrbCCmask[direction][slot_idx][section_idx]); + printf("%s%u 0x%02x\n",KEY_PRBELEM_DL_CC_M, section_idx, config->SlotPrbCCmask[direction][slot_idx][section_idx]); + } + } else if (strncmp(key, KEY_PRBELEM_DL, strlen(KEY_PRBELEM_DL)) == 0) { + sscanf(key,"PrbElemDl%u",§ion_idx); + if (section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm){ + printf("section_idx %d exceeds nPrbElemDl\n",section_idx); + } + else{ + struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx]; + sscanf(value, "%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd,%hd", + (int16_t*)&pPrbElem->nRBStart, + (int16_t*)&pPrbElem->nRBSize, + (int16_t*)&pPrbElem->nStartSymb, + (int16_t*)&pPrbElem->numSymb, + (int16_t*)&pPrbElem->nBeamIndex, + (int16_t*)&pPrbElem->bf_weight_update, + (int16_t*)&pPrbElem->compMethod, + (int16_t*)&pPrbElem->iqWidth, + (int16_t*)&pPrbElem->BeamFormingType); + printf("nPrbElemDl%d: ",section_idx); + printf("nRBStart %d,nRBSize %d,nStartSymb %d,numSymb %d,nBeamIndex %d, bf_weight_update %d compMethod %d, iqWidth %d BeamFormingType %d\n", + pPrbElem->nRBStart,pPrbElem->nRBSize,pPrbElem->nStartSymb,pPrbElem->numSymb,pPrbElem->nBeamIndex, pPrbElem->bf_weight_update, pPrbElem->compMethod, pPrbElem->iqWidth, pPrbElem->BeamFormingType); + } + } else if(strncmp(key, KEY_EXTBFW_DL, strlen(KEY_EXTBFW_DL)) == 0) { + sscanf(key, "ExtBfwDl%u", §ion_idx); + if(section_idx >= config->p_SlotPrbMap[direction][slot_idx]->nPrbElm) { + printf("section_idx %d of bfw exceeds nPrbElemUl\n",section_idx); + } + else{ + struct xran_prb_elm *pPrbElem = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx]; + sscanf(value, "%hhu,%hhu,%hhu,%hhu,%hhu,%hhu", + (uint8_t*)&pPrbElem->bf_weight.numBundPrb, + (uint8_t*)&pPrbElem->bf_weight.numSetBFWs, + (uint8_t*)&pPrbElem->bf_weight.RAD, + (uint8_t*)&pPrbElem->bf_weight.disableBFWs, + (uint8_t*)&pPrbElem->bf_weight.bfwIqWidth, + (uint8_t*)&pPrbElem->bf_weight.bfwCompMeth); + printf(KEY_EXTBFW_DL"%d: ",section_idx); + printf("numBundPrb %d, numSetBFW %d, RAD %d, disableBFW %d, bfwIqWidth %d, bfwCompMeth %d\n", + pPrbElem->bf_weight.numBundPrb, pPrbElem->bf_weight.numSetBFWs, pPrbElem->bf_weight.RAD, pPrbElem->bf_weight.disableBFWs, pPrbElem->bf_weight.bfwIqWidth, pPrbElem->bf_weight.bfwCompMeth); + } + } else { + printf("Unsupported configuration key [%s]\n", key); + return -1; + } + + return 0; +} + +struct xran_prb_map* +config_malloc_prb_map(void) +{ + uint32_t size = sizeof(struct xran_prb_map) + (XRAN_MAX_SECTIONS_PER_SLOT -1) * sizeof(struct xran_prb_elm); + void *ret = NULL; + + ret = malloc(size); + + if(ret) { + memset(ret, 0, size); + return (struct xran_prb_map*)ret; + } else { + rte_panic("xran_prb_map alloc failed"); + } +} + +int32_t +config_init(RuntimeConfig *p_o_xu_cfg) +{ + int32_t i, j, k, z; + memset(p_o_xu_cfg, 0, sizeof(RuntimeConfig)); + + p_o_xu_cfg->p_PrbMapDl = config_malloc_prb_map(); + p_o_xu_cfg->p_PrbMapUl = config_malloc_prb_map(); + p_o_xu_cfg->p_PrbMapSrs = config_malloc_prb_map(); + + for (i= 0; i < XRAN_DIR_MAX; i++){ + for (j= 0; j < XRAN_N_FE_BUF_LEN; j++){ + p_o_xu_cfg->p_SlotPrbMap[i][j] = config_malloc_prb_map(); + } + } + + for (i = 0; i < XRAN_DIR_MAX; i++) { + for (j = 0; j < XRAN_N_FE_BUF_LEN; j++) { + for (k = 0; k < XRAN_MAX_SECTOR_NR; k++) { + for (z = 0; z < XRAN_MAX_ANTENNA_NR; z++) { + p_o_xu_cfg->p_RunSlotPrbMap[i][j][k][z] = config_malloc_prb_map(); + p_o_xu_cfg->p_RunSrsSlotPrbMap[i][j][k][z] = config_malloc_prb_map(); + } + } + } + } + + return 0; +} + + +int +parseConfigFile(char *filename, RuntimeConfig *config) { char inputLine[MAX_LINE_SIZE] = {0}; int inputLen = 0; @@ -629,3 +1118,214 @@ int parseConfigFile(char *filename, RuntimeConfig *config) return 0; } + +int32_t +parseSlotConfigFile(char *dir, RuntimeConfig *config) +{ + int32_t ret = 0; + char filename[512]; + size_t len; + int32_t slot_idx = 0; + int32_t cc_idx = 0; + int32_t ant_idx = 0; + int32_t direction = 0; + struct slot_cfg_to_pars slot_cfg_param; + + for (direction = 0; direction < XRAN_DIR_MAX; direction++) { + for (slot_idx = 0; slot_idx < config->numSlots; slot_idx++){ + memset(filename, 0, sizeof(filename)); + printf("dir (%s)\n",dir); + len = strlen(dir) + 1; + if (len > 511) { + printf("parseSlotConfigFile: Name of directory, %s is too long. Maximum is 511 characters!!\n", dir); + return -1; + } else { + strncpy(filename, dir, len); + } + strncat(filename, "/", 1); + len +=1; + len = (sizeof(filename)) - len; + + if(len > strlen(config->SlotNum_file[direction][slot_idx])){ + strncat(filename, config->SlotNum_file[direction][slot_idx], RTE_MIN (len, strlen(config->SlotNum_file[direction][slot_idx]))); + } else { + printf("File name error\n"); + return -1; + } + printf("slot_file[%d][%d] (%s)\n",direction, slot_idx, filename); + printf("\n=================== Slot%s %d===================\n", ((direction == XRAN_DIR_UL) ? "RX" : "TX"), slot_idx); + + slot_cfg_param.direction = direction; + slot_cfg_param.slot_idx = slot_idx; + slot_cfg_param.config = config; + + if (parseFileViaCb(filename, fillSlotStructAsCb, (void*)&slot_cfg_param)) { + printf("Configuration file error\n"); + return -1; + } + } + } + + return ret; +} + +int32_t +parseFileViaCb (char *filename, fillConfigStruct_fn cbFn, void* cbParm) +{ + char inputLine[MAX_LINE_SIZE] = {0}; + int inputLen = 0; + int i; + int lineNum = 0; + char key[MAX_LINE_SIZE] = {0}; + char value[MAX_LINE_SIZE] = {0}; + FILE *file = fopen(filename, "r"); + + if (NULL == file) { + log_err("Error while opening config file from: %s", filename); + return -1; + } + + for (;;) { + if (fgets(inputLine, MAX_LINE_SIZE, file) == NULL) { + if (lineNum > 0) { + printf("%d lines of config file has been read.\n", lineNum); + break; + } else { + printf("Configuration file reading error has occurred.\n"); + fclose(file); + return -1; + } + } + + if (inputLine[strlen(inputLine)-1] == '\n') + inputLine[strlen(inputLine)-1] == '\0'; + + lineNum++; + inputLen = strlen(inputLine); + + for (i=0; i inputLen - 1) || (i - 2 > inputLen)) { + log_err("Parsing config file error at line %d", lineNum); + fclose(file); + return -1; + } + strncpy(value, &inputLine[i+1], (sizeof(value) - 1)); + value[inputLen-i-2] = '\0'; + trim(value); + + if (strlen(key) == 0 || strlen(value) == 0) { + printf("Parsing config file error at line %d", lineNum); + fclose(file); + return -1; + } + + if(cbFn){ + if (cbFn(cbParm, key, value) != 0) { + fclose(file); + return -1; + } + } else { + printf("cbFn==NULL\n"); + fclose(file); + return -1; + } + + break; + } + + memset(&inputLine[0], 0, sizeof(MAX_LINE_SIZE)); + memset(&key[0], 0, sizeof(MAX_LINE_SIZE)); + memset(&value[0], 0, sizeof(MAX_LINE_SIZE)); + } + fclose(file); + + return 0; +} + +int parseUsecaseFile(char *filename, UsecaseConfig *usecase_cfg) +{ + char inputLine[MAX_LINE_SIZE] = {0}; + int inputLen = 0; + int i; + int lineNum = 0; + char key[MAX_LINE_SIZE] = {0}; + char value[MAX_LINE_SIZE] = {0}; + FILE *file = fopen(filename, "r"); + + if (NULL == file) { + log_err("Error while opening config file from: %s", filename); + return -1; + } + + for (;;) { + if (fgets(inputLine, MAX_LINE_SIZE, file) == NULL) { + if (lineNum > 0) { + printf("%d lines of config file has been read.\n", lineNum); + break; + } else { + printf("Configuration file reading error has occurred.\n"); + fclose(file); + return -1; + } + } + + if (inputLine[strlen(inputLine)-1] == '\n') + inputLine[strlen(inputLine)-1] == '\0'; + + lineNum++; + inputLen = strlen(inputLine); + + for (i=0; i inputLen - 1) || (i - 2 > inputLen)) { + log_err("Parsing config file error at line %d", lineNum); + fclose(file); + return -1; + } + strncpy(value, &inputLine[i+1], (sizeof(value) - 1)); + value[inputLen-i-2] = '\0'; + trim(value); + + if (strlen(key) == 0 || strlen(value) == 0) { + printf("Parsing config file error at line %d", lineNum); + fclose(file); + return -1; + } + + if (fillUsecaseStruct(usecase_cfg, key, value) != 0) { + fclose(file); + return -1; + } + + break; + } + + memset(&inputLine[0], 0, sizeof(MAX_LINE_SIZE)); + memset(&key[0], 0, sizeof(MAX_LINE_SIZE)); + memset(&value[0], 0, sizeof(MAX_LINE_SIZE)); + } + fclose(file); + + return 0; +} diff --git a/fhi_lib/app/src/config.h b/fhi_lib/app/src/config.h index 0a713e7..c968cb3 100644 --- a/fhi_lib/app/src/config.h +++ b/fhi_lib/app/src/config.h @@ -29,6 +29,7 @@ #include #include #include "xran_fh_o_du.h" +#include "xran_pkt.h" /** Run time configuration of application */ typedef struct _RuntimeConfig @@ -42,6 +43,8 @@ typedef struct _RuntimeConfig uint32_t antElmTRx; /**< Number of antenna elements for TX and RX */ uint32_t muMimoUEs; /**< Number of UEs (with 1 RX ant)/beams */ + uint32_t o_xu_id; /**< id of O-DU|O-RU with in use case scenario */ + uint32_t DlLayersPerUe; /**< Number of DL layer per UE */ uint32_t UlLayersPerUe; /**< Number of UL layer per UE */ @@ -53,7 +56,8 @@ typedef struct _RuntimeConfig uint32_t instance_id; /**< Instance ID of application */ uint32_t io_core; /**< Core used for IO */ - uint64_t io_worker; /**< Mask for worker cores */ + uint64_t io_worker; /**< Mask for worker cores 0-63 */ + uint64_t io_worker_64_127; /**< Mask for worker cores 64-127 */ int32_t io_sleep; /**< enable sleep on PMD cores */ uint32_t system_core; /* house keeping core */ int iova_mode; /**< DPDK IOVA Mode */ @@ -79,12 +83,17 @@ typedef struct _RuntimeConfig uint8_t nebyteorderswap; /**< do swap of byte order from host byte order to network byte order. ETH */ uint8_t compression; /**< enable use case with compression */ uint8_t CompHdrType; /**< dynamic or static compression header */ + uint8_t prachCompMethod; /**< compression enable for PRACH */ + uint8_t prachiqWidth; /**< IQ width for PRACH */ uint16_t totalBfWeights; /**< The total number of beamforming weights on RU */ uint8_t enableSrs; /**< enable SRS (valid for Cat B only) */ uint16_t srsSymMask; /**< SRS symbol mask [014] within S/U slot [0-13] def is 13 */ + uint8_t puschMaskEnable; /**< enable PUSCH mask, which means not tranfer PUSCH in some UL slot */ + uint8_t puschMaskSlot; /**< PUSCH channel will not tranfer in slot module Frame */ + uint16_t maxFrameId; /**< max value of frame id */ uint16_t Tadv_cp_dl; @@ -128,16 +137,74 @@ typedef struct _RuntimeConfig uint8_t nFrameDuplexType; uint8_t nTddPeriod; struct xran_slot_config sSlotConfig[XRAN_MAX_TDD_PERIODICITY]; - struct xran_prb_map PrbMapDl; - struct xran_prb_map PrbMapUl; + + struct xran_prb_map* p_PrbMapDl; + struct xran_prb_map* p_PrbMapUl; + struct xran_prb_map* p_PrbMapSrs; + + uint16_t SlotPrbCCmask[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTIONS_PER_SLOT]; + uint64_t SlotPrbAntCMask[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTIONS_PER_SLOT]; + struct xran_prb_map* p_SlotPrbMap[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN]; + + int32_t RunSlotPrbMapEnabled; + struct xran_prb_map* p_RunSlotPrbMap[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_prb_map* p_RunSrsSlotPrbMap[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; int32_t DU_Port_ID_bitwidth; int32_t BandSector_ID_bitwidth; int32_t CC_ID_bitwidth; int32_t RU_Port_ID_bitwidth; + struct o_xu_buffers *p_buff; + + int32_t SlotNum_fileEnabled; + char SlotNum_file[XRAN_DIR_MAX][XRAN_N_FE_BUF_LEN][512]; /**< file to use for test vector */ + uint16_t max_sections_per_slot; + uint16_t max_sections_per_symbol; } RuntimeConfig; +/** use case configuration */ +typedef struct _UsecaseConfig +{ + uint8_t oXuNum; /**< Number of O-RU/O-DU connected to this instance */ + uint8_t appMode; /**< Application mode: O-DU or O-RU */ + + uint32_t instance_id; /**< Instance ID of application */ + uint32_t main_core; /**< Core used for main() */ + uint32_t io_core; /**< Core used for IO */ + uint64_t io_worker; /**< Mask for worker cores 0-63 */ + uint64_t io_worker_64_127; /**< Mask for worker cores 64-127 */ + int32_t io_sleep; /**< Enable sleep on PMD cores */ + uint32_t system_core; /**< System core */ + int32_t iova_mode; /**< DPDK IOVA Mode */ + int32_t dpdk_mem_sz; /**< Total DPDK memory size */ + + int32_t EthLinkSpeed; /**< Ethernet Physical Link speed per O-RU: 10,25,40,100 >*/ + int32_t EthLinesNumber; /**< 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) */ + int32_t one_vf_cu_plane; /**< 1 - C-plane and U-plane use one VF */ + uint16_t owdmInitEn; /**< One Way Delay Measurement Initiator if set, Recipient if clear */ + uint16_t owdmMeasMeth; /**< One Way Delay Measurement Method:0 REQUEST, 1 REM_REQ, 2 REQ_WFUP, 3 REM_REQ_WFUP */ + uint16_t owdmNumSamps; /**< One Way Delay Measurement number of samples per test */ + uint16_t owdmFltType; /**< One Way Delay Measurement Filter Type 0: Simple Average */ + uint64_t owdmRspTo; /**< One Way Delay Measurement Response Time Out in ns */ + uint16_t owdmMeasState; /**< One Way Delay Measurement State 0:INIT, 1:IDLE, 2:ACTIVE, 3:DONE */ + uint16_t owdmMeasId; /**< One Way Delay Measurement Id, Seed for the measurementId to be used */ + uint16_t owdmEnable; /**< One Way Delay Measurement master enable when set performs measurements on all vfs */ + uint16_t owdmPlLength; /**< One Way Delay Measurement Payload length 44<= PiLength <= 1400 bytes */ + + int num_vfs; /**< Total numbers of VFs accrose all O-RU|O-DU */ + int num_rxq; /**< Total numbers of HW RX queues for each VF O-RU|O-DU */ + + struct rte_ether_addr remote_o_xu_addr[XRAN_PORTS_NUM][XRAN_VF_MAX]; /**< O-DU Ethernet Mac Address */ + struct rte_ether_addr remote_o_xu_addr_copy[XRAN_VF_MAX]; /**< Temp Ethernet Mac Address */ + + char o_xu_cfg_file [XRAN_PORTS_NUM][512]; /**< file with config for each O-XU */ + char o_xu_pcie_bus_addr[XRAN_PORTS_NUM][XRAN_VF_MAX][512]; /**< VFs used for each O-RU|O-DU */ + + char prefix_name[256]; + +} UsecaseConfig; + /** * Parse application configuration file. * @@ -145,4 +212,20 @@ typedef struct _RuntimeConfig * @param config The configuration structure to be filled with parsed data. */ int parseConfigFile(char *filename, RuntimeConfig *config); +/** + * Parse application use case file. + * + * @param filename The name of the use case file to be parsed. + * @param config The configuration structure to be filled with parsed data. */ +int parseUsecaseFile(char *filename, UsecaseConfig *config); + +/** + * Parse slot config file. + * + * @param dir folder name. + * @param config The configuration structure to be filled with parsed data. */ +int32_t parseSlotConfigFile(char *dir, RuntimeConfig *config); +int32_t config_init(RuntimeConfig *p_o_xu_cfg); +struct xran_prb_map* config_malloc_prb_map(void); + #endif /* _SAMPLEAPP__CONFIG_H_ */ diff --git a/fhi_lib/app/src/sample-app.c b/fhi_lib/app/src/sample-app.c index d88e18f..713a58b 100644 --- a/fhi_lib/app/src/sample-app.c +++ b/fhi_lib/app/src/sample-app.c @@ -16,9 +16,20 @@ * *******************************************************************************/ +/** + * @brief Main module of sample application. Demonstration of usage of xRAN library for ORAN + * WG4 Front haul + * @file sample-app.c + * @ingroup xran + * @author Intel Corporation + * + **/ + #define _GNU_SOURCE #include +#include #include +#include #include #include #include @@ -31,165 +42,55 @@ #include #include #include -#include // for getopt - +#include +#include #include "common.h" #include "config.h" #include "xran_mlog_lnx.h" #include "xran_fh_o_du.h" -#include "xran_compression.h" -#include "xran_cp_api.h" #include "xran_sync_api.h" #include "xran_mlog_task_id.h" +#include "app_io_fh_xran.h" +#include "app_profile_xran.h" +#include "xran_ecpri_owd_measurements.h" #define MAX_BBU_POOL_CORE_MASK (4) - - -#define SW_FPGA_TOTAL_BUFFER_LEN 4*1024*1024*1024 -#define SW_FPGA_SEGMENT_BUFFER_LEN 1*1024*1024*1024 -#define SW_FPGA_FH_TOTAL_BUFFER_LEN 1*1024*1024*1024 -#define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192) - -#define NSEC_PER_SEC 1000000000 - -#define MAX_PKT_BURST (448+4) // 4x14x8 -#define N_MAX_BUFFER_SEGMENT MAX_PKT_BURST - +#ifndef NS_PER_SEC +#define NS_PER_SEC 1E9 +#endif #define MAIN_PRIORITY 98 -#define NUM_OF_SUBFRAME_PER_FRAME (10) - -enum app_state state; - -uint64_t tick_per_usec; -static volatile uint64_t timer_last_irq_tick = 0; -static uint64_t tsc_resolution_hz = 0; - -RuntimeConfig startupConfiguration = {0}; - -/* buffers size */ -uint32_t nFpgaToSW_FTH_RxBufferLen; -uint32_t nFpgaToSW_PRACH_RxBufferLen; -uint32_t nSW_ToFpga_FTH_TxBufferLen; - -static struct xran_fh_init xranInit; -void * xranHandle = NULL; +#define CPU_HZ ticks_per_usec /* us */ struct sample_app_params { int num_vfs; + int num_o_xu; char *cfg_file; + char *usecase_file; + char vf_pcie_addr[XRAN_PORTS_NUM][XRAN_VF_MAX][32]; }; +struct app_sym_cb_ctx { + int32_t cb_param; + struct xran_sense_of_time sense_of_time; +}; -struct xran_fh_config xranConf; -struct xran_fh_config *pXranConf = NULL; +static enum app_state state; +static uint64_t ticks_per_usec; +static volatile uint64_t timer_last_irq_tick = 0; +static uint64_t tsc_resolution_hz = 0; -typedef struct -{ - uint32_t phaseFlag :1; - uint32_t NRARFCN :22; - uint32_t SULFreShift :1; - uint32_t SULFlag :1; - uint32_t rsv :7; -}FPGAPhaseCompCfg; - -typedef struct XranLibConfig -{ - uint32_t nDriverCoreId; - uint32_t nTimingAdvance; - uint32_t nFhConfig; - uint32_t nFhBufIntFlag; - uint32_t nSectorNum; - uint32_t nNrOfSlotInSf; - uint32_t nNrofSfInFrame; - void * pFthInstanceHandles; -}XranLibConfigStruct; -typedef enum { - XRANFTHTX_OUT = 0, - XRANFTHTX_PRB_MAP_OUT, - XRANFTHTX_SEC_DESC_OUT, - XRANFTHRX_IN, - XRANFTHRX_PRB_MAP_IN, - XRANFTHTX_SEC_DESC_IN, - XRANFTHRACH_IN, - XRANSRS_IN, - MAX_SW_XRAN_INTERFACE_NUM -}SWXRANInterfaceTypeEnum; - -/* - * manage one cell's all Ethernet frames for one DL or UL LTE subframe - */ -typedef struct { - /* -1-this subframe is not used in current frame format - 0-this subframe can be transmitted, i.e., data is ready - 1-this subframe is waiting transmission, i.e., data is not ready - 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1, - set bValid to 10. - */ - int32_t bValid ; // when UL rx, it is subframe index. - int32_t nSegToBeGen; - int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE - // -1 means that DL packet to be transmitted is not ready in BS - int32_t nSegTransferred; // number of data segments has been transmitted or received - struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool - struct xran_buffer_list sBufferList; -} BbuIoBufCtrlStruct; - -typedef struct { - uint64_t nCoreMask; - int16_t cpuSocketId; - uint8_t nDriverCoreId; - uint8_t nFHCoreId; - - struct rte_mempool *bbuio_buf_pool; - - /* io struct */ - BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - - /* Cat B */ - BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; - - /* buffers lists */ - struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - - /* Cat B SRS buffers */ - struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; - - void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector - uint32_t nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool - uint16_t nInstanceNum; - - uint64_t nTscTiming[XRAN_N_FE_BUF_LEN]; // records the TSC when a timing packet is received. -} BbuXranIoIfStruct; - -static BbuXranIoIfStruct gsXranIoIf; -static XranLibConfigStruct *gpXranLibConfig = NULL; - -long old_rx_counter = 0; -long old_tx_counter = 0; - - -#define CPU_HZ tick_per_usec //us - -/* Application User space functions */ -void xran_fh_rx_callback(void *pCallbackTag, int32_t status); -void xran_fh_rx_prach_callback(void *pCallbackTag, int32_t status); - -static BbuXranIoIfStruct *xran_get_ctx(void) -{ - return &gsXranIoIf; -} +UsecaseConfig* p_usecaseConfiguration = {NULL}; +RuntimeConfig* p_startupConfiguration[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL}; + +struct app_sym_cb_ctx cb_sym_ctx[XRAN_CB_SYM_MAX]; -static void print_menu() +long old_rx_counter[XRAN_PORTS_NUM] = {0,0,0,0}; +long old_tx_counter[XRAN_PORTS_NUM] = {0,0,0,0}; + +static void +app_print_menu() { puts("+---------------------------------------+"); puts("| Press 1 to start 5G NR XRAN traffic |"); @@ -198,100 +99,13 @@ static void print_menu() puts("+---------------------------------------+"); } -static int32_t get_xran_sfidx(uint8_t nNrOfSlotInSf) -{ - int32_t nSfIdx = -1; - uint32_t nFrameIdx; - uint32_t nSubframeIdx; - uint32_t nSlotIdx; - uint64_t nSecond; - - uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); - nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf - + nSubframeIdx*nNrOfSlotInSf - + nSlotIdx; -#if 0 - printf("\nxranTime is %d, return is %d, radio frame is %d, subframe is %d slot is %d tsc is %llu us", - nXranTime, - nSfIdx, - nFrameIdx, - nSubframeIdx, - nSlotIdx, - __rdtsc()/CPU_HZ); -#endif - - return nSfIdx; -} - -void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status) -{ - uint64_t t1 = MLogTick(); - uint32_t mlogVar[10]; - uint32_t mlogVarCnt = 0; - uint8_t Numerlogy = xranConf.frame_conf.nNumerology; - uint8_t nNrOfSlotInSf = 1<> 16; /* tti */ - mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */ - mlogVar[mlogVarCnt++] = (uint32_t)sfIdx; - MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); - rte_pause(); - - MLogTask(PID_GNB_SYM_CB, t1, MLogTick()); - return; -} - -void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status) -{ - uint64_t t1 = MLogTick(); - uint32_t mlogVar[10]; - uint32_t mlogVarCnt = 0; - - mlogVar[mlogVarCnt++] = 0xDDDDDDDD; - mlogVar[mlogVarCnt++] = status >> 16; /* tti */ - mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */ - MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); - rte_pause(); - - MLogTask(PID_GNB_PRACH_CB, t1, MLogTick()); -} - -void xran_fh_rx_srs_callback(void *pCallbackTag, xran_status_t status) -{ - uint64_t t1 = MLogTick(); - uint32_t mlogVar[10]; - uint32_t mlogVarCnt = 0; - - mlogVar[mlogVarCnt++] = 0xCCCCCCCC; - mlogVar[mlogVarCnt++] = status >> 16; /* tti */ - mlogVar[mlogVarCnt++] = status & 0xFF; /* sym */ - MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); - rte_pause(); - - MLogTask(PID_GNB_SRS_CB, t1, MLogTick()); -} - - -//------------------------------------------------------------------------------------------- -/** @ingroup group_nbiot_source_auxlib_timer - * - * @param void - * - * @return Ticks - * - * @description - * This function reads the rtdsc clock and returns the current value in there. - * -**/ -//------------------------------------------------------------------------------------------- -unsigned long timer_get_ticks(void) +uint64_t +app_timer_get_ticks(void) { - unsigned long ret; + uint64_t ret; union { - unsigned long tsc_64; + uint64_t tsc_64; struct { uint32_t lo_32; @@ -303,12 +117,12 @@ unsigned long timer_get_ticks(void) "=a" (tsc.lo_32), "=d" (tsc.hi_32)); - ret = ((unsigned long)tsc.tsc_64); + ret = ((uint64_t)tsc.tsc_64); return ret; } //------------------------------------------------------------------------------------------- -/** @ingroup group_lte_source_auxlib_timer +/** @ingroup xran * * @param void * @@ -320,1656 +134,600 @@ unsigned long timer_get_ticks(void) * **/ //------------------------------------------------------------------------------------------- -int timer_set_tsc_freq_from_clock(void) +int32_t +app_timer_set_tsc_freq_from_clock(void) { -#define NS_PER_SEC 1E9 struct timespec sleeptime = {.tv_nsec = 5E8 }; /* 1/2 second */ struct timespec t_start, t_end; uint64_t tsc_resolution_hz = 0; - if (clock_gettime(CLOCK_MONOTONIC_RAW, &t_start) == 0) - { - unsigned long ns, end, start = timer_get_ticks(); + if (clock_gettime(CLOCK_MONOTONIC_RAW, &t_start) == 0) { + unsigned long ns, end, start = app_timer_get_ticks(); nanosleep(&sleeptime,NULL); clock_gettime(CLOCK_MONOTONIC_RAW, &t_end); - end = timer_get_ticks(); + end = app_timer_get_ticks(); ns = ((t_end.tv_sec - t_start.tv_sec) * NS_PER_SEC); ns += (t_end.tv_nsec - t_start.tv_nsec); double secs = (double)ns/NS_PER_SEC; tsc_resolution_hz = (unsigned long)((end - start)/secs); - tick_per_usec = (tsc_resolution_hz / 1000000); + ticks_per_usec = (tsc_resolution_hz / 1000000); printf("System clock (rdtsc) resolution %lu [Hz]\n", tsc_resolution_hz); - printf("Ticks per us %lu\n", tick_per_usec); + printf("Ticks per us %lu\n", ticks_per_usec); return 0; } return -1; } -int physide_dl_tti_call_back(void * param) +void +app_version_print(void) { - uint64_t t1 = MLogTick(); - rte_pause(); - MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); - return 0; -} + char sysversion[100]; + char *compilation_date = __DATE__; + char *compilation_time = __TIME__; -int physide_ul_half_slot_call_back(void * param) -{ - uint64_t t1 = MLogTick(); - rte_pause(); - MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); - return 0; + uint32_t nLen; + + snprintf(sysversion, 99, "Version: %s", VERSIONX); + nLen = strlen(sysversion); + + printf("\n\n"); + printf("===========================================================================================================\n"); + printf("SAMPLE-APP VERSION\n"); + printf("===========================================================================================================\n"); + + printf("%s\n", sysversion); + printf("build-date: %s\n", compilation_date); + printf("build-time: %s\n", compilation_time); } -int physide_ul_full_slot_call_back(void * param) +static void +app_help(void) { - uint64_t t1 = MLogTick(); - rte_pause(); - MLogTask(PID_GNB_PROC_TIMING, t1, MLogTick()); - return 0; + char help_content[] = \ + "sample application\n\n"\ + "Usage: sample-app --usecasefile ./usecase_du.cfg --num_eth_vfs 12"\ + "--vf_addr_o_xu_a \"0000:51:01.0,0000:51:01.1,0000:51:01.2,0000:51:01.3\""\ + "--vf_addr_o_xu_b \"0000:51:01.4,0000:51:01.5,0000:51:01.6,0000:51:01.7\""\ + "--vf_addr_o_xu_c \"0000:51:02.0,0000:51:02.1,0000:51:02.2,0000:51:02.3\"\n\n"\ + "or sample-app --usecasefile ./usecase_du.cfg --num_eth_vfs 2"\ + "--vf_addr_o_xu_a \"0000:51:01.0,0000:51:01.1\""\ + "supports the following options:\n\n"\ + "-p | --num_eth_pfs 2 - default\n" + "-a | --vf_addr_o_xu_a " + "-b | --vf_addr_o_xu_b " + "-c | --vf_addr_o_xu_c " + "-d | --vf_addr_o_xu_d " + "-u | --usecasefile \n"\ + "-h | --help print usage\n"; + + printf("%s", help_content); } -int32_t init_xran(void) +/** + ******************************************************************************* + * + * @fn app_parse_args + * @brief is used to parse incoming app args + * + * @description + * The routine is parse input args and convert them into app startup params + * + * @references + * + * @ingroup xran_lib + * + ******************************************************************************/ +static int32_t +app_parse_cmdline_args(int argc, char ** argv, struct sample_app_params* params) { - BbuXranIoIfStruct *psBbuIo = xran_get_ctx(); - xran_status_t status; - int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; - int32_t nSectorNum; - int32_t i, j, k, z; - - void *ptr; - void *mb; - uint32_t *u32dptr; - uint16_t *u16dptr; - uint8_t *u8dptr; - uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc); - uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr); - - SWXRANInterfaceTypeEnum eInterfaceType; - - XranLibConfigStruct *ptrLibConfig; - - struct xran_buffer_list *pFthTxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; - struct xran_buffer_list *pFthTxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; - struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; - struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; - struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; - struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN]; - - for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) - { - nSectorIndex[nSectorNum] = nSectorNum; - } + int32_t ret = 0; + int32_t c = 0; + int32_t vf_cnt = 0; + int32_t *pInt; + int32_t cnt = 0; + size_t optlen = 0; + char *saveptr = NULL; + char *token = NULL; + int32_t port = 4; + + static struct option long_options[] = { + {"cfgfile", required_argument, 0, 'z'}, + {"usecasefile", required_argument, 0, 'u'}, + {"num_eth_vfs", required_argument, 0, 'p'}, + {"vf_addr_o_xu_a", required_argument, 0, 'a'}, + {"vf_addr_o_xu_b", required_argument, 0, 'b'}, + {"vf_addr_o_xu_c", required_argument, 0, 'c'}, + {"vf_addr_o_xu_d", required_argument, 0, 'd'}, + {"help", no_argument, 0, 'h'}, + {0, 0, 0, 0} + }; - nSectorNum = numCCPorts; - printf ("XRAN front haul xran_mm_init \n"); - status = xran_mm_init (xranHandle, (uint64_t) SW_FPGA_FH_TOTAL_BUFFER_LEN, SW_FPGA_SEGMENT_BUFFER_LEN); - if (status != XRAN_STATUS_SUCCESS) - { - printf ("Failed at XRAN front haul xran_mm_init \n"); - exit(-1); - } + memset(params, 0, sizeof (*params)); - psBbuIo->nInstanceNum = numCCPorts; + while (1) { + //int this_option_optind = optind ? optind : 1; + int option_index = 0; - for (k = 0; k < XRAN_PORTS_NUM; k++) { - status = xran_sector_get_instances (xranHandle, psBbuIo->nInstanceNum,&psBbuIo->nInstanceHandle[k][0]); - if (status != XRAN_STATUS_SUCCESS) - { - printf ("get sector instance failed %d for XRAN nInstanceNum %d\n",k, psBbuIo->nInstanceNum); - exit(-1); - } - for (i = 0; i < psBbuIo->nInstanceNum; i++){ - printf("%s [%d]: CC %d handle %p\n", __FUNCTION__, k, i, psBbuIo->nInstanceHandle[0][i]); - } - } + c = getopt_long(argc, argv, "a:b:c:d:f:h:p:u:v", long_options, &option_index); - printf("Sucess xran_mm_init \n"); - gpXranLibConfig = (XranLibConfigStruct*)malloc(sizeof(XranLibConfigStruct)); - ptrLibConfig = gpXranLibConfig; - if (ptrLibConfig) - { - #if 0 - ptrLibConfig->nDriverCoreId = psBbuIo->nDriverCoreId; - ptrLibConfig->pFecInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FEC][0]); - ptrLibConfig->pFthInstanceHandles = &(psBbuIo->nInstanceHandle[FPGA_FRONTHAUL][0]); - ptrLibConfig->nTimingAdvance = psFPGAInitPara->nTimeAdvance; - ptrLibConfig->nFhConfig = psFPGAInitPara->nEthPorts; - ptrLibConfig->nFhBufIntFlag = 0; //need init fronthaul buffer, then set to 1. - ptrLibConfig->nNrofSfInFrame = NUM_OF_SUBFRAME_PER_FRAME; - ptrLibConfig->nNrOfSlotInSf = pConfigParams->nNumOfSlotPerSubframe; - if (pConfigParams->nNumerology < 3) - { - ptrLibConfig->nSectorNum = psFPGAInitPara->nSecNum; - } - #endif - } - else - { - printf ("could not allocate ptrLibConfig in init_xran\n"); - exit(-1); - } + if (c == -1) + break; - printf("nSectorNum %d\n", nSectorNum); + cnt += 1; + pInt = NULL; + port = 4; - /* Init Memory */ - for(i = 0; inInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init , status %d\n", status); - } - for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) - { - for(z = 0; z < xran_max_antenna_nr; z++){ - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxBuffers[j][i][z][0]; - - for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) - { - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status){ - rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); - } - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - psBbuIo->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; - - if(ptr){ - u32dptr = (uint32_t*)(ptr); - memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen); - // ptr_temp[0] = j; // TTI - // ptr_temp[1] = i; // Sec - // ptr_temp[2] = z; // Ant - // ptr_temp[3] = k; // sym - } + switch (c) { + case 'f': + params->cfg_file = optarg; + optlen = strlen(optarg) + 1; + printf("%s:%d: %s [len %ld]\n",__FUNCTION__, __LINE__, params->cfg_file, optlen); + break; + case 'p': + params->num_vfs = atoi(optarg); + printf("%s:%d: %d\n",__FUNCTION__, __LINE__, params->num_vfs); + break; + case 'u': + params->usecase_file = optarg; + optlen = strlen(optarg) + 1; + printf("%s:%d: %s [len %ld]\n",__FUNCTION__, __LINE__, params->usecase_file, optlen); + break; + case 'a': + port -= 1; + case 'b': + port -= 1; + case 'c': + port -= 1; + case 'd': + port -= 1; + vf_cnt = 0; + optlen = strlen(optarg) + 1; + printf("%s:%d: port %d %s [len %ld]\n",__FUNCTION__, __LINE__, port, optarg, optlen); + token = strtok_r(optarg, ",", &saveptr); + while (token != NULL) { + optlen = strlen(token) + 1; + snprintf(¶ms->vf_pcie_addr[port][vf_cnt][0], optlen, "%s", token); + printf("%s:%d: port %d %s [len %ld]\n",__FUNCTION__, __LINE__, port, ¶ms->vf_pcie_addr[port][vf_cnt][0], optlen); + token = strtok_r(NULL, ",", &saveptr); + vf_cnt +=1; } - } - } - - /* C-plane DL */ - eInterfaceType = XRANFTHTX_SEC_DESC_OUT; - status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc)); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init , status %d\n", status); + break; + case 'h': + app_help(); + exit(0); } + } + return cnt; +} - eInterfaceType = XRANFTHTX_PRB_MAP_OUT; - status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map)); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init , status %d\n", status); +int32_t +app_apply_slot_cfg(RuntimeConfig *config) +{ + int32_t ret = 0; + int32_t slot_idx = 0; + int32_t cc_idx = 0; + int32_t ant_idx = 0; + int32_t section_idx = 0; + int32_t direction = 0; + + int32_t enable = 0; + + for (slot_idx = 0; slot_idx < config->numSlots; slot_idx++) { + for (direction = 0; direction < XRAN_DIR_MAX; direction++) { + for (cc_idx = 0; cc_idx < config->numCC; cc_idx++) { + for (ant_idx = 0; ant_idx < ((direction == XRAN_DIR_UL) ? config->numUlAxc :config->numAxc); ant_idx++) { + for (section_idx = 0; section_idx < config->p_SlotPrbMap[direction][slot_idx]->nPrbElm && section_idx < XRAN_MAX_SECTIONS_PER_SLOT; section_idx++) { + if (config->SlotPrbCCmask[direction][slot_idx][section_idx] & (1L << cc_idx)) { + if (config->SlotPrbAntCMask[direction][slot_idx][section_idx] & (1L << ant_idx)) { + struct xran_prb_map *pRbMap = config->p_RunSlotPrbMap[direction][slot_idx][cc_idx][ant_idx]; + pRbMap->dir = direction; + pRbMap->xran_port = config->o_xu_id; + pRbMap->band_id = 0; + pRbMap->cc_id = cc_idx; + pRbMap->ru_port_id = ant_idx; + pRbMap->tti_id = slot_idx; + pRbMap->start_sym_id = 0; + if (pRbMap->nPrbElm < XRAN_MAX_SECTIONS_PER_SLOT && section_idx < XRAN_MAX_SECTIONS_PER_SLOT) { + struct xran_prb_elm *pMapElmRun = &pRbMap->prbMap[pRbMap->nPrbElm]; + struct xran_prb_elm *pMapElmCfg = &config->p_SlotPrbMap[direction][slot_idx]->prbMap[section_idx]; + memcpy(pMapElmRun, pMapElmCfg, sizeof(struct xran_prb_elm)); + } else { + rte_panic("Incorrect slot cfg\n"); + } + pRbMap->nPrbElm++; + enable = 1; } - - for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) - { - for(z = 0; z < xran_max_antenna_nr; z++){ - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulTxPrbMapBuffers[j][i][z]; - - { - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); - } - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; - psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; - - if(ptr){ - void *sd_ptr; - void *sd_mb; - int elm_id; - struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; - if (startupConfiguration.appMode == APP_O_DU) - memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map)); - else - memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map)); - - for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){ - struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; - for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT],&sd_ptr, &sd_mb); - if(XRAN_STATUS_SUCCESS != status){ - rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status); - } - pPrbElem->p_sec_desc[k] = sd_ptr; - memset(sd_ptr,0,sizeof(struct xran_section_desc)); - } - } - } - } + } +} + } } } } - for(i = 0; inInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); - if(XRAN_STATUS_SUCCESS != status) - { - printf("Failed at xran_bm_init, status %d\n", status); - iAssert(status == XRAN_STATUS_SUCCESS); - } + config->RunSlotPrbMapEnabled = enable; + printf("[%d]config->RunSlotPrbMapEnabled %d\n",config->o_xu_id, config->RunSlotPrbMapEnabled); - for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) - { - for(z = 0; z < xran_max_antenna_nr; z++){ - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxBuffers[j][i][z][0]; - for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) - { - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nFpgaToSW_FTH_RxBufferLen; // 1 symbols 3200bytes - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); - } - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb; - if(ptr){ - u32dptr = (uint32_t*)(ptr); - uint8_t *ptr_temp = (uint8_t *)ptr; - memset(u32dptr, 0x0, nFpgaToSW_FTH_RxBufferLen); - // ptr_temp[0] = j; // TTI - // ptr_temp[1] = i; // Sec - // ptr_temp[2] = z; // Ant - // ptr_temp[3] = k; // sym - } - } - } - } + return ret; +} - /* C-plane */ - eInterfaceType = XRANFTHTX_SEC_DESC_IN; - status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc)); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init , status %d\n", status); - } - eInterfaceType = XRANFTHRX_PRB_MAP_IN; - status = xran_bm_init(psBbuIo->nInstanceHandle[0][i], &psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map)); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init, status %d\n", status); - } +int32_t +app_parse_all_cfgs(struct sample_app_params* p_args, UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg) +{ + int32_t ret = 0; + int32_t vf_num = 0; + int32_t o_xu_id = 0; + char filename[512]; + char *dir; + size_t len; + + if (p_use_cfg) { + memset(p_use_cfg, 0, sizeof(UsecaseConfig)); + } else { + printf("p_use_cfg error.\n"); + exit(-1); + } - for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) { - for(z = 0; z < xran_max_antenna_nr; z++){ - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFrontHaulRxPrbMapBuffers[j][i][z]; - { - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_allocate_buffer , status %d\n",status); - } - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; - psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; - if(ptr){ - void *sd_ptr; - void *sd_mb; - int elm_id; - struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; - - if (startupConfiguration.appMode == APP_O_DU) - memcpy(ptr, &startupConfiguration.PrbMapUl, sizeof(struct xran_prb_map)); - else - memcpy(ptr, &startupConfiguration.PrbMapDl, sizeof(struct xran_prb_map)); - - for (elm_id = 0; elm_id < p_rb_map->nPrbElm; elm_id++){ - struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; - for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i], psBbuIo->nBufPoolIndex[nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN],&sd_ptr, &sd_mb); - if(XRAN_STATUS_SUCCESS != status){ - rte_panic("SD Failed at xran_bm_allocate_buffer , status %d\n",status); - } - pPrbElem->p_sec_desc[k] = sd_ptr; - memset(sd_ptr,0,sizeof(struct xran_section_desc)); - } - } - } - } - } - } + if (p_o_xu_cfg) { + int32_t i; + RuntimeConfig* p_o_xu_cfg_loc = p_o_xu_cfg; + for (i = 0; i < XRAN_PORTS_NUM; i++) { + config_init(p_o_xu_cfg_loc); + p_o_xu_cfg_loc++; + } + } else { + printf("p_o_xu_cfg error.\n"); + exit(-1); } + if (p_args) { + if (p_args->usecase_file) { /* use case for multiple O-RUs */ + printf("p_args->usecase_file (%s)\n", p_args->usecase_file); + len = strlen(p_args->usecase_file) + 1; + if (len > 511){ + printf("app_parse_all_cfgs: Name of p_args->usecase_file, %s is too long. Maximum is 511 characters!!\n", p_args->usecase_file); + return -1; + } else { + strncpy(filename, p_args->usecase_file, len); + } + if (parseUsecaseFile(filename, p_use_cfg) != 0) { + printf("Use case config file error.\n"); + return -1; + } + if (p_use_cfg->oXuNum > XRAN_PORTS_NUM) { + printf("Use case config file error.\n"); + return -1; + } - // add prach rx buffer - for(i = 0; inInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],XRAN_N_FE_BUF_LEN*xran_max_antenna_nr*XRAN_NUM_OF_SYMBOL_PER_SLOT, FPGA_TO_SW_PRACH_RX_BUFFER_LEN); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init, status %d\n", status); - } - for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) - { - for(z = 0; z < xran_max_antenna_nr; z++){ - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; // ant number. - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHPrachRxBuffers[j][i][z][0]; - for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) - { - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status); - } - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; - if(ptr){ - u32dptr = (uint32_t*)(ptr); - memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN); - } + /* use cmdline pcie address */ + for (o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum && o_xu_id < XRAN_PORTS_NUM; o_xu_id++) { + for (vf_num = 0; vf_num < XRAN_VF_MAX && p_args->num_vfs ; vf_num++) { + strncpy(&p_use_cfg->o_xu_pcie_bus_addr[o_xu_id][vf_num][0], &p_args->vf_pcie_addr[o_xu_id][vf_num][0], strlen(&p_args->vf_pcie_addr[o_xu_id][vf_num][0])); } } - } + dir = dirname(p_args->usecase_file); + for (o_xu_id = 0; o_xu_id < p_use_cfg->oXuNum && o_xu_id < XRAN_PORTS_NUM; o_xu_id++) { + memset(filename, 0, sizeof(filename)); + printf("dir (%s)\n",dir); + len = strlen(dir) + 1; + if (len > 511){ + printf("app_parse_all_cfgs: Name of directory, %s, xu_id = %d is too long. Maximum is 511 characters!!\n", dir, o_xu_id); + return -1; + } else { + strncpy(filename, dir, len); } - - /* add SRS rx buffer */ - for(i = 0; inInstanceHandle[0][i],&psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN*xran_max_ant_array_elm_nr*XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT, nSW_ToFpga_FTH_TxBufferLen); - - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_init, status %d\n", status); - } - for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) - { - for(z = 0; z < xran_max_ant_array_elm_nr; z++){ - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_ant_array_elm_nr; /* ant number */ - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psBbuIo->sFHSrsRxBuffers[j][i][z][0]; - for(k = 0; k < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; k++) - { - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = nSW_ToFpga_FTH_TxBufferLen; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[0][i],psBbuIo->nBufPoolIndex[nSectorIndex[i]][eInterfaceType],&ptr, &mb); - if(XRAN_STATUS_SUCCESS != status) { - rte_panic("Failed at xran_bm_allocate_buffer, status %d\n",status); + strncat(filename, "/", 1); + len +=1; + len = (sizeof(filename)) - len; + + if (len > strlen(p_use_cfg->o_xu_cfg_file[o_xu_id])) { + strncat(filename, p_use_cfg->o_xu_cfg_file[o_xu_id], RTE_MIN (len, strlen(p_use_cfg->o_xu_cfg_file[o_xu_id]))); + } else { + printf("File name error\n"); + return -1; + } + printf("cfg_file (%s)\n",filename); + printf("\n=================== O-XU %d===================\n", o_xu_id); + if (parseConfigFile(filename, p_o_xu_cfg) != 0) { + printf("Configuration file error\n"); + return -1; + } + p_o_xu_cfg->o_xu_id = o_xu_id; + if (p_o_xu_cfg->SlotNum_fileEnabled) { + if (parseSlotConfigFile(dir, p_o_xu_cfg) != 0) { + printf("parseSlotConfigFiles\n"); + return -1; } - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; - if(ptr){ - u32dptr = (uint32_t*)(ptr); - memset(u32dptr, 0x0, nSW_ToFpga_FTH_TxBufferLen); + if (app_apply_slot_cfg(p_o_xu_cfg)!= 0) { + printf("app_apply_slot_cfg\n"); + return -1; } } + p_o_xu_cfg++; } - } + } else { + printf("p_args error\n"); + app_help(); + exit(-1); } - - for(i=0; isFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList); - pFthTxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); - pFthRxBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList); - pFthRxPrbMapBuffer[i][z][j] = &(psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); - pFthRxRachBuffer[i][z][j] = &(psBbuIo->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList); - } + return ret; +} - for(z = 0; z < xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr; z++){ - pFthRxSrsBuffer[i][z][j] = &(psBbuIo->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList); - } - } - } +int32_t +app_setup_o_xu_buffers(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg, struct xran_fh_init* p_xran_fh_init) +{ + int32_t ret = 0; + int32_t i = 0; + int32_t j = 0; + char filename[256]; + struct o_xu_buffers *p_iq = NULL; - if(NULL != psBbuIo->nInstanceHandle[0]) - { - /* add pusch callback */ - for (i = 0; inInstanceHandle[0][i], - pFthTxBuffer[i], - pFthTxPrbMapBuffer[i], - pFthRxBuffer[i], - pFthRxPrbMapBuffer[i], - xran_fh_rx_callback, &pFthRxBuffer[i][0]); - } + if (p_o_xu_cfg->p_buff) { + p_iq = p_o_xu_cfg->p_buff; + printf("IQ files size is %d slots\n", p_o_xu_cfg->numSlots); - /* add prach callback here */ - for (i = 0; inInstanceHandle[0][i], pFthRxRachBuffer[i], - xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]); - } + p_iq->iq_playback_buffer_size_dl = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * + app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, + p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA) *4L); - /* add SRS callback here */ - for (i = 0; inInstanceHandle[0][i], pFthRxSrsBuffer[i], - xran_fh_rx_srs_callback,&pFthRxSrsBuffer[i][0]); - } + p_iq->iq_playback_buffer_size_ul = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * + app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, + p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA) *4L); - ptrLibConfig->nFhBufIntFlag = 1; - } - return status; -} + /* 10 * [14*32*273*2*2] = 4892160 bytes */ + p_iq->iq_bfw_buffer_size_dl = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * p_o_xu_cfg->antElmTRx * + app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, + p_o_xu_cfg->nDLBandwidth, p_o_xu_cfg->nDLAbsFrePointA) *4L); -int init_xran_iq_content(void) -{ - BbuXranIoIfStruct *psBbuIo = xran_get_ctx(); - xran_status_t status; - int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; - int32_t nSectorNum; - int32_t cc_id, ant_id, sym_id, tti; - int32_t flowId; - - uint8_t frame_id = 0; - uint8_t subframe_id = 0; - uint8_t slot_id = 0; - uint8_t sym = 0; - - void *ptr; - uint32_t *u32dptr; - uint16_t *u16dptr; - uint8_t *u8dptr; - - uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc); - uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr); - - char *pos = NULL; - struct xran_prb_map *pRbMap = NULL; - - for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) - { - nSectorIndex[nSectorNum] = nSectorNum; - } - nSectorNum = numCCPorts; - printf ("init_xran_iq_content\n"); + /* 10 * [14*32*273*2*2] = 4892160 bytes */ + p_iq->iq_bfw_buffer_size_ul = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * + app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, + p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA) *4L); - /* Init Memory */ - for(cc_id = 0; cc_id sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; - if(pRbMap){ - if (xranInit.DynamicSectionEna == 0){ - pRbMap->dir = XRAN_DIR_DL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = cc_id; - pRbMap->ru_port_id = ant_id; - pRbMap->tti_id = tti; - pRbMap->start_sym_id = 0; - pRbMap->nPrbElm = 1; - pRbMap->prbMap[0].nStartSymb = 0; - pRbMap->prbMap[0].numSymb = 14; - pRbMap->prbMap[0].nRBStart = 0; - pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs; - pRbMap->prbMap[0].nBeamIndex = 0; - pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; - pRbMap->prbMap[0].iqWidth = 16; - } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B - && startupConfiguration.appMode == APP_O_DU - && sym_id == 0){ /* BF Ws are per slot */ - int idxElm = 0; - char* dl_bfw_pos = ((char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId]; - struct xran_prb_elm* p_pRbMapElm = NULL; - for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){ - p_pRbMapElm = &pRbMap->prbMap[idxElm]; - p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx; - if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){ - int16_t ext_len = 9600; - int16_t ext_sec_total = 0; - int8_t * ext_buf =(int8_t*) xran_malloc(ext_len); - int8_t * ext_buf_start = ext_buf; - if (ext_buf){ - ext_buf += (RTE_PKTMBUF_HEADROOM + - sizeof (struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_common_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_len -= (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_common_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf, - ext_len, - (int16_t *) (dl_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4), - p_pRbMapElm->nRBSize, - pXranConf->nAntElmTRx, - p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod); - if(ext_sec_total > 0){ - p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start; - p_pRbMapElm->bf_weight.p_ext_section = ext_buf; - p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total; - }else { - rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total); - } - } else { - rte_panic("xran_malloc return NULL\n"); - } - } - } - } - } else { - printf("DL pRbMap ==NULL\n"); - exit(-1); - } + /* 10 * [1*273*2*2] = 349440 bytes */ + p_iq->iq_srs_buffer_size_ul = (p_o_xu_cfg->numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * + app_xran_get_num_rbs(p_o_xu_cfg->xranTech, p_o_xu_cfg->mu_number, + p_o_xu_cfg->nULBandwidth, p_o_xu_cfg->nULAbsFrePointA)*4L); - pos = ((char*)p_tx_play_buffer[flowId]) + tx_play_buffer_position[flowId]; - ptr = psBbuIo->sFrontHaulTxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - - if(ptr && pos){ - int idxElm = 0; - u8dptr = (uint8_t*)ptr; - int16_t payload_len = 0; - - uint8_t *dst = (uint8_t *)u8dptr; - uint8_t *src = (uint8_t *)pos; - struct xran_prb_elm* p_prbMapElm = &pRbMap->prbMap[idxElm]; - dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod); - for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) { - struct xran_section_desc *p_sec_desc = NULL; - p_prbMapElm = &pRbMap->prbMap[idxElm]; - p_sec_desc = p_prbMapElm->p_sec_desc[sym_id]; - - if(p_sec_desc == NULL){ - printf ("p_sec_desc == NULL\n"); - exit(-1); - } - src = (uint8_t *)(pos + p_prbMapElm->nRBStart*N_SC_PER_PRB*4L); - - if(p_prbMapElm->compMethod == XRAN_COMPMETHOD_NONE) { - payload_len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; - rte_memcpy(dst, src, payload_len); - - } else if (p_prbMapElm->compMethod == XRAN_COMPMETHOD_BLKFLOAT) { - struct xranlib_compress_request bfp_com_req; - struct xranlib_compress_response bfp_com_rsp; - - memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request)); - memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response)); - - bfp_com_req.data_in = (int16_t*)src; - bfp_com_req.numRBs = p_prbMapElm->nRBSize; - bfp_com_req.len = p_prbMapElm->nRBSize*N_SC_PER_PRB*4L; - bfp_com_req.compMethod = p_prbMapElm->compMethod; - bfp_com_req.iqWidth = p_prbMapElm->iqWidth; - - bfp_com_rsp.data_out = (int8_t*)dst; - bfp_com_rsp.len = 0; - - xranlib_compress_avx512(&bfp_com_req, &bfp_com_rsp); - payload_len = bfp_com_rsp.len; - - }else { - printf ("p_prbMapElm->compMethod == %d is not supported\n", - p_prbMapElm->compMethod); - exit(-1); - } - - /* update RB map for given element */ - p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(dst, u8dptr); - p_sec_desc->iq_buffer_len = payload_len; - - /* add headroom for ORAN headers between IQs for chunk of RBs*/ - dst += payload_len; - dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod); - } - } else { - exit(-1); - printf("ptr ==NULL\n"); - } + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + p_iq->p_tx_play_buffer[i] = (int16_t*)malloc(p_iq->iq_playback_buffer_size_dl); + p_iq->tx_play_buffer_size[i] = (int32_t)p_iq->iq_playback_buffer_size_dl; + if (p_iq->p_tx_play_buffer[i] == NULL) + exit(-1); - /* c-plane UL */ - pRbMap = (struct xran_prb_map *) psBbuIo->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; - if(pRbMap){ - if (xranInit.DynamicSectionEna == 0){ - pRbMap->dir = XRAN_DIR_UL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = cc_id; - pRbMap->ru_port_id = ant_id; - pRbMap->tti_id = tti; - pRbMap->start_sym_id = 0; - pRbMap->nPrbElm = 1; - pRbMap->prbMap[0].nRBStart = 0; - pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs; - pRbMap->prbMap[0].nStartSymb = 0; - pRbMap->prbMap[0].numSymb = 14; - pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_offset = 0; - pRbMap->prbMap[0].p_sec_desc[sym_id]->iq_buffer_len = pXranConf->nULRBs *4L; - pRbMap->prbMap[0].nBeamIndex = 0; - pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; - } else if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B - && startupConfiguration.appMode == APP_O_DU - && sym_id == 0){ - int idxElm = 0; - char * ul_bfw_pos = ((char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId]; - struct xran_prb_elm* p_pRbMapElm = NULL; - - for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++){ - p_pRbMapElm = &pRbMap->prbMap[idxElm]; - p_pRbMapElm->bf_weight.nAntElmTRx = pXranConf->nAntElmTRx; - if(p_pRbMapElm->BeamFormingType == XRAN_BEAM_WEIGHT && p_pRbMapElm->bf_weight_update){ - int16_t ext_len = 9600; - int16_t ext_sec_total = 0; - int8_t * ext_buf =(int8_t*) xran_malloc(ext_len); - int8_t * ext_buf_start = ext_buf; - int idRb = 0; - int16_t *ptr = NULL; - int i; - if (ext_buf){ - - ext_buf += (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_section1_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_len -= (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_section1_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ptr = (int16_t*)(ul_bfw_pos +(p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4); - ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf, - ext_len, - (int16_t *) (ul_bfw_pos + (p_pRbMapElm->nRBStart*pXranConf->nAntElmTRx)*4), - p_pRbMapElm->nRBSize, - pXranConf->nAntElmTRx, - p_pRbMapElm->iqWidth, p_pRbMapElm->compMethod); - if(ext_sec_total > 0){ - p_pRbMapElm->bf_weight.p_ext_start = ext_buf_start; - p_pRbMapElm->bf_weight.p_ext_section = ext_buf; - p_pRbMapElm->bf_weight.ext_section_sz = ext_sec_total; - }else { - rte_panic("xran_cp_populate_section_ext_1 return error [%d]\n", ext_sec_total); - } - } else { - rte_panic("xran_malloc return NULL\n"); - } - } - } - } - } else { - printf("DL pRbMap ==NULL\n"); - exit(-1); - } + p_iq->tx_play_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->ant_file[i], + "DL IFFT IN IQ Samples in binary format", + (uint8_t*)p_iq->p_tx_play_buffer[i], + p_iq->tx_play_buffer_size[i], + 1); + p_iq->tx_play_buffer_position[i] = 0; + } - tx_play_buffer_position[flowId] += pXranConf->nDLRBs*N_SC_PER_PRB*4; + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { - if(tx_play_buffer_position[flowId] >= tx_play_buffer_size[flowId]) - tx_play_buffer_position[flowId] = 0; + p_iq->p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(p_iq->iq_bfw_buffer_size_dl); + p_iq->tx_dl_bfw_buffer_size[i] = (int32_t)p_iq->iq_bfw_buffer_size_dl; - if(pXranConf->ru_conf.xranCat == XRAN_CATEGORY_B - && startupConfiguration.appMode == APP_O_DU - && sym_id == 0) { - tx_dl_bfw_buffer_position[flowId] += (pXranConf->nDLRBs*pXranConf->nAntElmTRx)*4; - if(tx_dl_bfw_buffer_position[flowId] >= tx_dl_bfw_buffer_size[flowId]) - tx_dl_bfw_buffer_position[flowId] = 0; - - tx_ul_bfw_buffer_position[flowId] += (pXranConf->nULRBs*pXranConf->nAntElmTRx)*4; - if(tx_ul_bfw_buffer_position[flowId] >= tx_ul_bfw_buffer_size[flowId]) - tx_ul_bfw_buffer_position[flowId] = 0; - } - } else { - //printf("flowId %d\n", flowId); - } - } - } - - /* prach TX for RU only */ - if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){ - for(ant_id = 0; ant_id < xran_max_antenna_nr; ant_id++){ - for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { - flowId = startupConfiguration.numAxc*cc_id + ant_id; - - if(p_tx_prach_play_buffer[flowId]){ - pos = ((char*)p_tx_prach_play_buffer[flowId]); - - ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - - if(ptr && pos){ - u32dptr = (uint32_t*)(ptr); - /* duplicate full PRACH (repetition * occassions ) in every symbol */ - memset(u32dptr,0 , PRACH_PLAYBACK_BUFFER_BYTES); - rte_memcpy(u32dptr, pos, RTE_MIN(PRACH_PLAYBACK_BUFFER_BYTES, tx_prach_play_buffer_size[flowId])); - } else { - exit(-1); - printf("ptr ==NULL\n"); - } - } else { - //printf("flowId %d\n", flowId); - } - } - } - } - - /* SRS TX for RU only */ - if(startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){ - for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++){ - for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++) { - flowId = startupConfiguration.antElmTRx*cc_id + ant_id; - - if(p_tx_srs_play_buffer[flowId]){ - pos = ((char*)p_tx_srs_play_buffer[flowId]) + tx_srs_play_buffer_position[flowId]; - ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - - if(startupConfiguration.srsSymMask & (1 << sym_id) ){ - if(ptr && pos){ - u32dptr = (uint32_t*)(ptr); - memset(u32dptr,0 , pXranConf->nULRBs*N_SC_PER_PRB*4); - rte_memcpy(u32dptr, pos, pXranConf->nULRBs*N_SC_PER_PRB*4); - } else { - exit(-1); - printf("ptr ==NULL\n"); - } - } - - tx_srs_play_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; - - if(tx_srs_play_buffer_position[flowId] >= tx_srs_play_buffer_size[flowId]) - tx_srs_play_buffer_position[flowId] = 0; - } else { - //printf("flowId %d\n", flowId); - } - } - } - } - } - } - - return 0; -} - -void stop_xran(void) -{ - xran_status_t status = 0; - SWXRANInterfaceTypeEnum eInterfaceType; - - free(gpXranLibConfig); - gpXranLibConfig = NULL; - - status += xran_mm_destroy(xranHandle)*2; - - if(XRAN_STATUS_SUCCESS != status) - { - printf("Failed at xran_mm_destroy, status %d\n",status); - iAssert(status == XRAN_STATUS_SUCCESS); - } -} - -int get_xran_iq_content(void) -{ - BbuXranIoIfStruct *psBbuIo = xran_get_ctx(); - xran_status_t status; - int32_t nSectorIndex[XRAN_MAX_SECTOR_NR]; - int32_t nSectorNum; - int32_t cc_id, ant_id, sym_id, tti; - int32_t flowId; - - uint8_t frame_id = 0; - uint8_t subframe_id = 0; - uint8_t slot_id = 0; - uint8_t sym = 0; - - void *ptr; - uint32_t *u32dptr; - uint16_t *u16dptr; - uint8_t *u8dptr; - - uint32_t xran_max_antenna_nr = RTE_MAX(startupConfiguration.numAxc, startupConfiguration.numUlAxc); - uint32_t xran_max_ant_array_elm_nr = RTE_MAX(startupConfiguration.antElmTRx, xran_max_antenna_nr); - - char *pos = NULL; - - for (nSectorNum = 0; nSectorNum < XRAN_MAX_SECTOR_NR; nSectorNum++) - { - nSectorIndex[nSectorNum] = nSectorNum; - } - nSectorNum = numCCPorts; - printf ("get_xran_iq_content\n"); - - /* Init Memory */ - for(cc_id = 0; cc_id sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; - if(pRbMap == NULL) - exit(-1); - - if(startupConfiguration.appMode == APP_O_RU) - flowId = startupConfiguration.numAxc * cc_id + ant_id; - else - flowId = startupConfiguration.numUlAxc * cc_id + ant_id; - - for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) { - pRbElm = &pRbMap->prbMap[0]; - if(pRbMap->nPrbElm == 1){ - if(p_rx_log_buffer[flowId]) { - pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId]; - ptr = psBbuIo->sFrontHaulRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - if(ptr){ - u32dptr = (uint32_t*)(ptr); - rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4L , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4L); - }else { - printf("[%d][%d][%d][%d]ptr ==NULL\n",tti,cc_id,ant_id, sym_id); - } - } - } else { - for(idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) { - pRbElm = &pRbMap->prbMap[idxElm]; - p_sec_desc = pRbElm->p_sec_desc[sym_id]; - if(p_rx_log_buffer[flowId] && p_sec_desc){ - if(sym_id >= pRbElm->nStartSymb && sym_id < pRbElm->nStartSymb + pRbElm->numSymb){ - pos = ((char*)p_rx_log_buffer[flowId]) + rx_log_buffer_position[flowId]; - ptr = p_sec_desc->pData; - if(ptr){ - int32_t payload_len = 0; - u32dptr = (uint32_t*)(ptr); - if (pRbElm->compMethod != XRAN_COMPMETHOD_NONE){ - struct xranlib_decompress_request bfp_decom_req; - struct xranlib_decompress_response bfp_decom_rsp; - - memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); - memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); - - bfp_decom_req.data_in = (int8_t *)u32dptr; - bfp_decom_req.numRBs = pRbElm->nRBSize; - bfp_decom_req.len = (3* pRbElm->iqWidth + 1)*pRbElm->nRBSize; - bfp_decom_req.compMethod = pRbElm->compMethod; - bfp_decom_req.iqWidth = pRbElm->iqWidth; - - bfp_decom_rsp.data_out = (int16_t *)(pos + pRbElm->nRBStart*N_SC_PER_PRB*4); - bfp_decom_rsp.len = 0; - - xranlib_decompress_avx512(&bfp_decom_req, &bfp_decom_rsp); - payload_len = bfp_decom_rsp.len; - - } else { - rte_memcpy(pos + pRbElm->nRBStart*N_SC_PER_PRB*4 , u32dptr, pRbElm->nRBSize*N_SC_PER_PRB*4); - } - } - } - } - } - } - rx_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; - - if(rx_log_buffer_position[flowId] >= rx_log_buffer_size[flowId]) - rx_log_buffer_position[flowId] = 0; - } - - /* prach RX for O-DU only */ - if(startupConfiguration.appMode == APP_O_DU) { - flowId = startupConfiguration.numAxc * cc_id + ant_id; - for(sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++){ - if(p_prach_log_buffer[flowId]){ - /* (0-79 slots) 10ms of IQs */ - pos = ((char*)p_prach_log_buffer[flowId]) + prach_log_buffer_position[flowId]; - ptr = psBbuIo->sFHPrachRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; //8192 144 - if(ptr){ - u32dptr = (uint32_t*)(ptr); - rte_memcpy(pos, u32dptr, PRACH_PLAYBACK_BUFFER_BYTES); - }else - printf("ptr ==NULL\n"); - - prach_log_buffer_position[flowId] += PRACH_PLAYBACK_BUFFER_BYTES; - - if(prach_log_buffer_position[flowId] >= prach_log_buffer_size[flowId]) - prach_log_buffer_position[flowId] = 0; - } else { - //printf("flowId %d\n", flowId); - } - } - } - } - - /* SRS RX for O-DU only */ - if(startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs) { - for(ant_id = 0; ant_id < xran_max_ant_array_elm_nr; ant_id++){ - flowId = startupConfiguration.antElmTRx*cc_id + ant_id; - for(sym_id = 0; sym_id < XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT; sym_id++){ - if(p_srs_log_buffer[flowId]){ - pos = ((char*)p_srs_log_buffer[flowId]) + srs_log_buffer_position[flowId]; - ptr = psBbuIo->sFHSrsRxBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - if(ptr){ - u32dptr = (uint32_t*)(ptr); - rte_memcpy(pos, u32dptr, pXranConf->nULRBs*N_SC_PER_PRB*4); - }else - printf("ptr ==NULL\n"); - - srs_log_buffer_position[flowId] += pXranConf->nULRBs*N_SC_PER_PRB*4; - - if(srs_log_buffer_position[flowId] >= srs_log_buffer_size[flowId]) - srs_log_buffer_position[flowId] = 0; - } else { - //printf("flowId %d\n", flowId); - } - } - } - } - } - } - - return 0; -} - -void version_print(void) -{ - char sysversion[100]; - char *compilation_date = __DATE__; - char *compilation_time = __TIME__; - - uint32_t nLen; - - snprintf(sysversion, 99, "Version: %s", VERSIONX); - nLen = strlen(sysversion); - - printf("\n\n"); - printf("===========================================================================================================\n"); - printf("SAMPLE-APP VERSION\n"); - printf("===========================================================================================================\n"); - - printf("%s\n", sysversion); - printf("build-date: %s\n", compilation_date); - printf("build-time: %s\n", compilation_time); -} - -static void app_Help(void) -{ - char help_content[] = \ - "sample application\n\n"\ - "Usage: sample-app config_file_o_du.dat -p 2 0000:21:02.0 0000:21:02.1 0000:21:0a.0 0000:21:0a.1\n\n"\ - "supports the following parameters:\n\n"\ - "-p | --num_eth_pfs 1 - default sanity test\n" - "-c | --cfgfile \n"\ - "-h | --help print usage\n"; - - printf("%s", help_content); -} - -/** - ******************************************************************************* - * - * @fn app_parse_args - * @brief is used to parse incoming app args - * - * @param[i] argc - app arg count - * @param[i] argv - array of args - * @param[o] params - app startup params filled basing on args parse - * @return number of parsed args - * - * @description - * The routine is parse input args and convert them into app startup params - * - * @references - * MS-111070-SP - * - * @ingroup icc_service_unit_test - * - ******************************************************************************/ -static int app_parse_args(int argc, char ** argv, struct sample_app_params* params) -{ - int c; - int *pInt; - int cnt = 0; - - struct option long_options[] = { - {"cfgfile", required_argument, 0, 'c'}, - {"num_eth_pfs", required_argument, 0, 'p'}, - {"help", no_argument, 0, 'h'}, - {0, 0, 0, 0} - }; - - memset(params, 0, sizeof (*params)); - - while (1) { - //int this_option_optind = optind ? optind : 1; - int option_index = 0; - - c = getopt_long(argc, argv, "c:p:h", long_options, &option_index); - - if (c == -1) - break; - - cnt += 1; - pInt = NULL; - - switch (c) { - case 'p': // test Case selection - pInt = ¶ms->num_vfs; - break; - case 'c': - params->cfg_file = optarg; - break; - case 'h': - app_Help(); - exit(0); - } - - if (pInt && optarg) { - // get int arg - if (optarg[0] == '0' && (optarg[1] == 'x' || optarg[1] == 'X')) { - sscanf(optarg, "%x", (unsigned *) pInt); - } else { - *pInt = atoi(optarg); - } - } - } - return cnt; -} - -int32_t app_init_set_eAxCId_conf(struct xran_eaxcid_config *p_eAxC_cfg, RuntimeConfig * p_s_cfg) -{ - int32_t shift; - uint16_t mask; - - if(p_s_cfg->DU_Port_ID_bitwidth && p_s_cfg->BandSector_ID_bitwidth && p_s_cfg->CC_ID_bitwidth - && p_s_cfg->RU_Port_ID_bitwidth && - (p_s_cfg->DU_Port_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->CC_ID_bitwidth - + p_s_cfg->RU_Port_ID_bitwidth) == 16 /* eAxC ID subfields are 16 bits */ - ){ /* bit mask provided */ - - mask = 0; - p_eAxC_cfg->bit_ruPortId = 0; - for (shift = 0; shift < p_s_cfg->RU_Port_ID_bitwidth; shift++){ - mask |= 1 << shift; - } - p_eAxC_cfg->mask_ruPortId = mask; - - p_eAxC_cfg->bit_ccId = p_s_cfg->RU_Port_ID_bitwidth; - mask = 0; - for (shift = p_s_cfg->RU_Port_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift++){ - mask |= 1 << shift; - } - p_eAxC_cfg->mask_ccId = mask; - - - p_eAxC_cfg->bit_bandSectorId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; - mask = 0; - for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth; shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; shift++){ - mask |= 1 << shift; - } - p_eAxC_cfg->mask_bandSectorId = mask; - - p_eAxC_cfg->bit_cuPortId = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; - mask = 0; - for (shift = p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth; - shift < p_s_cfg->RU_Port_ID_bitwidth + p_s_cfg->CC_ID_bitwidth + p_s_cfg->BandSector_ID_bitwidth + p_s_cfg->DU_Port_ID_bitwidth; shift++){ - mask |= 1 << shift; - } - p_eAxC_cfg->mask_cuPortId = mask; - - - } else { /* bit mask config is not provided */ - switch (p_s_cfg->xranCat){ - case XRAN_CATEGORY_A: { - p_eAxC_cfg->mask_cuPortId = 0xf000; - p_eAxC_cfg->mask_bandSectorId = 0x0f00; - p_eAxC_cfg->mask_ccId = 0x00f0; - p_eAxC_cfg->mask_ruPortId = 0x000f; - p_eAxC_cfg->bit_cuPortId = 12; - p_eAxC_cfg->bit_bandSectorId = 8; - p_eAxC_cfg->bit_ccId = 4; - p_eAxC_cfg->bit_ruPortId = 0; - break; - } - case XRAN_CATEGORY_B: { - p_eAxC_cfg->mask_cuPortId = 0xf000; - p_eAxC_cfg->mask_bandSectorId = 0x0c00; - p_eAxC_cfg->mask_ccId = 0x0300; - p_eAxC_cfg->mask_ruPortId = 0x00ff; /* more than [0-127] eAxC */ - p_eAxC_cfg->bit_cuPortId = 12; - p_eAxC_cfg->bit_bandSectorId = 10; - p_eAxC_cfg->bit_ccId = 8; - p_eAxC_cfg->bit_ruPortId = 0; - break; - } - default: - rte_panic("Incorrect Category\n"); - } - } - - if(p_s_cfg->xranCat == XRAN_CATEGORY_A) - p_s_cfg->numUlAxc = p_s_cfg->numAxc; - - printf("bit_cuPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_cuPortId, p_eAxC_cfg->mask_cuPortId); - printf("bit_bandSectorId %2d mask 0x%04x\n",p_eAxC_cfg->bit_bandSectorId, p_eAxC_cfg->mask_bandSectorId); - printf("bit_ccId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ccId, p_eAxC_cfg->mask_ccId); - printf("ruPortId %2d mask 0x%04x\n",p_eAxC_cfg->bit_ruPortId, p_eAxC_cfg->mask_ruPortId); - - return 0; -} - -int main(int argc, char *argv[]) -{ - int i; - int j, len; - int lcore_id = 0; - char filename[256]; - char prefix_name[256]; - uint32_t nCenterFreq; - int32_t xret = 0; - struct stat st = {0}; - uint32_t filenameLength = strlen(argv[1]); - enum xran_if_state xran_curr_if_state = XRAN_INIT; - struct sample_app_params arg_params; - - - uint64_t nTotalTime; - uint64_t nUsedTime; - uint32_t nCoreUsed; - float nUsedPercent; - - app_parse_args(argc, argv, &arg_params); - - if( (arg_params.num_vfs % 2) != 0 || arg_params.num_vfs >= XRAN_VF_MAX){ - printf("warning: arg_params.num_vfs is not correct\n"); - exit(-1); - } - - if (argc == 3 + arg_params.num_vfs){ - printf("Need at least two argument - the PCI address of the network port"); - exit(-1); - } - - if (filenameLength >= 256) - { - printf("Config file name input is too long, exiting!\n"); - exit(-1); - } - - version_print(); - - //add for Klocworks - printf("arg_params.cfg_file (%s)\n", arg_params.cfg_file); - len = strlen(arg_params.cfg_file) + 1; - if (len > (sizeof(filename) - 10)) - len = (sizeof(filename) - 10); - strncpy(filename, arg_params.cfg_file, (sizeof(filename) - 10)); - filename[len] = '\0'; - - if (xran_is_synchronized() != 0) - printf("Machine is not synchronized using PTP!\n"); - else - printf("Machine is synchronized using PTP!\n"); - - memset(&startupConfiguration, 0, sizeof(RuntimeConfig)); - - if (parseConfigFile(filename, (RuntimeConfig*)&startupConfiguration) != 0) { - printf("Configuration file error.\n"); - return -1; - } - - if(startupConfiguration.ant_file[0] == NULL){ - printf("it looks like test vector for antennas were not provided\n"); - exit(-1); - } - - if (startupConfiguration.numCC > XRAN_MAX_SECTOR_NR) { - printf("Number of cells %d exceeds max number supported %d!\n", startupConfiguration.numCC, XRAN_MAX_SECTOR_NR); - startupConfiguration.numCC = XRAN_MAX_SECTOR_NR; - - } - if (startupConfiguration.antElmTRx > XRAN_MAX_ANT_ARRAY_ELM_NR) { - printf("Number of Antenna elements %d exceeds max number supported %d!\n", startupConfiguration.antElmTRx, XRAN_MAX_ANT_ARRAY_ELM_NR); - startupConfiguration.antElmTRx = XRAN_MAX_ANT_ARRAY_ELM_NR; - } - - numCCPorts = startupConfiguration.numCC; - num_eAxc = startupConfiguration.numAxc; - - printf("numCCPorts %d num_eAxc%d\n", numCCPorts, num_eAxc); - - if (startupConfiguration.mu_number <= 1){ - nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/ - nFpgaToSW_PRACH_RxBufferLen = 8192; - nSW_ToFpga_FTH_TxBufferLen = 13168 + /* 273*12*4 + 64* + ETH AND ORAN HDRs */ - XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct radio_app_common_hdr) + - sizeof(struct data_section_hdr)); - } else if (startupConfiguration.mu_number == 3){ - nFpgaToSW_FTH_RxBufferLen = 3328; - nFpgaToSW_PRACH_RxBufferLen = 8192; - nSW_ToFpga_FTH_TxBufferLen = 3328 + - XRAN_MAX_SECTIONS_PER_SYM * (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct radio_app_common_hdr) + - sizeof(struct data_section_hdr)); - } else { - printf("given numerology is not supported %d\n", startupConfiguration.mu_number); - exit(-1); - } - printf("nSW_ToFpga_FTH_TxBufferLen %d\n", nSW_ToFpga_FTH_TxBufferLen); - - memset(&xranInit, 0, sizeof(struct xran_fh_init)); - - if(startupConfiguration.appMode == APP_O_DU) { - printf("set O-DU\n"); - xranInit.io_cfg.id = 0;/* O-DU */ - xranInit.io_cfg.core = startupConfiguration.io_core; - xranInit.io_cfg.system_core = startupConfiguration.system_core; - xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_worker; /* do not start */ - xranInit.io_cfg.pkt_aux_core = 0; /* do not start*/ - xranInit.io_cfg.timing_core = startupConfiguration.io_core; - xranInit.io_cfg.dpdkIoVaMode = startupConfiguration.iova_mode; - } else { - printf("set O-RU\n"); - xranInit.io_cfg.id = 1; /* O-RU*/ - xranInit.io_cfg.core = startupConfiguration.io_core; - xranInit.io_cfg.system_core = startupConfiguration.system_core; - xranInit.io_cfg.pkt_proc_core = startupConfiguration.io_worker; /* do not start */ - xranInit.io_cfg.pkt_aux_core = 0; /* do not start */ - xranInit.io_cfg.timing_core = startupConfiguration.io_core; - xranInit.io_cfg.dpdkIoVaMode = startupConfiguration.iova_mode; - } - - xranInit.io_cfg.io_sleep = startupConfiguration.io_sleep; - xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED; - - app_init_set_eAxCId_conf(&xranInit.eAxCId_conf, &startupConfiguration); - - printf("arg_params.num_vfs %d\n", arg_params.num_vfs); - for(i = 0; i < arg_params.num_vfs/2; i++){ - xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i] = argv[5+2*i]; - printf("VF[%d] %s\n",XRAN_UP_VF+2*i, xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i]); - xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i+1] = argv[5+2*i+1]; - printf("VF[%d] %s\n",XRAN_UP_VF+2*i+1, xranInit.io_cfg.dpdk_dev[XRAN_UP_VF+2*i+1]); - } - - xranInit.io_cfg.num_vfs = arg_params.num_vfs; - xranInit.mtu = startupConfiguration.mtu; - xranInit.p_o_du_addr = (int8_t *)startupConfiguration.o_du_addr; - xranInit.p_o_ru_addr = (int8_t *)startupConfiguration.o_ru_addr; - - sprintf(prefix_name, "wls_%d",startupConfiguration.instance_id); - xranInit.filePrefix = prefix_name; - - xranInit.totalBfWeights = startupConfiguration.totalBfWeights; - - xranInit.Tadv_cp_dl = startupConfiguration.Tadv_cp_dl; - xranInit.T2a_min_cp_dl = startupConfiguration.T2a_min_cp_dl; - xranInit.T2a_max_cp_dl = startupConfiguration.T2a_max_cp_dl; - xranInit.T2a_min_cp_ul = startupConfiguration.T2a_min_cp_ul; - xranInit.T2a_max_cp_ul = startupConfiguration.T2a_max_cp_ul; - xranInit.T2a_min_up = startupConfiguration.T2a_min_up; - xranInit.T2a_max_up = startupConfiguration.T2a_max_up; - xranInit.Ta3_min = startupConfiguration.Ta3_min; - xranInit.Ta3_max = startupConfiguration.Ta3_max; - xranInit.T1a_min_cp_dl = startupConfiguration.T1a_min_cp_dl; - xranInit.T1a_max_cp_dl = startupConfiguration.T1a_max_cp_dl; - xranInit.T1a_min_cp_ul = startupConfiguration.T1a_min_cp_ul; - xranInit.T1a_max_cp_ul = startupConfiguration.T1a_max_cp_ul; - xranInit.T1a_min_up = startupConfiguration.T1a_min_up; - xranInit.T1a_max_up = startupConfiguration.T1a_max_up; - xranInit.Ta4_min = startupConfiguration.Ta4_min; - xranInit.Ta4_max = startupConfiguration.Ta4_max; - - xranInit.enableCP = startupConfiguration.enableCP; - xranInit.prachEnable = startupConfiguration.enablePrach; - xranInit.srsEnable = startupConfiguration.enableSrs; - xranInit.debugStop = startupConfiguration.debugStop; - xranInit.debugStopCount = startupConfiguration.debugStopCount; - xranInit.DynamicSectionEna = startupConfiguration.DynamicSectionEna; - xranInit.io_cfg.bbdev_mode = XRAN_BBDEV_NOT_USED; - xranInit.GPS_Alpha = startupConfiguration.GPS_Alpha; - xranInit.GPS_Beta = startupConfiguration.GPS_Beta; - - xranInit.cp_vlan_tag = startupConfiguration.cp_vlan_tag; - xranInit.up_vlan_tag = startupConfiguration.up_vlan_tag; - - printf("IQ files size is %d slots\n", startupConfiguration.numSlots); - - iq_playback_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * - app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA) - *4L); - - iq_playback_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * - app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA) - *4L); - - - /* 10 * [14*32*273*2*2] = 4892160 bytes */ - iq_bfw_buffer_size_dl = (startupConfiguration.numSlots * N_SYM_PER_SLOT * startupConfiguration.antElmTRx * - app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA) - *4L); - - /* 10 * [14*32*273*2*2] = 4892160 bytes */ - iq_bfw_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * - app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA) - *4L); - - /* 10 * [1*273*2*2] = 349440 bytes */ - iq_srs_buffer_size_ul = (startupConfiguration.numSlots * N_SYM_PER_SLOT * N_SC_PER_PRB * - app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA) - *4L); - - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - p_tx_play_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_dl); - tx_play_buffer_size[i] = (int32_t)iq_playback_buffer_size_dl; - - if (p_tx_play_buffer[i] == NULL) - exit(-1); - - tx_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ant_file[i], - "DL IFFT IN IQ Samples in binary format", - (uint8_t*) p_tx_play_buffer[i], - tx_play_buffer_size[i], - 1); - tx_play_buffer_position[i] = 0; - } - - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - - p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl); - tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl; - - if (p_tx_dl_bfw_buffer[i] == NULL) + if (p_iq->p_tx_dl_bfw_buffer[i] == NULL) exit(-1); - tx_dl_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.dl_bfw_file[i], + p_iq->tx_dl_bfw_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->dl_bfw_file[i], "DL BF weights IQ Samples in binary format", - (uint8_t*) p_tx_dl_bfw_buffer[i], - tx_dl_bfw_buffer_size[i], + (uint8_t*) p_iq->p_tx_dl_bfw_buffer[i], + p_iq->tx_dl_bfw_buffer_size[i], 1); - tx_dl_bfw_buffer_position[i] = 0; + p_iq->tx_dl_bfw_buffer_position[i] = 0; } } - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){ + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul); - tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul; + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + p_iq->p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(p_iq->iq_bfw_buffer_size_ul); + p_iq->tx_ul_bfw_buffer_size[i] = (int32_t)p_iq->iq_bfw_buffer_size_ul; - if (p_tx_ul_bfw_buffer[i] == NULL) + if (p_iq->p_tx_ul_bfw_buffer[i] == NULL) exit(-1); - tx_ul_bfw_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_bfw_file[i], + p_iq->tx_ul_bfw_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->ul_bfw_file[i], "UL BF weights IQ Samples in binary format", - (uint8_t*) p_tx_ul_bfw_buffer[i], - tx_ul_bfw_buffer_size[i], + (uint8_t*) p_iq->p_tx_ul_bfw_buffer[i], + p_iq->tx_ul_bfw_buffer_size[i], 1); - tx_ul_bfw_buffer_position[i] = 0; + p_iq->tx_ul_bfw_buffer_position[i] = 0; } } - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - p_tx_prach_play_buffer[i] = (int16_t*)malloc(PRACH_PLAYBACK_BUFFER_BYTES); - tx_prach_play_buffer_size[i] = (int32_t)PRACH_PLAYBACK_BUFFER_BYTES; + if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enablePrach) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + p_iq->p_tx_prach_play_buffer[i] = (int16_t*)malloc(PRACH_PLAYBACK_BUFFER_BYTES); + p_iq->tx_prach_play_buffer_size[i] = (int32_t)PRACH_PLAYBACK_BUFFER_BYTES; - if (p_tx_prach_play_buffer[i] == NULL) + if (p_iq->p_tx_prach_play_buffer[i] == NULL) exit(-1); - memset(p_tx_prach_play_buffer[i], 0, PRACH_PLAYBACK_BUFFER_BYTES); + memset(p_iq->p_tx_prach_play_buffer[i], 0, PRACH_PLAYBACK_BUFFER_BYTES); - tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.prach_file[i], + p_iq->tx_prach_play_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->prach_file[i], "PRACH IQ Samples in binary format", - (uint8_t*) p_tx_prach_play_buffer[i], - tx_prach_play_buffer_size[i], + (uint8_t*) p_iq->p_tx_prach_play_buffer[i], + p_iq->tx_prach_play_buffer_size[i], 1); - tx_prach_play_buffer_position[i] = 0; + p_iq->tx_prach_play_buffer_position[i] = 0; } } - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){ + if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enableSrs) { for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); i++) { - p_tx_srs_play_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul); - tx_srs_play_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul; + p_iq->p_tx_srs_play_buffer[i] = (int16_t*)malloc(p_iq->iq_srs_buffer_size_ul); + p_iq->tx_srs_play_buffer_size[i] = (int32_t)p_iq->iq_srs_buffer_size_ul; - if (p_tx_srs_play_buffer[i] == NULL) + if (p_iq->p_tx_srs_play_buffer[i] == NULL) exit(-1); - memset(p_tx_srs_play_buffer[i], 0, iq_srs_buffer_size_ul); - tx_prach_play_buffer_size[i] = sys_load_file_to_buff(startupConfiguration.ul_srs_file[i], + memset(p_iq->p_tx_srs_play_buffer[i], 0, p_iq->iq_srs_buffer_size_ul); + p_iq->tx_srs_play_buffer_size[i] = sys_load_file_to_buff(p_o_xu_cfg->ul_srs_file[i], "SRS IQ Samples in binary format", - (uint8_t*) p_tx_srs_play_buffer[i], - tx_srs_play_buffer_size[i], + (uint8_t*) p_iq->p_tx_srs_play_buffer[i], + p_iq->tx_srs_play_buffer_size[i], 1); - tx_srs_play_buffer_position[i] = 0; + p_iq->tx_srs_play_buffer_position[i] = 0; } } /* log of ul */ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { - p_rx_log_buffer[i] = (int16_t*)malloc(iq_playback_buffer_size_ul); - rx_log_buffer_size[i] = (int32_t)iq_playback_buffer_size_ul; + p_iq->p_rx_log_buffer[i] = (int16_t*)malloc(p_iq->iq_playback_buffer_size_ul); + p_iq->rx_log_buffer_size[i] = (int32_t)p_iq->iq_playback_buffer_size_ul; - if (p_rx_log_buffer[i] == NULL) + if (p_iq->p_rx_log_buffer[i] == NULL) exit(-1); - rx_log_buffer_position[i] = 0; + p_iq->rx_log_buffer_position[i] = 0; - memset(p_rx_log_buffer[i], 0, rx_log_buffer_size[i]); + memset(p_iq->p_rx_log_buffer[i], 0, p_iq->rx_log_buffer_size[i]); } /* log of prach */ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { - p_prach_log_buffer[i] = (int16_t*)malloc(startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES); - prach_log_buffer_size[i] = (int32_t)startupConfiguration.numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES; + p_iq->p_prach_log_buffer[i] = (int16_t*)malloc(p_o_xu_cfg->numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES); + p_iq->prach_log_buffer_size[i] = (int32_t)p_o_xu_cfg->numSlots*XRAN_NUM_OF_SYMBOL_PER_SLOT*PRACH_PLAYBACK_BUFFER_BYTES; - if (p_prach_log_buffer[i] == NULL) + if (p_iq->p_prach_log_buffer[i] == NULL) exit(-1); - memset(p_prach_log_buffer[i], 0, prach_log_buffer_size[i]); - prach_log_buffer_position[i] = 0; + memset(p_iq->p_prach_log_buffer[i], 0, p_iq->prach_log_buffer_size[i]); + p_iq->prach_log_buffer_position[i] = 0; } /* log of SRS */ - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){ + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) { for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); i++) { - p_srs_log_buffer[i] = (int16_t*)malloc(iq_srs_buffer_size_ul); - srs_log_buffer_size[i] = (int32_t)iq_srs_buffer_size_ul; + p_iq->p_srs_log_buffer[i] = (int16_t*)malloc(p_iq->iq_srs_buffer_size_ul); + p_iq->srs_log_buffer_size[i] = (int32_t)p_iq->iq_srs_buffer_size_ul; - if (p_srs_log_buffer[i] == NULL) + if (p_iq->p_srs_log_buffer[i] == NULL) exit(-1); - memset(p_srs_log_buffer[i], 0, iq_srs_buffer_size_ul); - srs_log_buffer_position[i] = 0; - } + memset(p_iq->p_srs_log_buffer[i], 0, p_iq->iq_srs_buffer_size_ul); + p_iq->srs_log_buffer_position[i] = 0; } - - if (stat("./logs", &st) == -1) { - mkdir("./logs", 0777); } - for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { - sprintf(filename, "./logs/%s-play_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename), "./logs/%s%d-play_ant%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file_txt(filename, "DL IFFT IN IQ Samples in human readable format", - (uint8_t*) p_tx_play_buffer[i], - tx_play_buffer_size[i], + (uint8_t*) p_iq->p_tx_play_buffer[i], + p_iq->tx_play_buffer_size[i], 1); - sprintf(filename, "./logs/%s-play_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename),"./logs/%s%d-play_ant%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file(filename, "DL IFFT IN IQ Samples in binary format", - (uint8_t*) p_tx_play_buffer[i], - tx_play_buffer_size[i]/sizeof(short), + (uint8_t*) p_iq->p_tx_play_buffer[i], + p_iq->tx_play_buffer_size[i]/sizeof(short), sizeof(short)); - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){ - sprintf(filename, "./logs/%s-dl_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { + snprintf(filename, sizeof(filename),"./logs/%s%d-dl_bfw_ue%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file_txt(filename, "DL Beamformig weights IQ Samples in human readable format", - (uint8_t*) p_tx_dl_bfw_buffer[i], - tx_dl_bfw_buffer_size[i], + (uint8_t*) p_iq->p_tx_dl_bfw_buffer[i], + p_iq->tx_dl_bfw_buffer_size[i], 1); - sprintf(filename, "./logs/%s-dl_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename),"./logs/%s%d-dl_bfw_ue%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"),p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file(filename, "DL Beamformig weightsIQ Samples in binary format", - (uint8_t*) p_tx_dl_bfw_buffer[i], - tx_dl_bfw_buffer_size[i]/sizeof(short), + (uint8_t*) p_iq->p_tx_dl_bfw_buffer[i], + p_iq->tx_dl_bfw_buffer_size[i]/sizeof(short), sizeof(short)); - sprintf(filename, "./logs/%s-ul_bfw_ue%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename), "./logs/%s%d-ul_bfw_ue%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file_txt(filename, "UL Beamformig weights IQ Samples in human readable format", - (uint8_t*) p_tx_ul_bfw_buffer[i], - tx_ul_bfw_buffer_size[i], + (uint8_t*) p_iq->p_tx_ul_bfw_buffer[i], + p_iq->tx_ul_bfw_buffer_size[i], 1); - sprintf(filename, "./logs/%s-ul_bfw_ue%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename),"./logs/%s%d-ul_bfw_ue%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file(filename, "UL Beamformig weightsIQ Samples in binary format", - (uint8_t*) p_tx_ul_bfw_buffer[i], - tx_ul_bfw_buffer_size[i]/sizeof(short), + (uint8_t*) p_iq->p_tx_ul_bfw_buffer[i], + p_iq->tx_ul_bfw_buffer_size[i]/sizeof(short), sizeof(short)); } - - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){ - sprintf(filename, "./logs/%s-play_prach_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file_txt(filename, - "PRACH IQ Samples in human readable format", - (uint8_t*) p_tx_prach_play_buffer[i], - tx_prach_play_buffer_size[i], - 1); - - sprintf(filename, "./logs/%s-play_prach_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file(filename, - "PRACH IQ Samples in binary format", - (uint8_t*) p_tx_prach_play_buffer[i], - tx_prach_play_buffer_size[i]/sizeof(short), - sizeof(short)); - } } - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs && startupConfiguration.xranCat == XRAN_CATEGORY_B){ + if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enableSrs && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); i++) { - - sprintf(filename, "./logs/%s-play_srs_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename, sizeof(filename), "./logs/%s%d-play_srs_ant%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file_txt(filename, "SRS IQ Samples in human readable format", - (uint8_t*) p_tx_srs_play_buffer[i], - tx_srs_play_buffer_size[i], + (uint8_t*)p_iq->p_tx_srs_play_buffer[i], + p_iq->tx_srs_play_buffer_size[i], 1); - sprintf(filename, "./logs/%s-play_srs_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); + snprintf(filename,sizeof(filename), "./logs/%s%d-play_srs_ant%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); sys_save_buf_to_file(filename, "SRS IQ Samples in binary format", - (uint8_t*) p_tx_srs_play_buffer[i], - tx_srs_play_buffer_size[i]/sizeof(short), + (uint8_t*) p_iq->p_tx_srs_play_buffer[i], + p_iq->tx_srs_play_buffer_size[i]/sizeof(short), sizeof(short)); } } - if (startupConfiguration.iqswap == 1){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + if (p_o_xu_cfg->iqswap == 1) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { printf("TX: Swap I and Q to match RU format: [%d]\n",i); { /* swap I and Q */ int32_t j; - signed short *ptr = (signed short *) p_tx_play_buffer[i]; + signed short *ptr = (signed short *) p_iq->p_tx_play_buffer[i]; signed short temp; - for (j = 0; j < (int32_t)(tx_play_buffer_size[i]/sizeof(short)) ; j = j + 2){ + for (j = 0; j < (int32_t)(p_iq->tx_play_buffer_size[i]/sizeof(short)) ; j = j + 2) { temp = ptr[j]; ptr[j] = ptr[j + 1]; ptr[j + 1] = temp; } } - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){ + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { printf("DL BFW: Swap I and Q to match RU format: [%d]\n",i); { /* swap I and Q */ int32_t j; - signed short *ptr = (signed short *) p_tx_dl_bfw_buffer[i]; + signed short *ptr = (signed short *) p_iq->p_tx_dl_bfw_buffer[i]; signed short temp; - for (j = 0; j < (int32_t)(tx_dl_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){ + for (j = 0; j < (int32_t)(p_iq->tx_dl_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2) { temp = ptr[j]; ptr[j] = ptr[j + 1]; ptr[j + 1] = temp; @@ -1979,10 +737,10 @@ int main(int argc, char *argv[]) { /* swap I and Q */ int32_t j; - signed short *ptr = (signed short *) p_tx_ul_bfw_buffer[i]; + signed short *ptr = (signed short *) p_iq->p_tx_ul_bfw_buffer[i]; signed short temp; - for (j = 0; j < (int32_t)(tx_ul_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2){ + for (j = 0; j < (int32_t)(p_iq->tx_ul_bfw_buffer_size[i]/sizeof(short)) ; j = j + 2) { temp = ptr[j]; ptr[j] = ptr[j + 1]; ptr[j + 1] = temp; @@ -1991,16 +749,16 @@ int main(int argc, char *argv[]) } } - if (startupConfiguration.appMode == APP_O_RU){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + if (p_o_xu_cfg->appMode == APP_O_RU) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { printf("PRACH: Swap I and Q to match RU format: [%d]\n",i); { /* swap I and Q */ int32_t j; - signed short *ptr = (signed short *) p_tx_prach_play_buffer[i]; + signed short *ptr = (signed short *) p_iq-> p_tx_prach_play_buffer[i]; signed short temp; - for (j = 0; j < (int32_t)(tx_prach_play_buffer_size[i]/sizeof(short)) ; j = j + 2){ + for (j = 0; j < (int32_t)(p_iq->tx_prach_play_buffer_size[i]/sizeof(short)) ; j = j + 2) { temp = ptr[j]; ptr[j] = ptr[j + 1]; ptr[j + 1] = temp; @@ -2009,18 +767,18 @@ int main(int argc, char *argv[]) } } - if (startupConfiguration.appMode == APP_O_RU){ + if (p_o_xu_cfg->appMode == APP_O_RU) { for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); i++) { printf("SRS: Swap I and Q to match RU format: [%d]\n",i); { /* swap I and Q */ int32_t j; - signed short *ptr = (signed short *) p_tx_srs_play_buffer[i]; + signed short *ptr = (signed short *) p_iq->p_tx_srs_play_buffer[i]; signed short temp; - for (j = 0; j < (int32_t)(tx_srs_play_buffer_size[i]/sizeof(short)) ; j = j + 2){ + for (j = 0; j < (int32_t)(p_iq->tx_srs_play_buffer_size[i]/sizeof(short)) ; j = j + 2) { temp = ptr[j]; ptr[j] = ptr[j + 1]; ptr[j + 1] = temp; @@ -2031,51 +789,51 @@ int main(int argc, char *argv[]) } #if 0 - for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { sprintf(filename, "./logs/swap_IQ_play_ant%d.txt", i); sys_save_buf_to_file_txt(filename, "DL IFFT IN IQ Samples in human readable format", - (uint8_t*) p_tx_play_buffer[i], - tx_play_buffer_size[i], + (uint8_t*) p_iq->p_tx_play_buffer[i], + p_iq->tx_play_buffer_size[i], 1); } #endif - if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + if (p_o_xu_cfg->nebyteorderswap == 1 && p_o_xu_cfg->compression == 0) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { printf("TX: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i); - for (j = 0; j < tx_play_buffer_size[i]/sizeof(short); j++){ - p_tx_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_play_buffer[i][j]); + for (j = 0; j < p_iq->tx_play_buffer_size[i]/sizeof(short); j++) { + p_iq->p_tx_play_buffer[i][j] = rte_cpu_to_be_16(p_iq->p_tx_play_buffer[i][j]); } - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.xranCat == XRAN_CATEGORY_B){ + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->xranCat == XRAN_CATEGORY_B) { printf("DL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i); - for (j = 0; j < tx_dl_bfw_buffer_size[i]/sizeof(short); j++){ - p_tx_dl_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_dl_bfw_buffer[i][j]); + for (j = 0; j < p_iq->tx_dl_bfw_buffer_size[i]/sizeof(short); j++) { + p_iq->p_tx_dl_bfw_buffer[i][j] = rte_cpu_to_be_16(p_iq->p_tx_dl_bfw_buffer[i][j]); } printf("UL BFW: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i); - for (j = 0; j < tx_ul_bfw_buffer_size[i]/sizeof(short); j++){ - p_tx_ul_bfw_buffer[i][j] = rte_cpu_to_be_16(p_tx_ul_bfw_buffer[i][j]); + for (j = 0; j < p_iq->tx_ul_bfw_buffer_size[i]/sizeof(short); j++) { + p_iq->p_tx_ul_bfw_buffer[i][j] = rte_cpu_to_be_16(p_iq->p_tx_ul_bfw_buffer[i][j]); } } } - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enablePrach){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enablePrach) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { printf("PRACH: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i); - for (j = 0; j < tx_prach_play_buffer_size[i]/sizeof(short); j++){ - p_tx_prach_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_prach_play_buffer[i][j]); + for (j = 0; j < p_iq->tx_prach_play_buffer_size[i]/sizeof(short); j++) { + p_iq->p_tx_prach_play_buffer[i][j] = rte_cpu_to_be_16(p_iq->p_tx_prach_play_buffer[i][j]); } } } - if (startupConfiguration.appMode == APP_O_RU && startupConfiguration.enableSrs){ + if (p_o_xu_cfg->appMode == APP_O_RU && p_o_xu_cfg->enableSrs) { for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); i++) { printf("SRS: Convert S16 I and S16 Q to network byte order for XRAN Ant: [%d]\n",i); - for (j = 0; j < tx_srs_play_buffer_size[i]/sizeof(short); j++){ - p_tx_srs_play_buffer[i][j] = rte_cpu_to_be_16(p_tx_srs_play_buffer[i][j]); + for (j = 0; j < p_iq->tx_srs_play_buffer_size[i]/sizeof(short); j++) { + p_iq->p_tx_srs_play_buffer[i][j] = rte_cpu_to_be_16(p_iq->p_tx_srs_play_buffer[i][j]); } } } @@ -2083,224 +841,488 @@ int main(int argc, char *argv[]) } #if 0 - for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { sprintf(filename, "./logs/swap_be_play_ant%d.txt", i); sys_save_buf_to_file_txt(filename, "DL IFFT IN IQ Samples in human readable format", - (uint8_t*) p_tx_play_buffer[i], - tx_play_buffer_size[i], + (uint8_t*) p_iq->p_tx_play_buffer[i], + p_iq->tx_play_buffer_size[i], 1); } #endif + } - memset(&xranConf, 0, sizeof(struct xran_fh_config)); - pXranConf = &xranConf; - - pXranConf->nDLRBs = app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nDLBandwidth, startupConfiguration.nDLAbsFrePointA); - pXranConf->nULRBs = app_xran_get_num_rbs(startupConfiguration.xranTech, startupConfiguration.mu_number, startupConfiguration.nULBandwidth, startupConfiguration.nULAbsFrePointA); - - if(startupConfiguration.DynamicSectionEna == 0){ - struct xran_prb_map* pRbMap; - - pRbMap = &startupConfiguration.PrbMapDl; - - pRbMap->dir = XRAN_DIR_DL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = 0; - pRbMap->ru_port_id = 0; - pRbMap->tti_id = 0; - pRbMap->start_sym_id = 0; - pRbMap->nPrbElm = 1; - pRbMap->prbMap[0].nStartSymb = 0; - pRbMap->prbMap[0].numSymb = 14; - pRbMap->prbMap[0].nRBStart = 0; - pRbMap->prbMap[0].nRBSize = pXranConf->nDLRBs; - pRbMap->prbMap[0].nBeamIndex = 0; - pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; - pRbMap->prbMap[0].iqWidth = 16; - - pRbMap = &startupConfiguration.PrbMapUl; - pRbMap->dir = XRAN_DIR_UL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = 0; - pRbMap->ru_port_id = 0; - pRbMap->tti_id = 0; - pRbMap->start_sym_id = 0; - pRbMap->nPrbElm = 1; - pRbMap->prbMap[0].nStartSymb = 0; - pRbMap->prbMap[0].numSymb = 14; - pRbMap->prbMap[0].nRBStart = 0; - pRbMap->prbMap[0].nRBSize = pXranConf->nULRBs; - pRbMap->prbMap[0].nBeamIndex = 0; - pRbMap->prbMap[0].compMethod = XRAN_COMPMETHOD_NONE; - pRbMap->prbMap[0].iqWidth = 16; + return ret; +} + +int32_t +app_dump_o_xu_buffers(UsecaseConfig* p_use_cfg, RuntimeConfig* p_o_xu_cfg) +{ + int32_t ret = 0; + int32_t i = 0; + int32_t j = 0; + char filename[256]; + struct o_xu_buffers* p_iq = NULL; + + if (p_o_xu_cfg->p_buff) { + p_iq = p_o_xu_cfg->p_buff; } else { - struct xran_prb_map* pRbMap; - pRbMap = &startupConfiguration.PrbMapDl; - - pRbMap->dir = XRAN_DIR_DL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = 0; - pRbMap->ru_port_id = 0; - pRbMap->tti_id = 0; - pRbMap->start_sym_id = 0; - - pRbMap = &startupConfiguration.PrbMapUl; - pRbMap->dir = XRAN_DIR_UL; - pRbMap->xran_port = 0; - pRbMap->band_id = 0; - pRbMap->cc_id = 0; - pRbMap->ru_port_id = 0; - pRbMap->tti_id = 0; - pRbMap->start_sym_id = 0; + printf("Error p_o_xu_cfg->p_buff\n"); + exit(-1); } - timer_set_tsc_freq_from_clock(); - xret = xran_init(argc, argv, &xranInit, argv[0], &xranHandle); - if(xret != XRAN_STATUS_SUCCESS){ - printf("xran_init failed %d\n", xret); - exit(-1); + if (p_o_xu_cfg->iqswap == 1) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + printf("RX: Swap I and Q to match CPU format: [%d]\n",i); + { + /* swap I and Q */ + int32_t j; + signed short *ptr = (signed short *) p_iq->p_rx_log_buffer[i]; + signed short temp; + + for (j = 0; j < (int32_t)(p_iq->rx_log_buffer_size[i]/sizeof(short)) ; j = j + 2) { + temp = ptr[j]; + ptr[j] = ptr[j + 1]; + ptr[j + 1] = temp; + } + } + } + + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) { + for (i = 0; + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); + i++) { + printf("SRS: Swap I and Q to match CPU format: [%d]\n",i); + { + /* swap I and Q */ + int32_t j; + signed short *ptr = (signed short *) p_iq->p_srs_log_buffer[i]; + signed short temp; + + for (j = 0; j < (int32_t)(p_iq->srs_log_buffer_size[i]/sizeof(short)) ; j = j + 2) { + temp = ptr[j]; + ptr[j] = ptr[j + 1]; + ptr[j + 1] = temp; + } + } + } + } } - if(xranHandle == NULL) - exit(1); + if (p_o_xu_cfg->nebyteorderswap == 1 && p_o_xu_cfg->compression == 0) { + + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + printf("RX: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); + for (j = 0; j < p_iq->rx_log_buffer_size[i]/sizeof(short); j++) { + p_iq->p_rx_log_buffer[i][j] = rte_be_to_cpu_16(p_iq->p_rx_log_buffer[i][j]); + } + } + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) { + for (i = 0; + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); + i++) { + printf("SRS: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); + for (j = 0; j < p_iq->srs_log_buffer_size[i]/sizeof(short); j++) { + p_iq->p_srs_log_buffer[i][j] = rte_be_to_cpu_16(p_iq->p_srs_log_buffer[i][j]); + } + } + } + } - pXranConf->sector_id = 0; - pXranConf->nCC = numCCPorts; - pXranConf->neAxc = num_eAxc; - pXranConf->neAxcUl = startupConfiguration.numUlAxc; - pXranConf->nAntElmTRx = startupConfiguration.antElmTRx; + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { - pXranConf->frame_conf.nFrameDuplexType = startupConfiguration.nFrameDuplexType; - pXranConf->frame_conf.nNumerology = startupConfiguration.mu_number; - pXranConf->frame_conf.nTddPeriod = startupConfiguration.nTddPeriod; + snprintf(filename, sizeof(filename), "./logs/%s%d-rx_log_ant%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); + sys_save_buf_to_file_txt(filename, + "UL FFT OUT IQ Samples in human readable format", + (uint8_t*) p_iq->p_rx_log_buffer[i], + p_iq->rx_log_buffer_size[i], + 1); - for (i = 0; i < startupConfiguration.nTddPeriod; i++){ - pXranConf->frame_conf.sSlotConfig[i] = startupConfiguration.sSlotConfig[i]; + snprintf(filename, sizeof(filename), "./logs/%s%d-rx_log_ant%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); + sys_save_buf_to_file(filename, + "UL FFT OUT IQ Samples in binary format", + (uint8_t*) p_iq->p_rx_log_buffer[i], + p_iq->rx_log_buffer_size[i]/sizeof(short), + sizeof(short)); } - pXranConf->prach_conf.nPrachSubcSpacing = startupConfiguration.mu_number; - pXranConf->prach_conf.nPrachFreqStart = 0; - pXranConf->prach_conf.nPrachFilterIdx = XRAN_FILTERINDEX_PRACH_ABC; - pXranConf->prach_conf.nPrachConfIdx = startupConfiguration.prachConfigIndex; - pXranConf->prach_conf.nPrachFreqOffset = -792; + if (p_o_xu_cfg->appMode == APP_O_DU && p_o_xu_cfg->enableSrs) { + for (i = 0; + i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->antElmTRx); + i++) { + snprintf(filename, sizeof(filename), "./logs/%s%d-srs_log_ant%d.txt",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); + sys_save_buf_to_file_txt(filename, + "SRS UL FFT OUT IQ Samples in human readable format", + (uint8_t*)p_iq-> p_srs_log_buffer[i], + p_iq->srs_log_buffer_size[i], + 1); - pXranConf->srs_conf.symbMask = startupConfiguration.srsSymMask; - pXranConf->srs_conf.eAxC_offset = 2 * startupConfiguration.numAxc; /* PUSCH, PRACH, SRS */ + snprintf(filename, sizeof(filename), "./logs/%s%d-srs_log_ant%d.bin",((p_o_xu_cfg->appMode == APP_O_DU) ? "o-du" : "o-ru"), p_o_xu_cfg->o_xu_id, i); + sys_save_buf_to_file(filename, + "SRS UL FFT OUT IQ Samples in binary format", + (uint8_t*) p_iq->p_srs_log_buffer[i], + p_iq->srs_log_buffer_size[i]/sizeof(short), + sizeof(short)); + } + } - pXranConf->ru_conf.xranTech = startupConfiguration.xranTech; - pXranConf->ru_conf.xranCompHdrType = startupConfiguration.CompHdrType; - pXranConf->ru_conf.xranCat = startupConfiguration.xranCat; - pXranConf->ru_conf.iqWidth = startupConfiguration.PrbMapDl.prbMap[0].iqWidth; + if (p_o_xu_cfg->enablePrach) { + if (p_o_xu_cfg->iqswap == 1) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + printf("PRACH: Swap I and Q to match CPU format: [%d]\n",i); + { + /* swap I and Q */ + int32_t j; + signed short *ptr = (signed short *) p_iq->p_prach_log_buffer[i]; + signed short temp; - if (startupConfiguration.compression == 0) - pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_NONE; + for (j = 0; j < (int32_t)(p_iq->prach_log_buffer_size[i]/sizeof(short)) ; j = j + 2) { + temp = ptr[j]; + ptr[j] = ptr[j + 1]; + ptr[j + 1] = temp; + } + } + } + } + + if (p_o_xu_cfg->nebyteorderswap == 1 && p_o_xu_cfg->compression == 0) { + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + printf("PRACH: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); + for (j = 0; j < p_iq->prach_log_buffer_size[i]/sizeof(short); j++) { + p_iq->p_prach_log_buffer[i][j] = rte_be_to_cpu_16(p_iq->p_prach_log_buffer[i][j]); + } + } + } + + for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(p_o_xu_cfg->numCC * p_o_xu_cfg->numAxc); i++) { + + if (p_o_xu_cfg->appMode == APP_O_DU) + snprintf(filename, sizeof(filename), "./logs/%s%d%s_ant%d.txt","o-du",p_o_xu_cfg->o_xu_id,"-prach_log", i); else - pXranConf->ru_conf.compMeth = XRAN_COMPMETHOD_BLKFLOAT; + snprintf(filename, sizeof(filename), "./logs/%s%d%s_ant%d.txt","o-ru",p_o_xu_cfg->o_xu_id,"-play_prach", i); + sys_save_buf_to_file_txt(filename, + "PRACH IQ Samples in human readable format", + (uint8_t*) p_iq->p_prach_log_buffer[i], + p_iq->prach_log_buffer_size[i], + 1); - pXranConf->ru_conf.fftSize = 0; - while (startupConfiguration.nULFftSize >>= 1) - ++pXranConf->ru_conf.fftSize; + if (p_o_xu_cfg->appMode == APP_O_DU) + snprintf(filename, sizeof(filename), "./logs/%s%d%s_ant%d.bin","o-du",p_o_xu_cfg->o_xu_id,"-prach_log", i); + else + snprintf(filename, sizeof(filename), "./logs/%s%d%s_ant%d.bin","o-ru",p_o_xu_cfg->o_xu_id,"-play_prach", i); + sys_save_buf_to_file(filename, + "PRACH IQ Samples in binary format", + (uint8_t*) p_iq->p_prach_log_buffer[i], + p_iq->prach_log_buffer_size[i]/sizeof(short), + sizeof(short)); + } + } + return ret; +} - pXranConf->ru_conf.byteOrder = (startupConfiguration.nebyteorderswap == 1) ? XRAN_NE_BE_BYTE_ORDER : XRAN_CPU_LE_BYTE_ORDER ; - pXranConf->ru_conf.iqOrder = (startupConfiguration.iqswap == 1) ? XRAN_Q_I_ORDER : XRAN_I_Q_ORDER; +int32_t +app_set_main_core(UsecaseConfig* p_usecase) +{ + struct sched_param sched_param; + cpu_set_t cpuset; + int32_t result = 0; + memset(&sched_param, 0, sizeof(struct sched_param)); + /* set main thread affinity mask to CPU2 */ + sched_param.sched_priority = 99; + CPU_ZERO(&cpuset); + + printf("This system has %d processors configured and %d processors available.\n", get_nprocs_conf(), get_nprocs()); + + if (p_usecase->main_core < get_nprocs_conf()) + CPU_SET(p_usecase->main_core, &cpuset); + else + return -1; - printf("FFT Order %d\n", pXranConf->ru_conf.fftSize); + if (result = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset)) + { + printf("pthread_setaffinity_np failed: coreId = 2, result = %d\n",result); + } + printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, sched_getcpu(), getpid()); +#if 0 + if ((result = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param))) + { + printf("priority is not changed: coreId = 2, result = %d\n",result); + } +#endif + return result; +} - nCenterFreq = startupConfiguration.nDLAbsFrePointA + (((pXranConf->nDLRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number)); - pXranConf->nDLCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq); - printf("DL center freq %d DL NR-ARFCN %d\n", nCenterFreq, pXranConf->nDLCenterFreqARFCN); +int32_t +app_alloc_all_cfgs(void) +{ + void * ptr = NULL; + RuntimeConfig* p_rt_cfg = NULL; + int32_t i = 0; - nCenterFreq = startupConfiguration.nULAbsFrePointA + (((pXranConf->nULRBs * N_SC_PER_PRB) / 2) * app_xran_get_scs(startupConfiguration.mu_number)); - pXranConf->nULCenterFreqARFCN = app_xran_cal_nrarfcn(nCenterFreq); - printf("UL center freq %d UL NR-ARFCN %d\n", nCenterFreq, pXranConf->nULCenterFreqARFCN); + ptr = _mm_malloc(sizeof(UsecaseConfig), 256); + if (ptr == NULL) { + rte_panic("_mm_malloc: Can't allocate %lu bytes\n", sizeof(UsecaseConfig)); + } - pXranConf->bbdev_dec = NULL; - pXranConf->bbdev_enc = NULL; + p_usecaseConfiguration = (UsecaseConfig*)ptr; - pXranConf->log_level = 1; + ptr = _mm_malloc(sizeof(RuntimeConfig)*XRAN_PORTS_NUM, 256); + if (ptr == NULL) { + rte_panic("_mm_malloc: Can't allocate %lu bytes\n", sizeof(RuntimeConfig)*XRAN_PORTS_NUM); + } + p_rt_cfg = (RuntimeConfig*)ptr; - if(startupConfiguration.maxFrameId) - pXranConf->ru_conf.xran_max_frame = startupConfiguration.maxFrameId; + for (i = 0; i < XRAN_PORTS_NUM; i++) { + p_startupConfiguration[i] = p_rt_cfg++; + } - if(init_xran() != 0) + return 0; +} + +int main(int argc, char *argv[]) +{ + int i; + int j, len; + int32_t o_xu_id = 0; + int lcore_id = 0; + char filename[256]; + int32_t xret = 0; + struct stat st = {0}; + uint32_t filenameLength = strlen(argv[1]); + enum xran_if_state xran_curr_if_state = XRAN_INIT; + struct sample_app_params arg_params; + + uint64_t nTotalTime; + uint64_t nUsedTime; + uint32_t nCoresUsed; + uint32_t nCoreUsedNum[64]; + float nUsedPercent; + + app_version_print(); + app_timer_set_tsc_freq_from_clock(); + + if (xran_is_synchronized() != 0) + printf("Machine is not synchronized using PTP!\n"); + else + printf("Machine is synchronized using PTP!\n"); + + if (filenameLength >= 256) { + printf("Config file name input is too long, exiting!\n"); exit(-1); + } - xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI); - xran_reg_physide_cb(xranHandle, physide_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX); - xran_reg_physide_cb(xranHandle, physide_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX); + if ((xret = app_alloc_all_cfgs()) < 0) { + printf("app_alloc_all_cfgs failed %d\n", xret); + exit(-1); + } - init_xran_iq_content(); + if ((xret = app_parse_cmdline_args(argc, argv, &arg_params)) < 0) { + printf("app_parse_args failed %d\n", xret); + exit(-1); + } - xret = xran_open(xranHandle, pXranConf); + if ((xret = app_parse_all_cfgs(&arg_params, p_usecaseConfiguration, p_startupConfiguration[0])) < 0) { + printf("app_parse_all_cfgs failed %d\n", xret); + exit(-1); + } + if ((xret = app_set_main_core(p_usecaseConfiguration)) < 0) { + printf("app_set_main_core failed %d\n", xret); + exit(-1); + } + + app_io_xran_if_alloc(); + + /* one init for all O-XU */ + app_io_xran_fh_init_init(p_usecaseConfiguration, p_startupConfiguration[0], &app_io_xran_fh_init); + + xret = xran_init(argc, argv, &app_io_xran_fh_init, argv[0], &app_io_xran_handle); + if (xret != XRAN_STATUS_SUCCESS) { + printf("xran_init failed %d\n", xret); + exit(-1); + } + + if (app_io_xran_handle == NULL) + exit(1); + + if (stat("./logs", &st) == -1) { + mkdir("./logs", 0777); + } + + /** process all the O-RU|O-DU for use case */ + for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) { + RuntimeConfig* p_o_xu_cfg = p_startupConfiguration[o_xu_id]; + if (o_xu_id == 0) + app_io_xran_buffers_max_sz_set(p_o_xu_cfg); + + if (p_o_xu_cfg->ant_file[0] == NULL) { + printf("it looks like test vector for antennas were not provided\n"); + exit(-1); + } + if (p_o_xu_cfg->numCC > XRAN_MAX_SECTOR_NR) { + printf("Number of cells %d exceeds max number supported %d!\n", p_o_xu_cfg->numCC, XRAN_MAX_SECTOR_NR); + p_o_xu_cfg->numCC = XRAN_MAX_SECTOR_NR; + + } + if (p_o_xu_cfg->antElmTRx > XRAN_MAX_ANT_ARRAY_ELM_NR) { + printf("Number of Antenna elements %d exceeds max number supported %d!\n", p_o_xu_cfg->antElmTRx, XRAN_MAX_ANT_ARRAY_ELM_NR); + p_o_xu_cfg->antElmTRx = XRAN_MAX_ANT_ARRAY_ELM_NR; + } + + printf("Numm CC %d numAxc %d numUlAxc %d\n", p_o_xu_cfg->numCC, p_o_xu_cfg->numAxc, p_o_xu_cfg->numUlAxc); + + app_setup_o_xu_buffers(p_usecaseConfiguration, p_o_xu_cfg, &app_io_xran_fh_init); + + app_io_xran_fh_config_init(p_usecaseConfiguration, p_o_xu_cfg, &app_io_xran_fh_init, &app_io_xran_fh_config[o_xu_id]); + + xret = xran_open(app_io_xran_handle, &app_io_xran_fh_config[o_xu_id]); if(xret != XRAN_STATUS_SUCCESS){ printf("xran_open failed %d\n", xret); exit(-1); } - sprintf(filename, "mlog-%s", startupConfiguration.appMode == 0 ? "o-du" : "o-ru"); + if (app_io_xran_interface(o_xu_id, p_startupConfiguration[o_xu_id], p_usecaseConfiguration) != 0) + exit(-1); + + app_io_xran_iq_content_init(o_xu_id, p_startupConfiguration[o_xu_id]); + + if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_dl_tti_call_back, NULL, 10, XRAN_CB_TTI)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_physide_cb failed %d\n", xret); + exit(-1); + } + if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_ul_half_slot_call_back, NULL, 10, XRAN_CB_HALF_SLOT_RX)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_physide_cb failed %d\n", xret); + exit(-1); + } + if ((xret = xran_reg_physide_cb(app_io_xran_handle, app_io_xran_ul_full_slot_call_back, NULL, 10, XRAN_CB_FULL_SLOT_RX)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_physide_cb failed %d\n", xret); + exit(-1); + } +#ifdef TEST_SYM_CBS + if ((xret = xran_reg_sym_cb(app_io_xran_handle, app_io_xran_ul_custom_sym_call_back, + (void*)&cb_sym_ctx[0].cb_param, + &cb_sym_ctx[0].sense_of_time, + 3, XRAN_CB_SYM_RX_WIN_BEGIN)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_sym_cb failed %d\n", xret); + exit(-1); + } + + if ((xret = xran_reg_sym_cb(app_io_xran_handle, app_io_xran_ul_custom_sym_call_back, + (void*)&cb_sym_ctx[1].cb_param, + &cb_sym_ctx[1].sense_of_time, + 3, XRAN_CB_SYM_RX_WIN_END)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_sym_cb failed %d\n", xret); + exit(-1); + } + + if ((xret = xran_reg_sym_cb(app_io_xran_handle, app_io_xran_ul_custom_sym_call_back, + (void*)&cb_sym_ctx[2].cb_param, + &cb_sym_ctx[2].sense_of_time, + 3, XRAN_CB_SYM_TX_WIN_BEGIN)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_sym_cb failed %d\n", xret); + exit(-1); + } + + if ((xret = xran_reg_sym_cb(app_io_xran_handle, app_io_xran_ul_custom_sym_call_back, + (void*)&cb_sym_ctx[3].cb_param, + &cb_sym_ctx[3].sense_of_time, + 3, XRAN_CB_SYM_TX_WIN_END)) != XRAN_STATUS_SUCCESS) { + printf("xran_reg_sym_cb failed %d\n", xret); + exit(-1); + } +#endif + } + + snprintf(filename, sizeof(filename),"mlog-%s", p_usecaseConfiguration->appMode == 0 ? "o-du" : "o-ru"); /* MLogOpen(0, 32, 0, 0xFFFFFFFF, filename);*/ - MLogOpen(256, 3, 20000, 0, filename); + MLogOpen(128, 7, 20000, 0, filename); MLogSetMask(0); puts("----------------------------------------"); printf("MLog Info: virt=0x%016lx size=%d\n", MLogGetFileLocation(), MLogGetFileSize()); puts("----------------------------------------"); - uint64_t nActiveCoreMask[MAX_BBU_POOL_CORE_MASK] = {0}; - nActiveCoreMask[0] = (1 << xranInit.io_cfg.timing_core | xranInit.io_cfg.pkt_proc_core); + uint32_t totalCC = 0; + nActiveCoreMask[0] = ((1 << app_io_xran_fh_init.io_cfg.timing_core) | app_io_xran_fh_init.io_cfg.pkt_proc_core); + nActiveCoreMask[1] = app_io_xran_fh_init.io_cfg.pkt_proc_core_64_127; - MLogAddTestCase(nActiveCoreMask, startupConfiguration.numCC); + for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) { + RuntimeConfig* p_o_xu_cfg = p_startupConfiguration[o_xu_id]; + totalCC += p_o_xu_cfg->numCC; + } + MLogAddTestCase(nActiveCoreMask, totalCC); fcntl(0, F_SETFL, fcntl(0, F_GETFL) | O_NONBLOCK); state = APP_RUNNING; printf("Start XRAN traffic\n"); - xran_start(xranHandle); - sleep(3); - print_menu(); + xran_start(app_io_xran_handle); + app_print_menu(); + + struct xran_common_counters x_counters[XRAN_PORTS_NUM]; + int is_mlog_on = 0; for (;;) { - struct xran_common_counters x_counters; char input[10]; sleep(1); xran_curr_if_state = xran_get_if_state(); - if(xran_get_common_counters(xranHandle, &x_counters) == XRAN_STATUS_SUCCESS) { - xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoreUsed, 1); + if (xran_get_common_counters(app_io_xran_handle, &x_counters[0]) == XRAN_STATUS_SUCCESS) { + for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) { + if (o_xu_id == 0) { + xran_get_time_stats(&nTotalTime, &nUsedTime, &nCoresUsed, nCoreUsedNum, 1); + nUsedPercent = 0.0; + if (nTotalTime) { nUsedPercent = ((float)nUsedTime * 100.0) / (float)nTotalTime; + } + mlog_times.core_total_time += nTotalTime; + mlog_times.core_used_time += nUsedTime; - printf("[%s][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld] IO Util: %5.2f %%\n", - ((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), - x_counters.rx_counter, - x_counters.rx_counter-old_rx_counter, - x_counters.rx_bytes_per_sec*8/1000L, - x_counters.tx_counter, - x_counters.tx_counter-old_tx_counter, - x_counters.tx_bytes_per_sec*8/1000L, - x_counters.Rx_on_time, - x_counters.Rx_early, - x_counters.Rx_late, - x_counters.Rx_corrupt, - x_counters.Rx_pkt_dupl, - x_counters.Total_msgs_rcvd, - nUsedPercent); - - if(x_counters.rx_counter > old_rx_counter) - old_rx_counter = x_counters.rx_counter; - if(x_counters.tx_counter > old_tx_counter) - old_tx_counter = x_counters.tx_counter; - - if(x_counters.rx_counter > 0 && x_counters.tx_counter > 0) +#if 0 + printf("[nCoresUsed: %d] [MainCore: %d - Util: %5.2f %%]", nCoresUsed, nCoreUsedNum[0], nUsedPercent); + if (nCoresUsed > 1) { + printf("[Additional Cores: "); + for (int nCore = 1; nCore < nCoresUsed; nCore++) { + printf("%d ", nCoreUsedNum[nCore]); + } + printf("]"); + } + printf("\n"); +#endif + } + printf("[%s%d][rx %7ld pps %7ld kbps %7ld][tx %7ld pps %7ld kbps %7ld] [on_time %ld early %ld late %ld corrupt %ld pkt_dupl %ld Total %ld]\n", + ((p_usecaseConfiguration->appMode == APP_O_DU) ? "o-du" : "o-ru"), + o_xu_id, + x_counters[o_xu_id].rx_counter, + x_counters[o_xu_id].rx_counter-old_rx_counter[o_xu_id], + x_counters[o_xu_id].rx_bytes_per_sec*8/1000L, + x_counters[o_xu_id].tx_counter, + x_counters[o_xu_id].tx_counter-old_tx_counter[o_xu_id], + x_counters[o_xu_id].tx_bytes_per_sec*8/1000L, + x_counters[o_xu_id].Rx_on_time, + x_counters[o_xu_id].Rx_early, + x_counters[o_xu_id].Rx_late, + x_counters[o_xu_id].Rx_corrupt, + x_counters[o_xu_id].Rx_pkt_dupl, + x_counters[o_xu_id].Total_msgs_rcvd); + + if (x_counters[o_xu_id].rx_counter > old_rx_counter[o_xu_id]) + old_rx_counter[o_xu_id] = x_counters[o_xu_id].rx_counter; + if (x_counters[o_xu_id].tx_counter > old_tx_counter[o_xu_id]) + old_tx_counter[o_xu_id] = x_counters[o_xu_id].tx_counter; + + if(o_xu_id == 0){ + if(is_mlog_on == 0 && x_counters[o_xu_id].rx_counter > 0 && x_counters[o_xu_id].tx_counter > 0) { + xran_set_debug_stop(p_startupConfiguration[0]->debugStop, p_startupConfiguration[0]->debugStopCount); MLogSetMask(0xFFFFFFFF); + is_mlog_on = 1; + } + } + } } else { printf("error xran_get_common_counters\n"); } @@ -2315,13 +1337,13 @@ int main(int argc, char *argv[]) const int sel_opt = atoi(input); switch (sel_opt) { case 1: - xran_start(xranHandle); + xran_start(app_io_xran_handle); printf("Start XRAN traffic\n"); break; case 2: break; case 3: - xran_stop(xranHandle); + xran_stop(app_io_xran_handle); printf("Stop XRAN traffic\n"); state = APP_STOPPED; break; @@ -2333,158 +1355,49 @@ int main(int argc, char *argv[]) break; } - get_xran_iq_content(); - - puts("Closing l1 app... Ending all threads..."); - xran_close(xranHandle); - MLogPrint(NULL); - - stop_xran(); - puts("Dump IQs..."); - - if (startupConfiguration.iqswap == 1){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - printf("RX: Swap I and Q to match CPU format: [%d]\n",i); + /** process all the O-RU|O-DU for use case */ + for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) { + app_io_xran_iq_content_get(o_xu_id, p_startupConfiguration[o_xu_id]); + /* Check for owd results */ + if (p_usecaseConfiguration->owdmEnable) { - /* swap I and Q */ - int32_t j; - signed short *ptr = (signed short *) p_rx_log_buffer[i]; - signed short temp; - for (j = 0; j < (int32_t)(rx_log_buffer_size[i]/sizeof(short)) ; j = j + 2){ - temp = ptr[j]; - ptr[j] = ptr[j + 1]; - ptr[j + 1] = temp; - } - } + FILE *file= NULL; + uint64_t avgDelay =0; + snprintf(filename, sizeof(filename), "./logs/%s%d-owd_results.txt", ((p_startupConfiguration[o_xu_id]->appMode == APP_O_DU)?"o-du":"o-ru"),o_xu_id); + file = fopen(filename, "w"); + if (file == NULL) { + printf("can't open file %s\n",filename); + exit (-1); } - - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){ - for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); - i++) { - printf("SRS: Swap I and Q to match CPU format: [%d]\n",i); + if (xran_get_delay_measurements_results (app_io_xran_handle, (uint16_t) p_startupConfiguration[o_xu_id]->o_xu_id, p_usecaseConfiguration->appMode, &avgDelay)) { - /* swap I and Q */ - int32_t j; - signed short *ptr = (signed short *) p_srs_log_buffer[i]; - signed short temp; - - for (j = 0; j < (int32_t)(srs_log_buffer_size[i]/sizeof(short)) ; j = j + 2){ - temp = ptr[j]; - ptr[j] = ptr[j + 1]; - ptr[j + 1] = temp; - } - } - } + fprintf(file,"OWD Measurements failed for port %d and appMode %d \n", p_startupConfiguration[o_xu_id]->o_xu_id,p_usecaseConfiguration->appMode); } - } - - if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0) { - - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - printf("RX: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); - for (j = 0; j < rx_log_buffer_size[i]/sizeof(short); j++){ - p_rx_log_buffer[i][j] = rte_be_to_cpu_16(p_rx_log_buffer[i][j]); - } - } - - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){ - for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); - i++) { - printf("SRS: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); - for (j = 0; j < srs_log_buffer_size[i]/sizeof(short); j++){ - p_srs_log_buffer[i][j] = rte_be_to_cpu_16(p_srs_log_buffer[i][j]); - } - } - } - } - - for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - - sprintf(filename, "./logs/%s-rx_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file_txt(filename, - "UL FFT OUT IQ Samples in human readable format", - (uint8_t*) p_rx_log_buffer[i], - rx_log_buffer_size[i], - 1); - - sprintf(filename, "./logs/%s-rx_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file(filename, - "UL FFT OUT IQ Samples in binary format", - (uint8_t*) p_rx_log_buffer[i], - rx_log_buffer_size[i]/sizeof(short), - sizeof(short)); - } - - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enableSrs){ - for(i = 0; - i < MAX_ANT_CARRIER_SUPPORTED_CAT_B && i < (uint32_t)(numCCPorts * startupConfiguration.antElmTRx); - i++) { - sprintf(filename, "./logs/%s-srs_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file_txt(filename, - "SRS UL FFT OUT IQ Samples in human readable format", - (uint8_t*) p_srs_log_buffer[i], - srs_log_buffer_size[i], - 1); - - sprintf(filename, "./logs/%s-srs_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file(filename, - "SRS UL FFT OUT IQ Samples in binary format", - (uint8_t*) p_srs_log_buffer[i], - srs_log_buffer_size[i]/sizeof(short), - sizeof(short)); - } - } - - if (startupConfiguration.appMode == APP_O_DU && startupConfiguration.enablePrach){ - if (startupConfiguration.iqswap == 1){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - printf("PRACH: Swap I and Q to match CPU format: [%d]\n",i); + else { - /* swap I and Q */ - int32_t j; - signed short *ptr = (signed short *) p_prach_log_buffer[i]; - signed short temp; - - for (j = 0; j < (int32_t)(prach_log_buffer_size[i]/sizeof(short)) ; j = j + 2){ - temp = ptr[j]; - ptr[j] = ptr[j + 1]; - ptr[j + 1] = temp; - } - } - } - } - - - if (startupConfiguration.nebyteorderswap == 1 && startupConfiguration.compression == 0){ - for(i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - printf("PRACH: Convert S16 I and S16 Q to cpu byte order from XRAN Ant: [%d]\n",i); - for (j = 0; j < prach_log_buffer_size[i]/sizeof(short); j++){ - p_prach_log_buffer[i][j] = rte_be_to_cpu_16(p_prach_log_buffer[i][j]); + fprintf(file,"OWD Measurements passed for port %d and appMode %d with AverageDelay %lu [ns]\n", p_startupConfiguration[o_xu_id]->o_xu_id,p_usecaseConfiguration->appMode, avgDelay); } + fflush(file); + fclose(file); } } - for (i = 0; i < MAX_ANT_CARRIER_SUPPORTED && i < (uint32_t)(numCCPorts * num_eAxc); i++) { - - sprintf(filename, "./logs/%s-prach_log_ant%d.txt",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file_txt(filename, - "PRACH FFT OUT IQ Samples in human readable format", - (uint8_t*) p_prach_log_buffer[i], - prach_log_buffer_size[i], - 1); + puts("Closing l1 app... Ending all threads..."); - sprintf(filename, "./logs/%s-prach_log_ant%d.bin",((startupConfiguration.appMode == APP_O_DU) ? "o-du" : "o-ru"), i); - sys_save_buf_to_file(filename, - "PRACH FFT OUT IQ Samples in binary format", - (uint8_t*) p_prach_log_buffer[i], - prach_log_buffer_size[i]/sizeof(short), - sizeof(short)); + xran_close(app_io_xran_handle); + if(is_mlog_on) { + app_profile_xran_print_mlog_stats(arg_params.usecase_file); + rte_pause(); } + app_io_xran_if_stop(); + + puts("Dump IQs..."); + for (o_xu_id = 0; o_xu_id < p_usecaseConfiguration->oXuNum; o_xu_id++) { + app_dump_o_xu_buffers(p_usecaseConfiguration, p_startupConfiguration[o_xu_id]); } + app_io_xran_if_free(); return 0; } diff --git a/fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_du.dat similarity index 61% rename from fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_du.dat index 38544e5..a2cc38f 100644 --- a/fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=1024 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,56 +55,56 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_10mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_10mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_10mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_10mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_10mhz/ant_0.bin #CC1 -antC5=./usecase/mu0_10mhz/ant_1.bin #CC1 -antC6=./usecase/mu0_10mhz/ant_2.bin #CC1 -antC7=./usecase/mu0_10mhz/ant_3.bin #CC1 -antC8=./usecase/mu0_10mhz/ant_0.bin #CC2 -antC9=./usecase/mu0_10mhz/ant_1.bin #CC2 -antC10=./usecase/mu0_10mhz/ant_2.bin #CC2 -antC11=./usecase/mu0_10mhz/ant_3.bin #CC2 -antC12=./usecase/mu0_10mhz/ant_0.bin #CC3 -antC13=./usecase/mu0_10mhz/ant_1.bin #CC3 -antC14=./usecase/mu0_10mhz/ant_2.bin #CC3 -antC15=./usecase/mu0_10mhz/ant_3.bin #CC3 -antC16=./usecase/mu0_10mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_10mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_10mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_10mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_10mhz/ant_0.bin #CC5 -antC21=./usecase/mu0_10mhz/ant_1.bin #CC5 -antC22=./usecase/mu0_10mhz/ant_2.bin #CC5 -antC23=./usecase/mu0_10mhz/ant_3.bin #CC5 -antC24=./usecase/mu0_10mhz/ant_0.bin #CC6 -antC25=./usecase/mu0_10mhz/ant_1.bin #CC6 -antC26=./usecase/mu0_10mhz/ant_2.bin #CC6 -antC27=./usecase/mu0_10mhz/ant_3.bin #CC6 -antC28=./usecase/mu0_10mhz/ant_0.bin #CC7 -antC29=./usecase/mu0_10mhz/ant_1.bin #CC7 -antC30=./usecase/mu0_10mhz/ant_2.bin #CC7 -antC31=./usecase/mu0_10mhz/ant_3.bin #CC7 -antC32=./usecase/mu0_10mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_10mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_10mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_10mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_10mhz/ant_0.bin #CC9 -antC37=./usecase/mu0_10mhz/ant_1.bin #CC9 -antC38=./usecase/mu0_10mhz/ant_2.bin #CC9 -antC39=./usecase/mu0_10mhz/ant_3.bin #CC9 -antC40=./usecase/mu0_10mhz/ant_0.bin #CC10 -antC41=./usecase/mu0_10mhz/ant_1.bin #CC10 -antC42=./usecase/mu0_10mhz/ant_2.bin #CC10 -antC43=./usecase/mu0_10mhz/ant_3.bin #CC10 -antC44=./usecase/mu0_10mhz/ant_0.bin #CC11 -antC45=./usecase/mu0_10mhz/ant_1.bin #CC11 -antC46=./usecase/mu0_10mhz/ant_2.bin #CC11 -antC47=./usecase/mu0_10mhz/ant_3.bin #CC11 +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC1 +antC5=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC1 +antC6=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC1 +antC7=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC1 +antC8=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC2 +antC9=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC2 +antC10=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC2 +antC11=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC2 +antC12=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC3 +antC13=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC3 +antC14=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC3 +antC15=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC3 +antC16=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC5 +antC21=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC5 +antC22=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC5 +antC23=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC5 +antC24=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC6 +antC25=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC6 +antC26=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC6 +antC27=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC6 +antC28=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC7 +antC29=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC7 +antC30=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC7 +antC31=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC7 +antC32=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC9 +antC37=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC9 +antC38=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC9 +antC39=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC9 +antC40=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC10 +antC41=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC10 +antC42=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC10 +antC43=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC10 +antC44=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC11 +antC45=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC11 +antC46=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC11 +antC47=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC11 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index @@ -129,16 +129,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_ru.dat new file mode 100644 index 0000000..4d16009 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/config_file_o_ru.dat @@ -0,0 +1,217 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC1 +antC5=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC1 +antC6=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC1 +antC7=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC1 +antC8=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC2 +antC9=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC2 +antC10=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC2 +antC11=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC2 +antC12=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC3 +antC13=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC3 +antC14=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC3 +antC15=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC3 +antC16=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC5 +antC21=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC5 +antC22=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC5 +antC23=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC5 +antC24=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC6 +antC25=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC6 +antC26=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC6 +antC27=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC6 +antC28=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC7 +antC29=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC7 +antC30=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC7 +antC31=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC7 +antC32=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC9 +antC37=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC9 +antC38=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC9 +antC39=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC9 +antC40=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC10 +antC41=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC10 +antC42=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC10 +antC43=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC10 +antC44=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC11 +antC45=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC11 +antC46=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC11 +antC47=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC4=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC5=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC6=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC7=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC8=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC9=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC10=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC11=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC12=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC13=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC14=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC15=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC16=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC17=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC18=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC19=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC20=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC21=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC22=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC23=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC24=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC25=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC26=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC27=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC28=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC29=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC30=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC31=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC32=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC33=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC34=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC35=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC36=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC37=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC38=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC39=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC40=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC41=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC42=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC43=./usecase/cat_a/mu0_10mhz/ant_3.bin +antPrachC44=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC45=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC46=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC47=./usecase/cat_a/mu0_10mhz/ant_3.bin + + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/12/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_du.dat similarity index 61% rename from fhi_lib/app/usecase/mu0_10mhz/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_du.dat index 29a784d..732317a 100644 --- a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=1024 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,56 +55,56 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_10mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_10mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_10mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_10mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_10mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_10mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_10mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_10mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_10mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_10mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_10mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_10mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_10mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_10mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_10mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_10mhz/ant_15.bin #CC3 -antC16=./usecase/mu0_10mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_10mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_10mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_10mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_10mhz/ant_4.bin #CC5 -antC21=./usecase/mu0_10mhz/ant_5.bin #CC5 -antC22=./usecase/mu0_10mhz/ant_6.bin #CC5 -antC23=./usecase/mu0_10mhz/ant_7.bin #CC5 -antC24=./usecase/mu0_10mhz/ant_8.bin #CC6 -antC25=./usecase/mu0_10mhz/ant_9.bin #CC6 -antC26=./usecase/mu0_10mhz/ant_10.bin #CC6 -antC27=./usecase/mu0_10mhz/ant_11.bin #CC6 -antC28=./usecase/mu0_10mhz/ant_12.bin #CC7 -antC29=./usecase/mu0_10mhz/ant_13.bin #CC7 -antC30=./usecase/mu0_10mhz/ant_14.bin #CC7 -antC31=./usecase/mu0_10mhz/ant_15.bin #CC7 -antC32=./usecase/mu0_10mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_10mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_10mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_10mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_10mhz/ant_4.bin #CC9 -antC37=./usecase/mu0_10mhz/ant_5.bin #CC9 -antC38=./usecase/mu0_10mhz/ant_6.bin #CC9 -antC39=./usecase/mu0_10mhz/ant_7.bin #CC9 -antC40=./usecase/mu0_10mhz/ant_8.bin #CC10 -antC41=./usecase/mu0_10mhz/ant_9.bin #CC10 -antC42=./usecase/mu0_10mhz/ant_10.bin #CC10 -antC43=./usecase/mu0_10mhz/ant_11.bin #CC10 -antC44=./usecase/mu0_10mhz/ant_12.bin #CC11 -antC45=./usecase/mu0_10mhz/ant_13.bin #CC11 -antC46=./usecase/mu0_10mhz/ant_14.bin #CC11 -antC47=./usecase/mu0_10mhz/ant_15.bin #CC11 +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC3 +antC16=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC5 +antC21=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC5 +antC22=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC5 +antC23=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC5 +antC24=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC6 +antC25=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC6 +antC26=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC6 +antC27=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC6 +antC28=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC7 +antC29=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC7 +antC30=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC7 +antC31=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC7 +antC32=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC9 +antC37=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC9 +antC38=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC9 +antC39=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC9 +antC40=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC10 +antC41=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC10 +antC42=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC10 +antC43=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC10 +antC44=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC11 +antC45=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC11 +antC46=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC11 +antC47=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC11 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index @@ -129,16 +129,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat similarity index 59% rename from fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat index a972a17..051ba45 100644 --- a/fhi_lib/app/usecase/mu0_10mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/config_file_o_ru.dat @@ -37,7 +37,7 @@ nULFftSize=1024 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,64 +55,64 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_10mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_10mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_10mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_10mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_10mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_10mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_10mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_10mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_10mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_10mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_10mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_10mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_10mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_10mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_10mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_10mhz/ant_15.bin #CC3 -antC16=./usecase/mu0_10mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_10mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_10mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_10mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_10mhz/ant_4.bin #CC5 -antC21=./usecase/mu0_10mhz/ant_5.bin #CC5 -antC22=./usecase/mu0_10mhz/ant_6.bin #CC5 -antC23=./usecase/mu0_10mhz/ant_7.bin #CC5 -antC24=./usecase/mu0_10mhz/ant_8.bin #CC6 -antC25=./usecase/mu0_10mhz/ant_9.bin #CC6 -antC26=./usecase/mu0_10mhz/ant_10.bin #CC6 -antC27=./usecase/mu0_10mhz/ant_11.bin #CC6 -antC28=./usecase/mu0_10mhz/ant_12.bin #CC7 -antC29=./usecase/mu0_10mhz/ant_13.bin #CC7 -antC30=./usecase/mu0_10mhz/ant_14.bin #CC7 -antC31=./usecase/mu0_10mhz/ant_15.bin #CC7 -antC32=./usecase/mu0_10mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_10mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_10mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_10mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_10mhz/ant_4.bin #CC9 -antC37=./usecase/mu0_10mhz/ant_5.bin #CC9 -antC38=./usecase/mu0_10mhz/ant_6.bin #CC9 -antC39=./usecase/mu0_10mhz/ant_7.bin #CC9 -antC40=./usecase/mu0_10mhz/ant_8.bin #CC10 -antC41=./usecase/mu0_10mhz/ant_9.bin #CC10 -antC42=./usecase/mu0_10mhz/ant_10.bin #CC10 -antC43=./usecase/mu0_10mhz/ant_11.bin #CC10 -antC44=./usecase/mu0_10mhz/ant_12.bin #CC11 -antC45=./usecase/mu0_10mhz/ant_13.bin #CC11 -antC46=./usecase/mu0_10mhz/ant_14.bin #CC11 -antC47=./usecase/mu0_10mhz/ant_15.bin #CC11 +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC3 +antC16=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC5 +antC21=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC5 +antC22=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC5 +antC23=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC5 +antC24=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC6 +antC25=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC6 +antC26=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC6 +antC27=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC6 +antC28=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC7 +antC29=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC7 +antC30=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC7 +antC31=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC7 +antC32=./usecase/cat_a/mu0_10mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_10mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_10mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_10mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_10mhz/ant_4.bin #CC9 +antC37=./usecase/cat_a/mu0_10mhz/ant_5.bin #CC9 +antC38=./usecase/cat_a/mu0_10mhz/ant_6.bin #CC9 +antC39=./usecase/cat_a/mu0_10mhz/ant_7.bin #CC9 +antC40=./usecase/cat_a/mu0_10mhz/ant_8.bin #CC10 +antC41=./usecase/cat_a/mu0_10mhz/ant_9.bin #CC10 +antC42=./usecase/cat_a/mu0_10mhz/ant_10.bin #CC10 +antC43=./usecase/cat_a/mu0_10mhz/ant_11.bin #CC10 +antC44=./usecase/cat_a/mu0_10mhz/ant_12.bin #CC11 +antC45=./usecase/cat_a/mu0_10mhz/ant_13.bin #CC11 +antC46=./usecase/cat_a/mu0_10mhz/ant_14.bin #CC11 +antC47=./usecase/cat_a/mu0_10mhz/ant_15.bin #CC11 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index -antPrachC0=./usecase/mu0_10mhz/ant_0.bin -antPrachC1=./usecase/mu0_10mhz/ant_1.bin -antPrachC2=./usecase/mu0_10mhz/ant_2.bin -antPrachC3=./usecase/mu0_10mhz/ant_3.bin +antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_10mhz/ant_3.bin ## control of IQ byte order iqswap=0 #do swap of IQ before send buffer to eth @@ -133,16 +133,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_10mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du.dat similarity index 61% rename from fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du.dat index c2f32c8..92d90a3 100644 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du.dat @@ -21,8 +21,8 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=2048 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,71 +55,71 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_20mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_20mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_20mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_20mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_20mhz/ant_0.bin #CC1 -antC5=./usecase/mu0_20mhz/ant_1.bin #CC1 -antC6=./usecase/mu0_20mhz/ant_2.bin #CC1 -antC7=./usecase/mu0_20mhz/ant_3.bin #CC1 -antC8=./usecase/mu0_20mhz/ant_0.bin #CC2 -antC9=./usecase/mu0_20mhz/ant_1.bin #CC2 -antC10=./usecase/mu0_20mhz/ant_2.bin #CC2 -antC11=./usecase/mu0_20mhz/ant_3.bin #CC2 -antC12=./usecase/mu0_20mhz/ant_0.bin #CC3 -antC13=./usecase/mu0_20mhz/ant_1.bin #CC3 -antC14=./usecase/mu0_20mhz/ant_2.bin #CC3 -antC15=./usecase/mu0_20mhz/ant_3.bin #CC3 -antC16=./usecase/mu0_20mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_20mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_20mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_20mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_20mhz/ant_0.bin #CC5 -antC21=./usecase/mu0_20mhz/ant_1.bin #CC5 -antC22=./usecase/mu0_20mhz/ant_2.bin #CC5 -antC23=./usecase/mu0_20mhz/ant_3.bin #CC5 -antC24=./usecase/mu0_20mhz/ant_0.bin #CC6 -antC25=./usecase/mu0_20mhz/ant_1.bin #CC6 -antC26=./usecase/mu0_20mhz/ant_2.bin #CC6 -antC27=./usecase/mu0_20mhz/ant_3.bin #CC6 -antC28=./usecase/mu0_20mhz/ant_0.bin #CC7 -antC29=./usecase/mu0_20mhz/ant_1.bin #CC7 -antC30=./usecase/mu0_20mhz/ant_2.bin #CC7 -antC31=./usecase/mu0_20mhz/ant_3.bin #CC7 -antC32=./usecase/mu0_20mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_20mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_20mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_20mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_20mhz/ant_0.bin #CC9 -antC37=./usecase/mu0_20mhz/ant_1.bin #CC9 -antC38=./usecase/mu0_20mhz/ant_2.bin #CC9 -antC39=./usecase/mu0_20mhz/ant_3.bin #CC9 -antC40=./usecase/mu0_20mhz/ant_0.bin #CC10 -antC41=./usecase/mu0_20mhz/ant_1.bin #CC10 -antC42=./usecase/mu0_20mhz/ant_2.bin #CC10 -antC43=./usecase/mu0_20mhz/ant_3.bin #CC10 -antC44=./usecase/mu0_20mhz/ant_0.bin #CC11 -antC45=./usecase/mu0_20mhz/ant_1.bin #CC11 -antC46=./usecase/mu0_20mhz/ant_2.bin #CC11 -antC47=./usecase/mu0_20mhz/ant_3.bin #CC11 +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC3 +antC16=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC5 +antC21=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC5 +antC22=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC5 +antC23=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC5 +antC24=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC6 +antC25=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC6 +antC26=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC6 +antC27=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC6 +antC28=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC7 +antC29=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC7 +antC30=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC7 +antC31=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC7 +antC32=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC9 +antC37=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC9 +antC38=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC9 +antC39=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC9 +antC40=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC10 +antC41=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC10 +antC42=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC10 +antC43=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC10 +antC44=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC11 +antC45=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC11 +antC46=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC11 +antC47=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC11 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=1 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,75,0,14,0,1,0,16,1 nPrbElemUl=1 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,75,0,14,0,1,0,16,1 ########################################################### @@ -143,16 +143,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_0.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_0.dat new file mode 100644 index 0000000..d1f3391 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_0.dat @@ -0,0 +1,237 @@ +####################################################################### +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +####################################################################### + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +#fd 10Mhz 2 +#antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC4=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC5=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC6=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC7=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC8=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC9=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC10=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC11=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC12=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC13=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC14=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC15=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC16=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC17=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC18=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC19=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC20=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC21=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC22=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC23=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC24=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC25=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC26=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC27=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC28=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC29=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC30=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC31=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC32=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC33=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC34=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC35=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC36=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC37=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC38=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC39=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC40=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC41=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC42=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC43=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC44=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC45=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC46=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC47=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC0 + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 + +#antC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC1 +#antC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC1 +#antC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC1 +#antC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC1 +#antC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC2 +#antC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC2 +#antC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC2 +#antC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC2 +#antC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC3 +#antC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC3 +#antC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC3 +#antC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC3 +#antC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC4 +#antC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC4 +#antC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC4 +#antC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC4 +#antC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC5 +#antC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC5 +#antC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC5 +#antC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC5 +#antC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC6 +#antC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC6 +#antC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC6 +#antC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC6 +#antC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC7 +#antC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC7 +#antC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC7 +#antC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC7 +#antC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC8 +#antC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC8 +#antC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC8 +#antC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC8 +#antC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC9 +#antC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC9 +#antC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC9 +#antC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC9 +#antC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC10 +#antC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC10 +#antC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC10 +#antC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC10 +#antC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC11 +#antC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC11 +#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11 +#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_1.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_1.dat new file mode 100644 index 0000000..f395c78 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_du_1.dat @@ -0,0 +1,237 @@ +####################################################################### +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +####################################################################### + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +#fd 10Mhz 2 +#antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC4=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC5=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC6=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC7=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC8=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC9=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC10=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC11=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC12=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC13=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC14=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC15=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC16=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC17=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC18=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC19=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC20=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC21=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC22=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC23=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC24=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC25=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC26=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC27=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC28=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC29=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC30=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC31=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC32=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC33=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC34=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC35=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC36=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC37=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC38=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC39=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC40=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC41=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC42=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC43=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC44=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC45=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC46=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC47=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC0 + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 + +#antC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC1 +#antC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC1 +#antC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC1 +#antC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC1 +#antC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC2 +#antC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC2 +#antC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC2 +#antC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC2 +#antC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC3 +#antC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC3 +#antC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC3 +#antC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC3 +#antC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC4 +#antC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC4 +#antC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC4 +#antC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC4 +#antC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC5 +#antC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC5 +#antC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC5 +#antC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC5 +#antC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC6 +#antC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC6 +#antC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC6 +#antC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC6 +#antC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC7 +#antC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC7 +#antC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC7 +#antC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC7 +#antC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC8 +#antC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC8 +#antC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC8 +#antC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC8 +#antC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC9 +#antC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC9 +#antC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC9 +#antC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC9 +#antC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC10 +#antC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC10 +#antC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC10 +#antC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC10 +#antC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC11 +#antC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC11 +#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11 +#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru.dat new file mode 100644 index 0000000..08c3de2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru.dat @@ -0,0 +1,230 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC3 +antC16=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC4 +antC17=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC4 +antC18=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC4 +antC19=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC4 +antC20=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC5 +antC21=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC5 +antC22=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC5 +antC23=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC5 +antC24=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC6 +antC25=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC6 +antC26=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC6 +antC27=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC6 +antC28=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC7 +antC29=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC7 +antC30=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC7 +antC31=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC7 +antC32=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC8 +antC33=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC8 +antC34=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC8 +antC35=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC8 +antC36=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC9 +antC37=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC9 +antC38=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC9 +antC39=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC9 +antC40=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC10 +antC41=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC10 +antC42=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC10 +antC43=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC10 +antC44=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC11 +antC45=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC11 +antC46=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC11 +antC47=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC4=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC5=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC6=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC7=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC8=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC9=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC10=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC11=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC12=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC13=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC14=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC15=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC16=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC17=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC18=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC19=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC20=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC21=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC22=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC23=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC24=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC25=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC26=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC27=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC28=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC29=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC30=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC31=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC32=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC33=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC34=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC35=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC36=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC37=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC38=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC39=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC40=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC41=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC42=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC43=./usecase/cat_a/mu0_20mhz/ant_3.bin +antPrachC44=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC45=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC46=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC47=./usecase/cat_a/mu0_20mhz/ant_3.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,75,0,14,0,1,0,16,1 +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,75,0,14,0,1,0,16,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_0.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_0.dat new file mode 100644 index 0000000..98fe643 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_0.dat @@ -0,0 +1,287 @@ +####################################################################### +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +####################################################################### + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=3 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +#fd 10Mhz 2 +#antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC4=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC5=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC6=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC7=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC8=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC9=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC10=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC11=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC12=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC13=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC14=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC15=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC16=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC17=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC18=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC19=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC20=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC21=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC22=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC23=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC24=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC25=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC26=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC27=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC28=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC29=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC30=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC31=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC32=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC33=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC34=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC35=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC36=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC37=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC38=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC39=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC40=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC41=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC42=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC43=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC44=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC45=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC46=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC47=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC0 + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 + +#antC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC1 +#antC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC1 +#antC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC1 +#antC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC1 +#antC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC2 +#antC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC2 +#antC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC2 +#antC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC2 +#antC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC3 +#antC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC3 +#antC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC3 +#antC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC3 +#antC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC4 +#antC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC4 +#antC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC4 +#antC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC4 +#antC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC5 +#antC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC5 +#antC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC5 +#antC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC5 +#antC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC6 +#antC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC6 +#antC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC6 +#antC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC6 +#antC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC7 +#antC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC7 +#antC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC7 +#antC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC7 +#antC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC8 +#antC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC8 +#antC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC8 +#antC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC8 +#antC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC9 +#antC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC9 +#antC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC9 +#antC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC9 +#antC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC10 +#antC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC10 +#antC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC10 +#antC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC10 +#antC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC11 +#antC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC11 +#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11 +#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin +antPrachC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin +antPrachC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_1.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_1.dat new file mode 100644 index 0000000..b80a9b1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/config_file_o_ru_1.dat @@ -0,0 +1,287 @@ +####################################################################### +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +####################################################################### + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +#fd 10Mhz 2 +#antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC0=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC1=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC2=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC3=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC4=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC5=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC6=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC7=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC8=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC9=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC10=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC11=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC12=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC13=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC14=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC15=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC16=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC17=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC18=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC19=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC20=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC21=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC22=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC23=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC24=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC25=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC26=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC27=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC28=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC29=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC30=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC31=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC32=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC33=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC34=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC35=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC36=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC37=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC38=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC39=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC40=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC41=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC42=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC43=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + +antC44=../usecase/cat_a/mu0_20mhz/12/uliq0.bin #CC0 +antC45=../usecase/cat_a/mu0_20mhz/12/uliq1.bin #CC0 +antC46=../usecase/cat_a/mu0_20mhz/12/uliq2.bin #CC0 +antC47=../usecase/cat_a/mu0_20mhz/12/uliq3.bin #CC0 + + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC0 + +#antC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC1=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC2=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 +#antC3=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC0 + +#antC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC1 +#antC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC1 +#antC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC1 +#antC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC1 +#antC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC2 +#antC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC2 +#antC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC2 +#antC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC2 +#antC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC3 +#antC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC3 +#antC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC3 +#antC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC3 +#antC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC4 +#antC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC4 +#antC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC4 +#antC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC4 +#antC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC5 +#antC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC5 +#antC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC5 +#antC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC5 +#antC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC6 +#antC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC6 +#antC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC6 +#antC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC6 +#antC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC7 +#antC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC7 +#antC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC7 +#antC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC7 +#antC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin #CC8 +#antC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin #CC8 +#antC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin #CC8 +#antC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin #CC8 +#antC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin #CC9 +#antC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin #CC9 +#antC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin #CC9 +#antC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin #CC9 +#antC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin #CC10 +#antC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin #CC10 +#antC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin #CC10 +#antC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin #CC10 +#antC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin #CC11 +#antC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin #CC11 +#antC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin #CC11 +#antC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin #CC11 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC1=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC2=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC3=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC4=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC5=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC6=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC7=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC8=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC9=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC10=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC11=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC12=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC13=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC14=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC15=../usecase/cat_a/mu0_20mhz/12/ant_15.bin +antPrachC16=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC17=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC18=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC19=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC20=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC21=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC22=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC23=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC24=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC25=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC26=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC27=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC28=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC29=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC30=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC31=../usecase/cat_a/mu0_20mhz/12/ant_15.bin +antPrachC32=../usecase/cat_a/mu0_20mhz/12/ant_0.bin +antPrachC33=../usecase/cat_a/mu0_20mhz/12/ant_1.bin +antPrachC34=../usecase/cat_a/mu0_20mhz/12/ant_2.bin +antPrachC35=../usecase/cat_a/mu0_20mhz/12/ant_3.bin +antPrachC36=../usecase/cat_a/mu0_20mhz/12/ant_4.bin +antPrachC37=../usecase/cat_a/mu0_20mhz/12/ant_5.bin +antPrachC38=../usecase/cat_a/mu0_20mhz/12/ant_6.bin +antPrachC39=../usecase/cat_a/mu0_20mhz/12/ant_7.bin +antPrachC40=../usecase/cat_a/mu0_20mhz/12/ant_8.bin +antPrachC41=../usecase/cat_a/mu0_20mhz/12/ant_9.bin +antPrachC42=../usecase/cat_a/mu0_20mhz/12/ant_10.bin +antPrachC43=../usecase/cat_a/mu0_20mhz/12/ant_11.bin +antPrachC44=../usecase/cat_a/mu0_20mhz/12/ant_12.bin +antPrachC45=../usecase/cat_a/mu0_20mhz/12/ant_13.bin +antPrachC46=../usecase/cat_a/mu0_20mhz/12/ant_14.bin +antPrachC47=../usecase/cat_a/mu0_20mhz/12/ant_15.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=160 #in us +Ta3_max=256 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=480 +T1a_max_cp_ul=560 + +#U-plane +##Transmission Window +T1a_min_up=280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=360 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_du.cfg new file mode 100644 index 0000000..44af819 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] +#dpdkMemorySize=10240 +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_ru.cfg new file mode 100644 index 0000000..31a15b5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/12/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] +#dpdkMemorySize=10240 +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_du.dat new file mode 100644 index 0000000..f5d2d26 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_du.dat @@ -0,0 +1,136 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 ## 480 +T1a_max_cp_ul=356 ## 560 + +#U-plane +##Transmission Window +T1a_min_up=370 ## 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 ## 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_ru.dat new file mode 100644 index 0000000..208fee5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/config_file_o_ru.dat @@ -0,0 +1,143 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 # 480 +T1a_max_cp_ul=356 # 560 + +#U-plane +##Transmission Window +T1a_min_up=370 # 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 # 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_du.cfg new file mode 100644 index 0000000..5546c0e --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_du.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=1 #O-DU is always originator +oXuOwdmMeasMeth=0 # Measurement Method REQUEST +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=40 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_ru.cfg new file mode 100644 index 0000000..927a5f8 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/20/usecase_ru.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=0 #O-RU is always the recipient +oXuOwdmMeasMeth=0 # Measurement Method REQUEST +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=40 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_du.dat new file mode 100644 index 0000000..f5d2d26 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_du.dat @@ -0,0 +1,136 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 ## 480 +T1a_max_cp_ul=356 ## 560 + +#U-plane +##Transmission Window +T1a_min_up=370 ## 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 ## 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_ru.dat new file mode 100644 index 0000000..208fee5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/config_file_o_ru.dat @@ -0,0 +1,143 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 # 480 +T1a_max_cp_ul=356 # 560 + +#U-plane +##Transmission Window +T1a_min_up=370 # 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 # 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_du.cfg new file mode 100644 index 0000000..a1d3e6f --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_du.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=1 #O-DU is always the originator +oXuOwdmMeasMeth=1 # Measurement Method REM_REQ +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=512 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_ru.cfg new file mode 100644 index 0000000..256869b --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/21/usecase_ru.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=0 #O-RU is always the recipient +oXuOwdmMeasMeth=1 # Measurement Method REM_REQ +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=512 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_du.dat new file mode 100644 index 0000000..f5d2d26 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_du.dat @@ -0,0 +1,136 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 ## 480 +T1a_max_cp_ul=356 ## 560 + +#U-plane +##Transmission Window +T1a_min_up=370 ## 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 ## 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_ru.dat new file mode 100644 index 0000000..208fee5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/config_file_o_ru.dat @@ -0,0 +1,143 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 # 480 +T1a_max_cp_ul=356 # 560 + +#U-plane +##Transmission Window +T1a_min_up=370 # 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 # 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_du.cfg new file mode 100644 index 0000000..9f7faec --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_du.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=1 #O-DU is always recipient +oXuOwdmMeasMeth=2 # Measurement Method REQUESTwFUP +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=1024 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_ru.cfg new file mode 100644 index 0000000..1bac1ba --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/22/usecase_ru.cfg @@ -0,0 +1,79 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=0 #O-RU is always the recipient +oXuOwdmMeasMeth=2 # Measurement Method REQ_WFUP +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +oXuOwdmPlLength=1024 # PL for dummy payload in the measurement packet 40 <= PL <= 1400 +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu0_20mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_du.dat similarity index 76% rename from fhi_lib/app/usecase/mu0_20mhz/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_du.dat index f34c974..4abf087 100644 --- a/fhi_lib/app/usecase/mu0_20mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=2048 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,28 +55,27 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu0_20mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_20mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_20mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_20mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_20mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_20mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_20mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_20mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_20mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_20mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_20mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_20mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_20mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_20mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_20mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_20mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 ## RACH TODO: update for PRACH -rachEanble=1 # Enable (1)| disable (0) PRACH configuration -#rachOffset=43 # RB offset for prach detection (see RIU spec) -#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ## control of IQ byte order @@ -99,20 +98,20 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us +Ta3_min=100 #in us +Ta3_max=140 #in us ########################################################### ##lls-CU Settings @@ -132,6 +131,6 @@ T1a_max_up=400 #Reception Window Ta4_min=0 -Ta4_max=360 +Ta4_max=200 ########################################################### diff --git a/fhi_lib/app/usecase/mu0_20mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_ru.dat similarity index 76% rename from fhi_lib/app/usecase/mu0_20mhz/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_ru.dat index d5b3d5d..0aed8c8 100644 --- a/fhi_lib/app/usecase/mu0_20mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/config_file_o_ru.dat @@ -22,7 +22,7 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=2048 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -56,33 +56,33 @@ duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu0_20mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_20mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_20mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_20mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_20mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_20mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_20mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_20mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_20mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_20mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_20mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_20mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_20mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_20mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_20mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_20mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 ## RACH TODO: update for PRACH -rachEanble=1 # Enable (1)| disable (0) PRACH configuration +rachEanble=0 # Enable (1)| disable (0) PRACH configuration #rachOffset=43 # RB offset for prach detection (see RIU spec) prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index -antPrachC0=./usecase/mu0_20mhz/ant_0.bin -antPrachC1=./usecase/mu0_20mhz/ant_1.bin -antPrachC2=./usecase/mu0_20mhz/ant_2.bin -antPrachC3=./usecase/mu0_20mhz/ant_3.bin +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin ## control of IQ byte order @@ -105,20 +105,20 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us +Ta3_min=100 #in us +Ta3_max=140 #in us ########################################################### ##lls-CU Settings @@ -138,6 +138,6 @@ T1a_max_up=400 #Reception Window Ta4_min=0 -Ta4_max=360 +Ta4_max=200 ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_du.cfg new file mode 100644 index 0000000..f98f420 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_du.cfg @@ -0,0 +1,78 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=0 #O-DU is always recipient +oXuOwdmMeasMeth=3 # Measurement Method REM_REQ_WFUP +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_ru.cfg new file mode 100644 index 0000000..d4940dd --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/23/usecase_ru.cfg @@ -0,0 +1,78 @@ +#****************************************************************************** +# +# Copyright (c) 2020 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# One Way Delay Measurements configuration parameters +oXuOwdmInitEn=1 #O-RU is always the initiator +oXuOwdmMeasMeth=3 # Measurement Method REM_REQ_WFUP +oXuOwdmNumSamps=8 # Run 8 samples per port +oXuOwdmFltrType=0 # Simple average +oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns +oXuOwdmMeasState=0 # Measurement state is INIT +oXuOwdmMeasId=0 # Measurement Id seed +oXuOwdmEnabled=1 # Measurements are enabled +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_du.dat new file mode 100644 index 0000000..f5d2d26 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_du.dat @@ -0,0 +1,136 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 ## 480 +T1a_max_cp_ul=356 ## 560 + +#U-plane +##Transmission Window +T1a_min_up=370 ## 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 ## 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_ru.dat new file mode 100644 index 0000000..208fee5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/config_file_o_ru.dat @@ -0,0 +1,143 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +antPrachC0=./usecase/cat_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_20mhz/ant_3.bin + + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=125 #in us 400 +T2a_max_cp_ul=850 #in us + +#Reception Window U-plane +T2a_min_up=200 # in us +T2a_max_up=800 # in us + +#Transmission Window +Ta3_min=100 #in us +Ta3_max=140 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=560 +T1a_max_cp_dl=800 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=300 # 480 +T1a_max_cp_ul=356 # 560 + +#U-plane +##Transmission Window +T1a_min_up=370 # 280 +T1a_max_up=400 + +#Reception Window +Ta4_min=0 +Ta4_max=400 # 200 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_20mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu0_5mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_du.dat similarity index 81% rename from fhi_lib/app/usecase/mu0_5mhz/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_du.dat index feeeee4..37c8968 100644 --- a/fhi_lib/app/usecase/mu0_5mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -37,7 +37,7 @@ nULFftSize=512 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,24 +55,24 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_5mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_5mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_5mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_5mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_5mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_5mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_5mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_5mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_5mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_5mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_5mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_5mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_5mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_5mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_5mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_5mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files + +antC0=./usecase/cat_a/mu0_5mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_5mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_5mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_5mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_5mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_5mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_5mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_5mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_5mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_5mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_5mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_5mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_5mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_5mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_5mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_5mhz/ant_15.bin #CC3 ## RACH TODO: update for PRACH rachEanble=0 # Enable (1)| disable (0) PRACH configuration @@ -99,16 +99,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/mu0_5mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_ru.dat similarity index 78% rename from fhi_lib/app/usecase/mu0_5mhz/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_ru.dat index f2c20a2..bd9cd87 100644 --- a/fhi_lib/app/usecase/mu0_5mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu0_5mhz/config_file_o_ru.dat @@ -37,7 +37,7 @@ nULFftSize=512 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -55,32 +55,32 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu0_5mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_5mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_5mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_5mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_5mhz/ant_4.bin #CC1 -antC5=./usecase/mu0_5mhz/ant_5.bin #CC1 -antC6=./usecase/mu0_5mhz/ant_6.bin #CC1 -antC7=./usecase/mu0_5mhz/ant_7.bin #CC1 -antC8=./usecase/mu0_5mhz/ant_8.bin #CC2 -antC9=./usecase/mu0_5mhz/ant_9.bin #CC2 -antC10=./usecase/mu0_5mhz/ant_10.bin #CC2 -antC11=./usecase/mu0_5mhz/ant_11.bin #CC2 -antC12=./usecase/mu0_5mhz/ant_12.bin #CC3 -antC13=./usecase/mu0_5mhz/ant_13.bin #CC3 -antC14=./usecase/mu0_5mhz/ant_14.bin #CC3 -antC15=./usecase/mu0_5mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu0_5mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu0_5mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu0_5mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu0_5mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu0_5mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu0_5mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu0_5mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu0_5mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu0_5mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu0_5mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu0_5mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu0_5mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu0_5mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu0_5mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu0_5mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu0_5mhz/ant_15.bin #CC3 ## RACH TODO: update for PRACH rachEanble=0 # Enable (1)| disable (0) PRACH configuration #rachOffset=43 # RB offset for prach detection (see RIU spec) #prachConfigIndex=1 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index -antPrachC0=./usecase/mu0_10mhz/ant_0.bin -antPrachC1=./usecase/mu0_10mhz/ant_1.bin -antPrachC2=./usecase/mu0_10mhz/ant_2.bin -antPrachC3=./usecase/mu0_10mhz/ant_3.bin +antPrachC0=./usecase/cat_a/mu0_10mhz/ant_0.bin +antPrachC1=./usecase/cat_a/mu0_10mhz/ant_1.bin +antPrachC2=./usecase/cat_a/mu0_10mhz/ant_2.bin +antPrachC3=./usecase/cat_a/mu0_10mhz/ant_3.bin ## control of IQ byte order iqswap=0 #do swap of IQ before send buffer to eth @@ -99,16 +99,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us +T2a_min_cp_dl=400 #in us +T2a_max_cp_dl=850 #in us #Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us +T2a_min_cp_ul=400 #in us +T2a_max_cp_ul=850 #in us #Reception Window U-plane T2a_min_up=200 # in us -T2a_max_up=1120 # in us +T2a_max_up=800 # in us #Transmission Window Ta3_min=160 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu0_5mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_du.dat similarity index 84% rename from fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_du.dat index 888f1e0..0c80dee 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_du.dat @@ -21,7 +21,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # O-DU(0) | RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -66,34 +66,34 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,137,0,14,0,0,0,16,0 PrbElemDl1=137,136,0,14,0,0,0,16,0 PrbElemDl2=72,36,0,14,3,1,0,16,1 @@ -106,7 +106,7 @@ PrbElemDl7=252,21,0,14,8,1,0,16,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,137,0,14,0,0,0,16,0 PrbElemUl1=137,136,0,14,0,0,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 @@ -147,8 +147,8 @@ T2a_min_up=134 # 71.35in us T2a_max_up=345 # 428.12us #Transmission Window -Ta3_min=50 # in us -Ta3_max=171 # in us +Ta3_min=50 # in us +Ta3_max=171 # in us ########################################################### ##O-DU Settings @@ -167,7 +167,7 @@ T1a_min_up=294 #71 + 25 us T1a_max_up=345 #71 + 25 us #Reception Window -Ta4_min=50 # in us -Ta4_max=331 # in us +Ta4_min=50 # in us +Ta4_max=331 # in us ########################################################### diff --git a/fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_ru.dat similarity index 75% rename from fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_ru.dat index 77fe732..40cca8a 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/101/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/config_file_o_ru.dat @@ -21,7 +21,7 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -66,51 +66,51 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,137,0,14,0,0,0,16,0 PrbElemDl1=137,136,0,14,0,0,0,16,0 PrbElemDl2=72,36,0,14,3,1,0,16,1 @@ -123,7 +123,7 @@ PrbElemDl7=252,21,0,14,8,1,0,16,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,137,0,14,0,0,0,16,0 PrbElemUl1=137,136,0,14,0,0,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 @@ -162,8 +162,8 @@ T2a_min_up=134 # 71.35in us T2a_max_up=345 # 428.12us #Transmission Window -Ta3_min=50 # in us -Ta3_max=171 # in us +Ta3_min=50 # in us +Ta3_max=171 # in us ########################################################### ##O-DU Settings @@ -182,7 +182,7 @@ T1a_min_up=294 #71 + 25 us T1a_max_up=345 #71 + 25 us #Reception Window -Ta4_min=50 # in us -Ta4_max=331 # in us +Ta4_min=50 # in us +Ta4_max=331 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/101/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_du.dat similarity index 84% rename from fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_du.dat index 3a5104b..19fdafb 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_du.dat @@ -21,7 +21,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # O-DU(0) | RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -66,34 +66,34 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,137,0,14,1,1,0,16,0 PrbElemDl1=137,136,0,14,2,1,0,16,0 PrbElemDl2=72,36,0,14,3,1,0,16,1 @@ -106,7 +106,7 @@ PrbElemDl7=252,21,0,14,8,1,0,16,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,137,0,14,1,1,0,16,0 PrbElemUl1=137,136,0,14,2,1,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 @@ -147,8 +147,8 @@ T2a_min_up=134 # 71.35in us T2a_max_up=345 # 428.12us #Transmission Window -Ta3_min=50 # in us -Ta3_max=171 # in us +Ta3_min=50 # in us +Ta3_max=171 # in us ########################################################### ##O-DU Settings @@ -167,7 +167,7 @@ T1a_min_up=294 #71 + 25 us T1a_max_up=345 #71 + 25 us #Reception Window -Ta4_min=50 # in us -Ta4_max=331 # in us +Ta4_min=50 # in us +Ta4_max=331 # in us ########################################################### diff --git a/fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_ru.dat similarity index 75% rename from fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_ru.dat index 434574d..a7209cb 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/102/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/config_file_o_ru.dat @@ -21,7 +21,7 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -66,51 +66,51 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=147 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,137,0,14,1,1,0,16,0 PrbElemDl1=137,136,0,14,2,1,0,16,0 PrbElemDl2=72,36,0,14,3,1,0,16,1 @@ -123,7 +123,7 @@ PrbElemDl7=252,21,0,14,8,1,0,16,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,137,0,14,1,1,0,16,0 PrbElemUl1=137,136,0,14,2,1,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 @@ -162,8 +162,8 @@ T2a_min_up=134 # 71.35in us T2a_max_up=345 # 428.12us #Transmission Window -Ta3_min=50 # in us -Ta3_max=171 # in us +Ta3_min=50 # in us +Ta3_max=171 # in us ########################################################### ##O-DU Settings @@ -182,7 +182,7 @@ T1a_min_up=294 #71 + 25 us T1a_max_up=345 #71 + 25 us #Reception Window -Ta4_min=50 # in us -Ta4_max=331 # in us +Ta4_min=50 # in us +Ta4_max=331 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/102/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_du.dat similarity index 83% rename from fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_du.dat index f722129..0d4d03c 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_du.dat @@ -36,7 +36,7 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it’s 6:4:4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it�s 6:4:4 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -65,23 +65,23 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration @@ -115,8 +115,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##lls-CU Settings @@ -135,8 +135,8 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### ##Section Settings DynamicSectionEna=1 diff --git a/fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_ru.dat similarity index 73% rename from fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_ru.dat index 196e763..86e3219 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/2/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/config_file_o_ru.dat @@ -36,7 +36,7 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it’s 6:4:4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it�s 6:4:4 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD @@ -48,7 +48,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -65,40 +65,40 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=1 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/2/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_du.dat new file mode 100644 index 0000000..a5ab347 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_du.dat @@ -0,0 +1,174 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/256qam_ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/256qam_ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,273,0,14,0,0,4,4,0,10048,4095 +PrbElemDl1=36,36,0,14,2,1,0,16,1,0,0 +PrbElemDl2=72,36,0,14,3,1,0,16,1,0,0 +PrbElemDl3=108,36,0,14,4,1,0,16,1,0,0 +PrbElemDl4=144,36,0,14,5,1,0,16,1,0,0 +PrbElemDl5=180,36,0,14,6,1,0,16,1,0,0 +PrbElemDl6=216,36,0,14,7,1,0,16,1,0,0 +PrbElemDl7=252,21,0,14,8,1,0,16,1,0,0 + + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemUl0=0,137,0,14,0,0,0,16,0,0,0 +PrbElemUl1=137,136,0,14,0,0,0,16,0,0,0 +PrbElemUl2=72,36,0,14,3,1,0,16,1,0,0 +PrbElemUl3=108,36,0,14,4,1,0,16,1,0,0 +PrbElemUl4=144,36,0,14,5,1,0,16,1,0,0 +PrbElemUl5=180,36,0,14,6,1,0,16,1,0,0 +PrbElemUl6=216,36,0,14,7,1,0,16,1,0,0 +PrbElemUl7=252,21,0,14,8,1,0,16,1,0,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=392 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=392 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_ru.dat new file mode 100644 index 0000000..e37b8af --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/config_file_o_ru.dat @@ -0,0 +1,189 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,273,0,14,0,0,4,4,0,10048,4095 +PrbElemDl1=36,36,0,14,2,1,0,16,1,0,0 +PrbElemDl2=72,36,0,14,3,1,0,16,1,0,0 +PrbElemDl3=108,36,0,14,4,1,0,16,1,0,0 +PrbElemDl4=144,36,0,14,5,1,0,16,1,0,0 +PrbElemDl5=180,36,0,14,6,1,0,16,1,0,0 +PrbElemDl6=216,36,0,14,7,1,0,16,1,0,0 +PrbElemDl7=252,21,0,14,8,1,0,16,1,0,0 + + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemUl0=0,137,0,14,0,0,0,16,0,0,0 +PrbElemUl1=137,136,0,14,0,0,0,16,0,0,0 +PrbElemUl2=72,36,0,14,3,1,0,16,1,0,0 +PrbElemUl3=108,36,0,14,4,1,0,16,1,0,0 +PrbElemUl4=144,36,0,14,5,1,0,16,1,0,0 +PrbElemUl5=180,36,0,14,6,1,0,16,1,0,0 +PrbElemUl6=216,36,0,14,7,1,0,16,1,0,0 +PrbElemUl7=252,21,0,14,8,1,0,16,1,0,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=392 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=392 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/3/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu1_100mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_du.dat similarity index 71% rename from fhi_lib/app/usecase/mu1_100mhz/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_du.dat index 753b67d..865a361 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_du.dat @@ -18,11 +18,11 @@ # This is simple configuration file. Use '#' sign for comments -instanceId=1 # 0,1,2,... in case more than 1 application started on the same system -appMode=1 # O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -49,12 +49,12 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=10 +ioCore=5 # Eth 0 duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app @@ -67,52 +67,39 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachCompMethod=0 +prachiqWidth=16 ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 -nPrbElemDl=8 +nPrbElemDl=1 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,36,0,14,1,1,0,16,1 +# weight base beams +PrbElemDl0=0,273,0,14,0,0,0,16,0 PrbElemDl1=36,36,0,14,2,1,0,16,1 PrbElemDl2=72,36,0,14,3,1,0,16,1 PrbElemDl3=108,36,0,14,4,1,0,16,1 @@ -122,11 +109,11 @@ PrbElemDl6=216,36,0,14,7,1,0,16,1 PrbElemDl7=252,21,0,14,8,1,0,16,1 -nPrbElemUl=8 +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,36,0,14,1,1,0,16,1 -PrbElemUl1=36,36,0,14,2,1,0,16,1 +# weight base beams +PrbElemUl0=0,137,0,14,0,0,0,16,0 +PrbElemUl1=137,136,0,14,0,0,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 PrbElemUl3=108,36,0,14,4,1,0,16,1 PrbElemUl4=144,36,0,14,5,1,0,16,1 @@ -145,14 +132,16 @@ debugStop=1 #stop app on 1pps boundary (gps_second % 30) debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode -CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled ##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + Tadv_cp_dl=25 # in us # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL T2a_min_cp_dl=285 # 285.42us -T2a_max_cp_dl=392 # 428.12us +T2a_max_cp_dl=470 # 428.12us #Reception Window C-plane UL T2a_min_cp_ul=285 # 285.42us @@ -163,19 +152,19 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings #C-plane #Transmission Window Fast C-plane DL T1a_min_cp_dl=285 -T1a_max_cp_dl=392 +T1a_max_cp_dl=470 ##Transmission Window Fast C-plane UL T1a_min_cp_ul=285 -T1a_max_cp_ul=300 +T1a_max_cp_ul=429 #U-plane ##Transmission Window @@ -183,7 +172,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_ru.dat new file mode 100644 index 0000000..e7b87c9 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/config_file_o_ru.dat @@ -0,0 +1,193 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachCompMethod=0 +prachiqWidth=16 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,273,0,14,0,0,0,16,0 +PrbElemDl1=36,36,0,14,2,1,0,16,1 +PrbElemDl2=72,36,0,14,3,1,0,16,1 +PrbElemDl3=108,36,0,14,4,1,0,16,1 +PrbElemDl4=144,36,0,14,5,1,0,16,1 +PrbElemDl5=180,36,0,14,6,1,0,16,1 +PrbElemDl6=216,36,0,14,7,1,0,16,1 +PrbElemDl7=252,21,0,14,8,1,0,16,1 + + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,137,0,14,0,0,0,16,0 +PrbElemUl1=137,136,0,14,0,0,0,16,0 +PrbElemUl2=72,36,0,14,3,1,0,16,1 +PrbElemUl3=108,36,0,14,4,1,0,16,1 +PrbElemUl4=144,36,0,14,5,1,0,16,1 +PrbElemUl5=180,36,0,14,6,1,0,16,1 +PrbElemUl6=216,36,0,14,7,1,0,16,1 +PrbElemUl7=252,21,0,14,8,1,0,16,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=470 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=470 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=429 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu1_100mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_du.dat similarity index 83% rename from fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_du.dat index ddb54b5..f3c3af6 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_du.dat @@ -22,21 +22,21 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ####################################################################### #Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,33,0,14,1,1,1,12,1 PrbElemDl1=33,33,0,14,2,1,1,12,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,33,0,14,1,1,1,12,1 PrbElemUl1=33,33,0,14,2,1,1,12,1 ####################################################################### @@ -65,7 +65,7 @@ sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -85,23 +85,23 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -127,12 +127,12 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=50 #in us -T2a_max_cp_dl=140 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=50 #in us -T2a_max_cp_ul=140 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane T2a_min_up=25 #in us diff --git a/fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_ru.dat similarity index 73% rename from fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_ru.dat index efa8858..e8ea0a4 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/1/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/config_file_o_ru.dat @@ -22,21 +22,21 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ####################################################################### #Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,33,0,14,1,1,1,12,1 PrbElemDl1=33,33,0,14,2,1,1,12,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,33,0,14,1,1,1,12,1 PrbElemUl1=33,33,0,14,2,1,1,12,1 ####################################################################### @@ -65,7 +65,7 @@ sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -85,40 +85,40 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -144,16 +144,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=50 #in us -T2a_max_cp_dl=140 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=50 #in us -T2a_max_cp_ul=140 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane T2a_min_up=25 #in us -T2a_max_up=140 #in us +T2a_max_up=70 #in us #Transmission Window Ta3_min=20 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/1/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_du.dat similarity index 79% rename from fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_du.dat index 5ac3018..75f9e50 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=3 #mmWave 120Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -68,23 +68,23 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -104,43 +104,43 @@ u_plane_vlan_tag=2 #VLAN Tag used for U-Plane ##RU Settings totalBFWeights=32 # Total number of Beamforming Weights on RU -Tadv_cp_dl=63 #in us TODO: update per RU implementation +Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=116 #in us -T2a_max_cp_dl=327 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=63 #in us -T2a_max_cp_ul=274 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane -T2a_min_up=53 #in us -T2a_max_up=264 #in us +T2a_min_up=25 #in us +T2a_max_up=70 #in us #Transmission Window Ta3_min=20 #in us -Ta3_max=90 #in us +Ta3_max=32 #in us ########################################################### ##lls-CU Settings #C-plane #Transmission Window Fast C-plane DL -T1a_min_cp_dl=276 -T1a_max_cp_dl=327 +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 ##Transmission Window Fast C-plane UL -T1a_min_cp_ul=223 -T1a_max_cp_ul=274 +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 #U-plane ##Transmission Window -T1a_min_up=213 -T1a_max_up=264 +T1a_min_up=35 +T1a_max_up=50 #Reception Window -Ta4_min=20 -Ta4_max=250 +Ta4_min=0 +Ta4_max=45 ########################################################### diff --git a/fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_ru.dat similarity index 68% rename from fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_ru.dat index cc842b3..8d37d50 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/101/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/config_file_o_ru.dat @@ -22,7 +22,7 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=3 #mmWave 120Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -68,40 +68,40 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -122,43 +122,43 @@ u_plane_vlan_tag=2 #VLAN Tag used for U-Plane ##RU Settings totalBFWeights=32 # Total number of Beamforming Weights on RU -Tadv_cp_dl=63 #in us TODO: update per RU implementation +Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=116 #in us -T2a_max_cp_dl=327 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=63 #in us -T2a_max_cp_ul=274 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane -T2a_min_up=53 #in us -T2a_max_up=264 #in us +T2a_min_up=25 #in us +T2a_max_up=70 #in us #Transmission Window Ta3_min=20 #in us -Ta3_max=90 #in us +Ta3_max=32 #in us ########################################################### ##lls-CU Settings #C-plane #Transmission Window Fast C-plane DL -T1a_min_cp_dl=276 -T1a_max_cp_dl=327 +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 ##Transmission Window Fast C-plane UL -T1a_min_cp_ul=223 -T1a_max_cp_ul=274 +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 #U-plane ##Transmission Window -T1a_min_up=213 -T1a_max_up=264 +T1a_min_up=35 +T1a_max_up=50 #Reception Window -Ta4_min=20 -Ta4_max=250 +Ta4_min=0 +Ta4_max=45 ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/101/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_du.dat new file mode 100644 index 0000000..e344d31 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_du.dat @@ -0,0 +1,170 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +# not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +#3c:fd:fe:b9:f8:b5 +# +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=3c:fd:fe:b9:f8:b5 +#00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_ru.dat new file mode 100644 index 0000000..575cfbb --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/config_file_o_ru.dat @@ -0,0 +1,184 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/2/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu1_100mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_du.dat similarity index 80% rename from fhi_lib/app/usecase/mu1_100mhz/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_du.dat index 9b30773..1b1fb09 100644 --- a/fhi_lib/app/usecase/mu1_100mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # O-DU(0) | RU(1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=1 #30Khz Sub Carrier Spacing @@ -49,7 +49,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -67,35 +67,37 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu1_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu1_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu1_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu1_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu1_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu1_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu1_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu1_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu1_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu1_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu1_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu1_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu1_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 -nPrbElemDl=8 +nPrbElemDl=1 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,36,0,14,1,1,0,16,1 +# weight base beams +PrbElemDl0=0,273,0,14,0,0,0,16,0 PrbElemDl1=36,36,0,14,2,1,0,16,1 PrbElemDl2=72,36,0,14,3,1,0,16,1 PrbElemDl3=108,36,0,14,4,1,0,16,1 @@ -105,11 +107,11 @@ PrbElemDl6=216,36,0,14,7,1,0,16,1 PrbElemDl7=252,21,0,14,8,1,0,16,1 -nPrbElemUl=8 +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,36,0,14,1,1,0,16,1 -PrbElemUl1=36,36,0,14,2,1,0,16,1 +# weight base beams +PrbElemUl0=0,136,0,14,0,0,0,16,0 +PrbElemUl1=136,137,0,14,0,0,0,16,0 PrbElemUl2=72,36,0,14,3,1,0,16,1 PrbElemUl3=108,36,0,14,4,1,0,16,1 PrbElemUl4=144,36,0,14,5,1,0,16,1 @@ -148,8 +150,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -168,7 +170,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_ru.dat new file mode 100644 index 0000000..9a3c574 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu1_config_file_o_ru.dat @@ -0,0 +1,191 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu1_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu1_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu1_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu1_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu1_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu1_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu1_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu1_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=159 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,273,0,14,0,0,0,16,0 +PrbElemDl1=36,36,0,14,2,1,0,16,1 +PrbElemDl2=72,36,0,14,3,1,0,16,1 +PrbElemDl3=108,36,0,14,4,1,0,16,1 +PrbElemDl4=144,36,0,14,5,1,0,16,1 +PrbElemDl5=180,36,0,14,6,1,0,16,1 +PrbElemDl6=216,36,0,14,7,1,0,16,1 +PrbElemDl7=252,21,0,14,8,1,0,16,1 + + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,136,0,14,0,0,0,16,0 +PrbElemUl1=136,137,0,14,0,0,0,16,0 +PrbElemUl2=72,36,0,14,3,1,0,16,1 +PrbElemUl3=108,36,0,14,4,1,0,16,1 +PrbElemUl4=144,36,0,14,5,1,0,16,1 +PrbElemUl5=180,36,0,14,6,1,0,16,1 +PrbElemUl6=216,36,0,14,7,1,0,16,1 +PrbElemUl7=252,21,0,14,8,1,0,16,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=392 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=392 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_du.dat new file mode 100644 index 0000000..726eec3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_du.dat @@ -0,0 +1,177 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +# not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,36,0,14,1,1,0,16,1 +PrbElemDl1=36,36,0,14,2,1,0,16,1 +PrbElemDl2=72,36,0,14,3,1,0,16,1 +PrbElemDl3=108,36,0,14,4,1,0,16,1 +PrbElemDl4=144,36,0,14,5,1,0,16,1 +PrbElemDl5=180,36,0,14,6,1,0,16,1 +PrbElemDl6=216,36,0,14,7,1,0,16,1 +PrbElemDl7=252,21,0,14,8,1,0,16,1 + + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,36,0,14,1,1,0,16,1 +PrbElemUl1=36,36,0,14,2,1,0,16,1 +PrbElemUl2=72,36,0,14,3,1,0,16,1 +PrbElemUl3=108,36,0,14,4,1,0,16,1 +PrbElemUl4=144,36,0,14,5,1,0,16,1 +PrbElemUl5=180,36,0,14,6,1,0,16,1 +PrbElemUl6=216,36,0,14,7,1,0,16,1 +PrbElemUl7=252,21,0,14,8,1,0,16,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_ru.dat new file mode 100644 index 0000000..14f774e --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/mu3_config_file_o_ru.dat @@ -0,0 +1,194 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,36,0,14,1,1,0,16,1 +PrbElemDl1=36,36,0,14,2,1,0,16,1 +PrbElemDl2=72,36,0,14,3,1,0,16,1 +PrbElemDl3=108,36,0,14,4,1,0,16,1 +PrbElemDl4=144,36,0,14,5,1,0,16,1 +PrbElemDl5=180,36,0,14,6,1,0,16,1 +PrbElemDl6=216,36,0,14,7,1,0,16,1 +PrbElemDl7=252,21,0,14,8,1,0,16,1 + + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,36,0,14,1,1,0,16,1 +PrbElemUl1=36,36,0,14,2,1,0,16,1 +PrbElemUl2=72,36,0,14,3,1,0,16,1 +PrbElemUl3=108,36,0,14,4,1,0,16,1 +PrbElemUl4=144,36,0,14,5,1,0,16,1 +PrbElemUl5=180,36,0,14,6,1,0,16,1 +PrbElemUl6=216,36,0,14,7,1,0,16,1 +PrbElemUl7=252,21,0,14,8,1,0,16,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_du.cfg new file mode 100644 index 0000000..3d005c4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_du.cfg @@ -0,0 +1,69 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=2 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./mu3_config_file_o_du.dat #O-DU0 +oXuCfgFile1=./mu1_config_file_o_du.dat #O-DU1 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_ru.cfg new file mode 100644 index 0000000..d0136a5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/201/usecase_ru.cfg @@ -0,0 +1,69 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=2 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./mu3_config_file_o_ru.dat #O-RU0 +oXuCfgFile1=./mu1_config_file_o_ru.dat #O-RU1 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_du.dat new file mode 100644 index 0000000..1ab9aa6 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_du.dat @@ -0,0 +1,170 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=0 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +#3c:fd:fe:b9:f8:b5 +# +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_ru.dat new file mode 100644 index 0000000..ba78b37 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/config_file_o_ru.dat @@ -0,0 +1,190 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=0 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/uliq00_tst1.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/uliq01_tst1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/uliq00_tst1.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/uliq01_tst1.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 +#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/3/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_du.dat new file mode 100644 index 0000000..17e5b97 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_du.dat @@ -0,0 +1,171 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,0,16,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,0,16,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +#3c:fd:fe:b9:f8:b5 +# +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_ru.dat new file mode 100644 index 0000000..f50f3bc --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/config_file_o_ru.dat @@ -0,0 +1,191 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,0,16,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,0,16,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 +#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/4/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_du.dat new file mode 100644 index 0000000..61517aa --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_du.dat @@ -0,0 +1,170 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,1,9,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,1,9,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_ru.dat new file mode 100644 index 0000000..1fb8176 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/config_file_o_ru.dat @@ -0,0 +1,191 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,1,9,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,1,9,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 +#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/5/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_du.dat new file mode 100644 index 0000000..9be637d --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_du.dat @@ -0,0 +1,175 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,7,1,1,0,16,1 +PrbElemDl1=0,66,7,7,2,1,0,16,1 +#PrbElemDl2=0,66,10,4,3,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,7,1,1,0,16,1 +PrbElemUl1=0,66,7,7,2,1,0,16,1 +#PrbElemUl2=0,66,10,4,3,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +#ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +#ruMac0=00:11:22:33:44:55 +ruMac0=3c:fd:fe:b9:f8:b5 + +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=3c:fd:fe:b9:f8:b5 +#ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app +# + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_ru.dat new file mode 100644 index 0000000..bceb969 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/config_file_o_ru.dat @@ -0,0 +1,191 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,7,1,1,0,16,1 +PrbElemDl1=0,66,7,7,2,1,0,16,1 +#PrbElemDl2=0,66,10,4,3,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,7,1,1,0,16,1 +PrbElemUl1=0,66,7,7,2,1,0,16,1 +#PrbElemUl2=0,66,10,4,3,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 +#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=0 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/6/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_du.dat new file mode 100644 index 0000000..f1d9e82 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_du.dat @@ -0,0 +1,166 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,33,0,14,1,1,1,12,1 +PrbElemDl1=33,33,0,14,2,1,1,12,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,33,0,14,1,1,1,12,1 +PrbElemUl1=33,33,0,14,2,1,1,12,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +# not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_ru.dat new file mode 100644 index 0000000..b56ed33 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/config_file_o_ru.dat @@ -0,0 +1,182 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,33,0,14,1,1,1,12,1 +PrbElemDl1=33,33,0,14,2,1,1,12,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,33,0,14,1,1,1,12,1 +PrbElemUl1=33,33,0,14,2,1,1,12,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/7/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_du.dat new file mode 100644 index 0000000..57ef800 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_du.dat @@ -0,0 +1,170 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +# not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +#3c:fd:fe:b9:f8:b5 +# +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=3c:fd:fe:b9:f8:b5 +#00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_ru.dat new file mode 100644 index 0000000..f68b5c4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/config_file_o_ru.dat @@ -0,0 +1,184 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,22,0,14,0,1,1,14,1 +PrbElemDl1=22,22,0,14,1,1,1,14,1 +PrbElemDl2=44,22,0,14,2,1,1,14,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,22,0,14,0,1,1,14,1 +PrbElemUl1=22,22,0,14,1,1,1,14,1 +PrbElemUl2=44,22,0,14,2,1,1,14,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=4 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/8/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_du.dat new file mode 100644 index 0000000..b835103 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_du.dat @@ -0,0 +1,170 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # lls-CU(0) | RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,1,9,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,1,9,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=140 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_ru.dat new file mode 100644 index 0000000..7b01f32 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/config_file_o_ru.dat @@ -0,0 +1,191 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B + +####################################################################### +#Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,66,0,14,0,1,1,9,1 +PrbElemDl1=22,22,0,14,1,1,1,9,1 +PrbElemDl2=44,22,0,14,2,1,1,9,1 + +nPrbElemUl=1 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,66,0,14,0,1,1,9,1 +PrbElemUl1=22,22,0,14,1,1,1,9,1 +PrbElemUl2=44,22,0,14,2,1,1,9,1 +####################################################################### + +##Numerology +mu=3 #mmWave 120Khz Sub Carrier Spacing +ttiPeriod=125 # in us TTI period (mmWave default 125us) +nDLAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=27968160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-5] TDD priod e.g. DDDS 4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + #not used +#sSlotConfig4=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +#sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 +#9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +maxFrameId=99 # set for compatibility with O-RU + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +#antPrachC0=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC1=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 +#antPrachC2=./usecase/cat_a/mu3_100mhz/uliq00_prach_tst20.bin #CC0 +#antPrachC3=./usecase/cat_a/mu3_100mhz/uliq01_prach_tst20.bin #CC0 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +rachEanble=1 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=81 + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled +c_plane_vlan_tag=1 #VLAN Tag used for C-Plane +u_plane_vlan_tag=2 #VLAN Tag used for U-Plane + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 #in us TODO: update per RU implementation + #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages + +#Reception Window C-plane DL +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us + +#Reception Window C-plane UL +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us + +#Reception Window U-plane +T2a_min_up=25 #in us +T2a_max_up=70 #in us + +#Transmission Window +Ta3_min=20 #in us +Ta3_max=32 #in us + +########################################################### +##lls-CU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=70 +T1a_max_cp_dl=100 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=60 +T1a_max_cp_ul=70 + +#U-plane +##Transmission Window +T1a_min_up=35 +T1a_max_up=50 + +#Reception Window +Ta4_min=0 +Ta4_max=45 +########################################################### + diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/9/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu3_100mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_du.dat similarity index 82% rename from fhi_lib/app/usecase/mu3_100mhz/config_file_o_du.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_du.dat index fabd8a0..ee6b146 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_du.dat @@ -22,7 +22,7 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # lls-CU(0) | RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=3 #mmWave 120Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -68,23 +68,23 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -109,16 +109,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=50 #in us -T2a_max_cp_dl=140 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=50 #in us -T2a_max_cp_ul=140 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane T2a_min_up=25 #in us -T2a_max_up=140 #in us +T2a_max_up=70 #in us #Transmission Window Ta3_min=20 #in us diff --git a/fhi_lib/app/usecase/mu3_100mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_ru.dat similarity index 71% rename from fhi_lib/app/usecase/mu3_100mhz/config_file_o_ru.dat rename to fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_ru.dat index 3759c5f..a710a6e 100644 --- a/fhi_lib/app/usecase/mu3_100mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/config_file_o_ru.dat @@ -22,7 +22,7 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=3 #mmWave 120Khz Sub Carrier Spacing @@ -48,7 +48,7 @@ sSlotConfig3=0,2,2,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD #sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -68,40 +68,40 @@ ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app maxFrameId=99 # set for compatibility with O-RU -numSlots=40 #number of slots per IQ files -antC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antC15=./usecase/mu3_100mhz/ant_15.bin #CC3 - -antPrachC0=./usecase/mu3_100mhz/ant_0.bin #CC0 -antPrachC1=./usecase/mu3_100mhz/ant_1.bin #CC0 -antPrachC2=./usecase/mu3_100mhz/ant_2.bin #CC0 -antPrachC3=./usecase/mu3_100mhz/ant_3.bin #CC0 -antPrachC4=./usecase/mu3_100mhz/ant_4.bin #CC1 -antPrachC5=./usecase/mu3_100mhz/ant_5.bin #CC1 -antPrachC6=./usecase/mu3_100mhz/ant_6.bin #CC1 -antPrachC7=./usecase/mu3_100mhz/ant_7.bin #CC1 -antPrachC8=./usecase/mu3_100mhz/ant_8.bin #CC2 -antPrachC9=./usecase/mu3_100mhz/ant_9.bin #CC2 -antPrachC10=./usecase/mu3_100mhz/ant_10.bin #CC2 -antPrachC11=./usecase/mu3_100mhz/ant_11.bin #CC2 -antPrachC12=./usecase/mu3_100mhz/ant_12.bin #CC3 -antPrachC13=./usecase/mu3_100mhz/ant_13.bin #CC3 -antPrachC14=./usecase/mu3_100mhz/ant_14.bin #CC3 -antPrachC15=./usecase/mu3_100mhz/ant_15.bin #CC3 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 + +antPrachC0=./usecase/cat_a/mu3_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_a/mu3_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_a/mu3_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_a/mu3_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_a/mu3_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_a/mu3_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_a/mu3_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_a/mu3_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_a/mu3_100mhz/ant_8.bin #CC2 +antPrachC9=./usecase/cat_a/mu3_100mhz/ant_9.bin #CC2 +antPrachC10=./usecase/cat_a/mu3_100mhz/ant_10.bin #CC2 +antPrachC11=./usecase/cat_a/mu3_100mhz/ant_11.bin #CC2 +antPrachC12=./usecase/cat_a/mu3_100mhz/ant_12.bin #CC3 +antPrachC13=./usecase/cat_a/mu3_100mhz/ant_13.bin #CC3 +antPrachC14=./usecase/cat_a/mu3_100mhz/ant_14.bin #CC3 +antPrachC15=./usecase/cat_a/mu3_100mhz/ant_15.bin #CC3 rachEanble=1 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=81 @@ -126,16 +126,16 @@ Tadv_cp_dl=25 #in us TODO: update per RU implementation #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages #Reception Window C-plane DL -T2a_min_cp_dl=50 #in us -T2a_max_cp_dl=140 #in us +T2a_min_cp_dl=50 #in us +T2a_max_cp_dl=140 #in us #Reception Window C-plane UL -T2a_min_cp_ul=50 #in us -T2a_max_cp_ul=140 #in us +T2a_min_cp_ul=50 #in us +T2a_max_cp_ul=140 #in us #Reception Window U-plane T2a_min_up=25 #in us -T2a_max_up=140 #in us +T2a_max_up=70 #in us #Transmission Window Ta3_min=20 #in us diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_a/mu3_100mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_du.dat index d0ca6d6..395cc77 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_du.dat @@ -22,12 +22,12 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -57,12 +57,12 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id +ioCore=5 # core id ioWorker=0x2000000 # mask 0-no workers # Eth 0 @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -118,16 +118,18 @@ UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX anten rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 nPrbElemDl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,36,0,14,1,1,1,9,1 PrbElemDl1=36,36,0,14,2,1,1,9,1 PrbElemDl2=72,36,0,14,3,1,1,9,1 @@ -137,9 +139,20 @@ PrbElemDl5=180,36,0,14,6,1,1,9,1 PrbElemDl6=216,36,0,14,7,1,1,9,1 PrbElemDl7=252,21,0,14,8,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,3,0,0,9,1 +ExtBfwDl1=12,3,0,0,9,1 +ExtBfwDl2=12,3,0,0,9,1 +ExtBfwDl3=12,3,0,0,9,1 +ExtBfwDl4=12,3,0,0,9,1 +ExtBfwDl5=12,3,0,0,9,1 +ExtBfwDl6=12,3,0,0,9,1 +ExtBfwDl7=7,3,0,0,9,1 + nPrbElemUl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,36,0,14,1,1,1,9,1 PrbElemUl1=36,36,0,14,2,1,1,9,1 PrbElemUl2=72,36,0,14,3,1,1,9,1 @@ -149,6 +162,16 @@ PrbElemUl5=180,36,0,14,6,1,1,9,1 PrbElemUl6=216,36,0,14,7,1,1,9,1 PrbElemUl7=252,21,0,14,8,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,3,0,0,9,1 +ExtBfwUl1=12,3,0,0,9,1 +ExtBfwUl2=12,3,0,0,9,1 +ExtBfwUl3=12,3,0,0,9,1 +ExtBfwUl4=12,3,0,0,9,1 +ExtBfwUl5=12,3,0,0,9,1 +ExtBfwUl6=12,3,0,0,9,1 +ExtBfwUl7=7,3,0,0,9,1 ########################################################### ## control of IQ byte order @@ -181,8 +204,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -201,7 +224,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat index 55f0b1f..d149f4e 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/config_file_o_ru.dat @@ -22,12 +22,12 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -57,7 +57,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -75,7 +75,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -113,49 +113,51 @@ antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) -antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 nPrbElemDl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,36,0,14,1,1,1,9,1 PrbElemDl1=36,36,0,14,2,1,1,9,1 PrbElemDl2=72,36,0,14,3,1,1,9,1 @@ -167,7 +169,7 @@ PrbElemDl7=252,21,0,14,8,1,1,9,1 nPrbElemUl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,36,0,14,1,1,1,9,1 PrbElemUl1=36,36,0,14,2,1,1,9,1 PrbElemUl2=72,36,0,14,3,1,1,9,1 @@ -209,8 +211,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -229,7 +231,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/1/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat index 63fc5dd..2fa96ef 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_du.dat @@ -78,11 +78,11 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files -antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0 antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 @@ -127,17 +127,24 @@ srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,64,0,14,0,1,1,9,1 -PrbElemDl1=64,26,0,14,1,1,1,9,1 +PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095 +PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=32,2,0,0,9,1 +ExtBfwDl1=13,2,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,64,0,14,0,1,1,9,1 PrbElemUl1=64,26,0,14,1,1,1,9,1 - +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=64,2,0,0,9,1 +ExtBfwUl1=13,2,0,0,9,1 ########################################################### ## control of IQ byte order diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat index 7a9ed73..9a114c3 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -160,10 +160,10 @@ antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,64,0,14,0,1,1,9,1 -PrbElemDl1=64,26,0,14,1,1,1,9,1 +PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095 +PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -176,7 +176,7 @@ PrbElemUl1=64,26,0,14,1,1,1,9,1 ## control of IQ byte order iqswap=0 #do swap of IQ before send buffer to eth nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order -compression=0 # (1) compression enabled (0) compression disabled +compression=1 # (1) compression enabled (0) compression disabled ##Debug debugStop=1 #stop app on 1pps boundary (gps_second % 30) diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/101/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat index c28d96d..c2141f0 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat @@ -78,11 +78,11 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files -antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/16qam_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/16qam_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/16qam_ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/16qam_ant_3.bin #CC0 antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 @@ -127,16 +127,24 @@ srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,64,0,14,0,1,1,9,1 -PrbElemDl1=64,26,0,14,1,1,1,9,1 +PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095 +PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=32,2,0,0,9,1 +ExtBfwDl1=13,2,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,64,0,14,0,1,1,9,1 PrbElemUl1=64,26,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=64,2,0,0,9,1 +ExtBfwUl1=13,2,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_ru.dat index cb77c11..916a3d4 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -156,10 +156,10 @@ antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,64,0,14,0,1,1,9,1 -PrbElemDl1=64,26,0,14,1,1,1,9,1 +PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095 +PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_du.dat index b75fff9..31b7e0b 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_du.dat @@ -79,11 +79,11 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files -antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 -antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 -antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 -antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/qpsk_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/qpsk_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/qpsk_ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/qpsk_ant_3.bin #CC0 antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 @@ -130,16 +130,24 @@ srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,90,0,14,0,1,1,9,1 -PrbElemDl1=90,90,0,14,1,1,1,9,1 +PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095 +PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=30,3,0,0,9,1 +ExtBfwDl1=30,3,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,64,0,14,0,1,1,9,1 PrbElemUl1=64,26,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=30,3,0,0,9,1 +ExtBfwUl1=30,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_ru.dat index 12af582..123740c 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -159,10 +159,10 @@ antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=2 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask # weight base beams -PrbElemDl0=0,90,0,14,0,1,1,9,1 -PrbElemDl1=90,90,0,14,1,1,1,9,1 +PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095 +PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/103/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_du.dat index c7949af..a160231 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -152,6 +152,11 @@ nPrbElemDl=3 PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -159,6 +164,11 @@ nPrbElemUl=3 PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat index 99012a9..beee6f9 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/104/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_du.dat index 17c4b93..1697e3a 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_du.dat @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -154,6 +154,11 @@ nPrbElemDl=3 PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -161,6 +166,12 @@ nPrbElemUl=3 PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat index c3b4f78..53f0687 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_du.dat index 11b4c1a..31ca615 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_du.dat @@ -25,12 +25,12 @@ instanceId=0 # 0,1,2,... in case more than 1 application started on the same sys appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -60,12 +60,12 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id +ioCore=5 # core id ioWorker=0x2000000 # mask [0- no workers] # Eth 0 @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -138,7 +138,7 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) #DL PRB / % Used RBs UL PRB / % Used RBs @@ -146,24 +146,37 @@ srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 PrbElemDl3=90,30,0,14,3,1,1,9,1 PrbElemDl4=120,30,0,14,4,1,1,9,1 PrbElemDl5=150,30,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 +ExtBfwDl3=10,3,0,0,9,1 +ExtBfwDl4=10,3,0,0,9,1 +ExtBfwDl5=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 ########################################################### @@ -173,7 +186,7 @@ nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to compression=1 # (1) compression enabled (0) compression disabled ##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStop=1 #stop app on 1pps boundary (gps_second % 30) debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode @@ -197,8 +210,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -217,7 +230,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_ru.dat index daab55c..075a5b3 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/config_file_o_ru.dat @@ -25,12 +25,12 @@ instanceId=1 # 0,1,2,... in case more than 1 application started on the same sys appMode=1 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -60,7 +60,7 @@ sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -116,84 +116,84 @@ antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) -antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin #DL PRB / % Used RBs UL PRB / % Used RBs #66% 180 33% 90 ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 @@ -203,7 +203,7 @@ PrbElemDl5=150,30,0,14,5,1,1,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 @@ -216,7 +216,7 @@ nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to compression=1 # (1) compression enabled (0) compression disabled ##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStop=1 #stop app on 1pps boundary (gps_second % 30) debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode @@ -240,8 +240,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -260,7 +260,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/106/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_du.dat index e824e7b..0c37790 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -143,6 +143,11 @@ nPrbElemDl=3 PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -150,6 +155,11 @@ nPrbElemUl=3 PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_ru.dat index c9e6d4d..af78222 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/107/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_du.dat index a85a00d..98b723e 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -141,6 +141,11 @@ nPrbElemDl=3 PrbElemDl0=0,30,0,14,0,1,1,9,1 PrbElemDl1=30,30,0,14,1,1,1,9,1 PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -148,6 +153,11 @@ nPrbElemUl=3 PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_ru.dat index ada3b89..2b1d8f0 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/108/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_du.dat index 03dd810..a2f0b88 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -143,6 +143,14 @@ PrbElemDl2=60,30,0,14,2,1,1,9,1 PrbElemDl3=90,30,0,14,3,1,1,9,1 PrbElemDl4=120,30,0,14,4,1,1,9,1 PrbElemDl5=150,30,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 +ExtBfwDl3=10,3,0,0,9,1 +ExtBfwDl4=10,3,0,0,9,1 +ExtBfwDl5=10,3,0,0,9,1 nPrbElemUl=3 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -150,6 +158,11 @@ nPrbElemUl=3 PrbElemUl0=0,30,0,14,0,1,1,9,1 PrbElemUl1=30,30,0,14,1,1,1,9,1 PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_ru.dat index b7a6bd5..fd9b75c 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/109/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_du.dat new file mode 100644 index 0000000..669aab4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_du.dat @@ -0,0 +1,203 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 MAX MAX 33% 33% 4.25 1.725 0% DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask 0-no workers + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/64qam_ant_0.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/64qam_ant_1.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095 +PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=32,2,0,0,9,1 +ExtBfwDl1=13,2,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=64,2,0,0,9,1 +ExtBfwUl1=13,2,0,0,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_ru.dat new file mode 100644 index 0000000..07535db --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/config_file_o_ru.dat @@ -0,0 +1,229 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 MAX MAX 33% 33% 4.25 1.725 0% DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 # core id +ioWorker=0x800000000 # mask 0-no workers + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,64,0,14,0,1,4,3,1,5064,4095 +PrbElemDl1=64,26,0,14,1,1,4,3,1,5064,4095 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/111/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_du.dat new file mode 100644 index 0000000..3ec2f65 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_du.dat @@ -0,0 +1,204 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 MAX 16QAM 0.5 33% 90 33% 90 4.25 1.15 0% DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/16qam_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/16qam_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/16qam_ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/16qam_ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095 +PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=32,2,0,0,9,1 +ExtBfwDl1=13,2,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=64,2,0,0,9,1 +ExtBfwUl1=13,2,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_ru.dat new file mode 100644 index 0000000..ecababe --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/config_file_o_ru.dat @@ -0,0 +1,225 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 MAX 16QAM 0.5 33% 90 33% 90 4.25 1.15 0% DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 # core id + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095 +PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/112/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_du.dat new file mode 100644 index 0000000..3acd68a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_du.dat @@ -0,0 +1,207 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/qpsk_ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/qpsk_ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/qpsk_ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/qpsk_ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095 +PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=30,3,0,0,9,1 +ExtBfwDl1=30,3,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=30,3,0,0,9,1 +ExtBfwUl1=30,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_ru.dat new file mode 100644 index 0000000..8d13ad2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/config_file_o_ru.dat @@ -0,0 +1,228 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask +# weight base beams +PrbElemDl0=0,90,0,14,0,1,4,1,1,8192,4095 +PrbElemDl1=90,90,0,14,1,1,4,1,1,8192,4095 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,26,0,14,1,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/113/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_du.dat new file mode 100644 index 0000000..aed7f0e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_du.dat @@ -0,0 +1,228 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 16 8 MAX MAX 33% 90 33% 90 17 6.9 0% DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_ru.dat new file mode 100644 index 0000000..a627c5e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/config_file_o_ru.dat @@ -0,0 +1,262 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 8T8R 100 4 2 64QAM 0.5 16QAM 0.5 66% 180 33% 90 3.425 1.15 DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/114/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_du.dat new file mode 100644 index 0000000..6232d88 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_du.dat @@ -0,0 +1,231 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 16 8 MAX 16QAM 0.5 33% 90 33% 90 17 4.6 DU + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_ru.dat new file mode 100644 index 0000000..152c925 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/config_file_o_ru.dat @@ -0,0 +1,261 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 16 8 MAX 16QAM 0.5 33% 90 33% 90 17 4.6 DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/115/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_du.dat new file mode 100644 index 0000000..1821c6c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_du.dat @@ -0,0 +1,236 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 16 8 64QAM 0.5 16QAM 0.5 66% 180 33% 90 13.7 4.6 0% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +PrbElemDl3=90,30,0,14,3,1,1,9,1 +PrbElemDl4=120,30,0,14,4,1,1,9,1 +PrbElemDl5=150,30,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 +ExtBfwDl3=10,3,0,0,9,1 +ExtBfwDl4=10,3,0,0,9,1 +ExtBfwDl5=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_ru.dat new file mode 100644 index 0000000..4b8d207 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/config_file_o_ru.dat @@ -0,0 +1,266 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 16 8 64QAM 0.5 16QAM 0.5 66% 180 33% 90 13.7 4.6 0% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +PrbElemDl3=90,30,0,14,3,1,1,9,1 +PrbElemDl4=120,30,0,14,4,1,1,9,1 +PrbElemDl5=150,30,0,14,5,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/116/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_du.dat new file mode 100644 index 0000000..bca0aec --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_du.dat @@ -0,0 +1,219 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 MAX MAX 33% 90 33% 90 8.5 3.45 0% DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_ru.dat new file mode 100644 index 0000000..64c7256 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/config_file_o_ru.dat @@ -0,0 +1,261 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 MAX MAX 33% 90 33% 90 8.5 3.45 0% DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/117/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_du.dat new file mode 100644 index 0000000..a182ecd --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_du.dat @@ -0,0 +1,217 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 MAX 16QAM 0.5 33% 90 33% 90 8.5 2.3 DU + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_ru.dat new file mode 100644 index 0000000..8af8306 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/config_file_o_ru.dat @@ -0,0 +1,261 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 MAX 16QAM 0.5 33% 90 33% 90 8.5 2.3 DU + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/118/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_du.dat new file mode 100644 index 0000000..fd71303 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_du.dat @@ -0,0 +1,222 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 64QAM 0.5 16QAM 0.5 66% 180 33% 90 6.85 2.3 0% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +PrbElemDl3=90,30,0,14,3,1,1,9,1 +PrbElemDl4=120,30,0,14,4,1,1,9,1 +PrbElemDl5=150,30,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=10,3,0,0,9,1 +ExtBfwDl1=10,3,0,0,9,1 +ExtBfwDl2=10,3,0,0,9,1 +ExtBfwDl3=10,3,0,0,9,1 +ExtBfwDl4=10,3,0,0,9,1 +ExtBfwDl5=10,3,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=10,3,0,0,9,1 +ExtBfwUl1=10,3,0,0,9,1 +ExtBfwUl2=10,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_ru.dat new file mode 100644 index 0000000..da1a8b3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/config_file_o_ru.dat @@ -0,0 +1,262 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD 1 64T64R 100 8 4 64QAM 0.5 16QAM 0.5 66% 180 33% 90 6.85 2.3 0% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,30,0,14,0,1,1,9,1 +PrbElemDl1=30,30,0,14,1,1,1,9,1 +PrbElemDl2=60,30,0,14,2,1,1,9,1 +PrbElemDl3=90,30,0,14,3,1,1,9,1 +PrbElemDl4=120,30,0,14,4,1,1,9,1 +PrbElemDl5=150,30,0,14,5,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,30,0,14,0,1,1,9,1 +PrbElemUl1=30,30,0,14,1,1,1,9,1 +PrbElemUl2=60,30,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/119/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_du.dat index 9e35624..90f1fab 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_ru.dat index aeb9492..1031aea 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/2/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_du.dat index 6cee290..04bd7b4 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,6 +133,12 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=4 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -141,6 +147,12 @@ PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_ru.dat index d2ca4d3..6b0db13 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/config_file_o_ru.dat @@ -76,7 +76,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/201/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_du.dat index 87ddd75..8f05147 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -152,6 +152,14 @@ PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 PrbElemDl4=192,48,0,14,5,1,1,9,1 PrbElemDl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 nPrbElemUl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -162,6 +170,14 @@ PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 PrbElemUl4=192,48,0,14,5,1,1,9,1 PrbElemUl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_ru.dat index 2e0196d..a82daec 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/202/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_du.dat index 8a83298..38e4f73 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_du.dat @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -151,12 +151,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_ru.dat index 528a625..def1a53 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/203/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_du.dat index 471a89a..8369d0d 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_du.dat @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -151,12 +151,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_ru.dat index 156c6fe..f998ef7 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/204/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_du.dat index 4efdade..f3ef96c 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -153,12 +153,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_ru.dat index 5b2f595..88b8476 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/205/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_du.dat index aabd141..c6d502e 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -153,6 +153,12 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=4 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -161,6 +167,12 @@ PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_ru.dat index 4ce24b4..6eef136 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/206/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_du.dat index 484975d..a619b7e 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_du.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,6 +133,12 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=4 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -141,6 +147,12 @@ PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_ru.dat index 77121e7..715ab9c 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/config_file_o_ru.dat @@ -76,7 +76,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/211/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_du.dat index 86c4f81..3616b8b 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -152,6 +152,14 @@ PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 PrbElemDl4=192,48,0,14,5,1,1,9,1 PrbElemDl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 nPrbElemUl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -162,6 +170,14 @@ PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 PrbElemUl4=192,48,0,14,5,1,1,9,1 PrbElemUl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_ru.dat index 5be35b3..73297e7 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/212/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_du.dat index c6107db..65b7ec2 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_du.dat @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -151,12 +151,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### @@ -173,7 +183,7 @@ bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardw CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled ##O-RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU +totalBFWeights=64 # Total number of Beamforming Weights on RU Tadv_cp_dl=25 # in us # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_ru.dat index f1d9783..9d85f04 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -217,7 +217,7 @@ bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardw CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled ##O-RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU +totalBFWeights=64 # Total number of Beamforming Weights on RU Tadv_cp_dl=25 # in us # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/213/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_du.dat index df29394..68b8ab5 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_du.dat @@ -80,7 +80,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -151,12 +151,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### @@ -173,7 +183,7 @@ bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardw CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled ##O-RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU +totalBFWeights=64 # Total number of Beamforming Weights on RU Tadv_cp_dl=25 # in us # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_ru.dat index 61a678c..25a2865 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/config_file_o_ru.dat @@ -78,7 +78,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -217,7 +217,7 @@ bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardw CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled ##O-RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU +totalBFWeights=64 # Total number of Beamforming Weights on RU Tadv_cp_dl=25 # in us # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/214/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_du.dat index 4641351..e56d192 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -153,12 +153,22 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_ru.dat index 87a68b5..cfecdaf 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/215/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_du.dat index ec634aa..badad92 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_du.dat @@ -79,7 +79,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -153,6 +153,12 @@ PrbElemDl0=0,48,0,14,1,1,1,9,1 PrbElemDl1=48,48,0,14,2,1,1,9,1 PrbElemDl2=96,48,0,14,3,1,1,9,1 PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 nPrbElemUl=4 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -161,6 +167,12 @@ PrbElemUl0=0,48,0,14,1,1,1,9,1 PrbElemUl1=48,48,0,14,2,1,1,9,1 PrbElemUl2=96,48,0,14,3,1,1,9,1 PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_ru.dat index 604eca1..84aaebb 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/config_file_o_ru.dat @@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/216/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_du.dat new file mode 100644 index 0000000..140e216 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_du.dat @@ -0,0 +1,212 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_ru.dat new file mode 100644 index 0000000..0e02bd3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/config_file_o_ru.dat @@ -0,0 +1,229 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/221/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_du.dat new file mode 100644 index 0000000..e1aea1f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_du.dat @@ -0,0 +1,237 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +PrbElemDl4=192,48,0,14,5,1,1,9,1 +PrbElemDl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +PrbElemUl4=192,48,0,14,5,1,1,9,1 +PrbElemUl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_ru.dat new file mode 100644 index 0000000..da111a9 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/config_file_o_ru.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +PrbElemDl4=192,48,0,14,5,1,1,9,1 +PrbElemDl5=240,33,0,14,6,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +PrbElemUl4=192,48,0,14,5,1,1,9,1 +PrbElemUl5=240,33,0,14,6,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/222/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_du.dat new file mode 100644 index 0000000..6b33fe0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_du.dat @@ -0,0 +1,226 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_ru.dat new file mode 100644 index 0000000..12a6ff3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/config_file_o_ru.dat @@ -0,0 +1,260 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/223/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_du.dat new file mode 100644 index 0000000..b6bee4f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_du.dat @@ -0,0 +1,226 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_ru.dat new file mode 100644 index 0000000..4a53408 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/config_file_o_ru.dat @@ -0,0 +1,260 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/224/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_du.dat new file mode 100644 index 0000000..385ab3b --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_du.dat @@ -0,0 +1,228 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_ru.dat new file mode 100644 index 0000000..2e5a82a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/config_file_o_ru.dat @@ -0,0 +1,262 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/225/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_du.dat new file mode 100644 index 0000000..1fec4ba --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_du.dat @@ -0,0 +1,232 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_ru.dat new file mode 100644 index 0000000..aa63777 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/config_file_o_ru.dat @@ -0,0 +1,264 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/226/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_du.dat new file mode 100644 index 0000000..f0bb6c7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_du.dat @@ -0,0 +1,212 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_ru.dat new file mode 100644 index 0000000..2008a8f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/config_file_o_ru.dat @@ -0,0 +1,229 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 8T8R 100 8 4 70.3% 192 2304 70.0% 191 2292 new added 70% with 8T8R + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=8 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/231/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_du.dat new file mode 100644 index 0000000..9a1d176 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_du.dat @@ -0,0 +1,237 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +PrbElemDl4=192,48,0,14,5,1,1,9,1 +PrbElemDl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +PrbElemUl4=192,48,0,14,5,1,1,9,1 +PrbElemUl5=240,33,0,14,6,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_ru.dat new file mode 100644 index 0000000..126046e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/config_file_o_ru.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:5 1 64T64R 100 16 8 100.0% 273 3276 100.0% 273 3276 1 peak + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +PrbElemDl4=192,48,0,14,5,1,1,9,1 +PrbElemDl5=240,33,0,14,6,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +PrbElemUl4=192,48,0,14,5,1,1,9,1 +PrbElemUl5=240,33,0,14,6,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/232/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_du.dat new file mode 100644 index 0000000..097bc50 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_du.dat @@ -0,0 +1,226 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_ru.dat new file mode 100644 index 0000000..e16cd9c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/config_file_o_ru.dat @@ -0,0 +1,260 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 35% center + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/233/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_du.dat new file mode 100644 index 0000000..59fa3d1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_du.dat @@ -0,0 +1,226 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_ru.dat new file mode 100644 index 0000000..5086e26 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/config_file_o_ru.dat @@ -0,0 +1,260 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 16 4 70.3% 192 2304 35.0% 96 1152 45% mid + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/234/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_du.dat new file mode 100644 index 0000000..aab708b --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_du.dat @@ -0,0 +1,228 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_ru.dat new file mode 100644 index 0000000..d8014bf --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/config_file_o_ru.dat @@ -0,0 +1,262 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 4 1 70.3% 192 2304 35.0% 96 1152 20% edge + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/235/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_du.dat new file mode 100644 index 0000000..1a094fb --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_du.dat @@ -0,0 +1,232 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_ru.dat new file mode 100644 index 0000000..ad2e573 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/config_file_o_ru.dat @@ -0,0 +1,264 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#TDD DDDSUUDDDD: S it's 6:4:4 1 64T64R 100 8 4 70.3% 192 2304 70.0% 191 2292 70% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#33% 90 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=96,48,0,14,3,1,1,9,1 +PrbElemUl3=144,48,0,14,4,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/236/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_du.dat new file mode 100644 index 0000000..2fad5c7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_du.dat @@ -0,0 +1,230 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask 0-no workers + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=8 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,36,0,14,1,1,1,9,1 +PrbElemDl1=36,36,0,14,2,1,1,9,1 +PrbElemDl2=72,36,0,14,3,1,1,9,1 +PrbElemDl3=108,36,0,14,4,1,1,9,1 +PrbElemDl4=144,36,0,14,5,1,1,9,1 +PrbElemDl5=180,36,0,14,6,1,1,9,1 +PrbElemDl6=216,36,0,14,7,1,1,9,1 +PrbElemDl7=252,21,0,14,8,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,3,0,0,9,1 +ExtBfwDl1=12,3,0,0,9,1 +ExtBfwDl2=12,3,0,0,9,1 +ExtBfwDl3=12,3,0,0,9,1 +ExtBfwDl4=12,3,0,0,9,1 +ExtBfwDl5=12,3,0,0,9,1 +ExtBfwDl6=12,3,0,0,9,1 +ExtBfwDl7=7,3,0,0,9,1 + +nPrbElemUl=8 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,36,0,14,1,1,1,9,1 +PrbElemUl1=36,36,0,14,2,1,1,9,1 +PrbElemUl2=72,36,0,14,3,1,1,9,1 +PrbElemUl3=108,36,0,14,4,1,1,9,1 +PrbElemUl4=144,36,0,14,5,1,1,9,1 +PrbElemUl5=180,36,0,14,6,1,1,9,1 +PrbElemUl6=216,36,0,14,7,1,1,9,1 +PrbElemUl7=252,21,0,14,8,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,3,0,0,9,1 +ExtBfwUl1=12,3,0,0,9,1 +ExtBfwUl2=12,3,0,0,9,1 +ExtBfwUl3=12,3,0,0,9,1 +ExtBfwUl4=12,3,0,0,9,1 +ExtBfwUl5=12,3,0,0,9,1 +ExtBfwUl6=12,3,0,0,9,1 +ExtBfwUl7=7,3,0,0,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_ru.dat new file mode 100644 index 0000000..28424d5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/config_file_o_ru.dat @@ -0,0 +1,237 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 + +nPrbElemDl=8 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,36,0,14,1,1,1,9,1 +PrbElemDl1=36,36,0,14,2,1,1,9,1 +PrbElemDl2=72,36,0,14,3,1,1,9,1 +PrbElemDl3=108,36,0,14,4,1,1,9,1 +PrbElemDl4=144,36,0,14,5,1,1,9,1 +PrbElemDl5=180,36,0,14,6,1,1,9,1 +PrbElemDl6=216,36,0,14,7,1,1,9,1 +PrbElemDl7=252,21,0,14,8,1,1,9,1 + +nPrbElemUl=8 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,36,0,14,1,1,1,9,1 +PrbElemUl1=36,36,0,14,2,1,1,9,1 +PrbElemUl2=72,36,0,14,3,1,1,9,1 +PrbElemUl3=108,36,0,14,4,1,1,9,1 +PrbElemUl4=144,36,0,14,5,1,1,9,1 +PrbElemUl5=180,36,0,14,6,1,1,9,1 +PrbElemUl6=216,36,0,14,7,1,1,9,1 +PrbElemUl7=252,21,0,14,8,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_du.dat index 3d518d5..c375dd4 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_du.dat @@ -16,19 +16,22 @@ # #******************************************************************************/ -#TDD DDDFU 1 64T64R 100 16 8 100% 180 100% +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -46,34 +49,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id -ioWorker=0x2000000 # mask [0- no workers] - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -131,32 +119,51 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS -srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,48,0,14,0,1,1,9,1 PrbElemDl1=48,48,0,14,1,1,1,9,1 PrbElemDl2=96,48,0,14,2,1,1,9,1 PrbElemDl3=144,48,0,14,3,1,1,9,1 PrbElemDl4=192,48,0,14,4,1,1,9,1 PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 nPrbElemUl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,48,0,14,0,1,1,9,1 PrbElemUl1=48,48,0,14,1,1,1,9,1 PrbElemUl2=96,48,0,14,2,1,1,9,1 PrbElemUl3=144,48,0,14,3,1,1,9,1 PrbElemUl4=192,48,0,14,4,1,1,9,1 PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -166,7 +173,7 @@ nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to compression=1 # (1) compression enabled (0) compression disabled ##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStop=1 #stop app on 1pps boundary (gps_second % 30) debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode @@ -190,8 +197,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -210,7 +217,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_ru.dat index c3d4e70..0dfd4bd 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/config_file_o_ru.dat @@ -16,19 +16,21 @@ # #******************************************************************************/ -#TDD DDDFU 1 64T64R 100 16 8 100% 180 100% +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system appMode=1 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -46,32 +48,21 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=15 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -109,100 +100,119 @@ antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS -srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) - -antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin #DL PRB / % Used RBs UL PRB / % Used RBs #66% 180 33% 90 ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used nPrbElemDl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemDl0=0,48,0,14,0,1,1,9,1 PrbElemDl1=48,48,0,14,1,1,1,9,1 PrbElemDl2=96,48,0,14,2,1,1,9,1 PrbElemDl3=144,48,0,14,3,1,1,9,1 PrbElemDl4=192,48,0,14,4,1,1,9,1 PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 nPrbElemUl=6 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams +# weight base beams PrbElemUl0=0,48,0,14,0,1,1,9,1 PrbElemUl1=48,48,0,14,1,1,1,9,1 PrbElemUl2=96,48,0,14,2,1,1,9,1 PrbElemUl3=144,48,0,14,3,1,1,9,1 PrbElemUl4=192,48,0,14,4,1,1,9,1 PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -212,7 +222,7 @@ nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to compression=1 # (1) compression enabled (0) compression disabled ##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) +debugStop=1 #stop app on 1pps boundary (gps_second % 30) debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode @@ -236,8 +246,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -256,7 +266,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du_icx.cfg new file mode 100644 index 0000000..df51878 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_du_icx.cfg @@ -0,0 +1,59 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_du.dat index 32f65a7..752ea96 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_du.dat @@ -18,19 +18,19 @@ #Peak #4% -#TDD DDFU 1 64T64R 100 8 8 65% 178 65% 178 +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,34 +48,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id -ioWorker=0x2000000 # mask [0- no workers] - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,28 +118,35 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=6 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -188,8 +180,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -208,7 +200,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_ru.dat index 58bff2c..af91417 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/config_file_o_ru.dat @@ -18,19 +18,19 @@ #Peak #4% -#TDD DDFU 1 64T64R 100 8 8 65% 178 65% 178 +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system appMode=1 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,11 +48,11 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single @@ -60,20 +60,7 @@ MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protoco Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=15 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -178,29 +165,32 @@ antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin - -#DL PRB / % Used RBs UL PRB / % Used RBs -#66% 180 33% 90 - ########################################################### ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=4 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -234,8 +224,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -254,7 +244,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du.cfg new file mode 100644 index 0000000..d7b23b7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du.cfg @@ -0,0 +1,54 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du_icx.cfg new file mode 100644 index 0000000..c46970e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_du_icx.cfg @@ -0,0 +1,54 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_ru.cfg new file mode 100644 index 0000000..78ef5d1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/302/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_du.dat index 6589c9a..7e3eb43 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_du.dat @@ -16,21 +16,22 @@ # #******************************************************************************/ -#NC +#NC #12% -#TDD DDDFU 1 64T64R 100 16 4 65% 178 65% 178 +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,34 +49,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id -ioWorker=0x2000000 # mask [0- no workers] - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,28 +119,35 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=6 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -188,8 +181,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -208,7 +201,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_ru.dat index f2f82c7..d229a17 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/config_file_o_ru.dat @@ -18,7 +18,7 @@ #NC #12% -#TDD DDDFU 1 64T64R 100 16 4 65% 178 65% 178 +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system @@ -48,32 +48,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=15 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -178,29 +165,32 @@ antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin - -#DL PRB / % Used RBs UL PRB / % Used RBs -#66% 180 33% 90 - ########################################################### ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=4 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -234,8 +224,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -254,7 +244,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du.cfg new file mode 100644 index 0000000..5eb0082 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du_icx.cfg new file mode 100644 index 0000000..a8f6be4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/303/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_du.dat index 603f264..6b43cb4 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_du.dat @@ -18,19 +18,19 @@ #MC #20% -#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,19 +48,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id +ioCore=5 # core id ioWorker=0x2000000 # mask [0- no workers] # Eth 0 @@ -75,7 +75,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,28 +133,31 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used - -nPrbElemDl=4 +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=6 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 ########################################################### @@ -188,8 +191,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -208,7 +211,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_ru.dat index 5fd5ae5..4e8e300 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/config_file_o_ru.dat @@ -18,7 +18,7 @@ #MC #20% -#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system @@ -48,11 +48,11 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single @@ -73,7 +73,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -186,21 +186,25 @@ antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=4 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 ########################################################### @@ -234,8 +238,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -254,7 +258,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/304/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_du.dat index 3dc2d88..763aae0 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_du.dat @@ -18,19 +18,20 @@ #MEC #28% -#TDD DDDFU 1 64T64R 100 4 2 65% 178 65% 178 +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,34 +49,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id -ioWorker=0x2000000 # mask [0- no workers] - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,28 +119,32 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=6 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 ########################################################### @@ -188,8 +178,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -208,7 +198,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_ru.dat index 57a9a23..f337c32 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/config_file_o_ru.dat @@ -18,19 +18,19 @@ #MEC #28% -#TDD DDDFU 1 64T64R 100 4 2 65% 178 65% 178 +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system appMode=1 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,32 +48,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=15 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -114,90 +101,97 @@ prachConfigIndex=189 srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) -antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin -antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin -antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin -antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin -antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin -antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin -antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin -antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin -antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=4 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -231,8 +225,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -251,7 +245,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/305/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_du.dat index 2bd7abf..ab6d63f 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_du.dat @@ -18,19 +18,21 @@ #EC #36% -#TDD DDDFU 1 64T64R 100 2 1 65% 178 65% 178 +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + + # This is simple configuration file. Use '#' sign for comments instanceId=0 # 0,1,2,... in case more than 1 application started on the same system appMode=0 # O-DU(0) | O-RU(1) xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) -antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B -antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R #UEs -muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources DlLayersPerUe=1 #number of RX anntennas on DL UE side UlLayersPerUe=1 #number of TX anntennas on UL UE side @@ -48,34 +50,19 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=5 # core id -ioWorker=0x2000000 # mask [0- no workers] - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -133,28 +120,35 @@ UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX ante rachEanble=0 # Enable (1)| disable (0) PRACH configuration prachConfigIndex=189 -srsEanble=1 # Enable (1)| disable (0) SRS +srsEanble=1 # Enable (1)| disable (0) SRS srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=6 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -188,8 +182,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -208,7 +202,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_ru.dat index 1343a2c..2694156 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/config_file_o_ru.dat @@ -18,7 +18,7 @@ #EC #36% -#TDD DDDFU 1 64T64R 100 2 1 65% 178 65% 178 +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% # This is simple configuration file. Use '#' sign for comments instanceId=1 # 0,1,2,... in case more than 1 application started on the same system @@ -48,11 +48,11 @@ nDLFftSize=4096 nULFftSize=4096 nFrameDuplexType=1 # 0 - FDD 1 - TDD -nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD -sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single @@ -60,20 +60,7 @@ MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protoco Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 -ioCore=15 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -# Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -178,26 +165,32 @@ antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin - ########################################################### ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used -nPrbElemDl=4 +nPrbElemDl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,48,0,14,0,1,1,9,1 -PrbElemDl1=48,48,0,14,1,1,1,9,1 -PrbElemDl2=96,48,0,14,2,1,1,9,1 -PrbElemDl3=144,34,0,14,3,1,1,9,1 - -nPrbElemUl=4 +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,48,0,14,0,1,1,9,1 -PrbElemUl1=48,48,0,14,1,1,1,9,1 -PrbElemUl2=96,48,0,14,2,1,1,9,1 -PrbElemUl3=144,34,0,14,3,1,1,9,1 +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 ########################################################### @@ -231,8 +224,8 @@ T2a_min_up=71 # 71.35in us T2a_max_up=428 # 428.12us #Transmission Window -Ta3_min=20 # in us -Ta3_max=32 # in us +Ta3_min=20 # in us +Ta3_max=32 # in us ########################################################### ##O-DU Settings @@ -251,7 +244,7 @@ T1a_min_up=96 #71 + 25 us T1a_max_up=196 #71 + 25 us #Reception Window -Ta4_min=0 # in us -Ta4_max=75 # in us +Ta4_min=0 # in us +Ta4_max=75 # in us ########################################################### diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du.cfg new file mode 100644 index 0000000..5eb0082 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du_icx.cfg new file mode 100644 index 0000000..a8f6be4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/306/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_du.dat new file mode 100644 index 0000000..d976fbd --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_ru.dat new file mode 100644 index 0000000..58f09f7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/config_file_o_ru.dat @@ -0,0 +1,272 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du.cfg new file mode 100644 index 0000000..b741686 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs +#oXuRxqNumber=48 # number of HW RX Queues per VF (should >= RX IQ stream per VF) +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/311/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_du.dat new file mode 100644 index 0000000..fafc862 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_du.dat @@ -0,0 +1,206 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_ru.dat new file mode 100644 index 0000000..61282ce --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/312/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_du.dat new file mode 100644 index 0000000..a35ca5e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_du.dat @@ -0,0 +1,207 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_ru.dat new file mode 100644 index 0000000..5735405 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/313/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_du.dat new file mode 100644 index 0000000..cf9dd6e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_du.dat @@ -0,0 +1,217 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_ru.dat new file mode 100644 index 0000000..cee1913 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/config_file_o_ru.dat @@ -0,0 +1,264 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/314/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_du.dat new file mode 100644 index 0000000..788735e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_du.dat @@ -0,0 +1,204 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_ru.dat new file mode 100644 index 0000000..90fd63f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/config_file_o_ru.dat @@ -0,0 +1,251 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/315/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_du.dat new file mode 100644 index 0000000..bc19617 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_du.dat @@ -0,0 +1,208 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_ru.dat new file mode 100644 index 0000000..7d97cb4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du_icx.cfg new file mode 100644 index 0000000..0248866 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_du_icx.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/316/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du.dat new file mode 100644 index 0000000..f63a17f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du.dat @@ -0,0 +1,236 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du_tst377.dat new file mode 100644 index 0000000..a2b81a5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_du_tst377.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru.dat new file mode 100644 index 0000000..04ea30c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru.dat @@ -0,0 +1,288 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377.dat new file mode 100644 index 0000000..4d21c4f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377_dynamic.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377_dynamic.dat new file mode 100644 index 0000000..c2bd27d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_o_ru_tst377_dynamic.dat @@ -0,0 +1,292 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +puschMaskEnable=1 # Enable (1)| disable (0) PUSCH Mask +puschMaskSlot=3 # (num mode Frame) slots will not transfer PUSCH channel (def: sym 13) + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,64,0,14,0,1,1,9,1 +PrbElemUl1=64,36,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_du.dat new file mode 100644 index 0000000..50e08af --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_ru.dat new file mode 100644 index 0000000..4fb9aa4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du.dat new file mode 100644 index 0000000..0220c92 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du.dat @@ -0,0 +1,247 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du_tst376.dat new file mode 100644 index 0000000..86f752c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_du_tst376.dat @@ -0,0 +1,248 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru.dat new file mode 100644 index 0000000..e029b0e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru.dat @@ -0,0 +1,297 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376.dat new file mode 100644 index 0000000..a3edf84 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376.dat @@ -0,0 +1,298 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376_dynamic.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376_dynamic.dat new file mode 100644 index 0000000..332fe8f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_o_ru_tst376_dynamic.dat @@ -0,0 +1,301 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +puschMaskEnable=1 # Enable (1)| disable (0) PUSCH Mask +puschMaskSlot=3 # (num mode Frame) slots will not transfer PUSCH channel (def: sym 13) + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,46,0,14,0,1,1,9,1 +PrbElemUl1=46,46,0,14,1,1,1,9,1 +PrbElemUl2=92,46,0,14,2,1,1,9,1 +PrbElemUl3=138,46,0,14,3,1,1,9,1 +PrbElemUl4=184,46,0,14,4,1,1,9,1 +PrbElemUl5=230,43,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg new file mode 100644 index 0000000..29bacc1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du.cfg @@ -0,0 +1,65 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=22 # core id +ioWorker=0xC00000800000 # mask [0- no workers] + +dpdkMemorySize=18432 + +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs +#oXuRxqNumber=41 # number of HW RX Queues per VF (should >= RX IQ streams per VF) +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg new file mode 100644 index 0000000..c99d2d0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 + +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_dynamic.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_dynamic.cfg new file mode 100644 index 0000000..5b957bb --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3301/usecase_ru_dynamic.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376_dynamic.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377_dynamic.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377_dynamic.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du.dat new file mode 100644 index 0000000..6007dd5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du.dat @@ -0,0 +1,236 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du_tst377.dat new file mode 100644 index 0000000..83e136e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_du_tst377.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru.dat new file mode 100644 index 0000000..f53a3df --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru.dat @@ -0,0 +1,288 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru_tst377.dat new file mode 100644 index 0000000..a55c524 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_o_ru_tst377.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_du.dat new file mode 100644 index 0000000..ee44aed --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_ru.dat new file mode 100644 index 0000000..f3f2dc8 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du.dat new file mode 100644 index 0000000..9d6b5b7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du.dat @@ -0,0 +1,247 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du_tst376.dat new file mode 100644 index 0000000..ab287c0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_du_tst376.dat @@ -0,0 +1,248 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru.dat new file mode 100644 index 0000000..8d676a0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru.dat @@ -0,0 +1,297 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru_tst376.dat new file mode 100644 index 0000000..2418048 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_o_ru_tst376.dat @@ -0,0 +1,298 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du.cfg new file mode 100644 index 0000000..5b92998 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du.cfg @@ -0,0 +1,64 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=22 # core id +ioWorker=0xC00000800000 # mask [0- no workers] + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs +#oXuRxqNumber=49 # number of HW RX Queues per VF (should >= RX IQ stream per VF) +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru.cfg new file mode 100644 index 0000000..9d02494 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3311/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du.dat new file mode 100644 index 0000000..d37454a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du.dat @@ -0,0 +1,236 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du_tst377.dat new file mode 100644 index 0000000..5364ece --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_du_tst377.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru.dat new file mode 100644 index 0000000..c42caec --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru.dat @@ -0,0 +1,288 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru_tst377.dat new file mode 100644 index 0000000..9e50500 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_o_ru_tst377.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_du.dat new file mode 100644 index 0000000..92c8e3d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_ru.dat new file mode 100644 index 0000000..cb9411c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du.dat new file mode 100644 index 0000000..b4327a2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du.dat @@ -0,0 +1,247 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du_tst376.dat new file mode 100644 index 0000000..94876e3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_du_tst376.dat @@ -0,0 +1,248 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru.dat new file mode 100644 index 0000000..c156347 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru.dat @@ -0,0 +1,297 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru_tst376.dat new file mode 100644 index 0000000..364f411 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_o_ru_tst376.dat @@ -0,0 +1,298 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du.cfg new file mode 100644 index 0000000..bf76a2f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du.cfg @@ -0,0 +1,64 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=22 # core id +ioWorker=0xC00000800000 # mask [0- no workers] + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru.cfg new file mode 100644 index 0000000..9d02494 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3321/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du.dat new file mode 100644 index 0000000..036d629 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du.dat @@ -0,0 +1,236 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU 1 64T64R 100 8 4 65% 178 65% 178 + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du_tst377.dat new file mode 100644 index 0000000..d1e9642 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_du_tst377.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru.dat new file mode 100644 index 0000000..6fd054e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru.dat @@ -0,0 +1,288 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru_tst377.dat new file mode 100644 index 0000000..21a992e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_o_ru_tst377.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_du.dat new file mode 100644 index 0000000..d8f320c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_ru.dat new file mode 100644 index 0000000..b08fde6 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du.dat new file mode 100644 index 0000000..98821a4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du.dat @@ -0,0 +1,247 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du_tst376.dat new file mode 100644 index 0000000..23a9a7e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_du_tst376.dat @@ -0,0 +1,248 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru.dat new file mode 100644 index 0000000..b5a2502 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru.dat @@ -0,0 +1,297 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru_tst376.dat new file mode 100644 index 0000000..ed99005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_o_ru_tst376.dat @@ -0,0 +1,298 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 +#PrbElemSrs1=136,137,0,14,0,0,0,16,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du.cfg new file mode 100644 index 0000000..c9b501f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du.cfg @@ -0,0 +1,64 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=22 # core id +ioWorker=0xC00000800000 # mask [0- no workers] + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru.cfg new file mode 100644 index 0000000..9d02494 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3331/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du.dat new file mode 100644 index 0000000..b10a961 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du_tst377.dat new file mode 100644 index 0000000..b10a961 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_du_tst377.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru.dat new file mode 100644 index 0000000..0cc7dd4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru_tst377.dat new file mode 100644 index 0000000..e989e85 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_o_ru_tst377.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_du.dat new file mode 100644 index 0000000..50e08af --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_ru.dat new file mode 100644 index 0000000..4fb9aa4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du.dat new file mode 100644 index 0000000..5033f5c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du_tst376.dat new file mode 100644 index 0000000..5033f5c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_du_tst376.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru.dat new file mode 100644 index 0000000..c67c653 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru_tst376.dat new file mode 100644 index 0000000..67e96a1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_o_ru_tst376.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du.cfg new file mode 100644 index 0000000..4dd5356 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du.cfg @@ -0,0 +1,65 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0xE00000C00000 # mask [0- no workers] +dpdkMemorySize=8192 + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru.cfg new file mode 100644 index 0000000..84cdcc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3501/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du.dat new file mode 100644 index 0000000..33f6e6d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du_tst377.dat new file mode 100644 index 0000000..33f6e6d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_du_tst377.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru.dat new file mode 100644 index 0000000..d661b5f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru_tst377.dat new file mode 100644 index 0000000..9fa1310 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_o_ru_tst377.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_du.dat new file mode 100644 index 0000000..50e08af --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_ru.dat new file mode 100644 index 0000000..4fb9aa4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du.dat new file mode 100644 index 0000000..4f3b677 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du_tst376.dat new file mode 100644 index 0000000..4f3b677 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_du_tst376.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru.dat new file mode 100644 index 0000000..7305818 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru_tst376.dat new file mode 100644 index 0000000..1a8c62c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_o_ru_tst376.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du.cfg new file mode 100644 index 0000000..b50a11c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du.cfg @@ -0,0 +1,64 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0xE00000C00000 # mask [0- no workers] + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru.cfg new file mode 100644 index 0000000..84cdcc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3511/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du.dat new file mode 100644 index 0000000..a682dc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du_tst377.dat new file mode 100644 index 0000000..a682dc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_du_tst377.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru.dat new file mode 100644 index 0000000..942cea2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru_tst377.dat new file mode 100644 index 0000000..27ea2f5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_o_ru_tst377.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_du.dat new file mode 100644 index 0000000..92c8e3d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_ru.dat new file mode 100644 index 0000000..cb9411c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du.dat new file mode 100644 index 0000000..2aa2510 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du_tst376.dat new file mode 100644 index 0000000..2aa2510 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_du_tst376.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru.dat new file mode 100644 index 0000000..aee9e19 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru_tst376.dat new file mode 100644 index 0000000..f8d871c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_o_ru_tst376.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du.cfg new file mode 100644 index 0000000..4dd5356 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du.cfg @@ -0,0 +1,65 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0xE00000C00000 # mask [0- no workers] +dpdkMemorySize=8192 + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru.cfg new file mode 100644 index 0000000..84cdcc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3521/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du.dat new file mode 100644 index 0000000..d92540c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du_tst377.dat new file mode 100644 index 0000000..d92540c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_du_tst377.dat @@ -0,0 +1,265 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Component Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX antennas on DL UE side +UlLayersPerUe=1 #number of TX antennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru.dat new file mode 100644 index 0000000..dfebe7c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru_tst377.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru_tst377.dat new file mode 100644 index 0000000..6c70acc --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_o_ru_tst377.dat @@ -0,0 +1,315 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst377.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst377.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst377.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst377.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst377.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst377.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst377.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst377.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./avg_txconfig_1.cfg +#SlotNumTx1=./avg_txconfig_1.cfg +#SlotNumTx2=./avg_txconfig_1.cfg +#SlotNumTx3=./avg_txconfig_2.cfg +#SlotNumTx4=./avg_txconfig_0.cfg + +#SlotNumTx5=./avg_txconfig_1.cfg +#SlotNumTx6=./avg_txconfig_1.cfg +#SlotNumTx7=./avg_txconfig_1.cfg +#SlotNumTx8=./avg_txconfig_2.cfg +#SlotNumTx9=./avg_txconfig_0.cfg + +#SlotNumRx0=./avg_rxconfig_0.cfg +#SlotNumRx1=./avg_rxconfig_0.cfg +#SlotNumRx2=./avg_rxconfig_0.cfg +#SlotNumRx3=./avg_rxconfig_2.cfg +#SlotNumRx4=./avg_rxconfig_1.cfg + +#SlotNumRx5=./avg_rxconfig_0.cfg +#SlotNumRx6=./avg_rxconfig_0.cfg +#SlotNumRx7=./avg_rxconfig_0.cfg +#SlotNumRx8=./avg_rxconfig_3.cfg +#SlotNumRx9=./avg_rxconfig_1.cfg + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_0.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_0.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_1.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_1.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_2.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_2.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_3.cfg new file mode 100644 index 0000000..1143077 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_rxconfig_3.cfg @@ -0,0 +1,31 @@ +nPrbElemUl=4 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=10,4,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_0.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_0.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_1.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_1.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_2.cfg new file mode 100644 index 0000000..1f4514c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/avg_txconfig_2.cfg @@ -0,0 +1,32 @@ +nPrbElemDl=4 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,34,0,14,3,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=10,4,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_du.dat new file mode 100644 index 0000000..92c8e3d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_ru.dat new file mode 100644 index 0000000..cb9411c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/config_file_o_ru.dat @@ -0,0 +1,274 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du.dat new file mode 100644 index 0000000..a8238ac --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du_tst376.dat new file mode 100644 index 0000000..a8238ac --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_du_tst376.dat @@ -0,0 +1,305 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru.dat new file mode 100644 index 0000000..01009ac --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru_tst376.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru_tst376.dat new file mode 100644 index 0000000..9b3f143 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_o_ru_tst376.dat @@ -0,0 +1,353 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/uliq00_tst376.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/uliq01_tst376.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/uliq02_tst376.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/uliq03_tst376.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/uliq04_tst376.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/uliq05_tst376.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/uliq06_tst376.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/uliq07_tst376.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#SlotNumTx0=./peak_txconfig_1.cfg +#SlotNumTx1=./peak_txconfig_1.cfg +#SlotNumTx2=./peak_txconfig_1.cfg +#SlotNumTx3=./peak_txconfig_2.cfg +#SlotNumTx4=./peak_txconfig_0.cfg + +#SlotNumTx5=./peak_txconfig_1.cfg +#SlotNumTx6=./peak_txconfig_1.cfg +#SlotNumTx7=./peak_txconfig_1.cfg +#SlotNumTx8=./peak_txconfig_2.cfg +#SlotNumTx9=./peak_txconfig_0.cfg + +#SlotNumRx0=./peak_rxconfig_0.cfg +#SlotNumRx1=./peak_rxconfig_0.cfg +#SlotNumRx2=./peak_rxconfig_0.cfg +#SlotNumRx3=./peak_rxconfig_2.cfg +#SlotNumRx4=./peak_rxconfig_1.cfg + +#SlotNumRx5=./peak_rxconfig_0.cfg +#SlotNumRx6=./peak_rxconfig_0.cfg +#SlotNumRx7=./peak_rxconfig_0.cfg +#SlotNumRx8=./peak_rxconfig_3.cfg +#SlotNumRx9=./peak_rxconfig_1.cfg + + + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_0.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_0.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_1.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_1.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_2.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_2.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_3.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_3.cfg new file mode 100644 index 0000000..41d084a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_rxconfig_3.cfg @@ -0,0 +1,34 @@ +nPrbElemUl=6 + +# 0-15 CCs +PrbElemUlCCMask0=0f +PrbElemUlCCMask1=0f +PrbElemUlCCMask2=0f +PrbElemUlCCMask3=0f +PrbElemUlCCMask4=0f +PrbElemUlCCMask5=0f + +# 0-63 AntC +PrbElemUlAntCMask0=ffffffffffffffff +PrbElemUlAntCMask1=ffffffffffffffff +PrbElemUlAntCMask2=ffffffffffffffff +PrbElemUlAntCMask3=ffffffffffffffff +PrbElemUlAntCMask4=ffffffffffffffff +PrbElemUlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,4,0,0,9,1 +ExtBfwUl1=12,4,0,0,9,1 +ExtBfwUl2=12,4,0,0,9,1 +ExtBfwUl3=12,4,0,0,9,1 +ExtBfwUl4=12,4,0,0,9,1 +ExtBfwUl5=11,3,0,0,9,1 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_0.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_0.cfg new file mode 100644 index 0000000..b705198 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_0.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs S +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_1.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_1.cfg new file mode 100644 index 0000000..9359005 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_1.cfg @@ -0,0 +1,35 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_2.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_2.cfg new file mode 100644 index 0000000..6184512 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/peak_txconfig_2.cfg @@ -0,0 +1,36 @@ +nPrbElemDl=6 + +# 0-15 CCs +PrbElemDlCCMask0=0f +PrbElemDlCCMask1=0f +PrbElemDlCCMask2=0f +PrbElemDlCCMask3=0f +PrbElemDlCCMask4=0f +PrbElemDlCCMask5=0f + +# 0-63 AntC +PrbElemDlAntCMask0=ffffffffffffffff +PrbElemDlAntCMask1=ffffffffffffffff +PrbElemDlAntCMask2=ffffffffffffffff +PrbElemDlAntCMask3=ffffffffffffffff +PrbElemDlAntCMask4=ffffffffffffffff +PrbElemDlAntCMask5=ffffffffffffffff + + +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,4,0,0,9,1 +ExtBfwDl1=12,4,0,0,9,1 +ExtBfwDl2=12,4,0,0,9,1 +ExtBfwDl3=12,4,0,0,9,1 +ExtBfwDl4=12,4,0,0,9,1 +ExtBfwDl5=11,3,0,0,9,1 + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du.cfg new file mode 100644 index 0000000..fff013d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du.cfg @@ -0,0 +1,64 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=22 # core id +ioWorker=0xE00000C00000 # mask [0- no workers] + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du_csx.cfg new file mode 100644 index 0000000..4d9f87d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_du_csx.cfg @@ -0,0 +1,63 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x000000000 # mask [0- no workers] +#ioWorker=0x8000040000 # mask [0- no workers] +ioWorker=0x1E0000000 # mask [0- no workers] +#ioWorker=0x700000600 + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_du_tst376.dat #O-DU0 +oXuCfgFile1=./avg_o_du_tst377.dat #O-DU1 +oXuCfgFile2=./avg_o_du_tst377.dat #O-DU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru.cfg new file mode 100644 index 0000000..84cdcc2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru.cfg @@ -0,0 +1,62 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +# 3501 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % +# TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 Avg: 36 % + +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x3E00 # second socket + +dpdkMemorySize=18432 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru_csx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru_csx.cfg new file mode 100644 index 0000000..8ee5ce3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/3531/usecase_ru_csx.cfg @@ -0,0 +1,61 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=20 #core for main() +systemCore=22 +ioCore=28 # core id +#ioWorker=0x800000000 # mask [0- no workers] +#ioWorker=0x800004000 # mask [0- no workers] +#ioWorker=0xc000000 # second socket +ioWorker=0x3E0000000 # second socket + +dpdkMemorySize=16384 +iovaMode=0 + +oXuNum=3 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./peak_o_ru_tst376.dat #O-RU0 +oXuCfgFile1=./avg_o_ru_tst377.dat #O-RU1 +oXuCfgFile2=./avg_o_ru_tst377.dat #O-RU2 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_du.dat new file mode 100644 index 0000000..d74a2d3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 +PrbElemDl4=144,36,0,14,5,1,1,9,1 +PrbElemDl5=180,36,0,14,6,1,1,9,1 +PrbElemDl6=216,36,0,14,7,1,1,9,1 +PrbElemDl7=252,21,0,14,8,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +PrbElemUl2=72,36,0,14,3,1,1,9,1 +PrbElemUl3=108,36,0,14,4,1,1,9,1 +PrbElemUl4=144,36,0,14,5,1,1,9,1 +PrbElemUl5=180,36,0,14,6,1,1,9,1 +PrbElemUl6=216,36,0,14,7,1,1,9,1 +PrbElemUl7=252,21,0,14,8,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_ru.dat new file mode 100644 index 0000000..5020c29 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/config_file_o_ru.dat @@ -0,0 +1,260 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=2 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +ioWorker=0x800000000 +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=4 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,1,1,1,9,1 +PrbElemDl1=48,48,0,14,2,1,1,9,1 +PrbElemDl2=96,48,0,14,3,1,1,9,1 +PrbElemDl3=144,48,0,14,4,1,1,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,1,1,1,9,1 +PrbElemUl1=48,48,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/4/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_du.dat new file mode 100644 index 0000000..70e39b3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_du.dat @@ -0,0 +1,232 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,128,0,14,0,1,1,9,1 +PrbElemDl1=128,128,0,14,1,1,1,9,1 +PrbElemDl2=256,17,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,64,0,0,9,1 +ExtBfwDl1=2,64,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,128,0,14,0,1,1,9,1 +PrbElemUl1=128,128,0,14,1,1,1,9,1 +PrbElemUl2=256,17,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,64,0,0,9,1 +ExtBfwUl1=2,64,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_ru.dat new file mode 100644 index 0000000..a5c9062 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/config_file_o_ru.dat @@ -0,0 +1,268 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,128,0,14,0,1,1,9,1 +PrbElemDl1=128,128,0,14,1,1,1,9,1 +PrbElemDl2=256,17,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,128,0,14,0,1,1,9,1 +PrbElemUl1=128,128,0,14,1,1,1,9,1 +PrbElemUl2=256,17,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_du.cfg new file mode 100644 index 0000000..281607d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_du.cfg @@ -0,0 +1,69 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_ru.cfg new file mode 100644 index 0000000..b5fd930 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/401/usecase_ru.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x10000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_du.dat new file mode 100644 index 0000000..eefdbe7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_du.dat @@ -0,0 +1,232 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,128,0,14,0,1,1,9,1 +PrbElemDl1=128,128,0,14,1,1,1,9,1 +PrbElemDl2=256,17,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,64,0,0,9,1 +ExtBfwDl1=2,64,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,128,0,14,0,1,1,9,1 +PrbElemUl1=128,128,0,14,1,1,1,9,1 +PrbElemUl2=256,17,0,14,2,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,64,0,0,9,1 +ExtBfwUl1=2,64,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_ru.dat new file mode 100644 index 0000000..65b3486 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/config_file_o_ru.dat @@ -0,0 +1,268 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 6:4:4 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:00 # asigned MAC of O-DU VF +duMac1=00:11:22:33:44:10 # asigned MAC of O-DU VF + +ruMac0=00:11:22:33:44:01 # O-RU VF for O-RU app +ruMac1=00:11:22:33:44:11 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:20 # asigned MAC of O-DU VF +duMac3=00:11:22:33:44:30 # asigned MAC of O-DU VF + +ruMac2=00:11:22:33:44:21 # O-RU VF for O-RU app +ruMac3=00:11:22:33:44:31 # O-RU VF for O-RU app + +# Eth 1 +duMac4=00:11:22:33:44:40 # asigned MAC of O-DU VF +duMac5=00:11:22:33:44:50 # asigned MAC of O-DU VF +ruMac4=00:11:22:33:44:41 # O-RU VF for O-RU app +ruMac5=00:11:22:33:44:51 # O-RU VF for O-RU app + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,128,0,14,0,1,1,9,1 +PrbElemDl1=128,128,0,14,1,1,1,9,1 +PrbElemDl2=256,17,0,14,2,1,1,9,1 + +nPrbElemUl=3 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,128,0,14,0,1,1,9,1 +PrbElemUl1=128,128,0,14,1,1,1,9,1 +PrbElemUl2=256,17,0,14,2,1,1,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_du.cfg new file mode 100644 index 0000000..281607d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_du.cfg @@ -0,0 +1,69 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_ru.cfg new file mode 100644 index 0000000..b5fd930 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/411/usecase_ru.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=8 # core id +ioWorker=0x10000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_du.dat new file mode 100644 index 0000000..a6ea3d6 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_du.dat @@ -0,0 +1,281 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_ru.dat new file mode 100644 index 0000000..c67dc08 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/config_file_o_ru.dat @@ -0,0 +1,328 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du.cfg new file mode 100644 index 0000000..9b90a1c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +#ioWorker=0xE00000C00000 # mask [0- no workers] +ioWorker=0x1C000000001800 +dpdkMemorySize=8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du_icx.cfg new file mode 100644 index 0000000..78303c3 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +#ioWorker=0x200000000000 # mask [0- no workers] +ioWorker=0xE00000C00000 # mask [0- no workers] +dpdkMemorySize=8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_ru.cfg new file mode 100644 index 0000000..6aa5aad --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/501/usecase_ru.cfg @@ -0,0 +1,57 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_du.dat new file mode 100644 index 0000000..f459e44 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_ru.dat new file mode 100644 index 0000000..97c9ac9 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/config_file_o_ru.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/502/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_du.dat new file mode 100644 index 0000000..5555847 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_ru.dat new file mode 100644 index 0000000..dd2af52 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/503/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_du.dat new file mode 100644 index 0000000..2decc04 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_ru.dat new file mode 100644 index 0000000..3b66420 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/config_file_o_ru.dat @@ -0,0 +1,290 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/504/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_du.dat new file mode 100644 index 0000000..accadfc --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_ru.dat new file mode 100644 index 0000000..c92991e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/config_file_o_ru.dat @@ -0,0 +1,285 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/505/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_du.dat new file mode 100644 index 0000000..6d52750 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_du.dat @@ -0,0 +1,242 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_ru.dat new file mode 100644 index 0000000..dbc01f7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/506/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_du.dat new file mode 100644 index 0000000..508118a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_du.dat @@ -0,0 +1,281 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_ru.dat new file mode 100644 index 0000000..1ebc95c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/config_file_o_ru.dat @@ -0,0 +1,328 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du.cfg new file mode 100644 index 0000000..81c8cff --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du.cfg @@ -0,0 +1,59 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +#ioWorker=0xE00000C00000 # mask [0- no workers] +ioWorker=0x1C000000001800 +dpdkMemorySize=16384 +#8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du_icx.cfg new file mode 100644 index 0000000..2732d63 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0xE00000C00000 # mask [0- no workers] +dpdkMemorySize=16384 +#8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/511/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_du.dat new file mode 100644 index 0000000..431e4cd --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_ru.dat new file mode 100644 index 0000000..43436a8 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/512/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_du.dat new file mode 100644 index 0000000..a84ed42 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_ru.dat new file mode 100644 index 0000000..89dd171 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/513/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_du.dat new file mode 100644 index 0000000..250ccc0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_ru.dat new file mode 100644 index 0000000..229fa02 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/514/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_du.dat new file mode 100644 index 0000000..b3e2145 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_ru.dat new file mode 100644 index 0000000..93c5b17 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/515/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_du.dat new file mode 100644 index 0000000..259eeee --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_du.dat @@ -0,0 +1,242 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_ru.dat new file mode 100644 index 0000000..b2290d7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled + +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du_icx.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du_icx.cfg new file mode 100644 index 0000000..71f7c1d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_du_icx.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=21 # core id +ioWorker=0x200000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/516/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_du.dat new file mode 100644 index 0000000..42b4504 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_ru.dat new file mode 100644 index 0000000..9db693f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/config_file_o_ru.dat @@ -0,0 +1,272 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/601/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_du.dat new file mode 100644 index 0000000..89f734f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_du.dat @@ -0,0 +1,206 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_ru.dat new file mode 100644 index 0000000..d8f49d6 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_du.cfg new file mode 100644 index 0000000..d7b23b7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_du.cfg @@ -0,0 +1,54 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_ru.cfg new file mode 100644 index 0000000..78ef5d1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/602/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_du.dat new file mode 100644 index 0000000..e0d9e92 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_du.dat @@ -0,0 +1,207 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_ru.dat new file mode 100644 index 0000000..feb5e1c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_du.cfg new file mode 100644 index 0000000..5eb0082 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/603/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_du.dat new file mode 100644 index 0000000..55d2fc0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_du.dat @@ -0,0 +1,217 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_ru.dat new file mode 100644 index 0000000..ef27bc7 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/config_file_o_ru.dat @@ -0,0 +1,264 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/604/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_du.dat new file mode 100644 index 0000000..91cf79a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_du.dat @@ -0,0 +1,204 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_ru.dat new file mode 100644 index 0000000..b4a59f9 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/config_file_o_ru.dat @@ -0,0 +1,251 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/605/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_du.dat new file mode 100644 index 0000000..68c65bd --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_du.dat @@ -0,0 +1,208 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_ru.dat new file mode 100644 index 0000000..955acd8 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_du.cfg new file mode 100644 index 0000000..5eb0082 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() + +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/606/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_du.dat new file mode 100644 index 0000000..153598f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_du.dat @@ -0,0 +1,223 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_ru.dat new file mode 100644 index 0000000..62b891d --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/config_file_o_ru.dat @@ -0,0 +1,272 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,48,0,14,0,1,1,9,1 +PrbElemDl1=48,48,0,14,1,1,1,9,1 +PrbElemDl2=96,48,0,14,2,1,1,9,1 +PrbElemDl3=144,48,0,14,3,1,1,9,1 +PrbElemDl4=192,48,0,14,4,1,1,9,1 +PrbElemDl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,24,0,0,9,1 +ExtBfwDl1=2,24,0,0,9,1 +ExtBfwDl2=2,24,0,0,9,1 +ExtBfwDl3=2,24,0,0,9,1 +ExtBfwDl4=2,24,0,0,9,1 +ExtBfwDl5=2,17,0,0,9,1 + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,48,0,14,0,1,1,9,1 +PrbElemUl1=48,48,0,14,1,1,1,9,1 +PrbElemUl2=96,48,0,14,2,1,1,9,1 +PrbElemUl3=144,48,0,14,3,1,1,9,1 +PrbElemUl4=192,48,0,14,4,1,1,9,1 +PrbElemUl5=240,33,0,14,5,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,24,0,0,9,1 +ExtBfwUl1=2,24,0,0,9,1 +ExtBfwUl2=2,24,0,0,9,1 +ExtBfwUl3=2,24,0,0,9,1 +ExtBfwUl4=2,24,0,0,9,1 +ExtBfwUl5=2,17,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/611/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_du.dat new file mode 100644 index 0000000..603692c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_du.dat @@ -0,0 +1,206 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_ru.dat new file mode 100644 index 0000000..30ff1f5 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/612/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_du.dat new file mode 100644 index 0000000..ab47156 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_du.dat @@ -0,0 +1,207 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_ru.dat new file mode 100644 index 0000000..e0f31a0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/613/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_du.dat new file mode 100644 index 0000000..e58caba --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_du.dat @@ -0,0 +1,217 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_ru.dat new file mode 100644 index 0000000..7c83eff --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/config_file_o_ru.dat @@ -0,0 +1,264 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=15 +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +# Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/614/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_du.dat new file mode 100644 index 0000000..345f321 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_du.dat @@ -0,0 +1,204 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_ru.dat new file mode 100644 index 0000000..21b1981 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/config_file_o_ru.dat @@ -0,0 +1,251 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/615/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_du.dat new file mode 100644 index 0000000..1b4968e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_du.dat @@ -0,0 +1,208 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_ru.dat new file mode 100644 index 0000000..b981033 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/config_file_o_ru.dat @@ -0,0 +1,250 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,0,1,1,9,1 +PrbElemDl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,25,0,0,9,1 +ExtBfwDl1=2,25,0,0,9,1 + +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,0,1,1,9,1 +PrbElemUl1=50,50,0,14,1,1,1,9,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,25,0,0,9,1 +ExtBfwUl1=2,25,0,0,9,1 + +nPrbElemSrs=1 +PrbElemSrs0=0,273,0,14,0,0,1,9,0 + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_du.cfg new file mode 100644 index 0000000..da0df27 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_du.cfg @@ -0,0 +1,55 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_ru.cfg new file mode 100644 index 0000000..3ab240f --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/616/usecase_ru.cfg @@ -0,0 +1,51 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_du.dat new file mode 100644 index 0000000..48aaac1 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_du.dat @@ -0,0 +1,281 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_ru.dat new file mode 100644 index 0000000..0e3f297 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/config_file_o_ru.dat @@ -0,0 +1,328 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#301 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_du.cfg new file mode 100644 index 0000000..9b90a1c --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +#ioWorker=0xE00000C00000 # mask [0- no workers] +ioWorker=0x1C000000001800 +dpdkMemorySize=8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_ru.cfg new file mode 100644 index 0000000..6aa5aad --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/801/usecase_ru.cfg @@ -0,0 +1,57 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_du.dat new file mode 100644 index 0000000..292f860 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_ru.dat new file mode 100644 index 0000000..2835621 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/config_file_o_ru.dat @@ -0,0 +1,289 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#302 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/802/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_du.dat new file mode 100644 index 0000000..4307fd6 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_ru.dat new file mode 100644 index 0000000..d8a0383 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#303 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 4 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/803/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_du.dat new file mode 100644 index 0000000..37ef4be --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_ru.dat new file mode 100644 index 0000000..6347d8e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/config_file_o_ru.dat @@ -0,0 +1,290 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#304 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 4 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +#DL PRB / % Used RBs UL PRB / % Used RBs +#66% 180 33% 90 + +########################################################### +##Section Settings +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/804/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_du.dat new file mode 100644 index 0000000..b743972 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_ru.dat new file mode 100644 index 0000000..adefa71 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/config_file_o_ru.dat @@ -0,0 +1,285 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#305 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 2 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/805/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_du.dat new file mode 100644 index 0000000..c9d4c3e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_du.dat @@ -0,0 +1,242 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_ru.dat new file mode 100644 index 0000000..14964ca --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#306 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 1 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=1 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/806/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_du.dat new file mode 100644 index 0000000..d5d4660 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_du.dat @@ -0,0 +1,281 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_ru.dat new file mode 100644 index 0000000..4b1fc45 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/config_file_o_ru.dat @@ -0,0 +1,328 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak: 100 % +#311 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 16 100% 273 3276 100% 273 3276 Peak: 100 % + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + + + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin + + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=16 +max_sections_per_symbol=16 + +nPrbElemDl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,18,0,14,5,1,1,9,1 +PrbElemDl6=108,18,0,14,6,1,1,9,1 +PrbElemDl7=126,18,0,14,7,1,1,9,1 +PrbElemDl8=144,18,0,14,8,1,1,9,1 +PrbElemDl9=162,18,0,14,9,1,1,9,1 +PrbElemDl10=180,18,0,14,10,1,1,9,1 +PrbElemDl11=198,18,0,14,11,1,1,9,1 +PrbElemDl12=216,18,0,14,12,1,1,9,1 +PrbElemDl13=234,18,0,14,13,1,1,9,1 +PrbElemDl14=252,18,0,14,14,1,1,9,1 +PrbElemDl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,9,0,0,9,1 +ExtBfwDl6=2,9,0,0,9,1 +ExtBfwDl7=2,9,0,0,9,1 +ExtBfwDl8=2,9,0,0,9,1 +ExtBfwDl9=2,9,0,0,9,1 +ExtBfwDl10=2,9,0,0,9,1 +ExtBfwDl11=2,9,0,0,9,1 +ExtBfwDl12=2,9,0,0,9,1 +ExtBfwDl13=2,9,0,0,9,1 +ExtBfwDl14=2,9,0,0,9,1 +ExtBfwDl15=2,2,0,0,9,1 + + +nPrbElemUl=16 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,18,0,14,5,1,1,9,1 +PrbElemUl6=108,18,0,14,6,1,1,9,1 +PrbElemUl7=126,18,0,14,7,1,1,9,1 +PrbElemUl8=144,18,0,14,8,1,1,9,1 +PrbElemUl9=162,18,0,14,9,1,1,9,1 +PrbElemUl10=180,18,0,14,10,1,1,9,1 +PrbElemUl11=198,18,0,14,11,1,1,9,1 +PrbElemUl12=216,18,0,14,12,1,1,9,1 +PrbElemUl13=234,18,0,14,13,1,1,9,1 +PrbElemUl14=252,18,0,14,14,1,1,9,1 +PrbElemUl15=270,3,0,14,15,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,9,0,0,9,1 +ExtBfwUl6=2,9,0,0,9,1 +ExtBfwUl7=2,9,0,0,9,1 +ExtBfwUl8=2,9,0,0,9,1 +ExtBfwUl9=2,9,0,0,9,1 +ExtBfwUl10=2,9,0,0,9,1 +ExtBfwUl11=2,9,0,0,9,1 +ExtBfwUl12=2,9,0,0,9,1 +ExtBfwUl13=2,9,0,0,9,1 +ExtBfwUl14=2,9,0,0,9,1 +ExtBfwUl15=2,2,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_du.cfg new file mode 100644 index 0000000..81c8cff --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_du.cfg @@ -0,0 +1,59 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +#ioWorker=0xE00000C00000 # mask [0- no workers] +ioWorker=0x1C000000001800 +dpdkMemorySize=16384 +#8192 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/811/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_du.dat new file mode 100644 index 0000000..8b7dcdb --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_ru.dat new file mode 100644 index 0000000..7f07925 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#Peak +#4% +#312 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 16 37% 100 1200 37% 100 1200 Peak: 4 % + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=16 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/812/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_du.dat new file mode 100644 index 0000000..badeb9e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_ru.dat new file mode 100644 index 0000000..2ac67b0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#NC +#12% +#313 TDD DDDFU: S it's 10:2:2 1 64T64R 100 16 8 37% 100 1200 37% 100 1200 NC: 12% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=16 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/813/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_du.dat new file mode 100644 index 0000000..92d8164 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_du.dat @@ -0,0 +1,240 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_ru.dat new file mode 100644 index 0000000..59a261a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MC +#20% +#314 TDD DDDFU: S it's 10:2:2 1 64T64R 100 8 8 37% 100 1200 37% 100 1200 MC: 20% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=8 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/814/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_du.dat new file mode 100644 index 0000000..8c5624e --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_du.dat @@ -0,0 +1,241 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_ru.dat new file mode 100644 index 0000000..1f26676 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#MEC +#28% +#315 TDD DDDFU: S it's 10:2:2 1 64T64R 100 4 4 37% 100 1200 37% 100 1200 MEC: 28% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/815/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_du.dat new file mode 100644 index 0000000..598fce0 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_du.dat @@ -0,0 +1,242 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/cat_b/mu1_100mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_ru.dat new file mode 100644 index 0000000..4fece74 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/config_file_o_ru.dat @@ -0,0 +1,284 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + +#EC +#36% +#316 TDD DDDFU: S it's 10:2:2 1 64T64R 100 2 2 37% 100 1200 37% 100 1200 EC: 36% + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 4) +antNum=2 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=2 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=64 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side + + +##Numerology +mu=1 #30Khz Sub Carrier Spacing + +ttiPeriod=500 # in us TTI period (30Khz default 500us) + +nDLAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=3568160 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=100 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=4096 +nULFftSize=4096 + +nFrameDuplexType=1 # 0 - FDD 1 - TDD +nTddPeriod=5 #[0-9] DDDFU, for S it's 10:2:2 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,0,0,0,0,2,2,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=1500 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +numSlots=20 #number of slots per IQ files +antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +antPrachC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 +antPrachC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 +antPrachC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 +antPrachC3=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC0 +antPrachC4=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC1 +antPrachC5=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC1 +antPrachC6=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC1 +antPrachC7=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC1 +antPrachC8=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC2 +antPrachC9=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC2 +antPrachC10=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC2 +antPrachC11=./usecase/cat_b/mu1_100mhz/ant_3.bin #CC2 +antPrachC12=./usecase/cat_b/mu1_100mhz/ant_4.bin #CC3 +antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin #CC3 +antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin #CC3 +antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin #CC3 + +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +prachConfigIndex=189 + +srsEanble=1 # Enable (1)| disable (0) SRS +srsSym=1 # (1<<13) symbol used for SRS (def: sym 13) + +antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC2=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC3=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC4=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC5=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC6=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC7=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC8=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC9=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC10=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC11=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC12=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC13=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC14=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC15=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC16=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC17=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC18=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC19=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC20=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC21=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC22=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC23=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC24=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC25=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC26=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC27=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC28=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC29=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC30=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC32=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC33=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC34=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC35=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC36=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC37=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC38=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC39=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC40=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC41=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC42=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC43=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC44=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC45=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC46=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC47=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC48=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC49=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC50=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC51=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC52=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC53=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC54=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC55=./usecase/cat_b/mu1_100mhz/ant_7.bin +antSrsC56=./usecase/cat_b/mu1_100mhz/ant_0.bin +antSrsC57=./usecase/cat_b/mu1_100mhz/ant_1.bin +antSrsC58=./usecase/cat_b/mu1_100mhz/ant_2.bin +antSrsC59=./usecase/cat_b/mu1_100mhz/ant_3.bin +antSrsC60=./usecase/cat_b/mu1_100mhz/ant_4.bin +antSrsC61=./usecase/cat_b/mu1_100mhz/ant_5.bin +antSrsC62=./usecase/cat_b/mu1_100mhz/ant_6.bin +antSrsC63=./usecase/cat_b/mu1_100mhz/ant_7.bin +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=12 +max_sections_per_symbol=12 + +nPrbElemDl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,18,0,14,0,1,1,9,1 +PrbElemDl1=18,18,0,14,1,1,1,9,1 +PrbElemDl2=36,18,0,14,2,1,1,9,1 +PrbElemDl3=54,18,0,14,3,1,1,9,1 +PrbElemDl4=72,18,0,14,4,1,1,9,1 +PrbElemDl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=2,9,0,0,9,1 +ExtBfwDl1=2,9,0,0,9,1 +ExtBfwDl2=2,9,0,0,9,1 +ExtBfwDl3=2,9,0,0,9,1 +ExtBfwDl4=2,9,0,0,9,1 +ExtBfwDl5=2,5,0,0,9,1 + + +nPrbElemUl=6 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,18,0,14,0,1,1,9,1 +PrbElemUl1=18,18,0,14,1,1,1,9,1 +PrbElemUl2=36,18,0,14,2,1,1,9,1 +PrbElemUl3=54,18,0,14,3,1,1,9,1 +PrbElemUl4=72,18,0,14,4,1,1,9,1 +PrbElemUl5=90,10,0,14,5,1,1,9,1 + +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=2,9,0,0,9,1 +ExtBfwUl1=2,9,0,0,9,1 +ExtBfwUl2=2,9,0,0,9,1 +ExtBfwUl3=2,9,0,0,9,1 +ExtBfwUl4=2,9,0,0,9,1 +ExtBfwUl5=2,5,0,0,9,1 + + +nPrbElemSrs=11 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +PrbElemSrs0=0,30,0,1,0,0,1,9,0 +PrbElemSrs1=30,30,0,1,0,0,1,9,0 +PrbElemSrs2=60,30,0,1,0,0,1,9,0 +PrbElemSrs3=90,30,0,1,0,0,1,9,0 +PrbElemSrs4=120,30,0,1,0,0,1,9,0 +PrbElemSrs5=150,30,0,1,0,0,1,9,0 +PrbElemSrs6=180,30,0,1,0,0,1,9,0 +PrbElemSrs7=210,30,0,1,0,0,1,9,0 +PrbElemSrs8=240,30,0,1,0,0,1,9,0 +PrbElemSrs9=270,30,0,1,0,0,1,9,0 +PrbElemSrs10=270,3,0,1,0,0,1,9,0 + + +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##O-RU Settings +totalBFWeights=64 # Total number of Beamforming Weights on RU + +Tadv_cp_dl=25 # in us + # C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages +#Reception Window C-plane DL +T2a_min_cp_dl=285 # 285.42us +T2a_max_cp_dl=429 # 428.12us + +#Reception Window C-plane UL +T2a_min_cp_ul=285 # 285.42us +T2a_max_cp_ul=429 # 428.12us + +#Reception Window U-plane +T2a_min_up=71 # 71.35in us +T2a_max_up=428 # 428.12us + +#Transmission Window +Ta3_min=20 # in us +Ta3_max=32 # in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_min_cp_dl=285 +T1a_max_cp_dl=429 + +##Transmission Window Fast C-plane UL +T1a_min_cp_ul=285 +T1a_max_cp_ul=300 + +#U-plane +##Transmission Window +T1a_min_up=96 #71 + 25 us +T1a_max_up=196 #71 + 25 us + +#Reception Window +Ta4_min=0 # in us +Ta4_max=75 # in us +########################################################### + diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_du.cfg new file mode 100644 index 0000000..f6efede --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_du.cfg @@ -0,0 +1,58 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system + +mainCore=0 #core for main() +systemCore=2 +ioCore=10 # core id +ioWorker=0x4000000000000 # mask [0- no workers] +dpdkMemorySize=8192 + +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 + +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_ru.cfg new file mode 100644 index 0000000..7d7d28a --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/816/usecase_ru.cfg @@ -0,0 +1,56 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +mainCore=0 #core for main() +systemCore=2 +ioCore=4 # core id +ioWorker=0x3E0 # second socket +dpdkMemorySize=8192 +#dpdkMemorySize=17408 +iovaMode=0 + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=2 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) +oXuCPon1Vf=1 # (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_du.dat index 8094879..ba953d9 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_du.dat @@ -75,7 +75,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -122,6 +122,8 @@ srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) ########################################################### ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 nPrbElemDl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType @@ -134,6 +136,17 @@ PrbElemDl4=144,36,0,14,5,1,0,16,1 PrbElemDl5=180,36,0,14,6,1,0,16,1 PrbElemDl6=216,36,0,14,7,1,0,16,1 PrbElemDl7=252,21,0,14,8,1,0,16,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwDl0=12,3,0,0,9,1 +ExtBfwDl1=12,3,0,0,9,1 +ExtBfwDl2=12,3,0,0,9,1 +ExtBfwDl3=12,3,0,0,9,1 +ExtBfwDl4=12,3,0,0,9,1 +ExtBfwDl5=12,3,0,0,9,1 +ExtBfwDl6=12,3,0,0,9,1 +ExtBfwDl7=7,3,0,0,9,1 + nPrbElemUl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType # weight base beams @@ -145,6 +158,16 @@ PrbElemUl4=144,36,0,14,5,1,0,16,1 PrbElemUl5=180,36,0,14,6,1,0,16,1 PrbElemUl6=216,36,0,14,7,1,0,16,1 PrbElemUl7=252,21,0,14,8,1,0,16,1 +# Extension Parameters for Beamforming weights +# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth +ExtBfwUl0=12,3,0,0,9,1 +ExtBfwUl1=12,3,0,0,9,1 +ExtBfwUl2=12,3,0,0,9,1 +ExtBfwUl3=12,3,0,0,9,1 +ExtBfwUl4=12,3,0,0,9,1 +ExtBfwUl5=12,3,0,0,9,1 +ExtBfwUl6=12,3,0,0,9,1 +ExtBfwUl7=7,3,0,0,9,1 ########################################################### ## control of IQ byte order diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_ru.dat index 34ea329..fecb7e4 100644 --- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/config_file_o_ru.dat @@ -75,7 +75,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=10 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin #CC0 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin #CC0 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin #CC0 @@ -153,6 +153,8 @@ antSrsC31=./usecase/cat_b/mu1_100mhz/ant_7.bin ########################################################### ##Section Settings DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used +max_sections_per_slot=8 +max_sections_per_symbol=8 nPrbElemDl=8 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/testcases.md b/fhi_lib/app/usecase/cat_b/mu1_100mhz/testcases.md new file mode 100644 index 0000000..a7f39a2 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/testcases.md @@ -0,0 +1,57 @@ +| Test # | MTU | Duplexing | Slot pattern | Cells | Antennas | BW | MIMO DL | MIMO UL | DL PRB % | Used RBs | DL SCS | UL PRB % | Used RBs | UL SCS | Comment | +| ------ | --- | --------- | ------------ | ----- | -------- | -- | ------- | ------- | -------- | -------- | ------ | -------- | -------- | ------ | ------- | +101|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|8T8R|100|4|2|33%|90|1080|33%|90|1080 +102|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|8T8R|100|4|2|33%|90|1080|33%|90|1080 +103|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|8T8R|100|4|2|66%|180|2160|33%|90|1080 +104|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|33%|90|1080|33%|90|1080 +105|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|33%|90|1080|33%|90|1080 +106|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|66%|180|2160|33%|90|1080 +107|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|8|4|33%|90|1080|33%|90|1080 +108|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|8|4|33%|90|1080|33%|90|1080 +109|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|8|4|66%|180|2160|33%|90|1080 +201|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|8T8R|100|8|4|70.3%|192|2304|70.0%|191|2292|new added 70% with 8T8R +202|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|100.0%|273|3276|100.0%|273|3276|1 peak +203|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|4|70.3%|192|2304|35.0%|96|1152|35% center +204|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|4|70.3%|192|2304|35.0%|96|1152|45% mid +205|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|4|1|70.3%|192|2304|35.0%|96|1152|20% edge +206|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|8|4|70.3%|192|2304|70.0%|191|2292|70% +211|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|8T8R|100|8|8|70.3%|192|2304|70.0%|191|2292|new added 70% with 8T8R (2xUL) +212|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|16|100.0%|273|3276|100.0%|273|3276|1 peak (2xUL) +213|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|70.3%|192|2304|35.0%|96|1152|35% center (2xUL) +214|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|16|8|70.3%|192|2304|35.0%|96|1152|45% mid (2xUL) +215|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|4|2|70.3%|192|2304|35.0%|96|1152|20% edge (2xUL) +216|9600|TDD|DDDSUUDDDD: S it's 6:4:4|1|64T64R|100|8|8|70.3%|192|2304|70.0%|191|2292|70% (2xUL) +303|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|4|37%|100|1200|37%|100|1200|NC: 12% +304|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|4|37%|100|1200|37%|100|1200|MC: 20% +305|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|4|2|37%|100|1200|37%|100|1200|MEC: 28% +306|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|2|1|37%|100|1200|37%|100|1200|EC: 36% +3301|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|100%|273|3276|100%|273|3276|Peak: 100 % +3301|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|Avg: 36 % +3301|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|Avg: 36 % +311|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|100%|273|3276|100%|273|3276|Peak: 100 % +312|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|16|37%|100|1200|37%|100|1200|Peak: 4 % +313|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|NC: 12% +314|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|8|37%|100|1200|37%|100|1200|MC: 20% +315|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|4|4|37%|100|1200|37%|100|1200|MEC: 28% +316|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|2|2|37%|100|1200|37%|100|1200|EC: 36% +3311|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|100%|273|3276|100%|273|3276|Peak: 100 % +3311|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|37%|100|1200|37%|100|1200|Avg: 36 % +3311|9600|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|37%|100|1200|37%|100|1200|Avg: 36 % +501|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|100%|273|3276|100%|273|3276|Peak: 100 % +502|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|8|37%|100|1200|37%|100|1200|Peak: 4 % +503|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|4|37%|100|1200|37%|100|1200|NC: 12% +504|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|4|37%|100|1200|37%|100|1200|MC: 20% +505|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|4|2|37%|100|1200|37%|100|1200|MEC: 28% +506|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|2|1|37%|100|1200|37%|100|1200|EC: 36% +3501|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|100%|273|3276|100%|273|3276|Peak: 100 % +3501|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|Avg: 36 % +3501|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|Avg: 36 % +511|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|100%|273|3276|100%|273|3276|Peak: 100 % +512|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|16|37%|100|1200|37%|100|1200|Peak: 4 % +513|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|8|37%|100|1200|37%|100|1200|NC: 12% +514|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|8|8|37%|100|1200|37%|100|1200|MC: 20% +515|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|4|4|37%|100|1200|37%|100|1200|MEC: 28% +516|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|2|2|37%|100|1200|37%|100|1200|EC: 36% +3511|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|100%|273|3276|100%|273|3276|Peak: 100 % +3511|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|37%|100|1200|37%|100|1200|Avg: 36 % +3511|1500|TDD|DDDFU: S it's 10:2:2|1|64T64R|100|16|16|37%|100|1200|37%|100|1200|Avg: 36 % \ No newline at end of file diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_du.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_ru.cfg b/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_du.dat b/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_du.dat index aa6795d..5cf9eba 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_du.dat @@ -23,7 +23,7 @@ appMode=0 # O-DU (0) | RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=1024 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -58,7 +58,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_10mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_10mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_10mhz/ant_2.bin #CC0 @@ -103,9 +103,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -113,11 +113,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -131,8 +131,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -142,7 +142,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_ru.dat index 7397c2d..45a83ce 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_10mhz/config_file_o_ru.dat @@ -23,7 +23,7 @@ appMode=1 # O-DU(0) | O-RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=1024 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -59,7 +59,7 @@ duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_10mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_10mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_10mhz/ant_2.bin #CC0 @@ -108,9 +108,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -118,11 +118,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -136,8 +136,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -147,7 +147,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_10mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_du.dat b/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_du.dat index 166ce0f..9f1ab05 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_du.dat @@ -23,7 +23,7 @@ appMode=0 # O-DU (0) | RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=2048 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -58,7 +58,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_20mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_20mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_20mhz/ant_2.bin #CC0 @@ -101,9 +101,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -111,11 +111,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -129,8 +129,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -140,7 +140,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_ru.dat index 17f9bb2..a0d9ebc 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_20mhz/config_file_o_ru.dat @@ -23,7 +23,7 @@ appMode=1 # O-DU(0) | O-RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=2048 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -59,7 +59,7 @@ duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_20mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_20mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_20mhz/ant_2.bin #CC0 @@ -110,9 +110,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -120,11 +120,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -138,8 +138,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -149,7 +149,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_20mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_du.dat b/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_du.dat index a407ca0..d114adb 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_du.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_du.dat @@ -23,7 +23,7 @@ appMode=0 # O-DU (0) | RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=512 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -58,7 +58,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_5mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_5mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_5mhz/ant_2.bin #CC0 @@ -103,9 +103,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -113,11 +113,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -131,8 +131,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -142,7 +142,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_ru.dat index 80d564b..4c5c9de 100644 --- a/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_ru.dat +++ b/fhi_lib/app/usecase/lte_a/mu0_5mhz/config_file_o_ru.dat @@ -23,7 +23,7 @@ appMode=1 # O-DU(0) | O-RU(1) xranRanTech=1 # 5G NR (0) | LTE (1) xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B ##Numerology mu=0 #15Khz Sub Carrier Spacing @@ -38,7 +38,7 @@ nULFftSize=512 nFrameDuplexType=0 # 0 - FDD 1 - TDD nTddPeriod=0 #TDD priod e.g. DDDS 4 -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec Gps_Beta=0 @@ -59,7 +59,7 @@ duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app -numSlots=40 #number of slots per IQ files +numSlots=20 #number of slots per IQ files antC0=./usecase/lte_a/mu0_5mhz/ant_0.bin #CC0 antC1=./usecase/lte_a/mu0_5mhz/ant_1.bin #CC0 antC2=./usecase/lte_a/mu0_5mhz/ant_2.bin #CC0 @@ -110,9 +110,9 @@ BandSector_ID_bitwidth=3 CC_ID_bitwidth=3 RU_Port_ID_bitwidth=8 -# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF # O-RAN.WG4.IOT.0-v02.00 -# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF #U-plane ##Transmission Window @@ -120,11 +120,11 @@ T1a_max_up=437 T1a_min_up=366 #Reception Window U-plane -T2a_max_up=437 -T2a_min_up=206 - -Tadv_cp_dl=125 - +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + #Transmission Window Ta3_max=232 #in us Ta3_min=70 #in us @@ -138,8 +138,8 @@ T1a_max_cp_ul=356 T1a_min_cp_ul=285 #Reception Window C-plane UL -T2a_max_cp_ul=356 #in us -T2a_min_cp_ul=125 #in us +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us ########################################################### ##O-DU Settings @@ -149,7 +149,7 @@ T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B #O-RU Reception Window C-plane DL -T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B -T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B ########################################################### diff --git a/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_a/mu0_5mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_du.dat b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_du.dat new file mode 100644 index 0000000..279df40 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_du.dat @@ -0,0 +1,221 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU (0) | RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +ioWorker=0x2000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3 +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,25,0,14,1,1,1,9,1 +PrbElemDl1=25,25,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,25,0,14,1,1,1,9,1 +PrbElemUl1=25,25,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_ru.dat new file mode 100644 index 0000000..82ba60f --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/config_file_o_ru.dat @@ -0,0 +1,190 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=1024 +nULFftSize=1024 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +ioWorker=0x40000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration + +antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin +antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin +antPrachC2=./usecase/lte_a/mu0_10mhz/ant_2.bin +antPrachC3=./usecase/lte_a/mu0_10mhz/ant_3.bin +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,25,0,14,1,1,1,9,1 +PrbElemDl1=25,25,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,25,0,14,1,1,1,9,1 +PrbElemUl1=25,25,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/1/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_10mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_du.dat b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_du.dat new file mode 100644 index 0000000..3e40b3c --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_du.dat @@ -0,0 +1,221 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU (0) | RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +ioWorker=0x2000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3 +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/lte_b/mu0_20mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/lte_b/mu0_20mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,1,1,1,9,1 +PrbElemDl1=50,50,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,1,1,1,9,1 +PrbElemUl1=50,50,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_ru.dat new file mode 100644 index 0000000..afb3e80 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/config_file_o_ru.dat @@ -0,0 +1,190 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=2048 +nULFftSize=2048 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +ioWorker=0x40000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_20mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_20mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_20mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_20mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_20mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_20mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_20mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_20mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_20mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_20mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_20mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_20mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_20mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_20mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_20mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_20mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration + +antPrachC0=./usecase/lte_a/mu0_20mhz/ant_0.bin +antPrachC1=./usecase/lte_a/mu0_20mhz/ant_1.bin +antPrachC2=./usecase/lte_a/mu0_20mhz/ant_2.bin +antPrachC3=./usecase/lte_a/mu0_20mhz/ant_3.bin +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,50,0,14,1,1,1,9,1 +PrbElemDl1=50,50,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,50,0,14,1,1,1,9,1 +PrbElemUl1=50,50,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/1/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_20mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_du.dat b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_du.dat new file mode 100644 index 0000000..7805084 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_du.dat @@ -0,0 +1,221 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +appMode=0 # O-DU (0) | RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=512 +nULFftSize=512 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=5 +ioWorker=0x2000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3 +#DL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of TX elements and K- number of UEs (the same as Layers)] +DlBfwUe0=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe1=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe2=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe3=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe4=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe5=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe6=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe7=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe8=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe9=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe10=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe11=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe12=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe13=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe14=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +DlBfwUe15=./usecase/lte_b/mu0_10mhz/dl_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + +#UL beamforming weights used based on channel to UE [e.g Wzf = H^H(H*H^H)-1 wher H is MxK matrix, M - number of RX elements and K- number of UEs (the same as Layers)] +UlBfwUe0=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe1=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe2=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe3=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe4=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe5=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe6=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe7=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe8=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_0.bin #UE0 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe9=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_1.bin #UE1 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe10=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_2.bin #UE2 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe11=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_3.bin #UE3 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe12=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_4.bin #UE4 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe13=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_5.bin #UE5 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe14=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_6.bin #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points] +UlBfwUe15=./usecase/lte_b/mu0_10mhz/ul_bfw_ue_7.bin #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points] + + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration +#rachOffset=43 # RB offset for prach detection (see RIU spec) +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,15,0,14,1,1,1,9,1 +PrbElemDl1=15,10,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,15,0,14,1,1,1,9,1 +PrbElemUl1=15,10,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_ru.dat b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_ru.dat new file mode 100644 index 0000000..06d1473 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/config_file_o_ru.dat @@ -0,0 +1,190 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ + + +# This is simple configuration file. Use '#' sign for comments +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +appMode=1 # O-DU(0) | O-RU(1) +xranRanTech=1 # 5G NR (0) | LTE (1) +xranMode=1 # Category A (0) (precoder in O-DU) | Category B (1) (precoder in O-RU) +ccNum=1 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) +antNum=8 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B +antNumUL=4 # Cat B: UL Number of Antennas per CC (default: 8) or number of UL Digital streams for Category B +antElmTRx=32 #number of Antenna Elements for Cat B default 32T32R + +#UEs +muMimoUEs=8 #number of UEs serviced by MU-MIMO system. Number of independent beams within the same Freq/Time resources +DlLayersPerUe=1 #number of RX anntennas on DL UE side +UlLayersPerUe=1 #number of TX anntennas on UL UE side +##Numerology +mu=0 #15Khz Sub Carrier Spacing +ttiPeriod=1000 # in us TTI period (15Khz default 1000us) +nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 +nDLBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400 +nULBandwidth=5 #Carrier bandwidth for in MHz. Value: 5->400 +nDLFftSize=512 +nULFftSize=512 + +nFrameDuplexType=0 # 0 - FDD 1 - TDD +nTddPeriod=0 #TDD priod e.g. DDDS 4 +nTddPeriod=10 #[0-9] DDDSUUDDDD, for S it's 6:4:4 +sSlotConfig0=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig1=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig2=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig3=0,0,0,0,0,0,2,2,2,2,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig4=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig5=1,1,1,1,1,1,1,1,1,1,1,1,1,1 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig6=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig7=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig8=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD +sSlotConfig9=0,0,0,0,0,0,0,0,0,0,0,0,0,0 # (0) - DL (1) - UL (2) - GUARD + +MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single + #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) +Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec +Gps_Beta=0 + +ioCore=10 +ioWorker=0x40000000 # mask [0- no workers] +ioSleep=1 + +# Eth 0 +duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app +duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF +ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app + +#Eth 1 +duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app +duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF +ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app + + +numSlots=10 #number of slots per IQ files +antC0=./usecase/lte_b/mu0_10mhz/ant_0.bin #CC0 +antC1=./usecase/lte_b/mu0_10mhz/ant_1.bin #CC0 +antC2=./usecase/lte_b/mu0_10mhz/ant_2.bin #CC0 +antC3=./usecase/lte_b/mu0_10mhz/ant_3.bin #CC0 +antC4=./usecase/lte_b/mu0_10mhz/ant_4.bin #CC1 +antC5=./usecase/lte_b/mu0_10mhz/ant_5.bin #CC1 +antC6=./usecase/lte_b/mu0_10mhz/ant_6.bin #CC1 +antC7=./usecase/lte_b/mu0_10mhz/ant_7.bin #CC1 +antC8=./usecase/lte_b/mu0_10mhz/ant_8.bin #CC2 +antC9=./usecase/lte_b/mu0_10mhz/ant_9.bin #CC2 +antC10=./usecase/lte_b/mu0_10mhz/ant_10.bin #CC2 +antC11=./usecase/lte_b/mu0_10mhz/ant_11.bin #CC2 +antC12=./usecase/lte_b/mu0_10mhz/ant_12.bin #CC3 +antC13=./usecase/lte_b/mu0_10mhz/ant_13.bin #CC3 +antC14=./usecase/lte_b/mu0_10mhz/ant_14.bin #CC3 +antC15=./usecase/lte_b/mu0_10mhz/ant_15.bin #CC3 + +## RACH TODO: update for PRACH +rachEanble=0 # Enable (1)| disable (0) PRACH configuration + +antPrachC0=./usecase/lte_a/mu0_10mhz/ant_0.bin +antPrachC1=./usecase/lte_a/mu0_10mhz/ant_1.bin +antPrachC2=./usecase/lte_a/mu0_10mhz/ant_2.bin +antPrachC3=./usecase/lte_a/mu0_10mhz/ant_3.bin +#rachCfgIdx=14 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index +prachConfigIndex=189 + +srsEanble=0 # Enable (1)| disable (0) SRS +srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13) + +########################################################### +##Section Settings +DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used + +nPrbElemDl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemDl0=0,15,0,14,1,1,1,9,1 +PrbElemDl1=15,10,0,14,2,1,1,9,1 +nPrbElemUl=2 +#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType +# weight base beams +PrbElemUl0=0,15,0,14,1,1,1,9,1 +PrbElemUl1=15,10,0,14,2,1,1,9,1 +########################################################### + +## control of IQ byte order +iqswap=0 #do swap of IQ before send buffer to eth +nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order +compression=1 # (1) compression enabled (0) compression disabled +compType=1 # (1) Static Compression with config info sent over the M-Plane (0) Dynamic compression with configuration sent over the C and U Plane +##Debug +debugStop=1 #stop app on 1pps boundary (gps_second % 30) +debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary +bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode + +CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled + +##RU Settings +totalBFWeights=32 # Total number of Beamforming Weights on RU + +#CID settings +DU_Port_ID_bitwidth=2 +BandSector_ID_bitwidth=3 +CC_ID_bitwidth=3 +RU_Port_ID_bitwidth=8 + +# LTE-FDD-FR1-CAT-A-NoBF / LTE-FDD-FR1-CAT-A-DBF +# O-RAN.WG4.IOT.0-v02.00 +# Table A.2.3.2-1: LTE FDD IOT Profile 2 - LTE-FDD-FR1-CAT-A-NoBF + +#U-plane +##Transmission Window +T1a_max_up=437 +T1a_min_up=366 + +#Reception Window U-plane +T2a_max_up=437 +T2a_min_up=206 + +Tadv_cp_dl=125 + +#Transmission Window +Ta3_max=232 #in us +Ta3_min=70 #in us + +#Reception Window +Ta4_max=392 +Ta4_min=70 + +##Transmission Window Fast C-plane UL +T1a_max_cp_ul=356 +T1a_min_cp_ul=285 + +#Reception Window C-plane UL +T2a_max_cp_ul=356 #in us +T2a_min_cp_ul=125 #in us + +########################################################### +##O-DU Settings +#C-plane +#Transmission Window Fast C-plane DL +T1a_max_cp_dl=562 #in T1a_max_up + Tcp_adv_dl as per Annex B +T1a_min_cp_dl=491 #in T1a_min_up + Tcp_adv_dl as per Annex B + +#O-RU Reception Window C-plane DL +T2a_max_cp_dl=562 #in T2a_max_up + Tcp_adv_dl as per Annex B +T2a_min_cp_dl=331 #in T2a_min_up + Tcp_adv_dl as per Annex B +########################################################### + diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/1/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_du.cfg b/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_du.cfg new file mode 100644 index 0000000..5c067f4 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_du.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=0 # All O-DU(0) | O-RU(1) +instanceId=0 # 0,1,2,... in case more than 1 application started on the same system +ioCore=5 # core id +ioWorker=0x2000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_du.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:01.0 +#PciBusAddoXu0Vf1=0000:51:01.1 +#PciBusAddoXu0Vf2=0000:51:01.2 +#PciBusAddoXu0Vf3=0000:51:01.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:01.4 +#PciBusAddoXu1Vf1=0000:51:01.5 +#PciBusAddoXu1Vf2=0000:51:01.6 +#PciBusAddoXu1Vf3=0000:51:01.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:02.0 +#PciBusAddoXu2Vf1=0000:51:02.1 +#PciBusAddoXu2Vf2=0000:51:02.2 +#PciBusAddoXu2Vf3=0000:51:02.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:01 +oXuRem0Mac1=00:11:22:33:00:11 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:21 +oXuRem0Mac3=00:11:22:33:00:31 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:01 +oXuRem1Mac1=00:11:22:33:01:11 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:21 +oXuRem1Mac3=00:11:22:33:01:31 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:01 +oXuRem2Mac1=00:11:22:33:02:11 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:21 +oXuRem2Mac3=00:11:22:33:02:31 diff --git a/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_ru.cfg b/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_ru.cfg new file mode 100644 index 0000000..1ab0180 --- /dev/null +++ b/fhi_lib/app/usecase/lte_b/mu0_5mhz/usecase_ru.cfg @@ -0,0 +1,68 @@ +#****************************************************************************** +# +# Copyright (c) 2019 Intel. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#******************************************************************************/ +# This is simple configuration file. Use '#' sign for comments +appMode=1 # All O-DU(0) | O-RU(1) +instanceId=1 # 0,1,2,... in case more than 1 application started on the same system +ioCore=15 # core id +ioWorker=0x800000000 # mask [0- no workers] + +oXuNum=1 # numbers of O-RU connected to O-DU + +oXuEthLinkSpeed=25 # 10G,25G,40G,100G speed of Physical connection on O-RU +oXuLinesNumber=1 # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) + +oXuCfgFile0=./config_file_o_ru.dat #O-RU0 + +#O-XU 0 +#PciBusAddoXu0Vf0=0000:51:11.0 +#PciBusAddoXu0Vf1=0000:51:11.1 +#PciBusAddoXu0Vf2=0000:51:11.2 +#PciBusAddoXu0Vf3=0000:51:11.3 + +#O-XU 1 +#PciBusAddoXu1Vf0=0000:51:11.4 +#PciBusAddoXu1Vf1=0000:51:11.5 +#PciBusAddoXu1Vf2=0000:51:11.6 +#PciBusAddoXu1Vf3=0000:51:11.7 + +#O-XU 2 +#PciBusAddoXu2Vf0=0000:51:12.0 +#PciBusAddoXu2Vf1=0000:51:12.1 +#PciBusAddoXu2Vf2=0000:51:12.2 +#PciBusAddoXu2Vf3=0000:51:12.3 + +# remote O-XU 0 Eth Link 0 +oXuRem0Mac0=00:11:22:33:00:00 +oXuRem0Mac1=00:11:22:33:00:10 +# remote O-XU 0 Eth Link 1 +oXuRem0Mac2=00:11:22:33:00:20 +oXuRem0Mac3=00:11:22:33:00:30 + +# remote O-XU 1 Eth Link 0 +oXuRem1Mac0=00:11:22:33:01:00 +oXuRem1Mac1=00:11:22:33:01:10 +# remote O-XU 1 Eth Link 1 +oXuRem1Mac2=00:11:22:33:01:20 +oXuRem1Mac3=00:11:22:33:01:30 + +# remote O-XU 2 Eth Link 0 +oXuRem2Mac0=00:11:22:33:02:00 +oXuRem2Mac1=00:11:22:33:02:10 +# remote O-XU 2 Eth Link 1 +oXuRem2Mac2=00:11:22:33:02:20 +oXuRem2Mac3=00:11:22:33:02:30 diff --git a/fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_ru.dat b/fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_ru.dat deleted file mode 100644 index 5a5d228..0000000 --- a/fhi_lib/app/usecase/mu0_10mhz/12/config_file_o_ru.dat +++ /dev/null @@ -1,217 +0,0 @@ -#****************************************************************************** -# -# Copyright (c) 2019 Intel. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#******************************************************************************/ - - -# This is simple configuration file. Use '#' sign for comments -instanceId=1 # 0,1,2,... in case more than 1 application started on the same system -appMode=1 # O-DU(0) | O-RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=10 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=1024 -nULFftSize=1024 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=10 -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_10mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_10mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_10mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_10mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_10mhz/ant_0.bin #CC1 -antC5=./usecase/mu0_10mhz/ant_1.bin #CC1 -antC6=./usecase/mu0_10mhz/ant_2.bin #CC1 -antC7=./usecase/mu0_10mhz/ant_3.bin #CC1 -antC8=./usecase/mu0_10mhz/ant_0.bin #CC2 -antC9=./usecase/mu0_10mhz/ant_1.bin #CC2 -antC10=./usecase/mu0_10mhz/ant_2.bin #CC2 -antC11=./usecase/mu0_10mhz/ant_3.bin #CC2 -antC12=./usecase/mu0_10mhz/ant_0.bin #CC3 -antC13=./usecase/mu0_10mhz/ant_1.bin #CC3 -antC14=./usecase/mu0_10mhz/ant_2.bin #CC3 -antC15=./usecase/mu0_10mhz/ant_3.bin #CC3 -antC16=./usecase/mu0_10mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_10mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_10mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_10mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_10mhz/ant_0.bin #CC5 -antC21=./usecase/mu0_10mhz/ant_1.bin #CC5 -antC22=./usecase/mu0_10mhz/ant_2.bin #CC5 -antC23=./usecase/mu0_10mhz/ant_3.bin #CC5 -antC24=./usecase/mu0_10mhz/ant_0.bin #CC6 -antC25=./usecase/mu0_10mhz/ant_1.bin #CC6 -antC26=./usecase/mu0_10mhz/ant_2.bin #CC6 -antC27=./usecase/mu0_10mhz/ant_3.bin #CC6 -antC28=./usecase/mu0_10mhz/ant_0.bin #CC7 -antC29=./usecase/mu0_10mhz/ant_1.bin #CC7 -antC30=./usecase/mu0_10mhz/ant_2.bin #CC7 -antC31=./usecase/mu0_10mhz/ant_3.bin #CC7 -antC32=./usecase/mu0_10mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_10mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_10mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_10mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_10mhz/ant_0.bin #CC9 -antC37=./usecase/mu0_10mhz/ant_1.bin #CC9 -antC38=./usecase/mu0_10mhz/ant_2.bin #CC9 -antC39=./usecase/mu0_10mhz/ant_3.bin #CC9 -antC40=./usecase/mu0_10mhz/ant_0.bin #CC10 -antC41=./usecase/mu0_10mhz/ant_1.bin #CC10 -antC42=./usecase/mu0_10mhz/ant_2.bin #CC10 -antC43=./usecase/mu0_10mhz/ant_3.bin #CC10 -antC44=./usecase/mu0_10mhz/ant_0.bin #CC11 -antC45=./usecase/mu0_10mhz/ant_1.bin #CC11 -antC46=./usecase/mu0_10mhz/ant_2.bin #CC11 -antC47=./usecase/mu0_10mhz/ant_3.bin #CC11 - -rachEanble=1 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -antPrachC0=./usecase/mu0_10mhz/ant_0.bin -antPrachC1=./usecase/mu0_10mhz/ant_1.bin -antPrachC2=./usecase/mu0_10mhz/ant_2.bin -antPrachC3=./usecase/mu0_10mhz/ant_3.bin -antPrachC4=./usecase/mu0_10mhz/ant_0.bin -antPrachC5=./usecase/mu0_10mhz/ant_1.bin -antPrachC6=./usecase/mu0_10mhz/ant_2.bin -antPrachC7=./usecase/mu0_10mhz/ant_3.bin -antPrachC8=./usecase/mu0_10mhz/ant_0.bin -antPrachC9=./usecase/mu0_10mhz/ant_1.bin -antPrachC10=./usecase/mu0_10mhz/ant_2.bin -antPrachC11=./usecase/mu0_10mhz/ant_3.bin -antPrachC12=./usecase/mu0_10mhz/ant_0.bin -antPrachC13=./usecase/mu0_10mhz/ant_1.bin -antPrachC14=./usecase/mu0_10mhz/ant_2.bin -antPrachC15=./usecase/mu0_10mhz/ant_3.bin -antPrachC16=./usecase/mu0_10mhz/ant_0.bin -antPrachC17=./usecase/mu0_10mhz/ant_1.bin -antPrachC18=./usecase/mu0_10mhz/ant_2.bin -antPrachC19=./usecase/mu0_10mhz/ant_3.bin -antPrachC20=./usecase/mu0_10mhz/ant_0.bin -antPrachC21=./usecase/mu0_10mhz/ant_1.bin -antPrachC22=./usecase/mu0_10mhz/ant_2.bin -antPrachC23=./usecase/mu0_10mhz/ant_3.bin -antPrachC24=./usecase/mu0_10mhz/ant_0.bin -antPrachC25=./usecase/mu0_10mhz/ant_1.bin -antPrachC26=./usecase/mu0_10mhz/ant_2.bin -antPrachC27=./usecase/mu0_10mhz/ant_3.bin -antPrachC28=./usecase/mu0_10mhz/ant_0.bin -antPrachC29=./usecase/mu0_10mhz/ant_1.bin -antPrachC30=./usecase/mu0_10mhz/ant_2.bin -antPrachC31=./usecase/mu0_10mhz/ant_3.bin -antPrachC32=./usecase/mu0_10mhz/ant_0.bin -antPrachC33=./usecase/mu0_10mhz/ant_1.bin -antPrachC34=./usecase/mu0_10mhz/ant_2.bin -antPrachC35=./usecase/mu0_10mhz/ant_3.bin -antPrachC36=./usecase/mu0_10mhz/ant_0.bin -antPrachC37=./usecase/mu0_10mhz/ant_1.bin -antPrachC38=./usecase/mu0_10mhz/ant_2.bin -antPrachC39=./usecase/mu0_10mhz/ant_3.bin -antPrachC40=./usecase/mu0_10mhz/ant_0.bin -antPrachC41=./usecase/mu0_10mhz/ant_1.bin -antPrachC42=./usecase/mu0_10mhz/ant_2.bin -antPrachC43=./usecase/mu0_10mhz/ant_3.bin -antPrachC44=./usecase/mu0_10mhz/ant_0.bin -antPrachC45=./usecase/mu0_10mhz/ant_1.bin -antPrachC46=./usecase/mu0_10mhz/ant_2.bin -antPrachC47=./usecase/mu0_10mhz/ant_3.bin - - - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=1 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary -bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode - -CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_0.dat b/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_0.dat deleted file mode 100644 index e32337d..0000000 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_0.dat +++ /dev/null @@ -1,224 +0,0 @@ -####################################################################### -# -# -# -####################################################################### - -# This is simple configuration file. Use '#' sign for comments -instanceId=0 # 0,1,2,... in case more than 1 application started on the same system -appMode=0 # lls-CU(0) | RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=2048 -nULFftSize=2048 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=5 - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=20 #number of slots per IQ files -#fd 10Mhz 2 -#antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC4=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC5=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC6=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC7=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC8=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC9=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC10=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC11=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC12=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC13=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC14=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC15=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC16=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC17=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC18=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC19=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC20=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC21=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC22=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC23=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC24=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC25=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC26=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC27=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC28=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC29=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC30=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC31=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC32=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC33=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC34=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC35=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC36=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC37=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC38=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC39=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC40=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC41=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC42=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC43=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC44=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC45=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC46=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC47=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_3.bin #CC0 - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_0.bin #CC0 - -#antC4=../usecase/mu0_20mhz/12/ant_4.bin #CC1 -#antC5=../usecase/mu0_20mhz/12/ant_5.bin #CC1 -#antC6=../usecase/mu0_20mhz/12/ant_6.bin #CC1 -#antC7=../usecase/mu0_20mhz/12/ant_7.bin #CC1 -#antC8=../usecase/mu0_20mhz/12/ant_8.bin #CC2 -#antC9=../usecase/mu0_20mhz/12/ant_9.bin #CC2 -#antC10=../usecase/mu0_20mhz/12/ant_10.bin #CC2 -#antC11=../usecase/mu0_20mhz/12/ant_11.bin #CC2 -#antC12=../usecase/mu0_20mhz/12/ant_12.bin #CC3 -#antC13=../usecase/mu0_20mhz/12/ant_13.bin #CC3 -#antC14=../usecase/mu0_20mhz/12/ant_14.bin #CC3 -#antC15=../usecase/mu0_20mhz/12/ant_15.bin #CC3 -#antC16=../usecase/mu0_20mhz/12/ant_0.bin #CC4 -#antC17=../usecase/mu0_20mhz/12/ant_1.bin #CC4 -#antC18=../usecase/mu0_20mhz/12/ant_2.bin #CC4 -#antC19=../usecase/mu0_20mhz/12/ant_3.bin #CC4 -#antC20=../usecase/mu0_20mhz/12/ant_4.bin #CC5 -#antC21=../usecase/mu0_20mhz/12/ant_5.bin #CC5 -#antC22=../usecase/mu0_20mhz/12/ant_6.bin #CC5 -#antC23=../usecase/mu0_20mhz/12/ant_7.bin #CC5 -#antC24=../usecase/mu0_20mhz/12/ant_8.bin #CC6 -#antC25=../usecase/mu0_20mhz/12/ant_9.bin #CC6 -#antC26=../usecase/mu0_20mhz/12/ant_10.bin #CC6 -#antC27=../usecase/mu0_20mhz/12/ant_11.bin #CC6 -#antC28=../usecase/mu0_20mhz/12/ant_12.bin #CC7 -#antC29=../usecase/mu0_20mhz/12/ant_13.bin #CC7 -#antC30=../usecase/mu0_20mhz/12/ant_14.bin #CC7 -#antC31=../usecase/mu0_20mhz/12/ant_15.bin #CC7 -#antC32=../usecase/mu0_20mhz/12/ant_0.bin #CC8 -#antC33=../usecase/mu0_20mhz/12/ant_1.bin #CC8 -#antC34=../usecase/mu0_20mhz/12/ant_2.bin #CC8 -#antC35=../usecase/mu0_20mhz/12/ant_3.bin #CC8 -#antC36=../usecase/mu0_20mhz/12/ant_4.bin #CC9 -#antC37=../usecase/mu0_20mhz/12/ant_5.bin #CC9 -#antC38=../usecase/mu0_20mhz/12/ant_6.bin #CC9 -#antC39=../usecase/mu0_20mhz/12/ant_7.bin #CC9 -#antC40=../usecase/mu0_20mhz/12/ant_8.bin #CC10 -#antC41=../usecase/mu0_20mhz/12/ant_9.bin #CC10 -#antC42=../usecase/mu0_20mhz/12/ant_10.bin #CC10 -#antC43=../usecase/mu0_20mhz/12/ant_11.bin #CC10 -#antC44=../usecase/mu0_20mhz/12/ant_12.bin #CC11 -#antC45=../usecase/mu0_20mhz/12/ant_13.bin #CC11 -#antC46=../usecase/mu0_20mhz/12/ant_14.bin #CC11 -#antC47=../usecase/mu0_20mhz/12/ant_15.bin #CC11 - -rachEanble=0 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary - -CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_1.dat b/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_1.dat deleted file mode 100644 index dd08680..0000000 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_du_1.dat +++ /dev/null @@ -1,224 +0,0 @@ -####################################################################### -# -# -# -####################################################################### - -# This is simple configuration file. Use '#' sign for comments -instanceId=1 # 0,1,2,... in case more than 1 application started on the same system -appMode=0 # lls-CU(0) | RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=2048 -nULFftSize=2048 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=15 - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=20 #number of slots per IQ files -#fd 10Mhz 2 -#antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC4=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC5=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC6=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC7=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC8=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC9=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC10=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC11=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC12=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC13=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC14=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC15=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC16=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC17=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC18=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC19=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC20=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC21=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC22=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC23=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC24=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC25=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC26=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC27=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC28=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC29=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC30=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC31=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC32=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC33=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC34=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC35=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC36=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC37=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC38=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC39=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC40=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC41=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC42=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC43=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC44=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC45=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC46=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC47=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_3.bin #CC0 - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_0.bin #CC0 - -#antC4=../usecase/mu0_20mhz/12/ant_4.bin #CC1 -#antC5=../usecase/mu0_20mhz/12/ant_5.bin #CC1 -#antC6=../usecase/mu0_20mhz/12/ant_6.bin #CC1 -#antC7=../usecase/mu0_20mhz/12/ant_7.bin #CC1 -#antC8=../usecase/mu0_20mhz/12/ant_8.bin #CC2 -#antC9=../usecase/mu0_20mhz/12/ant_9.bin #CC2 -#antC10=../usecase/mu0_20mhz/12/ant_10.bin #CC2 -#antC11=../usecase/mu0_20mhz/12/ant_11.bin #CC2 -#antC12=../usecase/mu0_20mhz/12/ant_12.bin #CC3 -#antC13=../usecase/mu0_20mhz/12/ant_13.bin #CC3 -#antC14=../usecase/mu0_20mhz/12/ant_14.bin #CC3 -#antC15=../usecase/mu0_20mhz/12/ant_15.bin #CC3 -#antC16=../usecase/mu0_20mhz/12/ant_0.bin #CC4 -#antC17=../usecase/mu0_20mhz/12/ant_1.bin #CC4 -#antC18=../usecase/mu0_20mhz/12/ant_2.bin #CC4 -#antC19=../usecase/mu0_20mhz/12/ant_3.bin #CC4 -#antC20=../usecase/mu0_20mhz/12/ant_4.bin #CC5 -#antC21=../usecase/mu0_20mhz/12/ant_5.bin #CC5 -#antC22=../usecase/mu0_20mhz/12/ant_6.bin #CC5 -#antC23=../usecase/mu0_20mhz/12/ant_7.bin #CC5 -#antC24=../usecase/mu0_20mhz/12/ant_8.bin #CC6 -#antC25=../usecase/mu0_20mhz/12/ant_9.bin #CC6 -#antC26=../usecase/mu0_20mhz/12/ant_10.bin #CC6 -#antC27=../usecase/mu0_20mhz/12/ant_11.bin #CC6 -#antC28=../usecase/mu0_20mhz/12/ant_12.bin #CC7 -#antC29=../usecase/mu0_20mhz/12/ant_13.bin #CC7 -#antC30=../usecase/mu0_20mhz/12/ant_14.bin #CC7 -#antC31=../usecase/mu0_20mhz/12/ant_15.bin #CC7 -#antC32=../usecase/mu0_20mhz/12/ant_0.bin #CC8 -#antC33=../usecase/mu0_20mhz/12/ant_1.bin #CC8 -#antC34=../usecase/mu0_20mhz/12/ant_2.bin #CC8 -#antC35=../usecase/mu0_20mhz/12/ant_3.bin #CC8 -#antC36=../usecase/mu0_20mhz/12/ant_4.bin #CC9 -#antC37=../usecase/mu0_20mhz/12/ant_5.bin #CC9 -#antC38=../usecase/mu0_20mhz/12/ant_6.bin #CC9 -#antC39=../usecase/mu0_20mhz/12/ant_7.bin #CC9 -#antC40=../usecase/mu0_20mhz/12/ant_8.bin #CC10 -#antC41=../usecase/mu0_20mhz/12/ant_9.bin #CC10 -#antC42=../usecase/mu0_20mhz/12/ant_10.bin #CC10 -#antC43=../usecase/mu0_20mhz/12/ant_11.bin #CC10 -#antC44=../usecase/mu0_20mhz/12/ant_12.bin #CC11 -#antC45=../usecase/mu0_20mhz/12/ant_13.bin #CC11 -#antC46=../usecase/mu0_20mhz/12/ant_14.bin #CC11 -#antC47=../usecase/mu0_20mhz/12/ant_15.bin #CC11 - -rachEanble=0 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary - -CPenable=1 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru.dat b/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru.dat deleted file mode 100644 index 023bf6d..0000000 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru.dat +++ /dev/null @@ -1,230 +0,0 @@ -#****************************************************************************** -# -# Copyright (c) 2019 Intel. -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#******************************************************************************/ - - -# This is simple configuration file. Use '#' sign for comments -instanceId=1 # 0,1,2,... in case more than 1 application started on the same system -appMode=1 # O-DU(0) | O-RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=12 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) or number of Digital streams for Category B - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=2048 -nULFftSize=2048 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=15 - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=40 #number of slots per IQ files - -antC0=./usecase/mu0_20mhz/ant_0.bin #CC0 -antC1=./usecase/mu0_20mhz/ant_1.bin #CC0 -antC2=./usecase/mu0_20mhz/ant_2.bin #CC0 -antC3=./usecase/mu0_20mhz/ant_3.bin #CC0 -antC4=./usecase/mu0_20mhz/ant_0.bin #CC1 -antC5=./usecase/mu0_20mhz/ant_1.bin #CC1 -antC6=./usecase/mu0_20mhz/ant_2.bin #CC1 -antC7=./usecase/mu0_20mhz/ant_3.bin #CC1 -antC8=./usecase/mu0_20mhz/ant_0.bin #CC2 -antC9=./usecase/mu0_20mhz/ant_1.bin #CC2 -antC10=./usecase/mu0_20mhz/ant_2.bin #CC2 -antC11=./usecase/mu0_20mhz/ant_3.bin #CC2 -antC12=./usecase/mu0_20mhz/ant_0.bin #CC3 -antC13=./usecase/mu0_20mhz/ant_1.bin #CC3 -antC14=./usecase/mu0_20mhz/ant_2.bin #CC3 -antC15=./usecase/mu0_20mhz/ant_3.bin #CC3 -antC16=./usecase/mu0_20mhz/ant_0.bin #CC4 -antC17=./usecase/mu0_20mhz/ant_1.bin #CC4 -antC18=./usecase/mu0_20mhz/ant_2.bin #CC4 -antC19=./usecase/mu0_20mhz/ant_3.bin #CC4 -antC20=./usecase/mu0_20mhz/ant_0.bin #CC5 -antC21=./usecase/mu0_20mhz/ant_1.bin #CC5 -antC22=./usecase/mu0_20mhz/ant_2.bin #CC5 -antC23=./usecase/mu0_20mhz/ant_3.bin #CC5 -antC24=./usecase/mu0_20mhz/ant_0.bin #CC6 -antC25=./usecase/mu0_20mhz/ant_1.bin #CC6 -antC26=./usecase/mu0_20mhz/ant_2.bin #CC6 -antC27=./usecase/mu0_20mhz/ant_3.bin #CC6 -antC28=./usecase/mu0_20mhz/ant_0.bin #CC7 -antC29=./usecase/mu0_20mhz/ant_1.bin #CC7 -antC30=./usecase/mu0_20mhz/ant_2.bin #CC7 -antC31=./usecase/mu0_20mhz/ant_3.bin #CC7 -antC32=./usecase/mu0_20mhz/ant_0.bin #CC8 -antC33=./usecase/mu0_20mhz/ant_1.bin #CC8 -antC34=./usecase/mu0_20mhz/ant_2.bin #CC8 -antC35=./usecase/mu0_20mhz/ant_3.bin #CC8 -antC36=./usecase/mu0_20mhz/ant_0.bin #CC9 -antC37=./usecase/mu0_20mhz/ant_1.bin #CC9 -antC38=./usecase/mu0_20mhz/ant_2.bin #CC9 -antC39=./usecase/mu0_20mhz/ant_3.bin #CC9 -antC40=./usecase/mu0_20mhz/ant_0.bin #CC10 -antC41=./usecase/mu0_20mhz/ant_1.bin #CC10 -antC42=./usecase/mu0_20mhz/ant_2.bin #CC10 -antC43=./usecase/mu0_20mhz/ant_3.bin #CC10 -antC44=./usecase/mu0_20mhz/ant_0.bin #CC11 -antC45=./usecase/mu0_20mhz/ant_1.bin #CC11 -antC46=./usecase/mu0_20mhz/ant_2.bin #CC11 -antC47=./usecase/mu0_20mhz/ant_3.bin #CC11 - -rachEanble=1 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -antPrachC0=./usecase/mu0_20mhz/ant_0.bin -antPrachC1=./usecase/mu0_20mhz/ant_1.bin -antPrachC2=./usecase/mu0_20mhz/ant_2.bin -antPrachC3=./usecase/mu0_20mhz/ant_3.bin -antPrachC4=./usecase/mu0_20mhz/ant_0.bin -antPrachC5=./usecase/mu0_20mhz/ant_1.bin -antPrachC6=./usecase/mu0_20mhz/ant_2.bin -antPrachC7=./usecase/mu0_20mhz/ant_3.bin -antPrachC8=./usecase/mu0_20mhz/ant_0.bin -antPrachC9=./usecase/mu0_20mhz/ant_1.bin -antPrachC10=./usecase/mu0_20mhz/ant_2.bin -antPrachC11=./usecase/mu0_20mhz/ant_3.bin -antPrachC12=./usecase/mu0_20mhz/ant_0.bin -antPrachC13=./usecase/mu0_20mhz/ant_1.bin -antPrachC14=./usecase/mu0_20mhz/ant_2.bin -antPrachC15=./usecase/mu0_20mhz/ant_3.bin -antPrachC16=./usecase/mu0_20mhz/ant_0.bin -antPrachC17=./usecase/mu0_20mhz/ant_1.bin -antPrachC18=./usecase/mu0_20mhz/ant_2.bin -antPrachC19=./usecase/mu0_20mhz/ant_3.bin -antPrachC20=./usecase/mu0_20mhz/ant_0.bin -antPrachC21=./usecase/mu0_20mhz/ant_1.bin -antPrachC22=./usecase/mu0_20mhz/ant_2.bin -antPrachC23=./usecase/mu0_20mhz/ant_3.bin -antPrachC24=./usecase/mu0_20mhz/ant_0.bin -antPrachC25=./usecase/mu0_20mhz/ant_1.bin -antPrachC26=./usecase/mu0_20mhz/ant_2.bin -antPrachC27=./usecase/mu0_20mhz/ant_3.bin -antPrachC28=./usecase/mu0_20mhz/ant_0.bin -antPrachC29=./usecase/mu0_20mhz/ant_1.bin -antPrachC30=./usecase/mu0_20mhz/ant_2.bin -antPrachC31=./usecase/mu0_20mhz/ant_3.bin -antPrachC32=./usecase/mu0_20mhz/ant_0.bin -antPrachC33=./usecase/mu0_20mhz/ant_1.bin -antPrachC34=./usecase/mu0_20mhz/ant_2.bin -antPrachC35=./usecase/mu0_20mhz/ant_3.bin -antPrachC36=./usecase/mu0_20mhz/ant_0.bin -antPrachC37=./usecase/mu0_20mhz/ant_1.bin -antPrachC38=./usecase/mu0_20mhz/ant_2.bin -antPrachC39=./usecase/mu0_20mhz/ant_3.bin -antPrachC40=./usecase/mu0_20mhz/ant_0.bin -antPrachC41=./usecase/mu0_20mhz/ant_1.bin -antPrachC42=./usecase/mu0_20mhz/ant_2.bin -antPrachC43=./usecase/mu0_20mhz/ant_3.bin -antPrachC44=./usecase/mu0_20mhz/ant_0.bin -antPrachC45=./usecase/mu0_20mhz/ant_1.bin -antPrachC46=./usecase/mu0_20mhz/ant_2.bin -antPrachC47=./usecase/mu0_20mhz/ant_3.bin - -########################################################### -##Section Settings -DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used - -nPrbElemDl=1 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemDl0=0,75,0,14,0,1,0,16,1 -nPrbElemUl=1 -#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType -# weight base beams -PrbElemUl0=0,75,0,14,0,1,0,16,1 -########################################################### - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=1 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary -bbdevMode=-1 #bbdev mode, -1 = not use bbdev, 0: use software mode, 1: use hardware mode - -CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -totalBFWeights=32 # Total number of Beamforming Weights on RU -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_0.dat b/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_0.dat deleted file mode 100644 index ae8b5d4..0000000 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_0.dat +++ /dev/null @@ -1,274 +0,0 @@ -####################################################################### -# -# -# -####################################################################### - -# This is simple configuration file. Use '#' sign for comments -instanceId=0 # 0,1,2,... in case more than 1 application started on the same system -appMode=1 # lls-CU(0) | RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=2048 -nULFftSize=2048 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=3 - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=20 #number of slots per IQ files -#fd 10Mhz 2 -#antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC4=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC5=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC6=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC7=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC8=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC9=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC10=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC11=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC12=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC13=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC14=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC15=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC16=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC17=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC18=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC19=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC20=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC21=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC22=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC23=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC24=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC25=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC26=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC27=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC28=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC29=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC30=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC31=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC32=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC33=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC34=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC35=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC36=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC37=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC38=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC39=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC40=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC41=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC42=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC43=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC44=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC45=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC46=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC47=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_3.bin #CC0 - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_0.bin #CC0 - -#antC4=../usecase/mu0_20mhz/12/ant_4.bin #CC1 -#antC5=../usecase/mu0_20mhz/12/ant_5.bin #CC1 -#antC6=../usecase/mu0_20mhz/12/ant_6.bin #CC1 -#antC7=../usecase/mu0_20mhz/12/ant_7.bin #CC1 -#antC8=../usecase/mu0_20mhz/12/ant_8.bin #CC2 -#antC9=../usecase/mu0_20mhz/12/ant_9.bin #CC2 -#antC10=../usecase/mu0_20mhz/12/ant_10.bin #CC2 -#antC11=../usecase/mu0_20mhz/12/ant_11.bin #CC2 -#antC12=../usecase/mu0_20mhz/12/ant_12.bin #CC3 -#antC13=../usecase/mu0_20mhz/12/ant_13.bin #CC3 -#antC14=../usecase/mu0_20mhz/12/ant_14.bin #CC3 -#antC15=../usecase/mu0_20mhz/12/ant_15.bin #CC3 -#antC16=../usecase/mu0_20mhz/12/ant_0.bin #CC4 -#antC17=../usecase/mu0_20mhz/12/ant_1.bin #CC4 -#antC18=../usecase/mu0_20mhz/12/ant_2.bin #CC4 -#antC19=../usecase/mu0_20mhz/12/ant_3.bin #CC4 -#antC20=../usecase/mu0_20mhz/12/ant_4.bin #CC5 -#antC21=../usecase/mu0_20mhz/12/ant_5.bin #CC5 -#antC22=../usecase/mu0_20mhz/12/ant_6.bin #CC5 -#antC23=../usecase/mu0_20mhz/12/ant_7.bin #CC5 -#antC24=../usecase/mu0_20mhz/12/ant_8.bin #CC6 -#antC25=../usecase/mu0_20mhz/12/ant_9.bin #CC6 -#antC26=../usecase/mu0_20mhz/12/ant_10.bin #CC6 -#antC27=../usecase/mu0_20mhz/12/ant_11.bin #CC6 -#antC28=../usecase/mu0_20mhz/12/ant_12.bin #CC7 -#antC29=../usecase/mu0_20mhz/12/ant_13.bin #CC7 -#antC30=../usecase/mu0_20mhz/12/ant_14.bin #CC7 -#antC31=../usecase/mu0_20mhz/12/ant_15.bin #CC7 -#antC32=../usecase/mu0_20mhz/12/ant_0.bin #CC8 -#antC33=../usecase/mu0_20mhz/12/ant_1.bin #CC8 -#antC34=../usecase/mu0_20mhz/12/ant_2.bin #CC8 -#antC35=../usecase/mu0_20mhz/12/ant_3.bin #CC8 -#antC36=../usecase/mu0_20mhz/12/ant_4.bin #CC9 -#antC37=../usecase/mu0_20mhz/12/ant_5.bin #CC9 -#antC38=../usecase/mu0_20mhz/12/ant_6.bin #CC9 -#antC39=../usecase/mu0_20mhz/12/ant_7.bin #CC9 -#antC40=../usecase/mu0_20mhz/12/ant_8.bin #CC10 -#antC41=../usecase/mu0_20mhz/12/ant_9.bin #CC10 -#antC42=../usecase/mu0_20mhz/12/ant_10.bin #CC10 -#antC43=../usecase/mu0_20mhz/12/ant_11.bin #CC10 -#antC44=../usecase/mu0_20mhz/12/ant_12.bin #CC11 -#antC45=../usecase/mu0_20mhz/12/ant_13.bin #CC11 -#antC46=../usecase/mu0_20mhz/12/ant_14.bin #CC11 -#antC47=../usecase/mu0_20mhz/12/ant_15.bin #CC11 - -rachEanble=0 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -antPrachC0=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC1=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC2=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC3=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC4=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC5=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC6=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC7=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC8=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC9=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC10=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC11=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC12=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC13=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC14=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC15=../usecase/mu0_20mhz/12/ant_15.bin -antPrachC16=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC17=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC18=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC19=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC20=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC21=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC22=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC23=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC24=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC25=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC26=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC27=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC28=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC29=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC30=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC31=../usecase/mu0_20mhz/12/ant_15.bin -antPrachC32=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC33=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC34=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC35=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC36=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC37=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC38=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC39=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC40=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC41=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC42=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC43=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC44=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC45=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC46=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC47=../usecase/mu0_20mhz/12/ant_15.bin - - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary - -CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_1.dat b/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_1.dat deleted file mode 100644 index 157a64e..0000000 --- a/fhi_lib/app/usecase/mu0_20mhz/12/config_file_o_ru_1.dat +++ /dev/null @@ -1,274 +0,0 @@ -####################################################################### -# -# -# -####################################################################### - -# This is simple configuration file. Use '#' sign for comments -instanceId=1 # 0,1,2,... in case more than 1 application started on the same system -appMode=1 # lls-CU(0) | RU(1) -xranMode=0 # Category A (0) (precoder in lls-CU) | Category B (1) (precoder in RU) -ccNum=6 # Number of Componnent Carriers (CC) per ETH port with XRAN protocol (default:1 max: 12) -antNum=4 # Number of Antennas per CC (default: 4) - -##Numerology -mu=0 #15Khz Sub Carrier Spacing -ttiPeriod=1000 # in us TTI period (15Khz default 1000us) -nDLAbsFrePointA=2645460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nULAbsFrePointA=2525460 #nAbsFrePointA - Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 -nDLBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nULBandwidth=20 #Carrier bandwidth for in MHz. Value: 5->400 -nDLFftSize=2048 -nULFftSize=2048 - -nFrameDuplexType=0 # 0 - FDD 1 - TDD -nTddPeriod=0 #TDD priod e.g. DDDS 4 - -MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protocol data unit (PDU) that can be communicated in a single - #xRAN network layer transaction. supported 1500 bytes and 9600 bytes (Jumbo Frame) -Gps_Alpha=0 #alpha and beta value as in section 9.7.2 of ORAN spec -Gps_Beta=0 - -ioCore=10 - -# Eth 0 -duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app -duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF -ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app - -#Eth 1 -duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app -duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF -ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app - -numSlots=20 #number of slots per IQ files -#fd 10Mhz 2 -#antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC0=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC1=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC2=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC3=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC4=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC5=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC6=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC7=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC8=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC9=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC10=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC11=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC12=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC13=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC14=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC15=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC16=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC17=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC18=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC19=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC20=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC21=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC22=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC23=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC24=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC25=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC26=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC27=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC28=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC29=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC30=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC31=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC32=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC33=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC34=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC35=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC36=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC37=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC38=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC39=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC40=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC41=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC42=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC43=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - -antC44=../usecase/mu0_20mhz/12/uliq0.bin #CC0 -antC45=../usecase/mu0_20mhz/12/uliq1.bin #CC0 -antC46=../usecase/mu0_20mhz/12/uliq2.bin #CC0 -antC47=../usecase/mu0_20mhz/12/uliq3.bin #CC0 - - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_1.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_2.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_3.bin #CC0 - -#antC0=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC1=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC2=../usecase/mu0_20mhz/12/ant_0.bin #CC0 -#antC3=../usecase/mu0_20mhz/12/ant_0.bin #CC0 - -#antC4=../usecase/mu0_20mhz/12/ant_4.bin #CC1 -#antC5=../usecase/mu0_20mhz/12/ant_5.bin #CC1 -#antC6=../usecase/mu0_20mhz/12/ant_6.bin #CC1 -#antC7=../usecase/mu0_20mhz/12/ant_7.bin #CC1 -#antC8=../usecase/mu0_20mhz/12/ant_8.bin #CC2 -#antC9=../usecase/mu0_20mhz/12/ant_9.bin #CC2 -#antC10=../usecase/mu0_20mhz/12/ant_10.bin #CC2 -#antC11=../usecase/mu0_20mhz/12/ant_11.bin #CC2 -#antC12=../usecase/mu0_20mhz/12/ant_12.bin #CC3 -#antC13=../usecase/mu0_20mhz/12/ant_13.bin #CC3 -#antC14=../usecase/mu0_20mhz/12/ant_14.bin #CC3 -#antC15=../usecase/mu0_20mhz/12/ant_15.bin #CC3 -#antC16=../usecase/mu0_20mhz/12/ant_0.bin #CC4 -#antC17=../usecase/mu0_20mhz/12/ant_1.bin #CC4 -#antC18=../usecase/mu0_20mhz/12/ant_2.bin #CC4 -#antC19=../usecase/mu0_20mhz/12/ant_3.bin #CC4 -#antC20=../usecase/mu0_20mhz/12/ant_4.bin #CC5 -#antC21=../usecase/mu0_20mhz/12/ant_5.bin #CC5 -#antC22=../usecase/mu0_20mhz/12/ant_6.bin #CC5 -#antC23=../usecase/mu0_20mhz/12/ant_7.bin #CC5 -#antC24=../usecase/mu0_20mhz/12/ant_8.bin #CC6 -#antC25=../usecase/mu0_20mhz/12/ant_9.bin #CC6 -#antC26=../usecase/mu0_20mhz/12/ant_10.bin #CC6 -#antC27=../usecase/mu0_20mhz/12/ant_11.bin #CC6 -#antC28=../usecase/mu0_20mhz/12/ant_12.bin #CC7 -#antC29=../usecase/mu0_20mhz/12/ant_13.bin #CC7 -#antC30=../usecase/mu0_20mhz/12/ant_14.bin #CC7 -#antC31=../usecase/mu0_20mhz/12/ant_15.bin #CC7 -#antC32=../usecase/mu0_20mhz/12/ant_0.bin #CC8 -#antC33=../usecase/mu0_20mhz/12/ant_1.bin #CC8 -#antC34=../usecase/mu0_20mhz/12/ant_2.bin #CC8 -#antC35=../usecase/mu0_20mhz/12/ant_3.bin #CC8 -#antC36=../usecase/mu0_20mhz/12/ant_4.bin #CC9 -#antC37=../usecase/mu0_20mhz/12/ant_5.bin #CC9 -#antC38=../usecase/mu0_20mhz/12/ant_6.bin #CC9 -#antC39=../usecase/mu0_20mhz/12/ant_7.bin #CC9 -#antC40=../usecase/mu0_20mhz/12/ant_8.bin #CC10 -#antC41=../usecase/mu0_20mhz/12/ant_9.bin #CC10 -#antC42=../usecase/mu0_20mhz/12/ant_10.bin #CC10 -#antC43=../usecase/mu0_20mhz/12/ant_11.bin #CC10 -#antC44=../usecase/mu0_20mhz/12/ant_12.bin #CC11 -#antC45=../usecase/mu0_20mhz/12/ant_13.bin #CC11 -#antC46=../usecase/mu0_20mhz/12/ant_14.bin #CC11 -#antC47=../usecase/mu0_20mhz/12/ant_15.bin #CC11 - -rachEanble=0 # Enable (1)| disable (0) PRACH configuration -prachConfigIndex=189 # PRACH config index as per TS36.211 - Table 5.7.1-2 : PRACH Configuration Index - -antPrachC0=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC1=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC2=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC3=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC4=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC5=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC6=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC7=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC8=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC9=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC10=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC11=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC12=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC13=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC14=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC15=../usecase/mu0_20mhz/12/ant_15.bin -antPrachC16=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC17=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC18=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC19=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC20=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC21=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC22=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC23=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC24=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC25=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC26=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC27=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC28=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC29=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC30=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC31=../usecase/mu0_20mhz/12/ant_15.bin -antPrachC32=../usecase/mu0_20mhz/12/ant_0.bin -antPrachC33=../usecase/mu0_20mhz/12/ant_1.bin -antPrachC34=../usecase/mu0_20mhz/12/ant_2.bin -antPrachC35=../usecase/mu0_20mhz/12/ant_3.bin -antPrachC36=../usecase/mu0_20mhz/12/ant_4.bin -antPrachC37=../usecase/mu0_20mhz/12/ant_5.bin -antPrachC38=../usecase/mu0_20mhz/12/ant_6.bin -antPrachC39=../usecase/mu0_20mhz/12/ant_7.bin -antPrachC40=../usecase/mu0_20mhz/12/ant_8.bin -antPrachC41=../usecase/mu0_20mhz/12/ant_9.bin -antPrachC42=../usecase/mu0_20mhz/12/ant_10.bin -antPrachC43=../usecase/mu0_20mhz/12/ant_11.bin -antPrachC44=../usecase/mu0_20mhz/12/ant_12.bin -antPrachC45=../usecase/mu0_20mhz/12/ant_13.bin -antPrachC46=../usecase/mu0_20mhz/12/ant_14.bin -antPrachC47=../usecase/mu0_20mhz/12/ant_15.bin - - -## control of IQ byte order -iqswap=0 #do swap of IQ before send buffer to eth -nebyteorderswap=1 #do swap of byte order for each I and Q from CPU byte order to network byte order - -##Debug -debugStop=0 #stop app on 1pps boundary (gps_second % 30) -debugStopCount=0 #if this value is >0 then stop app after x transmission packets, otherwise app will stop at 1pps boundary - -CPenable=0 #(1) C-Plane is enabled| (0) C-Plane is disabled -c_plane_vlan_tag=1 #VLAN Tag used for C-Plane -u_plane_vlan_tag=2 #VLAN Tag used for U-Plane - -##RU Settings -Tadv_cp_dl=25 #in us TODO: update per RU implementation - #C-Plane messages must arrive at the RU some amount of time in advance (Tcp_adv_dl) of the corresponding U-Plane messages - -#Reception Window C-plane DL -T2a_min_cp_dl=400 #in us -T2a_max_cp_dl=1120 #in us - -#Reception Window C-plane UL -T2a_min_cp_ul=400 #in us -T2a_max_cp_ul=1120 #in us - -#Reception Window U-plane -T2a_min_up=200 # in us -T2a_max_up=1120 # in us - -#Transmission Window -Ta3_min=160 #in us -Ta3_max=256 #in us - -########################################################### -##lls-CU Settings -#C-plane -#Transmission Window Fast C-plane DL -T1a_min_cp_dl=560 -T1a_max_cp_dl=800 - -##Transmission Window Fast C-plane UL -T1a_min_cp_ul=480 -T1a_max_cp_ul=560 - -#U-plane -##Transmission Window -T1a_min_up=280 -T1a_max_up=400 - -#Reception Window -Ta4_min=0 -Ta4_max=360 -########################################################### - diff --git a/fhi_lib/lib/Makefile b/fhi_lib/lib/Makefile index 579a0c6..de141bf 100644 --- a/fhi_lib/lib/Makefile +++ b/fhi_lib/lib/Makefile @@ -1,6 +1,6 @@ #/****************************************************************************** #* -#* Copyright (c) 2019 Intel. +#* Copyright (c) 2020 Intel. #* #* Licensed under the Apache License, Version 2.0 (the "License"); #* you may not use this file except in compliance with the License. @@ -56,8 +56,8 @@ ifeq ($(RTE_SDK),) endif RTE_TARGET ?= x86_64-native-linux-icc -RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk) API_DIR := $(PROJECT_DIR)/api SRC_DIR := $(PROJECT_DIR)/src ETH_DIR := $(PROJECT_DIR)/ethernet @@ -79,14 +79,31 @@ CC_SRC = $(ETH_DIR)/ethdi.c \ $(SRC_DIR)/xran_ul_tables.c \ $(SRC_DIR)/xran_frame_struct.c \ $(SRC_DIR)/xran_app_frag.c \ - $(SRC_DIR)/xran_main.c + $(SRC_DIR)/xran_dev.c \ + $(SRC_DIR)/xran_rx_proc.c \ + $(SRC_DIR)/xran_tx_proc.c \ + $(SRC_DIR)/xran_cp_proc.c \ + $(SRC_DIR)/xran_cb_proc.c \ + $(SRC_DIR)/xran_mem_mgr.c \ + $(SRC_DIR)/xran_main.c \ + $(SRC_DIR)/xran_delay_measurement.c CPP_SRC = $(SRC_DIR)/xran_compression.cpp \ $(SRC_DIR)/xran_bfp_ref.cpp \ $(SRC_DIR)/xran_bfp_cplane8.cpp \ $(SRC_DIR)/xran_bfp_cplane16.cpp \ $(SRC_DIR)/xran_bfp_cplane32.cpp \ - $(SRC_DIR)/xran_bfp_cplane64.cpp + $(SRC_DIR)/xran_bfp_cplane64.cpp \ + $(SRC_DIR)/xran_bfp_uplane_9b16rb.cpp \ + $(SRC_DIR)/xran_bfp_uplane.cpp \ + $(SRC_DIR)/xran_mod_compression.cpp + +CPP_SRC_SNC = $(SRC_DIR)/xran_compression_snc.cpp \ + $(SRC_DIR)/xran_bfp_cplane8_snc.cpp \ + $(SRC_DIR)/xran_bfp_cplane16_snc.cpp \ + $(SRC_DIR)/xran_bfp_cplane32_snc.cpp \ + $(SRC_DIR)/xran_bfp_cplane64_snc.cpp \ + $(SRC_DIR)/xran_bfp_uplane_snc.cpp CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -fdata-sections \ @@ -95,12 +112,12 @@ CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -fPIC \ -Wall \ -Wimplicit-function-declaration \ - -g -O3 -wd1786 + -g -O3 -wd1786 -mcmodel=large CPP_FLAGS := -D__STDC_LIMIT_MACROS -D__STDC_CONSTANT_MACROS -D_GNU_SOURCE -D_REENTRANT -pipe -no-prec-div \ -no-prec-div -fp-model fast=2 -fPIC \ -no-prec-sqrt -falign-functions=16 -fast-transcendentals \ - -Werror -Wno-unused-variable -std=c++11 -mcmodel=large + -Werror -Wno-unused-variable -std=c++14 -mcmodel=large INC := -I$(API_DIR) -I$(ETH_DIR) -I$(SRC_DIR) -I$(RTE_INC) DEF := @@ -111,7 +128,9 @@ else DEF += -UMLOG_ENABLED endif + #DEF += -DFCN_ADAPT +#DEF += -DFCN_1_2_6_EARLIER AS_FLAGS := AR_FLAGS := rc @@ -120,17 +139,22 @@ PROJECT_OBJ_DIR := build/obj CC_OBJS := $(patsubst %.c,%.o,$(CC_SRC)) CPP_OBJS := $(patsubst %.cpp,%.o,$(CPP_SRC)) +CPP_OBJS_SNC := $(patsubst %.cpp,%.o,$(CPP_SRC_SNC)) AS_OBJS := $(patsubst %.s,%.o,$(AS_SRC)) -OBJS := $(CC_OBJS) $(CPP_OBJS) $(AS_OBJS) $(LIBS) +OBJS := $(CC_OBJS) $(CPP_OBJS) $(CPP_OBJS_SNC) $(AS_OBJS) $(LIBS) DIRLIST := $(addprefix $(PROJECT_OBJ_DIR)/,$(sort $(dir $(OBJS)))) CC_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(CC_OBJS)) CPP_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(CPP_OBJS)) +CPP_SNC_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(CPP_OBJS_SNC)) AS_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(AS_OBJS)) -CPP_COMP := -O3 -xcore-avx512 -restrict -g -fasm-blocks +#-qopt-report=5 -qopt-matmul -qopt-report-phase=all +CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -restrict -fasm-blocks +CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -restrict -fasm-blocks CC_FLAGS_FULL := $(CC_FLAGS) $(INC) $(DEF) CPP_FLAGS_FULL := $(CPP_FLAGS) $(CPP_COMP) $(INC) $(DEF) +CPP_FLAGS_FULL_SNC := $(CPP_FLAGS) $(CPP_COMP_SNC) $(INC) $(DEF) AS_FLAGS := $(AS_FLAGS) $(INC) @@ -142,6 +166,7 @@ else CC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CC_SRC))) CPP_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CPP_SRC))) +CPP_SNC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CPP_SRC_SNC))) GENERATE_DEPS := generate_deps endif @@ -159,8 +184,11 @@ $(CC_DEPS) : $(CPP_DEPS) : @$(CPP) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(PROJECT_OBJ_DIR)/$(patsubst %.cpp,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CPP_FLAGS_FULL) >> $(PROJECT_DEP_FILE) +$(CPP_SNC_DEPS) : + @$(CPP) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(PROJECT_OBJ_DIR)/$(patsubst %.cpp,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CPP_FLAGS_FULL_SNC) >> $(PROJECT_DEP_FILE) + .PHONY : generate_deps -generate_deps : clear_dep $(CC_DEPS) $(CPP_DEPS) +generate_deps : clear_dep $(CC_DEPS) $(CPP_DEPS) $(CPP_SNC_DEPS) .PHONY : echo_start_build @@ -178,6 +206,10 @@ $(CPP_OBJTARGETS) : @echo [CPP] $(subst $(PROJECT_OBJ_DIR)/,,$@) @$(CPP) -c $(CPP_FLAGS_FULL) -o"$@" $(patsubst %.o,%.cpp,$(subst $(PROJECT_OBJ_DIR)/,,$@)) +$(CPP_SNC_OBJTARGETS) : + @echo [CPP-SNC] $(subst $(PROJECT_OBJ_DIR)/,,$@) + @$(CPP) -c $(CPP_FLAGS_FULL_SNC) -o"$@" $(patsubst %.o,%.cpp,$(subst $(PROJECT_OBJ_DIR)/,,$@)) + $(AS_OBJTARGETS) : @echo [AS] $(subst $(PROJECT_OBJ_DIR)/,,$@) @$(AS) $(AS_FLAGS) -o"$@" $(patsubst %.o,%.s,$(subst $(PROJECT_OBJ_DIR)/,,$@)) @@ -191,7 +223,7 @@ endif .PHONY: clean xclean clean: @echo [CLEAN] : $(PROJECT_NAME) - @$(RM) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) + @$(RM) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(CPP_SNC_OBJTARGETS) $(AS_OBJTARGETS) xclean: clean ifneq ($(wildcard $(PROJECT_DIR)/$(PROJECT_MAKE)),) @@ -211,10 +243,11 @@ welcome_line : debug : all release : all -$(PROJECT_BINARY) : $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) + +$(PROJECT_BINARY) : $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(CPP_SNC_OBJTARGETS) $(AS_OBJTARGETS) @echo [AR] $(subst $(BUILDDIR)/,,$@) ifeq ($(XRAN_LIB_SO),) - @$(AR) $(AR_FLAGS) $@ $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) + @$(AR) $(AR_FLAGS) $@ $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(CPP_SNC_OBJTARGETS) $(AS_OBJTARGETS) else - @$(CC) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(AS_OBJTARGETS) -shared -fPIC -o $@ + @$(CC) $(CC_OBJTARGETS) $(CPP_OBJTARGETS) $(CPP_SNC_OBJTARGETS) $(AS_OBJTARGETS) -shared -fPIC -o $@ endif diff --git a/fhi_lib/lib/api/xran_compression.h b/fhi_lib/lib/api/xran_compression.h index 816acc0..5dc088f 100644 --- a/fhi_lib/lib/api/xran_compression.h +++ b/fhi_lib/lib/api/xran_compression.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,7 +18,7 @@ /*! \file xran_compression.h - \brief External API for compading with the use BFP algorithm. + \brief External C-callable API for compression/decompression with the use BFP algorithm and Modulation compression */ #ifndef _XRAN_COMPRESSION_H_ @@ -40,6 +40,9 @@ struct xranlib_compress_request { int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */ int16_t compMethod; /*!< Compression method */ int16_t iqWidth; /*!< Bit size */ + int16_t reMask; /*!< 12-bit RE mask representing 12REs in one RB */ + int16_t csf; /*!< 1-bit constellation shift flag defined in section 5.4.7.4 */ + uint16_t ScaleFactor; /*!< Scale factor as defined in section A.5*/ int32_t len; /*!< Length of input buffer in bytes */ }; @@ -63,7 +66,9 @@ struct xranlib_decompress_request { int16_t numDataElements; /*!< number of elements in block process [UP: 24 i.e 12RE*2; CP: 16,32,64,128. i.e AntElm*2] */ int16_t compMethod; /*!< Compression method */ int16_t iqWidth; /*!< Bit size */ - + int16_t reMask; /*!< 12-bit RE mask representing 12REs in one RB */ + int16_t csf; /*!< 1-bit constellation shift flag defined in section 5.4.7.4 */ + uint16_t ScaleFactor; /*!< Scale factor as defined in section A.5*/ int32_t len; /*!< Length of input data. */ }; @@ -107,8 +112,17 @@ int32_t xranlib_compress_avx512(const struct xranlib_compress_request *request, struct xranlib_compress_response *response); int32_t +xranlib_compress_avxsnc(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response); +int32_t +xranlib_compress_bfw(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response); +int32_t xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request, struct xranlib_compress_response *response); +int32_t +xranlib_compress_avxsnc_bfw(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response); //! @} //! @{ @@ -121,7 +135,6 @@ xranlib_compress_avx512_bfw(const struct xranlib_compress_request *request, int32_t xranlib_decompress(const struct xranlib_decompress_request *request, struct xranlib_decompress_response *response); - int32_t xranlib_decompress_sse(const struct xranlib_decompress_request *request, struct xranlib_decompress_response *response); @@ -132,8 +145,17 @@ int32_t xranlib_decompress_avx512(const struct xranlib_decompress_request *request, struct xranlib_decompress_response *response); int32_t +xranlib_decompress_avxsnc(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response); +int32_t +xranlib_decompress_bfw(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response); +int32_t xranlib_decompress_avx512_bfw(const struct xranlib_decompress_request *request, struct xranlib_decompress_response *response); +int32_t +xranlib_decompress_avxsnc_bfw(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response); //! @} diff --git a/fhi_lib/lib/api/xran_compression.hpp b/fhi_lib/lib/api/xran_compression.hpp index 01f49c0..9ca8561 100644 --- a/fhi_lib/lib/api/xran_compression.hpp +++ b/fhi_lib/lib/api/xran_compression.hpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -61,7 +61,7 @@ namespace BlockFloatCompander struct CompressedData { - /// Compressed data + /// Pointer to compressed data buffer CACHE_ALIGNED uint8_t dataCompressedDataOut[k_numSampsCompressed]; CACHE_ALIGNED uint8_t *dataCompressed; /// Size of mantissa including sign bit @@ -76,7 +76,7 @@ namespace BlockFloatCompander struct ExpandedData { - /// Expanded data or input data to compressor + /// Pointer to expanded data buffer CACHE_ALIGNED int16_t dataExpandedIn[k_numSampsExpanded]; CACHE_ALIGNED int16_t *dataExpanded; @@ -94,6 +94,10 @@ namespace BlockFloatCompander void BFPCompressRef(const ExpandedData& dataIn, CompressedData* dataOut); void BFPExpandRef(const CompressedData& dataIn, ExpandedData* dataOut); + /// User-Plane specific compression and expansion functions 9b Matissa 16RB ONLY + void BFPCompressUserPlaneAvx512_9b16RB(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandUserPlaneAvx512_9b16RB(const CompressedData& dataIn, ExpandedData* dataOut); + /// User-Plane specific compression and expansion functions void BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut); void BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut); @@ -113,5 +117,25 @@ namespace BlockFloatCompander /// Control-Plane specific compression and expansion functions for 64 antennas void BFPCompressCtrlPlane64Avx512(const ExpandedData& dataIn, CompressedData* dataOut); void BFPExpandCtrlPlane64Avx512(const CompressedData& dataIn, ExpandedData* dataOut); -} + + /// User-Plane specific compression and expansion functions + void BFPCompressUserPlaneAvxSnc(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandUserPlaneAvxSnc(const CompressedData& dataIn, ExpandedData* dataOut); + + /// Control-Plane specific compression and expansion functions for 8 antennas + void BFPCompressCtrlPlane8AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandCtrlPlane8AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut); + + /// Control-Plane specific compression and expansion functions for 16 antennas + void BFPCompressCtrlPlane16AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandCtrlPlane16AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut); + + /// Control-Plane specific compression and expansion functions for 32 antennas + void BFPCompressCtrlPlane32AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandCtrlPlane32AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut); + + /// Control-Plane specific compression and expansion functions for 64 antennas + void BFPCompressCtrlPlane64AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut); + void BFPExpandCtrlPlane64AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut); +} diff --git a/fhi_lib/lib/api/xran_cp_api.h b/fhi_lib/lib/api/xran_cp_api.h index 20b79fc..c45b5b6 100644 --- a/fhi_lib/lib/api/xran_cp_api.h +++ b/fhi_lib/lib/api/xran_cp_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -32,7 +32,6 @@ extern "C" { #endif - #include "xran_fh_o_du.h" #include "xran_pkt_cp.h" #include "xran_transport.h" @@ -68,6 +67,7 @@ enum xran_cp_filterindex { XRAN_FILTERINDEX_PRACH_3 = 2, /**< UL filter for PRACH preamble format 3 */ XRAN_FILTERINDEX_PRACH_ABC = 3, /**< UL filter for PRACH preamble format A1~3, B1~4, C0, C2 */ XRAN_FILTERINDEX_NPRACH = 4, /**< UL filter for NPRACH */ + XRAN_FILTERINDEX_LTE4 = 5, /**< UL filter for PRACH preamble format LTE-4 */ XRAN_FILTERINDEX_MAX }; @@ -150,7 +150,13 @@ enum xran_cp_sectionextcmd { XRAN_CP_SECTIONEXTCMD_3 = 3, /**< DL Precoding configuration parameters and indications, not supported */ XRAN_CP_SECTIONEXTCMD_4 = 4, /**< Modulation compression parameter */ XRAN_CP_SECTIONEXTCMD_5 = 5, /**< Modulation compression additional scaling parameters */ - XRAN_CP_SECTIONEXTCMD_MAX /* 6~127 reserved for future use */ + XRAN_CP_SECTIONEXTCMD_6 = 6, /**< Non-contiguous PRB allocation */ + XRAN_CP_SECTIONEXTCMD_7 = 7, /**< Multiple-eAxC designation */ + XRAN_CP_SECTIONEXTCMD_8 = 8, /**< MMSE parameters */ + XRAN_CP_SECTIONEXTCMD_9 = 9, /**< Dynamic Spectrum Sharing parameters */ + XRAN_CP_SECTIONEXTCMD_10 = 10, /**< Multiple ports grouping */ + XRAN_CP_SECTIONEXTCMD_11 = 11, /**< Flexible BF weights */ + XRAN_CP_SECTIONEXTCMD_MAX /* 12~127 reserved for future use */ }; /** Macro to convert bfwIqWidth defined in 5.4.7.1.1, Table 5-15 */ @@ -190,6 +196,27 @@ enum xran_cp_bfa_bitwidth { #define XRAN_TXS_SMUXNOCDD 1 /**< Spatial Multiplexing (no CDD) */ #define XRAN_TXS_TXDIV 2 /**< Transmit diversity */ +/** Resource Block Group Size 5.4.7.6.1 */ +enum xran_cp_rbgsize { + XRAN_RBGSIZE_1RB = 1, /**< 1 RB */ + XRAN_RBGSIZE_2RB = 2, /**< 2 RBs */ + XRAN_RBGSIZE_3RB = 3, /**< 3 RBs */ + XRAN_RBGSIZE_4RB = 4, /**< 4 RBs */ + XRAN_RBGSIZE_6RB = 5, /**< 6 RBs */ + XRAN_RBGSIZE_8RB = 6, /**< 8 RBs */ + XRAN_RBGSIZE_16RB = 7, /**< 16 RBs */ +}; + +/** Technology for Dynamic Spectrum Sharing operation 5,4,7.9.1 */ +#define XRAN_DSSTECH_LTE 0 /**< LTE support */ +#define XRAN_DSSTECH_NR 1 /**< NR support */ + +/** The type of beam grouping 5.4.7.10.1 */ +#define XRAN_BEAMGT_COMMON 0 /** common beam */ +#define XRAN_BEAMGT_MATRIXIND 1 /** beam matrix indication */ +#define XRAN_BEAMGT_VECTORLIST 2 /** beam vector listing */ + +#define XRAN_MAX_NUMPORTC_EXT10 64 /* defined in 5.4.7.10.2 */ /** * This structure contains the information to generate the section body of C-Plane message */ @@ -221,7 +248,7 @@ struct xran_section_info { struct xran_sectionext1_info { uint16_t rbNumber; /**< number RBs to ext1 chain */ uint16_t bfwNumber; /**< number of bf weights in this section */ - uint8_t bfwiqWidth; + uint8_t bfwIqWidth; uint8_t bfwCompMeth; int16_t *p_bfwIQ; /**< pointer to formed section extention */ int16_t bfwIQ_sz; /**< size of buffer with section extention information */ @@ -276,13 +303,84 @@ struct xran_sectionext5_info { } mc[XRAN_MAX_MODCOMP_ADDPARMS]; }; +struct xran_sectionext6_info { + uint8_t rbgSize; + uint8_t pad; + uint16_t symbolMask; + uint32_t rbgMask; +}; + +struct xran_sectionext7_info { + uint16_t eAxCmask; +}; + +struct xran_sectionext8_info { + uint16_t regularizationFactor; +}; + +struct xran_sectionext9_info { + uint8_t technology; +}; + +struct xran_sectionext10_info { + uint8_t numPortc; + uint8_t beamGrpType; + uint16_t beamID[XRAN_MAX_NUMPORTC_EXT10]; +}; + +struct xran_sectionext11_info { + uint8_t RAD; + uint8_t disableBFWs; + + uint8_t numBundPrb; + uint8_t numSetBFWs; /* Total number of beam forming weights set (L) */ + + uint8_t bfwCompMeth; + uint8_t bfwIqWidth; + + int32_t totalBfwIQLen; + int32_t maxExtBufSize; /* Maximum space of external buffer */ + uint8_t *pExtBuf; /* pointer to start of external buffer */ + void *pExtBufShinfo; /* Pointer to rte_mbuf_ext_shared_info */ +}; + +union xran_ext_bfwcompparam_info { + uint8_t exponent; +// uint8_t blockScaler; /* Not supported */ +// uint8_t compBitWidthShift; /* Not supported */ +// uint8_t *pActBeamspaceCoeffMask; /* Not supported */ + }; +struct xran_ext11_prbbundle_info { + union xran_ext_bfwcompparam_info bfwCompParam; + uint16_t beamId; /* 15bits, needs to strip MSB */ + uint16_t BFWSize; /* actual size of bfws in bytes */ + uint8_t *pBFWs; /* external buffer pointer */ +}; +struct xran_sectionext11_recv_info { + uint8_t RAD; + uint8_t disableBFWs; + + uint8_t numBundPrb; + uint8_t numSetBFWs; /* Total number of beam forming weights set (L) */ + + uint8_t bfwCompMeth; + uint8_t bfwIqWidth; + + int32_t totalBfwIQLen; + int32_t maxExtBufSize; /* Maximum space of external buffer */ + uint8_t *pExtBuf; /* pointer to start of external buffer */ + void *pExtBufShinfo; /* Pointer to rte_mbuf_ext_shared_info */ + + /* For parsing */ + struct xran_ext11_prbbundle_info bundInfo[XRAN_MAX_SET_BFWS]; +}; + struct xran_sectionext_info { uint16_t type; uint16_t len; void *data; }; - /** * This structure contains the information to generate the section header of C-Plane message */ struct xran_cp_header_params { @@ -318,15 +416,8 @@ struct xran_section_gen_info { uint32_t exDataSize; /**< The number of Extensions or type 6/7 data */ /** the array to store section extension */ struct xran_section_ext_gen_info exData[XRAN_MAX_NUM_EXTENSIONS]; - - struct xran_sectionext1_info m_ext1[XRAN_MAX_NUM_EXTENSIONS]; - struct xran_sectionext2_info m_ext2[XRAN_MAX_NUM_EXTENSIONS]; - struct xran_sectionext3_info m_ext3[XRAN_MAX_NUM_EXTENSIONS]; - struct xran_sectionext4_info m_ext4[XRAN_MAX_NUM_EXTENSIONS]; - struct xran_sectionext5_info m_ext5[XRAN_MAX_NUM_EXTENSIONS]; }; - /** * This structure to hold the information to generate a C-Plane message */ struct xran_cp_gen_params { @@ -340,6 +431,45 @@ struct xran_cp_gen_params { /**< Array of the section information */ }; +/** The structure to store received section extension */ +struct xran_section_ext_recv_info { + uint16_t type; /**< the type of section extension */ + uint16_t size; + union { + struct xran_sectionext1_info ext1; + struct xran_sectionext2_info ext2; + struct xran_sectionext3_info ext3; + struct xran_sectionext4_info ext4; + struct xran_sectionext5_info ext5; + struct xran_sectionext6_info ext6; + struct xran_sectionext10_info ext10; + struct xran_sectionext11_recv_info ext11; + } u; +}; + +/** + * This structure to hold the information of received sections of C-Plane message */ +struct xran_section_recv_info { + struct xran_section_info info; /**< The information for received section */ + + int32_t numExts; + /** the array to store section extension */ + struct xran_section_ext_recv_info exts[XRAN_MAX_NUM_EXTENSIONS]; +}; + +/** + * This structure to store received C-Plane message */ +struct xran_cp_recv_params { + uint8_t dir; /**< UL or DL */ + uint8_t sectionType; /**< each section must have same type with this */ + uint16_t numSections; /**< the number of sections received */ + + struct xran_cp_header_params hdr; + /**< The information for C-Plane message header */ + struct xran_section_recv_info *sections; + /**< Array of the section information */ +}; + /** * This structure to hold the information of RB allocation from PHY * to send data for allocated RBs only. */ @@ -361,9 +491,12 @@ struct xran_cp_rbmap_list { uint8_t pad0; }; +typedef struct tagSECTION_DB_TYPE { + struct xran_sectioninfo_db* p_sectiondb_elm[XRAN_MAX_SECTIONDB_CTX][XRAN_DIR_MAX][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; +} SECTION_DB_TYPE, * PSECTION_DB_TYPE; -uint16_t xran_get_cplength(int cpLength); -int32_t xran_get_freqoffset(int freqOffset, int scs); +uint16_t xran_get_cplength(int32_t cpLength); +int32_t xran_get_freqoffset(int32_t freqOffset, int32_t scs); int32_t xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params, @@ -371,7 +504,7 @@ int32_t xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf, uint8_t seq_id); int32_t xran_parse_cp_pkt(struct rte_mbuf *mbuf, - struct xran_cp_gen_params *result, + struct xran_cp_recv_params *result, struct xran_recv_packet_info *pkt_info); int32_t xran_cp_init_sectiondb(void *pHandle); @@ -389,8 +522,8 @@ struct xran_section_info *xran_cp_iterate_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, uint32_t *next); -int xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id); -int xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id); +int32_t xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id); +int32_t xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id); int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination buffer */ uint16_t ext1_dst_len, /**< dest buffer size */ int16_t *p_bfw_iq_src, /**< source buffer of IQs */ @@ -398,8 +531,16 @@ int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination uint16_t bfwNumber, /**< number of bf weights in this set of sections */ uint8_t bfwiqWidth, /**< bit size of IQs */ uint8_t bfwCompMeth); /**< compression method */ -struct rte_mbuf *xran_attach_cp_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, +struct rte_mbuf *xran_attach_cp_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, struct rte_mbuf_ext_shared_info * p_share_data); +int32_t xran_cp_attach_ext_buf(struct rte_mbuf *mbuf, uint8_t *extbuf_start, uint16_t extbuf_len, + struct rte_mbuf_ext_shared_info *shinfo); +int32_t xran_cp_prepare_ext11_bfws(uint8_t numSetBFW, uint8_t numBFW, + uint8_t iqWidth, uint8_t compMeth, + uint8_t *dst, int16_t dst_maxlen, + struct xran_ext11_bfw_info bfwInfo[]); +int32_t xran_cp_estimate_max_set_bfws(uint8_t numBFWs, uint8_t iqWidth, + uint8_t compMeth, uint16_t mtu); #ifdef __cplusplus } diff --git a/fhi_lib/lib/api/xran_fh_o_du.h b/fhi_lib/lib/api/xran_fh_o_du.h index 6365f27..7419ae1 100644 --- a/fhi_lib/lib/api/xran_fh_o_du.h +++ b/fhi_lib/lib/api/xran_fh_o_du.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -51,6 +51,7 @@ extern "C" { #include #include + #define XRAN_STATUS_SUCCESS (0) /**< * @ingroup xran @@ -105,19 +106,18 @@ extern "C" { /** Macro to calculate Slot number */ #define XranGetSlotNum(tti, numSlotPerSfn) ((uint32_t)tti % ((uint32_t)numSlotPerSfn)) -#define XRAN_PORTS_NUM (1) /**< number of XRAN ports (aka O-RU devices) supported */ -#define XRAN_N_FE_BUF_LEN (40) /**< Number of TTIs (slots) */ -#define XRAN_MAX_SECTOR_NR (12) /**< Max sectors per XRAN port */ +#define XRAN_PORTS_NUM (4) /**< number of XRAN ports (aka O-RU|O-DU devices) supported */ +#define XRAN_ETH_PF_LINKS_NUM (4) /**< number of Physical Ethernet links per one O-RU|O-DU */ +#define XRAN_N_FE_BUF_LEN (20) /**< Number of TTIs (slots) */ +#define XRAN_MAX_SECTOR_NR (16) /**< Max sectors per XRAN port */ #define XRAN_MAX_ANTENNA_NR (16) /**< Max number of extended Antenna-Carriers: a data flow for a single antenna (or spatial stream) for a single carrier in a single sector */ -/* see 10.2 Hierarchy of Radiation Structure in O-RU (assume TX and RX pannel are the same dimensions)*/ +/* see 10.2 Hierarchy of Radiation Structure in O-RU (assume TX and RX panel are the same dimensions)*/ #define XRAN_MAX_PANEL_NR (1) /**< Max number of Panels supported per O-RU */ #define XRAN_MAX_TRX_ANTENNA_ARRAY (1) /**< Max number of TX and RX arrays per panel in O-RU */ #define XRAN_MAX_ANT_ARRAY_ELM_NR (64) /**< Maximum number of Antenna Array Elemets in Antenna Array in the O-RU */ - - #define XRAN_NUM_OF_SYMBOL_PER_SLOT (14) /**< Number of symbols per slot */ #define XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT XRAN_NUM_OF_SYMBOL_PER_SLOT /**< Max Number of SRS symbols per slot */ #define XRAN_MAX_TDD_PERIODICITY (80) /**< Max TDD pattern period */ @@ -125,8 +125,15 @@ extern "C" { #define XRAN_COMPONENT_CARRIERS_MAX (XRAN_MAX_SECTOR_NR) /**< number of CCs */ #define XRAN_NUM_OF_ANT_RADIO (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR) /**< Max Number of Antennas supported for all CC on single XRAN port */ #define XRAN_MAX_PRBS (275) /**< Max of PRBs per CC per antanna for 5G NR */ +#define XRAN_NUM_OF_SC_PER_RB (12) /**< Number of subcarriers per RB */ + +#define XRAN_MAX_SECTIONS_PER_SLOT (24) /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */ +#define XRAN_MIN_SECTIONS_PER_SLOT (6) /**< Min number of different sections in single slot (section may be equal to RB allocation for UE) */ +#define XRAN_MAX_SECTIONS_PER_SYM (XRAN_MAX_SECTIONS_PER_SLOT) /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */ +#define XRAN_MIN_SECTIONS_PER_SYM (XRAN_MIN_SECTIONS_PER_SLOT) /**< Min number of different sections in single slot (section may be equal to RB allocation for UE) */ -#define XRAN_MAX_SECTIONS_PER_SYM (16) /**< Max number of different sections in single symbol (section is equal to RB allocation for UE) */ +#define XRAN_MAX_FRAGMENT (1) /**< Max number of fragmentations in single symbol */ +#define XRAN_MAX_SET_BFWS (64) /**< Assumed 64Ant, BFP 9bit with 9K jumbo frame */ #define XRAN_MAX_PKT_BURST (448+4) /**< 4x14x8 symbols per ms */ #define XRAN_N_MAX_BUFFER_SEGMENT XRAN_MAX_PKT_BURST /**< Max number of segments per ms */ @@ -151,6 +158,9 @@ extern "C" { //#define _XRAN_DEBUG /**< Enable debug log */ //#define _XRAN_VERBOSE /**< Enable verbose log */ +#define MX_NUM_SAMPLES (16)/**< MAX Number of Samples for One Way delay Measurement */ + +#define XRAN_VF_QUEUE_MAX (XRAN_MAX_ANTENNA_NR*2+XRAN_MAX_ANT_ARRAY_ELM_NR) /**< MAX number of HW queues for given VF */ #ifdef _XRAN_DEBUG #define xran_log_dbg(fmt, ...) \ @@ -189,7 +199,8 @@ enum xran_if_state { XRAN_INIT = 0, XRAN_RUNNING, - XRAN_STOPPED + XRAN_STOPPED, + XRAN_OWDM }; /** @@ -213,7 +224,7 @@ enum xran_compression_method { * @ingroup xran * * @description - * Callback function type for symbol packet enum + * enum of callback function type ids for TTI *****************************************************************************/ enum callback_to_phy_id { @@ -223,6 +234,27 @@ enum callback_to_phy_id XRAN_CB_MAX /**< max number of callbacks */ }; +/** + ****************************************************************************** + * @ingroup xran + * + * @description + * enum of callback function type ids for sumbol + *****************************************************************************/ +enum cb_per_sym_type_id +{ + XRAN_CB_SYM_OTA_TIME = 0, /**< callback on exact SYM OTA time (+-SW jitter) */ + XRAN_CB_SYM_RX_WIN_BEGIN = 1, /**< callback on exact SYM RX window start time (+-SW jitter) */ + XRAN_CB_SYM_RX_WIN_END = 2, /**< callback on exact SYM RX window stop time (+-SW jitter) */ + XRAN_CB_SYM_TX_WIN_BEGIN = 3, /**< callback on exact SYM TX window start time (+-SW jitter) */ + XRAN_CB_SYM_TX_WIN_END = 4, /**< callback on exact SYM TX window stop time (+-SW jitter) */ + XRAN_CB_SYM_CP_DL_WIN_BEGIN = 5, /**< callback on exact SYM DL CP window start time (+-SW jitter) */ + XRAN_CB_SYM_CP_DL_WIN_END = 6, /**< callback on exact SYM DL CP window stop time (+-SW jitter) */ + XRAN_CB_SYM_CP_UL_WIN_BEGIN = 7, /**< callback on exact SYM UL CP window start time (+-SW jitter) */ + XRAN_CB_SYM_CP_UL_WIN_END = 8, /**< callback on exact SYM UL CP window stop time (+-SW jitter) */ + XRAN_CB_SYM_MAX /**< max number of types of callbacks */ +}; + /** Beamforming type, enumerated as "frequency", "time" or "hybrid" section 10.4.2 Weight-based dynamic beamforming */ enum xran_weight_based_beamforming_type { @@ -232,13 +264,24 @@ enum xran_weight_based_beamforming_type { XRAN_BF_T_MAX }; +/** contains time related information according to type of event */ +struct xran_sense_of_time { + enum cb_per_sym_type_id type_of_event; /**< event type id */ + uint32_t tti_counter; /**< TTI counter with in GPS second */ + uint32_t nSymIdx; /**< Symbol Idx with in Slot [0-13] */ + uint32_t nFrameIdx; /**< ORAN Frame */ + uint32_t nSubframeIdx; /**< ORAN Subframe */ + uint32_t nSlotIdx; /**< Slot within subframe */ + uint64_t nSecond; /**< GPS second of this symbol */ +}; + typedef int32_t xran_status_t; /**< Xran status return value */ /** callback function type for Symbol packet */ -typedef void (*xran_callback_sym_fn)(void*); +typedef int32_t (*xran_callback_sym_fn)(void*, struct xran_sense_of_time* p_sense_of_time); /** Callback function type for TTI event */ -typedef int (*xran_fh_tti_callback_fn)(void*); +typedef int32_t (*xran_fh_tti_callback_fn)(void*); /** Callback function type packet arrival from transport layer (ETH or IP) */ typedef void (*xran_transport_callback_fn)(void*, xran_status_t); @@ -299,8 +342,9 @@ enum xran_category enum xran_beamforming_type { XRAN_BEAM_ID_BASED = 0, /**< beam index based */ - XRAN_BEAM_WEIGHT, /**< beam forming weights */ - XRAN_BEAM_ATTRIBUTE, /**< beam index based */ + XRAN_BEAM_WEIGHT = 1, /**< beam forming weights */ + XRAN_BEAM_ATTRIBUTE = 2, /**< beam index based */ + XRAN_BEAM_TYPE_MAX }; /** state of bbdev with xran */ @@ -309,32 +353,74 @@ enum xran_bbdev_init XRAN_BBDEV_NOT_USED = -1, /**< BBDEV is disabled */ XRAN_BBDEV_MODE_HW_OFF = 0, /**< BBDEV is enabled for SW sim mode */ XRAN_BBDEV_MODE_HW_ON = 1, /**< BBDEV is enable for HW */ + XRAN_BBDEV_MODE_HW_SW = 2, /**< BBDEV for SW and HW is enabled */ XRAN_BBDEV_MODE_MAX }; /** callback return information */ struct xran_cb_tag { uint16_t cellId; + uint16_t oXuId; uint32_t symbol; uint32_t slotiId; }; +/** Common Data for ecpri one-way delay measurements */ +struct xran_ecpri_del_meas_cmn { + uint16_t initiator_en; // Initiator 1, Recipient 0 + uint16_t numberOfSamples; // Total number of samples to be collected and averaged + uint32_t filterType; // Average for number of samples collected 0 + uint64_t responseTo; // Response Timeout in ns + uint16_t measVf; // Vf using the owd transmitter + uint16_t measState; // The state of the owd Transmitter: OWDMTX_DIS,OWDMTX_INIT,OWDMTX_IDLE,OWDMTX_ACTIVE,OWDTX_DONE + uint16_t measId; // Measurement Id to be used by the transmitter + uint16_t measMethod; // Measurement Method i.e. REQUEST, REM_REQ, REQ_WFUP or REM_REQ_WFUP + uint16_t owdm_enable; // 1: Enabled 0:Disabled + uint16_t owdm_PlLength; // Payload Length 44 <= PlLength <= 1400 +}; + +/** Port specific data for ecpri one-way delay measurements */ +struct xran_ecpri_del_meas_port { + uint64_t t1; // ecpri ts1 + uint64_t t2; // ecpri ts2 + uint64_t tr; // ecpri tr + int64_t delta; // stores differences based on the msState + uint8_t portid; // portid for this owdm + uint8_t runMeas; // run One Way Delay measurements for numberOfSamples + uint16_t currentMeasID; // Last Measurement ID received, for originator use as base for the Measurement ID being send out + uint16_t msState; // Measurement State for Initiator: Idle, Waiting_Response, Waiting_Request, Waiting_Request_with_fup, Waiting_fup, Done + // Measurement State for Recipient: Idle, Waiting_Response, Waiting_Follow_up, Done + uint16_t numMeas; // Number of Measurements completed (Running number up to common config numberOfSamples + uint16_t txDone; // For originator clear after each change of state and set once the transmission is done + uint64_t rspTimerIdx; // Timer Index for TimeOut Timer. On timeout abort current measurement and go back to idle state + uint64_t delaySamples[MX_NUM_SAMPLES]; // Storage for collected delay samples i.e. td + uint64_t delayAvg; // Contains the average based on the numberOfSamples for the delay, gets computed once we have + // completed the collection for all the numberOfSamples prescribed +}; + /** DPDK IO configuration for XRAN layer */ struct xran_io_cfg { uint8_t id; /**< should be (0) for O-DU or (1) O-RU (debug) */ uint8_t num_vfs; /**< number of VFs for C-plane and U-plane (should be even) */ + uint16_t num_rxq; /**< number of RX queues per VF */ char *dpdk_dev[XRAN_VF_MAX]; /**< VFs devices */ char *bbdev_dev[1]; /**< BBDev dev name */ int32_t bbdev_mode; /**< DPDK for BBDev */ uint32_t dpdkIoVaMode; /**< IOVA Mode */ uint32_t dpdkMemorySize; /**< DPDK max memory allocation */ - int32_t core; /**< reservd */ - int32_t system_core; /**< reservd */ - uint64_t pkt_proc_core; /**< worker mask */ - int32_t pkt_aux_core; /**< reservd */ + int32_t core; /**< reserved */ + int32_t system_core; /**< reserved */ + uint64_t pkt_proc_core; /**< worker mask 0-63 */ + uint64_t pkt_proc_core_64_127; /**< worker mask 64-127 */ + int32_t pkt_aux_core; /**< reserved */ int32_t timing_core; /**< core used by xRAN */ int32_t port[XRAN_VF_MAX]; /**< VFs ports */ int32_t io_sleep; /**< enable sleep on PMD cores */ + uint32_t nEthLinePerPort; /**< 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link) */ + uint32_t nEthLineSpeed; /**< 10G,25G,40G,100G speed of Physical connection on O-RU */ + int32_t one_vf_cu_plane; /**< 1 - C-plane and U-plane use one VF */ + struct xran_ecpri_del_meas_cmn eowd_cmn[2];/**52600000 */ uint32_t nULAbsFrePointA; /**< Abs Freq Point A of the Carrier Center Frequency for in KHz Value: 450000->52600000 */ - uint32_t nDLCenterFreqARFCN; /**< center frerquency for DL in MHz */ - uint32_t nULCenterFreqARFCN; /**< center frerquency for UL in MHz */ + uint32_t nDLCenterFreqARFCN; /**< center frequency for DL in MHz */ + uint32_t nULCenterFreqARFCN; /**< center frequency for UL in MHz */ xran_fh_tti_callback_fn ttiCb; /**< call back for TTI event */ void *ttiCbParam; /**< parameters of call back function */ + uint16_t Tadv_cp_dl; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_min_cp_dl; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_max_cp_dl; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_min_cp_ul; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_max_cp_ul; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_min_up; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T2a_max_up; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t Ta3_min; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t Ta3_max; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_min_cp_dl; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_max_cp_dl; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_min_cp_ul; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_max_cp_ul; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_min_up; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t T1a_max_up; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t Ta4_min; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + uint16_t Ta4_max; /**< Table 2 7 : xRAN Delay Management Model Parameters */ + + uint8_t enableCP; /**< enable C-plane */ + uint8_t prachEnable; /**< enable PRACH */ + uint8_t srsEnable; /**< enable SRS (Cat B specific) */ + uint8_t puschMaskEnable;/**< enable pusch mask> */ + uint8_t puschMaskSlot; /**< specific which slot pusch channel masked> */ + uint8_t cp_vlan_tag; /**< C-plane vlan tag */ + uint8_t up_vlan_tag; /**< U-plane vlan tag */ + int32_t debugStop; /**< enable auto stop */ + int32_t debugStopCount; /**< enable auto stop after number of Tx packets */ + int32_t DynamicSectionEna; /**< enable dynamic C-Plane section allocation */ + int32_t GPS_Alpha; // refer to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) + int32_t GPS_Beta; //beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 + struct xran_prach_config prach_conf; /**< PRACH specific configurations for FH */ struct xran_srs_config srs_conf; /**< SRS specific configurations for FH */ struct xran_frame_config frame_conf; /**< frame config */ @@ -562,6 +678,9 @@ struct xran_fh_config { uint16_t rx_up_eAxC2Vf[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< mapping of C-Plane (ecpriRtcid) or U-Plane (ecpriPcid) to VF */ uint32_t log_level; /**< configuration of log level */ + + uint16_t max_sections_per_slot; /**< M-Plane settings for section */ + uint16_t max_sections_per_symbol; /**< M-Plane settings for section */ }; /** @@ -586,6 +705,7 @@ struct xran_common_counters{ uint64_t rx_pusch_packets[XRAN_MAX_ANTENNA_NR]; uint64_t rx_prach_packets[XRAN_MAX_ANTENNA_NR]; uint64_t rx_srs_packets; + }; /** @@ -605,23 +725,16 @@ typedef void * xran_cc_handle_t; *****************************************************************************/ struct xran_flat_buffer { - uint32_t nElementLenInBytes; - /**< The Element length specified in bytes. + uint32_t nElementLenInBytes; /**< The Element length specified in bytes. * This parameter specifies the size of a single element in the buffer. * The total size of the buffer is described as * bufferSize = nElementLenInBytes * nNumberOfElements */ - uint32_t nNumberOfElements; - /**< The number of elements in the physical contiguous memory segment */ - uint32_t nOffsetInBytes; - /**< Offset in bytes to the start of the data in the physical contiguous + uint32_t nNumberOfElements; /**< The number of elements in the physical contiguous memory segment */ + uint32_t nOffsetInBytes; /**< Offset in bytes to the start of the data in the physical contiguous * memory segment */ uint32_t nIsPhyAddr; - uint8_t *pData; - /**< The data pointer is a virtual address, however the actual data pointed - * to is required to be in contiguous physical memory unless the field - requiresPhysicallyContiguousMemory in CpaInstanceInfo is false. */ - void *pCtrl; - /**< pointer to control section coresponding to data buffer */ + uint8_t *pData; /**< The data pointer is a virtual address */ + void *pCtrl; /**< pointer to control section coresponding to data buffer */ }; /** @@ -634,30 +747,13 @@ struct xran_flat_buffer * structure will be used where more than one flat buffer can be provided * on a particular API. * - * IMPORTANT - The memory for the pPrivateMetaData member must be allocated - * by the client as contiguous memory. When allocating memory for - * pPrivateMetaData a call to cpaCyBufferListGetMetaSize MUST be made to - * determine the size of the Meta Data Buffer. The returned size - * (in bytes) may then be passed in a memory allocation routine to allocate - * the pPrivateMetaData memory. - * *****************************************************************************/ struct xran_buffer_list { - uint32_t nNumBuffers; - /**< Number of pointers */ + uint32_t nNumBuffers; /**< Number of pointers */ struct xran_flat_buffer *pBuffers; - /**< Pointer to an unbounded array containing the number of CpaFlatBuffers - * defined by nNumBuffers */ void *pUserData; - /**< This is an opaque field that is not read or modified internally. */ void *pPrivateMetaData; - /**< Private Meta representation of this buffer List - the memory for this - * buffer needs to be allocated by the client as contiguous data. - * The amount of memory required is returned with a call to - * cpaCyBufferListGetMetaSize. If cpaCyBufferListGetMetaSize returns a size - * of zero no memory needs to be allocated, and this parameter can be NULL. - */ }; /** @@ -694,7 +790,7 @@ int32_t xran_init(int argc, char *argv[], struct xran_fh_init *p_xran_fh_init, c * @return * 0 - on success */ -int32_t xran_sector_get_instances (void * pHandle, uint16_t nNumInstances, +int32_t xran_sector_get_instances (uint32_t xran_port, void * pDevHandle, uint16_t nNumInstances, xran_cc_handle_t * pSectorInstanceHandles); /** @@ -838,6 +934,7 @@ int32_t xran_mm_destroy (void * pHandle); */ int32_t xran_5g_prach_req (void * pHandle, struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], + struct xran_buffer_list *pDstBufferDecomp[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag); @@ -861,6 +958,7 @@ int32_t xran_5g_prach_req (void * pHandle, */ int32_t xran_5g_srs_req (void * pHandle, struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN], + struct xran_buffer_list *pDstCpBuffer[XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag); @@ -882,7 +980,7 @@ int32_t xran_5g_srs_req (void * pHandle, * @return * 0 - on success */ -uint32_t xran_get_time_stats(uint64_t *total_time, uint64_t *used_time, uint32_t *core_used, uint32_t clear); +uint32_t xran_get_time_stats(uint64_t *total_time, uint64_t *used_time, uint32_t *num_core_used, uint32_t *core_used, uint32_t clear); /** * @ingroup xran @@ -947,18 +1045,19 @@ int32_t xran_close(void *pHandle); * Pointer to XRAN layer handle for given CC * @param symCb * pointer to callback function - * @param symCb + * @param symCbParam * pointer to Callback Function parameters * @param symb * symbol to be register for - * @param ant - * Antenna number to trigger callback for packet arrival + * @param cb_per_sym_type_id + * call back time identification (see enum cb_per_sym_type_id) * * @return * 0 - in case of success * -1 - in case of failure */ -int32_t xran_reg_sym_cb(void *pHandle, xran_callback_sym_fn symCb, void * symCbParam, uint8_t symb, uint8_t ant); +int32_t xran_reg_sym_cb(void *pHandle, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, uint8_t symb, enum cb_per_sym_type_id cb_sym_t_id); + /** * @ingroup xran @@ -1003,7 +1102,26 @@ int32_t xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbP * @return * current TTI number [0-7999] */ -int32_t xran_get_slot_idx (uint32_t *nFrameIdx, uint32_t *nSubframeIdx, uint32_t *nSlotIdx, uint64_t *nSecond); +int32_t xran_get_slot_idx (uint32_t PortId, uint32_t *nFrameIdx, uint32_t *nSubframeIdx, uint32_t *nSlotIdx, uint64_t *nSecond); + +/** + * @ingroup xran + * + * Function returns whether it is a prach slot or not based on given port and slot number + * + * @param PortId + * xRAN Port Id + * + * @param subframe_id + * Subframe number [0-9] + * + * @param slot_id + * Pointer to Slot number [0-7] + * + * @return + * whether it is a prach slot or not + */ +int32_t xran_is_prach_slot(uint8_t PortId, uint32_t subframe_id, uint32_t slot_id); /** * @ingroup xran @@ -1089,6 +1207,20 @@ uint8_t* xran_add_hdr_offset(uint8_t *dst, int16_t compMethod); */ uint8_t *xran_add_cp_hdr_offset(uint8_t *dst); +/** + * @ingroup xran + * + * Debug function to trigger stop on 1pps (GPS second) boundary + * + * @param value + * 1 - enable stop + * 0 - disable stop + * @param count + * enable auto stop after number of Tx packets + * @return + * 0 - on success + */ +int32_t xran_set_debug_stop(int32_t value, int32_t count); #ifdef __cplusplus } #endif diff --git a/fhi_lib/lib/src/xran_lib_mlog_tasks_id.h b/fhi_lib/lib/api/xran_lib_mlog_tasks_id.h similarity index 86% rename from fhi_lib/lib/src/xran_lib_mlog_tasks_id.h rename to fhi_lib/lib/api/xran_lib_mlog_tasks_id.h index 348949f..d0b63ac 100644 --- a/fhi_lib/lib/src/xran_lib_mlog_tasks_id.h +++ b/fhi_lib/lib/api/xran_lib_mlog_tasks_id.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,8 +23,8 @@ * @author Intel Corporation **/ -#ifndef _XRAN_TASK_ID_H_ -#define _XRAN_TASK_ID_H_ +#ifndef _XRAN_LIB_TASK_ID_H_ +#define _XRAN_LIB_TASK_ID_H_ #ifdef __cplusplus extern "C" { @@ -57,6 +57,8 @@ extern "C" { //-------------------------------------------------------------------- // POLLING //-------------------------------------------------------------------- +#define PID_XRAN_MAIN 101 + #define PID_XRAN_BBDEV_DL_POLL 51 #define PID_XRAN_BBDEV_DL_POLL_DISPATCH 52 #define PID_XRAN_BBDEV_UL_POLL 53 @@ -66,13 +68,13 @@ extern "C" { #define PID_TTI_CB 2101 #define PID_SYM_TIMER 2102 -#define PID_GNB_PROC_TIMING_TIMEOUT 2103 +//#define PID_GNB_PROC_TIMING_TIMEOUT 2103 #define PID_TIME_SYSTIME_POLL 2104 #define PID_TIME_SYSTIME_STOP 2105 #define PID_TIME_ARM_TIMER 2106 #define PID_TIME_ARM_TIMER_DEADLINE 2107 - +#define PID_TIME_ARM_USER_TIMER_DEADLINE 2108 #define PID_RADIO_FREQ_RX_PKT 2400 @@ -96,6 +98,10 @@ extern "C" { #define PID_RADIO_TX_PLAY_BACK_IQ 2415 #define PID_PROCESS_TX_SYM 2416 +#define PID_DISPATCH_TX_SYM 2417 +#define PID_PREPARE_TX_PKT 2418 +#define PID_ATTACH_EXT_BUF 2419 +#define PID_ETH_ENQUEUE_BURST 2420 #define PID_CP_DL_CB 2500 #define PID_CP_UL_CB 2501 @@ -106,14 +112,17 @@ extern "C" { #define PID_FULL_SLOT_CB_TO_PHY 2506 #define PID_UP_UL_HALF_DEAD_LINE_CB 2507 #define PID_UP_UL_FULL_DEAD_LINE_CB 2508 +#define PID_UP_UL_USER_DEAD_LINE_CB 2509 #define PID_PROCESS_UP_PKT 2600 +#define PID_PROCESS_UP_PKT_SRS 2601 +#define PID_PROCESS_UP_PKT_PARSE 2602 #define PID_PROCESS_CP_PKT 2700 +#define PID_PROCESS_DELAY_MEAS_PKT 2800 #ifdef __cplusplus } #endif -#endif /* _XRAN_TASK_ID_H_ */ - +#endif /* _XRAN_LIB_TASK_ID_H_ */ diff --git a/fhi_lib/lib/api/xran_mlog_lnx.h b/fhi_lib/lib/api/xran_mlog_lnx.h index 88fcaa4..e0913c7 100644 --- a/fhi_lib/lib/api/xran_mlog_lnx.h +++ b/fhi_lib/lib/api/xran_mlog_lnx.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -35,6 +35,7 @@ extern "C" #define MLogRestart(a) MLOG_FALSE #define MLogPrint(a) MLOG_FALSE #define MLogGetFileLocation() NULL +#define MLogGetFileName() NULL #define MLogGetFileSize() 0 #define MLogSetMask(a) MLOG_FALSE #define MLogGetMask() diff --git a/fhi_lib/lib/api/xran_pkt.h b/fhi_lib/lib/api/xran_pkt.h index 560feca..edf4352 100644 --- a/fhi_lib/lib/api/xran_pkt.h +++ b/fhi_lib/lib/api/xran_pkt.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -64,6 +64,19 @@ extern "C" { #define VLAN_ID 0 /**< Default Tag protocol identifier (TPID)*/ #define VLAN_PCP 7 /**< U-Plane and C-Plane only see Table 3 5 : Quality of service classes */ +#define XRAN_MTU_DEFAULT RTE_ETHER_MTU +#define XRAN_APP_LAYER_MAX_SIZE_L2_DEFAUT (XRAN_MTU_DEFAULT - 8) /**< In case of L2 only solution, application layer maximum transmission unit size + is standard IEEE 802.3 Ethernet frame payload + size (1500 bytes) – transport overhead (8 bytes) = 1492 bytes (or larger for Jumbo frames) */ + +#ifndef OK +#define OK 0 /* Function executed correctly */ +#endif +#ifndef FAIL +#define FAIL 1 /* Function failed to execute */ +#endif +#define NS_PER_SEC 1000000000LL + /** ****************************************************************************** * @ingroup xran_common_pkt @@ -87,6 +100,41 @@ enum ecpri_msg_type ECPRI_MSG_TYPE_MAX }; +/** + ****************************************************************************** + * @ingroup xran_common_pkt + * + * @description + * eCPRI Timestamp for one-way delay measurements format per IEEE-1588 + * clause 5.3.3. + *****************************************************************************/ + +typedef struct { + uint16_t secs_msb; // 6 bytes for seconds + uint32_t secs_lsb; + uint32_t ns; // 4 bytes for nanoseconds + } TimeStamp; + + +/** + ****************************************************************************** + * @ingroup xran_common_pkt + * + * @description + * eCPRI action types + * as per eCPRI spec Table 8 action Types + *****************************************************************************/ +enum ecpri_action_type +{ + ECPRI_REQUEST = 0x00, /* Uses Time Stamp T1 and Comp Delay 1 */ + ECPRI_REQUEST_W_FUP = 0x01, /* Uses 0 for Time Stamp and Comp Delay 1 */ + ECPRI_RESPONSE = 0x02, /* Uses Time Stamp T2 and Comp Delay 2 */ + ECPRI_REMOTE_REQ = 0x03, /* Uses 0 for Time Stamp and Comp Delay */ + ECPRI_REMOTE_REQ_W_FUP = 0x04, /* Uses 0 for Time Stamp and Comp Delay */ + ECPRI_FOLLOW_UP = 0x05, /* Uses Time Info and Comp Delay Info */ + ECPRI_ACTION_TYPE_MAX +}; + /** ****************************************************************************** * @ingroup xran_common_pkt @@ -94,13 +142,23 @@ enum ecpri_msg_type * @description * see 3.1.3.1.7 ecpriSeqid (message identifier) *****************************************************************************/ -struct ecpri_seq_id +union ecpri_seq_id +{ + struct { uint8_t seq_id:8; /**< Sequence ID */ uint8_t sub_seq_id:7; /**< Subsequence ID */ uint8_t e_bit:1; /**< E bit */ + } bits; + struct + { + uint16_t data_num_1; + } data; } __rte_packed; +#define ecpri_seq_id_bitfield_seq_id 0 +#define ecpri_seq_id_bitfield_sub_seq_id 8 +#define ecpri_seq_id_bitfield_e_bit 15 /** ****************************************************************************** @@ -110,13 +168,53 @@ struct ecpri_seq_id * Structure holds common eCPRI header as per * Table 3 1 : eCPRI Transport Header Field Definitions *****************************************************************************/ -struct xran_ecpri_cmn_hdr +union xran_ecpri_cmn_hdr +{ + struct { uint8_t ecpri_concat:1; /**< 3.1.3.1.3 eCPRI concatenation indicator */ uint8_t ecpri_resv:3; /**< 3.1.3.1.2 eCPRI reserved */ uint8_t ecpri_ver:4; /**< 3.1.3.1.1 eCPRI protocol revision, defined in XRAN_ECPRI_VER */ uint8_t ecpri_mesg_type; /**< 3.1.3.1.4 eCPRI message type, defined in ecpri_msg_type */ uint16_t ecpri_payl_size; /**< 3.1.3.1.5 eCPRI payload size, without common header and any padding bytes */ + } bits; + struct + { + uint32_t data_num_1; + } data; +} __rte_packed; + +#define xran_ecpri_cmn_hdr_bitfield_EcpriVer 4 +#define xran_ecpri_cmn_hdr_bitfield_EcpriMsgType 8 +/** + ****************************************************************************** + * @ingroup xran_common_pkt + * + * @description + * Structure holds common eCPRI delay measuurement header as per + * Table 2.17 : eCPRI One-Way delay measurement message + *****************************************************************************/ +struct xran_ecpri_delay_meas_pl +{ + uint8_t MeasurementID; /**< Table 2-17 Octet 5 */ + uint8_t ActionType; /**< Table 2-17 Octet 6 */ + TimeStamp ts; /**< Table 2-17 Octet 7-16 */ + int64_t CompensationValue; /**< Table 2-17 Octet 17 */ + uint8_t DummyBytes[1400]; /**< Table 2-17 Octet 25 */ +} __rte_packed; + +/** + ****************************************************************************** + * @ingroup xran_common_pkt + * + * @description + * Structure holds common eCPRI cmn header per eCPRI figure 8 and the measurement delay header and pl per + * eCPRI Figure 23 : eCPRI One-Way delay measurement message + *****************************************************************************/ + struct xran_ecpri_del_meas_pkt + { + union xran_ecpri_cmn_hdr cmnhdr; + struct xran_ecpri_delay_meas_pl deMeasPl; } __rte_packed; /** @@ -129,9 +227,9 @@ struct xran_ecpri_cmn_hdr *****************************************************************************/ struct xran_ecpri_hdr { - struct xran_ecpri_cmn_hdr cmnhdr; + union xran_ecpri_cmn_hdr cmnhdr; rte_be16_t ecpri_xtc_id; /**< 3.1.3.1.6 real time control data / IQ data transfer message series identifier */ - struct ecpri_seq_id ecpri_seq_id; /**< 3.1.3.1.7 message identifier */ + union ecpri_seq_id ecpri_seq_id; /**< 3.1.3.1.7 message identifier */ } __rte_packed; @@ -162,6 +260,9 @@ enum xran_pkt_dir struct radio_app_common_hdr { /* Octet 9 */ + union { + uint8_t value; + struct { uint8_t filter_id:4; /**< This parameter defines an index to the channel filter to be used between IQ data and air interface, both in DL and UL. For most physical channels filterIndex =0000b is used which @@ -171,6 +272,8 @@ struct radio_app_common_hdr for the following IEs in the application layer. In this version of the specification payloadVersion=001b shall be used. */ uint8_t data_direction:1; /**< This parameter indicates the gNB data direction. */ + }; + }data_feature; /* Octet 10 */ uint8_t frame_id:8; /**< This parameter is a counter for 10 ms frames (wrapping period 2.56 seconds) */ diff --git a/fhi_lib/lib/api/xran_pkt_cp.h b/fhi_lib/lib/api/xran_pkt_cp.h index 5d54ab6..531c51f 100644 --- a/fhi_lib/lib/api/xran_pkt_cp.h +++ b/fhi_lib/lib/api/xran_pkt_cp.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -59,6 +59,9 @@ struct xran_radioapp_udComp_header { * Common Radio Application Header for C-Plane */ struct xran_cp_radioapp_common_header { /* 6bytes, first 4bytes need the conversion for byte order */ + union { + uint32_t all_bits; + struct { uint32_t startSymbolId:6; /**< 5.4.4.7 start symbol identifier */ uint32_t slotId:6; /**< 5.4.4.6 slot identifier */ uint32_t subframeId:4; /**< 5.4.4.5 subframe identifier */ @@ -66,10 +69,22 @@ struct xran_cp_radioapp_common_header { /* 6bytes, first 4bytes need the con uint32_t filterIndex:4; /**< 5.4.4.3 filter index, XRAN_FILTERINDEX_xxxx */ uint32_t payloadVer:3; /**< 5.4.4.2 payload version, should be 1 */ uint32_t dataDirection:1; /**< 5.4.4.1 data direction (gNB Tx/Rx) */ + }; + } field; uint8_t numOfSections; /**< 5.4.4.8 number of sections */ uint8_t sectionType; /**< 5.4.4.9 section type */ } __attribute__((__packed__)); +#define xran_cp_radioapp_cmn_hdr_bitwidth_StartSymId 0 +#define xran_cp_radioapp_cmn_hdr_bitwidth_SlotId 6 +#define xran_cp_radioapp_cmn_hdr_bitwidth_SubFrameId 12 +#define xran_cp_radioapp_cmn_hdr_bitwidth_FrameId 16 +#define xran_cp_radioapp_cmn_hdr_bitwidth_FilterIdex 24 +#define xran_cp_radioapp_cmn_hdr_bitwidth_PayLoadVer 28 +#define xran_cp_radioapp_cmn_hdr_bitwidth_DataDir 31 + + + /** * @ingroup xran_cp_pkt * @@ -90,6 +105,7 @@ struct xran_cp_radioapp_frameStructure { */ struct xran_cp_radioapp_section_header { /* 8bytes, need the conversion for byte order */ union { + uint32_t first_4byte; struct { uint32_t reserved:16; uint32_t numSymbol:4; /**< 5.4.5.7 number of symbols */ @@ -114,14 +130,28 @@ struct xran_cp_radioapp_section_header { /* 8bytes, need the conversion for b uint32_t reMask:12; /**< 5.4.5.5 resource element mask */ } s5; } u; - + union { + uint32_t second_4byte; + struct { uint32_t numPrbc:8; /**< 5.4.5.6 number of contiguous PRBs per control section 0000 0000b = all PRBs */ uint32_t startPrbc:10; /**< 5.4.5.4 starting PRB of control section */ uint32_t symInc:1; /**< 5.4.5.3 symbol number increment command XRAN_SYMBOLNUMBER_xxxx */ uint32_t rb:1; /**< 5.4.5.2 resource block indicator, XRAN_RBIND_xxx */ uint32_t sectionId:12; /**< 5.4.5.1 section identifier */ + } common; + } u1; } __attribute__((__packed__)); +#define xran_cp_radioapp_sec_hdr_sc_BeamID 0 +#define xran_cp_radioapp_sec_hdr_sc_Ef 15 +#define xran_cp_radioapp_sec_hdr_sc_NumSym 16 +#define xran_cp_radioapp_sec_hdr_sc_ReMask 20 + +#define xran_cp_radioapp_sec_hdr_c_NumPrbc 0 +#define xran_cp_radioapp_sec_hdr_c_StartPrbc 8 +#define xran_cp_radioapp_sec_hdr_c_SymInc 18 +#define xran_cp_radioapp_sec_hdr_c_RB 19 +#define xran_cp_radioapp_sec_hdr_c_SecId 20 struct xran_cp_radioapp_section_ext_hdr { /* 12 bytes, need to convert byte order for two parts respectively @@ -203,8 +233,9 @@ struct xran_cp_radioapp_section_ext2 { * Only be used for LTE TM2-4 and not for other LTE TMs nor NR. * The structure is reordered for byte order conversion. */ -struct xran_cp_radioapp_section_ext3_first { +union xran_cp_radioapp_section_ext3_first { /* 16 bytes, need to convert byte order for two parts - 8/8 bytes */ + struct{ uint64_t reserved1:8; uint64_t crsSymNum:4; /**< 5.4.7.3.6 CRS symbol number indication */ uint64_t reserved0:3; @@ -222,8 +253,28 @@ struct xran_cp_radioapp_section_ext3_first { uint64_t beamIdAP2:16; /**< 5.4.7.3.9 beam id to be used for antenna port 2 */ uint64_t beamIdAP3:16; /**< 5.4.7.3.10 beam id to be used for antenna port 3 */ uint64_t reserved2:16; + }all_bits; + + struct{ + __m128i data_field1; + }data_field; } __attribute__((__packed__)); +#define xran_cp_radioapp_sec_ext3_Res1 0 +#define xran_cp_radioapp_sec_ext3_CrcSymNum 8 +#define xran_cp_radioapp_sec_ext3_Res0 12 +#define xran_cp_radioapp_sec_ext3_CrcShift 15 +#define xran_cp_radioapp_sec_ext3_CrcReMask 16 +#define xran_cp_radioapp_sec_ext3_TxScheme 28 + +#define xran_cp_radioapp_sec_ext3_NumLayers 0 +#define xran_cp_radioapp_sec_ext3_LayerId 4 +#define xran_cp_radioapp_sec_ext3_CodebookIdx 8 +#define xran_cp_radioapp_sec_ext3_ExtLen 16 +#define xran_cp_radioapp_sec_ext3_ExtType 24 +#define xran_cp_radioapp_sec_ext3_EF 31 + + /** * @ingroup xran_cp_pkt * @@ -233,7 +284,9 @@ struct xran_cp_radioapp_section_ext3_first { * Only be used for LTE TM2-4 and not for other LTE TMs nor NR. * The structure is reordered for byte order conversion. */ -struct xran_cp_radioapp_section_ext3_non_first { +union xran_cp_radioapp_section_ext3_non_first { + uint32_t data_field; + struct { /* 4 bytes, need to convert byte order at once */ uint32_t numLayers:4; /**< 5.4.7.3.4 number of layers used for DL transmission */ uint32_t layerId:4; /**< 5.4.7.3.2 Layer ID for DL transmission */ @@ -242,6 +295,7 @@ struct xran_cp_radioapp_section_ext3_non_first { uint32_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */ uint32_t extType:7; /**< 5.4.6.1 extension type */ uint32_t ef:1; /**< 5.4.6.2 extension flag */ + }all_bits; } __attribute__((__packed__)); /** @@ -281,6 +335,154 @@ struct xran_cp_radioapp_section_ext5 { uint32_t mcScaleReMask1:12; /**< 5.4.7.5.1 modulation compression power scale RE mask */ } __attribute__((__packed__)); +/** + * @ingroup xran_cp_pkt + * + * @description + * Non-contiguous PRB allocation in time and frequency domain. + * ExtType 6, Defined in 5.4.7.6 Table 5-28 + * Only applies to section type 1 3, and 5. + * The structure is reordered for byte order conversion. + */ +union xran_cp_radioapp_section_ext6 { + struct { + uint64_t symbolMask:14; /**< 5.4.7.6.3 symbol bit mask */ + uint64_t reserved1:2; + uint64_t rbgMask:28; /**< 5.4.7.6.2 resource block group bit mask */ + uint64_t rbgSize:3; /**< 5.4.7.6.1 resource block group size */ + uint64_t reserved0:1; + uint64_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */ + uint64_t extType:7; /**< 5.4.6.1 extension type */ + uint64_t ef:1; /**< 5.4.6.2 extension flag */ + }all_bits; + + struct{ + uint64_t data_field1; + }data_field; +} __attribute__((__packed__)); + +/** + * @ingroup xran_cp_pkt + * + * @description + * eAxC Mask Selection Extension (ExtType 7) + * Defined in 5.4.7.7 Table 5-29 + * applies to section type 0 + * The structure is reordered for byte order conversion. + */ +struct xran_cp_radioapp_section_ext7 { + uint32_t eAxCmask:16; /**< 5.4.7.7.1 eAxC Mask */ + uint32_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */ + uint32_t extType:7; /**< 5.4.6.1 extension type */ + uint32_t ef:1; /**< 5.4.6.2 extension flag */ + } __attribute__((__packed__)); + +/** + * @ingroup xran_cp_pkt + * + * @description + * Regularization factor (ExtType 8), defined in 5.4.7.8 Table 5-30 + * applies to section type 5 instead of sending section type 6 + * The structure is reordered for byte order conversion. + */ +struct xran_cp_radioapp_section_ext8 { + uint32_t regularizationFactor:16; /**< 5.4.7.8.1 eAxC Mask */ + uint32_t extLen:8; /**< 5.4.6.3 extension length, in 32bits words */ + uint32_t extType:7; /**< 5.4.6.1 extension type */ + uint32_t ef:1; /**< 5.4.6.2 extension flag */ + } __attribute__((__packed__)); + +/** + * @ingroup xran_cp_pkt + * + * @description + * Dynamic Spectrum Sharing parameters (ExtType 9) + * Defined in 5.4.7.9 Table 5-31 + * The structure does not need the conversion of byte order. + */ +struct xran_cp_radioapp_section_ext9 { + uint8_t extType:7; /**< 5.4.6.1 extension type */ + uint8_t ef:1; /**< 5.4.6.2 extension flag */ + uint8_t extLen; /**< 5.4.6.3 extension length, in 32bits words */ + uint8_t technology; /**< 5.4.7.9.1 technology (interface name) */ + uint8_t reserved; + } __attribute__((__packed__)); + +/** + * @ingroup xran_cp_pkt + * + * @description + * Section description for group configuration of multiple ports + * ExtType 10, Defined in 5.4.7.10 Table 5-32 and Table 5-33 + * Applies to section type 1 3, and 5. + * The structure does not need the conversion of byte order. + */ +union xran_cp_radioapp_section_ext10 { + uint32_t data_field; + struct{ + uint8_t extType:7; /**< 5.4.6.1 extension type */ + uint8_t ef:1; /**< 5.4.6.2 extension flag */ + uint8_t extLen; /**< 5.4.6.3 extension length, in 32bits words */ + uint8_t numPortc:6; /**< 5.4.7.10.2 the number of eAxC ports */ + uint8_t beamGroupType:2; /**< 5.4.7.10.1 the type of beam grouping */ + uint8_t reserved; /**< beam IDs start from here for group type 2 */ + }all_bits; + } __attribute__((__packed__)); + + +#define xran_cp_radioapp_sec_ext10_ExtType 0 +#define xran_cp_radioapp_sec_ext10_EF 7 +#define xran_cp_radioapp_sec_ext10_ExtLen 8 +#define xran_cp_radioapp_sec_ext10_NumPortc 16 +#define xran_cp_radioapp_sec_ext10_BeamGroupType 22 +#define xran_cp_radioapp_sec_ext10_Res0 24 + + +/** + * @ingroup xran_cp_pkt + * + * @description + * Flexible Beamforming Weights Extension Type (ExtType 11) + * Defined in 5.4.7.11 Table 5-35 + * The structure is reordered for network byte order. + */ +union xran_cp_radioapp_section_ext11 { + struct { + uint32_t reserved:6; + uint32_t RAD:1; /**< 5.4.7.11.8 Reset After PRB Discontinuity */ + uint32_t disableBFWs:1; /**< 5.4.7.11.6 disable beamforming weights */ + uint32_t extLen:16; /**< extension length in 32bits words - 2bytes */ + uint32_t extType:7; /**< 5.4.6.1 extension type */ + uint32_t ef:1; /**< 5.4.6.2 extension flag */ + uint8_t numBundPrb; /**< 5.4.7.11.3 Number of bundled PRBs per beamforming weights */ + uint8_t bfwCompMeth:4; /**< 5.4.7.11.1 Beamforming weight Compression method (5.4.7.1.1) */ + uint8_t bfwIqWidth:4; /**< 5.4.7.11.1 Beamforming weight IQ bit width (5.4.7.1.1) */ + } all_bits; + struct{ + uint32_t data_field1; + uint16_t data_field2; + }data_field; + /* + * bfwCompParam 5.4.7.11.2 beamforming weight compression parameter for PRB bundle + * beamId beam ID for PRB bundle (15bits) + * bfwI / bfwQ ....... beamforming weights for PRB bundle + * ..... + * repeat until PRB bundle L + * + * zero pad (4-byte boundary) + */ + } __attribute__((__packed__)); + +#define xran_cp_radioapp_sec_ext11_bitfield_REV 0 +#define xran_cp_radioapp_sec_ext11_bitfield_RAD 6 +#define xran_cp_radioapp_sec_ext11_bitfield_DisBFWs 7 +#define xran_cp_radioapp_sec_ext11_bitfield_ExtLen 8 +#define xran_cp_radioapp_sec_ext11_bitfield_ExtType 24 +#define xran_cp_radioapp_sec_ext11_bitfield_Ef 31 +#define xran_cp_radioapp_sec_ext11_bitfield_NumPrb 0 +#define xran_cp_radioapp_sec_ext11_bitfield_BFWCompMeth 8 +#define xran_cp_radioapp_sec_ext11_bitfield_BFWIQWidth 12 + /********************************************************** * Scheduling and Beam-forming Commands 5.4.2 diff --git a/fhi_lib/lib/api/xran_pkt_up.h b/fhi_lib/lib/api/xran_pkt_up.h index 3231fc2..674b584 100644 --- a/fhi_lib/lib/api/xran_pkt_up.h +++ b/fhi_lib/lib/api/xran_pkt_up.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -75,10 +75,6 @@ struct data_section_hdr { uint32_t sect_id:12; /**< 5.4.5.1 section identifier */ }; }fields; -#ifdef FCN_ADAPT - uint8_t udCompHdr; - uint8_t reserved; -#endif } __rte_packed; @@ -157,6 +153,21 @@ struct xran_up_pkt_hdr struct data_section_hdr data_sec_hdr; } __rte_packed; +/** + ****************************************************************************** + * @ingroup xran_common_pkt + * + * @description + * Structure holds complete xran u-plane packet header with compression + * 3.1.1 Ethernet Encapsulation + *****************************************************************************/ +struct xran_up_pkt_hdr_comp +{ + struct xran_ecpri_hdr ecpri_hdr; /**< eCPRI Transport Header */ + struct radio_app_common_hdr app_hdr; /**< eCPRI Transport Header */ + struct data_section_hdr data_sec_hdr; /**< data section Header */ + struct data_section_compression_hdr data_comp_hdr; /** Compression Header */ +} __rte_packed; /** ****************************************************************************** @@ -172,6 +183,13 @@ struct eth_xran_up_pkt_hdr struct xran_up_pkt_hdr xran_hdr; }__rte_packed; +struct eth_xran_up_pkt_hdr_comp +{ + struct rte_ether_hdr eth_hdr; + struct xran_up_pkt_hdr_comp xran_hdr; +}__rte_packed; + + #ifdef __cplusplus } #endif diff --git a/fhi_lib/lib/api/xran_sync_api.h b/fhi_lib/lib/api/xran_sync_api.h index 3be0dec..824aac4 100644 --- a/fhi_lib/lib/api/xran_sync_api.h +++ b/fhi_lib/lib/api/xran_sync_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/fhi_lib/lib/api/xran_timer.h b/fhi_lib/lib/api/xran_timer.h index b2cdfd8..a7e9330 100644 --- a/fhi_lib/lib/api/xran_timer.h +++ b/fhi_lib/lib/api/xran_timer.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -37,6 +37,19 @@ extern "C" { #include #include +/* Difference between Unix seconds to GPS seconds + GPS epoch: 1980.1.6 00:00:00 (UTC); Unix time epoch: 1970:1.1 00:00:00 UTC + Value is calculated on Sep.6 2019. Need to be change if International + Earth Rotation and Reference Systems Service (IERS) adds more leap seconds + 1970:1.1 - 1980.1.6: 3657 days + 3657*24*3600=315 964 800 seconds (unix seconds value at 1980.1.6 00:00:00 (UTC)) + There are 18 leap seconds inserted after 1980.1.6 00:00:00 (UTC), which means + GPS is 18 larger. 315 964 800 - 18 = 315 964 782 +*/ +#define UNIX_TO_GPS_SECONDS_OFFSET 315964782UL +#define NUM_OF_FRAMES_PER_SFN_PERIOD 1024 +#define NUM_OF_FRAMES_PER_SECOND 100 + #define MSEC_PER_SEC 1000L #define XranIncrementSymIdx(sym_idx, numSymPerMs) (((uint32_t)sym_idx >= (((uint32_t)numSymPerMs * MSEC_PER_SEC) - 1)) ? 0 : (uint32_t)sym_idx+1) @@ -49,7 +62,9 @@ long sleep_next_tick(long interval); int timing_set_debug_stop(int value, int count); int timing_get_debug_stop(void); inline uint64_t timing_get_current_second(void); +uint8_t timing_get_numerology(void); int timing_set_numerology(uint8_t value); +uint32_t xran_max_ota_sym_idx(uint8_t numerlogy); #ifdef __cplusplus } diff --git a/fhi_lib/lib/api/xran_transport.h b/fhi_lib/lib/api/xran_transport.h index bf88759..0b75fbe 100644 --- a/fhi_lib/lib/api/xran_transport.h +++ b/fhi_lib/lib/api/xran_transport.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -37,6 +37,8 @@ extern "C" { #include "xran_pkt.h" +#define XRAN_ECPRI_HDR_SZ (sizeof(struct xran_ecpri_hdr) - sizeof(union xran_ecpri_cmn_hdr)) + struct xran_eaxc_info { uint8_t cuPortId; uint8_t bandSectorId; diff --git a/fhi_lib/lib/api/xran_up_api.h b/fhi_lib/lib/api/xran_up_api.h index b6e29c6..7d3afc5 100644 --- a/fhi_lib/lib/api/xran_up_api.h +++ b/fhi_lib/lib/api/xran_up_api.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -80,17 +80,18 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, uint8_t *subframe_id, uint8_t *slot_id, uint8_t *symb_id, - struct ecpri_seq_id *seq_id, + union ecpri_seq_id *seq_id, uint16_t *num_prbu, uint16_t *start_prbu, uint16_t *sym_inc, uint16_t *rb, uint16_t *sect_id, int8_t expect_comp, + enum xran_comp_hdr_type staticComp, uint8_t *compMeth, uint8_t *iqWidth); -int xran_prepare_iq_symbol_portion( +inline int xran_prepare_iq_symbol_portion( struct rte_mbuf *mbuf, const void *iq_data_start, const enum xran_input_byte_order iq_buf_byte_order, @@ -99,6 +100,7 @@ int xran_prepare_iq_symbol_portion( uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id, + enum xran_comp_hdr_type staticEn, uint32_t do_copy); #ifdef __cplusplus diff --git a/fhi_lib/lib/ethernet/ethdi.c b/fhi_lib/lib/ethernet/ethdi.c index 873db7b..b6ba257 100644 --- a/fhi_lib/lib/ethernet/ethdi.c +++ b/fhi_lib/lib/ethernet/ethdi.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -37,12 +37,12 @@ #include #include #include - +#include #include #include #include #include -#include +#include #include #include #include @@ -66,11 +66,14 @@ #include "xran_fh_o_du.h" #include "xran_mlog_lnx.h" #include "xran_printf.h" +#include "xran_common.h" -#include "../src/xran_lib_mlog_tasks_id.h" +#include "xran_lib_mlog_tasks_id.h" #define BURST_RX_IO_SIZE 48 +//#define ORAN_OWD_DEBUG_TX_LOOP + struct xran_ethdi_ctx g_ethdi_ctx = { 0 }; enum xran_if_state xran_if_current_state = XRAN_STOPPED; @@ -79,6 +82,11 @@ struct rte_mbuf *xran_ethdi_mbuf_alloc(void) return rte_pktmbuf_alloc(_eth_mbuf_pool); } +struct rte_mbuf *xran_ethdi_mbuf_indir_alloc(void) +{ + return rte_pktmbuf_alloc(socket_indirect_pool); +} + int32_t xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id) { struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); @@ -107,13 +115,9 @@ struct { uint16_t ethertype; ethertype_handler fn; } xran_ethertype_handlers[] = { - { ETHER_TYPE_ETHDI, NULL }, { ETHER_TYPE_ECPRI, NULL }, - { ETHER_TYPE_START_TX, NULL } }; - - int32_t xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback) { int i; @@ -125,59 +129,40 @@ int32_t xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler ca return 1; } - elog("support for ethertype %u not found", ethertype); + print_err("support for ethertype %u not found", ethertype); return 0; } -int xran_handle_ether(uint16_t ethertype, struct rte_mbuf *pkt, uint64_t rx_time) +int xran_handle_ether(uint16_t ethertype, struct rte_mbuf* pkt_q[], uint16_t xport_id, struct xran_eaxc_info *p_cid, uint16_t num) { int i; for (i = 0; i < RTE_DIM(xran_ethertype_handlers); ++i) if (xran_ethertype_handlers[i].ethertype == ethertype) - if (xran_ethertype_handlers[i].fn) - return xran_ethertype_handlers[i].fn(pkt, rx_time); + if (xran_ethertype_handlers[i].fn){ +// rte_prefetch0(rte_pktmbuf_mtod(pkt, void *)); + return xran_ethertype_handlers[i].fn(pkt_q, xport_id, p_cid, num); + } - wlog("Packet with unrecognized ethertype '%.4X' dropped", ethertype); + print_err("Packet with unrecognized ethertype '%.4X' dropped", ethertype); - return 0; + return MBUF_FREE; }; /* Process vlan tag. Cut the ethernet header. Call the etherype handlers. */ -int xran_ethdi_filter_packet(struct rte_mbuf *pkt, uint64_t rx_time) +int xran_ethdi_filter_packet(struct rte_mbuf *pkt_q[], uint16_t vf_id, uint16_t q_id, uint16_t num) { + int ret; struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); + struct rte_ether_hdr* eth_hdr; + uint16_t port_id = ctx->vf2xran_port[vf_id]; + struct xran_eaxc_info *p_cid = &ctx->vf_and_q2cid[vf_id][q_id]; - const struct rte_ether_hdr *eth_hdr = rte_pktmbuf_mtod(pkt, void *); - -#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1 - nlog("*** processing RX'ed packet of size %d ***", - rte_pktmbuf_data_len(pkt)); - /* TODO: just dump ethernet header in readable format? */ -#endif - -#if defined(DPDKIO_DEBUG) && DPDKIO_DEBUG > 1 - { - char dst[ETHER_ADDR_FMT_SIZE] = "(empty)"; - char src[ETHER_ADDR_FMT_SIZE] = "(empty)"; - - ether_format_addr(dst, sizeof(dst), ð_hdr->d_addr); - ether_format_addr(src, sizeof(src), ð_hdr->s_addr); - nlog("src: %s dst: %s ethertype: %.4X", dst, src, - rte_be_to_cpu_16(eth_hdr->ether_type)); - } -#endif - - /* Cut out the ethernet header. It's not needed anymore. */ - if (rte_pktmbuf_adj(pkt, sizeof(*eth_hdr)) == NULL) { - wlog("Packet too short, dropping"); - return 0; - } - + ret = xran_handle_ether(ETHER_TYPE_ECPRI, pkt_q, port_id, p_cid, num); - return xran_handle_ether(rte_be_to_cpu_16(eth_hdr->ether_type), pkt, rx_time); + return MBUF_FREE; } /* Check the link status of all ports in up to 9s, and print them finally */ @@ -230,17 +215,112 @@ static void check_port_link_status(uint8_t portid) } } +/** + * create a flow rule that sends packets with matching pc_id + * to selected queue. + * + * @param port_id + * The selected port. + * @param rx_q + * The selected target queue. + * @param pc_id_be + * The value to apply to the pc_id. + * @param[out] error + * Perform verbose error reporting if not NULL. + * + * @return + * A flow if the rule could be created else return NULL. + */ +struct rte_flow * +generate_ecpri_flow(uint16_t port_id, uint16_t rx_q, uint16_t pc_id_be, struct rte_flow_error *error) +{ + struct rte_flow *flow = NULL; +#if (RTE_VER_YEAR >= 21) +#define MAX_PATTERN_NUM 3 +#define MAX_ACTION_NUM 2 + struct rte_flow_attr attr; + struct rte_flow_item pattern[MAX_PATTERN_NUM]; + struct rte_flow_action action[MAX_ACTION_NUM]; + + struct rte_flow_action_queue queue = { .index = rx_q }; + struct rte_flow_item_ecpri ecpri_spec; + struct rte_flow_item_ecpri ecpri_mask; + + int res; + print_dbg("%s\n", __FUNCTION__); + memset(pattern, 0, sizeof(pattern)); + memset(action, 0, sizeof(action)); + + /* + * set the rule attribute. + * in this case only ingress packets will be checked. + */ + memset(&attr, 0, sizeof(struct rte_flow_attr)); + attr.ingress = 1; + + /* + * create the action sequence. + * one action only, move packet to queue + */ + action[0].type = RTE_FLOW_ACTION_TYPE_QUEUE; + action[0].conf = &queue; + action[1].type = RTE_FLOW_ACTION_TYPE_END; + + /* + * set the first level of the pattern (ETH). + * since in this example we just want to get the + * eCPRI we set this level to allow all. + */ + pattern[0].type = RTE_FLOW_ITEM_TYPE_ETH; + + memset(&ecpri_spec, 0, sizeof(struct rte_flow_item_ecpri)); + memset(&ecpri_mask, 0, sizeof(struct rte_flow_item_ecpri)); + + ecpri_spec.hdr.common.type = RTE_ECPRI_MSG_TYPE_IQ_DATA; + ecpri_spec.hdr.type0.pc_id = pc_id_be; + + ecpri_mask.hdr.common.type = 0xff; + ecpri_mask.hdr.type0.pc_id = 0xffff; + + ecpri_spec.hdr.common.u32 = rte_cpu_to_be_32(ecpri_spec.hdr.common.u32); + + pattern[1].type = RTE_FLOW_ITEM_TYPE_ECPRI; + pattern[1].spec = &ecpri_spec; + pattern[1].mask = &ecpri_mask; + + struct rte_flow_item_ecpri *pecpri_spec = (struct rte_flow_item_ecpri *)pattern[1].spec; + struct rte_flow_item_ecpri *pecpri_mask = (struct rte_flow_item_ecpri *)pattern[1].mask; + print_dbg("RTE_FLOW_ITEM_TYPE_ECPRI\n"); + print_dbg("spec type %x pc_id %x\n", pecpri_spec->hdr.common.type, pecpri_spec->hdr.type0.pc_id); + print_dbg("mask type %x pc_id %x\n", pecpri_mask->hdr.common.type, pecpri_mask->hdr.type0.pc_id); + + /* the final level must be always type end */ + pattern[2].type = RTE_FLOW_ITEM_TYPE_END; + + res = rte_flow_validate(port_id, &attr, pattern, action, error); + if (!res) + flow = rte_flow_create(port_id, &attr, pattern, action, error); + else { + rte_panic("Flow can't be created %d message: %s\n", + error->type, + error->message ? error->message : "(no stated reason)"); + } +#endif + return flow; +} + int32_t xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, int *lcore_id, struct rte_ether_addr *p_o_du_addr, - struct rte_ether_addr *p_ru_addr) + struct rte_ether_addr *p_ru_addr, uint32_t mtu) { uint16_t port[XRAN_VF_MAX]; struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); int i,ivf; char core_mask[64]; - uint64_t c_mask = 0; + uint64_t c_mask = 0L; + uint64_t c_mask_64_127 = 0L; uint64_t nWorkerCore = 1; uint32_t coreNum = sysconf(_SC_NPROCESSORS_CONF); char bbdev_wdev[32] = ""; @@ -249,9 +329,14 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, char socket_mem[32] = "--socket-mem=8192"; char socket_limit[32] = "--socket-limit=8192"; char ring_name[32] = ""; + int32_t xran_port = -1; + portid_t port_id; + queueid_t qi = 0; + uint16_t count; char *argv[] = { name, core_mask, "-n2", iova_mode, socket_mem, socket_limit, "--proc-type=auto", - "--file-prefix", name, "-w", "0000:00:00.0", bbdev_wdev, bbdev_vdev}; + "--file-prefix", name, "-a0000:00:00.0", bbdev_wdev, bbdev_vdev}; + if (io_cfg == NULL) return 0; @@ -260,14 +345,18 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_ON){ // hw-accelerated bbdev printf("hw-accelerated bbdev %s\n", io_cfg->bbdev_dev[0]); - snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-w %s", io_cfg->bbdev_dev[0]); + + snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-a%s", io_cfg->bbdev_dev[0]); + } else if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_OFF){ - // hw-accelerated bbdev disable - if(io_cfg->bbdev_dev[0]){ - printf("hw-accelerated bbdev disable %s\n", io_cfg->bbdev_dev[0]); - snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-b %s", io_cfg->bbdev_dev[0]); - } + snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "%s", "--vdev=baseband_turbo_sw"); + } else if (io_cfg->bbdev_mode == XRAN_BBDEV_MODE_HW_SW){ + printf("software and hw-accelerated bbdev %s\n", io_cfg->bbdev_dev[0]); + + snprintf(bbdev_wdev, RTE_DIM(bbdev_wdev), "-a%s", io_cfg->bbdev_dev[0]); + + snprintf(bbdev_vdev, RTE_DIM(bbdev_vdev), "%s", "--vdev=baseband_turbo_sw"); } else { rte_panic("Cannot init DPDK incorrect [bbdev_mode %d]\n", io_cfg->bbdev_mode); } @@ -282,27 +371,46 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, snprintf(socket_limit, RTE_DIM(socket_limit), "--socket-limit=%d", io_cfg->dpdkMemorySize); } - c_mask = (long)(1L << io_cfg->core) | - (long)(1L << io_cfg->system_core) | - (long)(1L << io_cfg->timing_core); + if (io_cfg->core < 64) + c_mask |= (long)(1L << io_cfg->core); + else + c_mask_64_127 |= (long)(1L << (io_cfg->core - 64)); + + if (io_cfg->system_core < 64) + c_mask |= (long)(1L << io_cfg->system_core); + else + c_mask_64_127 |= (long)(1L << (io_cfg->system_core - 64)); + + if (io_cfg->timing_core < 64) + c_mask |= (long)(1L << io_cfg->timing_core); + else + c_mask_64_127 |= (long)(1L << (io_cfg->timing_core - 64)); nWorkerCore = 1L; - for (i = 0; i < coreNum; i++) { + for (i = 0; i < coreNum && i < 64; i++) { if (nWorkerCore & (uint64_t)io_cfg->pkt_proc_core) { c_mask |= nWorkerCore; } nWorkerCore = nWorkerCore << 1; } - printf("total cores %d c_mask 0x%lx core %d [id] system_core %d [id] pkt_proc_core 0x%lx [mask] pkt_aux_core %d [id] timing_core %d [id]\n", - coreNum, c_mask, io_cfg->core, io_cfg->system_core, io_cfg->pkt_proc_core, io_cfg->pkt_aux_core, io_cfg->timing_core); + nWorkerCore = 1L; + for (i = 64; i < coreNum && i < 128; i++) { + if (nWorkerCore & (uint64_t)io_cfg->pkt_proc_core_64_127) { + c_mask_64_127 |= nWorkerCore; + } + nWorkerCore = nWorkerCore << 1; + } + + printf("total cores %d c_mask 0x%lx%016lx core %d [id] system_core %d [id] pkt_proc_core 0x%lx%016lx [mask] pkt_aux_core %d [id] timing_core %d [id]\n", + coreNum, c_mask_64_127, c_mask, io_cfg->core, io_cfg->system_core, io_cfg->pkt_proc_core_64_127, io_cfg->pkt_proc_core, io_cfg->pkt_aux_core, io_cfg->timing_core); - snprintf(core_mask, sizeof(core_mask), "-c 0x%lx", c_mask); + snprintf(core_mask, sizeof(core_mask), "-c 0x%lx%016lx",c_mask_64_127,c_mask); ctx->io_cfg = *io_cfg; for (ivf = 0; ivf < XRAN_VF_MAX; ivf++){ - for (i = 0; i <= ID_BROADCAST; i++) /* Initialize all as broadcast */ + for (i = 0; i < ID_MAX; i++) /* Initialize all as broadcast */ memset(&ctx->entities[ivf][i], 0xFF, sizeof(ctx->entities[0][0])); } @@ -313,13 +421,16 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, } printf("\n"); - /* This will return on system_core, which is not necessarily the * one we're on right now. */ if (rte_eal_init(RTE_DIM(argv), argv) < 0) rte_panic("Cannot init EAL: %s\n", rte_strerror(rte_errno)); - xran_init_mbuf_pool(); + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + rte_exit(EXIT_FAILURE, + "Secondary process type not supported.\n"); + + xran_init_mbuf_pool(mtu); #ifdef RTE_LIBRTE_PDUMP /* initialize packet capture framework */ @@ -328,9 +439,6 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, /* Timers. */ rte_timer_subsystem_init(); - rte_timer_init(&ctx->timer_ping); - rte_timer_init(&ctx->timer_sync); - rte_timer_init(&ctx->timer_tx); *lcore_id = rte_get_next_lcore(rte_lcore_id(), 0, 0); @@ -352,27 +460,37 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, RTE_ETH_FOREACH_MATCHING_DEV(port_id, io_cfg->dpdk_dev[i], &iterator){ port[i] = port_id; - xran_init_port(port[i]); - } - } else { - printf("no DPDK port provided\n"); + xran_init_port(port[i], io_cfg->num_rxq, mtu); } - if(!(i & 1) ){ + if(!(i & 1) || io_cfg->one_vf_cu_plane){ snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "tx_ring_up", i); - ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING, - rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ); - snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "rx_ring_up", i); - ctx->rx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING, + ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING_TRX, rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ); + PANIC_ON(ctx->tx_ring[i] == NULL, "failed to allocate tx ring"); + for(qi = 0; qi < io_cfg->num_rxq; qi++) { + snprintf(ring_name, RTE_DIM(ring_name), "%s_%d_%d", "rx_ring_up", i, qi); + ctx->rx_ring[i][qi] = rte_ring_create(ring_name, NUM_MBUFS_RING_TRX, + rte_lcore_to_socket_id(*lcore_id), RING_F_SP_ENQ); + PANIC_ON(ctx->rx_ring[i][qi] == NULL, "failed to allocate rx ring"); + } }else { snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "tx_ring_cp", i); - ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING, - rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ); - snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "rx_ring_cp", i); - ctx->rx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING, + ctx->tx_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING_TRX, rte_lcore_to_socket_id(*lcore_id), RING_F_SC_DEQ); + PANIC_ON(ctx->tx_ring[i] == NULL, "failed to allocate rx ring"); + for(qi = 0; qi < io_cfg->num_rxq; qi++) { + snprintf(ring_name, RTE_DIM(ring_name), "%s_%d_%d", "rx_ring_cp", i, qi); + ctx->rx_ring[i][qi] = rte_ring_create(ring_name, NUM_MBUFS_RING_TRX, + rte_lcore_to_socket_id(*lcore_id), RING_F_SP_ENQ); + PANIC_ON(ctx->rx_ring[i][qi] == NULL, "failed to allocate rx ring"); + } + } + } else { + printf("no DPDK port provided\n"); + xran_init_port_mempool(i, mtu); } + if(io_cfg->dpdk_dev[i]){ check_port_link_status(port[i]); } @@ -380,37 +498,64 @@ xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, } else { rte_panic("ethdi_dpdk_io_loop() failed to start with RTE_PROC_SECONDARY\n"); } - PANIC_ON(ctx->tx_ring == NULL, "failed to allocate tx ring"); - PANIC_ON(ctx->rx_ring == NULL, "failed to allocate rx ring"); - PANIC_ON(ctx->pkt_dump_ring == NULL, "failed to allocate pkt dumping ring"); + for (i = 0; i < XRAN_VF_MAX && i < io_cfg->num_vfs; i++){ ctx->io_cfg.port[i] = port[i]; print_dbg("port_id 0x%04x\n", ctx->io_cfg.port[i]); } + for (i = 0; i < XRAN_VF_MAX; i++){ + ctx->vf2xran_port[i] = 0xFFFF; + ctx->rxq_per_port[i] = 1; + for (qi = 0; qi < XRAN_VF_QUEUE_MAX; qi++){ + ctx->vf_and_q2pc_id[i][qi] = 0xFFFF; + + ctx->vf_and_q2cid[i][qi].cuPortId = 0xFF; + ctx->vf_and_q2cid[i][qi].bandSectorId = 0xFF; + ctx->vf_and_q2cid[i][qi].ccId = 0xFF; + ctx->vf_and_q2cid[i][qi].ruPortId = 0xFF; + } + } + for (i = 0; i < XRAN_VF_MAX && i < io_cfg->num_vfs; i++){ if(io_cfg->dpdk_dev[i]){ struct rte_ether_addr *p_addr; + + if(i % (io_cfg->nEthLinePerPort * (2 - 1*ctx->io_cfg.one_vf_cu_plane)) == 0) /* C-p and U-p VFs per line */ + xran_port +=1; + rte_eth_macaddr_get(port[i], &ctx->entities[i][io_cfg->id]); p_addr = &ctx->entities[i][io_cfg->id]; - printf("vf %u local SRC MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 + printf("[%2d] vf %2u local SRC MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 " %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", + (unsigned)xran_port, (unsigned)i, p_addr->addr_bytes[0], p_addr->addr_bytes[1], p_addr->addr_bytes[2], p_addr->addr_bytes[3], p_addr->addr_bytes[4], p_addr->addr_bytes[5]); p_addr = &p_ru_addr[i]; - printf("vf %u remote DST MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 + printf("[%2d] vf %2u remote DST MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 " %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", + (unsigned)xran_port, (unsigned)i, p_addr->addr_bytes[0], p_addr->addr_bytes[1], p_addr->addr_bytes[2], p_addr->addr_bytes[3], p_addr->addr_bytes[4], p_addr->addr_bytes[5]); rte_ether_addr_copy(&p_ru_addr[i], &ctx->entities[i][ID_O_RU]); + ctx->vf2xran_port[i] = xran_port; + ctx->rxq_per_port[i] = io_cfg->num_rxq; } } + for(i = 0; i < xran_port + 1 && i < XRAN_PORTS_NUM; i++) { + snprintf(ring_name, RTE_DIM(ring_name), "%s_%d", "dl_gen_ring_up", i); + ctx->up_dl_pkt_gen_ring[i] = rte_ring_create(ring_name, NUM_MBUFS_RING, + rte_lcore_to_socket_id(*lcore_id), /*RING_F_SC_DEQ*/0); + PANIC_ON(ctx->up_dl_pkt_gen_ring[i] == NULL, "failed to allocate dl gen ring"); + printf("created %s\n", ring_name); + } + return 1; } @@ -428,22 +573,21 @@ static inline uint16_t xran_tx_from_ring(int port, struct rte_ring *r) return 0; /* Nothing to send. */ while (1) { /* When tx queue is full it is trying again till succeed */ - t1 = MLogTick(); sent += rte_eth_tx_burst(port, 0, &mbufs[sent], dequeued - sent); - + if (sent == dequeued){ MLogTask(PID_RADIO_ETH_TX_BURST, t1, MLogTick()); - - if (sent == dequeued) return remaining; } } +} -int32_t process_dpdk_io(void) +int32_t process_dpdk_io(void* args) { struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); struct xran_io_cfg * cfg = &(xran_ethdi_get_ctx()->io_cfg); int32_t* port = &cfg->port[0]; int port_id = 0; + int qi = 0; rte_timer_manage(); @@ -453,19 +597,101 @@ int32_t process_dpdk_io(void) return 0; /* RX */ - const uint16_t rxed = rte_eth_rx_burst(port[port_id], 0, mbufs, BURST_RX_IO_SIZE); + for(qi = 0; qi < ctx->rxq_per_port[port_id]; qi++) { + const uint16_t rxed = rte_eth_rx_burst(port[port_id], qi, mbufs, BURST_RX_IO_SIZE); if (rxed != 0){ unsigned enq_n = 0; long t1 = MLogTick(); - enq_n = rte_ring_enqueue_burst(ctx->rx_ring[port_id], (void*)mbufs, rxed, NULL); + ctx->rx_vf_queue_cnt[port[port_id]][qi] += rxed; + enq_n = rte_ring_enqueue_burst(ctx->rx_ring[port_id][qi], (void*)mbufs, rxed, NULL); if(rxed - enq_n) rte_panic("error enq\n"); MLogTask(PID_RADIO_RX_VALIDATE, t1, MLogTick()); } + } /* TX */ + const uint16_t sent = xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]); + /* One way Delay Measurements */ + if ((cfg->eowd_cmn[cfg->id].owdm_enable != 0) && (cfg->eowd_cmn[cfg->id].measVf == port_id)) + { + if (!xran_ecpri_port_update_required(cfg, (uint16_t)port_id)) + { +#ifdef ORAN_OWD_DEBUG_TX_LOOP + printf("going to owd tx for port %d\n", port_id); +#endif + if (xran_ecpri_one_way_delay_measurement_transmitter((uint16_t) port_id, (void*)xran_dev_get_ctx()) != OK) + { + errx(1,"Exit pdio port_id %d", port_id); + } + } + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + + return 0; +} +int32_t process_dpdk_io_tx(void* args) +{ + struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg * cfg = &(xran_ethdi_get_ctx()->io_cfg); + int32_t* port = &cfg->port[0]; + int port_id = 0; + + //rte_timer_manage(); + + for (port_id = 0; port_id < XRAN_VF_MAX && port_id < ctx->io_cfg.num_vfs; port_id++){ + struct rte_mbuf *mbufs[BURST_RX_IO_SIZE]; + if(port[port_id] == 0xFF) + return 0; + /* TX */ + const uint16_t sent = xran_tx_from_ring(port[port_id], ctx->tx_ring[port_id]); + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + + return 0; +} + +int32_t process_dpdk_io_rx(void* args) +{ + struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg * cfg = &(xran_ethdi_get_ctx()->io_cfg); + int32_t* port = &cfg->port[0]; + int port_id = 0; + int qi = 0; + + rte_timer_manage(); + + for (port_id = 0; port_id < XRAN_VF_MAX && port_id < ctx->io_cfg.num_vfs; port_id++){ + struct rte_mbuf *mbufs[BURST_RX_IO_SIZE]; + if(port[port_id] == 0xFF) + return 0; + + /* RX */ + for(qi = 0; qi < ctx->rxq_per_port[port_id]; qi++){ + const uint16_t rxed = rte_eth_rx_burst(port[port_id], qi, mbufs, BURST_RX_IO_SIZE); + if (rxed != 0){ + unsigned enq_n = 0; + long t1 = MLogTick(); + ctx->rx_vf_queue_cnt[port[port_id]][qi] += rxed; + enq_n = rte_ring_enqueue_burst(ctx->rx_ring[port_id][qi], (void*)mbufs, rxed, NULL); + if(rxed - enq_n) + rte_panic("error enq\n"); + MLogTask(PID_RADIO_RX_VALIDATE, t1, MLogTick()); + } + } if (XRAN_STOPPED == xran_if_current_state) return -1; } diff --git a/fhi_lib/lib/ethernet/ethdi.h b/fhi_lib/lib/ethernet/ethdi.h index 1e5d4f5..dec93eb 100644 --- a/fhi_lib/lib/ethernet/ethdi.h +++ b/fhi_lib/lib/ethernet/ethdi.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -31,8 +31,11 @@ extern "C" { #endif +#include + #include #include +#include #include /* comment this to enable PDUMP @@ -47,35 +50,38 @@ extern "C" { #endif #include "ethernet.h" +#include "xran_transport.h" #include "xran_fh_o_du.h" #define XRAN_THREAD_DEFAULT_PRIO (98) - -/* If we're not receiving packets for more then this threshold... */ -//#define SLEEP_THRESHOLD (rte_get_tsc_hz() / 30) /* = 33.3(3)ms */ -/* we go to sleep for this long (usleep). Undef SLEEP_TRESHOLD to disable. */ -#define SLEEP_TIME 200 /* (us) */ -#define BCAST {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} +#define XRAN_MAX_WORKERS 6 /**< max number of worker cores */ #define TX_TIMER_INTERVAL ((rte_get_timer_hz() / 1000000000L)*interval_us*1000) /* nanosec */ -#define TX_RX_LOOP_TIME rte_get_timer_hz() / 1 +#define TX_RX_LOOP_TIME (rte_get_timer_hz() / 1) + +typedef uint8_t lcoreid_t; +typedef uint16_t portid_t; +typedef uint16_t queueid_t; +typedef uint16_t streamid_t; /* CAUTION: Keep in sync with the string table below. */ enum xran_entities_id { ID_O_DU, ID_O_RU, - ID_BROADCAST, ID_MAX }; static char *const entity_names[] = { "ORAN O-DU sim app", - "ORAN O-RU sim app", + "ORAN O-RU sim app" }; typedef int (*PROCESS_CB)(void * arg); +extern queueid_t nb_rxq; /**< Number of RX queues per port. */ +extern queueid_t nb_txq; /**< Number of TX queues per port. */ + /** * Structure storing internal configuration of workers */ @@ -85,25 +91,33 @@ struct xran_worker_config { int32_t state; }; -struct xran_ethdi_ctx -{ +struct xran_ethdi_ctx { struct xran_io_cfg io_cfg; - struct rte_ether_addr entities[XRAN_VF_MAX][ID_BROADCAST + 1]; + struct rte_ether_addr entities[XRAN_VF_MAX][ID_MAX]; + uint16_t vf2xran_port[XRAN_VF_MAX]; + uint16_t vf_and_q2pc_id[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX]; + struct xran_eaxc_info vf_and_q2cid[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX]; + uint16_t rxq_per_port[XRAN_VF_MAX]; struct rte_ring *tx_ring[XRAN_VF_MAX]; - struct rte_ring *rx_ring[XRAN_VF_MAX]; - struct rte_ring *pkt_dump_ring[XRAN_VF_MAX]; - struct rte_timer timer_autodetect; - struct rte_timer timer_ping; - struct rte_timer timer_sync; - struct rte_timer timer_tx; + struct rte_ring *rx_ring[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX]; + + struct rte_ring *up_dl_pkt_gen_ring[XRAN_PORTS_NUM]; - struct xran_worker_config pkt_wrk_cfg[RTE_MAX_LCORE]; + struct xran_worker_config time_wrk_cfg; /**< core doing polling of time */ + struct xran_worker_config pkt_wrk_cfg[RTE_MAX_LCORE]; /**< worker cores */ - unsigned pkt_stats[PKT_LAST + 1]; + phy_encoder_poll_fn bbdev_enc; /**< call back to poll BBDev encoder */ + phy_decoder_poll_fn bbdev_dec; /**< call back to poll BBDev decoder */ + + uint32_t pkt_proc_core_id; /**< core used for processing DPDK timer cb */ + uint32_t num_workers; /**< number of workers */ + uint32_t worker_core[XRAN_MAX_WORKERS]; /**< id of core used as worker */ + + uint64_t rx_vf_queue_cnt[XRAN_VF_MAX][XRAN_VF_QUEUE_MAX]; }; -enum { +enum xran_mbuf_mem_op_id { MBUF_KEEP, MBUF_FREE }; @@ -113,25 +127,29 @@ extern enum xran_if_state xran_if_current_state; static inline struct xran_ethdi_ctx *xran_ethdi_get_ctx(void) { extern struct xran_ethdi_ctx g_ethdi_ctx; - return &g_ethdi_ctx; } -typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint64_t rx_time); +typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint16_t vf_id); -typedef int (*ethertype_handler)(struct rte_mbuf *, uint64_t rx_time); -typedef int (*xran_ethdi_handler)(struct rte_mbuf *, int sender, uint64_t rx_time); +typedef int (*ethertype_handler)(struct rte_mbuf* pkt_q[], uint16_t xport_id, struct xran_eaxc_info *p_cid, uint16_t num); -int xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback); +int32_t xran_register_ethertype_handler(uint16_t ethertype, ethertype_handler callback); int32_t xran_ethdi_init_dpdk_io(char *name, const struct xran_io_cfg *io_cfg, - int *lcore_id, struct rte_ether_addr *p_o_du_addr, - struct rte_ether_addr *p_ru_addr); + int32_t *lcore_id, struct rte_ether_addr *p_o_du_addr, + struct rte_ether_addr *p_ru_addr, uint32_t mtu); struct rte_mbuf *xran_ethdi_mbuf_alloc(void); +struct rte_mbuf *xran_ethdi_mbuf_indir_alloc(void); int32_t xran_ethdi_mbuf_send(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id); int32_t xran_ethdi_mbuf_send_cp(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id); -int32_t xran_ethdi_filter_packet(struct rte_mbuf *pkt, uint64_t rx_time); -int32_t process_dpdk_io(void); +int32_t xran_ethdi_filter_packet(struct rte_mbuf *pkt[], uint16_t vf_id, uint16_t q_id, uint16_t num); +int32_t process_dpdk_io(void* args); +int32_t process_dpdk_io_tx(void* args); +int32_t process_dpdk_io_rx(void* args); + +struct rte_flow * generate_ecpri_flow(uint16_t port_id, uint16_t rx_q, uint16_t pc_id_be, struct rte_flow_error *error); + #ifdef __cplusplus } diff --git a/fhi_lib/lib/ethernet/ethernet.c b/fhi_lib/lib/ethernet/ethernet.c index 0df06c7..0930665 100644 --- a/fhi_lib/lib/ethernet/ethernet.c +++ b/fhi_lib/lib/ethernet/ethernet.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -37,12 +37,11 @@ #include #include #include - +#include #include #include #include #include -#include #include #include #include @@ -66,178 +65,98 @@ #include "ethernet.h" #include "ethdi.h" -/* Our mbuf pools. */ +/* mbuf pools */ struct rte_mempool *_eth_mbuf_pool = NULL; -struct rte_mempool *_eth_mbuf_pool_inderect = NULL; +struct rte_mempool *_eth_mbuf_pool_indirect = NULL; struct rte_mempool *_eth_mbuf_pool_rx = NULL; -struct rte_mempool *_eth_mbuf_pool_small = NULL; -struct rte_mempool *_eth_mbuf_pool_big = NULL; +struct rte_mempool *_eth_mbuf_pkt_gen = NULL; struct rte_mempool *socket_direct_pool = NULL; struct rte_mempool *socket_indirect_pool = NULL; +struct rte_mempool *_eth_mbuf_pool_vf_rx[16][RTE_MAX_QUEUES_PER_PORT] = {NULL}; +struct rte_mempool *_eth_mbuf_pool_vf_small[16] = {NULL}; -/* - * Make sure the ring indexes are big enough to cover buf space x2 - * This ring-buffer maintains the property head - tail <= RINGSIZE. - * head == tail: ring buffer empty - * head - tail == RINGSIZE: ring buffer full - */ -typedef uint16_t ring_idx; -static struct { - ring_idx head; - ring_idx read_head; - ring_idx tail; - char buf[1024]; /* needs power of 2! */ -} io_ring = { {0}, 0, 0}; - -#define RINGSIZE sizeof(io_ring.buf) -#define RINGMASK (RINGSIZE - 1) - -int __xran_delayed_msg(const char *fmt, ...) +void +xran_init_mbuf_pool(uint32_t mtu) { -#if 0 - va_list ap; - int msg_len; - char localbuf[RINGSIZE]; - ring_idx old_head, new_head; - ring_idx copy_len; - - /* first prep a copy of the message on the local stack */ - va_start(ap, fmt); - msg_len = vsnprintf(localbuf, RINGSIZE, fmt, ap); - va_end(ap); - - /* atomically reserve space in the ring */ - for (;;) { - old_head = io_ring.head; /* snapshot head */ - /* free always within range of [0, RINGSIZE] - proof by induction */ - const ring_idx free = RINGSIZE - (old_head - io_ring.tail); - - copy_len = RTE_MIN(msg_len, free); - if (copy_len <= 0) - return 0; /* vsnprintf error or ringbuff full. Drop log. */ - - new_head = old_head + copy_len; - RTE_ASSERT((ring_idx)(new_head - io_ring.tail) <= RINGSIZE); - - if (likely(__atomic_compare_exchange_n(&io_ring.head, &old_head, - new_head, 0, __ATOMIC_ACQUIRE, __ATOMIC_RELAXED))) - break; - } - - /* Now copy data in at ease. */ - const int copy_start = (old_head & RINGMASK); - if (copy_start < (new_head & RINGMASK)) /* no wrap */ - memcpy(io_ring.buf + copy_start, localbuf, copy_len); - else { /* wrap-around */ - const int chunk_len = RINGSIZE - copy_start; - - memcpy(io_ring.buf + copy_start, localbuf, chunk_len); - memcpy(io_ring.buf, localbuf + chunk_len, copy_len - chunk_len); - } - - /* wait for previous writes to complete before updating read_head. */ - while (io_ring.read_head != old_head) - rte_pause(); - io_ring.read_head = new_head; - - - return copy_len; - #endif - return 0; -} - -/* - * Display part of the message stored in the ring buffer. - * Might require multiple calls to print the full message. - * Will return 0 when nothing left to print. - */ -#if 0 -int xran_show_delayed_message(void) -{ - ring_idx tail = io_ring.tail; - ring_idx wlen = io_ring.read_head - tail; /* always within [0, RINGSIZE] */ - - if (wlen <= 0) - return 0; - - tail &= RINGMASK; /* modulo the range down now that we have wlen */ - - /* Make sure we're not going over buffer end. Next call will wrap. */ - if (tail + wlen > RINGSIZE) - wlen = RINGSIZE - tail; - - RTE_ASSERT(tail + wlen <= RINGSIZE); + uint16_t data_room_size = MBUF_POOL_ELEMENT; + printf("%s: socket %d\n",__FUNCTION__, rte_socket_id()); - /* We use write() here to avoid recaculating string length in fwrite(). */ - const ssize_t written = write(STDOUT_FILENO, io_ring.buf + tail, wlen); - if (written <= 0) - return 0; /* To avoid moving tail the wrong way on error. */ - - /* Move tail up. Only we touch it. And we only print from one core. */ - io_ring.tail += written; - - return written; /* next invocation will print the rest if any */ + if (mtu <= 1500) { + data_room_size = MBUF_POOL_ELM_SMALL; } -#endif -void xran_init_mbuf_pool(void) -{ /* Init the buffer pool */ if (rte_eal_process_type() == RTE_PROC_PRIMARY) { _eth_mbuf_pool = rte_pktmbuf_pool_create("mempool", NUM_MBUFS, - MBUF_CACHE, 0, MBUF_POOL_ELEMENT, rte_socket_id()); -#ifdef XRAN_ATTACH_MBUF - _eth_mbuf_pool_inderect = rte_pktmbuf_pool_create("mempool_indirect", NUM_MBUFS, - MBUF_CACHE, 0, MBUF_POOL_ELEMENT, rte_socket_id());*/ -#endif - _eth_mbuf_pool_rx = rte_pktmbuf_pool_create("mempool_rx", NUM_MBUFS, - MBUF_CACHE, 0, MBUF_POOL_ELEMENT, rte_socket_id()); - _eth_mbuf_pool_small = rte_pktmbuf_pool_create("mempool_small", - NUM_MBUFS, MBUF_CACHE, 0, MBUF_POOL_ELM_SMALL, rte_socket_id()); - _eth_mbuf_pool_big = rte_pktmbuf_pool_create("mempool_big", - NUM_MBUFS_BIG, 0, 0, MBUF_POOL_ELM_BIG, rte_socket_id()); + MBUF_CACHE, 0, data_room_size, rte_socket_id()); + _eth_mbuf_pool_indirect = rte_pktmbuf_pool_create("mempool_indirect", NUM_MBUFS_VF, + MBUF_CACHE, 0, 0, rte_socket_id()); + _eth_mbuf_pkt_gen = rte_pktmbuf_pool_create("mempool_pkt_gen", + NUM_MBUFS, MBUF_CACHE, 0, MBUF_POOL_PKT_GEN_ELM, rte_socket_id()); } else { _eth_mbuf_pool = rte_mempool_lookup("mempool"); - _eth_mbuf_pool_inderect = rte_mempool_lookup("mempool_indirect"); - _eth_mbuf_pool_rx = rte_mempool_lookup("mempool_rx"); - _eth_mbuf_pool_small = rte_mempool_lookup("mempool_small"); - _eth_mbuf_pool_big = rte_mempool_lookup("mempool_big"); + _eth_mbuf_pool_indirect = rte_mempool_lookup("mempool_indirect"); + _eth_mbuf_pkt_gen = rte_mempool_lookup("mempool_pkt_gen"); } + if (_eth_mbuf_pool == NULL) rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); -#ifdef XRAN_ATTACH_MBUF - if (_eth_mbuf_pool_inderect == NULL) - rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); -#endif - if (_eth_mbuf_pool_rx == NULL) + if (_eth_mbuf_pool_indirect == NULL) rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); - if (_eth_mbuf_pool_small == NULL) - rte_panic("Cannot create small mbuf pool: %s\n", rte_strerror(rte_errno)); - if (_eth_mbuf_pool_big == NULL) - rte_panic("Cannot create big mbuf pool: %s\n", rte_strerror(rte_errno)); + if (_eth_mbuf_pkt_gen == NULL) + rte_panic("Cannot create packet gen pool: %s\n", rte_strerror(rte_errno)); if (socket_direct_pool == NULL) socket_direct_pool = _eth_mbuf_pool; if (socket_indirect_pool == NULL) - socket_indirect_pool = _eth_mbuf_pool_inderect; + socket_indirect_pool = _eth_mbuf_pool_indirect; +} + +/* Configure the Rx with optional split. */ +int +rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, + uint16_t nb_rx_desc, unsigned int socket_id, + struct rte_eth_rxconf *rx_conf, struct rte_mempool *mp) +{ + unsigned int i, mp_n; + int ret; +#ifndef RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT +#define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT 0x00100000 +#endif + if ((rx_conf->offloads & RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT) == 0) { +#if (RTE_VER_YEAR >= 21) + rx_conf->rx_seg = NULL; + rx_conf->rx_nseg = 0; +#endif + ret = rte_eth_rx_queue_setup(port_id, rx_queue_id, + nb_rx_desc, socket_id, + rx_conf, mp); + return ret; + + } else { + printf("rx_queue_setup error\n"); + ret = -EINVAL; + return ret; + } } /* Init NIC port, then start the port */ -void xran_init_port(int p_id) +void xran_init_port(int p_id, uint16_t num_rxq, uint32_t mtu) { static uint16_t nb_rxd = BURST_SIZE; static uint16_t nb_txd = BURST_SIZE; struct rte_ether_addr addr; - struct rte_eth_rxmode rxmode = - { .split_hdr_size = 0, + struct rte_eth_rxmode rxmode = { + .split_hdr_size = 0, .max_rx_pkt_len = MAX_RX_LEN, - .offloads=(DEV_RX_OFFLOAD_JUMBO_FRAME /*|DEV_RX_OFFLOAD_CRC_STRIP*/) + .offloads = DEV_RX_OFFLOAD_JUMBO_FRAME }; struct rte_eth_txmode txmode = { - .mq_mode = ETH_MQ_TX_NONE + .mq_mode = ETH_MQ_TX_NONE, + .offloads = DEV_TX_OFFLOAD_MULTI_SEGS }; struct rte_eth_conf port_conf = { .rxmode = rxmode, @@ -250,12 +169,28 @@ void xran_init_port(int p_id) struct rte_eth_dev_info dev_info; const char *drv_name = ""; int sock_id = rte_eth_dev_socket_id(p_id); + char rx_pool_name[32] = ""; + uint16_t data_room_size = MBUF_POOL_ELEMENT; + uint16_t qi = 0; + uint32_t num_mbufs = 0; + + if (mtu <= 1500) { + rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; + rxmode.max_rx_pkt_len = RTE_ETHER_MAX_LEN; + data_room_size = MBUF_POOL_ELM_SMALL; + } rte_eth_dev_info_get(p_id, &dev_info); if (dev_info.driver_name) drv_name = dev_info.driver_name; printf("initializing port %d for TX, drv=%s\n", p_id, drv_name); + if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE){ + printf("set DEV_TX_OFFLOAD_MBUF_FAST_FREE\n"); + port_conf.txmode.offloads |= + DEV_TX_OFFLOAD_MBUF_FAST_FREE; + } + rte_eth_macaddr_get(p_id, &addr); printf("Port %u MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 @@ -264,8 +199,16 @@ void xran_init_port(int p_id) addr.addr_bytes[0], addr.addr_bytes[1], addr.addr_bytes[2], addr.addr_bytes[3], addr.addr_bytes[4], addr.addr_bytes[5]); + if(num_rxq > 1) { + nb_rxd = 2048; + num_mbufs = 2*nb_rxd-1; + } else { + nb_rxd = BURST_SIZE; + num_mbufs = NUM_MBUFS; + } + /* Init port */ - ret = rte_eth_dev_configure(p_id, 1, 1, &port_conf); + ret = rte_eth_dev_configure(p_id, num_rxq, 1, &port_conf); if (ret < 0) rte_panic("Cannot configure port %u (%d)\n", p_id, ret); @@ -278,28 +221,77 @@ void xran_init_port(int p_id) } printf("Port %u: nb_rxd %d nb_txd %d\n", p_id, nb_rxd, nb_txd); + for (qi = 0; qi < num_rxq; qi++) { + snprintf(rx_pool_name, RTE_DIM(rx_pool_name), "%s_p_%d_q_%d", "mp_rx_", p_id, qi); + printf("[%d] %s num blocks %d\n", p_id, rx_pool_name, num_mbufs); + _eth_mbuf_pool_vf_rx[p_id][qi] = rte_pktmbuf_pool_create(rx_pool_name, num_mbufs, + MBUF_CACHE, 0, data_room_size, rte_socket_id()); + + if (_eth_mbuf_pool_vf_rx[p_id][qi] == NULL) + rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); + } + + snprintf(rx_pool_name, RTE_DIM(rx_pool_name), "%s_%d", "mempool_small_", p_id); + printf("[%d] %s\n", p_id, rx_pool_name); + _eth_mbuf_pool_vf_small[p_id] = rte_pktmbuf_pool_create(rx_pool_name, NUM_MBUFS_VF, + MBUF_CACHE, 0, MBUF_POOL_ELM_SMALL_INDIRECT, rte_socket_id()); + + if (_eth_mbuf_pool_vf_small[p_id] == NULL) + rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); + /* Init RX queues */ + fflush(stdout); rxq_conf = dev_info.default_rxconf; - ret = rte_eth_rx_queue_setup(p_id, 0, nb_rxd, - sock_id, &rxq_conf, _eth_mbuf_pool_rx); + + for (qi = 0; qi < num_rxq; qi++) { + ret = rx_queue_setup(p_id, qi, nb_rxd, + sock_id, &rxq_conf, _eth_mbuf_pool_vf_rx[p_id][qi]); + } + if (ret < 0) rte_panic("Cannot init RX for port %u (%d)\n", p_id, ret); /* Init TX queues */ + fflush(stdout); txq_conf = dev_info.default_txconf; + ret = rte_eth_tx_queue_setup(p_id, 0, nb_txd, sock_id, &txq_conf); if (ret < 0) rte_panic("Cannot init TX for port %u (%d)\n", p_id, ret); + ret = rte_eth_dev_set_ptypes(p_id, RTE_PTYPE_UNKNOWN, NULL, 0); + if (ret < 0) + rte_panic("Port %d: Failed to disable Ptype parsing\n", p_id); + /* Start port */ ret = rte_eth_dev_start(p_id); if (ret < 0) rte_panic("Cannot start port %u (%d)\n", p_id, ret); +} +void xran_init_port_mempool(int p_id, uint32_t mtu) +{ + int ret; + int sock_id = rte_eth_dev_socket_id(p_id); + char rx_pool_name[32] = ""; + uint16_t data_room_size = MBUF_POOL_ELEMENT; + + if (mtu <= 1500) { + data_room_size = MBUF_POOL_ELM_SMALL; } + snprintf(rx_pool_name, RTE_DIM(rx_pool_name), "%s_%d", "mempool_small_", p_id); + printf("[%d] %s\n", p_id, rx_pool_name); + _eth_mbuf_pool_vf_small[p_id] = rte_pktmbuf_pool_create(rx_pool_name, NUM_MBUFS_VF, + MBUF_CACHE, 0, MBUF_POOL_ELM_SMALL, rte_socket_id()); + + if (_eth_mbuf_pool_vf_small[p_id] == NULL) + rte_panic("Cannot create mbuf pool: %s\n", rte_strerror(rte_errno)); + + +} /* Prepend ethernet header, possibly vlan tag. */ void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb) diff --git a/fhi_lib/lib/ethernet/ethernet.h b/fhi_lib/lib/ethernet/ethernet.h index bc4bffb..f6b1b21 100644 --- a/fhi_lib/lib/ethernet/ethernet.h +++ b/fhi_lib/lib/ethernet/ethernet.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,8 +23,8 @@ * @author Intel Corporation **/ -#ifndef AUXLIB_ETHERNET_H -#define AUXLIB_ETHERNET_H +#ifndef _XRANLIB_ETHERNET_H_ +#define _XRANLIB_ETHERNET_H_ #ifdef __cplusplus extern "C" { @@ -34,80 +34,44 @@ extern "C" { #include #include -#define BURST_SIZE 4096 + +#define BURST_SIZE 4096 /** IAVF_MAX_RING_DESC 4096 */ #define ETHER_TYPE_ETHDI RTE_ETHER_TYPE_IPV4 /* hack needed for jumbo frames */ #define ETHER_TYPE_ECPRI 0xAEFE -#define ETHER_TYPE_SYNC 0xBEFE -#define ETHER_TYPE_START_TX 0xCEFE #define NUM_MBUFS 65535/*16383*/ /*65535*/ /** optimal is n = (2^q - 1) */ #define NUM_MBUFS_RING NUM_MBUFS+1 /** The size of the ring (must be a power of 2) */ +#define NUM_MBUFS_VF 1048575 + +#define NUM_MBUFS_RING_TRX 2097152 + #define MBUF_CACHE 256 +#define MBUF_POOL_ELM_SMALL_INDIRECT (128 + RTE_PKTMBUF_HEADROOM ) /* indirect */ + #define MBUF_POOL_ELM_SMALL (1500 + RTE_PKTMBUF_HEADROOM )/* regular ethernet MTU, most compatible */ #define MBUF_POOL_ELEMENT (MAX_RX_LEN + RTE_PKTMBUF_HEADROOM) +#define MBUF_POOL_PKT_GEN_ELM (256 + RTE_PKTMBUF_HEADROOM ) + #define MAX_RX_LEN 9600 #define MAX_TX_LEN (MAX_RX_LEN - 14) /* headroom for rx driver */ #define MAX_DATA_SIZE (MAX_TX_LEN - sizeof(struct ether_hdr) - \ sizeof(struct ethdi_hdr) - sizeof(struct burst_hdr)) -/* Looks like mbuf size is limited to 16 bits - see the buf_len field. */ -#define MBUF_POOL_ELM_BIG USHRT_MAX -#define NUM_MBUFS_BIG 64 - -#define DEFAULT_DUMP_LENGTH 96 - extern struct rte_mempool *_eth_mbuf_pool; -extern struct rte_mempool *_eth_mbuf_pool_small; + +extern struct rte_mempool *_eth_mbuf_pkt_gen; extern struct rte_mempool *_eth_mbuf_pool_big; extern struct rte_mempool *socket_direct_pool; extern struct rte_mempool *socket_indirect_pool; -/* Do NOT change the order of this enum and below - * - need to be in sync with the table of handlers in testue.c */ -enum pkt_type -{ - PKT_ZERO, - PKT_EMPTY, - PKT_DISCOVER_REQUEST, - PKT_PING, - PKT_PONG, - PKT_DISCOVER_REPLY, - PKT_LTE_DATA, - PKT_LTE_CONTROL, - PKT_BURST, - PKT_DATATEST, - PKT_ADD_ETHDEV, - PKT_SYNC_START, - PKT_LAST, -}; +extern struct rte_mempool *_eth_mbuf_pool_vf_rx[16][RTE_MAX_QUEUES_PER_PORT]; +extern struct rte_mempool *_eth_mbuf_pool_vf_small[16]; -/* Do NOT change the order. */ -static char * const xran_pkt_descriptions[PKT_LAST + 1] = { - "ZERO", - "empty packet", - "discovery request packet", - "ping packet", - "pong packet", - "discovery reply packet", - "LTE data packet", - "LTE control packet", - "BURST packet", - "DATATEST packet", - "Add ethernet port command packet", - "SYNC-START packet", - "LAST packet", -}; -struct burst_hdr { - int8_t pkt_idx; - int8_t total_pkts; - int8_t original_type; - int8_t data[]; -}; struct ethdi_hdr { uint8_t pkt_type; @@ -117,34 +81,11 @@ struct ethdi_hdr { }; -void xran_init_mbuf_pool(void); - -void xran_init_port(int port); - +void xran_init_mbuf_pool(uint32_t mtu); +void xran_init_port(int port, uint16_t num_rxq, uint32_t mtu); +void xran_init_port_mempool(int p_id, uint32_t mtu); void xran_add_eth_hdr_vlan(struct rte_ether_addr *dst, uint16_t ethertype, struct rte_mbuf *mb); -#if 0 -void xran_memdump(void *addr, int len); -void xran_add_eth_hdr(struct ether_addr *dst, uint16_t ethertype, struct rte_mbuf *); -int xran_send_mbuf(struct ether_addr *dst, struct rte_mbuf *mb); -int xran_send_message_burst(int dst_id, int pkt_type, void *body, int len); -int xran_show_delayed_message(void); -#endif -/* - * Print a message after all critical processing done. - * Mt-safe. 4 variants - normal, warning, error and debug log. - */ -int __xran_delayed_msg(const char *fmt, ...); -#define nlog(m, ...) __xran_delayed_msg("%s(): " m "\n", __FUNCTION__, ##__VA_ARGS__) -#define delayed_message nlog /* this is the old alias for this function */ -#define wlog(m, ...) nlog("WARNING: " m, ##__VA_ARGS__) -#define elog(m, ...) nlog("ERROR: " m, ##__VA_ARGS__) -#ifdef DEBUG -# define dlog(m, ...) nlog("DEBUG: " m, ##__VA_ARGS__) -#else -# define dlog(m, ...) -#endif - #define PANIC_ON(x, m, ...) do { if (unlikely(x)) \ rte_panic("%s: " m "\n", #x, ##__VA_ARGS__); } while (0) @@ -156,7 +97,7 @@ static inline int xran_enqueue_mbuf(struct rte_mbuf *mb, struct rte_ring *r) } rte_pktmbuf_free(mb); - wlog("failed to enqueue packet on port %d (ring full)", mb->port); + //print_err("failed to enqueue packet on port %d (ring full)", mb->port); return 0; /* fail */ } @@ -165,4 +106,4 @@ static inline int xran_enqueue_mbuf(struct rte_mbuf *mb, struct rte_ring *r) } #endif -#endif /* AUXLIB_ETHERNET_H */ +#endif /* _XRANLIB_ETHERNET_H_ */ diff --git a/fhi_lib/lib/src/xran_app_frag.c b/fhi_lib/lib/src/xran_app_frag.c index 96eb378..cb526ee 100644 --- a/fhi_lib/lib/src/xran_app_frag.c +++ b/fhi_lib/lib/src/xran_app_frag.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,7 +17,7 @@ *******************************************************************************/ /** - * @brief xRAN application frgamentation for U-plane packets + * @brief xRAN application fragmentation for U-plane packets * * @file xran_app_frag.c * @ingroup group_source_xran @@ -27,7 +27,7 @@ #include #include #include - +#include #include #include #include @@ -39,38 +39,63 @@ #include "xran_printf.h" #include "xran_common.h" -/* Fragment alignment */ -#define XRAN_PAYLOAD_RB_ALIGN (N_SC_PER_PRB*(IQ_BITS/8)*2) /**< at least 12*4=48 bytes per one RB */ - static inline void __fill_xranhdr_frag(struct xran_up_pkt_hdr *dst, const struct xran_up_pkt_hdr *src, uint16_t rblen_bytes, - uint16_t rboff_bytes, struct xran_section_info *sectinfo, uint32_t mf, uint8_t *seqid) + uint16_t rboff_bytes, uint16_t startPrbc, uint16_t numPrbc, uint32_t mf, uint8_t *seqid, uint8_t iqWidth) { struct data_section_hdr loc_data_sec_hdr; struct xran_ecpri_hdr loc_ecpri_hdr; rte_memcpy(dst, src, sizeof(*dst)); - dst->ecpri_hdr.ecpri_seq_id.seq_id = (*seqid)++; + dst->ecpri_hdr.ecpri_seq_id.bits.seq_id = (*seqid)++; - print_dbg("sec [%d %d] sec %d mf %d g_sec %d\n",sectinfo->startPrbc, sectinfo->numPrbc, dst->ecpri_hdr.ecpri_seq_id.seq_id, mf, *seqid); + print_dbg("sec [%d %d] sec %d mf %d g_sec %d\n",startPrbc, numPrbc, dst->ecpri_hdr.ecpri_seq_id.seq_id, mf, *seqid); loc_data_sec_hdr.fields.all_bits = rte_be_to_cpu_32(dst->data_sec_hdr.fields.all_bits); /* update RBs */ - loc_data_sec_hdr.fields.start_prbu = sectinfo->startPrbc + rboff_bytes/(N_SC_PER_PRB*(IQ_BITS/8*2)); - loc_data_sec_hdr.fields.num_prbu = rblen_bytes/(N_SC_PER_PRB*(IQ_BITS/8*2)); + loc_data_sec_hdr.fields.start_prbu = startPrbc + rboff_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth); + loc_data_sec_hdr.fields.num_prbu = rblen_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth); - print_dbg("sec [%d %d] pkt [%d %d] rboff_bytes %d rblen_bytes %d\n",sectinfo->startPrbc, sectinfo->numPrbc, loc_data_sec_hdr.fields.start_prbu, loc_data_sec_hdr.fields.num_prbu, + print_dbg("sec [%d %d] pkt [%d %d] rboff_bytes %d rblen_bytes %d\n",startPrbc, numPrbc, loc_data_sec_hdr.fields.start_prbu, loc_data_sec_hdr.fields.num_prbu, rboff_bytes, rblen_bytes); dst->data_sec_hdr.fields.all_bits = rte_cpu_to_be_32(loc_data_sec_hdr.fields.all_bits); - /* update length */ - dst->ecpri_hdr.cmnhdr.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) + + dst->ecpri_hdr.cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) + sizeof(struct data_section_hdr) + rblen_bytes + xran_get_ecpri_hdr_size()); } +static inline void __fill_xranhdr_frag_comp(struct xran_up_pkt_hdr_comp *dst, + const struct xran_up_pkt_hdr_comp *src, uint16_t rblen_bytes, + uint16_t rboff_bytes, uint16_t startPrbc, uint16_t numPrbc, uint32_t mf, uint8_t *seqid, uint8_t iqWidth) +{ + struct data_section_hdr loc_data_sec_hdr; + struct xran_ecpri_hdr loc_ecpri_hdr; + + rte_memcpy(dst, src, sizeof(*dst)); + + dst->ecpri_hdr.ecpri_seq_id.bits.seq_id = (*seqid)++; + + print_dbg("sec [%d %d] sec %d mf %d g_sec %d\n", startPrbc, numPrbc, dst->ecpri_hdr.ecpri_seq_id.seq_id, mf, *seqid); + + loc_data_sec_hdr.fields.all_bits = rte_be_to_cpu_32(dst->data_sec_hdr.fields.all_bits); + + /* update RBs */ + loc_data_sec_hdr.fields.start_prbu = startPrbc + rboff_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth); + loc_data_sec_hdr.fields.num_prbu = rblen_bytes/XRAN_PAYLOAD_1_RB_SZ(iqWidth); + + print_dbg("sec [%d %d] pkt [%d %d] rboff_bytes %d rblen_bytes %d\n",startPrbc, numPrbc, loc_data_sec_hdr.fields.start_prbu, loc_data_sec_hdr.fields.num_prbu, + rboff_bytes, rblen_bytes); + + dst->data_sec_hdr.fields.all_bits = rte_cpu_to_be_32(loc_data_sec_hdr.fields.all_bits); + + dst->ecpri_hdr.cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + sizeof(struct data_section_compression_hdr) + rblen_bytes + xran_get_ecpri_hdr_size()); +} + + static inline void __free_fragments(struct rte_mbuf *mb[], uint32_t num) { @@ -107,8 +132,11 @@ xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ uint16_t mtu_size, struct rte_mempool *pool_direct, struct rte_mempool *pool_indirect, - struct xran_section_info *sectinfo, - uint8_t *seqid) + int16_t nRBStart, /**< start RB of RB allocation */ + int16_t nRBSize, /**< number of RBs used */ + uint8_t *seqid, + uint8_t iqWidth, + uint8_t isUdCompHdr) { struct rte_mbuf *in_seg = NULL; uint32_t out_pkt_pos = 0, in_seg_data_pos = 0; @@ -118,28 +146,48 @@ xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ struct eth_xran_up_pkt_hdr *in_hdr; struct xran_up_pkt_hdr *in_hdr_xran; + struct eth_xran_up_pkt_hdr_comp *in_hdr_comp = NULL; + struct xran_up_pkt_hdr_comp *in_hdr_xran_comp = NULL; + + int32_t eth_xran_up_headers_sz = 0; + eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr); + + if(isUdCompHdr) + eth_xran_up_headers_sz += sizeof(struct data_section_compression_hdr); + /* * Ensure the XRAN payload length of all fragments is aligned to a * multiple of 48 bytes (1 RB with IQ of 16 bits each) */ - frag_size = ((mtu_size - sizeof(struct eth_xran_up_pkt_hdr) - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_RB_ALIGN)*XRAN_PAYLOAD_RB_ALIGN; - + frag_size = ((mtu_size - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqWidth))*XRAN_PAYLOAD_1_RB_SZ(iqWidth); print_dbg("frag_size %d\n",frag_size); + if(isUdCompHdr){ + in_hdr_comp = rte_pktmbuf_mtod(pkt_in, struct eth_xran_up_pkt_hdr_comp*); + in_hdr_xran_comp = &in_hdr_comp->xran_hdr; + if (unlikely(frag_size * nb_pkts_out < + (uint16_t)(pkt_in->pkt_len - sizeof (struct xran_up_pkt_hdr_comp)))){ + print_err("-EINVAL\n"); + return -EINVAL; + } + }else { in_hdr = rte_pktmbuf_mtod(pkt_in, struct eth_xran_up_pkt_hdr *); - in_hdr_xran = &in_hdr->xran_hdr; - /* Check that pkts_out is big enough to hold all fragments */ if (unlikely(frag_size * nb_pkts_out < (uint16_t)(pkt_in->pkt_len - sizeof (struct xran_up_pkt_hdr)))){ print_err("-EINVAL\n"); return -EINVAL; } + } in_seg = pkt_in; + if(isUdCompHdr){ + in_seg_data_pos = sizeof(struct eth_xran_up_pkt_hdr_comp); + }else{ in_seg_data_pos = sizeof(struct eth_xran_up_pkt_hdr); + } out_pkt_pos = 0; fragment_offset = 0; @@ -148,6 +196,7 @@ xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ struct rte_mbuf *out_pkt = NULL, *out_seg_prev = NULL; uint32_t more_out_segs; struct xran_up_pkt_hdr *out_hdr; + struct xran_up_pkt_hdr_comp *out_hdr_comp; /* Allocate direct buffer */ out_pkt = rte_pktmbuf_alloc(pool_direct); @@ -162,9 +211,16 @@ xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ /* Reserve space for the XRAN header that will be built later */ //out_pkt->data_len = sizeof(struct xran_up_pkt_hdr); //out_pkt->pkt_len = sizeof(struct xran_up_pkt_hdr); + if(isUdCompHdr){ + if(rte_pktmbuf_append(out_pkt, sizeof(struct xran_up_pkt_hdr_comp)) ==NULL){ + rte_panic("sizeof(struct xran_up_pkt_hdr)"); + } + }else{ if(rte_pktmbuf_append(out_pkt, sizeof(struct xran_up_pkt_hdr)) ==NULL){ rte_panic("sizeof(struct xran_up_pkt_hdr)"); } + } + frag_bytes_remaining = frag_size; out_seg_prev = out_pkt; @@ -233,14 +289,25 @@ xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ /* Build the XRAN header */ print_dbg("Build the XRAN header\n"); - out_hdr = rte_pktmbuf_mtod(out_pkt, struct xran_up_pkt_hdr *); + + if(isUdCompHdr){ + out_hdr_comp = rte_pktmbuf_mtod(out_pkt, struct xran_up_pkt_hdr_comp*); + __fill_xranhdr_frag_comp(out_hdr_comp, in_hdr_xran_comp, + (uint16_t)out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr_comp), + fragment_offset, nRBStart, nRBSize, more_in_segs, seqid, iqWidth); + + fragment_offset = (uint16_t)(fragment_offset + + out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr_comp)); + } else { + out_hdr = rte_pktmbuf_mtod(out_pkt, struct xran_up_pkt_hdr *); __fill_xranhdr_frag(out_hdr, in_hdr_xran, (uint16_t)out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr), - fragment_offset, sectinfo, more_in_segs, seqid); + fragment_offset, nRBStart, nRBSize, more_in_segs, seqid, iqWidth); fragment_offset = (uint16_t)(fragment_offset + out_pkt->pkt_len - sizeof(struct xran_up_pkt_hdr)); + } //out_pkt->l3_len = sizeof(struct xran_up_pkt_hdr); diff --git a/fhi_lib/lib/src/xran_app_frag.h b/fhi_lib/lib/src/xran_app_frag.h index 399f630..5f5e0e8 100644 --- a/fhi_lib/lib/src/xran_app_frag.h +++ b/fhi_lib/lib/src/xran_app_frag.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -44,14 +44,18 @@ extern "C" { #include "xran_fh_o_du.h" #include "xran_cp_api.h" -int32_t xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ +int32_t +xran_app_fragment_packet(struct rte_mbuf *pkt_in, /* eth hdr is prepended */ struct rte_mbuf **pkts_out, uint16_t nb_pkts_out, uint16_t mtu_size, struct rte_mempool *pool_direct, struct rte_mempool *pool_indirect, - struct xran_section_info *sectinfo, - uint8_t *seqid); + int16_t nRBStart, /**< start RB of RB allocation */ + int16_t nRBSize, /**< number of RBs used */ + uint8_t *seqid, + uint8_t iqWidth, + uint8_t isUdCompHdr); #ifdef __cplusplus } diff --git a/fhi_lib/lib/src/xran_bfp_byte_packing_utils.hpp b/fhi_lib/lib/src/xran_bfp_byte_packing_utils.hpp new file mode 100644 index 0000000..c32cd0a --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_byte_packing_utils.hpp @@ -0,0 +1,714 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP byte packing utilities functions + * + * @file xran_bfp_byte_packing_utils.hpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#pragma once +#include + +namespace BlockFloatCompander +{ + /// Define function signatures for byte packing functions + typedef __m512i(*PackFunction)(const __m512i); + typedef __m512i(*UnpackFunction)(const uint8_t*); + typedef __m256i(*UnpackFunction256)(const uint8_t*); + + /// Pack compressed 9 bit data in network byte order + inline __m512i + networkBytePack9b(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0C0D080904050001, + 0x0000000000000000, 0x0C0D080904050001, + 0x0000000000000000, 0x0C0D080904050001, + 0x0000000000000000, 0x0C0D080904050001); + constexpr uint64_t k_byteMask1 = 0x00FF00FF00FF00FF; + const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000000000E, 0x0F0A0B0607020300, + 0x000000000000000E, 0x0F0A0B0607020300, + 0x000000000000000E, 0x0F0A0B0607020300, + 0x000000000000000E, 0x0F0A0B0607020300); + constexpr uint64_t k_byteMask2 = 0x01FE01FE01FE01FE; + const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000000000FF, 0x01FC07F01FC07F00, + 0x00000000000000FF, 0x01FC07F01FC07F00, + 0x00000000000000FF, 0x01FC07F01FC07F00, + 0x00000000000000FF, 0x01FC07F01FC07F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 10 bit data in network byte order + inline __m512i + networkBytePack10b(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x000000000000000C, 0x0D08090004050001, + 0x000000000000000C, 0x0D08090004050001, + 0x000000000000000C, 0x0D08090004050001, + 0x000000000000000C, 0x0D08090004050001); + constexpr uint64_t k_byteMask1 = 0x01EF01EF01EF01EF; + const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000E0F, 0x0A0B000607020300, + 0x0000000000000E0F, 0x0A0B000607020300, + 0x0000000000000E0F, 0x0A0B000607020300, + 0x0000000000000E0F, 0x0A0B000607020300); + constexpr uint64_t k_byteMask2 = 0x03DE03DE03DE03DE; + const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x000000000000FF03, 0xF03F00FF03F03F00, + 0x000000000000FF03, 0xF03F00FF03F03F00, + 0x000000000000FF03, 0xF03F00FF03F03F00, + 0x000000000000FF03, 0xF03F00FF03F03F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 12 bit data in network byte order + inline __m512i + networkBytePack12b(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x00000000000C0D00, 0x0809000405000001, + 0x00000000000C0D00, 0x0809000405000001, + 0x00000000000C0D00, 0x0809000405000001, + 0x00000000000C0D00, 0x0809000405000001); + constexpr uint64_t k_byteMask1 = 0x06DB06DB06DB06DB; + const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000E0F000A, 0x0B00060700020300, + 0x000000000E0F000A, 0x0B00060700020300, + 0x000000000E0F000A, 0x0B00060700020300, + 0x000000000E0F000A, 0x0B00060700020300); + constexpr uint64_t k_byteMask2 = 0x0DB60DB60DB60DB6; + const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, + 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, + 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, + 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Unpack compressed 9 bit data in network byte order + inline __m512i + networkByteUnpack9b(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm512_set_epi32(9, 8, 7, 6, 7, 6, 5, 4, + 5, 4, 3, 2, 3, 2, 1, 0); + const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, there is + /// a different shuffle offset in each lane + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0607050604050304, + 0x090A080907080607, 0x0506040503040203, + 0x0809070806070506, 0x0405030402030102, + 0x0708060705060405, 0x0304020301020001); + const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000); + const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFF80); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 10 bit data in network byte order + inline __m512i + networkByteUnpack10b(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm512_set_epi32(10, 9, 8, 7, 8, 7, 6, 5, + 5, 4, 3, 2, 3, 2, 1, 0); + const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, lanes + /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0506040503040203, + 0x0809070806070506, 0x0304020301020001, + 0x0A0B090A08090708, 0x0506040503040203, + 0x0809070806070506, 0x0304020301020001); + const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000); + const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFFC0); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 12 bit data in network byte order + inline __m512i + networkByteUnpack12b(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm512_set_epi32(12, 11, 10, 9, 9, 8, 7, 6, + 6, 5, 4, 3, 3, 2, 1, 0); + const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A07080607, 0x0405030401020001, + 0x0A0B090A07080607, 0x0405030401020001, + 0x0A0B090A07080607, 0x0405030401020001, + 0x0A0B090A07080607, 0x0405030401020001); + const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000); + const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFFF0); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 9 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack9b256(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0); + const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, there is + /// a different shuffle offset in each lane + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0809070806070506, 0x0405030402030102, + 0x0708060705060405, 0x0304020301020001); + const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000); + const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFF80); + return _mm256_and_si256(inSetSign, k_expMask); + } + + + /// Unpack compressed 10 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack10b256(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0); + const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, lanes + /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A08090708, 0x0506040503040203, + 0x0809070806070506, 0x0304020301020001); + const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000); + const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFFC0); + return _mm256_and_si256(inSetSign, k_expMask); + } + + + /// Unpack compressed 12 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack12b256(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + const auto k_expPerm = _mm256_set_epi32(6, 5, 4, 3, 3, 2, 1, 0); + const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A07080607, 0x0405030401020001, + 0x0A0B090A07080607, 0x0405030401020001); + const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000); + const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFFF0); + return _mm256_and_si256(inSetSign, k_expMask); + } + + + + /// Pack compressed 9 bit data in network byte order + inline __m512i + networkBytePack9bSnc(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 permute of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0x00000000003C3D38, + 0x3934353031002C2D, 0x282924252021001C, + 0x1D18191415101100, 0x0C0D080904050001); + constexpr uint64_t k_byteMask1 = 0x00000007FBFDFEFF; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 permute of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0x000000003E3F3A3B, + 0x36373233002E2F2A, 0x2B26272223001E1F, + 0x1A1B16171213000E, 0x0F0A0B0607020300); + constexpr uint64_t k_byteMask2 = 0x0000000FF7FBFDFE; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0x00000000FF01FC07, + 0xF01FC07F00FF01FC, 0x07F01FC07F00FF01, + 0xFC07F01FC07F00FF, 0x01FC07F01FC07F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 10 bit data in network byte order + inline __m512i + networkBytePack10bSnc(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0x003C3D3839003435, + 0x3031002C2D282900, 0x24252021001C1D18, + 0x190014151011000C, 0x0D08090004050001); + constexpr uint64_t k_byteMask1 = 0x0000007BDEF7BDEF; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0x3E3F3A3B00363732, + 0x33002E2F2A2B0026, 0x272223001E1F1A1B, + 0x0016171213000E0F, 0x0A0B000607020300); + constexpr uint64_t k_byteMask2 = 0x000000F7BDEF7BDE; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x0000000000000000, 0xFF03F03F00FF03F0, + 0x3F00FF03F03F00FF, 0x03F03F00FF03F03F, + 0x00FF03F03F00FF03, 0xF03F00FF03F03F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + inline __m512i + networkBytePack12bSnc(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x003C3D0038390034, 0x35003031002C2D00, + 0x2829002425002021, 0x001C1D0018190014, + 0x15001011000C0D00, 0x0809000405000001); + constexpr uint64_t k_byteMask1 = 0x00006DB6DB6DB6DB; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0x3E3F003A3B003637, 0x003233002E2F002A, + 0x2B00262700222300, 0x1E1F001A1B001617, + 0x001213000E0F000A, 0x0B00060700020300); + constexpr uint64_t k_byteMask2 = 0x0000DB6DB6DB6DB6; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0x0000000000000000, + 0xFF0F00FF0F00FF0F, 0x00FF0F00FF0F00FF, + 0x0F00FF0F00FF0F00, 0xFF0F00FF0F00FF0F, + 0x00FF0F00FF0F00FF, 0x0F00FF0F00FF0F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 9 bit data in network byte order + /// This version is specific to the c-plane 8 antenna case, where 2 compression blocks + /// are handled in one register. + inline __m512i + networkBytePack9bSncB(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007, + 0x0000000100020003, 0x0004000500060007); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 permute of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x000000000000003C, + 0x3D38393435303100, 0x2C2D282924252021, + 0x0000000000000000, 0x000000000000001C, + 0x1D18191415101100, 0x0C0D080904050001); + constexpr uint64_t k_byteMask1 = 0x0001FEFF0001FEFF; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 permute of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000003E3F, + 0x3A3B36373233002E, 0x2F2A2B2627222300, + 0x0000000000000000, 0x0000000000001E1F, + 0x1A1B16171213000E, 0x0F0A0B0607020300); + constexpr uint64_t k_byteMask2 = 0x0003FDFE0003FDFE; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0x000000000000FF01, + 0xFC07F01FC07F00FF, 0x01FC07F01FC07F00, + 0x0000000000000000, 0x000000000000FF01, + 0xFC07F01FC07F00FF, 0x01FC07F01FC07F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 10 bit data in network byte order + /// This version is specific to the c-plane 8 antenna case, where 2 compression blocks + /// are handled in one register. + inline __m512i + networkBytePack10bSncB(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x00000000003C3D38, + 0x390034353031002C, 0x2D28290024252021, + 0x0000000000000000, 0x00000000001C1D18, + 0x190014151011000C, 0x0D08090004050001); + constexpr uint64_t k_byteMask1 = 0x0007BDEF0007BDEF; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x000000003E3F3A3B, + 0x0036373233002E2F, 0x2A2B002627222300, + 0x0000000000000000, 0x000000001E1F1A1B, + 0x0016171213000E0F, 0x0A0B000607020300); + constexpr uint64_t k_byteMask2 = 0x000F7BDE000F7BDE; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0x00000000FF03F03F, + 0x00FF03F03F00FF03, 0xF03F00FF03F03F00, + 0x0000000000000000, 0x00000000FF03F03F, + 0x00FF03F03F00FF03, 0xF03F00FF03F03F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + /// Pack compressed 12 bit data in network byte order + /// This version is specific to the c-plane 8 antenna case, where 2 compression blocks + /// are handled in one register. + inline __m512i + networkBytePack12bSncB(const __m512i compData) + { + /// Logical shift left to align network order byte parts + const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004, + 0x0000000400000004, 0x0000000400000004); + const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); + + /// First epi8 shuffle of even indexed samples + const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x003C3D0038390034, + 0x35003031002C2D00, 0x2829002425002021, + 0x0000000000000000, 0x001C1D0018190014, + 0x15001011000C0D00, 0x0809000405000001); + constexpr uint64_t k_byteMask1 = 0x006DB6DB006DB6DB; + const auto compDataShuff1 = _mm512_maskz_permutexvar_epi8(k_byteMask1, k_byteShuffleMask1, compDataPacked); + + /// Second epi8 shuffle of odd indexed samples + const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000000, 0x3E3F003A3B003637, + 0x003233002E2F002A, 0x2B00262700222300, + 0x0000000000000000, 0x1E1F001A1B001617, + 0x001213000E0F000A, 0x0B00060700020300); + constexpr uint64_t k_byteMask2 = 0x00DB6DB600DB6DB6; + auto compDataShuff2 = _mm512_maskz_permutexvar_epi8(k_byteMask2, k_byteShuffleMask2, compDataPacked); + + /// Ternary blend of the two shuffled results + const __m512i k_ternLogSelect = _mm512_set_epi64(0x0000000000000000, 0xFF0F00FF0F00FF0F, + 0x00FF0F00FF0F00FF, 0x0F00FF0F00FF0F00, + 0x0000000000000000, 0xFF0F00FF0F00FF0F, + 0x00FF0F00FF0F00FF, 0x0F00FF0F00FF0F00); + return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); + } + + + + /// Unpack compressed 9 bit data in network byte order + inline __m512i + networkByteUnpack9bSnc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, there is + /// a different shuffle offset in each lane + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x2223212220211F20, 0x1E1F1D1E1C1D1B1C, + 0x191A181917181617, 0x1516141513141213, + 0x10110F100E0F0D0E, 0x0C0D0B0C0A0B090A, + 0x0708060705060405, 0x0304020301020001); + constexpr uint64_t k_byteMask = 0xFFFFFFFFFFFFFFFF; + const auto inDataContig = _mm512_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000); + const auto inSetSign = _mm512_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFF80); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 10 bit data in network byte order + inline __m512i + networkByteUnpack10bSnc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, lanes + /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x2627252624252324, 0x212220211F201E1F, + 0x1C1D1B1C1A1B191A, 0x1718161715161415, + 0x1213111210110F10, 0x0D0E0C0D0B0C0A0B, + 0x0809070806070506, 0x0304020301020001); + constexpr uint64_t k_byteMask = 0xFFFFFFFFFFFFFFFF; + const auto inDataContig = _mm512_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000); + const auto inSetSign = _mm512_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFFC0); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 12 bit data in network byte order + inline __m512i + networkByteUnpack12bSnc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m512i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset + const __m512i k_byteShuffleMask = _mm512_set_epi64(0x2E2F2D2E2B2C2A2B, 0x2829272825262425, + 0x222321221F201E1F, 0x1C1D1B1C191A1819, + 0x1617151613141213, 0x10110F100D0E0C0D, + 0x0A0B090A07080607, 0x0405030401020001); + constexpr uint64_t k_byteMask = 0xFFFFFFFFFFFFFFFF; + const auto inDataContig = _mm512_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m512i k_slBits = _mm512_set_epi64(0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000); + const auto inSetSign = _mm512_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m512i k_expMask = _mm512_set1_epi16(0xFFF0); + return _mm512_and_epi64(inSetSign, k_expMask); + } + + + /// Unpack compressed 9 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack9b256Snc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, there is + /// a different shuffle offset in each lane + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x10110F100E0F0D0E, 0x0C0D0B0C0A0B090A, + 0x0708060705060405, 0x0304020301020001); + constexpr uint32_t k_byteMask = 0xFFFFFFFF; + const auto inDataContig = _mm256_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0007000600050004, 0x0003000200010000, + 0x0007000600050004, 0x0003000200010000); + const auto inSetSign = _mm256_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFF80); + return _mm256_and_si256(inSetSign, k_expMask); + } + + + /// Unpack compressed 10 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack10b256Snc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// Due to previous permute to get chunks of bytes into each lane, lanes + /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x1213111210110F10, 0x0D0E0C0D0B0C0A0B, + 0x0809070806070506, 0x0304020301020001); + constexpr uint32_t k_byteMask = 0xFFFFFFFF; + const auto inDataContig = _mm256_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0006000400020000, 0x0006000400020000, + 0x0006000400020000, 0x0006000400020000); + const auto inSetSign = _mm256_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFFC0); + return _mm256_and_si256(inSetSign, k_expMask); + } + + + /// Unpack compressed 12 bit data in network byte order + /// This unpacking function is for 256b registers + inline __m256i + networkByteUnpack12b256Snc(const uint8_t* inData) + { + /// Align chunks of compressed bytes into lanes to allow for expansion + const __m256i* rawDataIn = reinterpret_cast(inData); + + /// Byte shuffle to get all bits for each sample into 16b chunks + /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset + const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x1617151613141213, 0x10110F100D0E0C0D, + 0x0A0B090A07080607, 0x0405030401020001); + constexpr uint32_t k_byteMask = 0xFFFFFFFF; + const auto inDataContig = _mm256_maskz_permutexvar_epi8(k_byteMask, k_byteShuffleMask, *rawDataIn); + + /// Logical shift left to set sign bit + const __m256i k_slBits = _mm256_set_epi64x(0x0004000000040000, 0x0004000000040000, + 0x0004000000040000, 0x0004000000040000); + const auto inSetSign = _mm256_sllv_epi16(inDataContig, k_slBits); + + /// Mask to zero unwanted bits + const __m256i k_expMask = _mm256_set1_epi16(0xFFF0); + return _mm256_and_si256(inSetSign, k_expMask); + } + +} diff --git a/fhi_lib/lib/src/xran_bfp_cplane16.cpp b/fhi_lib/lib/src/xran_bfp_cplane16.cpp index 4f668ae..d678d4a 100644 --- a/fhi_lib/lib/src/xran_bfp_cplane16.cpp +++ b/fhi_lib/lib/src/xran_bfp_cplane16.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -26,6 +26,7 @@ #include "xran_compression.hpp" #include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" #include #include #include diff --git a/fhi_lib/lib/src/xran_bfp_cplane16_snc.cpp b/fhi_lib/lib/src/xran_bfp_cplane16_snc.cpp new file mode 100644 index 0000000..02fb9f7 --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_cplane16_snc.cpp @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression for C-plane with 16T16R + * + * @file xran_bfp_cplane16.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include +#include +#include + + +namespace BFP_CPlane_16_SNC +{ + /// Namespace constants + const int k_numDataElements = 32; /// 16 IQ pairs + + inline int + maxAbsOneBlock(const __m512i* inData) + { + /// Compute abs of input data + const auto thisRegAbs = _mm512_abs_epi16(*inData); + /// Horizontal max across register + return BlockFloatCompander::horizontalMax1x32(thisRegAbs); + } + + /// Compute exponent value for a set of 16 RB from the maximum absolute value. + inline __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for a set of 4 RB from the maximum absolute value. + inline __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for 1 RB from the maximum absolute value. + inline uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr); + /// Calculate exponent + const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + return ((uint8_t*)&exps)[0]; + } + + + + /// Apply compression to one compression block + template + inline void + applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, + const int iqWidth, const uint8_t thisExp, const uint64_t rbWriteMask) + { + /// Store exponent first + *outBlockAddr = thisExp; + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*dataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store compressed data + _mm512_mask_storeu_epi8(outBlockAddr + 1, rbWriteMask, compDataBytePacked); + } + + /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks + template + inline void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataInAddr + n, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks + template + inline void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompressionN_1RB(dataInAddr + n, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 1 RB + template + inline void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint64_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompressionN_1RB(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, rbWriteMask); + } + + /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint64_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + } + } + + + + /// Apply 8b compression to 1 compression block. + inline void + applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp) + { + /// Store exponent first + *outBlockAddr = thisExp; + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*dataIn, thisExp); + /// Truncate to 8bit and store + constexpr uint32_t k_writeMask = 0xFFFFFFFF; + _mm256_mask_storeu_epi8(outBlockAddr + 1, k_writeMask, _mm512_cvtepi16_epi8(compData)); + } + + /// Derive and apply 8b compression to 16 compression blocks + inline void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 4 compression blocks + inline void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 1 compression block + inline void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent); + } + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + inline void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + + /// Expand 1 compression block + template + inline void + applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift) + { + const auto thisExpShift = maxExpShift - *expAddr; + /// Unpack network order packed data + const auto inDataUnpacked = networkByteUnpack(expAddr + 1); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift); + /// Write expanded data to output + static constexpr uint8_t k_WriteMask = 0xFF; + _mm512_mask_storeu_epi64(dataOutAddr, k_WriteMask, expandedData); + } + + /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + void + expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerBlock, const int maxExpShift) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift); + } + break; + + case 1: + applyExpansionN_1RB(dataIn.dataCompressed, dataOutAddr, maxExpShift); + break; + } + } + + + /// Apply expansion to 1 compression block + inline void + applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr) + { + const __m256i* rawDataIn = reinterpret_cast(expAddr + 1); + const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn); + const auto expData = _mm512_slli_epi16(compData16, *expAddr); + static constexpr uint8_t k_WriteMask = 0xFF; + _mm512_mask_storeu_epi64(dataOutAddr, k_WriteMask, expData); + } + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n); + } + break; + + case 1: + applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr); + break; + } + } +} + + +/// Main kernel function for 16 antenna C-plane compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressCtrlPlane16AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_16_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + + /// Compressed data write mask for each iqWidth option + constexpr uint64_t rbWriteMask9 = 0x0000000FFFFFFFFF; + constexpr uint64_t rbWriteMask10 = 0x000000FFFFFFFFFF; + constexpr uint64_t rbWriteMask12 = 0x0000FFFFFFFFFFFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_16_SNC::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_CPlane_16_SNC::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, rbWriteMask9); + break; + + case 10: + BFP_CPlane_16_SNC::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, rbWriteMask10); + break; + + case 12: + BFP_CPlane_16_SNC::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, rbWriteMask12); + break; + } +} + + +/// Main kernel function for 16 antenna C-plane expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandCtrlPlane16AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_16_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_16_SNC::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_CPlane_16_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift9); + break; + + case 10: + BFP_CPlane_16_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift10); + break; + + case 12: + BFP_CPlane_16_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift12); + break; + } +} diff --git a/fhi_lib/lib/src/xran_bfp_cplane32.cpp b/fhi_lib/lib/src/xran_bfp_cplane32.cpp index e091620..8d63e8c 100644 --- a/fhi_lib/lib/src/xran_bfp_cplane32.cpp +++ b/fhi_lib/lib/src/xran_bfp_cplane32.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -26,6 +26,7 @@ #include "xran_compression.hpp" #include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" #include #include #include diff --git a/fhi_lib/lib/src/xran_bfp_cplane32_snc.cpp b/fhi_lib/lib/src/xran_bfp_cplane32_snc.cpp new file mode 100644 index 0000000..76b5eee --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_cplane32_snc.cpp @@ -0,0 +1,432 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression for C-plane with 32T32R + * + * @file xran_bfp_cplane32.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include +#include +#include + + +namespace BFP_CPlane_32_SNC +{ + /// Namespace constants + const int k_numDataElements = 64; /// 16 IQ pairs + const int k_numRegsPerBlock = 2; /// Number of AVX512 registers per compression block (input) + + inline int + maxAbsOneBlock(const __m512i* inData) + { + /// Vertical maxAbs on all registers + __m512i maxAbsReg = __m512i(); +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto thisRegAbs = _mm512_abs_epi16(inData[n]); + maxAbsReg = _mm512_max_epi16(thisRegAbs, maxAbsReg); + } + /// Horizontal max across remaining register + return BlockFloatCompander::horizontalMax1x32(maxAbsReg); + } + + /// Compute exponent value for a set of 16 RB from the maximum absolute value + inline __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for a set of 4 RB from the maximum absolute value + inline __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for 1 RB from the maximum absolute value + inline uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr); + /// Calculate exponent + const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + return ((uint8_t*)&exps)[0]; + } + + + + /// Apply compression to one compression block + template + inline void + applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, + const int iqWidth, const uint8_t thisExp, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + /// Store exponent first + *outBlockAddr = thisExp; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(dataIn[n], thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store compressed data + _mm512_mask_storeu_epi8(outBlockAddr + 1 + n * totNumBytesPerReg, rbWriteMask, compDataBytePacked); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks + template + inline void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks + template + inline void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompressionN_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 1 RB + template + inline void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompressionN_1RB(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, totNumBytesPerReg, rbWriteMask); + } + + /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + } + } + + + + /// Apply 8b compression to 1 compression block. + inline void + applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp) + { + /// Store exponent first + *outBlockAddr = thisExp; + constexpr uint32_t k_writeMask = 0xFFFFFFFF; + __m256i* regOutAddr = reinterpret_cast<__m256i*>(outBlockAddr + 1); +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(dataIn[n], thisExp); + /// Truncate to 8bit and store + _mm256_mask_storeu_epi8(regOutAddr + n, k_writeMask, _mm512_cvtepi16_epi8(compData)); + } + } + + /// Derive and apply 8b compression to 16 compression blocks + inline void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 4 compression blocks + inline void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 1 compression block + inline void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent); + } + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + inline void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + + /// Expand 1 compression block + template + inline void + applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift, const int totNumBytesPerReg) + { + static constexpr uint8_t k_WriteMask = 0xFF; + const auto thisExpShift = maxExpShift - *expAddr; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto thisInRegAddr = expAddr + 1 + n * totNumBytesPerReg; + /// Unpack network order packed data + const auto inDataUnpacked = networkByteUnpack(thisInRegAddr); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift); + /// Write expanded data to output + _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expandedData); + } + } + + /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + void + expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerBlock, const int totNumBytesPerReg, const int maxExpShift) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg); + } + break; + + case 1: + applyExpansionN_1RB(dataIn.dataCompressed, dataOutAddr, maxExpShift, totNumBytesPerReg); + break; + } + } + + + /// Apply expansion to 1 compression block + inline void + applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr) + { + const __m256i* rawDataIn = reinterpret_cast(expAddr + 1); + static constexpr uint8_t k_WriteMask = 0xFF; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto compData16 = _mm512_cvtepi8_epi16(rawDataIn[n]); + const auto expData = _mm512_slli_epi16(compData16, *expAddr); + _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expData); + } + } + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock); + } + break; + + case 1: + applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr); + break; + } + } +} + + +/// Main kernel function for 32 antenna C-plane compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressCtrlPlane32AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_32_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8 + const auto totNumBytesPerReg = dataIn.iqWidth << 2; + + /// Compressed data write mask for each iqWidth option + constexpr uint64_t rbWriteMask9 = 0x0000000FFFFFFFFF; + constexpr uint64_t rbWriteMask10 = 0x000000FFFFFFFFFF; + constexpr uint64_t rbWriteMask12 = 0x0000FFFFFFFFFFFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_32_SNC::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_CPlane_32_SNC::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask9); + break; + + case 10: + BFP_CPlane_32_SNC::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask10); + break; + + case 12: + BFP_CPlane_32_SNC::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask12); + break; + } +} + + +/// Main kernel function for 32 antenna C-plane expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandCtrlPlane32AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_32_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8 + const auto totNumBytesPerReg = dataIn.iqWidth << 2; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_32_SNC::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_CPlane_32_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift9); + break; + + case 10: + BFP_CPlane_32_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift10); + break; + + case 12: + BFP_CPlane_32_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift12); + break; + } +} diff --git a/fhi_lib/lib/src/xran_bfp_cplane64.cpp b/fhi_lib/lib/src/xran_bfp_cplane64.cpp index 1238494..3139516 100644 --- a/fhi_lib/lib/src/xran_bfp_cplane64.cpp +++ b/fhi_lib/lib/src/xran_bfp_cplane64.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -26,6 +26,7 @@ #include "xran_compression.hpp" #include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" #include #include #include diff --git a/fhi_lib/lib/src/xran_bfp_cplane64_snc.cpp b/fhi_lib/lib/src/xran_bfp_cplane64_snc.cpp new file mode 100644 index 0000000..9279ea0 --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_cplane64_snc.cpp @@ -0,0 +1,431 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression for C-plane with 64T64R + * + * @file xran_bfp_cplane64.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include +#include +#include + + +namespace BFP_CPlane_64_SNC +{ + /// Namespace constants + const int k_numDataElements = 128; /// 16 IQ pairs + const int k_numRegsPerBlock = 4; /// Number of AVX512 registers per compression block (input) + + inline int + maxAbsOneBlock(const __m512i* inData) + { + /// Vertical maxAbs on all registers + __m512i maxAbsReg = __m512i(); +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto thisRegAbs = _mm512_abs_epi16(inData[n]); + maxAbsReg = _mm512_max_epi16(thisRegAbs, maxAbsReg); + } + /// Horizontal max across remaining register + return BlockFloatCompander::horizontalMax1x32(maxAbsReg); + } + + /// Compute exponent value for a set of 16 RB from the maximum absolute value + inline __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for a set of 4 RB from the maximum absolute value + inline __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + ((uint32_t*)&maxAbs)[n] = maxAbsOneBlock(dataInAddr + n * k_numRegsPerBlock); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for 1 RB from the maximum absolute value + inline uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + ((uint32_t*)&maxAbs)[0] = maxAbsOneBlock(dataInAddr); + /// Calculate exponent + const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + return ((uint8_t*)&exps)[0]; + } + + + + /// Apply compression to one compression block + template + inline void + applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, + const int iqWidth, const uint8_t thisExp, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + /// Store exponent first + *outBlockAddr = thisExp; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(dataIn[n], thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store compressed data + _mm512_mask_storeu_epi8(outBlockAddr + 1 + n * totNumBytesPerReg, rbWriteMask, compDataBytePacked); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks + template + inline void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks + template + inline void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompressionN_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents)[n * 4], totNumBytesPerReg, rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 1 RB + template + inline void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompressionN_1RB(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, totNumBytesPerReg, rbWriteMask); + } + + /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const int totNumBytesPerReg, const uint64_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask); + break; + } + } + + + + /// Apply 8b compression to 1 compression block. + inline void + applyCompression8_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp) + { + /// Store exponent first + *outBlockAddr = thisExp; + constexpr uint32_t k_writeMask = 0xFFFFFFFF; + __m256i* regOutAddr = reinterpret_cast<__m256i*>(outBlockAddr + 1); +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(dataIn[n], thisExp); + /// Truncate to 8bit and store + _mm256_mask_storeu_epi8(regOutAddr + n, k_writeMask, _mm512_cvtepi16_epi8(compData)); + } + } + + /// Derive and apply 8b compression to 16 compression blocks + inline void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 4 compression blocks + inline void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataInAddr + n * k_numRegsPerBlock, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 1 compression block + inline void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent); + } + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + inline void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + + /// Expand 1 compression block + template + inline void + applyExpansionN_1RB(const uint8_t* expAddr, __m512i* dataOutAddr, const int maxExpShift, const int totNumBytesPerReg) + { + static constexpr uint8_t k_WriteMask = 0xFF; + const auto thisExpShift = maxExpShift - *expAddr; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto thisInRegAddr = expAddr + 1 + n * totNumBytesPerReg; + /// Unpack network order packed data + const auto inDataUnpacked = networkByteUnpack(thisInRegAddr); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto expandedData = _mm512_srai_epi16(inDataUnpacked, thisExpShift); + /// Write expanded data to output + _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expandedData); + } + } + + /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + void expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerBlock, const int totNumBytesPerReg, const int maxExpShift) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n * k_numRegsPerBlock, maxExpShift, totNumBytesPerReg); + } + break; + + case 1: + applyExpansionN_1RB(dataIn.dataCompressed, dataOutAddr, maxExpShift, totNumBytesPerReg); + break; + } + } + + + /// Apply expansion to 1 compression block + inline void + applyExpansion8_1RB(const uint8_t* expAddr, __m512i* dataOutAddr) + { + const __m256i* rawDataIn = reinterpret_cast(expAddr + 1); + static constexpr uint8_t k_WriteMask = 0xFF; +#pragma unroll(k_numRegsPerBlock) + for (int n = 0; n < k_numRegsPerBlock; ++n) + { + const auto compData16 = _mm512_cvtepi8_epi16(rawDataIn[n]); + const auto expData = _mm512_slli_epi16(compData16, *expAddr); + _mm512_mask_storeu_epi64(dataOutAddr + n, k_WriteMask, expData); + } + } + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + __m512i* dataOutAddr = reinterpret_cast<__m512i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n * k_numRegsPerBlock); + } + break; + + case 1: + applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr); + break; + } + } +} + + +/// Main kernel function for 64 antenna C-plane compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressCtrlPlane64AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_64_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8 + const auto totNumBytesPerReg = dataIn.iqWidth << 2; + + /// Compressed data write mask for each iqWidth option + constexpr uint64_t rbWriteMask9 = 0x0000000FFFFFFFFF; + constexpr uint64_t rbWriteMask10 = 0x000000FFFFFFFFFF; + constexpr uint64_t rbWriteMask12 = 0x0000FFFFFFFFFFFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_64_SNC::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_CPlane_64_SNC::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask9); + break; + + case 10: + BFP_CPlane_64_SNC::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask10); + break; + + case 12: + BFP_CPlane_64_SNC::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, totNumBytesPerReg, rbWriteMask12); + break; + } +} + + +/// Main kernel function for 64 antenna C-plane expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandCtrlPlane64AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_64_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + /// Total number of compressed bytes to handle per register is 32 * iqWidth / 8 + const auto totNumBytesPerReg = dataIn.iqWidth << 2; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_64_SNC::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_CPlane_64_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift9); + break; + + case 10: + BFP_CPlane_64_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift10); + break; + + case 12: + BFP_CPlane_64_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, totNumBytesPerReg, k_maxExpShift12); + break; + } +} diff --git a/fhi_lib/lib/src/xran_bfp_cplane8.cpp b/fhi_lib/lib/src/xran_bfp_cplane8.cpp index f11abe0..20672f6 100644 --- a/fhi_lib/lib/src/xran_bfp_cplane8.cpp +++ b/fhi_lib/lib/src/xran_bfp_cplane8.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -26,6 +26,7 @@ #include "xran_compression.hpp" #include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" #include #include #include diff --git a/fhi_lib/lib/src/xran_bfp_cplane8_snc.cpp b/fhi_lib/lib/src/xran_bfp_cplane8_snc.cpp new file mode 100644 index 0000000..ebc2ab1 --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_cplane8_snc.cpp @@ -0,0 +1,452 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression for C-plane with 8T8R + * + * @file xran_bfp_cplane8.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include +#include +#include + + +namespace BFP_CPlane_8_SNC +{ + /// Namespace constants + const int k_numDataElements = 16; /// 16 IQ pairs + + inline __m512i + maxAbsOneReg(const __m512i maxAbs, const __m512i* inData, const int pairNum) + { + /// Compute abs of input data + const auto thisRegAbs = _mm512_abs_epi16(*inData); + /// Swap each IQ pair in each lane (via 32b rotation) and compute max of + /// each pair. + const auto maxRot16 = _mm512_rol_epi32(thisRegAbs, BlockFloatCompander::k_numBitsIQ); + const auto maxAbsIQ = _mm512_max_epi16(thisRegAbs, maxRot16); + /// Convert to 32b values + const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ); + /// Swap 32b in each 64b chunk via rotation and compute 32b max + /// Results in blocks of 64b with 4 repeated 16b max values + const auto maxRot32 = _mm512_rol_epi64(maxAbsIQ32, BlockFloatCompander::k_numBitsIQPair); + const auto maxAbs32 = _mm512_max_epi32(maxAbsIQ32, maxRot32); + /// First 64b permute and max + /// Results in blocks of 128b with 8 repeated 16b max values + constexpr uint8_t k_perm64A = 0xB1; + const auto maxPerm64A = _mm512_permutex_epi64(maxAbs32, k_perm64A); + const auto maxAbs64 = _mm512_max_epi64(maxAbs32, maxPerm64A); + /// Second 64b permute and max + /// Results in blocks of 256b with 16 repeated 16b max values + constexpr uint8_t k_perm64B = 0x4E; + const auto maxPerm64B = _mm512_permutex_epi64(maxAbs64, k_perm64B); + const auto maxAbs128 = _mm512_max_epi64(maxAbs64, maxPerm64B); + /// Now register contains repeated max values for two compression blocks + /// Permute the desired results into maxAbs + const auto k_selectVals = _mm512_set_epi32(24, 16, 24, 16, 24, 16, 24, 16, + 24, 16, 24, 16, 24, 16, 24, 16); + constexpr uint16_t k_2ValsMsk[8] = { 0x0003, 0x000C, 0x0030, 0x00C0, 0x0300, 0x0C00, 0x3000, 0xC000 }; + return _mm512_mask_permutex2var_epi32(maxAbs, k_2ValsMsk[pairNum], k_selectVals, maxAbs128); + } + + /// Compute exponent value for a set of 16 RB from the maximum absolute value. + inline __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(8) + for (int n = 0; n < 8; ++n) + { + maxAbs = maxAbsOneReg(maxAbs, dataInAddr + n, n); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for a set of 4 RB from the maximum absolute value. + inline __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(2) + for (int n = 0; n < 2; ++n) + { + maxAbs = maxAbsOneReg(maxAbs, dataInAddr + n, n); + } + /// Calculate exponent + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + /// Compute exponent value for 1 RB from the maximum absolute value. + inline uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + maxAbs = maxAbsOneReg(maxAbs, dataInAddr, 0); + /// Calculate exponent + const auto exps = BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + return ((uint8_t*)&exps)[0]; + } + + + + /// Apply compression to one compression block + template + inline void + applyCompressionN_1RB(const __m512i* dataIn, uint8_t* outBlockAddr, + const int iqWidth, const uint8_t thisExp, const uint32_t rbWriteMask) + { + /// Store exponents first + *outBlockAddr = thisExp; + /// Apply the exponent shift + /// First Store the two exponent values in one register + const auto compData = _mm512_srai_epi16(*dataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store compressed data + _mm256_mask_storeu_epi8(outBlockAddr + 1, rbWriteMask, _mm512_extracti64x4_epi64(compDataBytePacked, 0)); + } + + /// Apply compression to two compression blocks + template + inline void + applyCompressionN_2RB(const __m512i* dataIn, uint8_t* outBlockAddr, + const int totNumBytesPerBlock, const int iqWidth, const uint8_t* theseExps, const uint32_t rbWriteMask) + { + /// Store exponents first + *outBlockAddr = theseExps[0]; + *(outBlockAddr + totNumBytesPerBlock) = theseExps[4]; + /// Apply the exponent shift + /// First Store the two exponent values in one register + __m512i thisExp = __m512i(); + constexpr uint32_t k_firstExpMask = 0x0000FFFF; + thisExp = _mm512_mask_set1_epi16(thisExp, k_firstExpMask, theseExps[0]); + constexpr uint32_t k_secondExpMask = 0xFFFF0000; + thisExp = _mm512_mask_set1_epi16(thisExp, k_secondExpMask, theseExps[4]); + const auto compData = _mm512_srav_epi16(*dataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Output of network byte packing has each compression block packed in each half register + /// Store compressed data + _mm256_mask_storeu_epi8(outBlockAddr + 1, rbWriteMask, _mm512_extracti64x4_epi64(compDataBytePacked, 0)); + _mm256_mask_storeu_epi8(outBlockAddr + totNumBytesPerBlock + 1, rbWriteMask, _mm512_extracti64x4_epi64(compDataBytePacked, 1)); + } + + /// Derive and apply 9, 10, or 12bit compression to 16 compression blocks + template + inline void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint32_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(8) + for (int n = 0; n < 8; ++n) + { + applyCompressionN_2RB(dataInAddr + n, dataOut->dataCompressed + n * 2 * totNumBytesPerBlock, totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents) + n * 8, rbWriteMask); + } + } + + /// Derive and apply 9, 10, or 12bit compression to 4 compression blocks + template + inline void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint32_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(2) + for (int n = 0; n < 2; ++n) + { + applyCompressionN_2RB(dataInAddr + n, dataOut->dataCompressed + n * 2 * totNumBytesPerBlock, totNumBytesPerBlock, dataIn.iqWidth, ((uint8_t*)&exponents) + n * 8, rbWriteMask);; + } + } + + /// Derive and apply 9, 10, or 12bit compression to 1 RB + template + inline void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint32_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m512i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompressionN_1RB(dataInAddr, dataOut->dataCompressed, dataIn.iqWidth, thisExponent, rbWriteMask); + } + + /// Calls compression function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerBlock, const uint32_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerBlock, rbWriteMask); + break; + } + } + + + + /// Apply 8b compression to 1 compression block. + inline void + applyCompression8_1RB(const __m256i* dataIn, uint8_t* outBlockAddr, const uint8_t thisExp) + { + /// Store exponent first + *outBlockAddr = thisExp; + /// Apply the exponent shift + const auto compData = _mm256_srai_epi16(*dataIn, thisExp); + /// Truncate to 8bit and store + constexpr uint16_t k_writeMask = 0xFFFF; + _mm_mask_storeu_epi8(outBlockAddr + 1, k_writeMask, _mm256_cvtepi16_epi8(compData)); + } + + /// Derive and apply 8b compression to 16 compression blocks + inline void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); + const __m256i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 4 compression blocks + inline void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); + const __m256i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataInAddr + n, dataOut->dataCompressed + n * (k_numDataElements + 1), ((uint8_t*)&exponents)[n * 4]); + } + } + + /// Derive and apply 8b compression to 1 compression block + inline void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + const __m256i* dataInAddr = reinterpret_cast(dataIn.dataExpanded); + applyCompression8_1RB(dataInAddr, dataOut->dataCompressed, thisExponent); + } + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + inline void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + /// Expand 1 compression block + template + inline void + applyExpansionN_1RB(const uint8_t* expAddr, __m256i* dataOutAddr, const int maxExpShift) + { + const auto thisExpShift = maxExpShift - *expAddr; + /// Unpack network order packed data + const auto inDataUnpacked = networkByteUnpack(expAddr + 1); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto expandedData = _mm256_srai_epi16(inDataUnpacked, thisExpShift); + /// Write expanded data to output + static constexpr uint8_t k_WriteMask = 0x0F; + _mm256_mask_storeu_epi64(dataOutAddr, k_WriteMask, expandedData); + } + + /// Calls expansion function specific to the number of blocks to be executed. For 9, 10, or 12bit iqWidth. + template + void expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerBlock, const int maxExpShift) + { + __m256i* dataOutAddr = reinterpret_cast<__m256i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn.dataCompressed + n * totNumBytesPerBlock, dataOutAddr + n, maxExpShift); + } + break; + + case 1: + applyExpansionN_1RB(dataIn.dataCompressed, dataOutAddr, maxExpShift); + break; + } + } + + + /// Apply expansion to 2 compression block + inline void + applyExpansion8_1RB(const uint8_t* expAddr, __m256i* dataOutAddr) + { + const __m128i* rawDataIn = reinterpret_cast(expAddr + 1); + const auto compData16 = _mm256_cvtepi8_epi16(*rawDataIn); + const auto expData = _mm256_slli_epi16(compData16, *expAddr); + static constexpr uint8_t k_WriteMask = 0x0F; + _mm256_mask_storeu_epi64(dataOutAddr, k_WriteMask, expData); + } + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + __m256i* dataOutAddr = reinterpret_cast<__m256i*>(dataOut->dataExpanded); + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn.dataCompressed + n * (k_numDataElements + 1), dataOutAddr + n); + } + break; + + case 1: + applyExpansion8_1RB(dataIn.dataCompressed, dataOutAddr); + break; + } + } +} + + +/// Main kernel function for 8 antenna C-plane compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressCtrlPlane8AvxSnc(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_8_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + + /// Compressed data write mask for each iqWidth option + /// Compressed data write mask for each iqWidth option + constexpr uint32_t rbWriteMask9 = 0x0003FFFF; + constexpr uint32_t rbWriteMask10 = 0x000FFFFF; + constexpr uint32_t rbWriteMask12 = 0x00FFFFFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_8_SNC::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_CPlane_8_SNC::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerBlock, rbWriteMask9); + break; + + case 10: + BFP_CPlane_8_SNC::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerBlock, rbWriteMask10); + break; + + case 12: + BFP_CPlane_8_SNC::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerBlock, rbWriteMask12); + break; + } +} + + +/// Main kernel function for 8 antenna C-plane expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandCtrlPlane8AvxSnc(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + /// Total number of data bytes per compression block is (iqWidth * numElements / 8) + 1 + const auto totNumBytesPerBlock = ((BFP_CPlane_8_SNC::k_numDataElements * dataIn.iqWidth) >> 3) + 1; + + switch (dataIn.iqWidth) + { + case 8: + BFP_CPlane_8_SNC::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_CPlane_8_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift9); + break; + + case 10: + BFP_CPlane_8_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift10); + break; + + case 12: + BFP_CPlane_8_SNC::expandByAllocN(dataIn, dataOut, totNumBytesPerBlock, k_maxExpShift12); + break; + } +} diff --git a/fhi_lib/lib/src/xran_bfp_ref.cpp b/fhi_lib/lib/src/xran_bfp_ref.cpp index 84a6962..e6d3067 100644 --- a/fhi_lib/lib/src/xran_bfp_ref.cpp +++ b/fhi_lib/lib/src/xran_bfp_ref.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/fhi_lib/lib/src/xran_bfp_uplane.cpp b/fhi_lib/lib/src/xran_bfp_uplane.cpp new file mode 100644 index 0000000..a345df4 --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_uplane.cpp @@ -0,0 +1,435 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression U-plane implementation and interface functions + * + * @file xran_compression.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include "xran_compression.h" +#include +#include +#include + + +namespace BFP_UPlane +{ + /// Namespace constants + const int k_numREReal = 24; /// 12 IQ pairs + + + /// Compute exponent value for a set of 16 RB from the maximum absolute value. + /// Max Abs operates in a loop, executing 4 RB per iteration. The results are + /// packed into the final output register. + __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Max Abs loop operates on 4RB at a time +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + /// Re-order and vertical max abs + auto maxAbsVert = BlockFloatCompander::maxAbsVertical4RB(rawData[3 * n + 0], rawData[3 * n + 1], rawData[3 * n + 2]); + /// Horizontal max abs + auto maxAbsHorz = BlockFloatCompander::horizontalMax4x16(maxAbsVert); + /// Pack these 4 values into maxAbs + maxAbs = BlockFloatCompander::slidePermute(maxAbsHorz, maxAbs, n); + } + /// Calculate exponent + const auto maxAbs32 = BlockFloatCompander::maskUpperWord(maxAbs); + return BlockFloatCompander::expLzCnt(maxAbs32, totShiftBits); + } + + + /// Compute exponent value for a set of 4 RB from the maximum absolute value. + /// Note that we do not need to perform any packing of result as we are only + /// computing 4 RB. The appropriate offset is taken later when extracting the + /// exponent. + __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Re-order and vertical max abs + const auto maxAbsVert = BlockFloatCompander::maxAbsVertical4RB(rawData[0], rawData[1], rawData[2]); + /// Horizontal max abs + const auto maxAbsHorz = BlockFloatCompander::horizontalMax4x16(maxAbsVert); + /// Calculate exponent + const auto maxAbs = BlockFloatCompander::maskUpperWord(maxAbsHorz); + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + + /// Compute exponent value for 1 RB from the maximum absolute value. + /// This works with horizontal max abs only, and needs to include a + /// step to select the final exponent from the 4 lanes. + uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Abs + const auto rawDataAbs = _mm512_abs_epi16(rawData[0]); + /// No need to do a full horizontal max operation here, just do a max IQ step, + /// compute the exponents and then use a reduce max over all exponent values. This + /// is the fastest way to handle a single RB. + const auto rawAbsIQSwap = _mm512_rol_epi32(rawDataAbs, BlockFloatCompander::k_numBitsIQ); + const auto maxAbsIQ = _mm512_max_epi16(rawDataAbs, rawAbsIQSwap); + /// Calculate exponent + const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ); + const auto exps = BlockFloatCompander::expLzCnt(maxAbsIQ32, totShiftBits); + /// At this point we have exponent values for the maximum of each IQ pair. + /// Run a reduce max step to compute the maximum exponent value in the first + /// three lanes - this will give the desired exponent for this RB. + constexpr uint16_t k_expMsk = 0x0FFF; + return (uint8_t)_mm512_mask_reduce_max_epi32(k_expMsk, exps); + } + + + /// Apply compression to 1 RB + template + void + applyCompressionN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr, const uint16_t rbWriteMask) + { + /// Get AVX512 pointer aligned to desired RB + const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store exponent first + dataOut->dataCompressed[thisRBExpAddr] = thisExp; + /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) + /// Use three offset stores to join + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0)); + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + dataIn.iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1)); + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * dataIn.iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2)); + } + + + /// Apply 9, 10, or 12bit compression to 16 RB + template + void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * totNumBytesPerRB, rbWriteMask); + } + } + + + /// Apply 9, 10, or 12bit compression to 4 RB + template + void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * totNumBytesPerRB, rbWriteMask); + } + } + + + /// Apply 9, 10, or 12bit compression to 1 RB + template + void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + applyCompressionN_1RB(dataIn, dataOut, 0, thisExponent, 0, rbWriteMask); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + } + } + + + /// Apply compression to 1 RB + void + applyCompression8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr) + { + /// Get AVX512 pointer aligned to desired RB + const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); + /// Store exponent first + dataOut->dataCompressed[thisRBExpAddr] = thisExp; + /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) + /// Use three offset stores to join + constexpr uint32_t k_rbMask = 0x00FFFFFF; // Write mask for 1RB (24 values) + _mm256_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_rbMask, _mm512_cvtepi16_epi8(compData)); + } + + + /// 8bit RB compression loop for 16 RB + void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * (k_numREReal + 1)); + } + } + + + /// 8bit RB compression loop for 4 RB + void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * (k_numREReal + 1)); + } + } + + + /// 8bit RB compression loop for 4 RB + void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + applyCompression8_1RB(dataIn, dataOut, 0, thisExponent, 0); + } + + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + /// Apply compression to 1 RB + template + void + applyExpansionN_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int expAddr, const int thisRBAddr, const int maxExpShift) + { + /// Unpack network order packed data + const auto dataUnpacked = networkByteUnpack(dataIn.dataCompressed + expAddr + 1); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto dataExpanded = _mm512_srai_epi16(dataUnpacked, maxExpShift - *(dataIn.dataCompressed + expAddr)); + /// Write expanded data to output + static constexpr uint32_t k_WriteMask = 0x00FFFFFF; + _mm512_mask_storeu_epi16(dataOut->dataExpanded + thisRBAddr, k_WriteMask, dataExpanded); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + void + expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerRB, const int maxExpShift) + { + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + } + break; + + case 1: + applyExpansionN_1RB(dataIn, dataOut, 0, 0, maxExpShift); + break; + } + } + + + /// Apply expansion to 1 RB and store + void + applyExpansion8_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int expAddr, const int thisRBAddr) + { + const __m256i* rawDataIn = reinterpret_cast(dataIn.dataCompressed + expAddr + 1); + const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn); + const auto expData = _mm512_slli_epi16(compData16, *(dataIn.dataCompressed + expAddr)); + constexpr uint8_t k_rbMask64 = 0b00111111; // 64b write mask for 1RB (24 int16 values) + _mm512_mask_storeu_epi64(dataOut->dataExpanded + thisRBAddr, k_rbMask64, expData); + } + + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); + } + break; + + case 1: + applyExpansion8_1RB(dataIn, dataOut, 0, 0); + break; + } + } +} + + + +/// Main kernel function for compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of compressed bytes per RB for each iqWidth option + constexpr int totNumBytesPerRB9 = 28; + constexpr int totNumBytesPerRB10 = 31; + constexpr int totNumBytesPerRB12 = 37; + + /// Compressed data write mask for each iqWidth option + constexpr uint16_t rbWriteMask9 = 0x01FF; + constexpr uint16_t rbWriteMask10 = 0x03FF; + constexpr uint16_t rbWriteMask12 = 0x0FFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_UPlane::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerRB9, rbWriteMask9); + break; + + case 10: + BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerRB10, rbWriteMask10); + break; + + case 12: + BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerRB12, rbWriteMask12); + break; + } +} + + + +/// Main kernel function for expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_totNumBytesPerRB9 = 28; + constexpr int k_totNumBytesPerRB10 = 31; + constexpr int k_totNumBytesPerRB12 = 37; + + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + switch (dataIn.iqWidth) + { + case 8: + BFP_UPlane::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB9, k_maxExpShift9); + break; + + case 10: + BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB10, k_maxExpShift10); + break; + + case 12: + BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB12, k_maxExpShift12); + break; + } +} \ No newline at end of file diff --git a/fhi_lib/lib/src/xran_bfp_uplane_9b16rb.cpp b/fhi_lib/lib/src/xran_bfp_uplane_9b16rb.cpp new file mode 100644 index 0000000..c28fc3d --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_uplane_9b16rb.cpp @@ -0,0 +1,164 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression U-plane implementation and interface functions + * + * @file xran_compression.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include "xran_compression.h" +#include +#include +#include +#include +#include + +namespace BFP_UPlane_9b16RB +{ + /// Namespace constants + const int k_numREReal = 24; /// 12 IQ pairs + + + /// Compute exponent value for a set of 16 RB from the maximum absolute value. + /// Max Abs operates in a loop, executing 4 RB per iteration. The results are + /// packed into the final output register. + inline __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Max Abs loop operates on 4RB at a time +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + /// Re-order and vertical max abs + auto maxAbsVert = BlockFloatCompander::maxAbsVertical4RB(rawData[3 * n + 0], rawData[3 * n + 1], rawData[3 * n + 2]); + /// Horizontal max abs + auto maxAbsHorz = BlockFloatCompander::horizontalMax4x16(maxAbsVert); + /// Pack these 4 values into maxAbs + maxAbs = BlockFloatCompander::slidePermute(maxAbsHorz, maxAbs, n); + } + /// Calculate exponent + const auto maxAbs32 = BlockFloatCompander::maskUpperWord(maxAbs); + return BlockFloatCompander::expLzCnt(maxAbs32, totShiftBits); + } + + + /// Apply compression to 1 RB + template + inline void + applyCompressionN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr, const uint16_t rbWriteMask) + { + /// Get AVX512 pointer aligned to desired RB + const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store exponent first + dataOut->dataCompressed[thisRBExpAddr] = thisExp; + /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) + /// Use three offset stores to join + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0)); + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + dataIn.iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1)); + _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * dataIn.iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2)); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * totNumBytesPerRB, rbWriteMask); + } + } + + + /// Apply compression to 1 RB + template + inline void + applyExpansionN_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int expAddr, const int thisRBAddr, const int maxExpShift) + { + /// Unpack network order packed data + const auto dataUnpacked = networkByteUnpack(dataIn.dataCompressed + expAddr + 1); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto dataExpanded = _mm512_srai_epi16(dataUnpacked, maxExpShift - *(dataIn.dataCompressed + expAddr)); + /// Write expanded data to output + static constexpr uint32_t k_WriteMask = 0x00FFFFFF; + _mm512_mask_storeu_epi16(dataOut->dataExpanded + thisRBAddr, k_WriteMask, dataExpanded); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + inline void + expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerRB, const int maxExpShift) + { +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + } + } +} + + + +/// Main kernel function for compression. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressUserPlaneAvx512_9b16RB(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits9 = _mm512_set1_epi32(24); + + /// Total number of compressed bytes per RB for each iqWidth option + constexpr int totNumBytesPerRB9 = 28; + + /// Compressed data write mask for each iqWidth option + constexpr uint16_t rbWriteMask9 = 0x01FF; + + BFP_UPlane_9b16RB::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerRB9, rbWriteMask9); +} + + + +/// Main kernel function for expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandUserPlaneAvx512_9b16RB(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_totNumBytesPerRB9 = 28; + constexpr int k_maxExpShift9 = 7; + BFP_UPlane_9b16RB::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB9, k_maxExpShift9); +} diff --git a/fhi_lib/lib/src/xran_bfp_uplane_snc.cpp b/fhi_lib/lib/src/xran_bfp_uplane_snc.cpp new file mode 100644 index 0000000..8710bc6 --- /dev/null +++ b/fhi_lib/lib/src/xran_bfp_uplane_snc.cpp @@ -0,0 +1,432 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression U-plane implementation and interface functions + * + * @file xran_compression.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include "xran_compression.hpp" +#include "xran_bfp_utils.hpp" +#include "xran_bfp_byte_packing_utils.hpp" +#include "xran_compression.h" +#include +#include +#include + + +namespace BFP_UPlane_SNC +{ + /// Namespace constants + const int k_numREReal = 24; /// 12 IQ pairs + + + /// Compute exponent value for a set of 16 RB from the maximum absolute value. + /// Max Abs operates in a loop, executing 4 RB per iteration. The results are + /// packed into the final output register. + __m512i + computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + __m512i maxAbs = __m512i(); + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Max Abs loop operates on 4RB at a time +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + /// Re-order and vertical max abs + auto maxAbsVert = BlockFloatCompander::maxAbsVertical4RB(rawData[3 * n + 0], rawData[3 * n + 1], rawData[3 * n + 2]); + /// Horizontal max abs + auto maxAbsHorz = BlockFloatCompander::horizontalMax4x16(maxAbsVert); + /// Pack these 4 values into maxAbs + maxAbs = BlockFloatCompander::slidePermute(maxAbsHorz, maxAbs, n); + } + /// Calculate exponent + const auto maxAbs32 = BlockFloatCompander::maskUpperWord(maxAbs); + return BlockFloatCompander::expLzCnt(maxAbs32, totShiftBits); + } + + + /// Compute exponent value for a set of 4 RB from the maximum absolute value. + /// Note that we do not need to perform any packing of result as we are only + /// computing 4 RB. The appropriate offset is taken later when extracting the + /// exponent. + __m512i + computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Re-order and vertical max abs + const auto maxAbsVert = BlockFloatCompander::maxAbsVertical4RB(rawData[0], rawData[1], rawData[2]); + /// Horizontal max abs + const auto maxAbsHorz = BlockFloatCompander::horizontalMax4x16(maxAbsVert); + /// Calculate exponent + const auto maxAbs = BlockFloatCompander::maskUpperWord(maxAbsHorz); + return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); + } + + + /// Compute exponent value for 1 RB from the maximum absolute value. + /// This works with horizontal max abs only, and needs to include a + /// step to select the final exponent from the 4 lanes. + uint8_t + computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) + { + const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); + /// Abs + const auto rawDataAbs = _mm512_abs_epi16(rawData[0]); + /// No need to do a full horizontal max operation here, just do a max IQ step, + /// compute the exponents and then use a reduce max over all exponent values. This + /// is the fastest way to handle a single RB. + const auto rawAbsIQSwap = _mm512_rol_epi32(rawDataAbs, BlockFloatCompander::k_numBitsIQ); + const auto maxAbsIQ = _mm512_max_epi16(rawDataAbs, rawAbsIQSwap); + /// Calculate exponent + const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ); + const auto exps = BlockFloatCompander::expLzCnt(maxAbsIQ32, totShiftBits); + /// At this point we have exponent values for the maximum of each IQ pair. + /// Run a reduce max step to compute the maximum exponent value in the first + /// three lanes - this will give the desired exponent for this RB. + constexpr uint16_t k_expMsk = 0x0FFF; + return (uint8_t)_mm512_mask_reduce_max_epi32(k_expMsk, exps); + } + + + /// Apply compression to 1 RB + template + void + applyCompressionN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr, const uint64_t rbWriteMask) + { + /// Get AVX512 pointer aligned to desired RB + const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); + /// Pack compressed data network byte order + const auto compDataBytePacked = networkBytePack(compData); + /// Store exponent first + dataOut->dataCompressed[thisRBExpAddr] = thisExp; + /// Store compressed data + _mm512_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, rbWriteMask, compDataBytePacked); + } + + + /// Apply 9, 10, or 12bit compression to 16 RB + template + void + compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * totNumBytesPerRB, rbWriteMask); + } + } + + + /// Apply 9, 10, or 12bit compression to 4 RB + template + void + compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint64_t rbWriteMask) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * totNumBytesPerRB, rbWriteMask); + } + } + + + /// Apply 9, 10, or 12bit compression to 1 RB + template + void + compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint64_t rbWriteMask) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + applyCompressionN_1RB(dataIn, dataOut, 0, thisExponent, 0, rbWriteMask); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + void + compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const __m512i totShiftBits, const int totNumBytesPerRB, const uint64_t rbWriteMask) + { + switch (dataIn.numBlocks) + { + case 16: + compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + + case 4: + compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + + case 1: + compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); + break; + } + } + + + /// Apply compression to 1 RB + void + applyCompression8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, + const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr) + { + /// Get AVX512 pointer aligned to desired RB + const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); + /// Apply the exponent shift + const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); + /// Store exponent first + dataOut->dataCompressed[thisRBExpAddr] = thisExp; + /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) + /// Use three offset stores to join + constexpr uint32_t k_rbMask = 0x00FFFFFF; // Write mask for 1RB (24 values) + _mm256_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_rbMask, _mm512_cvtepi16_epi8(compData)); + } + + + /// 8bit RB compression loop for 16 RB + void + compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_16RB(dataIn, totShiftBits); +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * (k_numREReal + 1)); + } + } + + + /// 8bit RB compression loop for 4 RB + void + compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto exponents = computeExponent_4RB(dataIn, totShiftBits); +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * (k_numREReal + 1)); + } + } + + + /// 8bit RB compression loop for 4 RB + void + compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); + applyCompression8_1RB(dataIn, dataOut, 0, thisExponent, 0); + } + + + /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. + void + compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) + { + switch (dataIn.numBlocks) + { + case 16: + compress8_16RB(dataIn, dataOut, totShiftBits); + break; + + case 4: + compress8_4RB(dataIn, dataOut, totShiftBits); + break; + + case 1: + compress8_1RB(dataIn, dataOut, totShiftBits); + break; + } + } + + + /// Apply compression to 1 RB + template + void + applyExpansionN_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int expAddr, const int thisRBAddr, const int maxExpShift) + { + /// Unpack network order packed data + const auto dataUnpacked = networkByteUnpack(dataIn.dataCompressed + expAddr + 1); + /// Apply exponent scaling (by appropriate arithmetic shift right) + const auto dataExpanded = _mm512_srai_epi16(dataUnpacked, maxExpShift - *(dataIn.dataCompressed + expAddr)); + /// Write expanded data to output + static constexpr uint32_t k_WriteMask = 0x00FFFFFF; + _mm512_mask_storeu_epi16(dataOut->dataExpanded + thisRBAddr, k_WriteMask, dataExpanded); + } + + + /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. + template + void + expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int totNumBytesPerRB, const int maxExpShift) + { + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + } + break; + + case 1: + applyExpansionN_1RB(dataIn, dataOut, 0, 0, maxExpShift); + break; + } + } + + + /// Apply expansion to 1 RB and store + void + applyExpansion8_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, + const int expAddr, const int thisRBAddr) + { + const __m256i* rawDataIn = reinterpret_cast(dataIn.dataCompressed + expAddr + 1); + const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn); + const auto expData = _mm512_slli_epi16(compData16, *(dataIn.dataCompressed + expAddr)); + constexpr uint8_t k_rbMask64 = 0b00111111; // 64b write mask for 1RB (24 int16 values) + _mm512_mask_storeu_epi64(dataOut->dataExpanded + thisRBAddr, k_rbMask64, expData); + } + + + /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. + void + expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) + { + switch (dataIn.numBlocks) + { + case 16: +#pragma unroll(16) + for (int n = 0; n < 16; ++n) + { + applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); + } + break; + + case 4: +#pragma unroll(4) + for (int n = 0; n < 4; ++n) + { + applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); + } + break; + + case 1: + applyExpansion8_1RB(dataIn, dataOut, 0, 0); + break; + } + } +} + + + +/// Main kernel function for compression. This version uses instructions available in Sunny Cove. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPCompressUserPlaneAvxSnc(const ExpandedData& dataIn, CompressedData* dataOut) +{ + /// Compensation for extra zeros in 32b leading zero count when computing exponent + const auto totShiftBits8 = _mm512_set1_epi32(25); + const auto totShiftBits9 = _mm512_set1_epi32(24); + const auto totShiftBits10 = _mm512_set1_epi32(23); + const auto totShiftBits12 = _mm512_set1_epi32(21); + + /// Total number of compressed bytes per RB for each iqWidth option + constexpr int totNumBytesPerRB9 = 28; + constexpr int totNumBytesPerRB10 = 31; + constexpr int totNumBytesPerRB12 = 37; + + /// Compressed data write mask for each iqWidth option + constexpr uint64_t rbWriteMask9 = 0x0000000007FFFFFF; + constexpr uint64_t rbWriteMask10 = 0x000000003FFFFFFF; + constexpr uint64_t rbWriteMask12 = 0x0000000FFFFFFFFF; + + switch (dataIn.iqWidth) + { + case 8: + BFP_UPlane_SNC::compressByAlloc8(dataIn, dataOut, totShiftBits8); + break; + + case 9: + BFP_UPlane_SNC::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerRB9, rbWriteMask9); + break; + + case 10: + BFP_UPlane_SNC::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerRB10, rbWriteMask10); + break; + + case 12: + BFP_UPlane_SNC::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerRB12, rbWriteMask12); + break; + } +} + + + +/// Main kernel function for expansion. +/// Starts by determining iqWidth specific parameters and functions. +void +BlockFloatCompander::BFPExpandUserPlaneAvxSnc(const CompressedData& dataIn, ExpandedData* dataOut) +{ + constexpr int k_totNumBytesPerRB9 = 28; + constexpr int k_totNumBytesPerRB10 = 31; + constexpr int k_totNumBytesPerRB12 = 37; + + constexpr int k_maxExpShift9 = 7; + constexpr int k_maxExpShift10 = 6; + constexpr int k_maxExpShift12 = 4; + + switch (dataIn.iqWidth) + { + case 8: + BFP_UPlane_SNC::expandByAlloc8(dataIn, dataOut); + break; + + case 9: + BFP_UPlane_SNC::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB9, k_maxExpShift9); + break; + + case 10: + BFP_UPlane_SNC::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB10, k_maxExpShift10); + break; + + case 12: + BFP_UPlane_SNC::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB12, k_maxExpShift12); + break; + } +} diff --git a/fhi_lib/lib/src/xran_bfp_utils.hpp b/fhi_lib/lib/src/xran_bfp_utils.hpp index 6f22139..dd6a2e5 100644 --- a/fhi_lib/lib/src/xran_bfp_utils.hpp +++ b/fhi_lib/lib/src/xran_bfp_utils.hpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,11 +29,6 @@ namespace BlockFloatCompander { - /// Define function signatures for byte packing functions - typedef __m512i(*PackFunction)(const __m512i); - typedef __m512i(*UnpackFunction)(const uint8_t*); - typedef __m256i(*UnpackFunction256)(const uint8_t*); - /// Calculate exponent based on 16 max abs values using leading zero count. inline __m512i maskUpperWord(const __m512i inData) @@ -45,6 +40,7 @@ namespace BlockFloatCompander return _mm512_and_epi64(inData, k_upperWordMask); } + /// Calculate exponent based on 16 max abs values using leading zero count. inline __m512i expLzCnt(const __m512i maxAbs, const __m512i totShiftBits) @@ -54,6 +50,8 @@ namespace BlockFloatCompander return _mm512_subs_epu16(totShiftBits, lzCount); } + + /// Full horizontal max of 16b values inline int horizontalMax1x32(const __m512i maxAbsReg) { @@ -67,297 +65,68 @@ namespace BlockFloatCompander return _mm512_reduce_max_epi32(maxAbs32); } - /// Pack compressed 9 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - inline __m512i - networkBytePack9b(const __m512i compData) - { - /// Logical shift left to align network order byte parts - const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000100020003, 0x0004000500060007, - 0x0000000100020003, 0x0004000500060007, - 0x0000000100020003, 0x0004000500060007, - 0x0000000100020003, 0x0004000500060007); - const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); - - /// First epi8 shuffle of even indexed samples - const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x0000000000000000, 0x0C0D080904050001, - 0x0000000000000000, 0x0C0D080904050001, - 0x0000000000000000, 0x0C0D080904050001, - 0x0000000000000000, 0x0C0D080904050001); - constexpr uint64_t k_byteMask1 = 0x00FF00FF00FF00FF; - const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); - - /// Second epi8 shuffle of odd indexed samples - const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000000000E, 0x0F0A0B0607020300, - 0x000000000000000E, 0x0F0A0B0607020300, - 0x000000000000000E, 0x0F0A0B0607020300, - 0x000000000000000E, 0x0F0A0B0607020300); - constexpr uint64_t k_byteMask2 = 0x01FE01FE01FE01FE; - const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); - - /// Ternary blend of the two shuffled results - const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000000000FF, 0x01FC07F01FC07F00, - 0x00000000000000FF, 0x01FC07F01FC07F00, - 0x00000000000000FF, 0x01FC07F01FC07F00, - 0x00000000000000FF, 0x01FC07F01FC07F00); - return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); - } - - - /// Pack compressed 10 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - inline __m512i - networkBytePack10b(const __m512i compData) - { - /// Logical shift left to align network order byte parts - const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, - 0x0000000200040006, 0x0000000200040006, - 0x0000000200040006, 0x0000000200040006, - 0x0000000200040006, 0x0000000200040006); - const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); - - /// First epi8 shuffle of even indexed samples - const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x000000000000000C, 0x0D08090004050001, - 0x000000000000000C, 0x0D08090004050001, - 0x000000000000000C, 0x0D08090004050001, - 0x000000000000000C, 0x0D08090004050001); - constexpr uint64_t k_byteMask1 = 0x01EF01EF01EF01EF; - const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); - - /// Second epi8 shuffle of odd indexed samples - const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x0000000000000E0F, 0x0A0B000607020300, - 0x0000000000000E0F, 0x0A0B000607020300, - 0x0000000000000E0F, 0x0A0B000607020300, - 0x0000000000000E0F, 0x0A0B000607020300); - constexpr uint64_t k_byteMask2 = 0x03DE03DE03DE03DE; - const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); - - /// Ternary blend of the two shuffled results - const __m512i k_ternLogSelect = _mm512_set_epi64(0x000000000000FF03, 0xF03F00FF03F03F00, - 0x000000000000FF03, 0xF03F00FF03F03F00, - 0x000000000000FF03, 0xF03F00FF03F03F00, - 0x000000000000FF03, 0xF03F00FF03F03F00); - return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); - } - - - /// Pack compressed 12 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - inline __m512i - networkBytePack12b(const __m512i compData) - { - /// Logical shift left to align network order byte parts - const __m512i k_shiftLeft = _mm512_set_epi64(0x0000000400000004, 0x0000000400000004, - 0x0000000400000004, 0x0000000400000004, - 0x0000000400000004, 0x0000000400000004, - 0x0000000400000004, 0x0000000400000004); - const auto compDataPacked = _mm512_sllv_epi16(compData, k_shiftLeft); - - /// First epi8 shuffle of even indexed samples - const __m512i k_byteShuffleMask1 = _mm512_set_epi64(0x00000000000C0D00, 0x0809000405000001, - 0x00000000000C0D00, 0x0809000405000001, - 0x00000000000C0D00, 0x0809000405000001, - 0x00000000000C0D00, 0x0809000405000001); - constexpr uint64_t k_byteMask1 = 0x06DB06DB06DB06DB; - const auto compDataShuff1 = _mm512_maskz_shuffle_epi8(k_byteMask1, compDataPacked, k_byteShuffleMask1); - - /// Second epi8 shuffle of odd indexed samples - const __m512i k_byteShuffleMask2 = _mm512_set_epi64(0x000000000E0F000A, 0x0B00060700020300, - 0x000000000E0F000A, 0x0B00060700020300, - 0x000000000E0F000A, 0x0B00060700020300, - 0x000000000E0F000A, 0x0B00060700020300); - constexpr uint64_t k_byteMask2 = 0x0DB60DB60DB60DB6; - const auto compDataShuff2 = _mm512_maskz_shuffle_epi8(k_byteMask2, compDataPacked, k_byteShuffleMask2); - - /// Ternary blend of the two shuffled results - const __m512i k_ternLogSelect = _mm512_set_epi64(0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, - 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, - 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00, - 0x00000000FF0F00FF, 0x0F00FF0F00FF0F00); - return _mm512_ternarylogic_epi64(compDataShuff1, compDataShuff2, k_ternLogSelect, 0xd8); - } - - /// Unpack compressed 9 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 + /// Perform horizontal max of 16 bit values across each lane inline __m512i - networkByteUnpack9b(const uint8_t* inData) + horizontalMax4x16(const __m512i maxAbsIn) { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m512i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm512_set_epi32(9, 8, 7, 6, 7, 6, 5, 4, - 5, 4, 3, 2, 3, 2, 1, 0); - const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// Due to previous permute to get chunks of bytes into each lane, there is - /// a different shuffle offset in each lane - const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0607050604050304, - 0x090A080907080607, 0x0506040503040203, - 0x0809070806070506, 0x0405030402030102, - 0x0708060705060405, 0x0304020301020001); - const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m512i k_slBits = _mm512_set_epi64(0x0007000600050004, 0x0003000200010000, - 0x0007000600050004, 0x0003000200010000, - 0x0007000600050004, 0x0003000200010000, - 0x0007000600050004, 0x0003000200010000); - const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m512i k_expMask = _mm512_set1_epi16(0xFF80); - return _mm512_and_epi64(inSetSign, k_expMask); + /// Swap 64b in each lane and compute max + const auto k_perm64b = _mm512_set_epi64(6, 7, 4, 5, 2, 3, 0, 1); + auto maxAbsPerm = _mm512_permutexvar_epi64(k_perm64b, maxAbsIn); + auto maxAbsHorz = _mm512_max_epi16(maxAbsIn, maxAbsPerm); + + /// Swap each pair of 32b in each lane and compute max + const auto k_perm32b = _mm512_set_epi32(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1); + maxAbsPerm = _mm512_permutexvar_epi32(k_perm32b, maxAbsHorz); + maxAbsHorz = _mm512_max_epi16(maxAbsHorz, maxAbsPerm); + + /// Swap each IQ pair in each lane (via 32b rotation) and compute max + maxAbsPerm = _mm512_rol_epi32(maxAbsHorz, BlockFloatCompander::k_numBitsIQ); + return _mm512_max_epi16(maxAbsHorz, maxAbsPerm); } - /// Unpack compressed 10 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 + /// Perform U-plane input data re-ordering and vertical max abs of 16b values + /// Works on 4 RB at a time inline __m512i - networkByteUnpack10b(const uint8_t* inData) + maxAbsVertical4RB(const __m512i inA, const __m512i inB, const __m512i inC) { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m512i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm512_set_epi32(10, 9, 8, 7, 8, 7, 6, 5, - 5, 4, 3, 2, 3, 2, 1, 0); - const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// Due to previous permute to get chunks of bytes into each lane, lanes - /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes - const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A08090708, 0x0506040503040203, - 0x0809070806070506, 0x0304020301020001, - 0x0A0B090A08090708, 0x0506040503040203, - 0x0809070806070506, 0x0304020301020001); - const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m512i k_slBits = _mm512_set_epi64(0x0006000400020000, 0x0006000400020000, - 0x0006000400020000, 0x0006000400020000, - 0x0006000400020000, 0x0006000400020000, - 0x0006000400020000, 0x0006000400020000); - const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m512i k_expMask = _mm512_set1_epi16(0xFFC0); - return _mm512_and_epi64(inSetSign, k_expMask); + /// Re-order the next 4RB in input data into 3 registers + /// Input SIMD vectors are: + /// [A A A A A A A A A A A A B B B B] + /// [B B B B B B B B C C C C C C C C] + /// [C C C C D D D D D D D D D D D D] + /// Re-ordered SIMD vectors are: + /// [A A A A B B B B C C C C D D D D] + /// [A A A A B B B B C C C C D D D D] + /// [A A A A B B B B C C C C D D D D] + constexpr uint8_t k_msk1 = 0b11111100; // Copy first lane of src + constexpr int k_shuff1 = 0x41; + const auto z_w1 = _mm512_mask_shuffle_i64x2(inA, k_msk1, inB, inC, k_shuff1); + + constexpr uint8_t k_msk2 = 0b11000011; // Copy middle two lanes of src + constexpr int k_shuff2 = 0xB1; + const auto z_w2 = _mm512_mask_shuffle_i64x2(inB, k_msk2, inA, inC, k_shuff2); + + constexpr uint8_t k_msk3 = 0b00111111; // Copy last lane of src + constexpr int k_shuff3 = 0xBE; + const auto z_w3 = _mm512_mask_shuffle_i64x2(inC, k_msk3, inA, inB, k_shuff3); + + /// Perform max abs on these 3 registers + const auto abs16_1 = _mm512_abs_epi16(z_w1); + const auto abs16_2 = _mm512_abs_epi16(z_w2); + const auto abs16_3 = _mm512_abs_epi16(z_w3); + return _mm512_max_epi16(_mm512_max_epi16(abs16_1, abs16_2), abs16_3); } - /// Unpack compressed 12 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 + /// Selects first 32 bit value in each src lane and packs into laneNum of dest inline __m512i - networkByteUnpack12b(const uint8_t* inData) - { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m512i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm512_set_epi32(12, 11, 10, 9, 9, 8, 7, 6, - 6, 5, 4, 3, 3, 2, 1, 0); - const auto inLaneAlign = _mm512_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset - const __m512i k_byteShuffleMask = _mm512_set_epi64(0x0A0B090A07080607, 0x0405030401020001, - 0x0A0B090A07080607, 0x0405030401020001, - 0x0A0B090A07080607, 0x0405030401020001, - 0x0A0B090A07080607, 0x0405030401020001); - const auto inDatContig = _mm512_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m512i k_slBits = _mm512_set_epi64(0x0004000000040000, 0x0004000000040000, - 0x0004000000040000, 0x0004000000040000, - 0x0004000000040000, 0x0004000000040000, - 0x0004000000040000, 0x0004000000040000); - const auto inSetSign = _mm512_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m512i k_expMask = _mm512_set1_epi16(0xFFF0); - return _mm512_and_epi64(inSetSign, k_expMask); - } - - - /// Unpack compressed 9 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - /// This unpacking function is for 256b registers - inline __m256i - networkByteUnpack9b256(const uint8_t* inData) - { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m256i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0); - const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// Due to previous permute to get chunks of bytes into each lane, there is - /// a different shuffle offset in each lane - const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0809070806070506, 0x0405030402030102, - 0x0708060705060405, 0x0304020301020001); - const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m256i k_slBits = _mm256_set_epi64x(0x0007000600050004, 0x0003000200010000, - 0x0007000600050004, 0x0003000200010000); - const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m256i k_expMask = _mm256_set1_epi16(0xFF80); - return _mm256_and_si256(inSetSign, k_expMask); - } - - - /// Unpack compressed 10 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - /// This unpacking function is for 256b registers - inline __m256i - networkByteUnpack10b256(const uint8_t* inData) - { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m256i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm256_set_epi32(5, 4, 3, 2, 3, 2, 1, 0); - const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// Due to previous permute to get chunks of bytes into each lane, lanes - /// 0 and 2 happen to be aligned, but lane 1 is offset by 2 bytes - const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A08090708, 0x0506040503040203, - 0x0809070806070506, 0x0304020301020001); - const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m256i k_slBits = _mm256_set_epi64x(0x0006000400020000, 0x0006000400020000, - 0x0006000400020000, 0x0006000400020000); - const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m256i k_expMask = _mm256_set1_epi16(0xFFC0); - return _mm256_and_si256(inSetSign, k_expMask); - } - - - /// Unpack compressed 12 bit data in network byte order - /// See https://soco.intel.com/docs/DOC-2665619 - /// This unpacking function is for 256b registers - inline __m256i - networkByteUnpack12b256(const uint8_t* inData) + slidePermute(const __m512i src, const __m512i dest, const int laneNum) { - /// Align chunks of compressed bytes into lanes to allow for expansion - const __m256i* rawDataIn = reinterpret_cast(inData); - const auto k_expPerm = _mm256_set_epi32(6, 5, 4, 3, 3, 2, 1, 0); - const auto inLaneAlign = _mm256_permutexvar_epi32(k_expPerm, *rawDataIn); - - /// Byte shuffle to get all bits for each sample into 16b chunks - /// For 12b mantissa all lanes post-permute are aligned and require same shuffle offset - const __m256i k_byteShuffleMask = _mm256_set_epi64x(0x0A0B090A07080607, 0x0405030401020001, - 0x0A0B090A07080607, 0x0405030401020001); - const auto inDatContig = _mm256_shuffle_epi8(inLaneAlign, k_byteShuffleMask); - - /// Logical shift left to set sign bit - const __m256i k_slBits = _mm256_set_epi64x(0x0004000000040000, 0x0004000000040000, - 0x0004000000040000, 0x0004000000040000); - const auto inSetSign = _mm256_sllv_epi16(inDatContig, k_slBits); - - /// Mask to zero unwanted bits - const __m256i k_expMask = _mm256_set1_epi16(0xFFF0); - return _mm256_and_si256(inSetSign, k_expMask); + const auto k_selectVals = _mm512_set_epi32(28, 24, 20, 16, 28, 24, 20, 16, + 28, 24, 20, 16, 28, 24, 20, 16); + constexpr uint16_t k_laneMsk[4] = { 0x000F, 0x00F0, 0x0F00, 0xF000 }; + return _mm512_mask_permutex2var_epi32(dest, k_laneMsk[laneNum], k_selectVals, src); } } diff --git a/fhi_lib/lib/src/xran_cb_proc.c b/fhi_lib/lib/src/xran_cb_proc.c new file mode 100644 index 0000000..b35d55c --- /dev/null +++ b/fhi_lib/lib/src/xran_cb_proc.c @@ -0,0 +1,628 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN Callback processing functionality and helper functions + * @file xran_cb_proc.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ethdi.h" +#include "xran_fh_o_du.h" +#include "xran_main.h" +#include "xran_dev.h" +#include "xran_common.h" +#include "xran_cb_proc.h" +#include "xran_mlog_lnx.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_printf.h" + +typedef void (*rx_dpdk_sym_cb_fn)(struct rte_timer *tim, void *arg); + +void xran_timer_arm(struct rte_timer *tim, void* arg, void *p_dev_ctx) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx; + uint64_t t3 = MLogTick(); + + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)arg; + rte_timer_reset_sync(tim, 0, SINGLE, p_xran_dev_ctx->fh_init.io_cfg.timing_core, fct, p_dev_ctx); + } + MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); +} + +void xran_timer_arm_cp_dl(struct rte_timer *tim, void* arg, void *p_dev_ctx) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx; + uint64_t t3 = MLogTick(); + + unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_CP_DL, p_xran_dev_ctx); + + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)arg; + rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_dev_ctx); + } + MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); +} + +void xran_timer_arm_cp_ul(struct rte_timer *tim, void* arg, void *p_dev_ctx) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx; + uint64_t t3 = MLogTick(); + + unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_CP_UL, p_xran_dev_ctx); + + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)arg; + rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_dev_ctx); + } + MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); +} + +void xran_timer_arm_for_deadline(struct rte_timer *tim, void* arg, void *p_dev_ctx) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_dev_ctx; + uint64_t t3 = MLogTick(); + + unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_DEADLINE, p_xran_dev_ctx); + + int32_t rx_tti; + int32_t cc_id; + uint32_t nFrameIdx; + uint32_t nSubframeIdx; + uint32_t nSlotIdx; + uint64_t nSecond; + + xran_get_slot_idx(p_xran_dev_ctx->xran_port_id, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local) + + nSubframeIdx*SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local) + + nSlotIdx; + + p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put % MAX_CB_TIMER_CTX].tti_to_process = rx_tti; + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)arg; + rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_xran_dev_ctx); + } + + MLogTask(PID_TIME_ARM_TIMER_DEADLINE, t3, MLogTick()); +} + +void xran_timer_arm_user_cb(struct rte_timer *tim, void* arg, void *p_ctx) +{ + struct cb_user_per_sym_ctx* p_sym_cb_ctx = (struct cb_user_per_sym_ctx *)p_ctx; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)p_sym_cb_ctx->p_dev; + uint64_t t3 = MLogTick(); + + unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_SYM_CB, NULL); + + int32_t rx_tti; + int32_t cc_id; + uint32_t nFrameIdx = 0; + uint32_t nSubframeIdx = 0; + uint32_t nSlotIdx = 0; + uint64_t nSecond = 0; + + xran_get_slot_idx(p_xran_dev_ctx->xran_port_id, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local) + + nSubframeIdx*SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local) + + nSlotIdx; + + p_sym_cb_ctx->user_cb_timer_ctx[p_sym_cb_ctx->user_timer_put % MAX_CB_TIMER_CTX].tti_to_process = rx_tti; + p_sym_cb_ctx->user_cb_timer_ctx[p_sym_cb_ctx->user_timer_put % MAX_CB_TIMER_CTX].ota_sym_idx = xran_lib_ota_sym_idx[p_xran_dev_ctx->xran_port_id]; + p_sym_cb_ctx->user_cb_timer_ctx[p_sym_cb_ctx->user_timer_put % MAX_CB_TIMER_CTX].xran_sfn_at_sec_start = xran_getSfnSecStart(); + p_sym_cb_ctx->user_cb_timer_ctx[p_sym_cb_ctx->user_timer_put % MAX_CB_TIMER_CTX].current_second = nSecond; + + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)arg; + rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, p_sym_cb_ctx); + if (++p_sym_cb_ctx->user_timer_put >= MAX_CB_TIMER_CTX) + p_sym_cb_ctx->user_timer_put = 0; + } + + MLogTask(PID_TIME_ARM_USER_TIMER_DEADLINE, t3, MLogTick()); +} + +void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore) +{ + uint64_t t3 = MLogTick(); + + if (xran_if_current_state == XRAN_RUNNING){ + rte_timer_cb_t fct = (rte_timer_cb_t)CbFct; + rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, CbArg); + } + MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); +} + +int32_t +xran_timing_create_cbs(void *args) +{ + int32_t res = XRAN_STATUS_SUCCESS; + int32_t do_reset = 0; + uint64_t t1 = 0; + int32_t result1,i,j; + uint32_t delay_cp_dl; + uint32_t delay_cp_ul; + uint32_t delay_up; + uint32_t time_diff_us; + uint32_t delay_cp2up; + uint32_t sym_cp_dl; + uint32_t sym_cp_ul; + uint32_t time_diff_nSymb; + int32_t sym_up; + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)args; + uint64_t tWake = 0, tWakePrev = 0, tUsed = 0; + struct cb_elem_entry * cb_elm = NULL; + uint32_t interval_us_local = p_dev_ctx->interval_us_local; + + /* ToS = Top of Second start +- 1.5us */ + struct timespec ts; + char buff[100]; + + if (p_dev_ctx->fh_init.io_cfg.id == O_DU) { + + delay_cp_dl = interval_us_local - p_dev_ctx->fh_cfg.T1a_max_cp_dl; + delay_cp_ul = interval_us_local - p_dev_ctx->fh_cfg.T1a_max_cp_ul; + delay_up = p_dev_ctx->fh_cfg.T1a_max_up; + time_diff_us = p_dev_ctx->fh_cfg.Ta4_max; + + delay_cp2up = delay_up-delay_cp_dl; + + sym_cp_dl = delay_cp_dl*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1; + sym_cp_ul = delay_cp_ul*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1; + time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT); + p_dev_ctx->sym_up = sym_up = -(delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT)); + p_dev_ctx->sym_up_ul = time_diff_nSymb = (time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1); + + printf("Start C-plane DL %d us after TTI [trigger on sym %d]\n", delay_cp_dl, sym_cp_dl); + printf("Start C-plane UL %d us after TTI [trigger on sym %d]\n", delay_cp_ul, sym_cp_ul); + printf("Start U-plane DL %d us before OTA [offset in sym %d]\n", delay_up, sym_up); + printf("Start U-plane UL %d us OTA [offset in sym %d]\n", time_diff_us, time_diff_nSymb); + + printf("C-plane to U-plane delay %d us after TTI\n", delay_cp2up); + printf("Start Sym timer %ld ns\n", TX_TIMER_INTERVAL/N_SYM_PER_SLOT); + + cb_elm = xran_create_cb(xran_timer_arm_cp_dl, tx_cp_dl_cb, (void*)p_dev_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_cp_dl], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + res = XRAN_STATUS_FAIL; + goto err0; + } + + cb_elm = xran_create_cb(xran_timer_arm_cp_ul, tx_cp_ul_cb, (void*)p_dev_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_cp_ul], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + res = XRAN_STATUS_FAIL; + goto err0; + } + + /* Full slot UL OTA + time_diff_us */ + cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb, (void*)p_dev_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[time_diff_nSymb], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + res = XRAN_STATUS_FAIL; + goto err0; + } + + /* Half slot UL OTA + time_diff_us*/ + cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_half_cb, (void*)p_dev_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[time_diff_nSymb + N_SYM_PER_SLOT/2], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + res = XRAN_STATUS_FAIL; + goto err0; + } + } else { // APP_O_RU + /* calculate when to send UL U-plane */ + delay_up = p_dev_ctx->fh_cfg.Ta3_min; + p_dev_ctx->sym_up = sym_up = delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1; + printf("Start UL U-plane %d us after OTA [offset in sym %d]\n", delay_up, sym_up); + + /* calcualte when to Receive DL U-plane */ + delay_up = p_dev_ctx->fh_cfg.T2a_max_up; + sym_up = delay_up*1000/(interval_us_local*1000/N_SYM_PER_SLOT)+1; + printf("Receive DL U-plane %d us after OTA [offset in sym %d]\n", delay_up, sym_up); + + /* Full slot UL OTA + time_diff_us */ + cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb, (void*)p_dev_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[sym_up], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + res = -1; + goto err0; + } + + do { + timespec_get(&ts, TIME_UTC); + }while (ts.tv_nsec >1500); + struct tm * ptm = gmtime(&ts.tv_sec); + if(ptm){ + strftime(buff, sizeof buff, "%D %T", ptm); + printf("RU: thread_run start time: %s.%09ld UTC [%d]\n", buff, ts.tv_nsec, interval_us_local); + } + } + + return XRAN_STATUS_SUCCESS; + + err0: + for (j = 0; j< XRAN_NUM_OF_SYMBOL_PER_SLOT; j++){ + struct cb_elem_entry *cb_elm; + LIST_FOREACH(cb_elm, &p_dev_ctx->sym_cb_list_head[j], pointers){ + if(cb_elm){ + LIST_REMOVE(cb_elm, pointers); + xran_destroy_cb(cb_elm); + } + } + } + + return XRAN_STATUS_FAIL; +} +int32_t +xran_timing_destroy_cbs(void *args) +{ + int res = XRAN_STATUS_SUCCESS; + int32_t do_reset = 0; + uint64_t t1 = 0; + int32_t result1,i,j; + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)args; + struct cb_elem_entry * cb_elm = NULL; + + for (j = 0; j< XRAN_NUM_OF_SYMBOL_PER_SLOT; j++){ + struct cb_elem_entry *cb_elm; + LIST_FOREACH(cb_elm, &p_dev_ctx->sym_cb_list_head[j], pointers){ + if(cb_elm){ + LIST_REMOVE(cb_elm, pointers); + xran_destroy_cb(cb_elm); + } + } + } + + return XRAN_STATUS_SUCCESS; +} + +static int32_t +xran_reg_sym_cb_ota(struct xran_device_ctx * p_dev_ctx, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, uint8_t symb, + struct cb_user_per_sym_ctx **p_sym_cb_ctx) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct cb_user_per_sym_ctx *p_loc_sym_cb_ctx = &p_dev_ctx->symCbCtx[symb][XRAN_CB_SYM_OTA_TIME]; + if(p_loc_sym_cb_ctx->status){ + ret = XRAN_STATUS_RESOURCE; + print_err("timer sym %d type id %d was already created",symb, XRAN_CB_SYM_OTA_TIME); + return ret; + } + printf("requested symb %d OTA coresponds to symb %d OTA time\n", symb, symb); + + p_loc_sym_cb_ctx->symb_num_req = symb; + p_loc_sym_cb_ctx->sym_diff = 0; /* OTA and Request Symb are the same */ + p_loc_sym_cb_ctx->symb_num_ota = symb; + p_loc_sym_cb_ctx->cb_type_id = XRAN_CB_SYM_OTA_TIME; + p_loc_sym_cb_ctx->p_dev = p_dev_ctx; + + p_loc_sym_cb_ctx->symCb = symCb; + p_loc_sym_cb_ctx->symCbParam = symCbParam; + p_loc_sym_cb_ctx->symCbTimeInfo = symCbTime; + + p_loc_sym_cb_ctx->status = 1; + + *p_sym_cb_ctx = p_loc_sym_cb_ctx; + + return ret; +} + +static int32_t +xran_reg_sym_cb_rx_win_end(struct xran_device_ctx * p_dev_ctx, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, + uint8_t symb, struct cb_user_per_sym_ctx **p_sym_cb_ctx) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct cb_user_per_sym_ctx *p_loc_sym_cb_ctx = &p_dev_ctx->symCbCtx[symb][XRAN_CB_SYM_RX_WIN_END]; + uint32_t time_diff_us = 0; + uint32_t time_diff_nSymb = 0; + uint32_t absolute_ota_sym = 0; + uint32_t interval_us_local = p_dev_ctx->interval_us_local; + + if(p_loc_sym_cb_ctx->status) { + ret = XRAN_STATUS_RESOURCE; + print_err("timer sym %d type id %d was already created",symb, XRAN_CB_SYM_RX_WIN_END); + return ret; + } + + time_diff_us = p_dev_ctx->fh_cfg.Ta4_max; + printf("RX WIN end Ta4_max is %d [us] where TTI is %d [us] \n", time_diff_us, interval_us_local); + time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT); + if ((time_diff_nSymb/1000/(interval_us_local*1000/N_SYM_PER_SLOT)) < time_diff_us) { + time_diff_nSymb+=1; + printf("time duration %d rounded up to duration of %d symbols\n", time_diff_us, time_diff_nSymb); + } + printf("U-plane UL delay %d [us] measured against OTA time [offset in symbols is %d]\n", time_diff_us, time_diff_nSymb); + absolute_ota_sym = (symb + time_diff_nSymb) % XRAN_NUM_OF_SYMBOL_PER_SLOT; + printf("requested symb %d pkt arrival time [deadline] coresponds to symb %d OTA time\n", symb, absolute_ota_sym); + + p_loc_sym_cb_ctx->symb_num_req = symb; + p_loc_sym_cb_ctx->sym_diff = -time_diff_nSymb; + p_loc_sym_cb_ctx->symb_num_ota = absolute_ota_sym; + p_loc_sym_cb_ctx->cb_type_id = XRAN_CB_SYM_RX_WIN_END; + p_loc_sym_cb_ctx->p_dev = p_dev_ctx; + + p_loc_sym_cb_ctx->symCb = symCb; + p_loc_sym_cb_ctx->symCbParam = symCbParam; + p_loc_sym_cb_ctx->symCbTimeInfo = symCbTime; + + p_loc_sym_cb_ctx->status = 1; + + *p_sym_cb_ctx =p_loc_sym_cb_ctx; + + return ret; +} + +static int32_t +xran_reg_sym_cb_rx_win_begin(struct xran_device_ctx * p_dev_ctx, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, + uint8_t symb, struct cb_user_per_sym_ctx **p_sym_cb_ctx) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct cb_user_per_sym_ctx *p_loc_sym_cb_ctx = &p_dev_ctx->symCbCtx[symb][XRAN_CB_SYM_RX_WIN_BEGIN]; + uint32_t time_diff_us = 0; + uint32_t time_diff_nSymb = 0; + uint32_t absolute_ota_sym = 0; + uint32_t interval_us_local = p_dev_ctx->interval_us_local; + + if(p_loc_sym_cb_ctx->status) { + ret = XRAN_STATUS_RESOURCE; + print_err("timer sym %d type id %d was already created",symb, XRAN_CB_SYM_RX_WIN_BEGIN); + return ret; + } + + time_diff_us = p_dev_ctx->fh_cfg.Ta4_min; + printf("RX WIN begin Ta4_min is %d [us] where TTI is %d [us] \n", time_diff_us, interval_us_local); + time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT); + printf("U-plane UL delay %d [us] measured against OTA time [offset in symbols is %d]\n", time_diff_us, time_diff_nSymb); + absolute_ota_sym = (symb + time_diff_nSymb) % XRAN_NUM_OF_SYMBOL_PER_SLOT; + printf("requested symb %d pkt arrival time [deadline] coresponds to symb %d OTA time\n", symb, absolute_ota_sym); + + p_loc_sym_cb_ctx->symb_num_req = symb; + p_loc_sym_cb_ctx->sym_diff = -time_diff_nSymb; + p_loc_sym_cb_ctx->symb_num_ota = absolute_ota_sym; + p_loc_sym_cb_ctx->cb_type_id = XRAN_CB_SYM_RX_WIN_BEGIN; + p_loc_sym_cb_ctx->p_dev = p_dev_ctx; + + p_loc_sym_cb_ctx->symCb = symCb; + p_loc_sym_cb_ctx->symCbParam = symCbParam; + p_loc_sym_cb_ctx->symCbTimeInfo = symCbTime; + + p_loc_sym_cb_ctx->status = 1; + + *p_sym_cb_ctx =p_loc_sym_cb_ctx; + + return ret; +} + +static int32_t +xran_reg_sym_cb_tx_win_end(struct xran_device_ctx * p_dev_ctx, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, + uint8_t symb, struct cb_user_per_sym_ctx **p_sym_cb_ctx) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct cb_user_per_sym_ctx *p_loc_sym_cb_ctx = &p_dev_ctx->symCbCtx[symb][XRAN_CB_SYM_TX_WIN_END]; + uint32_t time_diff_us = 0; + uint32_t time_diff_nSymb = 0; + uint32_t absolute_ota_sym = 0; + uint32_t interval_us_local = p_dev_ctx->interval_us_local; + + if(p_loc_sym_cb_ctx->status) { + ret = XRAN_STATUS_RESOURCE; + print_err("timer sym %d type id %d was already created",symb, XRAN_CB_SYM_TX_WIN_END); + return ret; + } + + time_diff_us = p_dev_ctx->fh_cfg.T1a_min_up; + printf("TX WIN end -T1a_min_up is %d [us] where TTI is %d [us] \n", time_diff_us, interval_us_local); + time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT); + if ((time_diff_nSymb/1000/(interval_us_local*1000/N_SYM_PER_SLOT)) < time_diff_us) { + time_diff_nSymb +=1; + printf("time duration %d rounded up to duration of %d symbols\n", time_diff_us, time_diff_nSymb); + } + printf("U-plane DL advance is %d [us] measured against OTA time [offset in symbols is %d]\n", time_diff_us, -time_diff_nSymb); + absolute_ota_sym = ((symb + XRAN_NUM_OF_SYMBOL_PER_SLOT) - time_diff_nSymb) % XRAN_NUM_OF_SYMBOL_PER_SLOT; + printf("requested symb %d pkt tx time [deadline] corresponds to symb %d OTA time\n", symb, absolute_ota_sym); + + p_loc_sym_cb_ctx->symb_num_req = symb; + p_loc_sym_cb_ctx->sym_diff = time_diff_nSymb; + p_loc_sym_cb_ctx->symb_num_ota = absolute_ota_sym; + p_loc_sym_cb_ctx->cb_type_id = XRAN_CB_SYM_TX_WIN_END; + p_loc_sym_cb_ctx->p_dev = p_dev_ctx; + + p_loc_sym_cb_ctx->symCb = symCb; + p_loc_sym_cb_ctx->symCbParam = symCbParam; + p_loc_sym_cb_ctx->symCbTimeInfo = symCbTime; + + p_loc_sym_cb_ctx->status = 1; + + *p_sym_cb_ctx = p_loc_sym_cb_ctx; + + return ret; +} + +static int32_t +xran_reg_sym_cb_tx_win_begin(struct xran_device_ctx * p_dev_ctx, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, + uint8_t symb, struct cb_user_per_sym_ctx **p_sym_cb_ctx) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct cb_user_per_sym_ctx *p_loc_sym_cb_ctx = &p_dev_ctx->symCbCtx[symb][XRAN_CB_SYM_TX_WIN_BEGIN]; + uint32_t time_diff_us = 0; + uint32_t time_diff_nSymb = 0; + uint32_t absolute_ota_sym = 0; + uint32_t interval_us_local = p_dev_ctx->interval_us_local; + + if(p_loc_sym_cb_ctx->status) { + ret = XRAN_STATUS_RESOURCE; + print_err("timer sym %d type id %d was already created",symb, XRAN_CB_SYM_TX_WIN_BEGIN); + return ret; + } + + time_diff_us = p_dev_ctx->fh_cfg.T1a_max_up; + printf("TX WIN begin -T1a_max_up is %d [us] where TTI is %d [us] \n", time_diff_us, interval_us_local); + time_diff_nSymb = (time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT)); + if ((time_diff_nSymb/1000/(interval_us_local*1000/N_SYM_PER_SLOT)) < time_diff_us) { + time_diff_nSymb +=1; + printf("time duration %d rounded up to duration of %d symbols\n", time_diff_us, time_diff_nSymb); + } + printf("U-plane DL advance is %d [us] measured against OTA time [offset in symbols is %d]\n", time_diff_us, -time_diff_nSymb); + printf("requested symb %d pkt tx time [deadline] corresponds to symb %d OTA time\n", symb, absolute_ota_sym); + absolute_ota_sym = ((symb + XRAN_NUM_OF_SYMBOL_PER_SLOT) - time_diff_nSymb) % XRAN_NUM_OF_SYMBOL_PER_SLOT; + + p_loc_sym_cb_ctx->symb_num_req = symb; + p_loc_sym_cb_ctx->sym_diff = time_diff_nSymb; + p_loc_sym_cb_ctx->symb_num_ota = absolute_ota_sym; + p_loc_sym_cb_ctx->cb_type_id = XRAN_CB_SYM_TX_WIN_BEGIN; + p_loc_sym_cb_ctx->p_dev = p_dev_ctx; + + p_loc_sym_cb_ctx->symCb = symCb; + p_loc_sym_cb_ctx->symCbParam = symCbParam; + p_loc_sym_cb_ctx->symCbTimeInfo = symCbTime; + + p_loc_sym_cb_ctx->status = 1; + + *p_sym_cb_ctx =p_loc_sym_cb_ctx; + + return ret; +} + +int32_t +xran_reg_sym_cb(void *pHandle, xran_callback_sym_fn symCb, void * symCbParam, struct xran_sense_of_time* symCbTime, uint8_t symb, enum cb_per_sym_type_id cb_sym_t_id) +{ + int32_t ret = XRAN_STATUS_SUCCESS; + struct xran_device_ctx * p_dev_ctx = NULL; + struct cb_elem_entry * cb_elm = NULL; + struct cb_user_per_sym_ctx *p_sym_cb_ctx = NULL; + rx_dpdk_sym_cb_fn dpdk_cb_to_arm = NULL; + + if(xran_get_if_state() == XRAN_RUNNING) { + print_err("Cannot register callback while running!!"); + return (-1); + } + + if(pHandle) { + p_dev_ctx = (struct xran_device_ctx *)pHandle; + } else { + print_err("pHandle==NULL"); + ret = XRAN_STATUS_INVALID_PARAM; + return ret; + } + + switch (cb_sym_t_id) { + case XRAN_CB_SYM_OTA_TIME: + ret = xran_reg_sym_cb_ota(p_dev_ctx, symCb, symCbParam, symCbTime, symb, &p_sym_cb_ctx); + if(ret != XRAN_STATUS_SUCCESS) + return ret; + dpdk_cb_to_arm = rx_ul_user_sym_cb; + break; + case XRAN_CB_SYM_RX_WIN_BEGIN: + ret = xran_reg_sym_cb_rx_win_begin(p_dev_ctx, symCb, symCbParam, symCbTime, symb, &p_sym_cb_ctx); + if(ret != XRAN_STATUS_SUCCESS) + return ret; + dpdk_cb_to_arm = rx_ul_user_sym_cb; + break; + case XRAN_CB_SYM_RX_WIN_END: + ret = xran_reg_sym_cb_rx_win_end(p_dev_ctx, symCb, symCbParam, symCbTime, symb, &p_sym_cb_ctx); + if(ret != XRAN_STATUS_SUCCESS) + return ret; + dpdk_cb_to_arm = rx_ul_user_sym_cb; + break; + case XRAN_CB_SYM_TX_WIN_BEGIN: + ret = xran_reg_sym_cb_tx_win_begin(p_dev_ctx, symCb, symCbParam, symCbTime, symb, &p_sym_cb_ctx); + if(ret != XRAN_STATUS_SUCCESS) + return ret; + dpdk_cb_to_arm = rx_ul_user_sym_cb; + break; + case XRAN_CB_SYM_TX_WIN_END: + ret = xran_reg_sym_cb_tx_win_end(p_dev_ctx, symCb, symCbParam, symCbTime, symb, &p_sym_cb_ctx); + if(ret != XRAN_STATUS_SUCCESS) + return ret; + dpdk_cb_to_arm = rx_ul_user_sym_cb; + break; + default: + /* functionality is not yet implemented */ + print_err("Functionality is not yet implemented !"); + ret = XRAN_STATUS_INVALID_PARAM; + return ret; + } + + cb_elm = xran_create_cb(xran_timer_arm_user_cb, dpdk_cb_to_arm, (void*)p_sym_cb_ctx); + if(cb_elm){ + LIST_INSERT_HEAD(&p_dev_ctx->sym_cb_list_head[p_sym_cb_ctx->symb_num_ota], + cb_elm, + pointers); + } else { + print_err("cb_elm is NULL\n"); + ret = XRAN_STATUS_FAIL; + return ret; + } + + return ret; +} + +int32_t +xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id id) +{ + struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + + if(xran_get_if_state() == XRAN_RUNNING) { + print_err("Cannot register callback while running!!\n"); + return (-1); + } + + p_xran_dev_ctx->ttiCb[id] = Cb; + p_xran_dev_ctx->TtiCbParam[id] = cbParam; + p_xran_dev_ctx->SkipTti[id] = skipTtiNum; + + return 0; +} + + + + diff --git a/fhi_lib/lib/src/xran_cb_proc.h b/fhi_lib/lib/src/xran_cb_proc.h new file mode 100644 index 0000000..fb253ad --- /dev/null +++ b/fhi_lib/lib/src/xran_cb_proc.h @@ -0,0 +1,49 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN Callback processing module header file + * @file xran_cb_proc.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_CB_PROC_H_ +#define _XRAN_CB_PROC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +int32_t xran_timing_create_cbs(void *args); +int32_t xran_timing_destroy_cbs(void *args); + +void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore); +void xran_timer_arm(struct rte_timer *tim, void* arg, void* p_dev_ctx); +void xran_timer_arm_cp_dl(struct rte_timer *tim, void* arg, void* p_dev_ctx); +void xran_timer_arm_cp_ul(struct rte_timer *tim, void* arg, void* p_dev_ctx); +void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore); + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_CB_PROC_H_ */ diff --git a/fhi_lib/lib/src/xran_common.c b/fhi_lib/lib/src/xran_common.c index c4cb3fb..baa673f 100644 --- a/fhi_lib/lib/src/xran_common.c +++ b/fhi_lib/lib/src/xran_common.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -24,30 +24,34 @@ * @author Intel Corporation **/ +#define _GNU_SOURCE #include #include #include #include #include +#include +#include +#include #include "xran_common.h" #include "ethdi.h" #include "xran_pkt.h" #include "xran_pkt_up.h" +#include "xran_cp_api.h" #include "xran_up_api.h" +#include "xran_cp_proc.h" +#include "xran_dev.h" #include "xran_lib_mlog_tasks_id.h" -#include "../src/xran_printf.h" -#include +#include "xran_printf.h" #include "xran_mlog_lnx.h" static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */ #define MBUFS_CNT 16 -extern long interval_us; - -extern int xran_process_rx_sym(void *arg, +extern int32_t xran_process_rx_sym(void *arg, struct rte_mbuf *mbuf, void *iq_data_start, uint16_t size, @@ -62,7 +66,10 @@ extern int xran_process_rx_sym(void *arg, uint16_t sym_inc, uint16_t rb, uint16_t sect_id, - uint32_t *mb_free); + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth); extern int xran_process_prach_sym(void *arg, @@ -97,7 +104,10 @@ extern int32_t xran_process_srs_sym(void *arg, uint16_t sym_inc, uint16_t rb, uint16_t sect_id, - uint32_t *mb_free); + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth); extern int32_t xran_pkt_validate(void *arg, struct rte_mbuf *mbuf, @@ -109,43 +119,523 @@ extern int32_t xran_pkt_validate(void *arg, uint8_t subframe_id, uint8_t slot_id, uint8_t symb_id, - struct ecpri_seq_id *seq_id, + union ecpri_seq_id *seq_id, uint16_t num_prbu, uint16_t start_prbu, uint16_t sym_inc, uint16_t rb, uint16_t sect_id); +int process_mbuf_batch(struct rte_mbuf* pkt_q[], void* handle, int16_t num, struct xran_eaxc_info *p_cid, uint32_t* ret_data) +{ + struct rte_mbuf* pkt; + struct xran_device_ctx* p_dev_ctx = (struct xran_device_ctx*)handle; + void* iq_samp_buf[MBUFS_CNT]; + union ecpri_seq_id seq[MBUFS_CNT]; + static int symbol_total_bytes[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR] = { 0 }; + int num_bytes[MBUFS_CNT] = { 0 }, num_bytes_pusch[MBUFS_CNT] = { 0 }; + int16_t i, j; + + struct xran_common_counters* pCnt = &p_dev_ctx->fh_counters; + + uint8_t CC_ID[MBUFS_CNT] = { 0 }; + uint8_t Ant_ID[MBUFS_CNT] = { 0 }; + uint8_t frame_id[MBUFS_CNT] = { 0 }; + uint8_t subframe_id[MBUFS_CNT] = { 0 }; + uint8_t slot_id[MBUFS_CNT] = { 0 }; + uint8_t symb_id[MBUFS_CNT] = { 0 }; + + uint16_t num_prbu[MBUFS_CNT]; + uint16_t start_prbu[MBUFS_CNT]; + uint16_t sym_inc[MBUFS_CNT]; + uint16_t rb[MBUFS_CNT]; + uint16_t sect_id[MBUFS_CNT]; + + uint8_t compMeth[MBUFS_CNT] = { 0 }; + uint8_t iqWidth[MBUFS_CNT] = { 0 }; + uint8_t compMeth_ini = 0; + uint8_t iqWidth_ini = 0; + + uint32_t pkt_size[MBUFS_CNT]; + + void* pHandle = NULL; + int32_t valid_res, res_loc; + int expect_comp = (p_dev_ctx->fh_cfg.ru_conf.compMeth != XRAN_COMPMETHOD_NONE); + enum xran_comp_hdr_type staticComp = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + int16_t num_pusch = 0, num_prach = 0, num_srs = 0; + int16_t pusch_idx[MBUFS_CNT] = { 0 }, prach_idx[MBUFS_CNT] = { 0 }, srs_idx[MBUFS_CNT] = { 0 }; + int8_t xran_port = xran_dev_ctx_get_port_id(p_dev_ctx); + int16_t max_ant_num = 0; + uint8_t *ptr_seq_id_num_port; + struct xran_eaxcid_config* conf; + uint8_t seq_id[MBUFS_CNT]; + uint16_t cid[MBUFS_CNT]; + + struct xran_ecpri_hdr* ecpri_hdr[MBUFS_CNT]; + struct radio_app_common_hdr* radio_hdr[MBUFS_CNT]; + struct data_section_hdr* data_hdr[MBUFS_CNT]; + struct data_section_compression_hdr* data_compr_hdr[MBUFS_CNT]; + + const int16_t ecpri_size = sizeof(struct xran_ecpri_hdr); + const int16_t rad_size = sizeof(struct radio_app_common_hdr); + const int16_t data_size = sizeof(struct data_section_hdr); + const int16_t compr_size = sizeof(struct data_section_compression_hdr); + + char* buf_start[MBUFS_CNT]; + uint16_t start_off[MBUFS_CNT]; + uint16_t iq_offset[MBUFS_CNT]; + uint16_t last[MBUFS_CNT]; + + uint32_t tti = 0; + struct rte_mbuf* mb = NULL; + struct xran_prb_map* pRbMap = NULL; + struct xran_prb_elm* prbMapElm = NULL; + uint16_t iq_sample_size_bits; + +#if XRAN_MLOG_VAR + uint32_t mlogVar[10]; + uint32_t mlogVarCnt = 0; +#endif + + if (xran_port < 0) { + print_err("Invalid pHandle - %p", pHandle); + return MBUF_FREE; + } -struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data) + if (xran_port > XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return MBUF_FREE; + } + + conf = &(p_dev_ctx->eAxc_id_cfg); + if (conf == NULL) { + rte_panic("conf == NULL"); + } + + if (p_dev_ctx->fh_init.io_cfg.id == O_DU) + { + max_ant_num = XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR; + ptr_seq_id_num_port = &xran_upul_seq_id_num[xran_port][0][0]; + } + else if (p_dev_ctx->fh_init.io_cfg.id == O_RU) + { + max_ant_num = XRAN_MAX_ANTENNA_NR; + ptr_seq_id_num_port = &xran_updl_seq_id_num[xran_port][0][0]; + } + else { - struct cb_elem_entry * cb_elm = (struct cb_elem_entry *)malloc(sizeof(struct cb_elem_entry)); - if(cb_elm){ - cb_elm->pSymCallback = cb_fn; - cb_elm->pSymCallbackTag = cb_data; + rte_panic("incorrect fh_init.io_cfg.id"); } - return cb_elm; + if (staticComp == XRAN_COMP_HDR_TYPE_STATIC) + { + compMeth_ini = p_dev_ctx->fh_cfg.ru_conf.compMeth; + iqWidth_ini = p_dev_ctx->fh_cfg.ru_conf.iqWidth; } -int xran_destroy_cb(struct cb_elem_entry * cb_elm) + for (i = 0; i < MBUFS_CNT; i++) { - if(cb_elm) - free(cb_elm); - return 0; + pkt_size[i] = pkt_q[i]->pkt_len; + buf_start[i] = (char*)pkt_q[i]->buf_addr; + start_off[i] = pkt_q[i]->data_off; +} + + if (expect_comp && (staticComp != XRAN_COMP_HDR_TYPE_STATIC)) + { +#pragma vector always + for (i = 0; i < MBUFS_CNT; i++) + { +#if XRAN_MLOG_VAR + mlogVarCnt = 0; +#endif + ecpri_hdr[i] = (void*)(buf_start[i] + start_off[i]); + radio_hdr[i] = (void*)(buf_start[i] + start_off[i] + ecpri_size); + data_hdr[i] = (void*)(buf_start[i] + start_off[i] + ecpri_size + rad_size); + data_compr_hdr[i] = (void*)(buf_start[i] + start_off[i] + ecpri_size + rad_size + data_size); + seq[i] = ecpri_hdr[i]->ecpri_seq_id; + seq_id[i] = seq[i].bits.seq_id; + last[i] = seq[i].bits.e_bit; + + iq_offset[i] = ecpri_size + rad_size + data_size + compr_size; + + iq_samp_buf[i] = (void*)(buf_start[i] + start_off[i] + iq_offset[i]); + num_bytes[i] = pkt_size[i] - iq_offset[i]; + + if (ecpri_hdr[i] == NULL || + radio_hdr[i] == NULL || + data_hdr[i] == NULL || + data_compr_hdr[i] == NULL || + iq_samp_buf[i] == NULL) + { + num_bytes[i] = 0; /* packet too short */ + } + +#if XRAN_MLOG_VAR + if(radio_hdr[i] != NULL && data_hdr[i] != NULL) + { + mlogVar[mlogVarCnt++] = 0xBBBBBBBB; + mlogVar[mlogVarCnt++] = xran_lib_ota_tti; + mlogVar[mlogVarCnt++] = radio_hdr[i]->frame_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.subframe_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.slot_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.symb_id; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.sect_id; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.start_prbu; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.num_prbu; + mlogVar[mlogVarCnt++] = rte_pktmbuf_pkt_len(pkt_q[i]); + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + } +#endif + } + } + else + { +#pragma vector always + for (i = 0; i < MBUFS_CNT; i++) + { +#if XRAN_MLOG_VAR + mlogVarCnt = 0; +#endif + ecpri_hdr[i] = (void*)(buf_start[i] + start_off[i]); + radio_hdr[i] = (void*)(buf_start[i] + start_off[i] + ecpri_size); + data_hdr[i] = (void*)(buf_start[i] + start_off[i] + ecpri_size + rad_size); + seq[i] = ecpri_hdr[i]->ecpri_seq_id; + seq_id[i] = seq[i].bits.seq_id; + last[i] = seq[i].bits.e_bit; + + iq_offset[i] = ecpri_size + rad_size + data_size; + iq_samp_buf[i] = (void*)(buf_start[i] + start_off[i] + iq_offset[i]); + num_bytes[i] = pkt_size[i] - iq_offset[i]; + + if (ecpri_hdr[i] == NULL || + radio_hdr[i] == NULL || + data_hdr[i] == NULL || + iq_samp_buf[i] == NULL) + { + num_bytes[i] = 0; /* packet too short */ + } + +#if XRAN_MLOG_VAR + if (radio_hdr[i] != NULL && data_hdr[i] != NULL) + { + mlogVar[mlogVarCnt++] = 0xBBBBBBBB; + mlogVar[mlogVarCnt++] = xran_lib_ota_tti; + mlogVar[mlogVarCnt++] = radio_hdr[i]->frame_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.subframe_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.slot_id; + mlogVar[mlogVarCnt++] = radio_hdr[i]->sf_slot_sym.symb_id; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.sect_id; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.start_prbu; + mlogVar[mlogVarCnt++] = data_hdr[i]->fields.num_prbu; + mlogVar[mlogVarCnt++] = rte_pktmbuf_pkt_len(pkt_q[i]); + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + } +#endif + } + } + + for (i = 0; i < MBUFS_CNT; i++) { + if(p_cid->ccId == 0xFF && p_cid->ruPortId == 0xFF) { + cid[i] = rte_be_to_cpu_16((uint16_t)ecpri_hdr[i]->ecpri_xtc_id); + if (num_bytes[i] > 0) { + CC_ID[i] = (cid[i] & conf->mask_ccId) >> conf->bit_ccId; + Ant_ID[i] = (cid[i] & conf->mask_ruPortId) >> conf->bit_ruPortId; + } + } else { + if (num_bytes[i] > 0) { + CC_ID[i] = p_cid->ccId; + Ant_ID[i] = p_cid->ruPortId; + } + } + } + + for (i = 0; i < MBUFS_CNT; i++) + { + radio_hdr[i]->sf_slot_sym.value = rte_be_to_cpu_16(radio_hdr[i]->sf_slot_sym.value); + data_hdr[i]->fields.all_bits = rte_be_to_cpu_32(data_hdr[i]->fields.all_bits); + } + + for (i = 0; i < MBUFS_CNT; i++) + { + if (num_bytes[i] > 0) + { + compMeth[i] = compMeth_ini; + iqWidth[i] = iqWidth_ini; + valid_res = XRAN_STATUS_SUCCESS; + + frame_id[i] = radio_hdr[i]->frame_id; + subframe_id[i] = radio_hdr[i]->sf_slot_sym.subframe_id; + slot_id[i] = radio_hdr[i]->sf_slot_sym.slot_id; + symb_id[i] = radio_hdr[i]->sf_slot_sym.symb_id; + + num_prbu[i] = data_hdr[i]->fields.num_prbu; + start_prbu[i] = data_hdr[i]->fields.start_prbu; + sym_inc[i] = data_hdr[i]->fields.sym_inc; + rb[i] = data_hdr[i]->fields.rb; + sect_id[i] = data_hdr[i]->fields.sect_id; + + if (expect_comp && (staticComp != XRAN_COMP_HDR_TYPE_STATIC)) + { + compMeth[i] = data_compr_hdr[i]->ud_comp_hdr.ud_comp_meth; + iqWidth[i] = data_compr_hdr[i]->ud_comp_hdr.ud_iq_width; + } + + if (CC_ID[i] >= XRAN_MAX_CELLS_PER_PORT || Ant_ID[i] >= max_ant_num || symb_id[i] >= XRAN_NUM_OF_SYMBOL_PER_SLOT) + { + ptr_seq_id_num_port[CC_ID[i] * max_ant_num + Ant_ID[i]] = seq_id[i]; // for next + valid_res = XRAN_STATUS_FAIL; + pCnt->Rx_pkt_dupl++; +// print_err("Invalid CC ID - %d or antenna ID or Symbol ID- %d", CC_ID[i], Ant_ID[i], symb_id[i]); + } + else + { + ptr_seq_id_num_port[CC_ID[i] * max_ant_num + Ant_ID[i]]++; + } + + pCnt->rx_counter++; + pCnt->Rx_on_time++; + pCnt->Total_msgs_rcvd++; + + if (Ant_ID[i] >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable) + { + Ant_ID[i] -= p_dev_ctx->srs_cfg.eAxC_offset; + if (last[i] == 1) + { + srs_idx[num_srs] = i; + num_srs += 1; + pCnt->rx_srs_packets++; + } + } + else if (Ant_ID[i] >= p_dev_ctx->PrachCPConfig.eAxC_offset && p_dev_ctx->fh_cfg.prachEnable) + { + Ant_ID[i] -= p_dev_ctx->PrachCPConfig.eAxC_offset; + if (last[i] == 1) + { + prach_idx[num_prach] = i; + num_prach += 1; + pCnt->rx_prach_packets[Ant_ID[i]]++; + } + } + else + { + if (last[i] == 1) + { + pusch_idx[num_pusch] = i; + num_pusch += 1; + pCnt->rx_pusch_packets[Ant_ID[i]]++; + } + } + symbol_total_bytes[xran_port][CC_ID[i]][Ant_ID[i]] += num_bytes[i]; + num_bytes_pusch[i] = symbol_total_bytes[xran_port][CC_ID[i]][Ant_ID[i]]; + if (last[i] == 1) + symbol_total_bytes[xran_port][CC_ID[i]][Ant_ID[i]] = 0; + } + } + + for (j = 0; j < num_prach; j++) + { + i = prach_idx[j]; + pkt = pkt_q[i]; + + print_dbg("Completed receiving PRACH symbol %d, size=%d bytes\n", symb_id[i], num_bytes[i]); + + int16_t res = xran_process_prach_sym(p_dev_ctx, + pkt, + iq_samp_buf[i], + num_bytes[i], + CC_ID[i], + Ant_ID[i], + frame_id[i], + subframe_id[i], + slot_id[i], + symb_id[i], + num_prbu[i], + start_prbu[i], + sym_inc[i], + rb[i], + sect_id[i], + &ret_data[i]); + } + + for (j = 0; j < num_srs; j++) + { + i = srs_idx[j]; + pkt = pkt_q[i]; + + print_dbg("SRS receiving symbol %d, size=%d bytes\n", + symb_id[i], symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID[i]][Ant_ID[i]]); + + uint64_t t1 = MLogTick(); + int16_t res = xran_process_srs_sym(p_dev_ctx, + pkt, + iq_samp_buf[i], + num_bytes[i], + CC_ID[i], + Ant_ID[i], + frame_id[i], + subframe_id[i], + slot_id[i], + symb_id[i], + num_prbu[i], + start_prbu[i], + sym_inc[i], + rb[i], + sect_id[i], + &ret_data[i], + expect_comp, + compMeth[i], + iqWidth[i]); + MLogTask(PID_PROCESS_UP_PKT_SRS, t1, MLogTick()); + } + + if (num_pusch == MBUFS_CNT) + { + for (i = 0; i < MBUFS_CNT; i++) + { + iq_sample_size_bits = 16; + if (expect_comp) + iq_sample_size_bits = iqWidth[i]; + + tti = frame_id[i] * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) + + subframe_id[i] * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id[i]; + + pRbMap = (struct xran_prb_map*)p_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers->pData; + + if (pRbMap) + { + prbMapElm = &pRbMap->prbMap[sect_id[i]]; + if (sect_id[i] >= pRbMap->nPrbElm) + { +// print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], pRbMap->nPrbElm); + ret_data[i] = MBUF_FREE; + continue; + } + } + else + { +// print_err("pRbMap==NULL\n"); + ret_data[i] = MBUF_FREE; + continue; + } + + if (pRbMap->nPrbElm == 1) + { + p_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers[symb_id[i]].pData = iq_samp_buf[i]; + p_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers[symb_id[i]].pCtrl = pkt_q[i]; + ret_data[i] = MBUF_KEEP; + } + else + { + struct xran_section_desc* p_sec_desc = NULL; + prbMapElm = &pRbMap->prbMap[sect_id[i]]; + p_sec_desc = prbMapElm->p_sec_desc[symb_id[i]][0]; + + if (p_sec_desc) + { + mb = p_sec_desc->pCtrl; + if (mb) { + rte_pktmbuf_free(mb); + } + p_sec_desc->pCtrl = pkt_q[i]; + p_sec_desc->pData = iq_samp_buf[i]; + p_sec_desc->start_prbu = start_prbu[i]; + p_sec_desc->num_prbu = num_prbu[i]; + p_sec_desc->iq_buffer_len = num_bytes_pusch[i]; + p_sec_desc->iq_buffer_offset = iq_offset[i]; + ret_data[i] = MBUF_KEEP; + } + else +{ +// print_err("p_sec_desc==NULL tti %u ant %d symb_id %d\n", tti, Ant_ID[i], symb_id[i]); + ret_data[i] = MBUF_FREE; + } + } + } + } + else + { + for (j = 0; j < num_pusch; j++) + { + i = pusch_idx[j]; + + iq_sample_size_bits = 16; + if (expect_comp) + iq_sample_size_bits = iqWidth[i]; + + tti = frame_id[i] * SLOTS_PER_SYSTEMFRAME(p_dev_ctx->interval_us_local) + + subframe_id[i] * SLOTNUM_PER_SUBFRAME(p_dev_ctx->interval_us_local) + slot_id[i]; + + pRbMap = (struct xran_prb_map*)p_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers->pData; + + if (pRbMap) + { + prbMapElm = &pRbMap->prbMap[sect_id[i]]; + if (sect_id[i] >= pRbMap->nPrbElm) + { +// print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], pRbMap->nPrbElm); + ret_data[i] = MBUF_FREE; + continue; + } + } + else + { +// print_err("pRbMap==NULL\n"); + ret_data[i] = MBUF_FREE; + continue; + } + + if (pRbMap->nPrbElm == 1) + { + p_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers[symb_id[i]].pData = iq_samp_buf[i]; + p_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID[i]][Ant_ID[i]].sBufferList.pBuffers[symb_id[i]].pCtrl = pkt_q[i]; + ret_data[i] = MBUF_KEEP; + } + else + { + struct xran_section_desc* p_sec_desc = NULL; + prbMapElm = &pRbMap->prbMap[sect_id[i]]; + p_sec_desc = prbMapElm->p_sec_desc[symb_id[i]][0]; + + if (p_sec_desc) + { + mb = p_sec_desc->pCtrl; + if (mb) { + rte_pktmbuf_free(mb); + } + p_sec_desc->pCtrl = pkt_q[i]; + p_sec_desc->pData = iq_samp_buf[i]; + p_sec_desc->start_prbu = start_prbu[i]; + p_sec_desc->num_prbu = num_prbu[i]; + p_sec_desc->iq_buffer_len = num_bytes_pusch[i]; + p_sec_desc->iq_buffer_offset = iq_offset[i]; + ret_data[i] = MBUF_KEEP; + } + else + { +// print_err("p_sec_desc==NULL tti %u ant %d symb_id %d\n", tti, Ant_ID[i], symb_id[i]); + ret_data[i] = MBUF_FREE; + } + } + } + } + return MBUF_FREE; } -int process_mbuf(struct rte_mbuf *pkt) +int +process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid) { + uint64_t tt1 = MLogTick(); + struct xran_device_ctx *p_dev_ctx = (struct xran_device_ctx *)handle; void *iq_samp_buf; - struct ecpri_seq_id seq; - static int symbol_total_bytes = 0; + union ecpri_seq_id seq; + static int symbol_total_bytes[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR] = {0}; int num_bytes = 0; - struct xran_device_ctx * p_x_ctx = xran_dev_get_ctx(); - struct xran_common_counters *pCnt = &p_x_ctx->fh_counters; - uint8_t CC_ID = 0; - uint8_t Ant_ID = 0; + struct xran_common_counters *pCnt = &p_dev_ctx->fh_counters; + + uint8_t CC_ID = p_cid->ccId; + uint8_t Ant_ID = p_cid->ruPortId; uint8_t frame_id = 0; uint8_t subframe_id = 0; uint8_t slot_id = 0; @@ -164,10 +654,16 @@ int process_mbuf(struct rte_mbuf *pkt) int ret = MBUF_FREE; uint32_t mb_free = 0; int32_t valid_res = 0; - int expect_comp = (p_x_ctx->fh_cfg.ru_conf.compMeth != XRAN_COMPMETHOD_NONE); + int expect_comp = (p_dev_ctx->fh_cfg.ru_conf.compMeth != XRAN_COMPMETHOD_NONE); + enum xran_comp_hdr_type staticComp = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + if (staticComp == XRAN_COMP_HDR_TYPE_STATIC) + { + compMeth = p_dev_ctx->fh_cfg.ru_conf.compMeth; + iqWidth = p_dev_ctx->fh_cfg.ru_conf.iqWidth; + } - if(p_x_ctx->xran2phy_mem_ready == 0) + if(p_dev_ctx->xran2phy_mem_ready == 0) return MBUF_FREE; num_bytes = xran_extract_iq_samples(pkt, @@ -185,6 +681,7 @@ int process_mbuf(struct rte_mbuf *pkt) &rb, §_id, expect_comp, + staticComp, &compMeth, &iqWidth); if (num_bytes <= 0){ @@ -192,7 +689,7 @@ int process_mbuf(struct rte_mbuf *pkt) return MBUF_FREE; } - valid_res = xran_pkt_validate(NULL, + valid_res = xran_pkt_validate(p_dev_ctx, pkt, iq_samp_buf, num_bytes, @@ -208,23 +705,25 @@ int process_mbuf(struct rte_mbuf *pkt) sym_inc, rb, sect_id); - +#ifndef FCN_ADAPT if(valid_res != 0) { print_dbg("valid_res is wrong [%d] ant %u (%u : %u : %u : %u) seq %u num_bytes %d\n", valid_res, Ant_ID, frame_id, subframe_id, slot_id, symb_id, seq.seq_id, num_bytes); return MBUF_FREE; } - - if (Ant_ID >= p_x_ctx->srs_cfg.eAxC_offset && p_x_ctx->fh_init.srsEnable) { +#endif + MLogTask(PID_PROCESS_UP_PKT_PARSE, tt1, MLogTick()); + if (Ant_ID >= p_dev_ctx->srs_cfg.eAxC_offset && p_dev_ctx->fh_cfg.srsEnable) { /* SRS packet has ruportid = 2*num_eAxc + ant_id */ - Ant_ID -= p_x_ctx->srs_cfg.eAxC_offset; - symbol_total_bytes += num_bytes; + Ant_ID -= p_dev_ctx->srs_cfg.eAxC_offset; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes; - if (seq.e_bit == 1) { + if (seq.bits.e_bit == 1) { print_dbg("SRS receiving symbol %d, size=%d bytes\n", - symb_id, symbol_total_bytes); + symb_id, symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]); - if (symbol_total_bytes) { - int16_t res = xran_process_srs_sym(NULL, + if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { + uint64_t t1 = MLogTick(); + int16_t res = xran_process_srs_sym(p_dev_ctx, pkt, iq_samp_buf, num_bytes, @@ -239,31 +738,34 @@ int process_mbuf(struct rte_mbuf *pkt) sym_inc, rb, sect_id, - &mb_free); - - if(res == symbol_total_bytes) { + &mb_free, + expect_comp, + compMeth, + iqWidth); + if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { ret = mb_free; } else { - print_err("res != symbol_total_bytes\n"); + print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n"); } pCnt->rx_srs_packets++; + MLogTask(PID_PROCESS_UP_PKT_SRS, t1, MLogTick()); } - symbol_total_bytes = 0; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0; } else { print_dbg("Transport layer fragmentation (eCPRI) is not supported\n"); } - } else if (Ant_ID >= p_x_ctx->PrachCPConfig.eAxC_offset && p_x_ctx->fh_init.prachEnable) { + } else if (Ant_ID >= p_dev_ctx->PrachCPConfig.eAxC_offset && p_dev_ctx->fh_cfg.prachEnable) { /* PRACH packet has ruportid = num_eAxc + ant_id */ - Ant_ID -= p_x_ctx->PrachCPConfig.eAxC_offset; - symbol_total_bytes += num_bytes; - if (seq.e_bit == 1) { + Ant_ID -= p_dev_ctx->PrachCPConfig.eAxC_offset; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes; + if (seq.bits.e_bit == 1) { print_dbg("Completed receiving PRACH symbol %d, size=%d bytes\n", symb_id, num_bytes); - if (symbol_total_bytes) { - int16_t res = xran_process_prach_sym(NULL, + if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { + int16_t res = xran_process_prach_sym(p_dev_ctx, pkt, iq_samp_buf, num_bytes, @@ -279,30 +781,31 @@ int process_mbuf(struct rte_mbuf *pkt) rb, sect_id, &mb_free); - if(res == symbol_total_bytes) { + if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { ret = mb_free; } else { - print_err("res != symbol_total_bytes\n"); + print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n"); } pCnt->rx_prach_packets[Ant_ID]++; } - symbol_total_bytes = 0; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0; } else { print_dbg("Transport layer fragmentation (eCPRI) is not supported\n"); } } else { /* PUSCH */ - symbol_total_bytes += num_bytes; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes; - if (seq.e_bit == 1) { + if (seq.bits.e_bit == 1) { print_dbg("Completed receiving symbol %d, size=%d bytes\n", - symb_id, symbol_total_bytes); + symb_id, symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]); - if (symbol_total_bytes) { - int res = xran_process_rx_sym(NULL, + if (symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { + uint64_t t1 = MLogTick(); + int res = xran_process_rx_sym(p_dev_ctx, pkt, iq_samp_buf, - symbol_total_bytes, + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID], CC_ID, Ant_ID, frame_id, @@ -314,15 +817,19 @@ int process_mbuf(struct rte_mbuf *pkt) sym_inc, rb, sect_id, - &mb_free); - if(res == symbol_total_bytes) { + &mb_free, + expect_comp, + compMeth, + iqWidth); + if(res == symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]) { ret = mb_free; } else { - print_err("res != symbol_total_bytes\n"); + print_err("res != symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID]\n"); } pCnt->rx_pusch_packets[Ant_ID]++; + MLogTask(PID_PROCESS_UP_PKT, t1, MLogTick()); } - symbol_total_bytes = 0; + symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] = 0; } else { print_dbg("Transport layer fragmentation (eCPRI) is not supported\n"); } @@ -343,10 +850,10 @@ static int set_iq_bit_width(uint8_t iq_bit_width, struct data_section_compressio } /* Send a single 5G symbol over multiple packets */ -int32_t prepare_symbol_ex(enum xran_pkt_dir direction, +inline int32_t prepare_symbol_ex(enum xran_pkt_dir direction, uint16_t section_id, struct rte_mbuf *mb, - struct rb_map *data, + uint8_t *data, uint8_t compMeth, uint8_t iqWidth, const enum xran_input_byte_order iq_buf_byte_order, @@ -359,28 +866,40 @@ int32_t prepare_symbol_ex(enum xran_pkt_dir direction, uint8_t CC_ID, uint8_t RU_Port_ID, uint8_t seq_id, - uint32_t do_copy) + uint32_t do_copy, + enum xran_comp_hdr_type staticEn) { - int32_t n_bytes = ((prb_num == 0) ? MAX_N_FULLBAND_SC : prb_num) * N_SC_PER_PRB * sizeof(struct rb_map); - - n_bytes = ((iqWidth == 0) || (iqWidth == 16)) ? n_bytes : ((3 * iqWidth + 1 ) * prb_num); - + int32_t n_bytes; int32_t prep_bytes; - - int16_t nPktSize = sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr) + - sizeof(struct radio_app_common_hdr)+ sizeof(struct data_section_hdr) + n_bytes; + int16_t nPktSize; uint32_t off; + int parm_size; struct xran_up_pkt_gen_params xp = { 0 }; - if(compMeth != XRAN_COMPMETHOD_NONE) - nPktSize += sizeof(struct data_section_compression_hdr); + iqWidth = (iqWidth==0) ? 16 : iqWidth; + switch(compMeth) { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + n_bytes = (3 * iqWidth + parm_size) * prb_num; n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN); + nPktSize = sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + + n_bytes; + if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) + nPktSize += sizeof(struct data_section_compression_hdr); + /* radio app header */ - xp.app_params.data_direction = direction; - xp.app_params.payl_ver = 1; - xp.app_params.filter_id = 0; + xp.app_params.data_feature.value = 0x10; + xp.app_params.data_feature.data_direction = direction; + //xp.app_params.payl_ver = 1; + //xp.app_params.filter_id = 0; xp.app_params.frame_id = frame_id; xp.app_params.sf_slot_sym.subframe_id = subframe_id; xp.app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0); @@ -389,19 +908,16 @@ int32_t prepare_symbol_ex(enum xran_pkt_dir direction, /* convert to network byte order */ xp.app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp.app_params.sf_slot_sym.value); + xp.sec_hdr.fields.all_bits = 0; xp.sec_hdr.fields.sect_id = section_id; xp.sec_hdr.fields.num_prbu = (uint8_t)prb_num; xp.sec_hdr.fields.start_prbu = (uint8_t)prb_start; - xp.sec_hdr.fields.sym_inc = 0; - xp.sec_hdr.fields.rb = 0; -#ifdef FCN_ADAPT - xp.sec_hdr.udCompHdr = 0; - xp.sec_hdr.reserved = 0; -#endif + //xp.sec_hdr.fields.sym_inc = 0; + //xp.sec_hdr.fields.rb = 0; /* compression */ xp.compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth; - xp.compr_hdr_param.ud_comp_hdr.ud_iq_width = iqWidth; + xp.compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth); xp.compr_hdr_param.rsrvd = 0; /* network byte order */ @@ -420,6 +936,7 @@ int32_t prepare_symbol_ex(enum xran_pkt_dir direction, CC_ID, RU_Port_ID, seq_id, + staticEn, do_copy); if (prep_bytes <= 0) errx(1, "failed preparing symbol"); @@ -434,27 +951,70 @@ int32_t prepare_symbol_ex(enum xran_pkt_dir direction, return prep_bytes; } -/* Send a single 5G symbol over multiple packets */ -int send_symbol_ex(enum xran_pkt_dir direction, - uint16_t section_id, - struct rte_mbuf *mb, - struct rb_map *data, - const enum xran_input_byte_order iq_buf_byte_order, +int32_t prepare_sf_slot_sym (enum xran_pkt_dir direction, uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id, uint8_t symbol_no, - int prb_start, - int prb_num, - uint8_t CC_ID, - uint8_t RU_Port_ID, - uint8_t seq_id) + struct xran_up_pkt_gen_params *xp) +{ + /* radio app header */ + xp->app_params.data_feature.value = 0x10; + xp->app_params.data_feature.data_direction = direction; + //xp->app_params.payl_ver = 1; + //xp->app_params.filter_id = 0; + xp->app_params.frame_id = frame_id; + xp->app_params.sf_slot_sym.subframe_id = subframe_id; + xp->app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0); + xp->app_params.sf_slot_sym.symb_id = symbol_no; + + /* convert to network byte order */ + xp->app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp->app_params.sf_slot_sym.value); + + return 0; +} + + + + +/* Send a single 5G symbol over multiple packets */ +int send_symbol_ex(void *handle, + enum xran_pkt_dir direction, + uint16_t section_id, + struct rte_mbuf *mb, uint8_t *data, + uint8_t compMeth, uint8_t iqWidth, + const enum xran_input_byte_order iq_buf_byte_order, + uint8_t frame_id, uint8_t subframe_id, + uint8_t slot_id, uint8_t symbol_no, + int prb_start, int prb_num, + uint8_t CC_ID, uint8_t RU_Port_ID, uint8_t seq_id) { uint32_t do_copy = 0; - int32_t n_bytes = ((prb_num == 0) ? MAX_N_FULLBAND_SC : prb_num) * N_SC_PER_PRB * sizeof(struct rb_map); - struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx(); - struct xran_common_counters *pCnt = &p_x_ctx->fh_counters; + int32_t n_bytes; + int hdr_len, parm_size; + int32_t sent=0; + struct xran_device_ctx *p_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_common_counters *pCnt = &p_dev_ctx->fh_counters; + enum xran_comp_hdr_type staticEn= XRAN_COMP_HDR_TYPE_DYNAMIC; + + if (p_dev_ctx != NULL) + { + staticEn = p_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + hdr_len = sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr); + if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) + hdr_len += sizeof(struct data_section_compression_hdr); + + switch(compMeth) { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + n_bytes = (3 * iqWidth + parm_size) * prb_num; if (mb == NULL){ char * pChar = NULL; @@ -463,7 +1023,7 @@ int send_symbol_ex(enum xran_pkt_dir direction, MLogPrint(NULL); errx(1, "out of mbufs after %d packets", 1); } - pChar = rte_pktmbuf_append(mb, sizeof(struct xran_ecpri_hdr)+ sizeof(struct radio_app_common_hdr)+ sizeof(struct data_section_hdr) + n_bytes); + pChar = rte_pktmbuf_append(mb, hdr_len + n_bytes); if(pChar == NULL){ MLogPrint(NULL); errx(1, "incorrect mbuf size %d packets", 1); @@ -474,16 +1034,17 @@ int send_symbol_ex(enum xran_pkt_dir direction, errx(1, "incorrect mbuf size %d packets", 1); } do_copy = 1; /* new mbuf hence copy of IQs */ - }else { + } + else { rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */ } - int32_t sent = prepare_symbol_ex(direction, + sent = prepare_symbol_ex(direction, section_id, mb, data, - 0, - 16, + compMeth, + iqWidth, iq_buf_byte_order, frame_id, subframe_id, @@ -494,20 +1055,19 @@ int send_symbol_ex(enum xran_pkt_dir direction, CC_ID, RU_Port_ID, seq_id, - do_copy); + do_copy, + staticEn); if(sent){ pCnt->tx_counter++; pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mb); - p_x_ctx->send_upmbuf2ring(mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(direction, CC_ID, RU_Port_ID)); - } else { - + p_dev_ctx->send_upmbuf2ring(mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(p_dev_ctx, direction, CC_ID, RU_Port_ID)); } #ifdef DEBUG printf("Symbol %2d sent (%d packets, %d bytes)\n", symbol_no, i, n_bytes); #endif - + } return sent; } @@ -518,8 +1078,8 @@ int send_cpmsg(void *pHandle, struct rte_mbuf *mbuf,struct xran_cp_gen_params *p uint8_t subframe_id = params->hdr.subframeId; uint8_t slot_id = params->hdr.slotId; uint8_t dir = params->dir; - struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx(); - struct xran_common_counters *pCnt = &p_x_ctx->fh_counters; + struct xran_device_ctx *p_dev_ctx =(struct xran_device_ctx *) pHandle; + struct xran_common_counters *pCnt = &p_dev_ctx->fh_counters; nsection = params->numSections; @@ -528,10 +1088,10 @@ int send_cpmsg(void *pHandle, struct rte_mbuf *mbuf,struct xran_cp_gen_params *p pCnt->tx_counter++; pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf); - p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, xran_map_ecpriRtcid_to_vf(dir, cc_id, ru_port_id)); + p_dev_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, xran_map_ecpriRtcid_to_vf(p_dev_ctx, dir, cc_id, ru_port_id)); for(i=0; iinterval_us_local))%XRAN_MAX_SECTIONDB_CTX, §_geninfo[i].info); return (ret); @@ -599,12 +1159,13 @@ int generate_cpmsg_dlul(void *pHandle, struct xran_cp_gen_params *params, struct int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struct xran_section_gen_info *sect_geninfo, struct rte_mbuf *mbuf, struct xran_device_ctx *pxran_lib_ctx, uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id, - uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint8_t seq_id) + uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint16_t occasionid, uint8_t seq_id) { int nsection, ret; struct xran_prach_cp_config *pPrachCPConfig = &(pxran_lib_ctx->PrachCPConfig); uint16_t timeOffset; uint16_t nNumerology = pxran_lib_ctx->fh_cfg.frame_conf.nNumerology; + uint8_t startSymId; if(unlikely(mbuf == NULL)) { print_err("Alloc fail!\n"); @@ -622,22 +1183,24 @@ int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struc pPrachCPConfig->freqOffset); #endif timeOffset = pPrachCPConfig->timeOffset; //this is the CP value per 38.211 tab 6.3.3.1-1&2 - timeOffset = timeOffset >> nNumerology; //original number is Tc, convert to Ts based on mu - if (pPrachCPConfig->startSymId > 0) + startSymId = pPrachCPConfig->startSymId + occasionid * pPrachCPConfig->numSymbol; + if (startSymId > 0) { - timeOffset += (pPrachCPConfig->startSymId * 2048) >> nNumerology; - if ((slot_id == 0) || (slot_id == (SLOTNUM_PER_SUBFRAME >> 1))) - timeOffset += 16; + timeOffset += startSymId * (2048 + 144); } + timeOffset = timeOffset >> nNumerology; //original number is Tc, convert to Ts based on mu + if ((slot_id == 0) || (slot_id == (SLOTNUM_PER_SUBFRAME(pxran_lib_ctx->interval_us_local) >> 1))) + timeOffset += 16; + params->dir = XRAN_DIR_UL; params->sectionType = XRAN_CP_SECTIONTYPE_3; params->hdr.filterIdx = pPrachCPConfig->filterIdx; params->hdr.frameId = frame_id; params->hdr.subframeId = subframe_id; params->hdr.slotId = slot_id; - params->hdr.startSymId = pPrachCPConfig->startSymId; - params->hdr.iqWidth = xran_get_conf_iqwidth(pHandle); - params->hdr.compMeth = xran_get_conf_compmethod(pHandle); + params->hdr.startSymId = startSymId; + params->hdr.iqWidth = xran_get_conf_iqwidth_prach(pHandle); + params->hdr.compMeth = xran_get_conf_compmethod_prach(pHandle); /* use timeOffset field for the CP length value for prach sequence */ params->hdr.timeOffset = timeOffset; params->hdr.fftSize = xran_get_conf_fftsize(pHandle); @@ -654,12 +1217,12 @@ int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struc sect_geninfo[nsection].info.symInc = XRAN_SYMBOLNUMBER_NOTINC; sect_geninfo[nsection].info.startPrbc = pPrachCPConfig->startPrbc; sect_geninfo[nsection].info.numPrbc = pPrachCPConfig->numPrbc, - sect_geninfo[nsection].info.numSymbol = pPrachCPConfig->numSymbol*pPrachCPConfig->occassionsInPrachSlot; + sect_geninfo[nsection].info.numSymbol = pPrachCPConfig->numSymbol; sect_geninfo[nsection].info.reMask = 0xfff; sect_geninfo[nsection].info.beamId = beam_id; sect_geninfo[nsection].info.freqOffset = pPrachCPConfig->freqOffset; - pxran_lib_ctx->prach_last_symbol[cc_id] = sect_geninfo[nsection].info.startSymId + sect_geninfo[nsection].info.numSymbol - 1; + pxran_lib_ctx->prach_last_symbol[cc_id] = pPrachCPConfig->startSymId + pPrachCPConfig->numSymbol*pPrachCPConfig->occassionsInPrachSlot - 1; sect_geninfo[nsection].info.ef = 0; sect_geninfo[nsection].exDataSize = 0; @@ -678,7 +1241,7 @@ int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struc } -int process_ring(struct rte_ring *r) +int process_ring(struct rte_ring *r, uint16_t ring_id, uint16_t q_id) { assert(r); @@ -692,68 +1255,99 @@ int process_ring(struct rte_ring *r) if (!dequeued) return 0; - t1 = MLogTick(); - for (i = 0; i < dequeued; ++i) { - if (xran_ethdi_filter_packet(mbufs[i], 0) == MBUF_FREE) - rte_pktmbuf_free(mbufs[i]); - } - MLogTask(PID_PROCESS_UP_PKT, t1, MLogTick()); + //t1 = MLogTick(); + + xran_ethdi_filter_packet(mbufs, ring_id, q_id, dequeued); + //MLogTask(PID_PROCESS_UP_PKT, t1, MLogTick()); return remaining; } - -int32_t ring_processing_func(void) +/** FH RX AND BBDEV */ +int32_t ring_processing_func(void* args) { struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); - struct xran_device_ctx *const pxran_lib_ctx = xran_dev_get_ctx(); int16_t retPoll = 0; int32_t i; + queueid_t qi; uint64_t t1, t2; rte_timer_manage(); - if (pxran_lib_ctx->bbdev_dec) { + if (ctx->bbdev_dec) { t1 = MLogTick(); - retPoll = pxran_lib_ctx->bbdev_dec(); - if (retPoll != -1) + retPoll = ctx->bbdev_dec(); + if (retPoll == 1) { t2 = MLogTick(); MLogTask(PID_XRAN_BBDEV_UL_POLL + retPoll, t1, t2); } } - if (pxran_lib_ctx->bbdev_enc) { + if (ctx->bbdev_enc) { t1 = MLogTick(); - retPoll = pxran_lib_ctx->bbdev_enc(); - if (retPoll != -1) + retPoll = ctx->bbdev_enc(); + if (retPoll == 1) { t2 = MLogTick(); MLogTask(PID_XRAN_BBDEV_DL_POLL + retPoll, t1, t2); } } - /* UP first */ - - for (i = 0; i < ctx->io_cfg.num_vfs && i < (XRAN_VF_MAX - 1); i = i+2){ - if (process_ring(ctx->rx_ring[i])) + for (i = 0; i < ctx->io_cfg.num_vfs && i < XRAN_VF_MAX; i++){ + for(qi = 0; qi < ctx->rxq_per_port[i]; qi++) { + if (process_ring(ctx->rx_ring[i][qi], i, qi)) return 0; + } + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; - /* CP next */ - if(ctx->io_cfg.id == O_RU) /* process CP only on O-RU */ - if (process_ring(ctx->rx_ring[i+1])) return 0; } +/** Generic thread to perform task on specific core */ +int32_t +xran_generic_worker_thread(void *args) +{ + int32_t res = 0; + struct xran_worker_th_ctx* pThCtx = (struct xran_worker_th_ctx*)args; + struct sched_param sched_param; + struct xran_io_cfg * const p_io_cfg = &(xran_ethdi_get_ctx()->io_cfg); + + memset(&sched_param, 0, sizeof(struct sched_param)); + + printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid()); + sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO; + if ((res = pthread_setschedparam(pthread_self(), SCHED_FIFO, &sched_param))){ + printf("priority is not changed: coreId = %d, result1 = %d\n",rte_lcore_id(), res); + } + pThCtx->worker_policy = SCHED_FIFO; + if ((res = pthread_setname_np(pthread_self(), pThCtx->worker_name))) { + printf("[core %d] pthread_setname_np = %d\n",rte_lcore_id(), res); + } + + for (;;) { + if(pThCtx->task_func) { + if(pThCtx->task_func(pThCtx->task_arg) != 0) + break; + } + if (XRAN_STOPPED == xran_if_current_state) return -1; + if(p_io_cfg->io_sleep) + nanosleep(&sleeptime,NULL); + } + + printf("%s worker thread finished on core %d [worker id %d]\n",pThCtx->worker_name, rte_lcore_id(), pThCtx->worker_id); return 0; } int ring_processing_thread(void *args) { struct sched_param sched_param; - struct xran_device_ctx *const p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_io_cfg * const p_io_cfg = &(xran_ethdi_get_ctx()->io_cfg); int res = 0; memset(&sched_param, 0, sizeof(struct sched_param)); @@ -765,11 +1359,11 @@ int ring_processing_thread(void *args) } for (;;){ - if(ring_processing_func() != 0) + if(ring_processing_func(args) != 0) break; /* work around for some kernel */ - if(p_xran_dev_ctx->fh_init.io_cfg.io_sleep) + if(p_io_cfg->io_sleep) nanosleep(&sleeptime,NULL); } diff --git a/fhi_lib/lib/src/xran_common.h b/fhi_lib/lib/src/xran_common.h index 694e711..3ed75cd 100644 --- a/fhi_lib/lib/src/xran_common.h +++ b/fhi_lib/lib/src/xran_common.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -39,11 +39,16 @@ extern "C" { #include #include #include +#include #include "xran_fh_o_du.h" #include "xran_pkt_up.h" #include "xran_cp_api.h" +#include "xran_dev.h" +#include "xran_pkt.h" + +extern uint64_t interval_us; #define O_DU 0 #define O_RU 1 @@ -51,19 +56,25 @@ extern "C" { #define MAX_N_FULLBAND_SC 273 #define N_SYM_PER_SLOT 14 #define SUBFRAME_DURATION_US 1000 -#define SLOTNUM_PER_SUBFRAME (SUBFRAME_DURATION_US/interval_us) +#define SLOTNUM_PER_SUBFRAME(interval) (SUBFRAME_DURATION_US/(interval)) #define SUBFRAMES_PER_SYSTEMFRAME 10 -#define SLOTS_PER_SYSTEMFRAME (SLOTNUM_PER_SUBFRAME*SUBFRAMES_PER_SYSTEMFRAME) - -/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 839 samples for long sequence or 144*14 (max) for short sequence. The payload length is 3356 octets.*/ -#define PRACH_PLAYBACK_BUFFER_BYTES (144*14*4L) +#define SLOTS_PER_SYSTEMFRAME(interval) ((SLOTNUM_PER_SUBFRAME(interval))*SUBFRAMES_PER_SYSTEMFRAME) +/* PRACH data samples are 32 bits wide, 16bits for I and 16bits for Q. Each packet contains 839 samples for long sequence or 144 for short sequence. The payload length is 840*16*2/8 octets.*/ +#ifdef FCN_1_2_6_EARLIER +#define PRACH_PLAYBACK_BUFFER_BYTES (144*4L) +#else +#define PRACH_PLAYBACK_BUFFER_BYTES (840*4L) +#endif #define PRACH_SRS_BUFFER_BYTES (144*14*4L) /**< this is the configuration of M-plane */ #define XRAN_MAX_NUM_SECTIONS (N_SYM_PER_SLOT* (XRAN_MAX_ANTENNA_NR*2) + XRAN_MAX_ANT_ARRAY_ELM_NR) -#define XRAN_MAX_MBUF_LEN 9600 /**< jumbo frame */ +#define XRAN_PAYLOAD_1_RB_SZ(iqWidth) (((iqWidth == 0) || (iqWidth == 16)) ? \ + (N_SC_PER_PRB*(MAX_IQ_BIT_WIDTH/8)*2) : (3 * iqWidth + 1)) + +#define XRAN_MAX_MBUF_LEN (13168 + XRAN_MAX_SECTIONS_PER_SYM* (RTE_PKTMBUF_HEADROOM + sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr) + sizeof(struct data_section_hdr))) #define NSEC_PER_SEC 1000000000L #define TIMER_RESOLUTION_CYCLES 1596*1 /* 1us */ #define XRAN_RING_SIZE 512 /*4*14*8 pow of 2 */ @@ -74,224 +85,74 @@ extern "C" { #define XRAN_MLOG_VAR 0 /**< enable debug variables to mlog */ -/* PRACH configuration table defines */ -#define XRAN_PRACH_CANDIDATE_PREAMBLE (2) -#define XRAN_PRACH_CANDIDATE_Y (2) -#define XRAN_PRACH_CANDIDATE_SLOT (40) -#define XRAN_PRACH_CONFIG_TABLE_SIZE (256) -#define XRAN_PRACH_PREAMBLE_FORMAT_OF_ABC (9) -typedef enum -{ - FORMAT_0 = 0, - FORMAT_1, - FORMAT_2, - FORMAT_3, - FORMAT_A1, - FORMAT_A2, - FORMAT_A3, - FORMAT_B1, - FORMAT_B2, - FORMAT_B3, - FORMAT_B4, - FORMAT_C0, - FORMAT_C2, - FORMAT_LAST -}PreambleFormatEnum; - -/* add PRACH used config table, same structure as used in refPHY */ -typedef struct -{ - uint8_t prachConfigIdx; - uint8_t preambleFmrt[XRAN_PRACH_CANDIDATE_PREAMBLE]; - uint8_t x; - uint8_t y[XRAN_PRACH_CANDIDATE_Y]; - uint8_t slotNr[XRAN_PRACH_CANDIDATE_SLOT]; - uint8_t slotNrNum; - uint8_t startingSym; - uint8_t nrofPrachInSlot; - uint8_t occassionsInPrachSlot; - uint8_t duration; -} xRANPrachConfigTableStruct; - -typedef struct -{ - uint8_t preambleFmrt; - uint16_t lRALen; - uint8_t fRA; - uint32_t nu; - uint16_t nRaCp; -}xRANPrachPreambleLRAStruct; - -struct xran_prach_cp_config -{ - uint8_t filterIdx; - uint8_t startSymId; - uint16_t startPrbc; - uint8_t numPrbc; - uint8_t numSymbol; - uint16_t timeOffset; - int32_t freqOffset; - uint8_t nrofPrachInSlot; - uint8_t occassionsInPrachSlot; - uint8_t x; - uint8_t y[XRAN_PRACH_CANDIDATE_Y]; - uint8_t isPRACHslot[XRAN_PRACH_CANDIDATE_SLOT]; - uint8_t eAxC_offset; /**< starting eAxC for PRACH stream */ -}; -#define XRAN_MAX_POOLS_PER_SECTOR_NR 8 /**< 2x(TX_OUT, RX_IN, PRACH_IN, SRS_IN) with C-plane */ - -typedef struct sectorHandleInfo -{ - /**< Structure that contains the information to describe the - * instance i.e service type, virtual function, package Id etc..*/ - uint16_t nIndex; - uint16_t nXranPort; - /* Unique ID of an handle shared between phy layer and library */ - /**< number of antennas supported per link*/ - uint32_t nBufferPoolIndex; - /**< Buffer poolIndex*/ - struct rte_mempool * p_bufferPool[XRAN_MAX_POOLS_PER_SECTOR_NR]; - uint32_t bufferPoolElmSz[XRAN_MAX_POOLS_PER_SECTOR_NR]; - uint32_t bufferPoolNumElm[XRAN_MAX_POOLS_PER_SECTOR_NR]; - -}XranSectorHandleInfo, *PXranSectorHandleInfo; - -typedef void (*XranSymCallbackFn)(struct rte_timer *tim, void* arg); - -struct cb_elem_entry{ - XranSymCallbackFn pSymCallback; - void *pSymCallbackTag; - LIST_ENTRY(cb_elem_entry) pointers; -}; +#define DIV_ROUND_OFFSET(X,Y) ( X/Y + ((X%Y)?1:0) ) + +#define MAX_NUM_OF_XRAN_CTX (2) +#define XranIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_XRAN_CTX-1)) ? 0 : (ctx+1)) +#define XranDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_XRAN_CTX-1) : (ctx-1)) + +#define MAX_NUM_OF_DPDK_TIMERS (10) +#define DpdkTimerIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_DPDK_TIMERS-1)) ? 0 : (ctx+1)) +#define DpdkTimerDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_DPDK_TIMERS-1) : (ctx-1)) /* Callback function to send mbuf to the ring */ typedef int (*xran_ethdi_mbuf_send_fn)(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id); -/* - * manage one cell's all Ethernet frames for one DL or UL LTE subframe - */ -typedef struct { - /* -1-this subframe is not used in current frame format - 0-this subframe can be transmitted, i.e., data is ready - 1-this subframe is waiting transmission, i.e., data is not ready - 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1, - set bValid to 10. - */ - int32_t bValid ; // when UL rx, it is subframe index. - int32_t nSegToBeGen; - int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE - // -1 means that DL packet to be transmitted is not ready in BS - int32_t nSegTransferred; // number of data segments has been transmitted or received - struct rte_mbuf *pData[XRAN_N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool - struct xran_buffer_list sBufferList; -} BbuIoBufCtrlStruct; - #define XranIncrementJob(i) ((i >= (XRAN_SYM_JOB_SIZE-1)) ? 0 : (i+1)) -#define XRAN_MAX_PKT_BURST_PER_SYM 32 -#define XRAN_MAX_PACKET_FRAG 9 - -#define MBUF_TABLE_SIZE (2 * MAX(XRAN_MAX_PKT_BURST_PER_SYM, XRAN_MAX_PACKET_FRAG)) - -struct mbuf_table { - uint16_t len; - struct rte_mbuf *m_table[MBUF_TABLE_SIZE]; -}; - -struct xran_device_ctx -{ - uint8_t sector_id; - uint8_t xran_port_id; - struct xran_eaxcid_config eAxc_id_cfg; - struct xran_fh_init fh_init; - struct xran_fh_config fh_cfg; - struct xran_prach_cp_config PrachCPConfig; - - uint32_t enablePrach; - uint32_t enableCP; - - int32_t DynamicSectionEna; - int64_t offset_sec; - int64_t offset_nsec; //offset to GPS time calcuated based on alpha and beta - - uint32_t enableSrs; - struct xran_srs_config srs_cfg; /** configuration of SRS */ - - BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; - - /* buffers lists */ - struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - - struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; - - xran_transport_callback_fn pCallback[XRAN_MAX_SECTOR_NR]; - void *pCallbackTag[XRAN_MAX_SECTOR_NR]; - - xran_transport_callback_fn pPrachCallback[XRAN_MAX_SECTOR_NR]; - void *pPrachCallbackTag[XRAN_MAX_SECTOR_NR]; - - xran_transport_callback_fn pSrsCallback[XRAN_MAX_SECTOR_NR]; - void *pSrsCallbackTag[XRAN_MAX_SECTOR_NR]; - - LIST_HEAD(sym_cb_elem_list, cb_elem_entry) sym_cb_list_head[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - - int32_t sym_up; /**< when we start sym 0 of up with respect to OTA time as measured in symbols */ - int32_t sym_up_ul; - - xran_fh_tti_callback_fn ttiCb[XRAN_CB_MAX]; - void *TtiCbParam[XRAN_CB_MAX]; - uint32_t SkipTti[XRAN_CB_MAX]; - - int xran2phy_mem_ready; +/** Worker task function type */ +typedef int32_t (*worker_task_fn)(void*); - int rx_packet_symb_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - int rx_packet_prach_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - int rx_packet_callback_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]; - int rx_packet_prach_callback_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]; - int prach_start_symbol[XRAN_MAX_SECTOR_NR]; - int prach_last_symbol[XRAN_MAX_SECTOR_NR]; +/** worker thread context structure */ +struct xran_worker_th_ctx { + pthread_t *pThread; - int phy_tti_cb_done; + struct sched_param sched_param; + char worker_name[32]; + int32_t worker_id; + uint64_t worker_core_id; + int32_t worker_policy; + int32_t worker_status; - struct rte_mempool *direct_pool; - struct rte_mempool *indirect_pool; - struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS]; - - struct xran_common_counters fh_counters; - - phy_encoder_poll_fn bbdev_enc; /**< call back to poll BBDev encoder */ - phy_decoder_poll_fn bbdev_dec; /**< call back to poll BBDev decoder */ + /* task */ + worker_task_fn task_func; + void* task_arg; +}; - xran_ethdi_mbuf_send_fn send_cpmbuf2ring; /**< callback to send mbufs of C-Plane packets to the ring */ - xran_ethdi_mbuf_send_fn send_upmbuf2ring; /**< callback to send mbufs of U-Plane packets to the ring */ - uint32_t pkt_proc_core_id; /**< core used for processing DPDK timer cb */ +struct xran_sectioninfo_db { + uint32_t cur_index; /**< Current index to store for this eAXC */ + struct xran_section_info list[XRAN_MAX_NUM_SECTIONS]; /**< The array of section information */ }; -extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_fdd[XRAN_PRACH_CONFIG_TABLE_SIZE]; -extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_tdd[XRAN_PRACH_CONFIG_TABLE_SIZE]; -extern const xRANPrachConfigTableStruct gxranPrachDataTable_mmw[XRAN_PRACH_CONFIG_TABLE_SIZE]; -extern const xRANPrachPreambleLRAStruct gxranPreambleforLRA[13]; +int32_t xran_generic_worker_thread(void *args); -int process_mbuf(struct rte_mbuf *pkt); -int process_ring(struct rte_ring *r); +int process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid); +int process_mbuf_batch(struct rte_mbuf* pkt[], void* handle, int16_t num, struct xran_eaxc_info *p_cid, uint32_t* ret); +int process_ring(struct rte_ring *r, uint16_t ring_id, uint16_t q_id); int ring_processing_thread(void *args); int packets_dump_thread(void *args); - -int send_symbol_ex(enum xran_pkt_dir direction, +// Support for 1-way eCPRI delay measurement per section 3.2.4.6 of eCPRI Specification V2.0 +int32_t xran_ecpri_port_update_required(struct xran_io_cfg * cfg, uint16_t port_id); +int xran_ecpri_one_way_delay_measurement_transmitter(uint16_t port_id, void* handle); +int xran_generate_delay_meas(uint16_t port_id, void* handle, uint8_t actionType, uint8_t MeasurementID ); +int process_delay_meas(struct rte_mbuf *pkt, void* handle, uint16_t port_id); +int xran_process_delmeas_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +int xran_process_delmeas_request_w_fup(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +int xran_process_delmeas_response(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +int xran_process_delmeas_rem_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +int xran_process_delmeas_rem_request_w_fup(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +int xran_process_delmeas_follow_up(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt*, uint16_t port_id); +void xran_initialize_ecpri_del_meas_port(struct xran_ecpri_del_meas_cmn* pCmn, struct xran_ecpri_del_meas_port* pPort,uint16_t full_init); + +int send_symbol_ex(void* handle, + enum xran_pkt_dir direction, uint16_t section_id, struct rte_mbuf *mb, - struct rb_map *data, + uint8_t *data, + uint8_t compMeth, + uint8_t iqWidth, const enum xran_input_byte_order iq_buf_byte_order, uint8_t frame_id, uint8_t subframe_id, @@ -306,7 +167,7 @@ int send_symbol_ex(enum xran_pkt_dir direction, int32_t prepare_symbol_ex(enum xran_pkt_dir direction, uint16_t section_id, struct rte_mbuf *mb, - struct rb_map *data, + uint8_t *data, uint8_t compMeth, uint8_t iqWidth, const enum xran_input_byte_order iq_buf_byte_order, @@ -319,7 +180,31 @@ int32_t prepare_symbol_ex(enum xran_pkt_dir direction, uint8_t CC_ID, uint8_t RU_Port_ID, uint8_t seq_id, - uint32_t do_copy); + uint32_t do_copy, + enum xran_comp_hdr_type staticEn); +inline int32_t prepare_sf_slot_sym (enum xran_pkt_dir direction, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symbol_no, + struct xran_up_pkt_gen_params *xp); + +static inline int32_t prepare_symbol_opt(enum xran_pkt_dir direction, + uint16_t section_id, + struct rte_mbuf *mb, + struct rb_map *data, + uint8_t compMeth, + uint8_t iqWidth, + const enum xran_input_byte_order iq_buf_byte_order, + int prb_start, + int prb_num, + uint8_t CC_ID, + uint8_t RU_Port_ID, + uint8_t seq_id, + uint32_t do_copy, + struct xran_up_pkt_gen_params *xp, + enum xran_comp_hdr_type staticEn); + int send_cpmsg(void *pHandle, struct rte_mbuf *mbuf,struct xran_cp_gen_params *params, struct xran_section_gen_info *sect_geninfo, uint8_t cc_id, uint8_t ru_port_id, uint8_t seq_id); @@ -331,37 +216,20 @@ int32_t generate_cpmsg_dlul(void *pHandle, struct xran_cp_gen_params *params, st int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struct xran_section_gen_info *sect_geninfo, struct rte_mbuf *mbuf, struct xran_device_ctx *pxran_lib_ctx, uint8_t frame_id, uint8_t subframe_id, uint8_t slot_id, - uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint8_t seq_id); + uint16_t beam_id, uint8_t cc_id, uint8_t prach_port_id, uint16_t occasionid, uint8_t seq_id); struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle); -uint8_t xran_get_conf_prach_scs(void *pHandle); -uint8_t xran_get_conf_fftsize(void *pHandle); -uint8_t xran_get_conf_numerology(void *pHandle); -uint8_t xran_get_conf_iqwidth(void *pHandle); -uint8_t xran_get_conf_compmethod(void *pHandle); -uint8_t xran_get_conf_num_bfweights(void *pHandle); - -uint8_t xran_get_num_cc(void *pHandle); -uint8_t xran_get_num_eAxc(void *pHandle); -uint8_t xran_get_num_eAxcUl(void *pHandle); -uint8_t xran_get_num_ant_elm(void *pHandle); -enum xran_category xran_get_ru_category(void *pHandle); - -struct xran_device_ctx *xran_dev_get_ctx(void); - int xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_mbuf_send_fn mbuf_send_up); uint16_t xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id); uint8_t xran_get_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id); -int32_t ring_processing_func(void); +int32_t ring_processing_func(void* arg); int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx); void xran_updateSfnSecStart(void); uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir); -struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data); -int xran_destroy_cb(struct cb_elem_entry * cb_elm); -uint16_t xran_map_ecpriRtcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id); -uint16_t xran_map_ecpriPcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id); +uint16_t xran_map_ecpriRtcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id); +uint16_t xran_map_ecpriPcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id); #ifdef __cplusplus } diff --git a/fhi_lib/lib/src/xran_compression.cpp b/fhi_lib/lib/src/xran_compression.cpp index 721cbe9..112caae 100644 --- a/fhi_lib/lib/src/xran_compression.cpp +++ b/fhi_lib/lib/src/xran_compression.cpp @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -25,486 +25,100 @@ **/ #include "xran_compression.hpp" -#include "xran_bfp_utils.hpp" #include "xran_compression.h" +#include "xran_mod_compression.h" +#include "xran_fh_o_du.h" #include #include #include #include #include -namespace BFP_UPlane -{ - /// Namespace constants - const int k_numREReal = 24; /// 12 IQ pairs - - /// Perform horizontal max of 16 bit values across each lane - __m512i - horizontalMax4x16(const __m512i maxAbsIn) - { - /// Swap 64b in each lane and compute max - const auto k_perm64b = _mm512_set_epi64(6, 7, 4, 5, 2, 3, 0, 1); - auto maxAbsPerm = _mm512_permutexvar_epi64(k_perm64b, maxAbsIn); - auto maxAbsHorz = _mm512_max_epi16(maxAbsIn, maxAbsPerm); - - /// Swap each pair of 32b in each lane and compute max - const auto k_perm32b = _mm512_set_epi32(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1); - maxAbsPerm = _mm512_permutexvar_epi32(k_perm32b, maxAbsHorz); - maxAbsHorz = _mm512_max_epi16(maxAbsHorz, maxAbsPerm); - - /// Swap each IQ pair in each lane (via 32b rotation) and compute max - maxAbsPerm = _mm512_rol_epi32(maxAbsHorz, BlockFloatCompander::k_numBitsIQ); - return _mm512_max_epi16(maxAbsHorz, maxAbsPerm); - } - - - /// Perform U-plane input data re-ordering and vertical max abs of 16b values - /// Works on 4 RB at a time - __m512i - maxAbsVertical4RB(const __m512i inA, const __m512i inB, const __m512i inC) - { - /// Re-order the next 4RB in input data into 3 registers - /// Input SIMD vectors are: - /// [A A A A A A A A A A A A B B B B] - /// [B B B B B B B B C C C C C C C C] - /// [C C C C D D D D D D D D D D D D] - /// Re-ordered SIMD vectors are: - /// [A A A A B B B B C C C C D D D D] - /// [A A A A B B B B C C C C D D D D] - /// [A A A A B B B B C C C C D D D D] - constexpr uint8_t k_msk1 = 0b11111100; // Copy first lane of src - constexpr int k_shuff1 = 0x41; - const auto z_w1 = _mm512_mask_shuffle_i64x2(inA, k_msk1, inB, inC, k_shuff1); - - constexpr uint8_t k_msk2 = 0b11000011; // Copy middle two lanes of src - constexpr int k_shuff2 = 0xB1; - const auto z_w2 = _mm512_mask_shuffle_i64x2(inB, k_msk2, inA, inC, k_shuff2); - - constexpr uint8_t k_msk3 = 0b00111111; // Copy last lane of src - constexpr int k_shuff3 = 0xBE; - const auto z_w3 = _mm512_mask_shuffle_i64x2(inC, k_msk3, inA, inB, k_shuff3); - - /// Perform max abs on these 3 registers - const auto abs16_1 = _mm512_abs_epi16(z_w1); - const auto abs16_2 = _mm512_abs_epi16(z_w2); - const auto abs16_3 = _mm512_abs_epi16(z_w3); - return _mm512_max_epi16(_mm512_max_epi16(abs16_1, abs16_2), abs16_3); - } - +using namespace BlockFloatCompander; - /// Selects first 32 bit value in each src lane and packs into laneNum of dest - __m512i - slidePermute(const __m512i src, const __m512i dest, const int laneNum) - { - const auto k_selectVals = _mm512_set_epi32(28, 24, 20, 16, 28, 24, 20, 16, - 28, 24, 20, 16, 28, 24, 20, 16); - constexpr uint16_t k_laneMsk[4] = { 0x000F, 0x00F0, 0x0F00, 0xF000 }; - return _mm512_mask_permutex2var_epi32(dest, k_laneMsk[laneNum], k_selectVals, src); - } - - - /// Compute exponent value for a set of 16 RB from the maximum absolute value. - /// Max Abs operates in a loop, executing 4 RB per iteration. The results are - /// packed into the final output register. - __m512i - computeExponent_16RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) - { - __m512i maxAbs = __m512i(); - const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); - /// Max Abs loop operates on 4RB at a time -#pragma unroll(4) - for (int n = 0; n < 4; ++n) - { - /// Re-order and vertical max abs - auto maxAbsVert = maxAbsVertical4RB(rawData[3 * n + 0], rawData[3 * n + 1], rawData[3 * n + 2]); - /// Horizontal max abs - auto maxAbsHorz = horizontalMax4x16(maxAbsVert); - /// Pack these 4 values into maxAbs - maxAbs = slidePermute(maxAbsHorz, maxAbs, n); - } - /// Calculate exponent - const auto maxAbs32 = BlockFloatCompander::maskUpperWord(maxAbs); - return BlockFloatCompander::expLzCnt(maxAbs32, totShiftBits); - } - - - /// Compute exponent value for a set of 4 RB from the maximum absolute value. - /// Note that we do not need to perform any packing of result as we are only - /// computing 4 RB. The appropriate offset is taken later when extracting the - /// exponent. - __m512i - computeExponent_4RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) - { - const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); - /// Re-order and vertical max abs - const auto maxAbsVert = maxAbsVertical4RB(rawData[0], rawData[1], rawData[2]); - /// Horizontal max abs - const auto maxAbsHorz = horizontalMax4x16(maxAbsVert); - /// Calculate exponent - const auto maxAbs = BlockFloatCompander::maskUpperWord(maxAbsHorz); - return BlockFloatCompander::expLzCnt(maxAbs, totShiftBits); - } - - - /// Compute exponent value for 1 RB from the maximum absolute value. - /// This works with horizontal max abs only, and needs to include a - /// step to select the final exponent from the 4 lanes. - uint8_t - computeExponent_1RB(const BlockFloatCompander::ExpandedData& dataIn, const __m512i totShiftBits) - { - const __m512i* rawData = reinterpret_cast(dataIn.dataExpanded); - /// Abs - const auto rawDataAbs = _mm512_abs_epi16(rawData[0]); - /// No need to do a full horizontal max operation here, just do a max IQ step, - /// compute the exponents and then use a reduce max over all exponent values. This - /// is the fastest way to handle a single RB. - const auto rawAbsIQSwap = _mm512_rol_epi32(rawDataAbs, BlockFloatCompander::k_numBitsIQ); - const auto maxAbsIQ = _mm512_max_epi16(rawDataAbs, rawAbsIQSwap); - /// Calculate exponent - const auto maxAbsIQ32 = BlockFloatCompander::maskUpperWord(maxAbsIQ); - const auto exps = BlockFloatCompander::expLzCnt(maxAbsIQ32, totShiftBits); - /// At this point we have exponent values for the maximum of each IQ pair. - /// Run a reduce max step to compute the maximum exponent value in the first - /// three lanes - this will give the desired exponent for this RB. - constexpr uint16_t k_expMsk = 0x0FFF; - return (uint8_t)_mm512_mask_reduce_max_epi32(k_expMsk, exps); - } - - - /// Apply compression to 1 RB - template - void - applyCompressionN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr, const uint16_t rbWriteMask) - { - /// Get AVX512 pointer aligned to desired RB - const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); - /// Apply the exponent shift - const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); - /// Pack compressed data network byte order - const auto compDataBytePacked = networkBytePack(compData); - /// Store exponent first - dataOut->dataCompressed[thisRBExpAddr] = thisExp; - /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) - /// Use three offset stores to join - _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 0)); - _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + dataIn.iqWidth, rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 1)); - _mm_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1 + (2 * dataIn.iqWidth), rbWriteMask, _mm512_extracti64x2_epi64(compDataBytePacked, 2)); - } - - - /// Apply 9, 10, or 12bit compression to 16 RB - template - void - compressN_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) - { - const auto exponents = computeExponent_16RB(dataIn, totShiftBits); -#pragma unroll(16) - for (int n = 0; n < 16; ++n) - { - applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * totNumBytesPerRB, rbWriteMask); - } - } - - - /// Apply 9, 10, or 12bit compression to 4 RB - template - void - compressN_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) - { - const auto exponents = computeExponent_4RB(dataIn, totShiftBits); -#pragma unroll(4) - for (int n = 0; n < 4; ++n) - { - applyCompressionN_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * totNumBytesPerRB, rbWriteMask); - } - } - - - /// Apply 9, 10, or 12bit compression to 1 RB - template - void - compressN_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) - { - const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); - applyCompressionN_1RB(dataIn, dataOut, 0, thisExponent, 0, rbWriteMask); - } - - - /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. - template - void - compressByAllocN(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const __m512i totShiftBits, const int totNumBytesPerRB, const uint16_t rbWriteMask) - { - switch (dataIn.numBlocks) - { - case 16: - compressN_16RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); - break; - - case 4: - compressN_4RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); - break; - - case 1: - compressN_1RB(dataIn, dataOut, totShiftBits, totNumBytesPerRB, rbWriteMask); - break; - } - } - - - /// Apply compression to 1 RB - void - applyCompression8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, - const int numREOffset, const uint8_t thisExp, const int thisRBExpAddr) - { - /// Get AVX512 pointer aligned to desired RB - const __m512i* rawDataIn = reinterpret_cast(dataIn.dataExpanded + numREOffset); - /// Apply the exponent shift - const auto compData = _mm512_srai_epi16(*rawDataIn, thisExp); - /// Store exponent first - dataOut->dataCompressed[thisRBExpAddr] = thisExp; - /// Now have 1 RB worth of bytes separated into 3 chunks (1 per lane) - /// Use three offset stores to join - constexpr uint32_t k_rbMask = 0x00FFFFFF; // Write mask for 1RB (24 values) - _mm256_mask_storeu_epi8(dataOut->dataCompressed + thisRBExpAddr + 1, k_rbMask, _mm512_cvtepi16_epi8(compData)); - } - - - /// 8bit RB compression loop for 16 RB - void - compress8_16RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) - { - const auto exponents = computeExponent_16RB(dataIn, totShiftBits); -#pragma unroll(16) - for (int n = 0; n < 16; ++n) - { - applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 4], n * (k_numREReal + 1)); - } - } +/** callback function type for Symbol packet */ +typedef void (*xran_bfp_compress_fn)(const BlockFloatCompander::ExpandedData& dataIn, + BlockFloatCompander::CompressedData* dataOut); +/** callback function type for Symbol packet */ +typedef void (*xran_bfp_decompress_fn)(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut); - /// 8bit RB compression loop for 4 RB - void - compress8_4RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) +int32_t +xranlib_compress(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response) { - const auto exponents = computeExponent_4RB(dataIn, totShiftBits); -#pragma unroll(4) - for (int n = 0; n < 4; ++n) + if (request->compMethod == XRAN_COMPMETHOD_MODULATION) { - applyCompression8_1RB(dataIn, dataOut, n * k_numREReal, ((uint8_t*)&exponents)[n * 16], n * (k_numREReal + 1)); - } - } - - - /// 8bit RB compression loop for 4 RB - void - compress8_1RB(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) - { - const auto thisExponent = computeExponent_1RB(dataIn, totShiftBits); - applyCompression8_1RB(dataIn, dataOut, 0, thisExponent, 0); + struct xranlib_5gnr_mod_compression_request mod_request; + struct xranlib_5gnr_mod_compression_response mod_response; + mod_request.data_in = request->data_in; + mod_request.unit = request->ScaleFactor; + mod_request.modulation = (enum xran_modulation_order)(request->iqWidth * 2); + mod_request.num_symbols = request->numRBs * XRAN_NUM_OF_SC_PER_RB; + mod_request.re_mask = request->reMask; + mod_response.data_out = response->data_out; + response->len = (request->numRBs * XRAN_NUM_OF_SC_PER_RB * request->iqWidth * 2) >> 3; + + return xranlib_5gnr_mod_compression(&mod_request, &mod_response); } - - - /// Calls compression function specific to the number of RB to be executed. For 8 bit iqWidth. - void - compressByAlloc8(const BlockFloatCompander::ExpandedData& dataIn, BlockFloatCompander::CompressedData* dataOut, const __m512i totShiftBits) - { - switch (dataIn.numBlocks) - { - case 16: - compress8_16RB(dataIn, dataOut, totShiftBits); - break; - - case 4: - compress8_4RB(dataIn, dataOut, totShiftBits); - break; - - case 1: - compress8_1RB(dataIn, dataOut, totShiftBits); - break; + else{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) { + return xranlib_compress_avxsnc(request,response); + } else { + return xranlib_compress_avx512(request,response); } } - - - /// Apply compression to 1 RB - template - void - applyExpansionN_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, - const int expAddr, const int thisRBAddr, const int maxExpShift) - { - /// Unpack network order packed data - const auto dataUnpacked = networkByteUnpack(dataIn.dataCompressed + expAddr + 1); - /// Apply exponent scaling (by appropriate arithmetic shift right) - const auto dataExpanded = _mm512_srai_epi16(dataUnpacked, maxExpShift - *(dataIn.dataCompressed + expAddr)); - /// Write expanded data to output - static constexpr uint32_t k_WriteMask = 0x00FFFFFF; - _mm512_mask_storeu_epi16(dataOut->dataExpanded + thisRBAddr, k_WriteMask, dataExpanded); } - - /// Calls compression function specific to the number of RB to be executed. For 9, 10, or 12bit iqWidth. - template - void - expandByAllocN(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, - const int totNumBytesPerRB, const int maxExpShift) +int32_t +xranlib_decompress(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response) { - switch (dataIn.numBlocks) + if (request->compMethod == XRAN_COMPMETHOD_MODULATION) { - case 16: -#pragma unroll(16) - for (int n = 0; n < 16; ++n) - { - applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); - } - break; - - case 4: -#pragma unroll(4) - for (int n = 0; n < 4; ++n) - { - applyExpansionN_1RB(dataIn, dataOut, n * totNumBytesPerRB, n * k_numREReal, maxExpShift); + struct xranlib_5gnr_mod_decompression_request mod_request; + struct xranlib_5gnr_mod_decompression_response mod_response; + mod_request.data_in = request->data_in; + mod_request.unit = request->ScaleFactor; + mod_request.modulation = (enum xran_modulation_order)(request->iqWidth * 2); + mod_request.num_symbols = request->numRBs * XRAN_NUM_OF_SC_PER_RB; + mod_request.re_mask = request->reMask; + mod_response.data_out = response->data_out; + response->len = request->numRBs * XRAN_NUM_OF_SC_PER_RB * 4; + + return xranlib_5gnr_mod_decompression(&mod_request, &mod_response); } - break; - - case 1: - applyExpansionN_1RB(dataIn, dataOut, 0, 0, maxExpShift); - break; + else{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) { + return xranlib_decompress_avxsnc(request,response); + } else { + return xranlib_decompress_avx512(request,response); } } - - - /// Apply expansion to 1 RB and store - void - applyExpansion8_1RB(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut, - const int expAddr, const int thisRBAddr) - { - const __m256i* rawDataIn = reinterpret_cast(dataIn.dataCompressed + expAddr + 1); - const auto compData16 = _mm512_cvtepi8_epi16(*rawDataIn); - const auto expData = _mm512_slli_epi16(compData16, *(dataIn.dataCompressed + expAddr)); - constexpr uint8_t k_rbMask64 = 0b00111111; // 64b write mask for 1RB (24 int16 values) - _mm512_mask_storeu_epi64(dataOut->dataExpanded + thisRBAddr, k_rbMask64, expData); } - - /// Calls expansion function specific to the number of RB to be executed. For 8 bit iqWidth. - void - expandByAlloc8(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut) - { - switch (dataIn.numBlocks) +int32_t +xranlib_compress_bfw(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response) { - case 16: -#pragma unroll(16) - for (int n = 0; n < 16; ++n) - { - applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); - } - break; - - case 4: -#pragma unroll(4) - for (int n = 0; n < 4; ++n) - { - applyExpansion8_1RB(dataIn, dataOut, n * (k_numREReal + 1), n * k_numREReal); - } - break; - - case 1: - applyExpansion8_1RB(dataIn, dataOut, 0, 0); - break; + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) { + return xranlib_compress_avxsnc_bfw(request,response); + } else { + return xranlib_compress_avx512_bfw(request,response); } } -} - - - -/// Main kernel function for compression. -/// Starts by determining iqWidth specific parameters and functions. -void -BlockFloatCompander::BFPCompressUserPlaneAvx512(const ExpandedData& dataIn, CompressedData* dataOut) -{ - /// Compensation for extra zeros in 32b leading zero count when computing exponent - const auto totShiftBits8 = _mm512_set1_epi32(25); - const auto totShiftBits9 = _mm512_set1_epi32(24); - const auto totShiftBits10 = _mm512_set1_epi32(23); - const auto totShiftBits12 = _mm512_set1_epi32(21); - - /// Total number of compressed bytes per RB for each iqWidth option - constexpr int totNumBytesPerRB9 = 28; - constexpr int totNumBytesPerRB10 = 31; - constexpr int totNumBytesPerRB12 = 37; - - /// Compressed data write mask for each iqWidth option - constexpr uint16_t rbWriteMask9 = 0x01FF; - constexpr uint16_t rbWriteMask10 = 0x03FF; - constexpr uint16_t rbWriteMask12 = 0x0FFF; - - switch (dataIn.iqWidth) - { - case 8: - BFP_UPlane::compressByAlloc8(dataIn, dataOut, totShiftBits8); - break; - - case 9: - BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits9, totNumBytesPerRB9, rbWriteMask9); - break; - - case 10: - BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits10, totNumBytesPerRB10, rbWriteMask10); - break; - - case 12: - BFP_UPlane::compressByAllocN(dataIn, dataOut, totShiftBits12, totNumBytesPerRB12, rbWriteMask12); - break; - } -} - - -/// Main kernel function for expansion. -/// Starts by determining iqWidth specific parameters and functions. -void -BlockFloatCompander::BFPExpandUserPlaneAvx512(const CompressedData& dataIn, ExpandedData* dataOut) -{ - constexpr int k_totNumBytesPerRB9 = 28; - constexpr int k_totNumBytesPerRB10 = 31; - constexpr int k_totNumBytesPerRB12 = 37; - - constexpr int k_maxExpShift9 = 7; - constexpr int k_maxExpShift10 = 6; - constexpr int k_maxExpShift12 = 4; - - switch (dataIn.iqWidth) +int32_t +xranlib_decompress_bfw(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response) { - case 8: - BFP_UPlane::expandByAlloc8(dataIn, dataOut); - break; - - case 9: - BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB9, k_maxExpShift9); - break; - - case 10: - BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB10, k_maxExpShift10); - break; - - case 12: - BFP_UPlane::expandByAllocN(dataIn, dataOut, k_totNumBytesPerRB12, k_maxExpShift12); - break; + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) { + return xranlib_decompress_avxsnc_bfw(request,response); + } else { + return xranlib_decompress_avx512_bfw(request,response); } } -/** callback function type for Symbol packet */ -typedef void (*xran_bfp_compress_fn)(const BlockFloatCompander::ExpandedData& dataIn, - BlockFloatCompander::CompressedData* dataOut); - -/** callback function type for Symbol packet */ -typedef void (*xran_bfp_decompress_fn)(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut); - int32_t xranlib_compress_avx512(const struct xranlib_compress_request *request, struct xranlib_compress_response *response) diff --git a/fhi_lib/lib/src/xran_compression_snc.cpp b/fhi_lib/lib/src/xran_compression_snc.cpp new file mode 100644 index 0000000..11096ab --- /dev/null +++ b/fhi_lib/lib/src/xran_compression_snc.cpp @@ -0,0 +1,270 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief xRAN BFP compression/decompression U-plane implementation and interface functions + * + * @file xran_compression.cpp + * @ingroup group_source_xran + * @author Intel Corporation + **/ +#include "xran_compression.hpp" +#include "xran_compression.h" +#include +#include +#include +#include +#include + +using namespace BlockFloatCompander; + +/** callback function type for Symbol packet */ +typedef void (*xran_bfp_compress_fn)(const BlockFloatCompander::ExpandedData& dataIn, + BlockFloatCompander::CompressedData* dataOut); + +/** callback function type for Symbol packet */ +typedef void (*xran_bfp_decompress_fn)(const BlockFloatCompander::CompressedData& dataIn, BlockFloatCompander::ExpandedData* dataOut); + +int32_t +xranlib_compress_avxsnc(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response) +{ + BlockFloatCompander::ExpandedData expandedDataInput; + BlockFloatCompander::CompressedData compressedDataOut; + xran_bfp_compress_fn com_fn = NULL; + uint16_t totalRBs = request->numRBs; + uint16_t remRBs = totalRBs; + int16_t len = 0; + int16_t block_idx_bytes = 0; + + switch (request->iqWidth) { + case 8: + case 9: + case 10: + case 12: + com_fn = BlockFloatCompander::BFPCompressUserPlaneAvxSnc; + break; + default: + com_fn = BlockFloatCompander::BFPCompressRef; + break; + } + + expandedDataInput.iqWidth = request->iqWidth; + expandedDataInput.numDataElements = 24; + + while (remRBs){ + expandedDataInput.dataExpanded = &request->data_in[block_idx_bytes]; + compressedDataOut.dataCompressed = (uint8_t*)&response->data_out[len]; + if(remRBs >= 16){ + expandedDataInput.numBlocks = 16; + com_fn(expandedDataInput, &compressedDataOut); + len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)16); + block_idx_bytes += 16*expandedDataInput.numDataElements; + remRBs -= 16; + }else if(remRBs >= 4){ + expandedDataInput.numBlocks = 4; + com_fn(expandedDataInput, &compressedDataOut); + len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)4); + block_idx_bytes +=4*expandedDataInput.numDataElements; + remRBs -=4; + }else if (remRBs >= 1){ + expandedDataInput.numBlocks = 1; + com_fn(expandedDataInput, &compressedDataOut); + len += ((3 * expandedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)1); + block_idx_bytes +=1*expandedDataInput.numDataElements; + remRBs = remRBs - 1; + } + } + + response->len = ((3 * expandedDataInput.iqWidth) + 1) * totalRBs; + + return 0; +} + +int32_t +xranlib_decompress_avxsnc(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response) +{ + BlockFloatCompander::CompressedData compressedDataInput; + BlockFloatCompander::ExpandedData expandedDataOut; + + xran_bfp_decompress_fn decom_fn = NULL; + uint16_t totalRBs = request->numRBs; + uint16_t remRBs = totalRBs; + int16_t len = 0; + int16_t block_idx_bytes = 0; + + switch (request->iqWidth) { + case 8: + case 9: + case 10: + case 12: + decom_fn = BlockFloatCompander::BFPExpandUserPlaneAvxSnc; + break; + default: + decom_fn = BlockFloatCompander::BFPExpandRef; + break; + } + + compressedDataInput.iqWidth = request->iqWidth; + compressedDataInput.numDataElements = 24; + + while(remRBs) { + compressedDataInput.dataCompressed = (uint8_t*)&request->data_in[block_idx_bytes]; + expandedDataOut.dataExpanded = &response->data_out[len]; + if(remRBs >= 16){ + compressedDataInput.numBlocks = 16; + decom_fn(compressedDataInput, &expandedDataOut); + len += 16*compressedDataInput.numDataElements; + block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)16); + remRBs -= 16; + }else if(remRBs >= 4){ + compressedDataInput.numBlocks = 4; + decom_fn(compressedDataInput, &expandedDataOut); + len += 4*compressedDataInput.numDataElements; + block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)4); + remRBs -=4; + }else if (remRBs >= 1){ + compressedDataInput.numBlocks = 1; + decom_fn(compressedDataInput, &expandedDataOut); + len += 1*compressedDataInput.numDataElements; + block_idx_bytes += ((3 * compressedDataInput.iqWidth) + 1) * std::min((int16_t)BlockFloatCompander::k_maxNumBlocks,(int16_t)1); + remRBs = remRBs - 1; + } + } + + response->len = totalRBs * compressedDataInput.numDataElements * sizeof(int16_t); + + return 0; +} + +int32_t +xranlib_compress_avxsnc_bfw(const struct xranlib_compress_request *request, + struct xranlib_compress_response *response) +{ + BlockFloatCompander::ExpandedData expandedDataInput; + BlockFloatCompander::CompressedData compressedDataOut; + xran_bfp_compress_fn com_fn = NULL; + + if (request->numRBs != 1){ + printf("Unsupported numRBs %d\n", request->numRBs); + return -1; + } + + switch (request->iqWidth) { + case 8: + case 9: + case 10: + case 12: + switch (request->numDataElements) { + case 16: + com_fn = BlockFloatCompander::BFPCompressCtrlPlane8AvxSnc; + break; + case 32: + com_fn = BlockFloatCompander::BFPCompressCtrlPlane16AvxSnc; + break; + case 64: + com_fn = BlockFloatCompander::BFPCompressCtrlPlane32AvxSnc; + break; + case 128: + com_fn = BlockFloatCompander::BFPCompressCtrlPlane64AvxSnc; + break; + case 24: + default: + printf("Unsupported numDataElements %d\n", request->numDataElements); + return -1; + break; + } + break; + default: + printf("Unsupported iqWidth %d\n", request->iqWidth); + return -1; + break; + } + + expandedDataInput.iqWidth = request->iqWidth; + expandedDataInput.numDataElements = request->numDataElements; + expandedDataInput.numBlocks = 1; + expandedDataInput.dataExpanded = &request->data_in[0]; + compressedDataOut.dataCompressed = (uint8_t*)&response->data_out[0]; + + com_fn(expandedDataInput, &compressedDataOut); + + response->len = (((expandedDataInput.numDataElements * expandedDataInput.iqWidth) >> 3) + 1) + * request->numRBs; + + return 0; +} + +int32_t +xranlib_decompress_avxsnc_bfw(const struct xranlib_decompress_request *request, + struct xranlib_decompress_response *response) +{ + BlockFloatCompander::CompressedData compressedDataInput; + BlockFloatCompander::ExpandedData expandedDataOut; + xran_bfp_decompress_fn decom_fn = NULL; + + if (request->numRBs != 1){ + printf("Unsupported numRBs %d\n", request->numRBs); + return -1; + } + + switch (request->iqWidth) { + case 8: + case 9: + case 10: + case 12: + switch (request->numDataElements) { + case 16: + decom_fn = BlockFloatCompander::BFPExpandCtrlPlane8AvxSnc; + break; + case 32: + decom_fn = BlockFloatCompander::BFPExpandCtrlPlane16AvxSnc; + break; + case 64: + decom_fn = BlockFloatCompander::BFPExpandCtrlPlane32AvxSnc; + break; + case 128: + decom_fn = BlockFloatCompander::BFPExpandCtrlPlane64AvxSnc; + break; + case 24: + default: + printf("Unsupported numDataElements %d\n", request->numDataElements); + return -1; + break; + } + break; + default: + printf("Unsupported iqWidth %d\n", request->iqWidth); + return -1; + break; + } + + compressedDataInput.iqWidth = request->iqWidth; + compressedDataInput.numDataElements = request->numDataElements; + compressedDataInput.numBlocks = 1; + compressedDataInput.dataCompressed = (uint8_t*)&request->data_in[0]; + expandedDataOut.dataExpanded = &response->data_out[0]; + + decom_fn(compressedDataInput, &expandedDataOut); + + response->len = request->numRBs * compressedDataInput.numDataElements * sizeof(int16_t); + + return 0; +} + diff --git a/fhi_lib/lib/src/xran_cp_api.c b/fhi_lib/lib/src/xran_cp_api.c index 9122337..02ba81c 100644 --- a/fhi_lib/lib/src/xran_cp_api.c +++ b/fhi_lib/lib/src/xran_cp_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -25,25 +25,19 @@ * @author Intel Corporation * **/ - +#include #include +#include +#include "ethdi.h" #include "xran_common.h" #include "xran_transport.h" #include "xran_cp_api.h" #include "xran_printf.h" #include "xran_compression.h" +#include "xran_dev.h" - -/** - * This structure to store the section information of C-Plane - * in order to generate and parse corresponding U-Plane */ -struct xran_sectioninfo_db { - uint32_t cur_index; /**< Current index to store for this eAXC */ - struct xran_section_info list[XRAN_MAX_NUM_SECTIONS]; /**< The array of section information */ - }; - -static struct xran_sectioninfo_db sectiondb[XRAN_MAX_SECTIONDB_CTX][XRAN_DIR_MAX][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; +PSECTION_DB_TYPE p_sectiondb[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL}; static const uint8_t zeropad[XRAN_SECTIONEXT_ALIGN] = { 0, 0, 0, 0 }; static const uint8_t bitmask[] = { 0x00, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff }; @@ -63,15 +57,59 @@ static const uint8_t bitmask[] = { 0x00, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xf * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_RESOURCE, if memory is not enough to allocate database area */ -int xran_cp_init_sectiondb(void *pHandle) +int32_t +xran_cp_init_sectiondb(void *pHandle) { - int ctx, dir, cc, ant; + int32_t ctx, dir, cc, ant; + struct xran_device_ctx* p_dev = NULL; + uint8_t xran_port_id = 0; + PSECTION_DB_TYPE p_sec_db = NULL; + struct xran_sectioninfo_db* p_sec_db_elm = NULL; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + if (p_sectiondb[xran_port_id] == NULL){ + p_sec_db = rte_zmalloc(NULL,sizeof(SECTION_DB_TYPE), 0); + if(p_sec_db){ + p_sectiondb[xran_port_id] = p_sec_db; + memset(p_sec_db, 0, sizeof(SECTION_DB_TYPE)); + print_dbg("xran_port_id %d %p\n",xran_port_id, p_sectiondb[xran_port_id]); + for (ctx = 0; ctx < XRAN_MAX_SECTIONDB_CTX; ctx++) { + for (dir = 0; dir < XRAN_DIR_MAX; dir++) { + for (cc = 0; cc < p_dev->fh_cfg.nCC && cc < XRAN_COMPONENT_CARRIERS_MAX; cc++) { + for (ant = 0; ant < (p_dev->fh_cfg.neAxc*2 + p_dev->fh_cfg.nAntElmTRx) && ant < (XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR); ant++) { + p_sec_db_elm = (struct xran_sectioninfo_db*)rte_zmalloc(NULL,sizeof(struct xran_sectioninfo_db), 0); + if(p_sec_db_elm) { + memset(p_sec_db_elm, 0, sizeof(struct xran_sectioninfo_db)); + p_sec_db->p_sectiondb_elm[ctx][dir][cc][ant] = p_sec_db_elm; + } else { + print_err("Memory Allocation Failed [port %d sz %ld]\n", xran_port_id, sizeof(struct xran_sectioninfo_db)); + return (XRAN_STATUS_RESOURCE); + } + } + } + } + } + } else { + print_err("Memory Allocation Failed [port %d sz %ld]\n", xran_port_id, sizeof(SECTION_DB_TYPE)); + return (XRAN_STATUS_RESOURCE); + } + }else { + p_sec_db = p_sectiondb[xran_port_id]; + } for(ctx=0; ctx < XRAN_MAX_SECTIONDB_CTX; ctx++) for(dir=0; dir < XRAN_DIR_MAX; dir++) - for(cc=0; cc < XRAN_COMPONENT_CARRIERS_MAX; cc++) - for(ant=0; ant < XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR; ant++) - sectiondb[ctx][dir][cc][ant].cur_index = 0; + for (cc = 0; cc < p_dev->fh_cfg.nCC && cc < XRAN_COMPONENT_CARRIERS_MAX; cc++) + for (ant = 0; ant < (p_dev->fh_cfg.neAxc*2 + p_dev->fh_cfg.nAntElmTRx) && ant < (XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR); ant++) + if(p_sec_db->p_sectiondb_elm[ctx][dir][cc][ant]) + p_sec_db->p_sectiondb_elm[ctx][dir][cc][ant]->cur_index = 0; return (XRAN_STATUS_SUCCESS); } @@ -86,17 +124,71 @@ int xran_cp_init_sectiondb(void *pHandle) * @return * XRAN_STATUS_SUCCESS on success */ -int xran_cp_free_sectiondb(void *pHandle) +int32_t +xran_cp_free_sectiondb(void *pHandle) { + int32_t ctx, dir, cc, ant; + struct xran_device_ctx* p_dev = NULL; + uint8_t xran_port_id = 0; + PSECTION_DB_TYPE p_sec_db = NULL; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + if (p_sectiondb[xran_port_id] == NULL){ + return (XRAN_STATUS_INVALID_PARAM); + } else { + p_sec_db = p_sectiondb[xran_port_id]; + for (ctx = 0; ctx < XRAN_MAX_SECTIONDB_CTX; ctx++) { + for (dir = 0; dir < XRAN_DIR_MAX; dir++) { + for (cc = 0; cc < XRAN_COMPONENT_CARRIERS_MAX; cc++) { + for (ant = 0; ant < (XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR); ant++) { + if(p_sec_db->p_sectiondb_elm[ctx][dir][cc][ant]) + rte_free(p_sec_db->p_sectiondb_elm[ctx][dir][cc][ant]); + } + } + } + } + rte_free(p_sec_db); + p_sectiondb[xran_port_id] = NULL; + } + return (XRAN_STATUS_SUCCESS); } -static inline struct xran_sectioninfo_db *xran_get_section_db(void *pHandle, +static inline struct xran_sectioninfo_db * +xran_get_section_db(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id) { struct xran_sectioninfo_db *ptr; + struct xran_device_ctx* p_dev = NULL; + uint8_t xran_port_id = 0; + PSECTION_DB_TYPE p_sec_db = NULL; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (NULL); + } + if(unlikely(xran_port_id >= XRAN_PORTS_NUM)) { + print_err("Invalid Port id - %d", p_dev->xran_port_id); + return (NULL); + } + if (p_sectiondb[xran_port_id] == NULL){ + print_err("p_sectiondb xran_port %d\n", xran_port_id); + return (NULL); + }else { + p_sec_db = p_sectiondb[xran_port_id]; + } if(unlikely(ctx_id >= XRAN_MAX_SECTIONDB_CTX)) { print_err("Invalid Context id - %d", ctx_id); return (NULL); @@ -117,12 +209,13 @@ static inline struct xran_sectioninfo_db *xran_get_section_db(void *pHandle, return (NULL); } - ptr = §iondb[ctx_id][dir][cc_id][ruport_id]; + ptr = p_sec_db->p_sectiondb_elm[ctx_id][dir][cc_id][ruport_id]; return(ptr); } -static inline struct xran_section_info *xran_get_section_info(struct xran_sectioninfo_db *ptr, uint16_t index) +static inline struct xran_section_info * +xran_get_section_info(struct xran_sectioninfo_db *ptr, uint16_t index) { if(unlikely(ptr == NULL)) return (NULL); @@ -157,14 +250,12 @@ static inline struct xran_section_info *xran_get_section_info(struct xran_sectio * XRAN_STATUS_INVALID_PARAM, if direction, CC ID or RU port ID is incorrect * XRAN_STATUS_RESOURCE, if no more space to add on database */ -int xran_cp_add_section_info(void *pHandle, - uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, - struct xran_section_info *info) +int32_t +xran_cp_add_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, struct xran_section_info *info) { struct xran_sectioninfo_db *ptr; struct xran_section_info *list; - ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id); if(unlikely(ptr == NULL)) { return (XRAN_STATUS_INVALID_PARAM); @@ -176,24 +267,27 @@ int xran_cp_add_section_info(void *pHandle, } list = xran_get_section_info(ptr, ptr->cur_index); - - rte_memcpy(list, info, sizeof(struct xran_section_info)); + if (list) + memcpy(list, info, sizeof(struct xran_section_info)); + else + { + print_err("Null list in section db\n!"); + return (XRAN_STATUS_INVALID_PARAM); + } ptr->cur_index++; return (XRAN_STATUS_SUCCESS); } -int xran_cp_add_multisection_info(void *pHandle, - uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, - struct xran_cp_gen_params *gen_info) +int32_t +xran_cp_add_multisection_info(void *pHandle, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, struct xran_cp_gen_params *gen_info) { - int i; + int32_t i; uint8_t dir, num_sections; struct xran_sectioninfo_db *ptr; struct xran_section_info *list; - dir = gen_info->dir; num_sections = gen_info->numSections; @@ -208,17 +302,24 @@ int xran_cp_add_multisection_info(void *pHandle, } list = xran_get_section_info(ptr, ptr->cur_index); - + if (list) + { for(i=0; isections[i].info, sizeof(struct xran_section_info)); + memcpy(&list[i], &gen_info->sections[i].info, sizeof(struct xran_section_info)); ptr->cur_index++; } + } + else + { + print_err("Null list in section db\n!"); + return (XRAN_STATUS_INVALID_PARAM); + } return (XRAN_STATUS_SUCCESS); } /** - * @brief Find a section information of C-Plane from dabase + * @brief Find a section information of C-Plane from database * by given information * * @ingroup xran_cp_pkt @@ -239,14 +340,12 @@ int xran_cp_add_multisection_info(void *pHandle, * The pointer of section information if matched section is found * NULL if failed to find matched section */ -struct xran_section_info *xran_cp_find_section_info(void *pHandle, - uint8_t dir, uint8_t cc_id, uint8_t ruport_id, - uint8_t ctx_id, uint16_t section_id) +struct xran_section_info * +xran_cp_find_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, uint16_t section_id) { - int index, num_index; + int32_t index, num_index; struct xran_sectioninfo_db *ptr; - ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id); if(unlikely(ptr == NULL)) return (NULL); @@ -288,14 +387,12 @@ struct xran_section_info *xran_cp_find_section_info(void *pHandle, * The pointer of section information in the list * NULL if reached at the end of the list */ -struct xran_section_info *xran_cp_iterate_section_info(void *pHandle, - uint8_t dir, uint8_t cc_id, uint8_t ruport_id, - uint8_t ctx_id, uint32_t *next) +struct xran_section_info * +xran_cp_iterate_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id, uint32_t *next) { - int index; + int32_t index; struct xran_sectioninfo_db *ptr; - ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id); if(unlikely(ptr == NULL)) return (NULL); @@ -331,12 +428,12 @@ struct xran_section_info *xran_cp_iterate_section_info(void *pHandle, * The size of stored entries * -1 if failed to find matched database */ -int32_t xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id) +int32_t +xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id) { - int index; + int32_t index; struct xran_sectioninfo_db *ptr; - ptr = xran_get_section_db(pHandle, dir, cc_id, ruport_id, ctx_id); if(unlikely(ptr == NULL)) return (-1); @@ -363,7 +460,8 @@ int32_t xran_cp_getsize_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PARM if failed to find matched database */ -int xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id) +int32_t +xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id) { struct xran_sectioninfo_db *ptr; @@ -377,13 +475,6 @@ int xran_cp_reset_section_info(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_ return (XRAN_STATUS_SUCCESS); } - -int xran_dump_sectiondb(void) -{ - // TODO: - return (0); -} - int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination buffer */ uint16_t ext1_dst_len, /**< dest buffer size */ int16_t *p_bfw_iq_src, /**< source buffer of IQs */ @@ -468,11 +559,11 @@ int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination break; case XRAN_BFWCOMPMETHOD_ULAW: - rte_panic("XRAN_BFWCOMPMETHOD_BLKSCALE"); + rte_panic("XRAN_BFWCOMPMETHOD_ULAW"); break; case XRAN_BFWCOMPMETHOD_BEAMSPACE: - rte_panic("XRAN_BFWCOMPMETHOD_BLKSCALE"); + rte_panic("XRAN_BFWCOMPMETHOD_BEAMSPACE"); break; case XRAN_BFWCOMPMETHOD_NONE: @@ -495,10 +586,10 @@ int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination print_dbg("copy BF W %p -> %p size %d \n", p_bfw_iq_src, p_bfw_content, parm_size); if (p_ext1->bfwIqWidth == 0 || p_ext1->bfwIqWidth == 16){ - rte_memcpy(p_bfw_content, p_bfw_iq_src, parm_size); + memcpy(p_bfw_content, p_bfw_iq_src, parm_size); } else { bfp_com_rsp.data_out = (int8_t*)p_bfw_content; - if(xranlib_compress_avx512_bfw(&bfp_com_req, &bfp_com_rsp) == 0){ + if(xranlib_compress_bfw(&bfp_com_req, &bfp_com_rsp) == 0){ comp_len = bfp_com_rsp.len; print_dbg("comp_len %d parm_size %d\n", comp_len, parm_size); } else { @@ -514,7 +605,7 @@ int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination if(parm_size) { parm_size = XRAN_SECTIONEXT_ALIGN - parm_size; p_bfw_content = (uint8_t *)(p_bfw_content + parm_size); - rte_memcpy(p_bfw_content, zeropad, parm_size); + memcpy(p_bfw_content, zeropad, RTE_MIN(parm_size, sizeof(zeropad))); cur_ext_len += parm_size; print_dbg("zeropad %d cur_ext_len %d\n", parm_size, cur_ext_len); } @@ -536,26 +627,18 @@ int32_t xran_cp_populate_section_ext_1(int8_t *p_ext1_dst, /**< destination return (total_len); } - -// Cyclic Prefix Length 5.4.4.14 -// CP_length = cpLength * Ts, Ts = 1/30.72MHz -// i.e cpLength = CP_length / Ts ? -#define CPLEN_TS (30720000) -inline uint16_t xran_get_cplength(int CP_length) -{ - return (CP_length); -} - +// TODO: Need to decide to add calculation or not // Frequency offset 5.4.5.11 // frequency_offset = freqOffset * SCS * 0.5 // i.e freqOffset = (frequency_offset *2 )/ SCS ? -inline int32_t xran_get_freqoffset(int32_t freqOffset, int32_t scs) +inline int32_t +xran_get_freqoffset(int32_t freqOffset, int32_t scs) { return (freqOffset); } -static int xran_append_sectionext_1(struct rte_mbuf *mbuf, - struct xran_sectionext1_info *params, int last_flag) +static int32_t +xran_append_sectionext_1(struct rte_mbuf *mbuf, struct xran_sectionext1_info *params, int32_t last_flag) { int32_t total_len = 0; @@ -574,128 +657,15 @@ static int xran_append_sectionext_1(struct rte_mbuf *mbuf, return (total_len); } - -static int xran_prepare_sectionext_1(struct rte_mbuf *mbuf, - struct xran_sectionext1_info *params, int last_flag) -{ - struct xran_cp_radioapp_section_ext1 *ext1; - uint8_t *data; - int parm_size, iq_size; - int total_len; - - total_len = 0; - - print_dbg("%s %d\n", __FUNCTION__, last_flag); - - parm_size = sizeof(struct xran_cp_radioapp_section_ext1); - ext1 = (struct xran_cp_radioapp_section_ext1 *)rte_pktmbuf_append(mbuf, parm_size); - if(ext1 == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - - total_len += parm_size; - - ext1->extType = XRAN_CP_SECTIONEXTCMD_1; - ext1->ef = last_flag; - ext1->bfwCompMeth = params->bfwCompMeth; - ext1->bfwIqWidth = XRAN_CONVERT_BFWIQWIDTH(params->bfwiqWidth); - - switch(params->bfwCompMeth) { - case XRAN_BFWCOMPMETHOD_BLKFLOAT: - parm_size = 1; - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - total_len += parm_size; - *data = (params->bfwCompParam.exponent & 0x0f); - break; - - case XRAN_BFWCOMPMETHOD_BLKSCALE: - parm_size = 1; - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - total_len += parm_size; - *data = params->bfwCompParam.blockScaler; - break; - - case XRAN_BFWCOMPMETHOD_ULAW: - parm_size = 1; - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - total_len += parm_size; - *data = params->bfwCompParam.compBitWidthShift; - break; - - case XRAN_BFWCOMPMETHOD_BEAMSPACE: - parm_size = params->bfwNumber>>3; - if(params->bfwNumber%8) parm_size++; - parm_size *= 8; - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - rte_memcpy(data, params->bfwCompParam.activeBeamspaceCoeffMask, parm_size); - total_len += parm_size; - break; - - case XRAN_BFWCOMPMETHOD_NONE: - default: - parm_size = 0; - } - - print_dbg("params->bfwNumber %d params->bfwiqWidth %d\n", params->bfwNumber, params->bfwiqWidth); - - iq_size = params->bfwNumber * params->bfwiqWidth * 2; - - parm_size = iq_size>>3; - if(iq_size%8) - parm_size++; - - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 BF W iq_size: [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - rte_memcpy(data, params->p_bfwIQ, parm_size); - - total_len += parm_size; - parm_size = total_len % XRAN_SECTIONEXT_ALIGN; - if(parm_size) { - parm_size = XRAN_SECTIONEXT_ALIGN - parm_size; - data = (uint8_t *)rte_pktmbuf_append(mbuf, parm_size); - if(data == NULL) { - print_err("Fail to allocate the space for section extension 1 [%d]", parm_size); - return (XRAN_STATUS_RESOURCE); - } - rte_memcpy(data, zeropad, parm_size); - total_len += parm_size; - } - - ext1->extLen = total_len / XRAN_SECTIONEXT_ALIGN; - - return (total_len); -} - -static int xran_prepare_sectionext_2(struct rte_mbuf *mbuf, - struct xran_sectionext2_info *params, int last_flag) +static int32_t +xran_prepare_sectionext_2(struct rte_mbuf *mbuf, struct xran_sectionext2_info *params, int32_t last_flag) { struct xran_cp_radioapp_section_ext2 *ext2; uint8_t *data; - int total_len; - int parm_size; + int32_t total_len; + int32_t parm_size; uint32_t val, shift_val; - int val_size, pad_size; - + int32_t val_size, pad_size; total_len = 0; @@ -721,32 +691,28 @@ static int xran_prepare_sectionext_2(struct rte_mbuf *mbuf, if(params->bfAzPtWidth) { val += params->bfAzPt & bitmask[params->bfAzPtWidth]; shift_val += 8 - (params->bfAzPtWidth+1); - } - else + } else shift_val += 8; if(params->bfZePtWidth) { val = val << (params->bfZePtWidth+1); val += params->bfZePt & bitmask[params->bfZePtWidth]; shift_val += 8 - (params->bfZePtWidth+1); - } - else + } else shift_val += 8; if(params->bfAz3ddWidth) { val = val << (params->bfAz3ddWidth+1); val += params->bfAz3dd & bitmask[params->bfAz3ddWidth]; shift_val += 8 - (params->bfAz3ddWidth+1); - } - else + } else shift_val += 8; if(params->bfZe3ddWidth) { val = val << (params->bfZe3ddWidth+1); val += params->bfZe3dd & bitmask[params->bfZe3ddWidth]; shift_val += 8 - (params->bfZe3ddWidth+1); - } - else + } else shift_val += 8; if(val) { @@ -772,11 +738,11 @@ static int xran_prepare_sectionext_2(struct rte_mbuf *mbuf, return (XRAN_STATUS_RESOURCE); } - rte_memcpy(data, &val, val_size); + memcpy(data, &val, val_size); data += val_size; *data = ((params->bfAzSI) << 3) + (params->bfZeSI); data++; - rte_memcpy(data, zeropad, pad_size); + memcpy(data, zeropad, pad_size); ext2->extLen = total_len / XRAN_SECTIONEXT_ALIGN; *(uint32_t *)ext2 = rte_cpu_to_be_32(*(uint32_t *)ext2); @@ -784,54 +750,78 @@ static int xran_prepare_sectionext_2(struct rte_mbuf *mbuf, return (total_len); } -static int xran_prepare_sectionext_3(struct rte_mbuf *mbuf, - struct xran_sectionext3_info *params, int last_flag) +static int32_t +xran_prepare_sectionext_3(struct rte_mbuf *mbuf, struct xran_sectionext3_info *params, int32_t last_flag) { - int total_len; - int adj; - + int32_t total_len; + int32_t adj; + int32_t data_first_byte, data_second_byte; + int32_t data_third_byte, data_fourth_byte; + int32_t extLen; if(params->layerId == XRAN_LAYERID_0 || params->layerId == XRAN_LAYERID_TXD) { /* first data layer */ - struct xran_cp_radioapp_section_ext3_first *ext3_f; + union xran_cp_radioapp_section_ext3_first *ext3_f; uint64_t *tmp; - total_len = sizeof(struct xran_cp_radioapp_section_ext3_first); - ext3_f = (struct xran_cp_radioapp_section_ext3_first *)rte_pktmbuf_append(mbuf, total_len); + total_len = sizeof(union xran_cp_radioapp_section_ext3_first); + ext3_f = (union xran_cp_radioapp_section_ext3_first *)rte_pktmbuf_append(mbuf, total_len); if(ext3_f == NULL) { print_err("Fail to allocate the space for section extension 3"); return (XRAN_STATUS_RESOURCE); } - ext3_f->layerId = params->layerId; - ext3_f->ef = last_flag; - ext3_f->extType = XRAN_CP_SECTIONEXTCMD_3; - ext3_f->crsSymNum = params->crsSymNum; - ext3_f->crsShift = params->crsShift; - ext3_f->crsReMask = params->crsReMask; - ext3_f->txScheme = params->txScheme; - ext3_f->numLayers = params->numLayers; - ext3_f->codebookIndex = params->codebookIdx; + /*ext3_f->data_field.data_field1 = _mm_setzero_si128(); + + ext3_f->all_bits.layerId = params->layerId; + ext3_f->all_bits.ef = last_flag; + ext3_f->all_bits.extType = XRAN_CP_SECTIONEXTCMD_3; + ext3_f->all_bits.crsSymNum = params->crsSymNum; + ext3_f->all_bits.crsShift = params->crsShift; + ext3_f->all_bits.crsReMask = params->crsReMask; + ext3_f->all_bits.txScheme = params->txScheme; + ext3_f->all_bits.numLayers = params->numLayers; + ext3_f->all_bits.codebookIndex = params->codebookIdx; if(params->numAntPort == 2) { - ext3_f->beamIdAP3 = params->beamIdAP1; - ext3_f->beamIdAP2 = 0; - ext3_f->beamIdAP1 = 0; - ext3_f->extLen = 3; + ext3_f->all_bits.beamIdAP3 = params->beamIdAP1; + ext3_f->all_bits.extLen = 3; adj = 4; total_len -= adj; } else { - ext3_f->beamIdAP3 = params->beamIdAP1; - ext3_f->beamIdAP2 = params->beamIdAP2; - ext3_f->beamIdAP1 = params->beamIdAP3; - ext3_f->extLen = 4; + ext3_f->all_bits.beamIdAP3 = params->beamIdAP1; + ext3_f->all_bits.beamIdAP2 = params->beamIdAP2; + ext3_f->all_bits.beamIdAP1 = params->beamIdAP3; + ext3_f->all_bits.extLen = 4; + adj = 0; + }*/ + + if(params->numAntPort == 2) { + data_third_byte = 0; + extLen = 3; + adj = 4; + total_len -= adj; + }else + { + data_third_byte = (params->beamIdAP2 << 16) | params->beamIdAP3; + extLen = 4; adj = 0; } - ext3_f->reserved0 = 0; - ext3_f->reserved1 = 0; - ext3_f->reserved2 = 0; + + data_first_byte = (params->txScheme << xran_cp_radioapp_sec_ext3_TxScheme) + | (params->crsReMask << xran_cp_radioapp_sec_ext3_CrcReMask) + | (params->crsShift << xran_cp_radioapp_sec_ext3_CrcShift) + | (params->crsSymNum << xran_cp_radioapp_sec_ext3_CrcSymNum); + data_second_byte = (last_flag << xran_cp_radioapp_sec_ext3_EF) + | (XRAN_CP_SECTIONEXTCMD_3 << xran_cp_radioapp_sec_ext3_ExtType) + | (extLen << xran_cp_radioapp_sec_ext3_ExtLen) + | (params->codebookIdx << xran_cp_radioapp_sec_ext3_CodebookIdx) + | (params->layerId << xran_cp_radioapp_sec_ext3_LayerId) + | (params->numLayers << xran_cp_radioapp_sec_ext3_NumLayers); + data_fourth_byte = params->beamIdAP1; + ext3_f->data_field.data_field1 = _mm_set_epi32(data_fourth_byte, data_third_byte, data_second_byte, data_first_byte); /* convert byte order */ tmp = (uint64_t *)ext3_f; @@ -842,22 +832,29 @@ static int xran_prepare_sectionext_3(struct rte_mbuf *mbuf, rte_pktmbuf_trim(mbuf, adj); } else { /* non-first data layer */ - struct xran_cp_radioapp_section_ext3_non_first *ext3_nf; + union xran_cp_radioapp_section_ext3_non_first *ext3_nf; - total_len = sizeof(struct xran_cp_radioapp_section_ext3_non_first); - ext3_nf = (struct xran_cp_radioapp_section_ext3_non_first *)rte_pktmbuf_append(mbuf, total_len); + total_len = sizeof(union xran_cp_radioapp_section_ext3_non_first); + ext3_nf = (union xran_cp_radioapp_section_ext3_non_first *)rte_pktmbuf_append(mbuf, total_len); if(ext3_nf == NULL) { print_err("Fail to allocate the space for section extension 3"); return (XRAN_STATUS_RESOURCE); } - ext3_nf->layerId = params->layerId; - ext3_nf->ef = last_flag; - ext3_nf->extType = XRAN_CP_SECTIONEXTCMD_3; - ext3_nf->numLayers = params->numLayers; - ext3_nf->codebookIndex = params->codebookIdx; + /*ext3_nf->all_bits.layerId = params->layerId; + ext3_nf->all_bits.ef = last_flag; + ext3_nf->all_bits.extType = XRAN_CP_SECTIONEXTCMD_3; + ext3_nf->all_bits.numLayers = params->numLayers; + ext3_nf->all_bits.codebookIndex = params->codebookIdx; - ext3_nf->extLen = sizeof(struct xran_cp_radioapp_section_ext3_non_first)/XRAN_SECTIONEXT_ALIGN; + ext3_nf->all_bits.extLen = sizeof(union xran_cp_radioapp_section_ext3_non_first)/XRAN_SECTIONEXT_ALIGN;*/ + + ext3_nf->data_field = (last_flag << xran_cp_radioapp_sec_ext3_EF) + | (XRAN_CP_SECTIONEXTCMD_3 << xran_cp_radioapp_sec_ext3_ExtType) + | ((sizeof(union xran_cp_radioapp_section_ext3_non_first)/XRAN_SECTIONEXT_ALIGN) << xran_cp_radioapp_sec_ext3_ExtLen) + | (params->codebookIdx << xran_cp_radioapp_sec_ext3_CodebookIdx) + | (params->layerId << xran_cp_radioapp_sec_ext3_LayerId) + | (params->numLayers << xran_cp_radioapp_sec_ext3_NumLayers); *(uint32_t *)ext3_nf = rte_cpu_to_be_32(*(uint32_t *)ext3_nf); } @@ -865,16 +862,11 @@ static int xran_prepare_sectionext_3(struct rte_mbuf *mbuf, return (total_len); } -static int xran_prepare_sectionext_4(struct rte_mbuf *mbuf, - struct xran_sectionext4_info *params, int last_flag) +static int32_t +xran_prepare_sectionext_4(struct rte_mbuf *mbuf, struct xran_sectionext4_info *params, int32_t last_flag) { struct xran_cp_radioapp_section_ext4 *ext4; - int parm_size; - int total_len; - int ret; - - - total_len = 0; + int32_t parm_size; parm_size = sizeof(struct xran_cp_radioapp_section_ext4); ext4 = (struct xran_cp_radioapp_section_ext4 *)rte_pktmbuf_append(mbuf, parm_size); @@ -882,31 +874,27 @@ static int xran_prepare_sectionext_4(struct rte_mbuf *mbuf, print_err("Fail to allocate the space for section extension 4"); return(XRAN_STATUS_RESOURCE); } - else { - total_len += parm_size; ext4->extType = XRAN_CP_SECTIONEXTCMD_4; ext4->ef = last_flag; ext4->modCompScaler = params->modCompScaler; ext4->csf = params->csf?1:0; - ext4->extLen = total_len / XRAN_SECTIONEXT_ALIGN; + ext4->extLen = parm_size / XRAN_SECTIONEXT_ALIGN; *(uint32_t *)ext4 = rte_cpu_to_be_32(*(uint32_t*)ext4); - } - return (total_len); + return (parm_size); } -static int xran_prepare_sectionext_5(struct rte_mbuf *mbuf, - struct xran_sectionext5_info *params, int last_flag) +static int32_t +xran_prepare_sectionext_5(struct rte_mbuf *mbuf, struct xran_sectionext5_info *params, int32_t last_flag) { struct xran_cp_radioapp_section_ext_hdr *ext_hdr; struct xran_cp_radioapp_section_ext5 ext5; - int padding; - int total_len; + int32_t padding; + int32_t total_len; uint8_t *data; - int i; - + int32_t i; if(params->num_sets > XRAN_MAX_MODCOMP_ADDPARMS) { print_err("Exceeds maximum number of parameters(%d). Skipping.", params->num_sets); @@ -948,7 +936,7 @@ static int xran_prepare_sectionext_5(struct rte_mbuf *mbuf, // adding two sets at once (due to the definition of structure) *((uint64_t *)&ext5) = rte_cpu_to_be_64(*((uint64_t *)&ext5)); - rte_memcpy(data, &ext5, sizeof(struct xran_cp_radioapp_section_ext5)); + memcpy(data, &ext5, sizeof(struct xran_cp_radioapp_section_ext5)); data += sizeof(struct xran_cp_radioapp_section_ext5); } else { // even index @@ -960,7 +948,7 @@ static int xran_prepare_sectionext_5(struct rte_mbuf *mbuf, if(i == params->num_sets) { // adding last even index *((uint64_t *)&ext5) = rte_cpu_to_be_64(*((uint64_t *)&ext5)); - rte_memcpy(data, &ext5, sizeof(struct xran_cp_radioapp_section_ext5)/2); + memcpy(data, &ext5, sizeof(struct xran_cp_radioapp_section_ext5)/2); data += sizeof(struct xran_cp_radioapp_section_ext5)/2; break; } @@ -969,7 +957,395 @@ static int xran_prepare_sectionext_5(struct rte_mbuf *mbuf, /* zero padding */ if(padding) - rte_memcpy(data, zeropad, padding); + memcpy(data, zeropad, padding); + + return (total_len); +} + +static int32_t +xran_prepare_sectionext_6(struct rte_mbuf *mbuf, + struct xran_sectionext6_info *params, int32_t last_flag) +{ + union xran_cp_radioapp_section_ext6 *ext6; + int32_t parm_size; + + parm_size = sizeof(union xran_cp_radioapp_section_ext6); + ext6 = (union xran_cp_radioapp_section_ext6 *)rte_pktmbuf_append(mbuf, parm_size); + if(ext6 == NULL) { + print_err("Fail to allocate the space for section extension 6"); + return(XRAN_STATUS_RESOURCE); + } + + ext6->data_field.data_field1 = 0x0LL; + ext6->all_bits.extType = XRAN_CP_SECTIONEXTCMD_6; + ext6->all_bits.ef = last_flag; + ext6->all_bits.rbgSize = params->rbgSize; + ext6->all_bits.rbgMask = params->rbgMask; + ext6->all_bits.symbolMask = params->symbolMask; + ext6->all_bits.extLen = parm_size / XRAN_SECTIONEXT_ALIGN; + //ext6->reserved0 = 0; + //ext6->reserved1 = 0; + + *(uint64_t *)ext6 = rte_cpu_to_be_64(*(uint64_t*)ext6); + + return (parm_size); +} + +static int32_t +xran_prepare_sectionext_10(struct rte_mbuf *mbuf, + struct xran_sectionext10_info *params, int32_t last_flag) +{ + union xran_cp_radioapp_section_ext10 *ext10; + int32_t parm_size; + int32_t total_len; + int32_t padding; + int32_t i; + uint16_t *id_ptr; + + +#if (XRAN_STRICT_PARM_CHECK) + if(params->beamGrpType != XRAN_BEAMGT_COMMON + && params->beamGrpType != XRAN_BEAMGT_MATRIXIND + && params->beamGrpType != XRAN_BEAMGT_VECTORLIST) { + print_err("Invalid beam group Type - %d\n", params->beamGrpType); + return (XRAN_STATUS_INVALID_PARAM); + } +#endif + /* should be checked since it will be used for the index of array */ + if(params->numPortc > XRAN_MAX_NUMPORTC_EXT10) { + print_err("Invalid Number of eAxC in extension 10 - %d\n", params->numPortc); + return (XRAN_STATUS_INVALID_PARAM); + } + + parm_size = sizeof(union xran_cp_radioapp_section_ext10); + ext10 = (union xran_cp_radioapp_section_ext10 *)rte_pktmbuf_append(mbuf, parm_size); + if(ext10 == NULL) { + print_err("Fail to allocate the space for section extension 10"); + return(XRAN_STATUS_RESOURCE); + } + + ext10->all_bits.extType = XRAN_CP_SECTIONEXTCMD_10; + ext10->all_bits.ef = last_flag; + ext10->all_bits.numPortc = params->numPortc; + ext10->all_bits.beamGroupType = params->beamGrpType; + ext10->all_bits.reserved = 0; + + total_len = parm_size; + + if(params->beamGrpType == XRAN_BEAMGT_VECTORLIST) { + /* Calculate required size, it needs to be reduced by one byte + * since beam ID starts from reserved field(fourth octet). */ + parm_size = params->numPortc * 2 - 1; + + /* for alignment */ + padding = (parm_size + total_len) % XRAN_SECTIONEXT_ALIGN; + if(padding) { + padding = XRAN_SECTIONEXT_ALIGN - padding; + parm_size += padding; + } + + id_ptr = (uint16_t *)rte_pktmbuf_append(mbuf, parm_size); + if(id_ptr == NULL) { + print_err("Fail to allocate the space for beam IDs in section extension 10"); + return(XRAN_STATUS_RESOURCE); + } + + /* Need to advance pointer by one-byte since beam IDs start from fourth octet */ + id_ptr = (uint16_t *)(((uint8_t *)id_ptr) - 1); + + /* this might not be optimal since the alignment is broken */ + for(i = 0; i < params->numPortc; i++) + id_ptr[i] = rte_cpu_to_be_16(params->beamID[i]); + + /* zero padding */ + if(padding) + memcpy((uint8_t *)&id_ptr[params->numPortc], zeropad, padding); + } + + total_len += parm_size; + ext10->all_bits.extLen = total_len / XRAN_SECTIONEXT_ALIGN; + + ext10->data_field = 0; + ext10->data_field = (XRAN_CP_SECTIONEXTCMD_10 << xran_cp_radioapp_sec_ext10_ExtType) + | (last_flag << xran_cp_radioapp_sec_ext10_EF) + | ((total_len / XRAN_SECTIONEXT_ALIGN) << xran_cp_radioapp_sec_ext10_ExtLen) + | (params->numPortc << xran_cp_radioapp_sec_ext10_NumPortc) + | (params->beamGrpType << xran_cp_radioapp_sec_ext10_BeamGroupType); + + + return (total_len); +} + +/** + * @brief Estimates how many BFW sets can be fit to given MTU size + * + * @ingroup xran_cp_pkt + * + * @param numBFW the number of BFW I/Qs + * @param iqWidth the bitwidth of BFW + * @param compMeth Compression method for BFW + * @param mtu MTU size + * + * @return + * the number of maximum set of BFWs on success + * XRAN_STATUS_INVALID_PARAM, if compression method is not supported. + */ +int32_t +xran_cp_estimate_max_set_bfws(uint8_t numBFWs, uint8_t iqWidth, uint8_t compMeth, uint16_t mtu) +{ + int32_t avail_len; + int32_t bfw_bitsize; + int32_t bundle_size; + + /* Exclude headers can be present */ + avail_len = mtu - ( RTE_PKTMBUF_HEADROOM \ + + sizeof(struct xran_ecpri_hdr) \ + + sizeof(struct xran_cp_radioapp_common_header) \ + + sizeof(struct xran_cp_radioapp_section1) \ + + sizeof(union xran_cp_radioapp_section_ext6) \ + + sizeof(union xran_cp_radioapp_section_ext10) ); + + /* Calculate the size of BFWs I/Q in bytes */ + bfw_bitsize = numBFWs * iqWidth * 2; + bundle_size = bfw_bitsize>>3; + if(bfw_bitsize%8) bundle_size++; + + bundle_size += 2; /* two bytes for Beam ID */ + switch(compMeth) { + case XRAN_BFWCOMPMETHOD_NONE: + break; + + case XRAN_BFWCOMPMETHOD_BLKFLOAT: + bundle_size += 1; /* for bfwCompParam */ + break; + + default: + print_err("Compression method %d is not supported!", compMeth); + return (XRAN_STATUS_INVALID_PARAM); + } + + return (avail_len / bundle_size); +} + +inline static uint32_t +xran_cp_get_hdroffset_section1(uint32_t exthdr_size) +{ + uint32_t hdr_len; + + hdr_len = ( RTE_PKTMBUF_HEADROOM \ + + sizeof(struct xran_ecpri_hdr) \ + + sizeof(struct xran_cp_radioapp_common_header) \ + + sizeof(struct xran_cp_radioapp_section1) \ + + exthdr_size ); + return (hdr_len); +} + +/** + * @brief Prepare Beam Forming Weights(BFWs) for Section Extension 11 + * Copy sets of BFWs to buffer after compression if required. + * + * @ingroup xran_cp_pkt + * + * @param numSetBFW the number of set of BFWs + * @param numBFW the number of BFWs in a set + * @param iqWidth the bitwidth of BFW + * @param compMeth Compression method for BFW + * @param bfwIQ the array of BFW I/Q source + * @param dst the pointer of destination buffer (external buffer) + * @param dst_maxlen the maximum length of destination buffer + * need to exclude headroom from MTU + * @param bfwInfo Extension 11 PRB bundle information array. + * BFW size, offset and pointer will be set. + * + * @return + * XRAN_STATUS_SUCCESS on success + * XRAN_STATUS_RESOURCE, if destination memory is not enough to store all BFWs + */ +int32_t xran_cp_prepare_ext11_bfws(uint8_t numSetBFW, uint8_t numBFW, + uint8_t iqWidth, uint8_t compMeth, + uint8_t *dst, int16_t dst_maxlen, + struct xran_ext11_bfw_info bfwInfo[]) +{ + int32_t i; + int32_t iq_bitsize, iq_size; + int32_t parm_size; + int32_t total_len; + uint32_t hdr_offset; + uint8_t *ptr; + + struct xranlib_compress_request bfpComp_req; + struct xranlib_compress_response bfpComp_rsp; + + if(dst == NULL) { + print_err("Invalid destination pointer!"); + return (XRAN_STATUS_INVALID_PARAM); + } + + /* Calculate the size of BFWs I/Q in bytes */ + iq_bitsize = numBFW * iqWidth * 2; + iq_size = iq_bitsize>>3; + if(iq_bitsize%8) + iq_size++; + + /* Check maximum size */ + parm_size = ((compMeth == XRAN_BFWCOMPMETHOD_NONE)?0:1) + 2; /* bfwCompParam + beamID(2) */ + total_len = numSetBFW * (parm_size + iq_size); + + if(total_len >= dst_maxlen) { + print_err("Exceed maximum length to fit the set of BFWs - (%d/%d)", + total_len, dst_maxlen); + return (XRAN_STATUS_RESOURCE); + } + + hdr_offset = xran_cp_get_hdroffset_section1(sizeof(union xran_cp_radioapp_section_ext11)); + + /* Copy BFWs to destination buffer */ + ptr = dst + hdr_offset + 2; + switch(compMeth) { + /* No compression */ + case XRAN_BFWCOMPMETHOD_NONE: + for(i = 0; i < numSetBFW; i++) { + *((uint16_t *)ptr) = rte_cpu_to_be_16((bfwInfo[i].beamId & 0x7fff)); + memcpy((ptr + 2), bfwInfo[i].pBFWs, iq_size); + ptr += iq_size + 2; /* beam ID + IQ size */ + } + break; + + /* currently only supports BFP compression */ + case XRAN_BFWCOMPMETHOD_BLKFLOAT: + memset(&bfpComp_req, 0, sizeof(struct xranlib_compress_request)); + memset(&bfpComp_rsp, 0, sizeof(struct xranlib_compress_response)); + + for(i = 0; i < numSetBFW; i++) { + bfpComp_req.numRBs = 1; + bfpComp_req.numDataElements = numBFW*2; + bfpComp_req.len = numBFW*2*2; + bfpComp_req.compMethod = compMeth; + bfpComp_req.iqWidth = iqWidth; + bfpComp_req.data_in = (int16_t *)bfwInfo[i].pBFWs; + bfpComp_rsp.data_out = (int8_t*)(ptr + 2); /* exponent will be stored at first byte */ + + if(xranlib_compress_bfw(&bfpComp_req, &bfpComp_rsp) == 0) { + print_dbg("comp_len %d iq_size %d\n", bfpComp_rsp.len, iq_size); + } else { + print_err("compression failed\n"); + return (XRAN_STATUS_FAIL); + } + /* move exponent, it is stored at first byte of output */ + *ptr = *(ptr + 2); + + /* beamId */ + *((uint16_t *)(ptr+1)) = rte_cpu_to_be_16((bfwInfo[i].beamId & 0x7fff)); + ptr += iq_size + 3; + } + break; + + default: + print_err("Compression method %d is not supported!", compMeth); + return (XRAN_STATUS_INVALID_PARAM); + } + + /* Update the length of extension with padding */ + parm_size = (total_len + sizeof(union xran_cp_radioapp_section_ext11)) + % XRAN_SECTIONEXT_ALIGN; + if(parm_size) { + /* Add padding */ + parm_size = XRAN_SECTIONEXT_ALIGN - parm_size; + memcpy(ptr, zeropad, parm_size); + total_len += parm_size; + } + + return (total_len); +} + + +static void free_ext_buf(void *addr, void *opaque) +{ + /* free is not required for external buffers */ +} + +/* + * extbuf_start : the pointer of the external buffer, + * It can be the start address of whole external buffer. + * extbuf_len : total length of the external buffer (available space to access) + * To use the length of the data, offset2data should be zero. + * */ +int32_t xran_cp_attach_ext_buf(struct rte_mbuf *mbuf, + uint8_t *extbuf_start, uint16_t extbuf_len, + struct rte_mbuf_ext_shared_info *shinfo) +{ + rte_iova_t extbuf_iova; + + + if(unlikely(mbuf == NULL)) { + print_err("Invalid mbuf to attach!\n"); + return (XRAN_STATUS_INVALID_PARAM); + } + + /* Update shared information */ + shinfo->free_cb = free_ext_buf; + rte_mbuf_ext_refcnt_update(shinfo, 1); + + extbuf_iova = rte_malloc_virt2iova(extbuf_start); + if(unlikely(extbuf_iova == RTE_BAD_IOVA)) { + print_err("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + return (XRAN_STATUS_INVALID_PARAM); + } + + rte_pktmbuf_attach_extbuf(mbuf, extbuf_start, extbuf_iova, extbuf_len, shinfo); + + rte_pktmbuf_reset_headroom(mbuf); + + return (XRAN_STATUS_SUCCESS); +} + + +static int32_t +xran_prepare_sectionext_11(struct rte_mbuf *mbuf, + struct xran_sectionext11_info *params, int32_t last_flag) +{ + union xran_cp_radioapp_section_ext11 *ext11; + int32_t total_len; + + +#if (XRAN_STRICT_PARM_CHECK) + if(unlikely((params->numSetBFWs == 0) + || (params->numSetBFWs > XRAN_MAX_SET_BFWS))) { + print_err("Invalid number of the set of PRB bundle [%d]", params->numSetBFWs); + return (XRAN_STATUS_INVALID_PARAM); + } +#endif + + /* BFWs are already present in the external buffer, just update the length */ + total_len = sizeof(union xran_cp_radioapp_section_ext11) + params->totalBfwIQLen; + + ext11 = (union xran_cp_radioapp_section_ext11 *)rte_pktmbuf_append(mbuf, total_len); + if(ext11 == NULL) { + print_err("Fail to allocate the space for section extension 11 [%d]", total_len); + return (XRAN_STATUS_RESOURCE); + } + + /*ext11->all_bits.extType = XRAN_CP_SECTIONEXTCMD_11; + ext11->all_bits.ef = last_flag; + ext11->all_bits.reserved = 0; + ext11->all_bits.RAD = params->RAD; + ext11->all_bits.disableBFWs = params->disableBFWs; + ext11->all_bits.numBundPrb = params->numBundPrb; + ext11->all_bits.bfwCompMeth = params->bfwCompMeth; + ext11->all_bits.bfwIqWidth = XRAN_CONVERT_BFWIQWIDTH(params->bfwIqWidth); + + ext11->all_bits.extLen = total_len / XRAN_SECTIONEXT_ALIGN;*/ + + ext11->data_field.data_field1 = (last_flag << xran_cp_radioapp_sec_ext11_bitfield_Ef) + | (XRAN_CP_SECTIONEXTCMD_11 << xran_cp_radioapp_sec_ext11_bitfield_ExtType) + | ((total_len / XRAN_SECTIONEXT_ALIGN) << xran_cp_radioapp_sec_ext11_bitfield_ExtLen) + | (params->disableBFWs << xran_cp_radioapp_sec_ext11_bitfield_DisBFWs) + | (params->RAD << xran_cp_radioapp_sec_ext11_bitfield_RAD); + ext11->data_field.data_field2 = ((XRAN_CONVERT_BFWIQWIDTH(params->bfwIqWidth)) << xran_cp_radioapp_sec_ext11_bitfield_BFWIQWidth) + | (params->bfwCompMeth << xran_cp_radioapp_sec_ext11_bitfield_BFWCompMeth) + | params->numBundPrb; + + *(uint32_t *)ext11 = rte_cpu_to_be_32(*(uint32_t*)ext11); return (total_len); } @@ -986,12 +1362,12 @@ static int xran_prepare_sectionext_5(struct rte_mbuf *mbuf, * XRAN_STATUS_INVALID_PARM * XRAN_STATUS_RESOURCE if failed to allocate the space to packet buffer */ -int xran_append_section_extensions(struct rte_mbuf *mbuf, struct xran_section_gen_info *params) +int32_t xran_append_section_extensions(struct rte_mbuf *mbuf, struct xran_section_gen_info *params) { - int i, ret; + int32_t i, ret; uint32_t totalen; - int last_flag; - int ext_size; + int32_t last_flag; + int32_t ext_size; if(unlikely(params->exDataSize > XRAN_MAX_NUM_EXTENSIONS)) { print_err("Invalid total number of extensions - %d", params->exDataSize); @@ -1028,6 +1404,15 @@ int xran_append_section_extensions(struct rte_mbuf *mbuf, struct xran_section_ge case XRAN_CP_SECTIONEXTCMD_5: ext_size = xran_prepare_sectionext_5(mbuf, params->exData[i].data, last_flag); break; + case XRAN_CP_SECTIONEXTCMD_6: + ext_size = xran_prepare_sectionext_6(mbuf, params->exData[i].data, last_flag); + break; + case XRAN_CP_SECTIONEXTCMD_10: + ext_size = xran_prepare_sectionext_10(mbuf, params->exData[i].data, last_flag); + break; + case XRAN_CP_SECTIONEXTCMD_11: + ext_size = xran_prepare_sectionext_11(mbuf, params->exData[i].data, last_flag); + break; default: print_err("Extension Type %d is not supported!", params->exData[i].type); ret = XRAN_STATUS_INVALID_PARAM; @@ -1056,9 +1441,8 @@ int xran_append_section_extensions(struct rte_mbuf *mbuf, struct xran_section_ge * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PARM if the number of symbol is invalid */ -static int xran_prepare_section0( - struct xran_cp_radioapp_section0 *section, - struct xran_section_gen_info *params) +static int32_t +xran_prepare_section0(struct xran_cp_radioapp_section0 *section, struct xran_section_gen_info *params) { #if (XRAN_STRICT_PARM_CHECK) if(unlikely(params->info.numSymbol > XRAN_SYMBOLNUMBER_MAX)) { @@ -1067,11 +1451,11 @@ static int xran_prepare_section0( } #endif - section->hdr.sectionId = params->info.id; - section->hdr.rb = params->info.rb; - section->hdr.symInc = params->info.symInc; - section->hdr.startPrbc = params->info.startPrbc; - section->hdr.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); + section->hdr.u1.common.sectionId = params->info.id; + section->hdr.u1.common.rb = params->info.rb; + section->hdr.u1.common.symInc = params->info.symInc; + section->hdr.u1.common.startPrbc = params->info.startPrbc; + section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); section->hdr.u.s0.reMask = params->info.reMask; section->hdr.u.s0.numSymbol = params->info.numSymbol; @@ -1082,6 +1466,7 @@ static int xran_prepare_section0( return (XRAN_STATUS_SUCCESS); } + /** * @brief Fill the section header of type 0 in C-Plane packet * @@ -1092,10 +1477,9 @@ static int xran_prepare_section0( * @return * XRAN_STATUS_SUCCESS always */ -static int xran_prepare_section0_hdr( - struct xran_cp_radioapp_section0_header *s0hdr, +static int32_t +xran_prepare_section0_hdr( struct xran_cp_radioapp_section0_header *s0hdr, struct xran_cp_gen_params *params) - { s0hdr->timeOffset = rte_cpu_to_be_16(params->hdr.timeOffset); s0hdr->frameStructure.fftSize = params->hdr.fftSize; @@ -1118,8 +1502,8 @@ static int xran_prepare_section0_hdr( * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PARM if the number of symbol is invalid */ -static int xran_prepare_section1( - struct xran_cp_radioapp_section1 *section, +static int32_t +xran_prepare_section1(struct xran_cp_radioapp_section1 *section, struct xran_section_gen_info *params) { #if (XRAN_STRICT_PARM_CHECK) @@ -1129,23 +1513,33 @@ static int xran_prepare_section1( } #endif - section->hdr.sectionId = params->info.id; - section->hdr.rb = params->info.rb; - section->hdr.symInc = params->info.symInc; - section->hdr.startPrbc = params->info.startPrbc; - section->hdr.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); + /*section->hdr.u1.common.sectionId = params->info.id; + section->hdr.u1.common.rb = params->info.rb; + section->hdr.u1.common.symInc = params->info.symInc; + section->hdr.u1.common.startPrbc = params->info.startPrbc; + section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); section->hdr.u.s1.reMask = params->info.reMask; section->hdr.u.s1.numSymbol = params->info.numSymbol; section->hdr.u.s1.beamId = params->info.beamId; - - section->hdr.u.s1.ef = params->info.ef; + section->hdr.u.s1.ef = params->info.ef;*/ + + section->hdr.u.first_4byte = (params->info.reMask << xran_cp_radioapp_sec_hdr_sc_ReMask) + | (params->info.numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym) + | (params->info.ef << xran_cp_radioapp_sec_hdr_sc_Ef) + | (params->info.beamId << xran_cp_radioapp_sec_hdr_sc_BeamID); + section->hdr.u1.second_4byte = (params->info.id << xran_cp_radioapp_sec_hdr_c_SecId) + | (params->info.rb << xran_cp_radioapp_sec_hdr_c_RB) + | (params->info.symInc << xran_cp_radioapp_sec_hdr_c_SymInc) + | (params->info.startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc) + | ((XRAN_CONVERT_NUMPRBC(params->info.numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc); // for network byte order *((uint64_t *)section) = rte_cpu_to_be_64(*((uint64_t *)section)); return (XRAN_STATUS_SUCCESS); } + /** * @brief Fill the section header of type 1 in C-Plane packet * @@ -1156,8 +1550,8 @@ static int xran_prepare_section1( * @return * XRAN_STATUS_SUCCESS always */ -static int xran_prepare_section1_hdr( - struct xran_cp_radioapp_section1_header *s1hdr, +static int32_t +xran_prepare_section1_hdr(struct xran_cp_radioapp_section1_header *s1hdr, struct xran_cp_gen_params *params) { s1hdr->udComp.udIqWidth = params->hdr.iqWidth; @@ -1179,8 +1573,8 @@ static int xran_prepare_section1_hdr( * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PARM if the number of symbol is invalid */ -static int xran_prepare_section3( - struct xran_cp_radioapp_section3 *section, +static int32_t +xran_prepare_section3(struct xran_cp_radioapp_section3 *section, struct xran_section_gen_info *params) { #if (XRAN_STRICT_PARM_CHECK) @@ -1190,26 +1584,36 @@ static int xran_prepare_section3( } #endif - section->hdr.sectionId = params->info.id; - section->hdr.rb = params->info.rb; - section->hdr.symInc = params->info.symInc; - section->hdr.startPrbc = params->info.startPrbc; - section->hdr.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); + /*section->hdr.u1.common.sectionId = params->info.id; + section->hdr.u1.common.rb = params->info.rb; + section->hdr.u1.common.symInc = params->info.symInc; + section->hdr.u1.common.startPrbc = params->info.startPrbc; + section->hdr.u1.common.numPrbc = XRAN_CONVERT_NUMPRBC(params->info.numPrbc); section->hdr.u.s3.reMask = params->info.reMask; section->hdr.u.s3.numSymbol = params->info.numSymbol; section->hdr.u.s3.beamId = params->info.beamId; + section->hdr.u.s3.ef = params->info.ef;*/ + + section->hdr.u.first_4byte = (params->info.reMask << xran_cp_radioapp_sec_hdr_sc_ReMask) + | (params->info.numSymbol << xran_cp_radioapp_sec_hdr_sc_NumSym) + | (params->info.ef << xran_cp_radioapp_sec_hdr_sc_Ef) + | (params->info.beamId << xran_cp_radioapp_sec_hdr_sc_BeamID); + section->hdr.u1.second_4byte = (params->info.id << xran_cp_radioapp_sec_hdr_c_SecId) + | (params->info.rb << xran_cp_radioapp_sec_hdr_c_RB) + | (params->info.symInc << xran_cp_radioapp_sec_hdr_c_SymInc) + | (params->info.startPrbc << xran_cp_radioapp_sec_hdr_c_StartPrbc) + | ((XRAN_CONVERT_NUMPRBC(params->info.numPrbc)) << xran_cp_radioapp_sec_hdr_c_NumPrbc); section->freqOffset = rte_cpu_to_be_32(params->info.freqOffset)>>8; section->reserved = 0; - section->hdr.u.s3.ef = params->info.ef; - - // for network byte order (header, 8 bytes) + /* for network byte order (header, 8 bytes) */ *((uint64_t *)section) = rte_cpu_to_be_64(*((uint64_t *)section)); return (XRAN_STATUS_SUCCESS); } + /** * @brief Fill the section header of type 3 in C-Plane packet * @@ -1220,10 +1624,9 @@ static int xran_prepare_section3( * @return * XRAN_STATUS_SUCCESS always */ -static int xran_prepare_section3_hdr( - struct xran_cp_radioapp_section3_header *s3hdr, +static int32_t +xran_prepare_section3_hdr(struct xran_cp_radioapp_section3_header *s3hdr, struct xran_cp_gen_params *params) - { s3hdr->timeOffset = rte_cpu_to_be_16(params->hdr.timeOffset); s3hdr->frameStructure.fftSize = params->hdr.fftSize; @@ -1248,30 +1651,30 @@ static int xran_prepare_section3_hdr( * XRAN_STATUS_INVALID_PARM if section type is not 1 or 3, or handler is NULL * XRAN_STATUS_RESOURCE if failed to allocate the space to packet buffer */ -int xran_append_control_section(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params) +int32_t +xran_append_control_section(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params) { - int i, ret, ext_flag; + int32_t i, ret, ext_flag; uint32_t totalen; void *section; - int section_size; - int (*xran_prepare_section_func)(void *section, void *params); - + int32_t section_size; + int32_t (*xran_prepare_section_func)(void *section, void *params); totalen = 0; switch(params->sectionType) { case XRAN_CP_SECTIONTYPE_0: /* Unused RB or Symbols in DL or UL, not supportted */ section_size = sizeof(struct xran_cp_radioapp_section0); - xran_prepare_section_func = (int (*)(void *, void *))xran_prepare_section0; + xran_prepare_section_func = (int32_t (*)(void *, void *))xran_prepare_section0; break; case XRAN_CP_SECTIONTYPE_1: /* Most DL/UL Radio Channels */ section_size = sizeof(struct xran_cp_radioapp_section1); - xran_prepare_section_func = (int (*)(void *, void *))xran_prepare_section1; + xran_prepare_section_func = (int32_t (*)(void *, void *))xran_prepare_section1; break; case XRAN_CP_SECTIONTYPE_3: /* PRACH and Mixed-numerology Channels */ section_size = sizeof(struct xran_cp_radioapp_section3); - xran_prepare_section_func = (int (*)(void *, void *))xran_prepare_section3; + xran_prepare_section_func = (int32_t (*)(void *, void *))xran_prepare_section3; break; case XRAN_CP_SECTIONTYPE_5: /* UE scheduling information, not supported */ @@ -1328,8 +1731,8 @@ int xran_append_control_section(struct rte_mbuf *mbuf, struct xran_cp_gen_params * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PARM if direction, slot index or symbold index is invalid */ -static inline int xran_prepare_radioapp_common_header( - struct xran_cp_radioapp_common_header *apphdr, +static inline int32_t +xran_prepare_radioapp_common_header(struct xran_cp_radioapp_common_header *apphdr, struct xran_cp_gen_params *params) { @@ -1348,19 +1751,29 @@ static inline int xran_prepare_radioapp_common_header( } #endif - apphdr->dataDirection = params->dir; - apphdr->payloadVer = XRAN_PAYLOAD_VER; - apphdr->filterIndex = params->hdr.filterIdx; - apphdr->frameId = params->hdr.frameId; - apphdr->subframeId = params->hdr.subframeId; - apphdr->slotId = xran_slotid_convert(params->hdr.slotId, 0); - apphdr->startSymbolId = params->hdr.startSymId; + /*apphdr->field.all_bits = XRAN_PAYLOAD_VER << 28; + apphdr->field.dataDirection = params->dir; + //apphdr->field.payloadVer = XRAN_PAYLOAD_VER; + apphdr->field.filterIndex = params->hdr.filterIdx; + apphdr->field.frameId = params->hdr.frameId; + apphdr->field.subframeId = params->hdr.subframeId; + apphdr->field.slotId = xran_slotid_convert(params->hdr.slotId, 0); + apphdr->field.startSymbolId = params->hdr.startSymId;*/ + + apphdr->field.all_bits = (params->dir << xran_cp_radioapp_cmn_hdr_bitwidth_DataDir) + | (XRAN_PAYLOAD_VER << xran_cp_radioapp_cmn_hdr_bitwidth_PayLoadVer) + | (params->hdr.filterIdx << xran_cp_radioapp_cmn_hdr_bitwidth_FilterIdex) + | (params->hdr.frameId << xran_cp_radioapp_cmn_hdr_bitwidth_FrameId) + | (params->hdr.subframeId << xran_cp_radioapp_cmn_hdr_bitwidth_SubFrameId) + | (xran_slotid_convert(params->hdr.slotId, 0) << xran_cp_radioapp_cmn_hdr_bitwidth_SlotId) + | (params->hdr.startSymId << xran_cp_radioapp_cmn_hdr_bitwidth_StartSymId); + apphdr->numOfSections = params->numSections; apphdr->sectionType = params->sectionType; /* radio app header has common parts of 4bytes for all section types */ - *((uint32_t *)apphdr) = rte_cpu_to_be_32(*((uint32_t *)apphdr)); - + //*((uint32_t *)apphdr) = rte_cpu_to_be_32(*((uint32_t *)apphdr)); + *((uint32_t *)apphdr) = rte_cpu_to_be_32(apphdr->field.all_bits); return (XRAN_STATUS_SUCCESS); } @@ -1376,12 +1789,13 @@ static inline int xran_prepare_radioapp_common_header( * XRAN_STATUS_INVALID_PARM if section type is invalid, or handler is NULL * XRAN_STATUS_RESOURCE if failed to allocate the space to packet buffer */ -int xran_append_radioapp_header(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params) +int32_t +xran_append_radioapp_header(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params) { - int ret; + int32_t ret; uint32_t totalen; struct xran_cp_radioapp_common_header *apphdr; - int (*xran_prepare_radioapp_section_hdr_func)(void *hdr, void *params); + int32_t (*xran_prepare_radioapp_section_hdr_func)(void *hdr, void *params); #if (XRAN_STRICT_PARM_CHECK) @@ -1393,17 +1807,17 @@ int xran_append_radioapp_header(struct rte_mbuf *mbuf, struct xran_cp_gen_params switch(params->sectionType) { case XRAN_CP_SECTIONTYPE_0: /* Unused RB or Symbols in DL or UL, not supportted */ - xran_prepare_radioapp_section_hdr_func = (int (*)(void *, void*))xran_prepare_section0_hdr; + xran_prepare_radioapp_section_hdr_func = (int32_t (*)(void *, void*))xran_prepare_section0_hdr; totalen = sizeof(struct xran_cp_radioapp_section0_header); break; case XRAN_CP_SECTIONTYPE_1: /* Most DL/UL Radio Channels */ - xran_prepare_radioapp_section_hdr_func = (int (*)(void *, void*))xran_prepare_section1_hdr; + xran_prepare_radioapp_section_hdr_func = (int32_t (*)(void *, void*))xran_prepare_section1_hdr; totalen = sizeof(struct xran_cp_radioapp_section1_header); break; case XRAN_CP_SECTIONTYPE_3: /* PRACH and Mixed-numerology Channels */ - xran_prepare_radioapp_section_hdr_func = (int (*)(void *, void*))xran_prepare_section3_hdr; + xran_prepare_radioapp_section_hdr_func = (int32_t (*)(void *, void*))xran_prepare_section3_hdr; totalen = sizeof(struct xran_cp_radioapp_section3_header); break; @@ -1460,16 +1874,16 @@ int xran_append_radioapp_header(struct rte_mbuf *mbuf, struct xran_cp_gen_params * XRAN_STATUS_RESOURCE if failed to allocate the space to packet buffer * XRAN_STATUS_INVALID_PARM if section type is invalid */ -int xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf, +int32_t +xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params, uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id) { - int ret; + int32_t ret; uint32_t payloadlen; struct xran_ecpri_hdr *ecpri_hdr; - payloadlen = xran_build_ecpri_hdr(mbuf, CC_ID, Ant_ID, seq_id, &ecpri_hdr); ret = xran_append_radioapp_header(mbuf, params); @@ -1487,23 +1901,22 @@ int xran_prepare_ctrl_pkt(struct rte_mbuf *mbuf, payloadlen += ret; /* set payload length */ - ecpri_hdr->cmnhdr.ecpri_payl_size = rte_cpu_to_be_16(payloadlen); + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(payloadlen); return (XRAN_STATUS_SUCCESS); } - /////////////////////////////////////// // for RU emulation -int xran_parse_section_ext1(void *ext, - struct xran_sectionext1_info *extinfo) +int32_t +xran_parse_section_ext1(void *ext, struct xran_sectionext1_info *extinfo) { - int len; - int total_len; + int32_t len; + int32_t total_len; struct xran_cp_radioapp_section_ext1 *ext1; uint8_t *data; - int parm_size, iq_size; - int N; + int32_t parm_size, iq_size; + int32_t N; void *pHandle; pHandle = NULL; @@ -1517,7 +1930,7 @@ int xran_parse_section_ext1(void *ext, total_len = ext1->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ extinfo->bfwCompMeth = ext1->bfwCompMeth; - extinfo->bfwiqWidth = (ext1->bfwIqWidth==0)?16:ext1->bfwIqWidth; + extinfo->bfwIqWidth = (ext1->bfwIqWidth==0)?16:ext1->bfwIqWidth; len += sizeof(struct xran_cp_radioapp_section_ext1); data += sizeof(struct xran_cp_radioapp_section_ext1); @@ -1544,7 +1957,7 @@ int xran_parse_section_ext1(void *ext, case XRAN_BFWCOMPMETHOD_BEAMSPACE: parm_size = N>>3; if(N%8) parm_size++; parm_size *= 8; - rte_memcpy(data, extinfo->bfwCompParam.activeBeamspaceCoeffMask, parm_size); + memcpy(data, extinfo->bfwCompParam.activeBeamspaceCoeffMask, parm_size); break; default: @@ -1556,11 +1969,11 @@ int xran_parse_section_ext1(void *ext, data += parm_size; /* Get BF weights */ - iq_size = N * extinfo->bfwiqWidth * 2; // total in bits + iq_size = N * extinfo->bfwIqWidth * 2; // total in bits parm_size = iq_size>>3; // total in bytes (/8) if(iq_size%8) parm_size++; // round up - //rte_memcpy(data, extinfo->p_bfwIQ, parm_size); + //memcpy(data, extinfo->p_bfwIQ, parm_size); extinfo->p_bfwIQ = (int16_t*)data; len += parm_size; @@ -1576,17 +1989,16 @@ int xran_parse_section_ext1(void *ext, return (total_len); } -int xran_parse_section_ext2(void *ext, - struct xran_sectionext2_info *extinfo) +int32_t +xran_parse_section_ext2(void *ext, struct xran_sectionext2_info *extinfo) { - int len; - int total_len; + int32_t len; + int32_t total_len; struct xran_cp_radioapp_section_ext2 *ext2; uint8_t *data; - int parm_size; + int32_t parm_size; uint32_t val; - int val_size; - + int32_t val_size; ext2 = (struct xran_cp_radioapp_section_ext2 *)ext; data = (uint8_t *)ext; @@ -1658,11 +2070,11 @@ int xran_parse_section_ext2(void *ext, } -int xran_parse_section_ext3(void *ext, - struct xran_sectionext3_info *extinfo) +int32_t +xran_parse_section_ext3(void *ext, struct xran_sectionext3_info *extinfo) { - int len; - int total_len; + int32_t len; + int32_t total_len; total_len = 0; len = *((uint8_t *)ext + 1); @@ -1670,37 +2082,37 @@ int xran_parse_section_ext3(void *ext, switch(len) { case 1: /* non-first data layer */ { - struct xran_cp_radioapp_section_ext3_non_first *ext3_nf; + union xran_cp_radioapp_section_ext3_non_first *ext3_nf; - ext3_nf = (struct xran_cp_radioapp_section_ext3_non_first *)ext; + ext3_nf = (union xran_cp_radioapp_section_ext3_non_first *)ext; *(uint32_t *)ext3_nf = rte_be_to_cpu_32(*(uint32_t *)ext3_nf); - total_len = ext3_nf->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ + total_len = ext3_nf->all_bits.extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ - extinfo->codebookIdx= ext3_nf->codebookIndex; - extinfo->layerId = ext3_nf->layerId; - extinfo->numLayers = ext3_nf->numLayers; + extinfo->codebookIdx= ext3_nf->all_bits.codebookIndex; + extinfo->layerId = ext3_nf->all_bits.layerId; + extinfo->numLayers = ext3_nf->all_bits.numLayers; } break; case 3: /* first data layer with two antenna */ case 4: /* first data layer with four antenna */ { - struct xran_cp_radioapp_section_ext3_first *ext3_f; + union xran_cp_radioapp_section_ext3_first *ext3_f; uint16_t *beamid; - ext3_f = (struct xran_cp_radioapp_section_ext3_first *)ext; + ext3_f = (union xran_cp_radioapp_section_ext3_first *)ext; *(uint64_t *)ext3_f = rte_be_to_cpu_64(*(uint64_t *)ext3_f); - total_len = ext3_f->extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ + total_len = ext3_f->all_bits.extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ - extinfo->codebookIdx= ext3_f->codebookIndex; - extinfo->layerId = ext3_f->layerId; - extinfo->numLayers = ext3_f->numLayers; - extinfo->txScheme = ext3_f->txScheme; - extinfo->crsReMask = ext3_f->crsReMask; - extinfo->crsShift = ext3_f->crsShift; - extinfo->crsSymNum = ext3_f->crsSymNum; + extinfo->codebookIdx= ext3_f->all_bits.codebookIndex; + extinfo->layerId = ext3_f->all_bits.layerId; + extinfo->numLayers = ext3_f->all_bits.numLayers; + extinfo->txScheme = ext3_f->all_bits.txScheme; + extinfo->crsReMask = ext3_f->all_bits.crsReMask; + extinfo->crsShift = ext3_f->all_bits.crsShift; + extinfo->crsSymNum = ext3_f->all_bits.crsSymNum; /* beam IDs are stored from 10th octet */ beamid = (uint16_t *)((uint8_t *)ext + 10); @@ -1724,13 +2136,12 @@ int xran_parse_section_ext3(void *ext, return (total_len); } -int xran_parse_section_ext4(void *ext, - struct xran_sectionext4_info *extinfo) +int32_t +xran_parse_section_ext4(void *ext, struct xran_sectionext4_info *extinfo) { - int len; + int32_t len; struct xran_cp_radioapp_section_ext4 *ext4; - int total_len; - + int32_t total_len; ext4 = (struct xran_cp_radioapp_section_ext4 *)ext; @@ -1750,14 +2161,15 @@ int xran_parse_section_ext4(void *ext, return (total_len); } -int xran_parse_section_ext5(void *ext, +int32_t +xran_parse_section_ext5(void *ext, struct xran_sectionext5_info *extinfo) { - int len; + int32_t len; struct xran_cp_radioapp_section_ext_hdr *ext_hdr; struct xran_cp_radioapp_section_ext5 ext5; - int parm_size; - int total_len; + int32_t parm_size; + int32_t total_len; uint8_t *data; uint16_t i; @@ -1811,15 +2223,175 @@ int xran_parse_section_ext5(void *ext, return (total_len); } -int xran_parse_section_extension(struct rte_mbuf *mbuf, +int32_t +xran_parse_section_ext6(void *ext, + struct xran_sectionext6_info *extinfo) +{ + int32_t len; + union xran_cp_radioapp_section_ext6 *ext6; + int32_t total_len; + + ext6 = (union xran_cp_radioapp_section_ext6 *)ext; + *(uint64_t *)ext6 = rte_be_to_cpu_64(*(uint64_t *)ext6); + + total_len = ext6->all_bits.extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ + + extinfo->rbgSize = ext6->all_bits.rbgSize; + extinfo->rbgMask = ext6->all_bits.rbgMask; + extinfo->symbolMask = ext6->all_bits.symbolMask; + + len = sizeof(union xran_cp_radioapp_section_ext6); + if(len != total_len) { + print_err("The size of extension 6 is not correct! [%d:%d]", len, total_len); + } + + return (total_len); +} + +int32_t +xran_parse_section_ext10(void *ext, + struct xran_sectionext10_info *extinfo) +{ + int32_t len, padding; + int32_t i; + union xran_cp_radioapp_section_ext10 *ext10; + int32_t total_len; + uint16_t *ptr; + + ext10 = (union xran_cp_radioapp_section_ext10 *)ext; + + total_len = ext10->all_bits.extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ + + extinfo->numPortc = ext10->all_bits.numPortc; + extinfo->beamGrpType= ext10->all_bits.beamGroupType; + + len = sizeof(union xran_cp_radioapp_section_ext10); + if(ext10->all_bits.beamGroupType == XRAN_BEAMGT_VECTORLIST) { + len += extinfo->numPortc * 2 - 1; + padding = len % XRAN_SECTIONEXT_ALIGN; + if(padding) { + padding = XRAN_SECTIONEXT_ALIGN - padding; + len += padding; + } + + ptr = (uint16_t *)&ext10->all_bits.reserved; + for(i=0; i < extinfo->numPortc; i++) + extinfo->beamID[i] = rte_be_to_cpu_16(ptr[i]); + } + + if(len != total_len) { + print_err("The size of extension 10 is not correct! [%d:%d]", len, total_len); + } + + return (total_len); +} + +int32_t +xran_parse_section_ext11(void *ext, + struct xran_sectionext11_recv_info *extinfo) +{ + int32_t len; + int32_t total_len; + union xran_cp_radioapp_section_ext11 *ext11; + uint8_t *data; + int32_t parm_size, iq_size; + int32_t N; + void *pHandle; + + pHandle = NULL; + N = xran_get_conf_num_bfweights(pHandle); + + ext11 = (union xran_cp_radioapp_section_ext11 *)ext; + data = (uint8_t *)ext; + + *(uint32_t *)ext11 = rte_cpu_to_be_32(*(uint32_t*)ext11); + total_len = ext11->all_bits.extLen * XRAN_SECTIONEXT_ALIGN; /* from word to byte */ + + extinfo->RAD = ext11->all_bits.RAD; + extinfo->disableBFWs = ext11->all_bits.disableBFWs; + extinfo->numBundPrb = ext11->all_bits.numBundPrb; + extinfo->bfwCompMeth = ext11->all_bits.bfwCompMeth; + extinfo->bfwIqWidth = (ext11->all_bits.bfwIqWidth==0)?16:ext11->all_bits.bfwIqWidth; + + len = sizeof(union xran_cp_radioapp_section_ext11); + data += sizeof(union xran_cp_radioapp_section_ext11); + + extinfo->numSetBFWs = 0; + while((len+4) < total_len) { /* adding 4 is to consider zero pads */ + /* Get bfwCompParam */ + switch(ext11->all_bits.bfwCompMeth) { + case XRAN_BFWCOMPMETHOD_NONE: + parm_size = 0; + break; + + case XRAN_BFWCOMPMETHOD_BLKFLOAT: + parm_size = 1; + extinfo->bundInfo[extinfo->numSetBFWs].bfwCompParam.exponent = *data & 0x0f; + break; +#if 0 /* Not supported */ + case XRAN_BFWCOMPMETHOD_BLKSCALE: + parm_size = 1; + extinfo->bundInfo[extinfo->numSetBFWs].bfwCompParam.blockScaler = *data; + break; + + case XRAN_BFWCOMPMETHOD_ULAW: + parm_size = 1; + extinfo->bundInfo[extinfo->numSetBFWs].bfwCompParam.compBitWidthShift = *data; + break; + + case XRAN_BFWCOMPMETHOD_BEAMSPACE: + parm_size = N>>3; if(N%8) parm_size++; parm_size *= 8; + memcpy(data, extinfo->bundInfo[extinfo->numSetBFWs].bfwCompParam.activeBeamspaceCoeffMask, parm_size); + break; +#endif + default: + print_err("Invalid BfComp method - %d", ext11->all_bits.bfwCompMeth); + parm_size = 0; + } + len += parm_size; + data += parm_size; + + /* Get beam ID */ + extinfo->bundInfo[extinfo->numSetBFWs].beamId = rte_be_to_cpu_16(*((int16_t *)data)); + len += sizeof(int16_t); + data += sizeof(int16_t); + + /* Get BF weights */ + iq_size = N * extinfo->bfwIqWidth * 2; // total in bits + parm_size = iq_size>>3; // total in bytes (/8) + if(iq_size%8) parm_size++; // round up + + if(extinfo->bundInfo[extinfo->numSetBFWs].pBFWs) { + memcpy(extinfo->bundInfo[extinfo->numSetBFWs].pBFWs, data, parm_size); + } + extinfo->bundInfo[extinfo->numSetBFWs].BFWSize = parm_size; + + len += parm_size; + data += parm_size; + extinfo->numSetBFWs++; + } + + parm_size = len % XRAN_SECTIONEXT_ALIGN; + if(parm_size) + len += (XRAN_SECTIONEXT_ALIGN - parm_size); + + if(len != total_len) { + print_err("The size of extension 11 is not correct! [%d:%d]", len, total_len); + } + + return (total_len); +} + +int32_t +xran_parse_section_extension(struct rte_mbuf *mbuf, void *ext, - struct xran_section_gen_info *section) + struct xran_section_recv_info *section) { - int total_len, len, numext; + int32_t total_len, len, numext; uint8_t *ptr; - int flag_last; - int ext_type; - int i; + int32_t flag_last; + int32_t ext_type; + int32_t i; total_len = 0; ptr = (uint8_t *)ext; @@ -1833,28 +2405,31 @@ int xran_parse_section_extension(struct rte_mbuf *mbuf, flag_last = (*ptr & 0x80); ext_type = *ptr & 0x7f; - section->exData[numext].type = ext_type; + section->exts[numext].type = ext_type; switch(ext_type) { case XRAN_CP_SECTIONEXTCMD_1: - section->exData[numext].data = §ion->m_ext1[numext]; - len = xran_parse_section_ext1(ptr, section->exData[numext].data); - section->exData[numext].len = len; + len = xran_parse_section_ext1(ptr, §ion->exts[numext].u.ext1); break; case XRAN_CP_SECTIONEXTCMD_2: - section->exData[numext].data = §ion->m_ext2[numext]; - len = xran_parse_section_ext2(ptr, section->exData[numext].data); + len = xran_parse_section_ext2(ptr, §ion->exts[numext].u.ext2); break; case XRAN_CP_SECTIONEXTCMD_3: - section->exData[numext].data = §ion->m_ext3[numext]; - len = xran_parse_section_ext3(ptr, section->exData[numext].data); + len = xran_parse_section_ext3(ptr, §ion->exts[numext].u.ext3); break; case XRAN_CP_SECTIONEXTCMD_4: - section->exData[numext].data = §ion->m_ext4[numext]; - len = xran_parse_section_ext4(ptr, section->exData[numext].data); + len = xran_parse_section_ext4(ptr, §ion->exts[numext].u.ext4); break; case XRAN_CP_SECTIONEXTCMD_5: - section->exData[numext].data = §ion->m_ext5[numext]; - len = xran_parse_section_ext5(ptr, section->exData[numext].data); + len = xran_parse_section_ext5(ptr, §ion->exts[numext].u.ext5); + break; + case XRAN_CP_SECTIONEXTCMD_6: + len = xran_parse_section_ext6(ptr, §ion->exts[numext].u.ext6); + break; + case XRAN_CP_SECTIONEXTCMD_10: + len = xran_parse_section_ext10(ptr, §ion->exts[numext].u.ext10); + break; + case XRAN_CP_SECTIONEXTCMD_11: + len = xran_parse_section_ext11(ptr, §ion->exts[numext].u.ext11); break; default: @@ -1862,7 +2437,7 @@ int xran_parse_section_extension(struct rte_mbuf *mbuf, len = 0; } - section->exData[numext].len = len; + section->exts[numext].size = len; ptr += len; total_len += len; i++; @@ -1872,10 +2447,9 @@ int xran_parse_section_extension(struct rte_mbuf *mbuf, break; } - section->exDataSize = numext; + section->numExts = numext; return (total_len); - } /** @@ -1894,15 +2468,15 @@ int xran_parse_section_extension(struct rte_mbuf *mbuf, * XRAN_STATUS_SUCCESS on success * XRAN_STATUS_INVALID_PACKET if failed to parse the packet */ -int xran_parse_cp_pkt(struct rte_mbuf *mbuf, - struct xran_cp_gen_params *result, +int32_t +xran_parse_cp_pkt(struct rte_mbuf *mbuf, + struct xran_cp_recv_params *result, struct xran_recv_packet_info *pkt_info) { struct xran_ecpri_hdr *ecpri_hdr; struct xran_cp_radioapp_common_header *apphdr; - int i, ret; - int extlen; - + int32_t i, ret; + int32_t extlen; ret = xran_parse_ecpri_hdr(mbuf, &ecpri_hdr, pkt_info); if(ret < 0 && ecpri_hdr == NULL) @@ -1917,17 +2491,17 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, *((uint32_t *)apphdr) = rte_be_to_cpu_32(*((uint32_t *)apphdr)); - if(apphdr->payloadVer != XRAN_PAYLOAD_VER) { - print_err("Invalid Payload version - %d", apphdr->payloadVer); + if(apphdr->field.payloadVer != XRAN_PAYLOAD_VER) { + print_err("Invalid Payload version - %d", apphdr->field.payloadVer); ret = XRAN_STATUS_INVALID_PACKET; } - result->dir = apphdr->dataDirection; - result->hdr.filterIdx = apphdr->filterIndex; - result->hdr.frameId = apphdr->frameId; - result->hdr.subframeId = apphdr->subframeId; - result->hdr.slotId = apphdr->slotId; - result->hdr.startSymId = apphdr->startSymbolId; + result->dir = apphdr->field.dataDirection; + result->hdr.filterIdx = apphdr->field.filterIndex; + result->hdr.frameId = apphdr->field.frameId; + result->hdr.subframeId = apphdr->field.subframeId; + result->hdr.slotId = apphdr->field.slotId; + result->hdr.startSymId = apphdr->field.startSymbolId; result->sectionType = apphdr->sectionType; result->numSections = apphdr->numOfSections; @@ -1960,25 +2534,25 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section0_header)); if(section == NULL) { - print_err("Invalid packet 0 - radio app hedaer!"); + print_err("Invalid packet: section type0 - radio app hedaer!"); return (XRAN_STATUS_INVALID_PACKET); } for(i=0; inumSections; i++) { *((uint64_t *)section) = rte_be_to_cpu_64(*((uint64_t *)section)); result->sections[i].info.type = apphdr->sectionType; - result->sections[i].info.id = section->hdr.sectionId; - result->sections[i].info.rb = section->hdr.rb; - result->sections[i].info.symInc = section->hdr.symInc; - result->sections[i].info.startPrbc = section->hdr.startPrbc; - result->sections[i].info.numPrbc = section->hdr.numPrbc, + result->sections[i].info.id = section->hdr.u1.common.sectionId; + result->sections[i].info.rb = section->hdr.u1.common.rb; + result->sections[i].info.symInc = section->hdr.u1.common.symInc; + result->sections[i].info.startPrbc = section->hdr.u1.common.startPrbc; + result->sections[i].info.numPrbc = section->hdr.u1.common.numPrbc, result->sections[i].info.numSymbol = section->hdr.u.s0.numSymbol; result->sections[i].info.reMask = section->hdr.u.s0.reMask; //section->hdr.u.s0.reserved; /* should be zero */ section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section0)); if(section == NULL) { - print_err("Invalid packet 0 - number of section [%d:%d]!", + print_err("Invalid packet: section type0 - number of section [%d:%d]!", result->numSections, i); result->numSections = i; ret = XRAN_STATUS_INVALID_PACKET; @@ -2000,7 +2574,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section1_header)); if(section == NULL) { - print_err("Invalid packet 1 - radio app hedaer!"); + print_err("Invalid packet: section type1 - radio app hedaer!"); return (XRAN_STATUS_INVALID_PACKET); } @@ -2008,11 +2582,11 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, *((uint64_t *)section) = rte_be_to_cpu_64(*((uint64_t *)section)); result->sections[i].info.type = apphdr->sectionType; - result->sections[i].info.id = section->hdr.sectionId; - result->sections[i].info.rb = section->hdr.rb; - result->sections[i].info.symInc = section->hdr.symInc; - result->sections[i].info.startPrbc = section->hdr.startPrbc; - result->sections[i].info.numPrbc = section->hdr.numPrbc, + result->sections[i].info.id = section->hdr.u1.common.sectionId; + result->sections[i].info.rb = section->hdr.u1.common.rb; + result->sections[i].info.symInc = section->hdr.u1.common.symInc; + result->sections[i].info.startPrbc = section->hdr.u1.common.startPrbc; + result->sections[i].info.numPrbc = section->hdr.u1.common.numPrbc, result->sections[i].info.numSymbol = section->hdr.u.s1.numSymbol; result->sections[i].info.reMask = section->hdr.u.s1.reMask; result->sections[i].info.beamId = section->hdr.u.s1.beamId; @@ -2021,7 +2595,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section1)); if(section == NULL) { - print_err("Invalid packet 1 - number of section [%d:%d]!", + print_err("Invalid packet: section type1 - number of section [%d:%d]!", result->numSections, i); result->numSections = i; ret = XRAN_STATUS_INVALID_PACKET; @@ -2034,7 +2608,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, if(extlen > 0) { section = (void *)rte_pktmbuf_adj(mbuf, extlen); if(section == NULL) { - print_err("Invalid packet 1 - section extension [%d]!", i); + print_err("Invalid packet: section type1 - section extension [%d]!", i); ret = XRAN_STATUS_INVALID_PACKET; break; } @@ -2061,7 +2635,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section3_header)); if(section == NULL) { - print_err("Invalid packet 3 - radio app hedaer!"); + print_err("Invalid packet: section type3 - radio app hedaer!"); return (XRAN_STATUS_INVALID_PACKET); } @@ -2069,11 +2643,11 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, *((uint64_t *)section) = rte_be_to_cpu_64(*((uint64_t *)section)); result->sections[i].info.type = apphdr->sectionType; - result->sections[i].info.id = section->hdr.sectionId; - result->sections[i].info.rb = section->hdr.rb; - result->sections[i].info.symInc = section->hdr.symInc; - result->sections[i].info.startPrbc = section->hdr.startPrbc; - result->sections[i].info.numPrbc = section->hdr.numPrbc, + result->sections[i].info.id = section->hdr.u1.common.sectionId; + result->sections[i].info.rb = section->hdr.u1.common.rb; + result->sections[i].info.symInc = section->hdr.u1.common.symInc; + result->sections[i].info.startPrbc = section->hdr.u1.common.startPrbc; + result->sections[i].info.numPrbc = section->hdr.u1.common.numPrbc, result->sections[i].info.numSymbol = section->hdr.u.s3.numSymbol; result->sections[i].info.reMask = section->hdr.u.s3.reMask; result->sections[i].info.beamId = section->hdr.u.s3.beamId; @@ -2081,13 +2655,13 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, result->sections[i].info.freqOffset = ((int32_t)rte_be_to_cpu_32(section->freqOffset))>>8; if(section->reserved) { - print_err("Invalid packet 3 - section[%d:%d]", i, section->reserved); + print_err("Invalid packet: section type3 - section[%d] reserved[%d]", i, section->reserved); ret = XRAN_STATUS_INVALID_PACKET; } section = (void *)rte_pktmbuf_adj(mbuf, sizeof(struct xran_cp_radioapp_section3)); if(section == NULL) { - print_err("Invalid packet 3 - number of section [%d:%d]!", + print_err("Invalid packet: section type3 - number of section [%d:%d]!", result->numSections, i); result->numSections = i; ret = XRAN_STATUS_INVALID_PACKET; @@ -2100,7 +2674,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, if(extlen > 0) { section = (void *)rte_pktmbuf_adj(mbuf, extlen); if(section == NULL) { - print_err("Invalid packet 3 - section extension [%d]!", i); + print_err("Invalid packet: section type3 - section extension [%d]!", i); ret = XRAN_STATUS_INVALID_PACKET; break; } @@ -2140,7 +2714,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, result->sections[i].info.ef); if(result->sections[i].info.ef) { - for(int j=0; jsections[i].exDataSize; j++) { + for(int32_t j=0; jsections[i].exDataSize; j++) { printf(" || %2d : type=%d len=%d\n", j, result->sections[i].exData[j].type, result->sections[i].exData[j].len); switch(result->sections[i].exData[j].type) { @@ -2148,8 +2722,8 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, { struct xran_sectionext1_info *ext1; ext1 = result->sections[i].exData[j].data; - printf(" || bfwNumber=%d bfwiqWidth=%d bfwCompMeth=%d\n", - ext1->bfwNumber, ext1->bfwiqWidth, ext1->bfwCompMeth); + printf(" || bfwNumber=%d bfwIqWidth=%d bfwCompMeth=%d\n", + ext1->bfwNumber, ext1->bfwIqWidth, ext1->bfwCompMeth); } break; case XRAN_CP_SECTIONEXTCMD_2: @@ -2177,7 +2751,7 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, struct xran_sectionext5_info *ext5; ext5 = result->sections[i].exData[j].data; printf(" || num_sets=%d\n", ext5->num_sets); - for(int k=0; knum_sets; k++) { + for(int32_t k=0; knum_sets; k++) { printf(" || %d - csf=%d mcScaleReMask=%04x mcScaleOffset=%04x\n", k, ext5->mc[k].csf, ext5->mc[k].mcScaleReMask, ext5->mc[k].mcScaleOffset); @@ -2197,4 +2771,3 @@ int xran_parse_cp_pkt(struct rte_mbuf *mbuf, return(ret); } - diff --git a/fhi_lib/lib/src/xran_cp_proc.c b/fhi_lib/lib/src/xran_cp_proc.c new file mode 100644 index 0000000..e40ce72 --- /dev/null +++ b/fhi_lib/lib/src/xran_cp_proc.c @@ -0,0 +1,584 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN C plane processing functionality and helper functions + * @file xran_cp_proc.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xran_fh_o_du.h" + +#include "ethdi.h" +#include "xran_pkt.h" +#include "xran_up_api.h" +#include "xran_cp_api.h" +#include "xran_sync_api.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_timer.h" +#include "xran_common.h" +#include "xran_dev.h" +#include "xran_frame_struct.h" +#include "xran_printf.h" +#include "xran_app_frag.h" +#include "xran_cp_proc.h" +#include "xran_tx_proc.h" + +#include "xran_mlog_lnx.h" + +uint8_t xran_cp_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_DIR_MAX][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /* XRAN_MAX_ANTENNA_NR * 2 for PUSCH and PRACH */ +uint8_t xran_updl_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR]; +uint8_t xran_upul_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< PUSCH, PRACH, SRS for Cat B */ +uint8_t xran_section_id_curslot[XRAN_PORTS_NUM][XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; +uint16_t xran_section_id[XRAN_PORTS_NUM][XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; + +struct xran_recv_packet_info parse_recv[XRAN_PORTS_NUM]; + +////////////////////////////////////////// +// For RU emulation +struct xran_section_recv_info *recvSections[XRAN_PORTS_NUM] = {NULL,NULL,NULL,NULL}; +struct xran_cp_recv_params recvCpInfo[XRAN_PORTS_NUM]; + +static void +extbuf_free_callback(void *addr __rte_unused, void *opaque __rte_unused) +{ + /*long t1 = MLogTick(); + MLogTask(77777, t1, t1+100);*/ +} + +int32_t +xran_init_sectionid(void *pHandle) +{ + int cell, ant, dir; + struct xran_device_ctx* p_dev = NULL; + uint8_t xran_port_id = 0; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (-1); + } + + for (dir = 0; dir < XRAN_DIR_MAX; dir++){ + for(cell=0; cell < XRAN_MAX_CELLS_PER_PORT; cell++) { + for(ant=0; ant < XRAN_MAX_ANTENNA_NR; ant++) { + xran_section_id[xran_port_id][dir][cell][ant] = 0; + xran_section_id_curslot[xran_port_id][dir][cell][ant] = 255; + } + } + } + + return (0); +} + +int32_t +xran_init_seqid(void *pHandle) +{ + int cell, dir, ant; + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + + for(cell=0; cell < XRAN_MAX_CELLS_PER_PORT; cell++) { + for(dir=0; dir < XRAN_DIR_MAX; dir++) { + for(ant=0; ant < XRAN_MAX_ANTENNA_NR * 2; ant++) + xran_cp_seq_id_num[xran_port][cell][dir][ant] = 0; + } + for(ant=0; ant < XRAN_MAX_ANTENNA_NR; ant++) + xran_updl_seq_id_num[xran_port][cell][ant] = 0; + for(ant=0; ant < XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR; ant++) + xran_upul_seq_id_num[xran_port][cell][ant] = 0; + } + + return (0); +} + +int32_t +process_cplane(struct rte_mbuf *pkt, void* handle) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle; + + if(p_xran_dev_ctx) { + if(xran_dev_get_ctx_by_id(0)->fh_cfg.debugStop) /* check CP with standard tests only */ + xran_parse_cp_pkt(pkt, &recvCpInfo[p_xran_dev_ctx->xran_port_id], &parse_recv[p_xran_dev_ctx->xran_port_id]); + } + + return (MBUF_FREE); +} + +int32_t +xran_check_symbolrange(int symbol_type, uint32_t PortId, int cc_id, int tti, + int start_sym, int numsym_in, int *numsym_out) +{ + int i; + int first_pos, last_pos; + int start_pos, end_pos; + + first_pos = last_pos = -1; + + /* Find first symbol which is same with given symbol type */ + for(i=0; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++) + if(xran_fs_get_symbol_type(PortId, cc_id, tti, i) == symbol_type) { + first_pos = i; break; + } + + if(first_pos < 0) { +// for(i=0; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++) +// printf("symbol_type %d - %d:%d\n", symbol_type, i, xran_fs_get_symbol_type(cc_id, tti, i)); + *numsym_out = 0; + return (first_pos); + } + + /* Find the rest of consecutive symbols which are same with given symbol type */ + for( ; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++) + if(xran_fs_get_symbol_type(PortId, cc_id, tti, i) != symbol_type) + break; + last_pos = i; + + start_pos = (first_pos > start_sym) ? first_pos : start_sym; + end_pos = ((start_sym + numsym_in) > last_pos) ? last_pos : (start_sym + numsym_in); + *numsym_out = end_pos - start_pos; + + return (start_pos); +} + +struct rte_mbuf * +xran_attach_cp_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, + struct rte_mbuf_ext_shared_info * p_share_data) +{ + struct rte_mbuf *mb_oran_hdr_ext = NULL; + struct rte_mbuf *tmp = NULL; + int8_t *ext_buff = NULL; + rte_iova_t ext_buff_iova = 0; + + ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + ext_buff_len += (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)) + 18; + +// mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small); + mb_oran_hdr_ext = xran_ethdi_mbuf_indir_alloc(); + + if (unlikely (( mb_oran_hdr_ext) == NULL)) { + rte_panic("Failed rte_pktmbuf_alloc\n"); + } + + p_share_data->free_cb = extbuf_free_callback; + p_share_data->fcb_opaque = NULL; + rte_mbuf_ext_refcnt_set(p_share_data, 1); + + ext_buff_iova = rte_malloc_virt2iova(p_ext_buff_start); + if (unlikely (( ext_buff_iova) == 0)) { + rte_panic("Failed rte_mem_virt2iova \n"); + } + + if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { + rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + } + + rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext, + ext_buff, + ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start), + ext_buff_len, + p_share_data); + + rte_pktmbuf_reset_headroom(mb_oran_hdr_ext); + + return mb_oran_hdr_ext; +} + +int32_t +xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id, + struct xran_prb_map *prbMap, enum xran_category category, uint8_t ctx_id) +{ + int32_t ret = 0; + struct xran_device_ctx *p_x_ctx = (struct xran_device_ctx *)pHandle; + struct xran_common_counters *pCnt = &p_x_ctx->fh_counters; + struct xran_cp_gen_params params; + struct xran_section_gen_info sect_geninfo[1]; + struct rte_mbuf *mbuf; + uint32_t interval = p_x_ctx->interval_us_local; + uint8_t PortId = p_x_ctx->xran_port_id; + + + uint32_t i, j, loc_sym; + uint32_t nsection = 0; + struct xran_prb_elm *pPrbMapElem = NULL; + struct xran_prb_elm *pPrbMapElemPrev = NULL; + uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval)); + uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME); + uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval)); + + uint8_t seq_id = 0; + uint16_t vf_id = 0; + + int next; + struct xran_sectionext1_info ext1; + struct xran_sectionext4_info ext4 = {0}; + struct xran_sectionext11_info ext11; + + //frame_id = (frame_id & 0xff); /* ORAN frameId, 8 bits, [0, 255] */ + frame_id = ((frame_id + ((0 == tti)?NUM_OF_FRAMES_PER_SECOND:0)) & 0xff); /* ORAN frameId, 8 bits, [0, 255] */ + + if(prbMap) { + nsection = prbMap->nPrbElm; + pPrbMapElem = &prbMap->prbMap[0]; + } else { + print_err("prbMap is NULL\n"); + return (-1); + } + + /* Generate a C-Plane message per each section, + * not a C-Plane message with multi sections */ + for (i = 0; i < nsection; i++) { + int startSym, numSyms; + + pPrbMapElem = &prbMap->prbMap[i]; + + /* For Special Subframe, + * Check validity of given symbol range with slot configuration + * and adjust symbol range accordingly. */ + if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_FDD) != 1 + && xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1) { + /* This function cannot handle two or more groups of consecutive same type of symbol. + * If there are two or more, then it might cause an error */ + startSym = xran_check_symbolrange( + ((dir==XRAN_DIR_DL)?XRAN_SYMBOL_TYPE_DL:XRAN_SYMBOL_TYPE_UL), + PortId, cc_id, tti, + pPrbMapElem->nStartSymb, + pPrbMapElem->numSymb, &numSyms); + if(startSym < 0 || numSyms == 0) { + /* if start symbol is not valid, then skip this section */ + print_err("Skip section %d due to invalid symbol range - [%d:%d], [%d:%d]", + i, + pPrbMapElem->nStartSymb, pPrbMapElem->numSymb, + startSym, numSyms); + continue; + } + } else { + startSym = pPrbMapElem->nStartSymb; + numSyms = pPrbMapElem->numSymb; + } + + vf_id = xran_map_ecpriRtcid_to_vf(p_x_ctx, dir, cc_id, ru_port_id); + params.dir = dir; + params.sectionType = XRAN_CP_SECTIONTYPE_1; + params.hdr.filterIdx = XRAN_FILTERINDEX_STANDARD; + params.hdr.frameId = frame_id; + params.hdr.subframeId = subframe_id; + params.hdr.slotId = slot_id; + params.hdr.startSymId = startSym; + params.hdr.iqWidth = pPrbMapElem->iqWidth; + params.hdr.compMeth = pPrbMapElem->compMethod; + + print_dbg("cp[%d:%d:%d] ru_port_id %d dir=%d\n", + frame_id, subframe_id, slot_id, ru_port_id, dir); + + seq_id = xran_get_cp_seqid(pHandle, XRAN_DIR_DL, cc_id, ru_port_id); + + sect_geninfo[0].info.type = params.sectionType; + sect_geninfo[0].info.startSymId = params.hdr.startSymId; + sect_geninfo[0].info.iqWidth = params.hdr.iqWidth; + sect_geninfo[0].info.compMeth = params.hdr.compMeth; + + sect_geninfo[0].info.id = i; /* do not revert 'i' to + xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, slot_id); */ + + if(sect_geninfo[0].info.id > XRAN_MAX_SECTIONS_PER_SLOT) + print_err("sectinfo->id %d\n", sect_geninfo[0].info.id); +#if 0 + if (dir == XRAN_DIR_UL) { + for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) { + int32_t sec_desc_idx = pPrbMapElem->nSecDesc[loc_sym]; + struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym][0]; + if(p_sec_desc) { + p_sec_desc->section_id = sect_geninfo[0].info.id; + if(p_sec_desc->pCtrl) { + rte_pktmbuf_free(p_sec_desc->pCtrl); + p_sec_desc->pCtrl = NULL; + p_sec_desc->pData = NULL; + } + } + else { + print_err("section desc is NULL\n"); + } + sec_desc_idx--; + pPrbMapElem->nSecDesc[loc_sym] = 0; + } + } +#endif + + sect_geninfo[0].info.rb = XRAN_RBIND_EVERY; + sect_geninfo[0].info.startPrbc = pPrbMapElem->nRBStart; + sect_geninfo[0].info.numPrbc = pPrbMapElem->nRBSize; + sect_geninfo[0].info.numSymbol = numSyms; + sect_geninfo[0].info.reMask = 0xfff; + sect_geninfo[0].info.beamId = pPrbMapElem->nBeamIndex; + sect_geninfo[0].info.symInc = XRAN_SYMBOLNUMBER_NOTINC; + + for(loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++) { + struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym][0]; + if(p_sec_desc) { + p_sec_desc->section_id = sect_geninfo[0].info.id; + + sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset; + sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len; + } else { + print_err("section desc is NULL\n"); + } + } + + if(unlikely((category != XRAN_CATEGORY_A) && (category != XRAN_CATEGORY_B))) { + print_err("Unsupported Category %d\n", category); + return (-1); + } + + /* Add extentions if required */ + next = 0; + sect_geninfo[0].exDataSize = 0; + + /* Extension 4 for modulation compression */ + if(pPrbMapElem->compMethod == XRAN_COMPMETHOD_MODULATION) { + mbuf = xran_ethdi_mbuf_alloc(); + + ext4.csf = 0; //no shift for now only + ext4.modCompScaler = pPrbMapElem->ScaleFactor; + sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_4; + sect_geninfo[0].exData[next].len = sizeof(ext4); + sect_geninfo[0].exData[next].data = &ext4; + + sect_geninfo[0].info.ef = 1; + sect_geninfo[0].exDataSize++; + next++; + } + + /* Extension 1 or 11 for Beam forming weights */ + if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) { + /* add extantion section for BF Weights if update is needed */ + if(pPrbMapElem->bf_weight.numBundPrb == 0) { + /* No bundled PRBs, using Extension 1 */ + struct rte_mbuf_ext_shared_info * p_share_data = &p_x_ctx->cp_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info.id]; + + /*add extention section for BF Weights if update is needed */ + if(pPrbMapElem->bf_weight.p_ext_start) { + /* use buffer with BF Weights for mbuf */ + mbuf = xran_attach_cp_ext_buf(vf_id, pPrbMapElem->bf_weight.p_ext_start, + pPrbMapElem->bf_weight.p_ext_section, + pPrbMapElem->bf_weight.ext_section_sz, p_share_data); + } else { + print_err("p %d cc %d dir %d Alloc fail!\n", PortId, cc_id, dir); + return (-1); + } + + memset(&ext1, 0, sizeof (struct xran_sectionext1_info)); + ext1.bfwNumber = pPrbMapElem->bf_weight.nAntElmTRx; + ext1.bfwIqWidth = pPrbMapElem->iqWidth; + ext1.bfwCompMeth = pPrbMapElem->compMethod; + ext1.p_bfwIQ = (int16_t*)pPrbMapElem->bf_weight.p_ext_section; + ext1.bfwIQ_sz = pPrbMapElem->bf_weight.ext_section_sz; + + sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_1; + sect_geninfo[0].exData[next].len = sizeof(ext1); + sect_geninfo[0].exData[next].data = &ext1; + + sect_geninfo[0].info.ef = 1; + sect_geninfo[0].exDataSize++; + next++; + } else { /* if(pPrbMapElem->bf_weight.numBundPrb == 0) */ + /* Using Extension 11 */ + struct rte_mbuf_ext_shared_info *shared_info; + + shared_info = &p_x_ctx->bfw_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id][sect_geninfo[0].info.id]; + + + shared_info->free_cb = NULL; + shared_info->fcb_opaque = NULL; + + mbuf = xran_ethdi_mbuf_indir_alloc(); + if(unlikely(mbuf == NULL)) { + rte_panic("Alloc fail!\n"); + return (-1); + } + //mbuf = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]); + if(xran_cp_attach_ext_buf(mbuf, (uint8_t *)pPrbMapElem->bf_weight.p_ext_start, pPrbMapElem->bf_weight.maxExtBufSize, shared_info) < 0) { + rte_pktmbuf_free(mbuf); + return (-1); + } + + rte_mbuf_ext_refcnt_update(shared_info, 0); + + ext11.RAD = pPrbMapElem->bf_weight.RAD; + ext11.disableBFWs = pPrbMapElem->bf_weight.disableBFWs; + + ext11.numBundPrb = pPrbMapElem->bf_weight.numBundPrb; + ext11.numSetBFWs = pPrbMapElem->bf_weight.numSetBFWs; + + ext11.bfwCompMeth = pPrbMapElem->bf_weight.bfwCompMeth; + ext11.bfwIqWidth = pPrbMapElem->bf_weight.bfwIqWidth; + + ext11.maxExtBufSize = pPrbMapElem->bf_weight.maxExtBufSize; + ext11.pExtBufShinfo = shared_info; + + ext11.pExtBuf = (uint8_t *)pPrbMapElem->bf_weight.p_ext_start; + ext11.totalBfwIQLen = pPrbMapElem->bf_weight.ext_section_sz; + + sect_geninfo[0].exData[next].type = XRAN_CP_SECTIONEXTCMD_11; + sect_geninfo[0].exData[next].len = sizeof(ext11); + sect_geninfo[0].exData[next].data = &ext11; + + sect_geninfo[0].info.ef = 1; + sect_geninfo[0].exDataSize++; + next++; + } + } else { /* if((category == XRAN_CATEGORY_B) && (pPrbMapElem->bf_weight_update)) */ + mbuf = xran_ethdi_mbuf_alloc(); + sect_geninfo[0].info.ef = 0; + sect_geninfo[0].exDataSize = 0; + } + + if(unlikely(mbuf == NULL)) { + print_err("Alloc fail!\n"); + return (-1); + } + + params.numSections = 1;//nsection; + params.sections = sect_geninfo; + + ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id); + if(ret < 0) { + print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n", + frame_id, subframe_id, slot_id, dir); + } else { + int32_t cp_sent = 0; + int32_t pkt_len = 0; + /* add in the ethernet header */ + struct rte_ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h)); + pkt_len = rte_pktmbuf_pkt_len(mbuf); + pCnt->tx_counter++; + pCnt->tx_bytes_counter += pkt_len; //rte_pktmbuf_pkt_len(mbuf); + if(pkt_len > p_x_ctx->fh_init.mtu) + rte_panic("section %d: pkt_len = %d maxExtBufSize %d\n", i, pkt_len, pPrbMapElem->bf_weight.maxExtBufSize); + //rte_mbuf_sanity_check(mbuf, 0); + cp_sent = p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, vf_id); + if(cp_sent != 1) { + rte_pktmbuf_free(mbuf); + } + xran_cp_add_section_info(pHandle, dir, cc_id, ru_port_id, ctx_id, §_geninfo[0].info); + } + } /* for (i=0; ixran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + if(xran_port_id < XRAN_PORTS_NUM) { + if(recvSections[xran_port_id]) { + print_err("Memory already allocated!"); + return (-1); + } + + recvSections[xran_port_id] = malloc(sizeof(struct xran_section_recv_info) * XRAN_MAX_NUM_SECTIONS); + if(recvSections == NULL) { + print_err("Fail to allocate memory!"); + return (-1); + } + + recvCpInfo[xran_port_id].sections = recvSections[xran_port_id]; + } else { + print_err("Incorrect xran port %d\n", xran_port_id); + return (-1); + } + + + return (0); +} + +int32_t +xran_ruemul_release(void *pHandle) +{ + uint16_t xran_port_id; + struct xran_device_ctx* p_dev = NULL; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + if(xran_port_id < XRAN_PORTS_NUM){ + if(recvSections[xran_port_id]) { + free(recvSections[xran_port_id]); + recvCpInfo[xran_port_id].sections = NULL; + } + } else { + print_err("Incorrect xran port %d\n", xran_port_id); + return (-1); + } + + return (0); +} diff --git a/fhi_lib/lib/src/xran_cp_proc.h b/fhi_lib/lib/src/xran_cp_proc.h new file mode 100644 index 0000000..1d627fd --- /dev/null +++ b/fhi_lib/lib/src/xran_cp_proc.h @@ -0,0 +1,336 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN C-plane processing module header file + * @file xran_cp_proc.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_CP_PROC_H_ +#define _XRAN_CP_PROC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#include + +#include "xran_fh_o_du.h" +#include "xran_printf.h" + +extern uint8_t xran_cp_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_DIR_MAX][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; +extern uint8_t xran_updl_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR]; +extern uint8_t xran_upul_seq_id_num[XRAN_PORTS_NUM][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; +extern uint8_t xran_section_id_curslot[XRAN_PORTS_NUM][XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; +extern uint16_t xran_section_id[XRAN_PORTS_NUM][XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; + +int32_t xran_init_sectionid(void *pHandle); +int32_t xran_init_seqid(void *pHandle); + +int32_t process_cplane(struct rte_mbuf *pkt, void* handle); +int32_t xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id, struct xran_prb_map *prbMap, + enum xran_category category, uint8_t ctx_id); +int32_t xran_ruemul_init(void *pHandle); +int32_t xran_ruemul_release(void *pHandle); + +static __rte_always_inline uint16_t +xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (0); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { //for PRACH, ant_id starts from num_ant + print_err("Invalid antenna ID - %d", ant_id); + return (0); + } + + /* if new slot has been started, + * then initializes section id again for new start */ + if(xran_section_id_curslot[xran_port][dir][cc_id][ant_id] != slot_id) { + xran_section_id[xran_port][dir][cc_id][ant_id] = 0; + xran_section_id_curslot[xran_port][dir][cc_id][ant_id] = slot_id; + } + + return(xran_section_id[xran_port][dir][cc_id][ant_id]++); +} + +static __rte_always_inline uint8_t +xran_get_upul_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (0); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (0); + } + + return(xran_upul_seq_id_num[xran_port][cc_id][ant_id]++); +} + +static __rte_always_inline uint8_t* +xran_get_upul_seqid_addr(void *pHandle, uint8_t cc_id, uint8_t ant_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (0); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2) { + print_err("Invalid antenna ID - %d", ant_id); + return (0); + } + + return(&xran_upul_seq_id_num[xran_port][cc_id][ant_id]); +} + +static __rte_always_inline int8_t +xran_check_cp_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t seq_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(dir >= XRAN_DIR_MAX) { + print_err("Invalid direction - %d", dir); + return (-1); + } + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (-1); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2) { + print_err("Invalid antenna ID - %d", ant_id); + return (-1); + } + + xran_cp_seq_id_num[xran_port][cc_id][dir][ant_id]++; + if(xran_cp_seq_id_num[xran_port][cc_id][dir][ant_id] == seq_id) { /* expected sequence */ + return (0); + } + else { + xran_cp_seq_id_num[xran_port][cc_id][dir][ant_id] = seq_id; + return (-1); + } +} + +static __rte_always_inline int8_t +xran_check_updl_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id, uint8_t seq_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (-1); + } + + if(ant_id >= XRAN_MAX_ANTENNA_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (-1); + } + + /* O-RU needs to check the sequence ID of U-Plane DL from O-DU */ + xran_updl_seq_id_num[xran_port][cc_id][ant_id]++; + if(xran_updl_seq_id_num[xran_port][cc_id][ant_id] == seq_id) { + /* expected sequence */ + /*print_dbg("ant %u cc_id %u : slot_id %u : seq_id %u : expected seq_id %u\n", + ant_id, cc_id, slot_id, seq_id, xran_updl_seq_id_num[cc_id][ant_id]);*/ + return (0); + } else { + /*print_err("[%d] ant %u cc_id %u : slot_id %u : seq_id %u : expected seq_id %u\n", + xran_port, ant_id, cc_id, slot_id, seq_id, xran_updl_seq_id_num[xran_port][cc_id][ant_id]);*/ + + xran_updl_seq_id_num[xran_port][cc_id][ant_id] = seq_id; + + return (-1); + } +} + +static __rte_always_inline int8_t +xran_check_upul_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id, uint8_t seq_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (-1); + } + + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (-1); + } + + /* O-DU needs to check the sequence ID of U-Plane UL from O-RU */ + xran_upul_seq_id_num[xran_port][cc_id][ant_id]++; + if(xran_upul_seq_id_num[xran_port][cc_id][ant_id] == seq_id) { /* expected sequence */ + return (XRAN_STATUS_SUCCESS); + } else { + print_dbg("[%d]expected seqid %u received %u, slot %u, ant %u cc %u", xran_port, xran_upul_seq_id_num[xran_port][cc_id][ant_id], seq_id, slot_id, ant_id, cc_id); + xran_upul_seq_id_num[xran_port][cc_id][ant_id] = seq_id; // for next + return (-1); + } +} + +static __rte_always_inline uint8_t* +xran_get_updl_seqid_addr(void *pHandle, uint8_t cc_id, uint8_t ant_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (NULL); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (NULL); + } + + /* Only U-Plane DL needs to get sequence ID in O-DU */ + return(&xran_updl_seq_id_num[xran_port][cc_id][ant_id]); +} + +static __rte_always_inline uint8_t +xran_get_cp_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + + if(dir >= XRAN_DIR_MAX) { + print_err("Invalid direction - %d", dir); + return (0); + } + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (0); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (0); + } + + return(xran_cp_seq_id_num[xran_port][cc_id][dir][ant_id]++); +} + +static __rte_always_inline uint8_t +xran_get_updl_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id) +{ + int8_t xran_port = 0; + if((xran_port = xran_dev_ctx_get_port_id(pHandle)) < 0 ){ + print_err("Invalid pHandle - %p", pHandle); + return (0); + } + + if(xran_port >= XRAN_PORTS_NUM) { + print_err("Invalid port - %d", xran_port); + return (0); + } + if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { + print_err("Invalid CC ID - %d", cc_id); + return (0); + } + if(ant_id >= XRAN_MAX_ANTENNA_NR) { + print_err("Invalid antenna ID - %d", ant_id); + return (0); + } + + /* Only U-Plane DL needs to get sequence ID in O-DU */ + return(xran_updl_seq_id_num[xran_port][cc_id][ant_id]++); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_CP_PROC_H_ */ diff --git a/fhi_lib/lib/src/xran_delay_measurement.c b/fhi_lib/lib/src/xran_delay_measurement.c new file mode 100644 index 0000000..931aceb --- /dev/null +++ b/fhi_lib/lib/src/xran_delay_measurement.c @@ -0,0 +1,1418 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN layer one-way delay measurement support + * @file xran_delay_measurement.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xran_common.h" +#include "ethdi.h" +#include "xran_pkt.h" +#include "xran_dev.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_ecpri_owd_measurements.h" + +#include "xran_printf.h" +#include "xran_mlog_lnx.h" + +//#define ORAN_OWD_DEBUG_MSG_FLOW +//#define XRAN_OWD_DEBUG_MSG_FLOW +//#define XRAN_OWD_DEBUG_DELAY_INFO +//#define XRAN_OWD_DEBUG_TIME_STAMPS_INFO +//#define XRAN_OWD_DEBUG_MEAS_DB +//#define XRAN_OWD_TIMING_MODS + + + // Support for 1-way eCPRI delay measurement per section 3.2.4.6 of eCPRI Specification V2.0 + +uint64_t xran_ptp_to_host(uint64_t compValue) +{ + return (rte_be_to_cpu_64(compValue)); +} +void xran_host_to_ptp_ts(TimeStamp *ts, struct timespec *t) +{ + uint64_t seconds, nanoseconds; + + seconds = t->tv_sec; + nanoseconds = t->tv_nsec%1000000000LL; +#ifdef XRAN_OWD_DEBUG_DELAY_CONV_FUNCTIONS + printf("H2P_ts tv_sec %8"PRIx64" tv_nsec %8"PRIx64" seconds %8"PRIx64" ns %8"PRIx64" \n",t->tv_sec,t->tv_nsec,seconds,nanoseconds); +#endif + + ts->secs_msb = rte_cpu_to_be_16((rte_be16_t)((seconds >> 32) & 0xFFFF)); + ts->secs_lsb = rte_cpu_to_be_32((rte_be32_t)(seconds & 0xFFFFFFFF)); + ts->ns = rte_cpu_to_be_32((rte_be32_t)nanoseconds); +#ifdef XRAN_OWD_DEBUG_DELAY_CONV_FUNCTIONS + printf("Net order s_msb %4"PRIx16" s_lsb %8"PRIx32" ns %8"PRIx32" \n", ts->secs_msb, ts->secs_lsb,ts->ns ); +#endif +} + +uint64_t xran_ptp_ts_to_ns(TimeStamp *t) +{ + uint64_t seconds, nanoseconds; + uint64_t ret_value; + // Convert to host order + t->secs_msb=rte_be_to_cpu_16(t->secs_msb); + t->secs_lsb=rte_be_to_cpu_32(t->secs_lsb); + seconds = ((uint64_t)t->secs_msb << 32) | ((uint64_t)t->secs_lsb ); + nanoseconds = rte_be_to_cpu_32((uint64_t)t->ns); + ret_value = seconds * NS_PER_SEC + nanoseconds; +#ifdef XRAN_OWD_DEBUG_DELAY_CONV_FUNCTIONS + printf("PTP ts to ns sec_msb %4"PRIx16" secs_lsb %4"PRIx32" ns %4"PRIx32" seconds %8"PRIx64" nanosec %8"PRIx64" ret_value %8"PRIx64"\n",t->secs_msb,t->secs_lsb,t->ns,seconds, nanoseconds,ret_value); +#endif + return ret_value; + +} +static inline uint64_t xran_timespec_to_ns(struct timespec *t) +{ + uint64_t ret_val; + + ret_val = t->tv_sec * NS_PER_SEC + t->tv_nsec; +#ifdef XRAN_OWD_DEBUG_DELAY_CONV_FUNCTIONS + printf("t->tv_sec is %08"PRIx64" tv_nsec is %08"PRIx64" ret_val is %08"PRIx64" ts_to_ns\n",t->tv_sec,t->tv_nsec,ret_val); +#endif + return ret_val; + +} + +void xran_ns_to_timespec(uint64_t ns, struct timespec *t) +{ + t->tv_sec = ns/NS_PER_SEC; + t->tv_nsec = ns % NS_PER_SEC; + +} + +void xran_initialize_and_verify_owd_pl_length(void* handle) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle; + + if ((p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_PlLength == 0)||(p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_PlLength < MIN_OWDM_PL_LENGTH)) + { + // Use default length value + p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_PlLength = MIN_OWDM_PL_LENGTH; + } + else if ( p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_PlLength > MAX_OWDM_PL_LENGTH) + { + p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_PlLength = MAX_OWDM_PL_LENGTH; + } + +} + +void xran_adjust_timing_parameters(void* Handle) +{ + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)Handle; +#ifdef XRAN_OWD_TIMING_MODS + printf("delayAvg is %d and DELAY_THRESHOLD is %d \n", p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][0].delayAvg, DELAY_THRESHOLD); +#endif + if (p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][0].delayAvg < DELAY_THRESHOLD ) + { + /* Modify the timing parameters */ + if (p_xran_dev_ctx->fh_cfg.T1a_max_up >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.T1a_max_up -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.T2a_max_up >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.T2a_max_up -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.Ta3_min >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.Ta3_min -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.T1a_max_cp_dl >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.T1a_max_cp_dl -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.T1a_min_up >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.T1a_min_up -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.T1a_max_up >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.T1a_max_up -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.Ta4_min >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.Ta4_min -= ADJUSTMENT; + if (p_xran_dev_ctx->fh_cfg.Ta4_max >= ADJUSTMENT) + p_xran_dev_ctx->fh_cfg.Ta4_max -= ADJUSTMENT; +#ifdef XRAN_OWD_TIMING_MODS + printf("Mod T1a_max_up is %d\n",p_xran_dev_ctx->fh_cfg.T1a_max_up); + printf("Mod T2a_max_up is %d\n",p_xran_dev_ctx->fh_cfg.T2a_max_up); + printf("Mod Ta3_min is %d\n",p_xran_dev_ctx->fh_cfg.Ta3_min); + printf("Mod T1a_max_cp_dl is %d\n",p_xran_dev_ctx->fh_cfg.T1a_max_cp_dl); + printf("Mod T1a_min_up is %d\n",p_xran_dev_ctx->fh_cfg.T1a_min_up); + printf("Mod T1a_max_up is %d\n",p_xran_dev_ctx->fh_cfg.T1a_max_up); + printf("Mod Ta4_min is %d\n",p_xran_dev_ctx->fh_cfg.Ta4_min); + printf("Mod Ta4_max is %d\n",p_xran_dev_ctx->fh_cfg.Ta4_max); +#endif + } + +} + + + +void xran_compute_and_report_delay_estimate (struct xran_ecpri_del_meas_port *portData, uint16_t totalSamples, uint16_t id ) +{ + uint16_t i; + uint64_t *samples= portData->delaySamples; + + + for (i=2 ; i < MX_NUM_SAMPLES; i++) //Ignore first 2 samples + { + portData->delayAvg += samples[i]; + + } + + // Average the delay by the number of samples + if ((totalSamples != 0)&&(totalSamples > 2)) + { + portData->delayAvg /= (totalSamples-2); + } + // Report Average with printf + flockfile(stdout); + printf("OWD for port %i is %lu [ns] id %d \n", portData->portid, portData->delayAvg, id); + funlockfile(stdout); + +} + +int xran_get_delay_measurements_results (void* handle, uint16_t port_id, uint8_t id, uint64_t* pdelay_avg) +{ + int ret_value = FAIL; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)handle; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[id][port_id]; + // Check is the one way delay measurement completed successfully + if (powdp->msState == XRAN_OWDM_DONE) + { + *pdelay_avg = powdp->delayAvg; + ret_value = OK; + } + return (ret_value); +} + + +void xran_build_owd_meas_ecpri_hdr(char* mbuf, struct xran_ecpri_del_meas_cmn* eowdcmn) +{ + union xran_ecpri_cmn_hdr *tmp= (union xran_ecpri_cmn_hdr*)mbuf; + /* Fill common header */ + tmp->bits.ecpri_ver = XRAN_ECPRI_VER; + tmp->bits.ecpri_resv = 0; // should be zero + tmp->bits.ecpri_concat = 0; + tmp->bits.ecpri_mesg_type = ECPRI_DELAY_MEASUREMENT; + tmp->bits.ecpri_payl_size = 10 + eowdcmn->owdm_PlLength; + tmp->bits.ecpri_payl_size = rte_cpu_to_be_16(tmp->bits.ecpri_payl_size); +} + +void xran_add_at_and_measId_info_to_header(void* pbuf, uint8_t actionType, uint8_t MeasurementID) +{ + struct xran_ecpri_delay_meas_pl* tmp = (struct xran_ecpri_delay_meas_pl*)pbuf; + // Fill ActionType and MeasurementId + tmp->ActionType = actionType; + tmp->MeasurementID = MeasurementID; +} + +void xran_initialize_ecpri_del_meas_port(struct xran_ecpri_del_meas_cmn* pCmn, struct xran_ecpri_del_meas_port* pPort, uint16_t full) +{ + + uint16_t i=0; + // Initialize port parameters during the first pass + pPort->currentMeasID++; + pPort->runMeas = 1; + pPort->txDone = 0; + + if (full) + { + pPort->numMeas = 0; + pPort->portid = pCmn->measVf; + pPort->delayAvg = 0; + pPort->delta = 0; + pPort->t1 = 0; + pPort->t2 = 0; + pPort->tr = 0; +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Clearing t1 and delta\n"); +#endif + + for (i=0; i < MX_NUM_SAMPLES; i++) + { + pPort->delaySamples[i] = 0; + } + } + // Set msState based on measMethod and whether the FHI is initiator or recipient + + if (pCmn->initiator_en) + { + switch (pCmn->measMethod) + { + case XRAN_REQUEST: + pPort->msState = XRAN_OWDM_WAITRESP; + break; + case XRAN_REM_REQ: + pPort->msState = XRAN_OWDM_WAITREQ; + break; + case XRAN_REQ_WFUP: + pPort->msState = XRAN_OWDM_WAITRESP; + break; + case XRAN_REM_REQ_WFUP: + pPort->msState = XRAN_OWDM_WAITREQWFUP; + break; + default: + pPort->msState = XRAN_OWDM_WAITRESP; + break; + } + } + else + { + switch (pCmn->measMethod) + { + case XRAN_REQUEST: + pPort->msState = XRAN_OWDM_WAITREQ; + break; + case XRAN_REM_REQ: + pPort->msState = XRAN_OWDM_WAITREMREQ; + break; + case XRAN_REQ_WFUP: + pPort->msState = XRAN_OWDM_WAITREQWFUP; + break; + case XRAN_REM_REQ_WFUP: + pPort->msState = XRAN_OWDM_WAITREMREQWFUP; + break; + default: + pPort->msState = XRAN_OWDM_WAITREQ; + break; + } + } +} + +int32_t xran_ecpri_port_update_required (struct xran_io_cfg * cfg, uint16_t port_id) +{ + int32_t ret_value = 0; + int32_t* port = &cfg->port[0]; + + if (cfg != NULL) + { + + struct xran_ecpri_del_meas_port* eowdp = &cfg->eowd_port[cfg->id][port_id]; + struct xran_ecpri_del_meas_cmn* eowdc = &cfg->eowd_cmn[cfg->id]; + + + // Check if the current port has completed all the measurements to move to the next port + if (eowdp->numMeas == eowdc->numberOfSamples) + { + // Mark state as done and move to the next port + if (port_id < cfg->num_vfs) + { + port_id++; + if (port[port_id] == 0xFF) + { + // Done with all ports disable further execution + eowdc->owdm_enable = 0; + } + else + { + eowdc->measVf++; + eowdp= &cfg->eowd_port[cfg->id][port_id]; + // Initialize the next port +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Init call_1 port %d\n", port_id); +#endif + xran_initialize_ecpri_del_meas_port(eowdc, eowdp,1); + } + ret_value = 1; // Wait for the next pass through the loop to go to the next port + } + else + { + // Disable the measurements + eowdc->owdm_enable = 0; + ret_value = 1; + } + } + else + { + // Continue running on the same port + ret_value = 0; +// xran_initialize_ecpri_del_meas_port(eowdc, eowdp,0); //Now this logic is driven by the receiver + } + } + else + { + errx(1, "Exit 1 epur with cfg null"); + } + return ret_value; +} + + +/** + * @brief ecpri 2.0 one-way delay measurement transmitter control + * + * @ingroup group_source_xran + * + * @param port_id + * port_id to be used + * @param handle + * Pointer to an xran_device_ctx (cast) + * + * @return + * OK on success + * FAIL if failed to process the packet + + */ +int xran_ecpri_one_way_delay_measurement_transmitter(uint16_t port_id, void* handle) +{ + // The ecpri one way delay measurement transmitter handles the transmission + // of the owd measurement packets on each of the vfs present in the system in a sequential order + // so the owd_meas_method is provided from the configuration file and it can be one of 4 possible + // methods: REQUEST, REM_REQ, REQ_WFUP or REM_REQ_WFUP + // In the current implementation the measurement is performed on one vf until completion of the number + // of measurements defined from the configuration file. + // A variable in the xran_ecpri_del_meas_cmn keeps track of the current vf that is using the transmitter and + // when the current vf completes all the measurements it moves to the next vf until all of the vfs complete + // the measurements + // In the current implementation the measurements start after the xran_if_current_state has reached the + // XRAN_RUNNING state (i.e. after having executed the xran_start()) + // The measurements run only once for the current release. + int ret_value = FAIL; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + + if (powdc->measState == OWDMTX_INIT) + { + // Perform the initialization for the very first call to the transmitter for a given port + powdc->measVf = port_id; + powdc->measState = OWDMTX_ACTIVE; + // Check whether PL length was passed in config file and if it is within bounds + if ((powdc->owdm_PlLength == 0)|| ( powdc->owdm_PlLength < MIN_OWDM_PL_LENGTH )) + { + // Use default length value + powdc->owdm_PlLength = MIN_OWDM_PL_LENGTH; + } + else if ( powdc->owdm_PlLength > MAX_OWDM_PL_LENGTH) + { + powdc->owdm_PlLength = MAX_OWDM_PL_LENGTH; + } +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Clear call 2 port_id %d\n", port_id); +#endif + xran_initialize_ecpri_del_meas_port(powdc, powdp,1); + } + + // Initiator State Machine , recipient state machine driven from process_delay_meas() +// printf("owdm tx w state %d runMeas %d inen %d\n", powdp->msState,powdp->runMeas,powdc->initiator_en); + + if ((powdp->runMeas != 0 )&&(powdc->initiator_en != 0)) // Current port still running measurements + { + switch (powdp->msState) + { + case XRAN_OWDM_WAITRESP: + // Check the measmethod to define the action + if (powdc->measMethod == XRAN_REQUEST) + { + if (!powdp->txDone) + { +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("owdm ecpri tx req gen\n"); +#endif + if (xran_generate_delay_meas(port_id, handle, (uint8_t)ECPRI_REQUEST, powdc->measId) == 0 ) + { + errx(1, "Exit 1 owdm tx port_id %d measId %d", port_id, powdc->measId); + } + powdp->txDone =1; + } + } + else + { + // The only else corresponds to XRAN_REQ_WFUP + if (!powdp->txDone) + { +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("owdm ecpri tx req w fup gen\n"); +#endif + if (xran_generate_delay_meas(port_id, handle, (uint8_t)ECPRI_REQUEST_W_FUP , powdc->measId) == 0 ) + { + errx(1, "Exit 2 owdm tx port_id %d measId %d", port_id, powdc->measId ); + } + powdp->txDone=0; // Needs fup + } + } + break; + case XRAN_OWDM_WAITREQ: + if (!powdp->txDone) + { +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("owdm ecpri tx rem req gen\n"); +#endif + if (xran_generate_delay_meas(port_id, handle, (uint8_t)ECPRI_REMOTE_REQ , powdc->measId) == 0 ) + { + errx(1, "Exit 3 owdm tx port_id %d measId %d", port_id, powdc->measId ); + } + powdp->txDone=1; + } + break; + case XRAN_OWDM_WAITREQWFUP: + if (!powdp->txDone) + { +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("owdm ecpri tx rem req w fup gen\n"); +#endif + if (xran_generate_delay_meas(port_id, handle, (uint8_t)ECPRI_REMOTE_REQ_W_FUP , powdc->measId) == 0 ) + { + errx(1, "Exit 4 owdm tx port_id %d measId %d", port_id, powdc->measId ); + } + powdp->txDone=1; + } + break; + case XRAN_OWDM_GENFUP: + if (!powdp->txDone) + { +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("owdm ecpri follow up gen\n"); +#endif + if (xran_generate_delay_meas(port_id, handle, (uint8_t)ECPRI_FOLLOW_UP , powdc->measId) == 0 ) + { + errx(1, "Exit 4 owdm tx port_id %d measId %d", port_id, powdc->measId ); + } + powdp->txDone=1; + } + break; + case XRAN_OWDM_WAITFUP: + case XRAN_OWDM_DONE: + case XRAN_OWDM_IDLE: + // Transmitter doesn't have to do anything in these states + break; + default: + errx(1, "Exit 5 owdm tx port_id %d measId %d id %d state %d", port_id, powdc->measId, p_xran_dev_ctx->fh_init.io_cfg.id, powdp->msState ); + + } + } + ret_value = OK; + return ret_value; + +} + +/** + * @brief Generate a Delay Measurement packet + * Transport layer fragmentation is not supported. + * + * @ingroup group_source_xran + * + * @param port_id + * port_id to be used + * @param handle + * Pointer to an xran_device_ctx (cast) + * @param actionType + * actionType to be used in the owd measurement packet + * @param MeasurementID + * MeasurementID to be populated in the owd measurement packet + * @return + * OK on success + * FAIL if failed to process the packet + + */ +int xran_generate_delay_meas(uint16_t port_id, void* handle, uint8_t actionType, uint8_t MeasurementID ) +{ + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_delay_meas_pkt *ecpri_delmeas_pkt; + int pkt_len; + struct rte_mbuf *mbuf,*pkt; + char* pChar; + struct xran_ecpri_delay_meas_pl * pdm= NULL; + uint64_t tcv1,tr2m,trm; + struct timespec tr2, tr; + struct xran_io_cfg* cfg = &p_xran_dev_ctx->fh_init.io_cfg; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + int32_t *port = &cfg->port[port_id]; + int ret_value = FAIL; + struct rte_ether_addr addr; + uint16_t ethertype = ETHER_TYPE_ECPRI; + +// printf("in xran_generate_delay_meas for action_type %d\n", actionType); + + pkt_len = sizeof(struct xran_ecpri_del_meas_pkt); + // Allocate a buffer from the pool + mbuf =xran_ethdi_mbuf_alloc(); + if (mbuf == NULL) + { + MLogPrint(NULL); + errx(1,"exit 1 owdm gen"); + } + pChar = rte_pktmbuf_append(mbuf, pkt_len); + if (pChar == NULL) + { + MLogPrint(NULL); + errx(1,"exit 2 owdm gen"); + } + pChar = rte_pktmbuf_prepend(mbuf, sizeof(struct rte_ether_hdr)); + if (pChar == NULL) + { + MLogPrint(NULL); + errx(1,"exit 3 owdm gen"); + } + + struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); + + struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(mbuf, struct rte_ether_hdr*); + PANIC_ON(h == NULL, "mbuf prepend of ether_hdr failed"); + + /* Fill in the ethernet header. */ + rte_eth_macaddr_get(port_id, &h->s_addr); /* set source addr */ + + if (p_xran_dev_ctx->fh_init.io_cfg.id) + { +// rte_ether_addr_copy( (struct rte_ether_addr *)p_xran_dev_ctx->fh_init.p_o_du_addr[port_id],&h->d_addr); + h->d_addr = ctx->entities[port_id][ID_O_DU]; /* set dst addr */ + } + else + { + h->d_addr = ctx->entities[port_id][ID_O_RU]; /* set dst addr */ +// rte_ether_addr_copy( (struct rte_ether_addr *)p_xran_dev_ctx->fh_init.p_o_ru_addr[port_id],&h->d_addr); + } + + h->ether_type = rte_cpu_to_be_16(ethertype); /* ethertype too */ + mbuf->port = ctx->io_cfg.port[port_id]; + + + // Prepare the ecpri header info + // Advance pointer to the begining of the ecpri common header + pChar = pChar + sizeof (struct rte_ether_hdr); + xran_build_owd_meas_ecpri_hdr(pChar, powdc ); + // Advance pointer to the begining of the xran_ecpri_delay_meas_pl + pChar = pChar + sizeof (union xran_ecpri_cmn_hdr); + xran_add_at_and_measId_info_to_header(pChar, actionType, MeasurementID); + + pdm = (struct xran_ecpri_delay_meas_pl *)rte_pktmbuf_mtod_offset(mbuf, struct xran_ecpri_delay_meas_pl *, sizeof(struct rte_ether_hdr) + sizeof(union xran_ecpri_cmn_hdr)); + switch (actionType) + { + // For owd meas originator there are a subset of actionTypes used see ecpri 2.0 Figures 25 and 26 for the details + case ECPRI_REQUEST: + // Record t1, prepare Request Message and determine tcv1 and include both time stamps in the packet + // 1) Record the current timestamp when the preparation of the message started i.e. t1 + if (clock_gettime(CLOCK_REALTIME, &tr )) // t1 + { + return ret_value; + } + trm = xran_timespec_to_ns(&tr); +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf("trm at gen is %8"PRIx64" \n", trm); +#endif + // 2) Prepare the delay measurement request packet + pdm->ActionType = ECPRI_REQUEST; + // 3) Record the current timestamp at the moment that the delay measurement packet is ready to be transmitted tr2 i.e.t1+tcv1 and write it + // to the Delay Measurement request packet PL field + if (clock_gettime(CLOCK_REALTIME, &tr2 )) // ts + { + return ret_value; + } + // 4) Convert host to ptp time stamp format for tr and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->ts, &tr); + // 5) Convert from Timestamp tr2 to ns before computing the compensation value + tr2m = xran_timespec_to_ns(&tr2); + // 6) Compute tcv1 as tr2m-trm + tcv1 = tr2m - trm; +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf("tcv1 is %08"PRIx64"\n",tcv1); +#endif + + // 7) write tcv1 to the CompensationValue field of the delay measurement request packet + pdm->CompensationValue = rte_cpu_to_be_64(tcv1); +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf("compensation value after net order %8"PRIx64" \n", pdm->CompensationValue); +#endif + // 8) Store t1 and tcv1 to be used later once we get the response message + powdp->currentMeasID = pdm->MeasurementID; + powdp->t1 = trm; + powdp->delta = tcv1; + powdp->msState = XRAN_OWDM_WAITRESP; +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf("At req gen t1 %8"PRIx64" and delta %8"PRIx64" port %d \n",powdp->t1,powdp->delta,port_id); +#endif + break; + + case ECPRI_REMOTE_REQ: + // Prepare and send Remote Request Message with zero timestamp and correction values + tr.tv_sec = 0; + tr.tv_nsec = 0; + tcv1 = 0; + // Convert host to ptp time stamp format for tr and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->ts, &tr); + // write zero to the CompensationValue field of the delay measurement remote request packet + pdm->CompensationValue = rte_cpu_to_be_64(tcv1); + // 1) Prepare the delay measurement request packet + pdm->ActionType = ECPRI_REMOTE_REQ; + // 2) Store MeasurementID and msState to be checked once the Request Message is received + powdp->currentMeasID = pdm->MeasurementID; + powdp->msState = XRAN_OWDM_WAITREQ; + + break; + + case ECPRI_REQUEST_W_FUP: + // Record t1, prepare Request with follow up Message and determine tcv1, send zero timestamp and correction value in the packet + // 1) Record the current timestamp when the message preparation started i.e. t1 + if (clock_gettime(CLOCK_REALTIME, &tr )) // t1 + { + return ret_value; + } + trm = xran_timespec_to_ns(&tr); + // 2) Prepare the delay measurement remote request with follow up packet + pdm->ActionType = ECPRI_REQUEST_W_FUP; + // 3) Record the current timestamp at the moment that the delay measurement packet is ready to be transmitted tr2 i.e.t1+tcv1 + if (clock_gettime(CLOCK_REALTIME, &tr2 )) // ts + { + return ret_value; + } + // 4) Convert from Timestamp tr2 to ns before computing the compensation value + tr2m = xran_timespec_to_ns(&tr2); + // 5) Compute tcv1 as tr2m-trm + tcv1 = tr2m - trm; + // Prepare and send Remote Request Message with zero timestamp and correction values + tr.tv_sec = 0; + tr.tv_nsec = 0; + powdp->delta = tcv1; // Save tcv1 while waiting for the Response + tcv1 = 0; + // Convert host to ptp time stamp format for tr and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->ts, &tr); + // write zero to the CompensationValue field of the delay measurement remote request packet + pdm->CompensationValue = rte_cpu_to_be_64(tcv1); + // 6) Store MeasurementID and msState to be checked once the Request Message is received + powdp->currentMeasID = pdm->MeasurementID; + powdp->t1 = trm; + powdp->msState = XRAN_OWDM_GENFUP; + + break; + + case ECPRI_FOLLOW_UP: + // Use the t1 and tcv1 values recorded in the ECPRI_REQUEST_W_FUP packet generation step and send these values in the follow up packet + // 1) Prepare the delay measurement follow up packet + pdm->ActionType = ECPRI_FOLLOW_UP; + // 2) Convert t1 from host to ptp format + xran_ns_to_timespec(powdp->t1, &tr); + // 3) Convert host to ptp time stamp format for tr and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->ts, &tr); + // 4) write tcv1 to the CompensationValue field of the delay measurement request packet + pdm->CompensationValue = rte_cpu_to_be_64(powdp->delta); + powdp->currentMeasID = pdm->MeasurementID; + powdp->msState = XRAN_OWDM_WAITRESP; + break; + + case ECPRI_REMOTE_REQ_W_FUP: + // Prepare the Remote Request with follow up Message, send zero timestamp and correction value in the packet + tr.tv_sec = 0; + tr.tv_nsec = 0; + tcv1 = 0; + // Convert host to ptp time stamp format for tr and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->ts, &tr); + // write zero to the CompensationValue field of the delay measurement remote request packet + pdm->CompensationValue = rte_cpu_to_be_64(tcv1); + // 1) Prepare the delay measurement request packet + pdm->ActionType = ECPRI_REMOTE_REQ_W_FUP; + // 2) Store MeasurementID and msState to be checked once the Request Message is received + powdp->currentMeasID = pdm->MeasurementID; + powdp->msState = XRAN_OWDM_WAITREQWFUP; + + break; + + default: + errx(1,"exit 4 owdm gen"); + break; + } + + // printf("xran_gen_del_4n"); + + // Retrieve Ethernet Header for the port and copy to the packet + rte_eth_macaddr_get(port_id, &addr); +#ifdef XRAN_OWD_DEBUG_PKTS + printf("id is %d\n", p_xran_dev_ctx->fh_init.io_cfg.id); + printf("Port %u SRC MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8 + " %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", + (unsigned)port_id, + addr.addr_bytes[0], addr.addr_bytes[1], addr.addr_bytes[2], + addr.addr_bytes[3], addr.addr_bytes[4], addr.addr_bytes[5]); +#endif + + if (p_xran_dev_ctx->fh_init.io_cfg.id) + { +#ifdef XRAN_OWD_DEBUG_PKTS + int8_t *pa = &p_xran_dev_ctx->fh_init.p_o_du_addr[0]; + printf("DST_MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pa[0],pa[1],pa[2],pa[3],pa[4],pa[5]); +#endif + rte_ether_addr_copy((struct rte_ether_addr *)&p_xran_dev_ctx->fh_init.p_o_du_addr[0], (struct rte_ether_addr *)&h->d_addr.addr_bytes[0]); + + } + else + { +#ifdef XRAN_OWD_DEBUG_PKTS + int8_t *pb = &p_xran_dev_ctx->fh_init.p_o_ru_addr[0]; + printf("DST_MAC: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pb[0],pb[1],pb[2],pb[3],pb[4],pb[5]); +#endif + rte_ether_addr_copy((struct rte_ether_addr *)&p_xran_dev_ctx->fh_init.p_o_ru_addr[0], (struct rte_ether_addr *)&h->d_addr.addr_bytes[0]); + + } +#ifdef XRAN_OWD_DEBUG_PKTS + uint8_t *pc = &h->s_addr.addr_bytes[0]; + printf(" Src MAC from packet: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pc[0],pc[1],pc[2],pc[3],pc[4],pc[5]); + uint8_t *pd = &h->d_addr.addr_bytes[0]; + printf(" Dst MAC from packet: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pd[0],pd[1],pd[2],pd[3],pd[4],pd[5]); +#endif + // Copy dest address from above + // Send out the packet + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &mbuf, 1); +// Try using the normal scheme of passing through the ring +// ret_value = xran_enqueue_mbuf(mbuf, ctx->tx_ring[port_id]); +#ifdef XRAN_OWD_DEBUG_PKTS + printf("owdt rte_eth_tx_burst returns %d for port %d\n", ret_value,port_id); +#endif + return ret_value; +} + + +/** + * @brief Process a Delay Measurement Request packet + * + * @ingroup group_source_xran + * + * @param mbuf + * The pointer of the packet buffer to be processed + * @param handle + * Pointer to an xran_device_ctx (cast) + * @param xran_ecpri_delay_meas_pl + * Pointer to an eCPRI delay measurement PL + * @return + * OK on success + * FAIL if failed to process the packet + */ +int xran_process_delmeas_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = FAIL; + + struct xran_ecpri_delay_meas_pl *txDelayHdr; + TimeStamp pt1; + struct rte_mbuf* pkt1; + char* pchar; + uint64_t tcv1, tcv2,t2m,trm, td12, t1m; + struct xran_ecpri_del_meas_pkt *pdm= NULL; + union xran_ecpri_cmn_hdr *cmn; + struct timespec tr, t2; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct rte_ether_hdr *eth_hdr; + struct rte_ether_addr addr; + struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); +//101620 + struct xran_io_cfg* cfg = &p_xran_dev_ctx->fh_init.io_cfg; +// struct xran_io_cfg *cfg = &ctx->io_cfg; + int32_t *port = &cfg->port[port_id]; + +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("RX ecpri Measure Request \n"); +#endif + // Since we are processing the receipt of a delay measurement request packet the following actions + // need to be taken (Per eCPRI V2.0 Figure 25) + // 1) Record the current timestamp when the message was received i.e. tr + if (clock_gettime(CLOCK_REALTIME, &tr )) // tr + { + errx(1, "Exit 1 owd rx f1 port_id %d", port_id); + return ret_value; + } + + trm = xran_timespec_to_ns(&tr); + // 2) Copy MeasurementID to the Delay Measurement Response packet + // but first prepend ethernet header since the info is still in the buffer +// pchar = rte_pktmbuf_prepend(pkt, (uint16_t)(sizeof(struct rte_ether_hdr)+ sizeof(union xran_ecpri_cmn_hdr ))); // Pointer to new data start address 10/20/20 Now not removing ecpri_cmn in process_delay_meas + pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr)); + pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX); + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr)); + // 3) Get time stamp T1 from the Timestamp field i.e. t1 + pt1 = pdm->deMeasPl.ts; + // 3a) Convert to ns in the host format + t1m = xran_ptp_ts_to_ns(&pt1); + // 4) Get the compensation value from the packet i.e. tcv1 + tcv1 = rte_be_to_cpu_64(pdm->deMeasPl.CompensationValue); + // 5) Prepare the delay measurement response packet + pdm->deMeasPl.ActionType = ECPRI_RESPONSE; + // 6) Record the current timestamp at the moment that the delay measurement packet is ready to be transmitted i.e.t2 and write it + // to the Delay Measurement response packet PL field + if (clock_gettime(CLOCK_REALTIME, &t2 )) // t2 + { + errx(1,"Exit 2 owd rx f1 port_id %d", port_id); + return ret_value; + } + // 7) Convert host to ptp time stamp format for t2 and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->deMeasPl.ts, &t2); + // 8) Convert from Timestamp t2 to ns before computing the compensation value + t2m = xran_timespec_to_ns(&t2); + // 9) Compute tcv2 as t2-tr + tcv2 = t2m - trm; + // 10) write cv2 to the CompensationValue field of the delay measurement response packet + pdm->deMeasPl.CompensationValue = rte_cpu_to_be_64(tcv2); + // 11) Fill the ethernet header properly by swapping src and dest addressed from the copied frame + eth_hdr = rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr *); + /* Swap dest and src mac addresses. */ + rte_ether_addr_copy(ð_hdr->d_addr, &addr); + rte_ether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr); + rte_ether_addr_copy(&addr, ð_hdr->s_addr); + // Still need to check ol_flags state and update if necessary + // Compute the delay td12 and save + // Still need to define the DB to save the info and run averages + td12 = t2m - tcv2 - (t1m + tcv1); + // 12) Send the response right away + struct rte_ether_hdr *h = (struct rte_ether_hdr *)rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr*); +#ifdef XRAN_OWD_DEBUG_PKTS + uint8_t *pc = &h->s_addr.addr_bytes[0]; + printf(" Src MAC from packet: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pc[0],pc[1],pc[2],pc[3],pc[4],pc[5]); + uint8_t *pd = &h->d_addr.addr_bytes[0]; + printf(" Dst MAC from packet: %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8" %02"PRIx8"\n", pd[0],pd[1],pd[2],pd[3],pd[4],pd[5]); +// printf("EtherType: %04"PRIx16" \n",&h->ether_type); +#endif + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt *, sizeof(struct rte_ether_hdr) ); + pdm->cmnhdr.bits.ecpri_payl_size = 10 + powdc->owdm_PlLength; // 10 correponds to the xran_ecpri_delay_meas_pl minus the dummy_bytes field which now allows the user to select the length for this field to be sent + pdm->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(pdm->cmnhdr.bits.ecpri_payl_size); + pdm->cmnhdr.bits.ecpri_mesg_type = ECPRI_DELAY_MEASUREMENT; +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf ("pdm has:%02"PRIx8" %04"PRIx16" %02"PRIx8" %02"PRIx8" \n", pdm->cmnhdr.bits.ecpri_mesg_type, pdm->cmnhdr.bits.ecpri_payl_size, pdm->cmnhdr.bits.ecpri_ver,pdm->deMeasPl.MeasurementID); +#endif + + // Copy dest address from above + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &pkt1, 1); // Need to check for the proper method of getting the port and mac address +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf ("in dly ms req sending response rte_eth_tx_burst returns %d for port %d\n",ret_value, *port); +#endif + // 13) Update measurements DB and check if completed + powdp->delaySamples[powdp->numMeas]= td12 ; +#ifdef XRAN_OWD_DEBUG_DELAY_INFO + printf("Computed delay is %08"PRIx64" MeasNum %d portId %d id is %d \n",powdp->delaySamples[powdp->numMeas],powdp->numMeas, port_id, p_xran_dev_ctx->fh_init.io_cfg.id); +#endif + + powdp->numMeas++; + + if (powdp->numMeas == powdc->numberOfSamples) + { + xran_compute_and_report_delay_estimate(powdp, powdc->numberOfSamples, p_xran_dev_ctx->fh_init.io_cfg.id); + powdp->msState = XRAN_OWDM_DONE; + xran_if_current_state = XRAN_RUNNING; + } + else + { + +// powdp->msState = XRAN_OWDM_IDLE; + if (powdc->initiator_en) + { + // Reinitialize txDone for next pass + powdp->txDone = 0; +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Clear call 3 port id %d \n", port_id); +#endif + xran_initialize_ecpri_del_meas_port(powdc, powdp,0); + } + } + return 1; + +} + +int xran_process_delmeas_request_w_fup(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = FAIL; + struct xran_ecpri_delay_meas_pl* txDelayHdr; + TimeStamp pt2; + struct rte_mbuf* pkt1; + uint64_t trm; + struct xran_ecpri_del_meas_pkt* pdm= ptr; + struct timespec tr; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg *cfg = &ctx->io_cfg; + int32_t* port = &cfg->port[port_id]; + + // Since we are processing the receipt of a delay measurement request with follow up packet the following actions + // need to be taken (Per eCPRI V2.0 Figure 26) +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("RX ecpri Measure Request with fup\n"); +#endif + + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod(pkt, struct xran_ecpri_del_meas_pkt*); + // Record tr and save to memory with the associated measurement Id and Port + // 1) Record the current timestamp when the message was received i.e. tr + if (clock_gettime(CLOCK_REALTIME, &tr )) // tr + { + errx(1, "Exit 1 owd rx f2 port_id %d",port_id); + return ret_value; + } + trm = xran_timespec_to_ns(&tr); + // Save trm so when the Follow Up packet is received we can compute tcv2 as t2-trm + powdp->tr = trm; + // Save the measurement Id + powdp->currentMeasID = pdm->deMeasPl.MeasurementID; + // Change the state to waiting for follow up + powdp->msState = XRAN_OWDM_WAITFUP; + + return ret_value; + +} + +int xran_process_delmeas_response(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = 1; + struct xran_ecpri_delay_meas_pl* txDelayHdr; + TimeStamp pt2; + struct rte_mbuf* pkt1; + uint64_t tcv1, tcv2,t2m,trm, td12; + struct xran_ecpri_del_meas_pkt* pdm; + struct timespec tr, t2; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg *cfg = &ctx->io_cfg; + struct xran_io_cfg* cfg1 = &p_xran_dev_ctx->fh_init.io_cfg; + int32_t* port = &cfg->port[port_id]; + + + // Since we are processing the receipt of a delay measurement response packet the following actions + // need to be taken (Per eCPRI V2.0 Figure 25) + // Need to know if a Remote Request was processed against this measurement ID if so then the receipt of the response + // is used to compute the one-way delay as td= (t2-tcv2) - (t1+tcv1) with t2, tcv2 contained in the packet and + // t1 and tcv1 stored from the previous Remote Request packet processing task +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("RX ecpri Measure Response \n"); +#endif + + pdm = (struct xran_ecpri_del_meas_pkt*)(struct xran_ecpri_del_meas_pkt *)rte_pktmbuf_mtod(pkt, struct xran_ecpri_del_meas_pkt *); + // Save the measurement Id + powdp->currentMeasID = pdm->deMeasPl.MeasurementID; + + // 1) Get time stamp T2 from the Timestamp field i.e. t2 + pt2 = pdm->deMeasPl.ts; + + // 2a) Convert to ns in the host format + t2m = xran_ptp_ts_to_ns(&pt2); + // 3) Get the compensation value from the packet i.e. tcv2 + tcv2 = rte_be_to_cpu_64(pdm->deMeasPl.CompensationValue); +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf ("tcv2 at Gen is %08"PRIx64" \n",tcv2); +#endif + // Compute the delay using the stored t1 and tcv1 used in the request message + // td= (t2-tcv2) - (t1+tcv1) where t1 and tcv1 have been stored previously for the same measurement ID +#ifdef XRAN_OWD_DEBUG_TIME_STAMPS_INFO + printf("Delay comp at orig has t2m %08"PRIx64" tcv2 %08"PRIx64" t1 %08"PRIx64" delta %08"PRIx64" port_id %d \n", t2m,tcv2,powdp->t1 ,powdp->delta,port_id); +#endif + powdp->delaySamples[powdp->numMeas]= (t2m-tcv2) -(powdp->t1 + powdp->delta); +#ifdef XRAN_OWD_DEBUG_DELAY_INFO + printf("Computed delay is %08"PRIx64" MeasNum %d portId %d id is %d \n",powdp->delaySamples[powdp->numMeas],powdp->numMeas, port_id,p_xran_dev_ctx->fh_init.io_cfg.id ); +#endif + + powdp->numMeas++; + + + + if (powdp->numMeas == powdc->numberOfSamples) + { + xran_compute_and_report_delay_estimate(powdp, powdc->numberOfSamples,p_xran_dev_ctx->fh_init.io_cfg.id); + powdp->msState = XRAN_OWDM_DONE; + xran_if_current_state= XRAN_RUNNING; + } + else + { + +// powdp->msState = XRAN_OWDM_IDLE; + if (powdc->initiator_en) + { + // Reinitialize txDone for next pass + powdp->txDone = 0; +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Clear call_4 port_id %d \n", port_id); +#endif + xran_initialize_ecpri_del_meas_port(powdc, powdp,0); +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Reseting done \n"); +#endif + + } + + } + // Needs work and change ret_value to OK + return ret_value; +} + +int xran_process_delmeas_rem_request(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = FAIL; + struct xran_ecpri_delay_meas_pl* txDelayHdr; + struct rte_mbuf* pkt1; + uint64_t tcv1,tr2m,trm; + struct xran_ecpri_del_meas_pkt* pdm; + char* pchar; + struct timespec tr2, tr; + struct rte_ether_hdr *eth_hdr; + struct rte_ether_addr addr; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg *cfg = &ctx->io_cfg; + int32_t* port = &cfg->port[port_id]; + + // Since we are processing the receipt of a delay measurement remote request packet the following actions + // need to be taken (Per eCPRI V2.0 Figure 25) +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("RX ecpri Measure Remote Request \n"); +#endif + + // 1) Record the current timestamp when the message was received i.e. t1 + if (clock_gettime(CLOCK_REALTIME, &tr )) // t1 + { + errx(1,"Exit 1 owd rx f4 port_id %d", port_id); + return ret_value; + } + trm = xran_timespec_to_ns(&tr); + // 2) Copy MeasurementID to the Delay Measurement Request packet + // but first prepend ethernet header since the info is still in the buffer + pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr)); + pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX); + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr)); + + // 3) Prepare the delay measurement request packet + pdm->deMeasPl.ActionType = ECPRI_REQUEST; + // 4) Record the current timestamp at the moment that the delay measurement packet is ready to be transmitted tr2 i.e.t1+tcv1 and write it + // to the Delay Measurement request packet PL field + if (clock_gettime(CLOCK_REALTIME, &tr2 )) // tr2 + { + errx(1,"Exit 2 owd rx f4 port_id %d", port_id); + return ret_value; + } + // 5) Convert host to ptp time stamp format for tr2 and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->deMeasPl.ts, &tr); + // 6) Convert from Timestamp tr2 to ns before computing the compensation value + tr2m = xran_timespec_to_ns(&tr2); + // 7) Compute tcv1 as tr2m-trm + tcv1 = tr2m - trm; + // 8) write tcv1 to the CompensationValue field of the delay measurement request packet + pdm->deMeasPl.CompensationValue = rte_cpu_to_be_64(tcv1); + // 9) Fill the ethernet header properly by swapping src and dest addressed from the copied frame + eth_hdr = rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr *); + /* Swap dest and src mac addresses. */ + rte_ether_addr_copy(ð_hdr->d_addr, &addr); + rte_ether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr); + rte_ether_addr_copy(&addr, ð_hdr->s_addr); + // 10) Send the response right away + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt *, sizeof(struct rte_ether_hdr) ); + pdm->cmnhdr.bits.ecpri_payl_size = 10 + powdc->owdm_PlLength; // 10 correponds to the xran_ecpri_delay_meas_pl minus the dummy_bytes field which now allows the user to select the length for this field to be sent + pdm->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(pdm->cmnhdr.bits.ecpri_payl_size); + pdm->cmnhdr.bits.ecpri_mesg_type = ECPRI_DELAY_MEASUREMENT; +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("Ecpri Measure Sending Request Msg \n"); +#endif + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &pkt1, 1); // Need to check for the proper method of getting the port and mac address + // Still need to check ol_flags state and update if necessary + // Save the computed delays and the measurementId + powdp->t1 = trm; + powdp->delta = tcv1; + powdp->currentMeasID = pdm->deMeasPl.MeasurementID; + powdp->msState = XRAN_OWDM_WAITRESP; + return ret_value; + + +} +int xran_process_delmeas_rem_request_w_fup(struct rte_mbuf* pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = FAIL; + struct xran_ecpri_delay_meas_pl* txDelayHdr; + TimeStamp pt2; + struct rte_mbuf* pkt1; + struct rte_mbuf* pkt2; + uint64_t tcv1,tsm,t1; + struct rte_ether_hdr *eth_hdr; + struct rte_ether_addr addr; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct xran_ecpri_del_meas_pkt* pdm; + struct timespec tr, ts; + char* pchar; + + + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg *cfg = &ctx->io_cfg; + int32_t* port = &cfg->port[port_id]; + tsm = 0; + + // Since we are processing the receipt of a delay measurement remote request with follow up packet the following + // actions need to be taken (Per eCPRI V2.0 Figure 26) + // record t1 for the packet arrival time and then prepare Request with follow up packet which uses 0 for timsetamp + // and for correctionvalue. +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("RX ecpri Measure Remote Request w Fup \n"); +#endif + // 1) Record the current timestamp when the message was received i.e. t1 + if (clock_gettime(CLOCK_REALTIME, &tr )) // t1 + { + errx(1,"Exit 1 owd rx f5 port_id %d", port_id); + return ret_value; + } + t1 = xran_timespec_to_ns(&tr); + // 2) Copy MeasurementID to the Delay Measurement Request packet + // but first prepend ethernet header since the info is still in the buffer + pchar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr)); + pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX); + + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr)); + + + // 3) Prepare the delay measurement request w fup packet + pdm->deMeasPl.ActionType = ECPRI_REQUEST_W_FUP; + // 4) Zero the ts and CompensationValue entries in the packet + ts.tv_sec=0; + ts.tv_nsec =0; + // 5) Convert host to ptp time stamp format for t2 and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->deMeasPl.ts, &ts); + // 6) write zero to the CompensationValue field of the delay measurement response packet + pdm->deMeasPl.CompensationValue = rte_cpu_to_be_64(tsm); + // 7) Fill the ethernet header properly by swapping src and dest addressed from the copied frame + eth_hdr = rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr *); + /* Swap dest and src mac addresses. */ + rte_ether_addr_copy(ð_hdr->d_addr, &addr); + rte_ether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr); + rte_ether_addr_copy(&addr, ð_hdr->s_addr); + // 8) Duplicate packet to be used for the follow up packet + pkt2 = rte_pktmbuf_copy(pkt1, _eth_mbuf_pool, 0, UINT32_MAX); + // 9) Record the current timestamp when the request with follow up is being sent + if (clock_gettime(CLOCK_REALTIME, &ts )) // ts + { + errx(1,"Exit 2 owd rx f5 port_id %d", port_id); + return ret_value; + } + // 10) Send the request with follow up +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("ecpri Measure sending Request with Fup \n"); +#endif + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &pkt1, 1); // Need to check for the proper method of getting the port and mac address + + // After the Request with follow up packet has been sent, prepare follow up packet with t1 and tcv1, where + // tcv1 = ts - t1 and writing it to the outgoing packet + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt2, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr)); + // 11) Prepare the delay measurement request with follow up packet + pdm->deMeasPl.ActionType = ECPRI_FOLLOW_UP; + // 12) Convert host to ptp time stamp format for t1 and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->deMeasPl.ts, &tr); + // 13) Convert from Timestamp t2 to ns before computing the compensation value + tsm = xran_timespec_to_ns(&ts); + // 14) Compute tcv1 as tsm-t1 + tcv1 = tsm - t1; + // 15) write cv1 to the CompensationValue field of the delay measurement response packet + pdm->deMeasPl.CompensationValue = rte_cpu_to_be_64(tcv1); + + // 16) Send the follow up message +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("ecpri Measure sending Follow Up \n"); +#endif + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &pkt2, 1); // Need to check for the proper method of getting the port and mac address + + // Save trm since it will be used to compute tcv2 based on the arrival of the Follow Up packet + powdp->currentMeasID = pdm->deMeasPl.MeasurementID; + powdp->t1 = t1; + powdp->delta = tcv1; + powdp->msState = XRAN_OWDM_WAITRESP; + + return ret_value; + +} + +int xran_process_delmeas_follow_up(struct rte_mbuf *pkt, void* handle, struct xran_ecpri_del_meas_pkt* ptr, uint16_t port_id) +{ + int ret_value = FAIL; + struct xran_ecpri_delay_meas_pl *txDelayHdr; + struct rte_mbuf *pkt1; + char* pChar= NULL; + uint64_t tcv1,tr2m, tcv2, t1; + struct xran_ecpri_del_meas_pkt *pdm; + struct timespec tr2, tr; + struct rte_ether_hdr *eth_hdr; + struct rte_ether_addr addr; + TimeStamp pt1; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_cmn* powdc = &p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id]; + struct xran_ecpri_del_meas_port* powdp = &p_xran_dev_ctx->fh_init.io_cfg.eowd_port[p_xran_dev_ctx->fh_init.io_cfg.id][port_id]; + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + struct xran_io_cfg *cfg = &ctx->io_cfg; + int32_t *port = &cfg->port[0]; + // Since we are processing the receipt of a delay measurement follow up packet the following actions + // need to be taken (Per eCPRI V2.0 Figure 26) +#ifdef XRAN_OWD_DEBUG_MSG_FLOW + printf("ecpri Measure received Followup \n"); +#endif + + // 1) Record the current timestamp when the message was received i.e. tr2 + if (clock_gettime(CLOCK_REALTIME, &tr2 )) // tr2 + { + errx(1,"Exit 1 owd rx f6 port_id %d", port_id); + return ret_value; + } + tr2m = xran_timespec_to_ns(&tr2); + + + // 2) Copy MeasurementID to the Delay Measurement Response packet + // but first prepend ethernet header since the info is still in the buffer + pChar = rte_pktmbuf_prepend(pkt, (uint16_t)sizeof(struct rte_ether_hdr)); + pkt1 = rte_pktmbuf_copy(pkt, _eth_mbuf_pool, 0, UINT32_MAX); + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt*, sizeof(struct rte_ether_hdr)); + + // 3) Get time stamp T1 from the Timestamp field i.e. t1 + pt1 = pdm->deMeasPl.ts; + // 4) Convert to ns in the host format + t1 = xran_ptp_ts_to_ns(&pt1); + // 5) Get the compensation value from the packet i.e. tcv1 + tcv1 = rte_be_to_cpu_64(pdm->deMeasPl.CompensationValue); + + // 6) Prepare the delay measurement response packet + pdm->deMeasPl.ActionType = ECPRI_RESPONSE; + + // 7) Convert host to ptp time stamp format for tr2 and write to the outgoing packet + xran_host_to_ptp_ts(&pdm->deMeasPl.ts, &tr2); + // 8) Convert from Timestamp tr2 to ns before computing the compensation value + tr2m = xran_timespec_to_ns(&tr2); + // 9) Compute tcv2 as tr2m-trm + tcv2 = tr2m - powdp->tr; + // 0) write tcv2 to the CompensationValue field of the delay measurement request packet + pdm->deMeasPl.CompensationValue = rte_cpu_to_be_64(tcv2); + // 9) Fill the ethernet header properly by swapping src and dest addressed from the copied frame + eth_hdr = rte_pktmbuf_mtod(pkt1, struct rte_ether_hdr *); + /* Swap dest and src mac addresses. */ + rte_ether_addr_copy(ð_hdr->d_addr, &addr); + rte_ether_addr_copy(ð_hdr->s_addr, ð_hdr->d_addr); + rte_ether_addr_copy(&addr, ð_hdr->s_addr); + pdm = (struct xran_ecpri_del_meas_pkt*)rte_pktmbuf_mtod_offset(pkt1, struct xran_ecpri_del_meas_pkt *, sizeof(struct rte_ether_hdr) ); + pdm->cmnhdr.bits.ecpri_payl_size = 10 + powdc->owdm_PlLength; // 10 correponds to the xran_ecpri_delay_meas_pl minus the dummy_bytes field which now allows the user to select the length for this field to be sent + pdm->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(pdm->cmnhdr.bits.ecpri_payl_size); + pdm->cmnhdr.bits.ecpri_mesg_type = ECPRI_DELAY_MEASUREMENT; + + // 10) Send the response right away + ret_value = rte_eth_tx_burst((uint16_t)*port, 0, &pkt1, 1); // Need to check for the proper method of getting the port and mac address + + // Compute the delay using the stored t1 and tcv1 used in the request message + // td= (t2-tcv2) - (t1+tcv1) where t1 and tcv1 have been stored previously for the same measurement ID + powdp->delaySamples[powdp->numMeas]= (tr2m-tcv2) -(t1 + tcv1); +#ifdef XRAN_OWD_DEBUG_DELAY_INFO + printf("Computed delay is %08"PRIx64" MeasNum %d portId %d id %d \n",powdp->delaySamples[powdp->numMeas],powdp->numMeas,port_id,p_xran_dev_ctx->fh_init.io_cfg.id); +#endif + powdp->numMeas++; + + if (powdp->numMeas == powdc->numberOfSamples) + { + xran_compute_and_report_delay_estimate(powdp, powdc->numberOfSamples, p_xran_dev_ctx->fh_init.io_cfg.id); + powdp->msState = XRAN_OWDM_DONE; + xran_if_current_state = XRAN_RUNNING; + } + else + { +; +// powdp->msState = XRAN_OWDM_IDLE; + if (powdc->initiator_en) + { + // Reinitialize txDone for next pass + powdp->txDone = 0; +#ifdef XRAN_OWD_DEBUG_MEAS_DB + printf("Clear Call_5 port_id %d \n", port_id); +#endif + xran_initialize_ecpri_del_meas_port(powdc, powdp,0); + } + } + + return ret_value; + +} + + +/** + * @brief Parse a Delay Measurement packet + * Transport layer fragmentation is not supported. + * + * @ingroup group_source_xran + * + * @param mbuf + * The pointer of the packet buffer to be parsed + * @param handle + * Pointer to an xran_device_ctx (cast) + * @return + * OK on success + * FAIL if failed to process the packet + */ +int process_delay_meas(struct rte_mbuf *pkt, void* handle, uint16_t port_id) +{ + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)handle; + struct xran_ecpri_del_meas_pkt *ecpri_delmeas_pkt; + union xran_ecpri_cmn_hdr * ecpricmn; + int ret_value = FAIL; +#ifdef XRAN_OWD_DEBUG_PKTS + printf("pdm Device is %d\n", p_xran_dev_ctx->fh_init.io_cfg.id); +#endif + /* Process eCPRI cmn header. */ + + // (void *)rte_pktmbuf_adj(pkt, sizeof(*ecpricmn)); + ecpri_delmeas_pkt = (struct xran_ecpri_del_meas_pkt *)rte_pktmbuf_mtod(pkt, struct xran_ecpri_del_meas_pkt *); + // The processing of the delay measurement here corresponds to eCPRI sections 3.2.4.6.2 and 3.42.6.3 + + switch(ecpri_delmeas_pkt->deMeasPl.ActionType) { + case ECPRI_REQUEST: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc rx Dly Meas Req\n"); +#endif + ret_value = xran_process_delmeas_request(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + case ECPRI_REQUEST_W_FUP: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas rx Req w Fup\n"); +#endif + ret_value = xran_process_delmeas_request_w_fup(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + case ECPRI_RESPONSE: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas rx Resp\n"); +#endif + ret_value = xran_process_delmeas_response(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + case ECPRI_REMOTE_REQ: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas rx Rem Req\n"); +#endif + ret_value = xran_process_delmeas_rem_request(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + case ECPRI_REMOTE_REQ_W_FUP: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas Rem rx Req w Fup\n"); +#endif + ret_value = xran_process_delmeas_rem_request_w_fup(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + case ECPRI_FOLLOW_UP: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas rx Fup\n"); +#endif + ret_value = xran_process_delmeas_follow_up(pkt, p_xran_dev_ctx, ecpri_delmeas_pkt, port_id); + break; + default: +#ifdef ORAN_OWD_DEBUG_MSG_FLOW + printf("Proc Dly Meas default\n"); +#endif + break; + } + return ret_value; + +} diff --git a/fhi_lib/lib/src/xran_dev.c b/fhi_lib/lib/src/xran_dev.c new file mode 100644 index 0000000..fef64c8 --- /dev/null +++ b/fhi_lib/lib/src/xran_dev.c @@ -0,0 +1,480 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN library device (O-RU or O-DU) specific context and coresponding methods + * @file xran_dev.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xran_fh_o_du.h" +#include "xran_dev.h" +#include "ethdi.h" +#include "xran_printf.h" + +static struct xran_device_ctx *g_xran_dev_ctx[XRAN_PORTS_NUM] = {NULL, NULL, NULL, NULL}; + +int32_t +xran_dev_create_ctx(uint32_t xran_ports_num) +{ + int32_t i = 0; + struct xran_device_ctx * pCtx = NULL; + + if (xran_ports_num > XRAN_PORTS_NUM) + return -1; + + pCtx = (struct xran_device_ctx *) _mm_malloc(sizeof(struct xran_device_ctx)*xran_ports_num, 64); + if(pCtx){ + for(i = 0; i < xran_ports_num; i++){ + g_xran_dev_ctx[i] = pCtx; + pCtx++; + } + } else { + return -1; + } + return 0; +} + +int32_t +xran_dev_destroy_ctx(void) +{ + if (g_xran_dev_ctx[0]) + free(g_xran_dev_ctx[0]); + + return 0; +} +struct xran_device_ctx *xran_dev_get_ctx(void) +{ + return g_xran_dev_ctx[0]; +} + +struct xran_device_ctx **xran_dev_get_ctx_addr(void) +{ + return &g_xran_dev_ctx[0]; +} + +struct xran_device_ctx *xran_dev_get_ctx_by_id(uint32_t xran_port_id) +{ + if (xran_port_id >= XRAN_PORTS_NUM) + return NULL; + else + return g_xran_dev_ctx[xran_port_id]; +} + +static struct xran_fh_config *xran_lib_get_ctx_fhcfg(void *pHandle) +{ + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx*)pHandle; + return (&(p_dev_ctx->fh_cfg)); +} + + +/** + * @brief Get the configuration of eAxC ID + * + * @return the pointer of configuration + */ +struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle) +{ + struct xran_device_ctx * p_dev_ctx = pHandle; + if(p_dev_ctx == NULL) + p_dev_ctx = xran_dev_get_ctx(); + + if(p_dev_ctx == NULL) + return NULL; + return (&(p_dev_ctx->eAxc_id_cfg)); +} + +/** + * @brief Get the configuration of the total number of beamforming weights on RU + * + * @return Configured the number of beamforming weights + */ +uint8_t xran_get_conf_num_bfweights(void *pHandle) +{ + struct xran_device_ctx * p_dev_ctx = pHandle; + if(p_dev_ctx == NULL) + p_dev_ctx = xran_dev_get_ctx(); + + if(p_dev_ctx == NULL) + return 0; + + return (p_dev_ctx->fh_init.totalBfWeights); +} + +/** + * @brief Get the configuration of subcarrier spacing for PRACH + * + * @return subcarrier spacing value for PRACH + */ +uint8_t xran_get_conf_prach_scs(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->prach_conf.nPrachSubcSpacing); +} + +/** + * @brief Get the configuration of FFT size for RU + * + * @return FFT size value for RU + */ +uint8_t xran_get_conf_fftsize(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->ru_conf.fftSize); +} + +/** + * @brief Get the configuration of nummerology + * + * @return Configured numerology + */ +uint8_t xran_get_conf_numerology(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->frame_conf.nNumerology); +} + +/** + * @brief Get the configuration of IQ bit width for RU + * + * @return IQ bit width for RU + */ +uint8_t xran_get_conf_iqwidth_prach(void *pHandle) +{ + struct xran_fh_config *pFhCfg; + + pFhCfg = xran_lib_get_ctx_fhcfg(pHandle); + return ((pFhCfg->ru_conf.iqWidth_PRACH==16)?0:pFhCfg->ru_conf.iqWidth_PRACH); +} + +/** + * @brief Get the configuration of compression method for RU + * + * @return Compression method for RU + */ +uint8_t xran_get_conf_compmethod_prach(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->ru_conf.compMeth_PRACH); +} + + +/** + * @brief Get the configuration of the number of component carriers + * + * @return Configured the number of component carriers + */ +uint8_t xran_get_num_cc(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->nCC); +} + +/** + * @brief Get the configuration of the number of antenna for UL + * + * @return Configured the number of antenna + */ +uint8_t xran_get_num_eAxc(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->neAxc); +} + +/** + * @brief Get configuration of O-RU (Cat A or Cat B) + * + * @return Configured the number of antenna + */ +enum xran_category xran_get_ru_category(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->ru_conf.xranCat); +} + +/** + * @brief Get the configuration of the number of antenna + * + * @return Configured the number of antenna + */ +uint8_t xran_get_num_eAxcUl(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->neAxcUl); +} + +/** + * @brief Get the configuration of the number of antenna elements + * + * @return Configured the number of antenna + */ +uint8_t xran_get_num_ant_elm(void *pHandle) +{ + return (xran_lib_get_ctx_fhcfg(pHandle)->nAntElmTRx); +} + +int32_t xran_get_common_counters(void *pXranLayerHandle, struct xran_common_counters *pStats) +{ + int32_t o_xu_id = 0; + int32_t xran_port_num = 0; + struct xran_device_ctx* pDev = (struct xran_device_ctx*)pXranLayerHandle; + struct xran_ethdi_ctx *ctx = xran_ethdi_get_ctx(); + uint16_t port, qi; + + if(pStats && pDev) { + xran_port_num = pDev->fh_init.xran_ports; + for(o_xu_id = 0; o_xu_id < XRAN_PORTS_NUM;o_xu_id++ ){ + if(o_xu_id < xran_port_num ){ + pStats[o_xu_id] = pDev->fh_counters; + } + pDev++; + } + if (ctx->io_cfg.id == 0 && ctx->io_cfg.num_rxq > 1) { + for (port = 0; port < ctx->io_cfg.num_vfs; port++) { + printf("vf %d: ", port); + for (qi = 0; qi < ctx->rxq_per_port[port]; qi++){ + printf("%6ld ", ctx->rx_vf_queue_cnt[port][qi]); + } + printf("\n"); + } + } + + return XRAN_STATUS_SUCCESS; + } else { + return XRAN_STATUS_INVALID_PARAM; + } +} + +uint16_t xran_get_beamid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id) +{ + return (0); // NO BEAMFORMING +} + +struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data, void* p_dev_ctx) +{ + struct cb_elem_entry * cb_elm = (struct cb_elem_entry *)malloc(sizeof(struct cb_elem_entry)); + if(cb_elm){ + cb_elm->pSymCallback = cb_fn; + cb_elm->pSymCallbackTag = cb_data; + cb_elm->p_dev_ctx = p_dev_ctx; + } + + return cb_elm; +} + +int32_t +xran_destroy_cb(struct cb_elem_entry * cb_elm) +{ + if(cb_elm) + free(cb_elm); + return 0; +} + +uint16_t +xran_map_ecpriRtcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id) +{ + return (p_dev_ctx->map2vf[dir][cc_id][ru_port_id][XRAN_CP_VF]); +} + +uint16_t +xran_map_ecpriPcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id) +{ + return (p_dev_ctx->map2vf[dir][cc_id][ru_port_id][XRAN_UP_VF]); +} + +uint16_t +xran_set_map_ecpriRtcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id, uint16_t vf_id) +{ + p_dev_ctx->map2vf[dir][cc_id][ru_port_id][XRAN_CP_VF] = vf_id; + return XRAN_STATUS_SUCCESS; +} + +uint16_t +xran_set_map_ecpriPcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id, uint16_t vf_id) +{ + p_dev_ctx->map2vf[dir][cc_id][ru_port_id][XRAN_UP_VF] = vf_id; + return XRAN_STATUS_SUCCESS; +} + +const char * +xran_pcid_str_type(struct xran_device_ctx* p_dev, int ant) +{ + if(ant < xran_get_num_eAxcUl(p_dev)) + return "PUSCH"; + else if (ant >= xran_get_num_eAxcUl(p_dev) && ant < 2*xran_get_num_eAxcUl(p_dev)) + return "PRACH"; + else if ( ant >= xran_get_num_eAxcUl(p_dev) * 2 && ant < 2*xran_get_num_eAxcUl(p_dev) + xran_get_num_ant_elm(p_dev)) + return " SRS "; + else + return " N/A "; +} + +int32_t +xran_init_vf_rxq_to_pcid_mapping(void *pHandle) +{ +/* eCPRI flow supported with DPDK 21.02 or later */ +#if (RTE_VER_YEAR >= 21) /* eCPRI flow supported with DPDK 21.02 or later */ + struct xran_ethdi_ctx *eth_ctx = xran_ethdi_get_ctx(); + uint8_t xran_port_id = 0; + struct xran_device_ctx* p_dev = NULL; + struct rte_flow_error error; + int32_t vf_id = 0; + int32_t ant = 0; + int32_t cc = 0; + uint16_t pc_id_be = 0; + uint16_t rx_q[XRAN_VF_MAX] = { 0 }; + + int32_t dir = XRAN_DIR_UL; + uint8_t num_eAxc = 0; + uint8_t num_cc = 0; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + num_cc = xran_get_num_cc(p_dev); + + if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_A) + num_eAxc = xran_get_num_eAxc(p_dev); + else + num_eAxc = xran_get_num_eAxcUl(p_dev); + + num_eAxc *= 2; /* +PRACH */ + num_eAxc += xran_get_num_ant_elm(p_dev); /* +SRS */ + + for(cc = 0; cc < num_cc; cc++) { + for(ant = 0; ant < num_eAxc; ant++) { + pc_id_be = xran_compose_cid(0, 0, cc, ant); + vf_id = xran_map_ecpriPcid_to_vf(p_dev, dir, cc, ant); + + /* don't use queue 0 for eCpri Flows */ + if(rx_q[vf_id] == 0) + rx_q[vf_id]++; + + p_dev->p_iq_flow[p_dev->iq_flow_cnt] = generate_ecpri_flow(vf_id, rx_q[vf_id], pc_id_be, &error); + eth_ctx->vf_and_q2pc_id[vf_id][rx_q[vf_id]] = rte_be_to_cpu_16(pc_id_be); + + xran_decompose_cid((uint16_t)pc_id_be, ð_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]]); + + eth_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]].bandSectorId = vf_id; + eth_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]].cuPortId = rx_q[vf_id]; + + printf("%s: p %d vf %d qi %d 0x%016p UP: dir %d cc %d (%d) ant %d (%d) type %s", __FUNCTION__, xran_port_id, vf_id, rx_q[vf_id], ð_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]], dir, + cc, eth_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]].ccId, ant, eth_ctx->vf_and_q2cid[vf_id][rx_q[vf_id]].ruPortId, xran_pcid_str_type(p_dev, ant)); + + printf(" queue_id %d flow_id %d pc_id 0x%04x\n",rx_q[vf_id], p_dev->iq_flow_cnt, pc_id_be); + p_dev->iq_flow_cnt++; + rx_q[vf_id]++; + + if(rx_q[vf_id] > eth_ctx->io_cfg.num_rxq) + rte_panic("Not enough RX Queues\n"); + eth_ctx->rxq_per_port[vf_id] = rx_q[vf_id]; + } + } +#endif + return XRAN_STATUS_SUCCESS; +} + +int32_t +xran_init_vfs_mapping(void *pHandle) +{ + int ctx, dir, cc, ant, i; + struct xran_device_ctx* p_dev = NULL; + uint8_t xran_port_id = 0; + uint16_t vf_id = 0; + uint16_t vf_id_cp = 0; + struct xran_ethdi_ctx *eth_ctx = xran_ethdi_get_ctx(); + uint16_t vf_id_all[XRAN_VF_MAX]; + uint16_t total_vf_cnt = 0; + + if(pHandle) { + p_dev = (struct xran_device_ctx* )pHandle; + xran_port_id = p_dev->xran_port_id; + } else { + print_err("Invalid pHandle - %p", pHandle); + return (XRAN_STATUS_FAIL); + } + + memset(vf_id_all, 0, sizeof(vf_id_all)); + + for(i = 0; i < XRAN_VF_MAX; i++){ + if(eth_ctx->vf2xran_port[i] == xran_port_id){ + vf_id_all[total_vf_cnt++] = i; + printf("%s: p %d vf %d\n", __FUNCTION__, xran_port_id, i); + } + } + + print_dbg("total_vf_cnt %d\n", total_vf_cnt); + + if(eth_ctx->io_cfg.nEthLinePerPort != (total_vf_cnt >> (1 - eth_ctx->io_cfg.one_vf_cu_plane))) { + print_err("Invalid total_vf_cnt - %d [expected %d]", total_vf_cnt, + eth_ctx->io_cfg.nEthLinePerPort << (1 - eth_ctx->io_cfg.one_vf_cu_plane)); + return (XRAN_STATUS_FAIL); + } + + for(dir=0; dir < 2; dir++){ + for(cc=0; cc < xran_get_num_cc(p_dev); cc++){ + for(ant=0; ant < xran_get_num_eAxc(p_dev)*2 + xran_get_num_ant_elm(p_dev); ant++){ + if(total_vf_cnt = 2 && eth_ctx->io_cfg.one_vf_cu_plane){ + if(ant & 1) { /* split ant half and half on VFs */ + vf_id = vf_id_all[XRAN_UP_VF+1]; + xran_set_map_ecpriPcid_to_vf(p_dev, dir, cc, ant, vf_id); + vf_id_cp = vf_id_all[XRAN_UP_VF+1]; + xran_set_map_ecpriRtcid_to_vf(p_dev, dir, cc, ant, vf_id_cp); + } else { + vf_id = vf_id_all[XRAN_UP_VF]; + xran_set_map_ecpriPcid_to_vf(p_dev, dir, cc, ant, vf_id); + vf_id_cp = vf_id_all[XRAN_UP_VF]; + xran_set_map_ecpriRtcid_to_vf(p_dev, dir, cc, ant, vf_id_cp); + } + } else { + vf_id = vf_id_all[XRAN_UP_VF]; + xran_set_map_ecpriPcid_to_vf(p_dev, dir, cc, ant, vf_id); + vf_id_cp = vf_id_all[(eth_ctx->io_cfg.one_vf_cu_plane ? XRAN_UP_VF : XRAN_CP_VF)]; + xran_set_map_ecpriRtcid_to_vf(p_dev, dir, cc, ant, vf_id_cp); + } + print_dbg("%s: p %d vf %d UP: dir %d cc %d ant %d\n", __FUNCTION__, xran_port_id, vf_id, dir, cc, ant); + print_dbg("%s: p %d vf %d CP: dir %d cc %d ant %d\n", __FUNCTION__, xran_port_id, vf_id_cp, dir, cc, ant); + } + } + } + + return (XRAN_STATUS_SUCCESS); +} diff --git a/fhi_lib/lib/src/xran_dev.h b/fhi_lib/lib/src/xran_dev.h new file mode 100644 index 0000000..7d3412f --- /dev/null +++ b/fhi_lib/lib/src/xran_dev.h @@ -0,0 +1,334 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN layer O-DU|O-RU device context + * @file xran_dev.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_DEV_H_ +#define _XRAN_DEV_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include +#include +#include + +#include "xran_fh_o_du.h" +#include "xran_prach_cfg.h" +#include "xran_up_api.h" +#include "xran_cp_api.h" + +#define DIV_ROUND_OFFSET(X,Y) ( X/Y + ((X%Y)?1:0) ) + +#define MAX_NUM_OF_XRAN_CTX (2) +#define MAX_CB_TIMER_CTX (10*MAX_NUM_OF_XRAN_CTX) +#define MAX_TTI_TO_PHY_TIMER (10) +#define XranIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_XRAN_CTX-1)) ? 0 : (ctx+1)) +#define XranDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_XRAN_CTX-1) : (ctx-1)) + +#define MAX_NUM_OF_DPDK_TIMERS (10) +#define DpdkTimerIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_DPDK_TIMERS-1)) ? 0 : (ctx+1)) +#define DpdkTimerDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_DPDK_TIMERS-1) : (ctx-1)) + +enum xran_job_type_id { + XRAN_JOB_TYPE_OTA_CB = 0, + XRAN_JOB_TYPE_CP_DL = 1, + XRAN_JOB_TYPE_CP_UL = 2, + XRAN_JOB_TYPE_DEADLINE = 3, + XRAN_JOB_TYPE_SYM_CB = 4, + XRAN_JOB_TYPE_MAX +}; + +struct xran_timer_ctx { + uint32_t tti_to_process; + uint32_t ota_sym_idx; + uint16_t xran_sfn_at_sec_start; + uint64_t current_second; +}; + +#define XRAN_MAX_POOLS_PER_SECTOR_NR 8 /**< 2x(TX_OUT, RX_IN, PRACH_IN, SRS_IN) with C-plane */ + +typedef struct sectorHandleInfo +{ + /**< Structure that contains the information to describe the + * instance i.e service type, virtual function, package Id etc..*/ + uint16_t nIndex; + uint16_t nXranPort; + /* Unique ID of an handle shared between phy layer and library */ + /**< number of antennas supported per link*/ + uint32_t nBufferPoolIndex; + /**< Buffer poolIndex*/ + struct rte_mempool * p_bufferPool[XRAN_MAX_POOLS_PER_SECTOR_NR]; + uint32_t bufferPoolElmSz[XRAN_MAX_POOLS_PER_SECTOR_NR]; + uint32_t bufferPoolNumElm[XRAN_MAX_POOLS_PER_SECTOR_NR]; + +}XranSectorHandleInfo, *PXranSectorHandleInfo; + +typedef void (*XranSymCallbackFn)(struct rte_timer *tim, void* arg, void *p_dev_ctx); +typedef int32_t (*tx_sym_gen_fn)(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, + uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, + uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db); + +struct cb_elem_entry{ + XranSymCallbackFn pSymCallback; + void *pSymCallbackTag; + void *p_dev_ctx; + LIST_ENTRY(cb_elem_entry) pointers; +}; + +/* Callback function to send mbuf to the ring */ +typedef int (*xran_ethdi_mbuf_send_fn)(struct rte_mbuf *mb, uint16_t ethertype, uint16_t vf_id); + +/* + * manage one cell's all Ethernet frames for one DL or UL LTE subframe + */ +typedef struct { + /* -1-this subframe is not used in current frame format + 0-this subframe can be transmitted, i.e., data is ready + 1-this subframe is waiting transmission, i.e., data is not ready + 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1, + set bValid to 10. + */ + int32_t bValid ; // when UL rx, it is subframe index. + int32_t nSegToBeGen; + int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE + // -1 means that DL packet to be transmitted is not ready in BS + int32_t nSegTransferred; // number of data segments has been transmitted or received + struct rte_mbuf *pData[XRAN_N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool + struct xran_buffer_list sBufferList; +} BbuIoBufCtrlStruct; + + +#define XranIncrementJob(i) ((i >= (XRAN_SYM_JOB_SIZE-1)) ? 0 : (i+1)) + +#define XRAN_MAX_PKT_BURST_PER_SYM 96 /**< 16 layers with 6 sections each */ +#define XRAN_MAX_PACKET_FRAG 9 + +#define MBUF_TABLE_SIZE (2 * MAX(XRAN_MAX_PKT_BURST_PER_SYM, XRAN_MAX_PACKET_FRAG)) + +#define XRAN_IQ_FLOW_MAX 512 /**< Maximum flow IQ flows per XRAN port */ + +struct mbuf_table { + uint16_t len; + struct rte_mbuf *m_table[MBUF_TABLE_SIZE]; +}; + +/** Symbols CB structure defining context of exection */ +struct cb_user_per_sym_ctx { + int32_t status; /** status of CB - free, used */ + int32_t symb_num_req; /**< requested Symb for CB */ + int32_t sym_diff; /**< delay/advace as measured against OTA "-" - delay(later OTA) "+" - advace (earlier OTA) */ + int32_t symb_num_ota; /**< coresponding "execution time" for Symb according to type of CB */ + int32_t cb_type_id; /**< type of CB */ + + /** DPDK timer specific variables */ + int32_t user_timer_put; /**< put index (producer)*/ + int32_t user_timer_get; /**< get index (consumer)*/ + struct xran_timer_ctx user_cb_timer_ctx[MAX_CB_TIMER_CTX]; /**< DPDK timer context */ + + xran_callback_sym_fn symCb; /**< call back for Symb event */ + void *symCbParam; /**< parameters of call back function */ + struct xran_sense_of_time *symCbTimeInfo; /**< Time related infomation to this CB */ + void *p_dev; /**< poiter back to coresponding Device context */ +}; + +/** Shared data at the end of an external buffer for C-plane and U-plane*/ +struct xran_shared_data_ucp_t { + struct rte_mbuf_ext_shared_info sh_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_MAX_SECTIONS_PER_SLOT]; +}; + +/** Shared data at the end of an external buffer for Beam forming weights */ +struct xran_shared_data_bfw_t { + struct rte_mbuf_ext_shared_info sh_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_MAX_SECTIONS_PER_SLOT]; +}; + +/** Shared data at the end of an external buffer for SRS */ +struct xran_shared_data_srs_t { + struct rte_mbuf_ext_shared_info sh_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; +}; + +struct __rte_cache_aligned xran_device_ctx +{ + uint8_t sector_id; + uint8_t xran_port_id; + struct xran_eaxcid_config eAxc_id_cfg; + struct xran_fh_init fh_init; + struct xran_fh_config fh_cfg; + struct xran_prach_cp_config PrachCPConfig; + + uint32_t enablePrach; + uint32_t enableCP; + + int32_t DynamicSectionEna; + int64_t offset_sec; + int64_t offset_nsec; //offset to GPS time calcuated based on alpha and beta + uint32_t interval_us_local; + + uint32_t enableSrs; + uint8_t puschMaskEnable; + uint8_t puschMaskSlot; + struct xran_srs_config srs_cfg; /** configuration of SRS */ + + BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrlDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + + BbuIoBufCtrlStruct sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + BbuIoBufCtrlStruct sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + + /* buffers lists */ + struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + + struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + + xran_transport_callback_fn pCallback[XRAN_MAX_SECTOR_NR]; + void *pCallbackTag[XRAN_MAX_SECTOR_NR]; + + xran_transport_callback_fn pPrachCallback[XRAN_MAX_SECTOR_NR]; + void *pPrachCallbackTag[XRAN_MAX_SECTOR_NR]; + + xran_transport_callback_fn pSrsCallback[XRAN_MAX_SECTOR_NR]; + void *pSrsCallbackTag[XRAN_MAX_SECTOR_NR]; + + LIST_HEAD(sym_cb_elem_list, cb_elem_entry) sym_cb_list_head[XRAN_NUM_OF_SYMBOL_PER_SLOT]; + + int32_t sym_up; /**< when we start sym 0 of up with respect to OTA time as measured in symbols */ + int32_t sym_up_ul; + + xran_fh_tti_callback_fn ttiCb[XRAN_CB_MAX]; + void *TtiCbParam[XRAN_CB_MAX]; + uint32_t SkipTti[XRAN_CB_MAX]; + + int xran2phy_mem_ready; + + int rx_packet_symb_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + int rx_packet_prach_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + int rx_packet_callback_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]; + int rx_packet_prach_callback_tracker[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]; + int prach_start_symbol[XRAN_MAX_SECTOR_NR]; + int prach_last_symbol[XRAN_MAX_SECTOR_NR]; + + int phy_tti_cb_done; + + struct rte_mempool *direct_pool; + struct rte_mempool *indirect_pool; + + struct xran_common_counters fh_counters; + + xran_ethdi_mbuf_send_fn send_cpmbuf2ring; /**< callback to send mbufs of C-Plane packets to the ring */ + xran_ethdi_mbuf_send_fn send_upmbuf2ring; /**< callback to send mbufs of U-Plane packets to the ring */ + + struct xran_timer_ctx timer_ctx[MAX_NUM_OF_XRAN_CTX]; + struct xran_timer_ctx cb_timer_ctx[MAX_CB_TIMER_CTX]; + + struct rte_timer tti_to_phy_timer[MAX_TTI_TO_PHY_TIMER]; + struct rte_timer sym_timer; + struct rte_timer dpdk_timer[MAX_NUM_OF_DPDK_TIMERS]; + + uint16_t map2vf[2][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR*2 + XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_VF_MAX]; + + int32_t ctx; + + int timer_put; + + struct cb_user_per_sym_ctx symCbCtx[XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_CB_SYM_MAX]; + + volatile int32_t timing_source_thread_running; + + struct rte_mbuf *to_free_mbuf[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_MAX_SECTIONS_PER_SLOT]; + + tx_sym_gen_fn tx_sym_gen_func; + + int32_t job2wrk_id[XRAN_JOB_TYPE_MAX]; /** mapping of HI prio Job to worker core */ + + struct xran_shared_data_ucp_t share_data; + struct xran_shared_data_ucp_t cp_share_data; + struct xran_shared_data_bfw_t bfw_share_data; + struct xran_shared_data_srs_t srs_share_data; + + struct rte_flow *p_iq_flow[XRAN_IQ_FLOW_MAX]; + uint32_t iq_flow_cnt; /**< number of IQ flows configured */ +}; + +struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle); +uint8_t xran_get_conf_prach_scs(void *pHandle); +uint8_t xran_get_conf_fftsize(void *pHandle); +uint8_t xran_get_conf_numerology(void *pHandle); +uint8_t xran_get_conf_iqwidth_prach(void *pHandle); +uint8_t xran_get_conf_compmethod_prach(void *pHandle); +uint8_t xran_get_conf_num_bfweights(void *pHandle); +uint8_t xran_get_num_cc(void *pHandle); +uint8_t xran_get_num_eAxc(void *pHandle); +uint8_t xran_get_num_eAxcUl(void *pHandle); +uint8_t xran_get_num_ant_elm(void *pHandle); +enum xran_category xran_get_ru_category(void *pHandle); +uint16_t xran_get_beamid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id); + +int32_t xran_dev_create_ctx(uint32_t xran_ports_num); +int32_t xran_dev_destroy_ctx(); +struct xran_device_ctx *xran_dev_get_ctx(void); +struct xran_device_ctx *xran_dev_get_ctx_by_id(uint32_t xran_port_id); +struct xran_device_ctx **xran_dev_get_ctx_addr(void); + +struct cb_elem_entry *xran_create_cb(XranSymCallbackFn cb_fn, void *cb_data, void* p_dev_ctx); +int32_t xran_destroy_cb(struct cb_elem_entry * cb_elm); + +uint16_t xran_map_ecpriRtcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id); +uint16_t xran_map_ecpriPcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id); + +uint16_t xran_set_map_ecpriRtcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id, uint16_t vf_id); +uint16_t xran_set_map_ecpriPcid_to_vf(struct xran_device_ctx *p_dev_ctx, int32_t dir, int32_t cc_id, int32_t ru_port_id, uint16_t vf_id); + +int32_t xran_init_vfs_mapping(void *pHandle); +int32_t xran_init_vf_rxq_to_pcid_mapping(void *pHandle); + +static inline int8_t xran_dev_ctx_get_port_id(void * handle) +{ + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)handle; + if(p_dev_ctx) + return (int8_t)p_dev_ctx->xran_port_id; + else + return -1; +}; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/fhi_lib/lib/src/xran_ecpri_owd_measurements.h b/fhi_lib/lib/src/xran_ecpri_owd_measurements.h new file mode 100644 index 0000000..15206cf --- /dev/null +++ b/fhi_lib/lib/src/xran_ecpri_owd_measurements.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ +// Ecpri One-way delay measurement support definitions + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum xran_owdm_state +{ + XRAN_OWDM_IDLE = 0, + XRAN_OWDM_WAITRESP, + XRAN_OWDM_WAITREQ, + XRAN_OWDM_WAITFUP, + XRAN_OWDM_GENFUP, + XRAN_OWDM_WAITREQWFUP, + XRAN_OWDM_WAITREMREQ, + XRAN_OWDM_WAITREMREQWFUP, + XRAN_OWDM_DONE +}; + +enum xran_owd_meas_method +{ + XRAN_REQUEST = 0, + XRAN_REM_REQ, + XRAN_REQ_WFUP, + XRAN_REM_REQ_WFUP +}; + +enum xran_owdm_tx_state +{ + OWDMTX_INIT = 0, + OWDMTX_IDLE, + OWDMTX_ACTIVE, + OWDTX_DONE +}; + +#define DELAY_THRESHOLD 60000 /* in ns */ +#define ADJUSTMENT 60 /* in us */ +#define MIN_OWDM_PL_LENGTH 40 /* Minimum owdm Payload length in bytes */ +#define MAX_OWDM_PL_LENGTH 1400 /* Maximum owdm Payload length in bytes */ + +int xran_get_delay_measurements_results (void* Handle, uint16_t port_id, uint8_t id, uint64_t* pdelay_avg); + +void xran_adjust_timing_parameters(void* Handle); + +void xran_initialize_and_verify_owd_pl_length(void* Handle); + +int process_delay_meas(struct rte_mbuf *pkt, void* handle, uint16_t port_id); \ No newline at end of file diff --git a/fhi_lib/lib/src/xran_frame_struct.c b/fhi_lib/lib/src/xran_frame_struct.c index 35fcaab..f531fb0 100644 --- a/fhi_lib/lib/src/xran_frame_struct.c +++ b/fhi_lib/lib/src/xran_frame_struct.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -73,7 +73,7 @@ static uint16_t nTtiInterval[4] = 1000, // mu = 0 500, // mu = 1 250, // mu = 2 - 125, // mu = 3 + 125 // mu = 3 }; // F1 Tables 38.101-1 Table F.5.3. Window length for normal CP @@ -93,15 +93,15 @@ static int16_t nCpSizeF2[2][4][2] = {{68, 36}, {136, 72}, {272, 144}, {544, 288}}, // Numerology 3 (120KHz) }; -static uint32_t xran_fs_max_slot_num = 8000; -static uint32_t xran_fs_max_slot_num_SFN = 20480; /* max slot number counted as SFN is 0-1023 */ -static uint16_t xran_fs_num_slot_tdd_loop[XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP }; -static uint16_t xran_fs_num_dl_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0}; -static uint16_t xran_fs_num_ul_sym_sp[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0}; -static uint8_t xran_fs_slot_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}}; -static uint8_t xran_fs_slot_symb_type[XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{XRAN_SLOT_TYPE_INVALID}}}; -static float xran_fs_ul_rate[XRAN_MAX_SECTOR_NR] = {0.0}; -static float xran_fs_dl_rate[XRAN_MAX_SECTOR_NR] = {0.0}; +static uint32_t xran_fs_max_slot_num[XRAN_PORTS_NUM] = {8000, 8000, 8000, 8000}; +static uint32_t xran_fs_max_slot_num_SFN[XRAN_PORTS_NUM] = {20480,20480,20480,20480}; /* max slot number counted as SFN is 0-1023 */ +static uint16_t xran_fs_num_slot_tdd_loop[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = { XRAN_NUM_OF_SLOT_IN_TDD_LOOP }; +static uint16_t xran_fs_num_dl_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0}; +static uint16_t xran_fs_num_ul_sym_sp[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {0}; +static uint8_t xran_fs_slot_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP] = {{XRAN_SLOT_TYPE_INVALID}}; +static uint8_t xran_fs_slot_symb_type[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][XRAN_NUM_OF_SLOT_IN_TDD_LOOP][XRAN_NUM_OF_SYMBOL_PER_SLOT] = {{{XRAN_SLOT_TYPE_INVALID}}}; +static float xran_fs_ul_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {0.0}; +static float xran_fs_dl_rate[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {0.0}; extern uint16_t xran_max_frame; @@ -306,44 +306,44 @@ uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq) return (nNRARFCN); } -uint32_t xran_fs_slot_limit_init(int32_t tti_interval_us) +uint32_t xran_fs_slot_limit_init(uint32_t PortId, int32_t tti_interval_us) { - xran_fs_max_slot_num = (1000/tti_interval_us)*1000; - xran_fs_max_slot_num_SFN = (1000/tti_interval_us)*(xran_max_frame+1)*10; - return xran_fs_max_slot_num; + xran_fs_max_slot_num[PortId] = (1000/tti_interval_us)*1000; + xran_fs_max_slot_num_SFN[PortId] = (1000/tti_interval_us)*(xran_max_frame+1)*10; + return xran_fs_max_slot_num[PortId]; } -uint32_t xran_fs_get_max_slot(void) +uint32_t xran_fs_get_max_slot(uint32_t PortId) { - return xran_fs_max_slot_num; + return xran_fs_max_slot_num[PortId]; } -uint32_t xran_fs_get_max_slot_SFN(void) +uint32_t xran_fs_get_max_slot_SFN(uint32_t PortId) { - return xran_fs_max_slot_num_SFN; + return xran_fs_max_slot_num_SFN[PortId]; } -int32_t xran_fs_slot_limit(int32_t nSfIdx) +int32_t xran_fs_slot_limit(uint32_t PortId, int32_t nSfIdx) { while (nSfIdx < 0) { - nSfIdx += xran_fs_max_slot_num; + nSfIdx += xran_fs_max_slot_num[PortId]; } - while (nSfIdx >= xran_fs_max_slot_num) { - nSfIdx -= xran_fs_max_slot_num; + while (nSfIdx >= xran_fs_max_slot_num[PortId]) { + nSfIdx -= xran_fs_max_slot_num[PortId]; } return nSfIdx; } -void xran_fs_clear_slot_type(uint32_t nPhyInstanceId) +void xran_fs_clear_slot_type(uint32_t PortId, uint32_t nPhyInstanceId) { - xran_fs_ul_rate[nPhyInstanceId] = 0.0; - xran_fs_dl_rate[nPhyInstanceId] = 0.0; - xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1; + xran_fs_ul_rate[PortId][nPhyInstanceId] = 0.0; + xran_fs_dl_rate[PortId][nPhyInstanceId] = 0.0; + xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = 1; } -int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig) +int32_t xran_fs_set_slot_type(uint32_t PortId, uint32_t nPhyInstanceId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig) { uint32_t nSlotNum, nSymNum, nVal, i, j; uint32_t numDlSym, numUlSym, numGuardSym; @@ -355,28 +355,28 @@ int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType // nTddPeriod Tdd Periodicity // psSlotConfig[80] Slot Config Structure for nTddPeriod Slots - xran_fs_ul_rate[nPhyInstanceId] = 0.0; - xran_fs_dl_rate[nPhyInstanceId] = 0.0; - xran_fs_num_slot_tdd_loop[nPhyInstanceId] = nTddPeriod; + xran_fs_ul_rate[PortId][nPhyInstanceId] = 0.0; + xran_fs_dl_rate[PortId][nPhyInstanceId] = 0.0; + xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = nTddPeriod; for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++) { - xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID; - xran_fs_num_dl_sym_sp[nPhyInstanceId][i] = 0; - xran_fs_num_ul_sym_sp[nPhyInstanceId][i] = 0; + xran_fs_slot_type[PortId][nPhyInstanceId][i] = XRAN_SLOT_TYPE_INVALID; + xran_fs_num_dl_sym_sp[PortId][nPhyInstanceId][i] = 0; + xran_fs_num_ul_sym_sp[PortId][nPhyInstanceId][i] = 0; } if (nFrameDuplexType == XRAN_FDD) { for (i = 0; i < XRAN_NUM_OF_SLOT_IN_TDD_LOOP; i++) { - xran_fs_slot_type[nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD; + xran_fs_slot_type[PortId][nPhyInstanceId][i] = XRAN_SLOT_TYPE_FDD; for(j = 0; j < XRAN_NUM_OF_SYMBOL_PER_SLOT; j++) - xran_fs_slot_symb_type[nPhyInstanceId][i][j] = XRAN_SYMBOL_TYPE_FDD; + xran_fs_slot_symb_type[PortId][nPhyInstanceId][i][j] = XRAN_SYMBOL_TYPE_FDD; } - xran_fs_num_slot_tdd_loop[nPhyInstanceId] = 1; - xran_fs_dl_rate[nPhyInstanceId] = 1.0; - xran_fs_ul_rate[nPhyInstanceId] = 1.0; + xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] = 1; + xran_fs_dl_rate[PortId][nPhyInstanceId] = 1.0; + xran_fs_ul_rate[PortId][nPhyInstanceId] = 1.0; } else { @@ -391,14 +391,14 @@ int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType { case XRAN_SYMBOL_TYPE_DL: numDlSym++; - xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_DL; + xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_DL; break; case XRAN_SYMBOL_TYPE_GUARD: - xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_GUARD; + xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_GUARD; numGuardSym++; break; default: - xran_fs_slot_symb_type[nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_UL; + xran_fs_slot_symb_type[PortId][nPhyInstanceId][nSlotNum][nSymNum] = XRAN_SYMBOL_TYPE_UL; numUlSym++; break; } @@ -408,46 +408,46 @@ int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType if ((numUlSym == 0) && (numGuardSym == 0)) { - xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL; + xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_DL; numDlSlots++; print_dbg("XRAN_SLOT_TYPE_DL\n"); } else if ((numDlSym == 0) && (numGuardSym == 0)) { - xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL; + xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_UL; numUlSlots++; print_dbg("XRAN_SLOT_TYPE_UL\n"); } else { - xran_fs_slot_type[nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP; + xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum] = XRAN_SLOT_TYPE_SP; numSpSlots++; print_dbg("XRAN_SLOT_TYPE_SP\n"); if (numDlSym) { numSpDlSlots++; - xran_fs_num_dl_sym_sp[nPhyInstanceId][nSlotNum] = numDlSym; + xran_fs_num_dl_sym_sp[PortId][nPhyInstanceId][nSlotNum] = numDlSym; } if (numUlSym) { numSpUlSlots++; - xran_fs_num_ul_sym_sp[nPhyInstanceId][nSlotNum] = numUlSym; + xran_fs_num_ul_sym_sp[PortId][nPhyInstanceId][nSlotNum] = numUlSym; } } print_dbg(" numDlSlots[%d] numUlSlots[%d] numSpSlots[%d] numSpDlSlots[%d] numSpUlSlots[%d]\n", numDlSlots, numUlSlots, numSpSlots, numSpDlSlots, numSpUlSlots); } - xran_fs_dl_rate[nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod; - xran_fs_ul_rate[nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod; + xran_fs_dl_rate[PortId][nPhyInstanceId] = (float)(numDlSlots + numSpDlSlots) / (float)nTddPeriod; + xran_fs_ul_rate[PortId][nPhyInstanceId] = (float)(numUlSlots + numSpUlSlots) / (float)nTddPeriod; } print_dbg("%s: nPhyInstanceId[%d] nFrameDuplexType[%d], nTddPeriod[%d]\n", __FUNCTION__, nPhyInstanceId, nFrameDuplexType, nTddPeriod); - print_dbg("DLRate[%f] ULRate[%f]\n", xran_fs_dl_rate[nPhyInstanceId], xran_fs_ul_rate[nPhyInstanceId]); + print_dbg("DLRate[%f] ULRate[%f]\n", xran_fs_dl_rate[PortId][nPhyInstanceId], xran_fs_ul_rate[PortId][nPhyInstanceId]); - nVal = (xran_fs_num_slot_tdd_loop[nPhyInstanceId] < 10) ? xran_fs_num_slot_tdd_loop[nPhyInstanceId] : 10; + nVal = (xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] < 10) ? xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId] : 10; print_dbg("SlotPattern:\n"); print_dbg("Slot: "); @@ -458,11 +458,11 @@ int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType print_dbg("\n"); print_dbg(" %3d ", 0); - for (nSlotNum = 0, i = 0; nSlotNum < xran_fs_num_slot_tdd_loop[nPhyInstanceId]; nSlotNum++) + for (nSlotNum = 0, i = 0; nSlotNum < xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId]; nSlotNum++) { - print_dbg("%s ", sSlotPattern[xran_fs_slot_type[nPhyInstanceId][nSlotNum]]); + print_dbg("%s ", sSlotPattern[xran_fs_slot_type[PortId][nPhyInstanceId][nSlotNum]]); i++; - if ((i == 10) && ((nSlotNum+1) < xran_fs_num_slot_tdd_loop[nPhyInstanceId])) + if ((i == 10) && ((nSlotNum+1) < xran_fs_num_slot_tdd_loop[PortId][nPhyInstanceId])) { print_dbg("\n"); print_dbg(" %3d ", nSlotNum); @@ -474,12 +474,12 @@ int32_t xran_fs_set_slot_type(uint32_t nPhyInstanceId, uint32_t nFrameDuplexType return 0; } -int32_t xran_fs_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType) +int32_t xran_fs_get_slot_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nType) { int32_t nSfIdxMod, nSfType, ret = 0; - nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1); - nSfType = xran_fs_slot_type[nCellIdx][nSfIdxMod]; + nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1); + nSfType = xran_fs_slot_type[PortId][nCellIdx][nSfIdxMod]; if (nSfType == nType) { @@ -487,12 +487,12 @@ int32_t xran_fs_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType) } else if (nSfType == XRAN_SLOT_TYPE_SP) { - if ((nType == XRAN_SLOT_TYPE_DL) && xran_fs_num_dl_sym_sp[nCellIdx][nSfIdxMod]) + if ((nType == XRAN_SLOT_TYPE_DL) && xran_fs_num_dl_sym_sp[PortId][nCellIdx][nSfIdxMod]) { ret = 1; } - if ((nType == XRAN_SLOT_TYPE_UL) && xran_fs_num_ul_sym_sp[nCellIdx][nSfIdxMod]) + if ((nType == XRAN_SLOT_TYPE_UL) && xran_fs_num_ul_sym_sp[PortId][nCellIdx][nSfIdxMod]) { ret = 1; } @@ -505,13 +505,13 @@ int32_t xran_fs_get_slot_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nType) return ret; } -int32_t xran_fs_get_symbol_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx) +int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx) { int32_t nSfIdxMod, nSfType, ret = 0; - nSfIdxMod = xran_fs_slot_limit(nSlotdx) % ((xran_fs_num_slot_tdd_loop[nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[nCellIdx]: 1); + nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1); - return xran_fs_slot_symb_type[nCellIdx][nSfIdxMod][nSymbIdx]; + return xran_fs_slot_symb_type[PortId][nCellIdx][nSfIdxMod][nSymbIdx]; } diff --git a/fhi_lib/lib/src/xran_frame_struct.h b/fhi_lib/lib/src/xran_frame_struct.h index abc7f71..7ed0a3a 100644 --- a/fhi_lib/lib/src/xran_frame_struct.h +++ b/fhi_lib/lib/src/xran_frame_struct.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -67,14 +67,14 @@ uint16_t xran_fs_get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, uint32_t **/ //------------------------------------------------------------------------------------------- uint32_t xran_fs_cal_nrarfcn(uint32_t nCenterFreq); -int32_t xran_fs_slot_limit(int32_t nSlotIdx); -void xran_fs_clear_slot_type(uint32_t nCcId); -int32_t xran_fs_set_slot_type(uint32_t nCcId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig); -int32_t xran_fs_get_slot_type(int32_t nCcId, int32_t nSlotIdx, int32_t nType); -uint32_t xran_fs_slot_limit_init(int32_t tti_interval_us); -uint32_t xran_fs_get_max_slot(void); -uint32_t xran_fs_get_max_slot_SFN(void); -int32_t xran_fs_get_symbol_type(int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx); +int32_t xran_fs_slot_limit(uint32_t PortId, int32_t nSlotIdx); +void xran_fs_clear_slot_type(uint32_t PortId, uint32_t nCcId); +int32_t xran_fs_set_slot_type(uint32_t PortId, uint32_t nCcId, uint32_t nFrameDuplexType, uint32_t nTddPeriod, struct xran_slot_config* psSlotConfig); +int32_t xran_fs_get_slot_type(uint32_t PortId, int32_t nCcId, int32_t nSlotIdx, int32_t nType); +uint32_t xran_fs_slot_limit_init(uint32_t PortId, int32_t tti_interval_us); +uint32_t xran_fs_get_max_slot(uint32_t PortId); +uint32_t xran_fs_get_max_slot_SFN(uint32_t PortId); +int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx, int32_t nSymbIdx); #ifdef __cplusplus } diff --git a/fhi_lib/lib/src/xran_main.c b/fhi_lib/lib/src/xran_main.c index 17acc2a..89dcc1f 100644 --- a/fhi_lib/lib/src/xran_main.c +++ b/fhi_lib/lib/src/xran_main.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -45,10 +46,18 @@ #include #include #include - +#include +#include +#if (RTE_VER_YEAR >= 21) /* eCPRI flow supported with DPDK 21.02 or later */ +#include +#endif #include "xran_fh_o_du.h" +#include "xran_main.h" #include "ethdi.h" +#include "xran_mem_mgr.h" +#include "xran_tx_proc.h" +#include "xran_rx_proc.h" #include "xran_pkt.h" #include "xran_up_api.h" #include "xran_cp_api.h" @@ -56,159 +65,50 @@ #include "xran_lib_mlog_tasks_id.h" #include "xran_timer.h" #include "xran_common.h" +#include "xran_dev.h" #include "xran_frame_struct.h" #include "xran_printf.h" #include "xran_app_frag.h" +#include "xran_cp_proc.h" +#include "xran_tx_proc.h" +#include "xran_rx_proc.h" +#include "xran_cb_proc.h" +#include "xran_ecpri_owd_measurements.h" #include "xran_mlog_lnx.h" -#define DIV_ROUND_OFFSET(X,Y) ( X/Y + ((X%Y)?1:0) ) - -#define MAX_NUM_OF_XRAN_CTX (2) -#define XranIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_XRAN_CTX-1)) ? 0 : (ctx+1)) -#define XranDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_XRAN_CTX-1) : (ctx-1)) - -#define MAX_NUM_OF_DPDK_TIMERS (10) -#define DpdkTimerIncrementCtx(ctx) ((ctx >= (MAX_NUM_OF_DPDK_TIMERS-1)) ? 0 : (ctx+1)) -#define DpdkTimerDecrementCtx(ctx) ((ctx == 0) ? (MAX_NUM_OF_DPDK_TIMERS-1) : (ctx-1)) - -/* Difference between Unix seconds to GPS seconds - GPS epoch: 1980.1.6 00:00:00 (UTC); Unix time epoch: 1970:1.1 00:00:00 UTC - Value is calculated on Sep.6 2019. Need to be change if International - Earth Rotation and Reference Systems Service (IERS) adds more leap seconds - 1970:1.1 - 1980.1.6: 3657 days - 3657*24*3600=315 964 800 seconds (unix seconds value at 1980.1.6 00:00:00 (UTC)) - There are 18 leap seconds inserted after 1980.1.6 00:00:00 (UTC), which means - GPS is 18 larger. 315 964 800 - 18 = 315 964 782 -*/ -#define UNIX_TO_GPS_SECONDS_OFFSET 315964782UL -#define NUM_OF_FRAMES_PER_SFN_PERIOD 1024 -#define NUM_OF_FRAMES_PER_SECOND 100 - -//#define XRAN_CREATE_RBMAP /**< generate slot map base on symbols */ - - -struct xran_timer_ctx { - uint32_t tti_to_process; -}; - -enum xran_in_period -{ - XRAN_IN_PREV_PERIOD = 0, - XRAN_IN_CURR_PERIOD, - XRAN_IN_NEXT_PERIOD -}; - static xran_cc_handle_t pLibInstanceHandles[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR] = {NULL}; -static struct xran_device_ctx g_xran_dev_ctx[XRAN_PORTS_NUM] = { 0 }; - -struct xran_timer_ctx timer_ctx[MAX_NUM_OF_XRAN_CTX]; -struct xran_timer_ctx cb_timer_ctx[10*MAX_NUM_OF_XRAN_CTX]; +uint64_t interval_us = 1000; //the TTI interval of the cell with maximum numerology -static struct rte_timer tti_to_phy_timer[10]; -static struct rte_timer sym_timer; -static struct rte_timer dpdk_timer[MAX_NUM_OF_DPDK_TIMERS]; - -uint64_t interval_us = 1000; - -uint32_t xran_lib_ota_tti = 0; /**< Slot index in a second [0:(1000000/TTI-1)] */ -uint32_t xran_lib_ota_sym = 0; /**< Symbol index in a slot [0:13] */ -uint32_t xran_lib_ota_sym_idx = 0; /**< Symbol index in a second [0 : 14*(1000000/TTI)-1] +uint32_t xran_lib_ota_tti[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Slot index in a second [0:(1000000/TTI-1)] */ +uint32_t xran_lib_ota_sym[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Symbol index in a slot [0:13] */ +uint32_t xran_lib_ota_sym_idx[XRAN_PORTS_NUM] = {0,0,0,0}; /**< Symbol index in a second [0 : 14*(1000000/TTI)-1] where TTI is TTI interval in microseconds */ + uint16_t xran_SFN_at_Sec_Start = 0; /**< SFN at current second start */ uint16_t xran_max_frame = 1023; /**< value of max frame used. expected to be 99 (old compatibility mode) and 1023 as per section 9.7.2 System Frame Number Calculation */ -static uint8_t xran_cp_seq_id_num[XRAN_MAX_CELLS_PER_PORT][XRAN_DIR_MAX][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /* XRAN_MAX_ANTENNA_NR * 2 for PUSCH and PRACH */ -static uint8_t xran_updl_seq_id_num[XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR]; -static uint8_t xran_upul_seq_id_num[XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR]; /**< PUSCH, PRACH, SRS for Cat B */ - -static uint8_t xran_section_id_curslot[XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; -static uint16_t xran_section_id[XRAN_DIR_MAX][XRAN_MAX_CELLS_PER_PORT][XRAN_MAX_ANTENNA_NR * 2+ XRAN_MAX_ANT_ARRAY_ELM_NR]; static uint64_t xran_total_tick = 0, xran_used_tick = 0; -static uint32_t xran_core_used = 0; +static uint32_t xran_num_cores_used = 0; +static uint32_t xran_core_used[64] = {0}; static int32_t first_call = 0; - -static void -extbuf_free_callback(void *addr __rte_unused, void *opaque __rte_unused) -{ -} - -static struct rte_mbuf_ext_shared_info share_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; -static struct rte_mbuf_ext_shared_info cp_share_data[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - - -void xran_timer_arm(struct rte_timer *tim, void* arg); - -int32_t xran_process_tx_sym(void *arg); - -int32_t xran_process_rx_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free); - -int32_t xran_process_prach_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free); - -int32_t xran_process_srs_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free); - +struct cp_up_tx_desc * xran_pkt_gen_desc_alloc(void); +int32_t xran_pkt_gen_desc_free(struct cp_up_tx_desc *p_desc); void tti_ota_cb(struct rte_timer *tim, void *arg); void tti_to_phy_cb(struct rte_timer *tim, void *arg); -void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore); +int32_t xran_pkt_gen_process_ring(struct rte_ring *r); -// Return SFN at current second start, 10 bits, [0, 1023] -static inline uint16_t xran_getSfnSecStart(void) -{ - return xran_SFN_at_Sec_Start; -} -void xran_updateSfnSecStart(void) +void +xran_updateSfnSecStart(void) { struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters; + int32_t xran_ports = p_xran_dev_ctx->fh_init.xran_ports; + int32_t o_xu_id = 0; uint64_t currentSecond = timing_get_current_second(); // Assume always positive uint64_t gpsSecond = currentSecond - UNIX_TO_GPS_SECONDS_OFFSET; @@ -216,89 +116,62 @@ void xran_updateSfnSecStart(void) uint16_t sfn = (uint16_t)(nFrames % (xran_max_frame + 1)); xran_SFN_at_Sec_Start = sfn; + for(o_xu_id = 0; o_xu_id < xran_ports; o_xu_id++){ pCnt->tx_bytes_per_sec = pCnt->tx_bytes_counter; pCnt->rx_bytes_per_sec = pCnt->rx_bytes_counter; pCnt->tx_bytes_counter = 0; pCnt->rx_bytes_counter = 0; + p_xran_dev_ctx++; + pCnt = &p_xran_dev_ctx->fh_counters; + } } -static inline int32_t xran_getSlotIdxSecond(void) +static inline int32_t +xran_getSlotIdxSecond(uint32_t interval) { int32_t frameIdxSecond = xran_getSfnSecStart(); - int32_t slotIndxSecond = frameIdxSecond * SLOTS_PER_SYSTEMFRAME; + int32_t slotIndxSecond = frameIdxSecond * SLOTS_PER_SYSTEMFRAME(interval); return slotIndxSecond; } -struct xran_device_ctx *xran_dev_get_ctx(void) -{ - return &g_xran_dev_ctx[0]; -} - -static inline struct xran_fh_config *xran_lib_get_ctx_fhcfg(void) -{ - return (&(xran_dev_get_ctx()->fh_cfg)); -} - -static inline int32_t XranOffsetSym(int32_t offSym, int32_t otaSym, int32_t numSymTotal, enum xran_in_period* pInPeriod) -{ - int32_t sym; - - // Suppose the offset is usually small - if (unlikely(offSym > otaSym)) - { - sym = numSymTotal - offSym + otaSym; - *pInPeriod = XRAN_IN_PREV_PERIOD; - } - else - { - sym = otaSym - offSym; - - if (unlikely(sym >= numSymTotal)) - { - sym -= numSymTotal; - *pInPeriod = XRAN_IN_NEXT_PERIOD; - } - else +enum xran_if_state +xran_get_if_state(void) { - *pInPeriod = XRAN_IN_CURR_PERIOD; - } - } - - return sym; + return xran_if_current_state; } -uint16_t xran_get_beamid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id) +int32_t xran_is_prach_slot(uint8_t PortId, uint32_t subframe_id, uint32_t slot_id) { - return (0); // NO BEAMFORMING -} - -enum xran_if_state xran_get_if_state(void) + int32_t is_prach_slot = 0; + struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx_by_id(PortId); + if (p_xran_dev_ctx == NULL) { - return xran_if_current_state; + print_err("PortId %d not exist\n", PortId); + return is_prach_slot; } - -int xran_is_prach_slot(uint32_t subframe_id, uint32_t slot_id) -{ - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig); - int32_t is_prach_slot = 0; + uint8_t nNumerology = xran_get_conf_numerology(p_xran_dev_ctx); - if (p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology < 2){ + if (nNumerology < 2){ //for FR1, in 38.211 tab 6.3.3.2-2&3 it is subframe index if (pPrachCPConfig->isPRACHslot[subframe_id] == 1){ - if (pPrachCPConfig->nrofPrachInSlot != 1) + if (pPrachCPConfig->nrofPrachInSlot == 0){ + if(slot_id == 0) + is_prach_slot = 1; + } + else if (pPrachCPConfig->nrofPrachInSlot == 2) is_prach_slot = 1; else{ - if (p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology == 0) + if (nNumerology == 0) is_prach_slot = 1; else if (slot_id == 1) is_prach_slot = 1; } } - } else if (p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology == 3){ + } else if (nNumerology == 3){ //for FR2, 38.211 tab 6.3.3.4 it is slot index of 60kHz slot uint32_t slotidx; - slotidx = subframe_id * SLOTNUM_PER_SUBFRAME + slot_id; + slotidx = subframe_id * SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local) + slot_id; if (pPrachCPConfig->nrofPrachInSlot == 2){ if (pPrachCPConfig->isPRACHslot[slotidx>>1] == 1) is_prach_slot = 1; @@ -308,27 +181,12 @@ int xran_is_prach_slot(uint32_t subframe_id, uint32_t slot_id) } } } else - print_err("Numerology %d not supported", p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology); + print_err("Numerology %d not supported", nNumerology); return is_prach_slot; } -int xran_init_sectionid(void *pHandle) -{ - int cell, ant, dir; - - for (dir = 0; dir < XRAN_DIR_MAX; dir++){ - for(cell=0; cell < XRAN_MAX_CELLS_PER_PORT; cell++) { - for(ant=0; ant < XRAN_MAX_ANTENNA_NR; ant++) { - xran_section_id[dir][cell][ant] = 0; - xran_section_id_curslot[dir][cell][ant] = 255; - } - } - } - - return (0); -} - -int xran_init_srs(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) +int32_t +xran_init_srs(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) { struct xran_srs_config *p_srs = &(p_xran_dev_ctx->srs_cfg); @@ -341,13 +199,15 @@ int xran_init_srs(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_ return (XRAN_STATUS_SUCCESS); } -int xran_init_prach_lte(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) +int32_t +xran_init_prach_lte(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) { /* update Rach for LTE */ return xran_init_prach(pConf, p_xran_dev_ctx); } -int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) +int32_t +xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xran_dev_ctx) { int32_t i; uint8_t slotNr; @@ -412,207 +272,26 @@ int xran_init_prach(struct xran_fh_config* pConf, struct xran_device_ctx * p_xra printf("PRACH start symbol %u lastsymbol %u\n", p_xran_dev_ctx->prach_start_symbol[0], p_xran_dev_ctx->prach_last_symbol[0]); } - pPrachCPConfig->eAxC_offset = xran_get_num_eAxc(NULL); + pPrachCPConfig->eAxC_offset = xran_get_num_eAxc(p_xran_dev_ctx); print_dbg("PRACH eAxC_offset %d\n", pPrachCPConfig->eAxC_offset); - return (XRAN_STATUS_SUCCESS); -} - -inline uint16_t xran_alloc_sectionid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (0); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { //for PRACH, ant_id starts from num_ant - print_err("Invalid antenna ID - %d", ant_id); - return (0); - } - - /* if new slot has been started, - * then initializes section id again for new start */ - if(xran_section_id_curslot[dir][cc_id][ant_id] != slot_id) { - xran_section_id[dir][cc_id][ant_id] = 0; - xran_section_id_curslot[dir][cc_id][ant_id] = slot_id; - } - - return(xran_section_id[dir][cc_id][ant_id]++); -} - -int xran_init_seqid(void *pHandle) -{ - int cell, dir, ant; - - for(cell=0; cell < XRAN_MAX_CELLS_PER_PORT; cell++) { - for(dir=0; dir < XRAN_DIR_MAX; dir++) { - for(ant=0; ant < XRAN_MAX_ANTENNA_NR * 2; ant++) - xran_cp_seq_id_num[cell][dir][ant] = 0; - } - for(ant=0; ant < XRAN_MAX_ANTENNA_NR; ant++) - xran_updl_seq_id_num[cell][ant] = 0; - for(ant=0; ant < XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR; ant++) - xran_upul_seq_id_num[cell][ant] = 0; - } - - return (0); -} - -static inline uint8_t xran_get_cp_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id) -{ - if(dir >= XRAN_DIR_MAX) { - print_err("Invalid direction - %d", dir); - return (0); - } - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (0); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (0); - } - - return(xran_cp_seq_id_num[cc_id][dir][ant_id]++); -} -static inline uint8_t xran_get_updl_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (0); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (0); - } - - /* Only U-Plane DL needs to get sequence ID in O-DU */ - return(xran_updl_seq_id_num[cc_id][ant_id]++); -} -static inline uint8_t *xran_get_updl_seqid_addr(void *pHandle, uint8_t cc_id, uint8_t ant_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (NULL); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (NULL); - } - - /* Only U-Plane DL needs to get sequence ID in O-DU */ - return(&xran_updl_seq_id_num[cc_id][ant_id]); -} -static inline int8_t xran_check_upul_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id, uint8_t seq_id) -{ - - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (-1); - } - - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (-1); - } + /* Save some configs for app */ + pPRACHConfig->startSymId = pPrachCPConfig->startSymId; + pPRACHConfig->lastSymId = pPrachCPConfig->startSymId + pPrachCPConfig->numSymbol * pPrachCPConfig->occassionsInPrachSlot - 1; + pPRACHConfig->startPrbc = pPrachCPConfig->startPrbc; + pPRACHConfig->numPrbc = pPrachCPConfig->numPrbc; + pPRACHConfig->timeOffset = pPrachCPConfig->timeOffset; + pPRACHConfig->freqOffset = pPrachCPConfig->freqOffset; + pPRACHConfig->eAxC_offset = pPrachCPConfig->eAxC_offset; - /* O-DU needs to check the sequence ID of U-Plane UL from O-RU */ - xran_upul_seq_id_num[cc_id][ant_id]++; - if(xran_upul_seq_id_num[cc_id][ant_id] == seq_id) { /* expected sequence */ return (XRAN_STATUS_SUCCESS); - } else { - print_dbg("expected seqid %u received %u, slot %u, ant %u cc %u", xran_upul_seq_id_num[cc_id][ant_id], seq_id, slot_id, ant_id, cc_id); - xran_upul_seq_id_num[cc_id][ant_id] = seq_id; // for next - return (-1); - } -} - -////////////////////////////////////////// -// For RU emulation -static inline uint8_t xran_get_upul_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (0); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (0); - } - - return(xran_upul_seq_id_num[cc_id][ant_id]++); -} -static inline uint8_t *xran_get_upul_seqid_addr(void *pHandle, uint8_t cc_id, uint8_t ant_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (0); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2) { - print_err("Invalid antenna ID - %d", ant_id); - return (0); - } - - return(&xran_upul_seq_id_num[cc_id][ant_id]); -} -static inline int8_t xran_check_cp_seqid(void *pHandle, uint8_t dir, uint8_t cc_id, uint8_t ant_id, uint8_t seq_id) -{ - if(dir >= XRAN_DIR_MAX) { - print_err("Invalid direction - %d", dir); - return (-1); - } - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (-1); - } - if(ant_id >= XRAN_MAX_ANTENNA_NR * 2) { - print_err("Invalid antenna ID - %d", ant_id); - return (-1); - } - - xran_cp_seq_id_num[cc_id][dir][ant_id]++; - if(xran_cp_seq_id_num[cc_id][dir][ant_id] == seq_id) { /* expected sequence */ - return (0); } - else { - xran_cp_seq_id_num[cc_id][dir][ant_id] = seq_id; - return (-1); - } -} -static inline int8_t xran_check_updl_seqid(void *pHandle, uint8_t cc_id, uint8_t ant_id, uint8_t slot_id, uint8_t seq_id) -{ - if(cc_id >= XRAN_MAX_CELLS_PER_PORT) { - print_err("Invalid CC ID - %d", cc_id); - return (-1); - } - - if(ant_id >= XRAN_MAX_ANTENNA_NR) { - print_err("Invalid antenna ID - %d", ant_id); - return (-1); - } - - /* O-RU needs to check the sequence ID of U-Plane DL from O-DU */ - xran_updl_seq_id_num[cc_id][ant_id]++; - if(xran_updl_seq_id_num[cc_id][ant_id] == seq_id) { - /* expected sequence */ - /*print_dbg("ant %u cc_id %u : slot_id %u : seq_id %u : expected seq_id %u\n", - ant_id, cc_id, slot_id, seq_id, xran_updl_seq_id_num[cc_id][ant_id]);*/ - return (0); - } else { - /* print_err("ant %u cc_id %u : slot_id %u : seq_id %u : expected seq_id %u\n", - ant_id, cc_id, slot_id, seq_id, xran_updl_seq_id_num[cc_id][ant_id]);*/ - - xran_updl_seq_id_num[cc_id][ant_id] = seq_id; - - return (-1); - } -} -uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir) //dir = 0, from PHY slotid to xran spec slotid as defined in 5.3.2, dir=1, from xran slotid to phy slotid +uint32_t +xran_slotid_convert(uint16_t slot_id, uint16_t dir) //dir = 0, from PHY slotid to xran spec slotid as defined in 5.3.2, dir=1, from xran slotid to phy slotid { -#ifdef FCN_ADAPT return slot_id; -#endif - +#if 0 struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); uint8_t mu = p_xran_dev_ctx->fh_cfg.frame_conf.nNumerology; uint8_t FR = 1; @@ -640,76 +319,99 @@ uint32_t xran_slotid_convert(uint16_t slot_id, uint16_t dir) //dir = 0, from PHY return (slot_id >> (3-mu)); } } - -} - -static struct xran_section_gen_info cpSections[XRAN_MAX_NUM_SECTIONS]; -static struct xran_cp_gen_params cpInfo; -int process_cplane(struct rte_mbuf *pkt) -{ - struct xran_recv_packet_info recv; - - cpInfo.sections = cpSections; - xran_parse_cp_pkt(pkt, &cpInfo, &recv); - - return (MBUF_FREE); +#endif } -////////////////////////////////////////// -void sym_ota_cb(struct rte_timer *tim, void *arg, unsigned long *used_tick) +void +sym_ota_cb(struct rte_timer *tim, void *arg, unsigned long *used_tick) { - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)arg; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; long t1 = MLogTick(), t2; long t3; - static int32_t ctx = 0; - if(XranGetSymNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT) == 0){ + if(XranGetSymNum(xran_lib_ota_sym_idx[p_xran_dev_ctx->xran_port_id], XRAN_NUM_OF_SYMBOL_PER_SLOT) == 0){ t3 = xran_tick(); - tti_ota_cb(NULL, arg); + tti_ota_cb(NULL, (void*)p_xran_dev_ctx); *used_tick += get_ticks_diff(xran_tick(), t3); } -#if 0 - if(XranGetSymNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT) == 3){ - if(p_xran_dev_ctx->phy_tti_cb_done == 0){ - /* rearm timer to deliver TTI event to PHY */ t3 = xran_tick(); - p_xran_dev_ctx->phy_tti_cb_done = 0; - xran_timer_arm_ex(&tti_to_phy_timer[xran_lib_ota_tti % 10], tti_to_phy_cb, (void*)pTCtx, p_xran_dev_ctx->fh_init.io_cfg.timing_core); - *used_tick += get_ticks_diff(xran_tick(), t3); - } - } -#endif - - - t3 = xran_tick(); - if (xran_process_tx_sym(timer_ctx)) + if (xran_process_tx_sym(p_xran_dev_ctx)) { *used_tick += get_ticks_diff(xran_tick(), t3); } /* check if there is call back to do something else on this symbol */ - struct cb_elem_entry *cb_elm; - LIST_FOREACH(cb_elm, &p_xran_dev_ctx->sym_cb_list_head[0][xran_lib_ota_sym], pointers){ + LIST_FOREACH(cb_elm, &p_xran_dev_ctx->sym_cb_list_head[xran_lib_ota_sym[p_xran_dev_ctx->xran_port_id]], pointers){ if(cb_elm){ - cb_elm->pSymCallback(&dpdk_timer[ctx], cb_elm->pSymCallbackTag); - ctx = DpdkTimerIncrementCtx(ctx); + cb_elm->pSymCallback(&p_xran_dev_ctx->dpdk_timer[p_xran_dev_ctx->ctx % MAX_NUM_OF_DPDK_TIMERS], cb_elm->pSymCallbackTag, cb_elm->p_dev_ctx); + p_xran_dev_ctx->ctx = DpdkTimerIncrementCtx(p_xran_dev_ctx->ctx); } } - // This counter is incremented in advance before it is the time for the next symbol - xran_lib_ota_sym++; - if(xran_lib_ota_sym >= N_SYM_PER_SLOT){ - xran_lib_ota_sym=0; - } - t2 = MLogTick(); MLogTask(PID_SYM_OTA_CB, t1, t2); } -void tti_ota_cb(struct rte_timer *tim, void *arg) +uint32_t +xran_schedule_to_worker(enum xran_job_type_id job_type_id, struct xran_device_ctx * p_xran_dev_ctx) +{ + struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx(); + uint32_t tim_lcore = eth_ctx->io_cfg.timing_core; /* default to timing core */ + + if(eth_ctx) { + if(eth_ctx->num_workers == 0) { /* no workers */ + tim_lcore = eth_ctx->io_cfg.timing_core; + } else if (eth_ctx->num_workers == 1) { /* one worker */ + switch (job_type_id) + { + case XRAN_JOB_TYPE_OTA_CB: + tim_lcore = eth_ctx->io_cfg.timing_core; + break; + case XRAN_JOB_TYPE_CP_DL: + case XRAN_JOB_TYPE_CP_UL: + case XRAN_JOB_TYPE_DEADLINE: + case XRAN_JOB_TYPE_SYM_CB: + tim_lcore = eth_ctx->worker_core[0]; + break; + default: + print_err("incorrect job type id %d\n", job_type_id); + tim_lcore = eth_ctx->io_cfg.timing_core; + break; + } + } else if (eth_ctx->num_workers >= 2 && eth_ctx->num_workers <= 6) { + switch (job_type_id) + { + case XRAN_JOB_TYPE_OTA_CB: + tim_lcore = eth_ctx->worker_core[0]; + break; + case XRAN_JOB_TYPE_CP_DL: + tim_lcore = eth_ctx->worker_core[p_xran_dev_ctx->job2wrk_id[XRAN_JOB_TYPE_CP_DL]]; + break; + case XRAN_JOB_TYPE_CP_UL: + tim_lcore = eth_ctx->worker_core[p_xran_dev_ctx->job2wrk_id[XRAN_JOB_TYPE_CP_UL]]; + break; + case XRAN_JOB_TYPE_DEADLINE: + case XRAN_JOB_TYPE_SYM_CB: + tim_lcore = eth_ctx->worker_core[0]; + break; + default: + print_err("incorrect job type id %d\n", job_type_id); + tim_lcore = eth_ctx->io_cfg.timing_core; + break; + } + } else { + print_err("incorrect eth_ctx->num_workers id %d\n", eth_ctx->num_workers); + tim_lcore = eth_ctx->io_cfg.timing_core; + } + } + + return tim_lcore; +} + +void +tti_ota_cb(struct rte_timer *tim, void *arg) { uint32_t frame_id = 0; uint32_t subframe_id = 0; @@ -722,483 +424,352 @@ void tti_ota_cb(struct rte_timer *tim, void *arg) uint64_t t3 = 0; uint32_t reg_tti = 0; uint32_t reg_sfn = 0; - struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)arg; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + uint32_t i; + + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)p_xran_dev_ctx->timer_ctx; + uint8_t PortId = p_xran_dev_ctx->xran_port_id; + uint32_t interval_us_local = p_xran_dev_ctx->interval_us_local; + + unsigned tim_lcore = xran_schedule_to_worker(XRAN_JOB_TYPE_OTA_CB, p_xran_dev_ctx); - unsigned tim_lcore = (p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core) ? p_xran_dev_ctx->pkt_proc_core_id : - p_xran_dev_ctx->fh_init.io_cfg.timing_core; MLogTask(PID_TTI_TIMER, t1, MLogTick()); + if(p_xran_dev_ctx->xran_port_id == 0){ /* To match TTbox */ - if(xran_lib_ota_tti == 0) - reg_tti = xran_fs_get_max_slot() - 1; + if(xran_lib_ota_tti[0] == 0) + reg_tti = xran_fs_get_max_slot(PortId) - 1; else - reg_tti = xran_lib_ota_tti -1; + reg_tti = xran_lib_ota_tti[0] -1; + MLogIncrementCounter(); - reg_sfn = XranGetFrameNum(reg_tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME)*10 + XranGetSubFrameNum(reg_tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME);; + reg_sfn = XranGetFrameNum(reg_tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us))*10 + XranGetSubFrameNum(reg_tti,SLOTNUM_PER_SUBFRAME(interval_us), SUBFRAMES_PER_SYSTEMFRAME);; /* subframe and slot */ - MLogRegisterFrameSubframe(reg_sfn, reg_tti % (SLOTNUM_PER_SUBFRAME)); + MLogRegisterFrameSubframe(reg_sfn, reg_tti % (SLOTNUM_PER_SUBFRAME(interval_us))); MLogMark(1, t1); + } - slot_id = XranGetSlotNum(xran_lib_ota_tti, SLOTNUM_PER_SUBFRAME); - subframe_id = XranGetSubFrameNum(xran_lib_ota_tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - frame_id = XranGetFrameNum(xran_lib_ota_tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); + slot_id = XranGetSlotNum(xran_lib_ota_tti[PortId], SLOTNUM_PER_SUBFRAME(interval_us_local)); + subframe_id = XranGetSubFrameNum(xran_lib_ota_tti[PortId], SLOTNUM_PER_SUBFRAME(interval_us_local), SUBFRAMES_PER_SYSTEMFRAME); + frame_id = XranGetFrameNum(xran_lib_ota_tti[PortId],xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us_local)); - pTCtx[(xran_lib_ota_tti & 1) ^ 1].tti_to_process = xran_lib_ota_tti; + pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process = xran_lib_ota_tti[PortId]; mlogVar[mlogVarCnt++] = 0x11111111; - mlogVar[mlogVarCnt++] = xran_lib_ota_tti; - mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx; - mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx / 14; + mlogVar[mlogVarCnt++] = xran_lib_ota_tti[PortId]; + mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx[PortId]; + mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx[PortId] / 14; mlogVar[mlogVarCnt++] = frame_id; mlogVar[mlogVarCnt++] = subframe_id; mlogVar[mlogVarCnt++] = slot_id; mlogVar[mlogVarCnt++] = 0; MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); + if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_O_DU) - next_tti = xran_lib_ota_tti + 1; - else - next_tti = xran_lib_ota_tti; + next_tti = xran_lib_ota_tti[PortId] + 1; + else{ + next_tti = xran_lib_ota_tti[PortId]; + } - if(next_tti>= xran_fs_get_max_slot()){ + if(next_tti>= xran_fs_get_max_slot(PortId)){ print_dbg("[%d]SFN %d sf %d slot %d\n",next_tti, frame_id, subframe_id, slot_id); next_tti=0; } - slot_id = XranGetSlotNum(next_tti, SLOTNUM_PER_SUBFRAME); - subframe_id = XranGetSubFrameNum(next_tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - frame_id = XranGetFrameNum(next_tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); + slot_id = XranGetSlotNum(next_tti, SLOTNUM_PER_SUBFRAME(interval_us_local)); + subframe_id = XranGetSubFrameNum(next_tti,SLOTNUM_PER_SUBFRAME(interval_us_local), SUBFRAMES_PER_SYSTEMFRAME); + frame_id = XranGetFrameNum(next_tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us_local)); print_dbg("[%d]SFN %d sf %d slot %d\n",next_tti, frame_id, subframe_id, slot_id); if(p_xran_dev_ctx->fh_init.io_cfg.id == ID_O_DU){ - pTCtx[(xran_lib_ota_tti & 1)].tti_to_process = next_tti; + pTCtx[(xran_lib_ota_tti[PortId] & 1)].tti_to_process = next_tti; } else { - pTCtx[(xran_lib_ota_tti & 1)].tti_to_process = pTCtx[(xran_lib_ota_tti & 1)^1].tti_to_process; + pTCtx[(xran_lib_ota_tti[PortId] & 1)].tti_to_process = pTCtx[(xran_lib_ota_tti[PortId] & 1)^1].tti_to_process; } + if(p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]) { p_xran_dev_ctx->phy_tti_cb_done = 0; - xran_timer_arm_ex(&tti_to_phy_timer[xran_lib_ota_tti % 10], tti_to_phy_cb, (void*)pTCtx, tim_lcore); - + xran_timer_arm_ex(&p_xran_dev_ctx->tti_to_phy_timer[xran_lib_ota_tti[PortId] % MAX_TTI_TO_PHY_TIMER], tti_to_phy_cb, (void*)p_xran_dev_ctx, tim_lcore); + } //slot index is increased to next slot at the beginning of current OTA slot - xran_lib_ota_tti++; - if(xran_lib_ota_tti >= xran_fs_get_max_slot()){ - print_dbg("[%d]SFN %d sf %d slot %d\n",xran_lib_ota_tti, frame_id, subframe_id, slot_id); - xran_lib_ota_tti=0; + xran_lib_ota_tti[PortId]++; + if(xran_lib_ota_tti[PortId] >= xran_fs_get_max_slot(PortId)) { + print_dbg("[%d]SFN %d sf %d slot %d\n",xran_lib_ota_tti[PortId], frame_id, subframe_id, slot_id); + xran_lib_ota_tti[PortId] = 0; } MLogTask(PID_TTI_CB, t1, MLogTick()); } -void xran_timer_arm(struct rte_timer *tim, void* arg) +void +tx_cp_dl_cb(struct rte_timer *tim, void *arg) { - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint64_t t3 = MLogTick(); + long t1 = MLogTick(); + int tti, buf_id; + uint32_t slot_id, subframe_id, frame_id; + int cc_id; + uint8_t ctx_id; + uint8_t ant_id, num_eAxc, num_CCPorts; + void *pHandle; + int num_list; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + if(!p_xran_dev_ctx) + { + print_err("Null xRAN context!!\n"); + return; + } + struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)&p_xran_dev_ctx->timer_ctx[0]; + uint32_t interval_us_local = p_xran_dev_ctx->interval_us_local; + uint8_t PortId = p_xran_dev_ctx->xran_port_id; + pHandle = p_xran_dev_ctx; + + num_eAxc = xran_get_num_eAxc(pHandle); + num_CCPorts = xran_get_num_cc(pHandle); + + if(first_call && p_xran_dev_ctx->enableCP) { + + tti = pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process; + buf_id = tti % XRAN_N_FE_BUF_LEN; + + slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval_us_local)); + subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval_us_local), SUBFRAMES_PER_SYSTEMFRAME); + frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us_local)); + if (tti == 0){ + /* Wrap around to next second */ + frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; + } - if (xran_if_current_state == XRAN_RUNNING){ - rte_timer_cb_t fct = (rte_timer_cb_t)arg; - rte_timer_init(tim); - rte_timer_reset_sync(tim, 0, SINGLE, p_xran_dev_ctx->fh_init.io_cfg.timing_core, fct, &timer_ctx[0]); + ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval_us_local)) % XRAN_MAX_SECTIONDB_CTX; + + print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id); + for(ant_id = 0; ant_id < num_eAxc; ++ant_id) { + for(cc_id = 0; cc_id < num_CCPorts; cc_id++ ) { + /* start new section information list */ + xran_cp_reset_section_info(pHandle, XRAN_DIR_DL, cc_id, ant_id, ctx_id); + if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) { + if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers) { + if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData){ + num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_DL, tti, cc_id, + (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData, + p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id); + } else { + print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pData]\n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id); + } + } else { + print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d [pBuffers] \n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id); + } + } /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) */ + } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */ + } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */ + MLogTask(PID_CP_DL_CB, t1, MLogTick()); } - MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); } -void xran_timer_arm_for_deadline(struct rte_timer *tim, void* arg) +void +rx_ul_deadline_half_cb(struct rte_timer *tim, void *arg) { - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint64_t t3 = MLogTick(); - static int timer_cnt = 0; - unsigned tim_lcore = (p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core) ? p_xran_dev_ctx->pkt_proc_core_id : - p_xran_dev_ctx->fh_init.io_cfg.timing_core; - + long t1 = MLogTick(); + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + xran_status_t status; + /* half of RX for current TTI as measured against current OTA time */ int32_t rx_tti; int32_t cc_id; uint32_t nFrameIdx; uint32_t nSubframeIdx; uint32_t nSlotIdx; uint64_t nSecond; - - - xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + struct xran_timer_ctx* p_timer_ctx = NULL; + /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME + nSubframeIdx*SLOTNUM_PER_SUBFRAME - + nSlotIdx; + + nSlotIdx;*/ + if(p_xran_dev_ctx->xran2phy_mem_ready == 0) + return; - cb_timer_ctx[timer_cnt].tti_to_process = rx_tti; + p_timer_ctx = &p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put++ % MAX_CB_TIMER_CTX]; + if (p_xran_dev_ctx->timer_put >= MAX_CB_TIMER_CTX) + p_xran_dev_ctx->timer_put = 0; - if (xran_if_current_state == XRAN_RUNNING){ - rte_timer_cb_t fct = (rte_timer_cb_t)arg; - rte_timer_init(tim); - rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, &cb_timer_ctx[timer_cnt++]); - if (timer_cnt >= 10*MAX_NUM_OF_XRAN_CTX) - timer_cnt = 0; - } + rx_tti = p_timer_ctx->tti_to_process; - MLogTask(PID_TIME_ARM_TIMER_DEADLINE, t3, MLogTick()); -} + for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) { + if(p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] == 0){ + if(p_xran_dev_ctx->pCallback[cc_id]) { + struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id]; + if(pTag) { + //pTag->cellId = cc_id; + pTag->slotiId = rx_tti; + pTag->symbol = 0; /* last 7 sym means full slot of Symb */ + status = XRAN_STATUS_SUCCESS; + p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status); + } + } + } else { + p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] = 0; + } + } -void xran_timer_arm_ex(struct rte_timer *tim, void* CbFct, void *CbArg, unsigned tim_lcore) -{ - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint64_t t3 = MLogTick(); - - if (xran_if_current_state == XRAN_RUNNING){ - rte_timer_cb_t fct = (rte_timer_cb_t)CbFct; - rte_timer_init(tim); - rte_timer_reset_sync(tim, 0, SINGLE, tim_lcore, fct, CbArg); - } - MLogTask(PID_TIME_ARM_TIMER, t3, MLogTick()); -} - -uint16_t xran_map_ecpriRtcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id) -{ - return XRAN_CP_VF; -} - -uint16_t xran_map_ecpriPcid_to_vf(int32_t dir, int32_t cc_id, int32_t ru_port_id) -{ - return XRAN_UP_VF; -} - -int xran_cp_create_and_send_section(void *pHandle, uint8_t ru_port_id, int dir, int tti, int cc_id, - struct xran_prb_map *prbMap, enum xran_category category, uint8_t ctx_id) -{ - struct xran_device_ctx *p_x_ctx = xran_dev_get_ctx(); - struct xran_common_counters *pCnt = &p_x_ctx->fh_counters; - struct xran_cp_gen_params params; - struct xran_section_gen_info sect_geninfo[1]; - struct rte_mbuf *mbuf; - int ret = 0; - - uint32_t i, loc_sym; - uint32_t nsection = 0; - struct xran_prb_elm *pPrbMapElem = NULL; - struct xran_prb_elm *pPrbMapElemPrev = NULL; - uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - - frame_id = (frame_id & 0xff); /* ORAN frameId, 8 bits, [0, 255] */ - uint8_t seq_id = 0; - - struct xran_sectionext1_info m_ext1; - - if(prbMap) { - nsection = prbMap->nPrbElm; - pPrbMapElem = &prbMap->prbMap[0]; - if (nsection < 1){ - print_dbg("cp[%d:%d:%d] ru_port_id %d dir=%d nsection %d\n", - frame_id, subframe_id, slot_id, ru_port_id, dir, nsection); - } - } else { - print_err("prbMap is NULL\n"); - return (-1); - } - - for (i=0; iprbMap[i]; - params.dir = dir; - params.sectionType = XRAN_CP_SECTIONTYPE_1; /* Most DL/UL Radio Channels */ - params.hdr.filterIdx = XRAN_FILTERINDEX_STANDARD; - params.hdr.frameId = frame_id; - params.hdr.subframeId = subframe_id; - params.hdr.slotId = slot_id; - params.hdr.startSymId = pPrbMapElem->nStartSymb; - params.hdr.iqWidth = pPrbMapElem->iqWidth; /*xran_get_conf_iqwidth(pHandle);*/ - params.hdr.compMeth = pPrbMapElem->compMethod; - - print_dbg("cp[%d:%d:%d] ru_port_id %d dir=%d\n", - frame_id, subframe_id, slot_id, ru_port_id, dir); - - seq_id = xran_get_cp_seqid(pHandle, XRAN_DIR_DL, cc_id, ru_port_id); - - sect_geninfo[0].info.type = params.sectionType; // for database - sect_geninfo[0].info.startSymId = params.hdr.startSymId; // for database - sect_geninfo[0].info.iqWidth = params.hdr.iqWidth; // for database - sect_geninfo[0].info.compMeth = params.hdr.compMeth; // for database - - sect_geninfo[0].info.id = i; /*xran_alloc_sectionid(pHandle, dir, cc_id, ru_port_id, slot_id);*/ - - if(sect_geninfo[0].info.id > 7) - print_err("sectinfo->id %d\n", sect_geninfo[0].info.id); - - if (dir == XRAN_DIR_UL) { - for (loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++){ - struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym]; - if(p_sec_desc) { - p_sec_desc->section_id = sect_geninfo[0].info.id; - if(p_sec_desc->pCtrl) { - rte_pktmbuf_free(p_sec_desc->pCtrl); - p_sec_desc->pCtrl = NULL; - p_sec_desc->pData = NULL; - } - } else { - print_err("section desc is NULL\n"); - } - } - } - - sect_geninfo[0].info.rb = XRAN_RBIND_EVERY; - sect_geninfo[0].info.startPrbc = pPrbMapElem->nRBStart; - sect_geninfo[0].info.numPrbc = pPrbMapElem->nRBSize; - sect_geninfo[0].info.numSymbol = pPrbMapElem->numSymb; - sect_geninfo[0].info.reMask = 0xfff; - sect_geninfo[0].info.beamId = pPrbMapElem->nBeamIndex; - - for (loc_sym = 0; loc_sym < XRAN_NUM_OF_SYMBOL_PER_SLOT; loc_sym++){ - struct xran_section_desc *p_sec_desc = pPrbMapElem->p_sec_desc[loc_sym]; - if(p_sec_desc) { - p_sec_desc->section_id = sect_geninfo[0].info.id; - - sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_offset = p_sec_desc->iq_buffer_offset; - sect_geninfo[0].info.sec_desc[loc_sym].iq_buffer_len = p_sec_desc->iq_buffer_len; - } else { - print_err("section desc is NULL\n"); - } - } - - if (i==0) - sect_geninfo[0].info.symInc = XRAN_SYMBOLNUMBER_NOTINC; - else - { - pPrbMapElemPrev = &prbMap->prbMap[i-1]; - if (pPrbMapElemPrev->nStartSymb == pPrbMapElem->nStartSymb) - { - sect_geninfo[0].info.symInc = XRAN_SYMBOLNUMBER_NOTINC; - if (pPrbMapElemPrev->numSymb != pPrbMapElem->numSymb) - print_err("section info error: previous numSymb %d not equal to current numSymb %d\n", pPrbMapElemPrev->numSymb, pPrbMapElem->numSymb); - } - else - { - sect_geninfo[0].info.symInc = XRAN_SYMBOLNUMBER_INC; - if (pPrbMapElem->nStartSymb != (pPrbMapElemPrev->nStartSymb + pPrbMapElemPrev->numSymb)) - print_err("section info error: current startSym %d not equal to previous endSymb %d\n", pPrbMapElem->nStartSymb, pPrbMapElemPrev->nStartSymb + pPrbMapElemPrev->numSymb); - } - } - - if(category == XRAN_CATEGORY_A){ - /* no extention sections for category */ - sect_geninfo[0].info.ef = 0; - sect_geninfo[0].exDataSize = 0; - mbuf = xran_ethdi_mbuf_alloc(); - } else if (category == XRAN_CATEGORY_B) { - /*add extantion section for BF Weights if update is needed */ - if(pPrbMapElem->bf_weight_update){ - struct rte_mbuf_ext_shared_info * p_share_data = &cp_share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ru_port_id]; - - if (pPrbMapElem->bf_weight.p_ext_start){ - /* use buffer with BF Weights for mbuf */ - mbuf = xran_attach_cp_ext_buf(pPrbMapElem->bf_weight.p_ext_start, - pPrbMapElem->bf_weight.p_ext_section, pPrbMapElem->bf_weight.ext_section_sz, p_share_data); - } else { - print_err("Alloc fail!\n"); - return (-1); - } - - memset(&m_ext1, 0, sizeof (struct xran_sectionext1_info)); - m_ext1.bfwNumber = pPrbMapElem->bf_weight.nAntElmTRx; - m_ext1.bfwiqWidth = pPrbMapElem->iqWidth; - m_ext1.bfwCompMeth = pPrbMapElem->compMethod; - m_ext1.p_bfwIQ = (int16_t*)pPrbMapElem->bf_weight.p_ext_section; - m_ext1.bfwIQ_sz = pPrbMapElem->bf_weight.ext_section_sz; - - sect_geninfo[0].exData[0].type = XRAN_CP_SECTIONEXTCMD_1; - sect_geninfo[0].exData[0].len = sizeof(m_ext1); - sect_geninfo[0].exData[0].data = &m_ext1; - - sect_geninfo[0].info.ef = 1; - sect_geninfo[0].exDataSize = 1; - } else { - mbuf = xran_ethdi_mbuf_alloc(); - sect_geninfo[0].info.ef = 0; - sect_geninfo[0].exDataSize = 0; - } - } else { - print_err("Unsupported Category %d\n", category); - return (-1); - } - - if(unlikely(mbuf == NULL)) { - print_err("Alloc fail!\n"); - return (-1); - } - - params.numSections = 1;//nsection; - params.sections = sect_geninfo; - - ret = xran_prepare_ctrl_pkt(mbuf, ¶ms, cc_id, ru_port_id, seq_id); - if(ret < 0) { - print_err("Fail to build control plane packet - [%d:%d:%d] dir=%d\n", - frame_id, subframe_id, slot_id, dir); - } else { - /* add in the ethernet header */ - struct rte_ether_hdr *const h = (void *)rte_pktmbuf_prepend(mbuf, sizeof(*h)); - pCnt->tx_counter++; - pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(mbuf); - p_x_ctx->send_cpmbuf2ring(mbuf, ETHER_TYPE_ECPRI, xran_map_ecpriRtcid_to_vf(dir, cc_id, ru_port_id)); - - /*for(i=0; ienableCP) { - - tti = pTCtx[(xran_lib_ota_tti & 1) ^ 1].tti_to_process; - buf_id = tti % XRAN_N_FE_BUF_LEN; - - slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - if (tti == 0){ - /* Wrap around to next second */ - frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; + if(p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]){ + if(p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX] <= 0){ + p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX](p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]); + }else{ + p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]--; } - - ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME) % XRAN_MAX_SECTIONDB_CTX; - - print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id); - for(ant_id = 0; ant_id < num_eAxc; ++ant_id) { - for(cc_id = 0; cc_id < num_CCPorts; cc_id++ ) { - /* start new section information list */ - xran_cp_reset_section_info(pHandle, XRAN_DIR_DL, cc_id, ant_id, ctx_id); - if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) { - if(p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData){ - num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_DL, tti, cc_id, - (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData, - p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id); - } else { - print_err("[%d]SFN %d sf %d slot %d: ant_id %d cc_id %d \n", tti, frame_id, subframe_id, slot_id, ant_id, cc_id); - } - } /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_DL) == 1) */ - } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */ - } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */ - MLogTask(PID_CP_DL_CB, t1, MLogTick()); } -} - -void rx_ul_deadline_half_cb(struct rte_timer *tim, void *arg) -{ - long t1 = MLogTick(); - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - xran_status_t status; - /* half of RX for current TTI as measured against current OTA time */ - int32_t rx_tti; - int32_t cc_id; - uint32_t nFrameIdx; - uint32_t nSubframeIdx; - uint32_t nSlotIdx; - uint64_t nSecond; - - /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); - rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME - + nSubframeIdx*SLOTNUM_PER_SUBFRAME - + nSlotIdx;*/ - struct xran_timer_ctx* p_timer_ctx = (struct xran_timer_ctx*)arg; - rx_tti = p_timer_ctx->tti_to_process; - - if(p_xran_dev_ctx->xran2phy_mem_ready == 0) - return; - - for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) { - if(p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] == 0){ - struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id]; - pTag->cellId = cc_id; - pTag->slotiId = rx_tti; - pTag->symbol = 0; /* last 7 sym means full slot of Symb */ - status = XRAN_STATUS_SUCCESS; - if(p_xran_dev_ctx->pCallback[cc_id]) - p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status); - } else { - p_xran_dev_ctx->rx_packet_callback_tracker[rx_tti % XRAN_N_FE_BUF_LEN][cc_id] = 0; - } - } MLogTask(PID_UP_UL_HALF_DEAD_LINE_CB, t1, MLogTick()); } -void rx_ul_deadline_full_cb(struct rte_timer *tim, void *arg) +void +rx_ul_deadline_full_cb(struct rte_timer *tim, void *arg) { long t1 = MLogTick(); - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; xran_status_t status = 0; - int32_t rx_tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); + int32_t rx_tti = 0;// = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); int32_t cc_id = 0; uint32_t nFrameIdx; uint32_t nSubframeIdx; uint32_t nSlotIdx; uint64_t nSecond; + struct xran_timer_ctx* p_timer_ctx = NULL; + + if(p_xran_dev_ctx->xran2phy_mem_ready == 0) + return; - xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + /*xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); rx_tti = nFrameIdx*SUBFRAMES_PER_SYSTEMFRAME*SLOTNUM_PER_SUBFRAME + nSubframeIdx*SLOTNUM_PER_SUBFRAME - + nSlotIdx; + + nSlotIdx;*/ + p_timer_ctx = &p_xran_dev_ctx->cb_timer_ctx[p_xran_dev_ctx->timer_put++ % MAX_CB_TIMER_CTX]; + + if (p_xran_dev_ctx->timer_put >= MAX_CB_TIMER_CTX) + p_xran_dev_ctx->timer_put = 0; + rx_tti = p_timer_ctx->tti_to_process; +#if 1 if(rx_tti == 0) - rx_tti = (xran_fs_get_max_slot_SFN()-1); + rx_tti = (xran_fs_get_max_slot_SFN(p_xran_dev_ctx->xran_port_id)-1); else rx_tti -= 1; /* end of RX for prev TTI as measured against current OTA time */ - - if(p_xran_dev_ctx->xran2phy_mem_ready == 0) - return; - +#endif /* U-Plane */ for(cc_id = 0; cc_id < xran_get_num_cc(p_xran_dev_ctx); cc_id++) { + if(p_xran_dev_ctx->pCallback[cc_id]){ struct xran_cb_tag *pTag = p_xran_dev_ctx->pCallbackTag[cc_id]; - pTag->cellId = cc_id; + if(pTag) { + //pTag->cellId = cc_id; pTag->slotiId = rx_tti; pTag->symbol = 7; /* last 7 sym means full slot of Symb */ status = XRAN_STATUS_SUCCESS; - if(p_xran_dev_ctx->pCallback[cc_id]) p_xran_dev_ctx->pCallback[cc_id](p_xran_dev_ctx->pCallbackTag[cc_id], status); + } + } if(p_xran_dev_ctx->pPrachCallback[cc_id]){ struct xran_cb_tag *pTag = p_xran_dev_ctx->pPrachCallbackTag[cc_id]; - pTag->cellId = cc_id; + if(pTag) { + //pTag->cellId = cc_id; pTag->slotiId = rx_tti; pTag->symbol = 7; /* last 7 sym means full slot of Symb */ p_xran_dev_ctx->pPrachCallback[cc_id](p_xran_dev_ctx->pPrachCallbackTag[cc_id], status); } + } if(p_xran_dev_ctx->pSrsCallback[cc_id]){ struct xran_cb_tag *pTag = p_xran_dev_ctx->pSrsCallbackTag[cc_id]; - pTag->cellId = cc_id; + if(pTag) { + //pTag->cellId = cc_id; pTag->slotiId = rx_tti; pTag->symbol = 7; /* last 7 sym means full slot of Symb */ p_xran_dev_ctx->pSrsCallback[cc_id](p_xran_dev_ctx->pSrsCallbackTag[cc_id], status); } } + } + + /* user call backs if any */ + if(p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]){ + if(p_xran_dev_ctx->SkipTti[XRAN_CB_FULL_SLOT_RX] <= 0){ + p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX](p_xran_dev_ctx->TtiCbParam[XRAN_CB_FULL_SLOT_RX]); + }else{ + p_xran_dev_ctx->SkipTti[XRAN_CB_FULL_SLOT_RX]--; + } + } MLogTask(PID_UP_UL_FULL_DEAD_LINE_CB, t1, MLogTick()); } +void +rx_ul_user_sym_cb(struct rte_timer *tim, void *arg) +{ + long t1 = MLogTick(); + struct xran_device_ctx * p_dev_ctx = NULL; + struct cb_user_per_sym_ctx *p_sym_cb_ctx = (struct cb_user_per_sym_ctx *)arg; + xran_status_t status = 0; + int32_t rx_tti = 0; //(int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); + int32_t cc_id = 0; + uint32_t nFrameIdx; + uint32_t nSubframeIdx; + uint32_t nSlotIdx; + uint64_t nSecond; + uint32_t interval, ota_sym_idx = 0; + uint8_t nNumerology = 0; + struct xran_timer_ctx* p_timer_ctx = NULL; + + if(p_sym_cb_ctx->p_dev) + p_dev_ctx = (struct xran_device_ctx *)p_sym_cb_ctx->p_dev; + else + rte_panic("p_sym_cb_ctx->p_dev == NULL"); + + if(p_dev_ctx->xran2phy_mem_ready == 0) + return; + nNumerology = xran_get_conf_numerology(p_dev_ctx); + interval = p_dev_ctx->interval_us_local; + + p_timer_ctx = &p_sym_cb_ctx->user_cb_timer_ctx[p_sym_cb_ctx->user_timer_get++ % MAX_CB_TIMER_CTX]; + if (p_sym_cb_ctx->user_timer_get >= MAX_CB_TIMER_CTX) + p_sym_cb_ctx->user_timer_get = 0; + + rx_tti = p_timer_ctx->tti_to_process; + + if( p_sym_cb_ctx->sym_diff > 0) + /* + advacne TX Wind: at OTA Time we indicating event in future */ + ota_sym_idx = ((p_timer_ctx->ota_sym_idx + p_sym_cb_ctx->sym_diff) % xran_max_ota_sym_idx(nNumerology)); + else if (p_sym_cb_ctx->sym_diff < 0) { + /* - dealy RX Win: at OTA Time we indicate event in the past */ + if(p_timer_ctx->ota_sym_idx >= abs(p_sym_cb_ctx->sym_diff)) { + ota_sym_idx = p_timer_ctx->ota_sym_idx + p_sym_cb_ctx->sym_diff; + } else { + ota_sym_idx = ((xran_max_ota_sym_idx(nNumerology) + p_timer_ctx->ota_sym_idx) + p_sym_cb_ctx->sym_diff) % xran_max_ota_sym_idx(nNumerology); + } + } else /* 0 - OTA exact time */ + ota_sym_idx = p_timer_ctx->ota_sym_idx; + + rx_tti = (int32_t)XranGetTtiNum(ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); -void tx_cp_ul_cb(struct rte_timer *tim, void *arg) + if(p_sym_cb_ctx->symCbTimeInfo) { + struct xran_sense_of_time *p_sense_time = p_sym_cb_ctx->symCbTimeInfo; + p_sense_time->type_of_event = p_sym_cb_ctx->cb_type_id; + p_sense_time->nSymIdx = p_sym_cb_ctx->symb_num_req; + p_sense_time->tti_counter = rx_tti; + p_sense_time->nSlotIdx = (uint32_t)XranGetSlotNum(rx_tti, SLOTNUM_PER_SUBFRAME(interval)); + p_sense_time->nSubframeIdx = (uint32_t)XranGetSubFrameNum(rx_tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME); + p_sense_time->nFrameIdx = (uint32_t)XranGetFrameNum(rx_tti, p_timer_ctx->xran_sfn_at_sec_start,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval)); + p_sense_time->nSecond = p_timer_ctx->current_second; + } + + /* user call backs if any */ + if(p_sym_cb_ctx->symCb){ + p_sym_cb_ctx->symCb(p_sym_cb_ctx->symCbParam, p_sym_cb_ctx->symCbTimeInfo); + } + + MLogTask(PID_UP_UL_USER_DEAD_LINE_CB, t1, MLogTick()); +} + +void +tx_cp_ul_cb(struct rte_timer *tim, void *arg) { long t1 = MLogTick(); int tti, buf_id; @@ -1206,6 +777,7 @@ void tx_cp_ul_cb(struct rte_timer *tim, void *arg) uint32_t slot_id, subframe_id, frame_id; int32_t cc_id; int ant_id, prach_port_id; + uint16_t occasionid; uint16_t beam_id; uint8_t num_eAxc, num_CCPorts; uint8_t ctx_id; @@ -1213,28 +785,34 @@ void tx_cp_ul_cb(struct rte_timer *tim, void *arg) void *pHandle; int num_list; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + if(!p_xran_dev_ctx) + { + print_err("Null xRAN context!!\n"); + return; + } struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig); - struct xran_timer_ctx *pTCtx = (struct xran_timer_ctx *)arg; + struct xran_timer_ctx *pTCtx = &p_xran_dev_ctx->timer_ctx[0]; + uint32_t interval = p_xran_dev_ctx->interval_us_local; + uint8_t PortId = p_xran_dev_ctx->xran_port_id; - pHandle = NULL; // TODO: temp implemantation + tti = pTCtx[(xran_lib_ota_tti[PortId] & 1) ^ 1].tti_to_process; + buf_id = tti % XRAN_N_FE_BUF_LEN; + slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval)); + subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME); + frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval)); + if (tti == 0) { + //Wrap around to next second + frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; + } + ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval)) % XRAN_MAX_SECTIONDB_CTX; + pHandle = p_xran_dev_ctx; if(xran_get_ru_category(pHandle) == XRAN_CATEGORY_A) num_eAxc = xran_get_num_eAxc(pHandle); else num_eAxc = xran_get_num_eAxcUl(pHandle); - num_CCPorts = xran_get_num_cc(pHandle); - tti = pTCtx[(xran_lib_ota_tti & 1) ^ 1].tti_to_process; - buf_id = tti % XRAN_N_FE_BUF_LEN; - slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - if (tti == 0) { - //Wrap around to next second - frame_id = (frame_id + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; - } - ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME) % XRAN_MAX_SECTIONDB_CTX; if(first_call && p_xran_dev_ctx->enableCP) { @@ -1242,22 +820,27 @@ void tx_cp_ul_cb(struct rte_timer *tim, void *arg) for(ant_id = 0; ant_id < num_eAxc; ++ant_id) { for(cc_id = 0; cc_id < num_CCPorts; cc_id++) { - if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_UL) == 1 || - xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_SP) == 1 ){ + if(xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_UL) == 1 + /* || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_SP) == 1*/ ) { /* start new section information list */ xran_cp_reset_section_info(pHandle, XRAN_DIR_UL, cc_id, ant_id, ctx_id); + if(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers){ + if(p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData){ num_list = xran_cp_create_and_send_section(pHandle, ant_id, XRAN_DIR_UL, tti, cc_id, (struct xran_prb_map *)p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[buf_id][cc_id][ant_id].sBufferList.pBuffers->pData, p_xran_dev_ctx->fh_cfg.ru_conf.xranCat, ctx_id); - } /* if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_UL) == 1 */ - } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */ - } /* for(ant_id = 0; ant_id < num_eAxc; ++ant_id) */ + } + } + } + } + } if(p_xran_dev_ctx->enablePrach) { - uint32_t is_prach_slot = xran_is_prach_slot(subframe_id, slot_id); + uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id); if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0]) && (is_prach_slot==1)) { //is prach slot for(ant_id = 0; ant_id < num_eAxc; ++ant_id) { for(cc_id = 0; cc_id < num_CCPorts; cc_id++) { + for (occasionid = 0; occasionid < pPrachCPConfig->occassionsInPrachSlot; occasionid++) { struct xran_cp_gen_params params; struct xran_section_gen_info sect_geninfo[8]; struct rte_mbuf *mbuf = xran_ethdi_mbuf_alloc(); @@ -1268,7 +851,7 @@ void tx_cp_ul_cb(struct rte_timer *tim, void *arg) beam_id = xran_get_beamid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id, slot_id); ret = generate_cpmsg_prach(pHandle, ¶ms, sect_geninfo, mbuf, p_xran_dev_ctx, frame_id, subframe_id, slot_id, - beam_id, cc_id, prach_port_id, + beam_id, cc_id, prach_port_id, occasionid, xran_get_cp_seqid(pHandle, XRAN_DIR_UL, cc_id, prach_port_id)); if (ret == XRAN_STATUS_SUCCESS) send_cpmsg(pHandle, mbuf, ¶ms, sect_geninfo, @@ -1277,22 +860,18 @@ void tx_cp_ul_cb(struct rte_timer *tim, void *arg) } } } + } } /* if(p_xran_dev_ctx->enableCP) */ MLogTask(PID_CP_UL_CB, t1, MLogTick()); } -void ul_up_full_slot_cb(struct rte_timer *tim, void *arg) -{ - long t1 = MLogTick(); - rte_pause(); - MLogTask(PID_TTI_CB_TO_PHY, t1, MLogTick()); -} - -void tti_to_phy_cb(struct rte_timer *tim, void *arg) +void +tti_to_phy_cb(struct rte_timer *tim, void *arg) { long t1 = MLogTick(); - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + uint32_t interval = p_xran_dev_ctx->interval_us_local; p_xran_dev_ctx->phy_tti_cb_done = 1; /* DPDK called CB */ if (first_call){ @@ -1305,11 +884,11 @@ void tti_to_phy_cb(struct rte_timer *tim, void *arg) } } else { if(p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]){ - int32_t tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); - uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - if((frame_id == xran_max_frame)&&(subframe_id==9)&&(slot_id == SLOTNUM_PER_SUBFRAME-1)) { //(tti == xran_fs_get_max_slot()-1) + int32_t tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx[p_xran_dev_ctx->xran_port_id], XRAN_NUM_OF_SYMBOL_PER_SLOT); + uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval)); + uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME); + uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval)); + if((frame_id == xran_max_frame)&&(subframe_id==9)&&(slot_id == SLOTNUM_PER_SUBFRAME(interval)-1)) { //(tti == xran_fs_get_max_slot()-1) first_call = 1; } } @@ -1318,7 +897,8 @@ void tti_to_phy_cb(struct rte_timer *tim, void *arg) MLogTask(PID_TTI_CB_TO_PHY, t1, MLogTick()); } -int xran_timing_source_thread(void *args) +int32_t +xran_timing_source_thread(void *args) { int res = 0; cpu_set_t cpuset; @@ -1326,35 +906,28 @@ int xran_timing_source_thread(void *args) uint64_t t1 = 0; uint64_t delta; int32_t result1,i,j; - uint32_t delay_cp_dl; - uint32_t delay_cp_ul; - uint32_t delay_up; - uint32_t delay_up_ul; - uint32_t delay_cp2up; - uint32_t sym_cp_dl; - uint32_t sym_cp_ul; - uint32_t sym_up_ul; - int32_t sym_up; + + uint32_t xran_port_id = 0; + static int owdm_init_done = 0; + struct sched_param sched_param; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *) args ; uint64_t tWake = 0, tWakePrev = 0, tUsed = 0; struct cb_elem_entry * cb_elm = NULL; + struct xran_device_ctx * p_dev_ctx_run = NULL; /* ToS = Top of Second start +- 1.5us */ struct timespec ts; - + char thread_name[32]; char buff[100]; - xran_core_used = rte_lcore_id(); printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, rte_lcore_id(), getpid()); - memset(&sched_param, 0, sizeof(struct sched_param)); - /* set main thread affinity mask to CPU2 */ sched_param.sched_priority = XRAN_THREAD_DEFAULT_PRIO; - CPU_ZERO(&cpuset); - CPU_SET(p_xran_dev_ctx->fh_init.io_cfg.timing_core, &cpuset); + CPU_SET(p_dev_ctx->fh_init.io_cfg.timing_core, &cpuset); + if (result1 = pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpuset)) { printf("pthread_setaffinity_np failed: coreId = 2, result1 = %d\n",result1); @@ -1364,103 +937,51 @@ int xran_timing_source_thread(void *args) printf("priority is not changed: coreId = 2, result1 = %d\n",result1); } - if (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { - do { - timespec_get(&ts, TIME_UTC); - }while (ts.tv_nsec >1500); - struct tm * ptm = gmtime(&ts.tv_sec); - if(ptm){ - strftime(buff, sizeof buff, "%D %T", ptm); - printf("O-DU: thread_run start time: %s.%09ld UTC [%ld]\n", buff, ts.tv_nsec, interval_us); + snprintf(thread_name, RTE_DIM(thread_name), "%s-%d", "fh_main_poll", rte_lcore_id()); + if ((res = pthread_setname_np(pthread_self(), thread_name))) { + printf("[core %d] pthread_setname_np = %d\n",rte_lcore_id(), res); } - delay_cp_dl = interval_us - p_xran_dev_ctx->fh_init.T1a_max_cp_dl; - delay_cp_ul = interval_us - p_xran_dev_ctx->fh_init.T1a_max_cp_ul; - delay_up = p_xran_dev_ctx->fh_init.T1a_max_up; - delay_up_ul = p_xran_dev_ctx->fh_init.Ta4_max; - - delay_cp2up = delay_up-delay_cp_dl; - - sym_cp_dl = delay_cp_dl*1000/(interval_us*1000/N_SYM_PER_SLOT)+1; - sym_cp_ul = delay_cp_ul*1000/(interval_us*1000/N_SYM_PER_SLOT)+1; - sym_up_ul = delay_up_ul*1000/(interval_us*1000/N_SYM_PER_SLOT); - p_xran_dev_ctx->sym_up = sym_up = -(delay_up*1000/(interval_us*1000/N_SYM_PER_SLOT)); - p_xran_dev_ctx->sym_up_ul = sym_up_ul = (delay_up_ul*1000/(interval_us*1000/N_SYM_PER_SLOT)+1); - - printf("Start C-plane DL %d us after TTI [trigger on sym %d]\n", delay_cp_dl, sym_cp_dl); - printf("Start C-plane UL %d us after TTI [trigger on sym %d]\n", delay_cp_ul, sym_cp_ul); - printf("Start U-plane DL %d us before OTA [offset in sym %d]\n", delay_up, sym_up); - printf("Start U-plane UL %d us OTA [offset in sym %d]\n", delay_up_ul, sym_up_ul); - - printf("C-plane to U-plane delay %d us after TTI\n", delay_cp2up); - printf("Start Sym timer %ld ns\n", TX_TIMER_INTERVAL/N_SYM_PER_SLOT); - - cb_elm = xran_create_cb(xran_timer_arm, tx_cp_dl_cb); - if(cb_elm){ - LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_cp_dl], - cb_elm, - pointers); - } else { - print_err("cb_elm is NULL\n"); - res = -1; - goto err0; - } + printf("TTI interval %ld [us]\n", interval_us); - cb_elm = xran_create_cb(xran_timer_arm, tx_cp_ul_cb); - if(cb_elm){ - LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_cp_ul], - cb_elm, - pointers); - } else { - print_err("cb_elm is NULL\n"); - res = -1; - goto err0; + if (!p_dev_ctx->fh_init.io_cfg.eowd_cmn[p_dev_ctx->fh_init.io_cfg.id].owdm_enable) { + if ((res = xran_timing_create_cbs(args)) < 0){ + return res; } - - /* Full slot UL OTA + delay_up_ul */ - cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_full_cb); - if(cb_elm){ - LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_up_ul], - cb_elm, - pointers); - } else { - print_err("cb_elm is NULL\n"); - res = -1; - goto err0; } - /* Half slot UL OTA + delay_up_ul*/ - cb_elm = xran_create_cb(xran_timer_arm_for_deadline, rx_ul_deadline_half_cb); - if(cb_elm){ - LIST_INSERT_HEAD(&p_xran_dev_ctx->sym_cb_list_head[0][sym_up_ul + N_SYM_PER_SLOT/2], - cb_elm, - pointers); - } else { - print_err("cb_elm is NULL\n"); - res = -1; - goto err0; - } - } else { // APP_O_RU - /* calcualte when to send UL U-plane */ - delay_up = p_xran_dev_ctx->fh_init.Ta3_min; - p_xran_dev_ctx->sym_up = sym_up = delay_up*1000/(interval_us*1000/N_SYM_PER_SLOT)+1; - printf("Start UL U-plane %d us after OTA [offset in sym %d]\n", delay_up, sym_up); do { timespec_get(&ts, TIME_UTC); }while (ts.tv_nsec >1500); + struct tm * ptm = gmtime(&ts.tv_sec); if(ptm){ strftime(buff, sizeof buff, "%D %T", ptm); - printf("RU: thread_run start time: %s.%09ld UTC [%ld]\n", buff, ts.tv_nsec, interval_us); - } + printf("%s: thread_run start time: %s.%09ld UTC [%ld]\n", + (p_dev_ctx->fh_init.io_cfg.id == O_DU ? "O-DU": "O-RU"), buff, ts.tv_nsec, interval_us); } - printf("interval_us %ld\n", interval_us); do { timespec_get(&ts, TIME_UTC); }while (ts.tv_nsec == 0); + p_dev_ctx->timing_source_thread_running = 1; while(1) { + + /* Check if owdm finished to create the timing cbs based on measurement results */ + if ((p_dev_ctx->fh_init.io_cfg.eowd_cmn[p_dev_ctx->fh_init.io_cfg.id].owdm_enable)&&(!owdm_init_done)&&unlikely(XRAN_RUNNING == xran_if_current_state)) { + // Adjust Windows based on Delay Measurement results + xran_adjust_timing_parameters(p_dev_ctx); + if ((res = xran_timing_create_cbs(args)) < 0){ + return res; + } + printf("TTI interval %ld [us]\n", interval_us); + owdm_init_done = 1; + + } + + + /* Update Usage Stats */ tWake = xran_tick(); xran_used_tick += tUsed; @@ -1475,1039 +996,161 @@ int xran_timing_source_thread(void *args) if (XRAN_STOPPED == xran_if_current_state) break; - if (likely(XRAN_RUNNING == xran_if_current_state)) - sym_ota_cb(&sym_timer, timer_ctx, &tUsed); + if (likely(XRAN_RUNNING == xran_if_current_state)) { + for(xran_port_id = 0; xran_port_id < XRAN_PORTS_NUM; xran_port_id++ ) { + p_dev_ctx_run = xran_dev_get_ctx_by_id(xran_port_id); + if(p_dev_ctx_run) { + if(p_dev_ctx_run->xran_port_id == xran_port_id) { + if(XranGetSymNum(xran_lib_ota_sym_idx[p_dev_ctx_run->xran_port_id], XRAN_NUM_OF_SYMBOL_PER_SLOT) == xran_lib_ota_sym[xran_port_id]) + { + sym_ota_cb(&p_dev_ctx_run->sym_timer, p_dev_ctx_run, &tUsed); + xran_lib_ota_sym[xran_port_id]++; + if(xran_lib_ota_sym[xran_port_id] >= N_SYM_PER_SLOT) + xran_lib_ota_sym[xran_port_id]=0; + } + } + else { + rte_panic("p_dev_ctx_run == xran_port_id"); } - - err0: - for (i = 0; i< XRAN_MAX_SECTOR_NR; i++){ - for (j = 0; j< XRAN_NUM_OF_SYMBOL_PER_SLOT; j++){ - struct cb_elem_entry *cb_elm; - LIST_FOREACH(cb_elm, &p_xran_dev_ctx->sym_cb_list_head[i][j], pointers){ - if(cb_elm){ - LIST_REMOVE(cb_elm, pointers); - xran_destroy_cb(cb_elm); } } } } + xran_timing_destroy_cbs(args); printf("Closing timing source thread...\n"); return res; } /* Handle ecpri format. */ -int handle_ecpri_ethertype(struct rte_mbuf *pkt, uint64_t rx_time) +#define MBUFS_CNT 16 + +int32_t handle_ecpri_ethertype(struct rte_mbuf* pkt_q[], uint16_t xport_id, struct xran_eaxc_info *p_cid, uint16_t num) { - const struct xran_ecpri_hdr *ecpri_hdr; + struct rte_mbuf* pkt, * pkt0; + uint16_t i; + struct rte_ether_hdr* eth_hdr; + struct xran_ecpri_hdr* ecpri_hdr; + union xran_ecpri_cmn_hdr* ecpri_cmn; unsigned long t1; int32_t ret = MBUF_FREE; + uint32_t ret_data[MBUFS_CNT] = { MBUFS_CNT * MBUF_FREE }; + struct xran_device_ctx* p_dev_ctx = xran_dev_get_ctx_by_id(xport_id); + uint16_t num_data = 0, num_control = 0, num_meas = 0; + struct rte_mbuf* pkt_data[MBUFS_CNT], * pkt_control[MBUFS_CNT], * pkt_meas[MBUFS_CNT], *pkt_adj[MBUFS_CNT]; + static uint32_t owdm_rx_first_pass = 1; - if (rte_pktmbuf_data_len(pkt) < sizeof(struct xran_ecpri_hdr)) { - print_err("Packet too short - %d bytes", rte_pktmbuf_data_len(pkt)); - return 0; - } + if (p_dev_ctx == NULL) + return ret; - /* check eCPRI header. */ + for (i = 0; i < num; i++) + { + pkt = pkt_q[i]; + +// rte_prefetch0(rte_pktmbuf_mtod(pkt, void*)); + + rte_pktmbuf_adj(pkt, sizeof(*eth_hdr)); ecpri_hdr = rte_pktmbuf_mtod(pkt, struct xran_ecpri_hdr *); - if(ecpri_hdr == NULL){ - print_err("ecpri_hdr error\n"); - return MBUF_FREE; - } - xran_dev_get_ctx()->fh_counters.rx_bytes_counter += rte_pktmbuf_pkt_len(pkt); - switch(ecpri_hdr->cmnhdr.ecpri_mesg_type) { + p_dev_ctx->fh_counters.rx_bytes_counter += rte_pktmbuf_pkt_len(pkt); + + pkt_adj[i] = pkt; + switch (ecpri_hdr->cmnhdr.bits.ecpri_mesg_type) + { case ECPRI_IQ_DATA: - // t1 = MLogTick(); - ret = process_mbuf(pkt); - // MLogTask(PID_PROCESS_UP_PKT, t1, MLogTick()); + pkt_data[num_data++] = pkt; break; // For RU emulation case ECPRI_RT_CONTROL_DATA: - t1 = MLogTick(); - if(xran_dev_get_ctx()->fh_init.io_cfg.id == O_RU) { - ret = process_cplane(pkt); - xran_dev_get_ctx()->fh_counters.rx_counter++; - } else { - print_err("O-DU recevied C-Plane message!"); - } - MLogTask(PID_PROCESS_CP_PKT, t1, MLogTick()); + pkt_control[num_control++] = pkt; break; - default: - print_err("Invalid eCPRI message type - %d", ecpri_hdr->cmnhdr.ecpri_mesg_type); - } - - return ret; -} - -int xran_process_prach_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free) + case ECPRI_DELAY_MEASUREMENT: + if (owdm_rx_first_pass != 0) { - char *pos = NULL; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint8_t symb_id_offset; - uint32_t tti = 0; - xran_status_t status; - void *pHandle = NULL; - struct rte_mbuf *mb; - - uint16_t iq_sample_size_bits = 16; - - if(p_xran_dev_ctx->xran2phy_mem_ready == 0) - return 0; + // Initialize and verify that Payload Length is in range */ + xran_initialize_and_verify_owd_pl_length((void*)p_dev_ctx); + owdm_rx_first_pass = 0; - tti = frame_id * SLOTS_PER_SYSTEMFRAME + subframe_id * SLOTNUM_PER_SUBFRAME + slot_id; - - status = tti << 16 | symb_id; - - if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){ - symb_id_offset = symb_id - p_xran_dev_ctx->prach_start_symbol[CC_ID]; //make the storing of prach packets to start from 0 for easy of processing within PHY - pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData; - if(pos && iq_data_start && size){ - if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { - int idx = 0; - uint16_t *psrc = (uint16_t *)iq_data_start; - uint16_t *pdst = (uint16_t *)pos; - /* network byte (be) order of IQ to CPU byte order (le) */ - for (idx = 0; idx < size/sizeof(int16_t); idx++){ - pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); - } - *mb_free = MBUF_FREE; - }else { - mb = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl; - if(mb){ - rte_pktmbuf_free(mb); - }else{ - print_err("mb==NULL\n"); } - p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData = iq_data_start; - p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl = mbuf; - *mb_free = MBUF_KEEP; - } - } else { - print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); + pkt_meas[num_meas++] = pkt; + break; + default: + if (p_dev_ctx->fh_init.io_cfg.id == O_DU) { + print_err("Invalid eCPRI message type - %d", ecpri_hdr->cmnhdr.bits.ecpri_mesg_type); } - } else { - print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); + break; } - - return size; } -int32_t xran_process_srs_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free) + if(num_data == MBUFS_CNT && p_dev_ctx->fh_cfg.ru_conf.xranCat == XRAN_CATEGORY_B) /* w/a for Cat A issue */ { - char *pos = NULL; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint32_t tti = 0; - xran_status_t status; - struct rte_mbuf *mb = NULL; - - uint16_t iq_sample_size_bits = 16; - - if(p_xran_dev_ctx->xran2phy_mem_ready == 0) - return 0; - - tti = frame_id * SLOTS_PER_SYSTEMFRAME + subframe_id * SLOTNUM_PER_SUBFRAME + slot_id; - - status = tti << 16 | symb_id; - - if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < p_xran_dev_ctx->fh_cfg.nAntElmTRx && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT) { - pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData; - pos += start_prbu * N_SC_PER_PRB*(iq_sample_size_bits/8)*2; - if(pos && iq_data_start && size){ - if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { - int idx = 0; - uint16_t *psrc = (uint16_t *)iq_data_start; - uint16_t *pdst = (uint16_t *)pos; - rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb); - /* network byte (be) order of IQ to CPU byte order (le) */ - for (idx = 0; idx < size/sizeof(int16_t); idx++){ - pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); - } - } else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){ - if (likely (p_xran_dev_ctx->fh_init.mtu >= - p_xran_dev_ctx->fh_cfg.nULRBs * N_SC_PER_PRB*(iq_sample_size_bits/8)*2)) { - /* no fragmentation */ - mb = p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl; - if(mb){ - rte_pktmbuf_free(mb); - }else{ - print_err("mb==NULL\n"); - } - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData = iq_data_start; - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl = mbuf; - *mb_free = MBUF_KEEP; - } else { - /* packet can be fragmented copy RBs */ - rte_memcpy(pos, iq_data_start, size); - *mb_free = MBUF_FREE; - } - } - } else { - print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); - } - } else { - print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); - } - - return size; -} - -int32_t xran_pkt_validate(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - struct ecpri_seq_id *seq_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id) + for (i = 0; i < MBUFS_CNT; i++) { - struct xran_device_ctx * pctx = xran_dev_get_ctx(); - struct xran_common_counters *pCnt = &pctx->fh_counters; - - if(pctx->fh_init.io_cfg.id == O_DU) { - if(xran_check_upul_seqid(NULL, CC_ID, Ant_ID, slot_id, seq_id->seq_id) != XRAN_STATUS_SUCCESS) { - pCnt->Rx_pkt_dupl++; - return (XRAN_STATUS_FAIL); - } - }else if(pctx->fh_init.io_cfg.id == O_RU) { - if(xran_check_updl_seqid(NULL, CC_ID, Ant_ID, slot_id, seq_id->seq_id) != XRAN_STATUS_SUCCESS) { - pCnt->Rx_pkt_dupl++; - return (XRAN_STATUS_FAIL); - } - }else { - print_err("incorrect dev type %d\n", pctx->fh_init.io_cfg.id); - } - - pCnt->rx_counter++; - - pCnt->Rx_on_time++; - pCnt->Total_msgs_rcvd++; - - return XRAN_STATUS_SUCCESS; + ret_data[i] == MBUF_FREE; } -int32_t xran_process_rx_sym(void *arg, - struct rte_mbuf *mbuf, - void *iq_data_start, - uint16_t size, - uint8_t CC_ID, - uint8_t Ant_ID, - uint8_t frame_id, - uint8_t subframe_id, - uint8_t slot_id, - uint8_t symb_id, - uint16_t num_prbu, - uint16_t start_prbu, - uint16_t sym_inc, - uint16_t rb, - uint16_t sect_id, - uint32_t *mb_free) + if (p_dev_ctx->fh_init.io_cfg.id == O_DU || p_dev_ctx->fh_init.io_cfg.id == O_RU) { - char *pos = NULL; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - uint32_t tti = 0; - xran_status_t status; - void *pHandle = NULL; - struct rte_mbuf *mb = NULL; - struct xran_prb_map * pRbMap = NULL; - struct xran_prb_elm * prbMapElm = NULL; - - uint16_t iq_sample_size_bits = 16; - - tti = frame_id * SLOTS_PER_SYSTEMFRAME + subframe_id * SLOTNUM_PER_SUBFRAME + slot_id; - - status = tti << 16 | symb_id; - - if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){ - pos = (char*) p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData; - pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData; - if(pRbMap){ - prbMapElm = &pRbMap->prbMap[sect_id]; - if(sect_id >= pRbMap->nPrbElm) { - print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm); - *mb_free = MBUF_FREE; - return size; - } - } else { - print_err("pRbMap==NULL\n"); - *mb_free = MBUF_FREE; - return size; - } - - pos += start_prbu * N_SC_PER_PRB*(iq_sample_size_bits/8)*2; - if(pos && iq_data_start && size){ - if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { - int idx = 0; - uint16_t *psrc = (uint16_t *)iq_data_start; - uint16_t *pdst = (uint16_t *)pos; - rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb); - /* network byte (be) order of IQ to CPU byte order (le) */ - for (idx = 0; idx < size/sizeof(int16_t); idx++){ - pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); - } - } else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){ - if (pRbMap->nPrbElm == 1){ - if (likely (p_xran_dev_ctx->fh_init.mtu >= - p_xran_dev_ctx->fh_cfg.nULRBs * N_SC_PER_PRB*(iq_sample_size_bits/8)*2)) + if (p_dev_ctx->xran2phy_mem_ready != 0) + ret = process_mbuf_batch(pkt_data, (void*)p_dev_ctx, MBUFS_CNT, p_cid, ret_data ); + for (i = 0; i < MBUFS_CNT; i++) { - /* no fragmentation */ - mb = p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl; - if(mb){ - rte_pktmbuf_free(mb); - }else{ - print_err("mb==NULL\n"); - } - p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData = iq_data_start; - p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl = mbuf; - *mb_free = MBUF_KEEP; - } else { - /* packet can be fragmented copy RBs */ - rte_memcpy(pos, iq_data_start, size); - *mb_free = MBUF_FREE; - } - } else { - prbMapElm = &pRbMap->prbMap[sect_id]; - struct xran_section_desc *p_sec_desc = prbMapElm->p_sec_desc[symb_id]; - if(p_sec_desc){ - mb = p_sec_desc->pCtrl; - if(mb){ - rte_pktmbuf_free(mb); - } - p_sec_desc->pData = iq_data_start; - p_sec_desc->pCtrl = mbuf; - p_sec_desc->iq_buffer_len = size; - p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf); - } else { - print_err("p_sec_desc==NULL\n"); - *mb_free = MBUF_FREE; - return size; - } - *mb_free = MBUF_KEEP; + if (ret_data[i] == MBUF_FREE) + rte_pktmbuf_free(pkt_data[i]); } } - } else { - print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); - } - } else { - print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); - } - - return size; -} - -/* Send burst of packets on an output interface */ -static inline int -xran_send_burst(struct xran_device_ctx *dev, uint16_t n, uint16_t port) -{ - struct xran_common_counters * pCnt = NULL; - struct rte_mbuf **m_table; - struct rte_mbuf *m; - int32_t i = 0; - int j; - int32_t ret = 0; - - - if(dev) - pCnt = &dev->fh_counters; else - rte_panic("incorrect dev\n"); - - m_table = (struct rte_mbuf **)dev->tx_mbufs[port].m_table; - - for(i = 0; i < n; i++){ - rte_mbuf_sanity_check(m_table[i], 0); - /*rte_pktmbuf_dump(stdout, m_table[i], 256);*/ - pCnt->tx_counter++; - pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(m_table[i]); - ret += dev->send_upmbuf2ring(m_table[i], ETHER_TYPE_ECPRI, port); - } - - if (unlikely(ret < n)) { - print_err("ret < n\n"); - } - - return 0; -} - -int32_t xran_process_tx_sym_cp_off(uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, - int32_t do_srs) -{ - int32_t retval = 0; - - void *pHandle = NULL; - char *pos = NULL; - char *p_sec_iq = NULL; - //char *p_sect_iq = NULL; - void *mb = NULL; - void *send_mb = NULL; - int prb_num = 0; - uint16_t iq_sample_size_bits = 16; // TODO: make dynamic per - - struct xran_prb_map *prb_map = NULL; - uint8_t num_ant_elm = 0; - - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters; - struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig); - struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg); - num_ant_elm = xran_get_num_ant_elm(pHandle); - enum xran_pkt_dir direction; - - struct rte_mbuf *eth_oran_hdr = NULL; - char *ext_buff = NULL; - uint16_t ext_buff_len = 0; - struct rte_mbuf *tmp = NULL; - rte_iova_t ext_buff_iova = 0; - - struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id]; - - if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { - direction = XRAN_DIR_DL; /* O-DU */ - prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; - } else { - direction = XRAN_DIR_UL; /* RU */ - prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; - } - - if(xran_fs_get_slot_type(cc_id, tti, ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SLOT_TYPE_DL : XRAN_SLOT_TYPE_UL)) == 1 - || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_SP) == 1 - || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_FDD) == 1){ - - if(xran_fs_get_symbol_type(cc_id, tti, sym_id) == ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SYMBOL_TYPE_DL : XRAN_SYMBOL_TYPE_UL) - || xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD){ - - pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - mb = (void*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; - prb_map = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData; - - - if(prb_map){ - int32_t elmIdx = 0; - for (elmIdx = 0; elmIdx < prb_map->nPrbElm; elmIdx++){ - uint16_t sec_id = elmIdx; - struct xran_prb_elm * prb_map_elm = &prb_map->prbMap[elmIdx]; - struct xran_section_desc * p_sec_desc = NULL; - - if(prb_map_elm == NULL){ - rte_panic("p_sec_desc == NULL\n"); - } - - p_sec_desc = prb_map_elm->p_sec_desc[sym_id]; - -#if 1 - p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset); - - /* calculete offset for external buffer */ - ext_buff_len = p_sec_desc->iq_buffer_len; - ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM + - sizeof (struct xran_ecpri_hdr) + - sizeof (struct radio_app_common_hdr) + - sizeof(struct data_section_hdr)); - - ext_buff_len += RTE_PKTMBUF_HEADROOM + - sizeof (struct xran_ecpri_hdr) + - sizeof (struct radio_app_common_hdr) + - sizeof(struct data_section_hdr) + 18; - - if(prb_map_elm->compMethod != XRAN_COMPMETHOD_NONE){ - ext_buff -= sizeof (struct data_section_compression_hdr); - ext_buff_len += sizeof (struct data_section_compression_hdr); - } - - eth_oran_hdr = rte_pktmbuf_alloc(_eth_mbuf_pool_small); - - if (unlikely (( eth_oran_hdr) == NULL)) { - rte_panic("Failed rte_pktmbuf_alloc\n"); - } - - p_share_data->free_cb = extbuf_free_callback; - p_share_data->fcb_opaque = NULL; - rte_mbuf_ext_refcnt_set(p_share_data, 1); - - ext_buff_iova = rte_mempool_virt2iova(mb); - if (unlikely (( ext_buff_iova) == 0)) { - rte_panic("Failed rte_mem_virt2iova \n"); - } - - if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { - rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); - } - - rte_pktmbuf_attach_extbuf(eth_oran_hdr, - ext_buff, - ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb), - ext_buff_len, - p_share_data); - - rte_pktmbuf_reset_headroom(eth_oran_hdr); - - tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr)); - if (unlikely (( tmp) == NULL)) { - rte_panic("Failed rte_pktmbuf_prepend \n"); - } - send_mb = eth_oran_hdr; - - - uint8_t seq_id = (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_id); - - - - /* first all PRBs */ - int32_t num_bytes = prepare_symbol_ex(direction, sec_id, - send_mb, - (struct rb_map *)p_sec_iq, - prb_map_elm->compMethod, - prb_map_elm->iqWidth, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - prb_map_elm->nRBStart, prb_map_elm->nRBSize, - cc_id, ant_id, - seq_id, - 0); - - rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0); - pCnt->tx_counter++; - pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb); - p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, xran_map_ecpriPcid_to_vf(direction, cc_id, ant_id)); -#else - p_sect_iq = pos + p_sec_desc->iq_buffer_offset; - prb_num = prb_map_elm->nRBSize; - - if( prb_num > 136 || prb_num == 0) { - /* first 136 PRBs */ - rte_panic("first 136 PRBs\n"); - send_symbol_ex(direction, - sec_id, - NULL, - (struct rb_map *)p_sect_iq, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - 0, 136, - cc_id, ant_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_id)); - - pos += 136 * N_SC_PER_PRB * (iq_sample_size_bits/8)*2; - /* last 137 PRBs */ - send_symbol_ex(direction, sec_id, - NULL, - (struct rb_map *)p_sect_iq, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - 136, 137, - cc_id, ant_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_id)); - retval = 1; - } else { - send_symbol_ex(direction, - sec_id, /* xran_alloc_sectionid(pHandle, direction, cc_id, ant_id, slot_id)*/ - /*(struct rte_mbuf *)mb*/ NULL, - (struct rb_map *)p_sect_iq, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - prb_map_elm->nRBStart, prb_map_elm->nRBSize, - cc_id, ant_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_id)); - retval = 1; - } - -#endif - - } - } else { - printf("(%d %d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_id, sym_id); - } - - if(p_xran_dev_ctx->enablePrach - && (p_xran_dev_ctx->fh_init.io_cfg.id == O_RU)) { /* Only RU needs to send PRACH I/Q */ - uint32_t is_prach_slot = xran_is_prach_slot(subframe_id, slot_id); - if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0]) - && (is_prach_slot == 1) - && (sym_id >= p_xran_dev_ctx->prach_start_symbol[cc_id]) - && (sym_id <= p_xran_dev_ctx->prach_last_symbol[cc_id])) { //is prach slot - int prach_port_id = ant_id + pPrachCPConfig->eAxC_offset; - pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pData; - pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]) * pPrachCPConfig->numPrbc * N_SC_PER_PRB * 4; - mb = NULL;//(void*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pCtrl; - - send_symbol_ex(direction, - xran_alloc_sectionid(pHandle, direction, cc_id, prach_port_id, slot_id), - (struct rte_mbuf *)mb, - (struct rb_map *)pos, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - pPrachCPConfig->startPrbc, pPrachCPConfig->numPrbc, - cc_id, prach_port_id, - xran_get_upul_seqid(pHandle, cc_id, prach_port_id)); - retval = 1; - } /* if((frame_id % pPrachCPConfig->x == pPrachCPConfig->y[0]) .... */ - } /* if(p_xran_dev_ctx->enablePrach ..... */ - - - if(p_xran_dev_ctx->enableSrs && (p_xran_dev_ctx->fh_init.io_cfg.id == O_RU)){ - if( p_srs_cfg->symbMask & (1 << sym_id) /* is SRS symbol */ - && do_srs) { - int32_t ant_elm_id = 0; - - for (ant_elm_id = 0; ant_elm_id < num_ant_elm; ant_elm_id++){ - int32_t ant_elm_eAxC_id = ant_elm_id + p_srs_cfg->eAxC_offset; - - pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_elm_id].sBufferList.pBuffers[sym_id].pData; - mb = (void*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_elm_id].sBufferList.pBuffers[sym_id].pCtrl; - - if( prb_num > 136 || prb_num == 0) { - uint16_t sec_id = xran_alloc_sectionid(pHandle, direction, cc_id, ant_elm_id, slot_id); - /* first 136 PRBs */ - send_symbol_ex(direction, - sec_id, - NULL, - (struct rb_map *)pos, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - 0, 136, - cc_id, ant_elm_eAxC_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_elm_eAxC_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_elm_eAxC_id)); - - pos += 136 * N_SC_PER_PRB * (iq_sample_size_bits/8)*2; - /* last 137 PRBs */ - send_symbol_ex(direction, sec_id, - NULL, - (struct rb_map *)pos, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - 136, 137, - cc_id, ant_elm_eAxC_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_elm_eAxC_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_elm_eAxC_id)); - } else { - send_symbol_ex(direction, - xran_alloc_sectionid(pHandle, direction, cc_id, ant_elm_eAxC_id, slot_id), - (struct rte_mbuf *)mb, - (struct rb_map *)pos, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - 0, prb_num, - cc_id, ant_elm_eAxC_id, - (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? - xran_get_updl_seqid(pHandle, cc_id, ant_elm_eAxC_id) : - xran_get_upul_seqid(pHandle, cc_id, ant_elm_eAxC_id)); - retval = 1; - } - } /* for ant elem */ - } /* SRS symbol */ - } /* SRS enabled */ - } /* RU mode or C-Plane is not used */ - } - - return retval; -} - -struct rte_mbuf * -xran_attach_cp_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, - struct rte_mbuf_ext_shared_info * p_share_data) -{ - struct rte_mbuf *mb_oran_hdr_ext = NULL; - struct rte_mbuf *tmp = NULL; - int8_t *ext_buff = NULL; - rte_iova_t ext_buff_iova = 0; - - ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_section1_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_buff_len += (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_section1_header) + - sizeof(struct xran_cp_radioapp_section1)) + 18; - - mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small); - - if (unlikely (( mb_oran_hdr_ext) == NULL)) { - rte_panic("Failed rte_pktmbuf_alloc\n"); - } - - p_share_data->free_cb = extbuf_free_callback; - p_share_data->fcb_opaque = NULL; - rte_mbuf_ext_refcnt_set(p_share_data, 1); - - ext_buff_iova = rte_malloc_virt2iova(p_ext_buff_start); - if (unlikely (( ext_buff_iova) == 0)) { - rte_panic("Failed rte_mem_virt2iova \n"); - } - - if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { - rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); - } - - rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext, - ext_buff, - ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start), - ext_buff_len, - p_share_data); - - rte_pktmbuf_reset_headroom(mb_oran_hdr_ext); - - return mb_oran_hdr_ext; -} - - -struct rte_mbuf * -xran_attach_up_ext_buf(int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, - struct rte_mbuf_ext_shared_info * p_share_data, - enum xran_compression_method compMeth) { - struct rte_mbuf *mb_oran_hdr_ext = NULL; - struct rte_mbuf *tmp = NULL; - int8_t *ext_buff = NULL; - rte_iova_t ext_buff_iova = 0; - - ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct radio_app_common_hdr) + - sizeof(struct data_section_hdr)); - - ext_buff_len += RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct radio_app_common_hdr) + - sizeof(struct data_section_hdr) + 18; - - if(compMeth != XRAN_COMPMETHOD_NONE) { - ext_buff -= sizeof (struct data_section_compression_hdr); - ext_buff_len += sizeof (struct data_section_compression_hdr); - } - - mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_small); - - if (unlikely (( mb_oran_hdr_ext) == NULL)) { - rte_panic("Failed rte_pktmbuf_alloc\n"); - } - - p_share_data->free_cb = extbuf_free_callback; - p_share_data->fcb_opaque = NULL; - rte_mbuf_ext_refcnt_set(p_share_data, 1); - - ext_buff_iova = rte_mempool_virt2iova(p_ext_buff_start); - if (unlikely (( ext_buff_iova) == 0)) { - rte_panic("Failed rte_mem_virt2iova \n"); - } - - if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { - rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); - } - - rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext, - ext_buff, - ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start), - ext_buff_len, - p_share_data); - - rte_pktmbuf_reset_headroom(mb_oran_hdr_ext); - - tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(mb_oran_hdr_ext, sizeof(struct rte_ether_hdr)); - if (unlikely (( tmp) == NULL)) { - rte_panic("Failed rte_pktmbuf_prepend \n"); - } - - return mb_oran_hdr_ext; -} - -int32_t xran_process_tx_sym_cp_on(uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, - uint32_t slot_id, uint32_t sym_id) + for (i = 0; i < MBUFS_CNT; i++) { - int32_t retval = 0; - - struct rte_mbuf *eth_oran_hdr = NULL; - char *ext_buff = NULL; - uint16_t ext_buff_len = 0; - struct rte_mbuf *tmp = NULL; - rte_iova_t ext_buff_iova = 0; - void *pHandle = NULL; - char *pos = NULL; - char *p_sec_iq = NULL; - void *mb = NULL; - int prb_num = 0; - uint16_t iq_sample_size_bits = 16; // TODO: make dynamic per - uint32_t next = 0; - int32_t num_sections = 0; - - struct xran_section_info *sectinfo = NULL; - struct xran_device_ctx *p_xran_dev_ctx = xran_dev_get_ctx(); - enum xran_pkt_dir direction; - - struct rte_mbuf_ext_shared_info * p_share_data = &share_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id]; - - if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { - direction = XRAN_DIR_DL; /* O-DU */ - prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; - } else { - direction = XRAN_DIR_UL; /* RU */ - prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; - } - - next = 0; - num_sections = xran_cp_getsize_section_info(pHandle, direction, cc_id, ant_id, ctx_id); - /* iterate C-Plane configuration to generate corresponding U-Plane */ - while(next < num_sections) { - sectinfo = xran_cp_iterate_section_info(pHandle, direction, cc_id, ant_id, ctx_id, &next); - - if(sectinfo == NULL) - break; - - if(sectinfo->type != XRAN_CP_SECTIONTYPE_1) { /* only supports type 1 */ - print_err("Invalid section type in section DB - %d", sectinfo->type); - continue; - } - - /* skip, if not scheduled */ - if(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol) - continue; - - if(sectinfo->compMeth) - iq_sample_size_bits = sectinfo->iqWidth; - - print_dbg(">>> sym %2d [%d] type%d, id %d, startPrbc=%d, numPrbc=%d, numSymbol=%d\n", sym_id, next, - sectinfo->type, sectinfo->id, sectinfo->startPrbc, - sectinfo->numPrbc, sectinfo->numSymbol); - - p_xran_dev_ctx->tx_mbufs[0].len = 0; - uint16_t len = p_xran_dev_ctx->tx_mbufs[0].len; - int16_t len2 = 0; - uint16_t i = 0; - - //Added for Klocworks - if (len >= MBUF_TABLE_SIZE) - len = MBUF_TABLE_SIZE - 1; - - pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; - mb = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; - - p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset); - ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len; - - mb = xran_attach_up_ext_buf((int8_t *)mb, (int8_t *) p_sec_iq, - (uint16_t) ext_buff_len, - p_share_data, (enum xran_compression_method) sectinfo->compMeth); - /* first all PRBs */ - prepare_symbol_ex(direction, sectinfo->id, - mb, - (struct rb_map *)p_sec_iq, - sectinfo->compMeth, - sectinfo->iqWidth, - p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, - frame_id, subframe_id, slot_id, sym_id, - sectinfo->startPrbc, sectinfo->numPrbc, - cc_id, ant_id, - xran_get_updl_seqid(pHandle, cc_id, ant_id), - 0); - - /* if we don't need to do any fragmentation */ - if (likely (p_xran_dev_ctx->fh_init.mtu >= - sectinfo->numPrbc * (3*iq_sample_size_bits + 1))) { - /* no fragmentation */ - p_xran_dev_ctx->tx_mbufs[0].m_table[len] = mb; - len2 = 1; - } else { - /* fragmentation */ - uint8_t * seq_num = xran_get_updl_seqid_addr(pHandle, cc_id, ant_id); - if(seq_num) - (*seq_num)--; - else - rte_panic("pointer to seq number is NULL [CC %d Ant %d]\n", cc_id, ant_id); - - len2 = xran_app_fragment_packet(mb, - &p_xran_dev_ctx->tx_mbufs[0].m_table[len], - (uint16_t)(MBUF_TABLE_SIZE - len), - p_xran_dev_ctx->fh_init.mtu, - p_xran_dev_ctx->direct_pool, - p_xran_dev_ctx->indirect_pool, - sectinfo, - seq_num); - - /* Free input packet */ - rte_pktmbuf_free(mb); - - /* If we fail to fragment the packet */ - if (unlikely (len2 < 0)){ - print_err("len2= %d\n", len2); - return 0; - } - } - - if(len2 > 1){ - for (i = len; i < len + len2; i ++) { - struct rte_mbuf *m; - m = p_xran_dev_ctx->tx_mbufs[0].m_table[i]; - struct rte_ether_hdr *eth_hdr = (struct rte_ether_hdr *) - rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr)); - if (eth_hdr == NULL) { - rte_panic("No headroom in mbuf.\n"); - } + if (ret_data[i] == MBUF_FREE) + rte_pktmbuf_free(pkt_data[i]); } + print_err("incorrect dev type %d\n", p_dev_ctx->fh_init.io_cfg.id); } - - len += len2; - - if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM)) { - rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n"); } - - /* Transmit packets */ - xran_send_burst(p_xran_dev_ctx, (uint16_t)len, xran_map_ecpriPcid_to_vf(direction, cc_id, ant_id)); - p_xran_dev_ctx->tx_mbufs[0].len = 0; - retval = 1; - } /* while(section) */ - - return retval; -} - -int32_t xran_process_tx_sym(void *arg) + else { - int32_t retval = 0; - uint32_t tti=0; -#if XRAN_MLOG_VAR - uint32_t mlogVar[10]; - uint32_t mlogVarCnt = 0; -#endif - unsigned long t1 = MLogTick(); - - void *pHandle = NULL; - int32_t ant_id = 0; - int32_t cc_id = 0; - uint8_t num_eAxc = 0; - uint8_t num_CCPorts = 0; - uint32_t frame_id = 0; - uint32_t subframe_id = 0; - uint32_t slot_id = 0; - uint32_t sym_id = 0; - uint32_t sym_idx = 0; - - uint8_t ctx_id; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - enum xran_in_period inPeriod; - - if(p_xran_dev_ctx->xran2phy_mem_ready == 0) - return 0; - - /* O-RU: send symb after OTA time with delay (UL) */ - /* O-DU: send symb in advance of OTA time (DL) */ - sym_idx = XranOffsetSym(p_xran_dev_ctx->sym_up, xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT*SLOTNUM_PER_SUBFRAME*1000, &inPeriod); - - tti = XranGetTtiNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); - slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - - uint16_t sfnSecStart = xran_getSfnSecStart(); - if (unlikely(inPeriod == XRAN_IN_NEXT_PERIOD)) + for (i = 0; i < num_data; i++) { - // For DU - sfnSecStart = (sfnSecStart + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; + ret = process_mbuf(pkt_data[i], (void*)p_dev_ctx, p_cid); + if (ret == MBUF_FREE) + rte_pktmbuf_free(pkt_data[i]); } - else if (unlikely(inPeriod == XRAN_IN_PREV_PERIOD)) + + for (i = 0; i < num_control; i++) { - // For RU - if (sfnSecStart >= NUM_OF_FRAMES_PER_SECOND) + t1 = MLogTick(); + if (p_dev_ctx->fh_init.io_cfg.id == O_RU) { - sfnSecStart -= NUM_OF_FRAMES_PER_SECOND; + ret = process_cplane(pkt_control[i], (void*)p_dev_ctx); + p_dev_ctx->fh_counters.rx_counter++; + if (ret == MBUF_FREE) + rte_pktmbuf_free(pkt_control[i]); } else { - sfnSecStart += NUM_OF_FRAMES_PER_SFN_PERIOD - NUM_OF_FRAMES_PER_SECOND; + print_err("O-DU recevied C-Plane message!"); } + MLogTask(PID_PROCESS_CP_PKT, t1, MLogTick()); } - frame_id = XranGetFrameNum(tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - // ORAN frameId, 8 bits, [0, 255] - frame_id = (frame_id & 0xff); - - sym_id = XranGetSymNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); - ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME) % XRAN_MAX_SECTIONDB_CTX; - print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id); - -#if XRAN_MLOG_VAR - mlogVar[mlogVarCnt++] = 0xAAAAAAAA; - mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx; - mlogVar[mlogVarCnt++] = sym_idx; - mlogVar[mlogVarCnt++] = abs(p_xran_dev_ctx->sym_up); - mlogVar[mlogVarCnt++] = tti; - mlogVar[mlogVarCnt++] = frame_id; - mlogVar[mlogVarCnt++] = subframe_id; - mlogVar[mlogVarCnt++] = slot_id; - mlogVar[mlogVarCnt++] = sym_id; - MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); -#endif - - if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B) { - num_eAxc = xran_get_num_eAxcUl(pHandle); - } else { - num_eAxc = xran_get_num_eAxc(pHandle); + for (i = 0; i < num_meas; i++) + { + t1 = MLogTick(); + ret = process_delay_meas(pkt_meas[i], (void*)p_dev_ctx, xport_id); + // printf("Got delay_meas_pkt xport_id %d p_dev_ctx %08"PRIx64"\n", xport_id,(int64_t*)p_dev_ctx) ; + if (ret == MBUF_FREE) + rte_pktmbuf_free(pkt_meas[i]); + MLogTask(PID_PROCESS_DELAY_MEAS_PKT, t1, MLogTick()); } - - num_CCPorts = xran_get_num_cc(pHandle); - /* U-Plane */ - for(ant_id = 0; ant_id < num_eAxc; ant_id++) { - for(cc_id = 0; cc_id < num_CCPorts; cc_id++) { - if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU && p_xran_dev_ctx->enableCP){ - retval = xran_process_tx_sym_cp_on(ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id); - } else { - retval = xran_process_tx_sym_cp_off(ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, (ant_id == (num_eAxc - 1))); } - } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */ - } /* for(ant_id = 0; ant_id < num_eAxc; ant_id++) */ - MLogTask(PID_PROCESS_TX_SYM, t1, MLogTick()); - return retval; + return MBUF_FREE; } -int xran_packet_and_dpdk_timer_thread(void *args) +int32_t +xran_packet_and_dpdk_timer_thread(void *args) { struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); @@ -2544,91 +1187,165 @@ int xran_packet_and_dpdk_timer_thread(void *args) return 0; } +void xran_initialize_ecpri_owd_meas_cmn( struct xran_io_cfg *ptr) +{ +// ptr->eowd_cmn.initiator_en = 0; // Initiator 1, Recipient 0 +// ptr->eowd_cmn.filterType = 0; // 0 Simple average based on number of measurements + // Set default values if the Timeout and numberOfSamples are not set + if ( ptr->eowd_cmn[ptr->id].responseTo == 0) + ptr->eowd_cmn[ptr->id].responseTo = 10E6; // 10 ms timeout expressed in ns + if ( ptr->eowd_cmn[ptr->id].numberOfSamples == 0) + ptr->eowd_cmn[ptr->id].numberOfSamples = 8; // Number of samples to be averaged +} +void xran_initialize_ecpri_owd_meas_per_port (int i, struct xran_io_cfg *ptr ) +{ + /* This function initializes one_way delay measurements on a per port basis, + most variables default to zero */ + ptr->eowd_port[ptr->id][i].portid = (uint8_t)i; +} -int32_t xran_init(int argc, char *argv[], +int32_t +xran_init(int argc, char *argv[], struct xran_fh_init *p_xran_fh_init, char *appName, void ** pXranLayerHandle) { + int32_t ret = XRAN_STATUS_SUCCESS; int32_t i; int32_t j; + int32_t o_xu_id = 0; - struct xran_io_cfg *p_io_cfg = (struct xran_io_cfg *)&p_xran_fh_init->io_cfg; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + struct xran_io_cfg *p_io_cfg = NULL; + struct xran_device_ctx * p_xran_dev_ctx = NULL; int32_t lcore_id = 0; char filename[64]; - int64_t offset_sec, offset_nsec; + const char *version = rte_version(); + + if (version == NULL) + rte_panic("version == NULL"); + + printf("'%s'\n", version); + + if (p_xran_fh_init->xran_ports < 1 || p_xran_fh_init->xran_ports > XRAN_PORTS_NUM) { + ret = XRAN_STATUS_INVALID_PARAM; + print_err("fh_init xran_ports= %d is wrong [%d]\n", p_xran_fh_init->xran_ports, ret); + return ret; + } + + p_io_cfg = (struct xran_io_cfg *)&p_xran_fh_init->io_cfg; + + if ((ret = xran_dev_create_ctx(p_xran_fh_init->xran_ports)) < 0) { + print_err("context allocation error [%d]\n", ret); + return ret; + } + + for(o_xu_id = 0; o_xu_id < p_xran_fh_init->xran_ports; o_xu_id++){ + p_xran_dev_ctx = xran_dev_get_ctx_by_id(o_xu_id); memset(p_xran_dev_ctx, 0, sizeof(struct xran_device_ctx)); + p_xran_dev_ctx->xran_port_id = o_xu_id; /* copy init */ p_xran_dev_ctx->fh_init = *p_xran_fh_init; - printf(" %s: MTU %d\n", __FUNCTION__, p_xran_dev_ctx->fh_init.mtu); - xran_if_current_state = XRAN_INIT; - memcpy(&(p_xran_dev_ctx->eAxc_id_cfg), &(p_xran_fh_init->eAxCId_conf), sizeof(struct xran_eaxcid_config)); - - p_xran_dev_ctx->enableCP = p_xran_fh_init->enableCP; - p_xran_dev_ctx->enablePrach = p_xran_fh_init->prachEnable; - p_xran_dev_ctx->enableSrs = p_xran_fh_init->srsEnable; - p_xran_dev_ctx->DynamicSectionEna = p_xran_fh_init->DynamicSectionEna; - /* To make sure to set default functions */ p_xran_dev_ctx->send_upmbuf2ring = NULL; p_xran_dev_ctx->send_cpmbuf2ring = NULL; + // Ecpri initialization for One Way delay measurements common variables to default values + xran_initialize_ecpri_owd_meas_cmn(&p_xran_dev_ctx->fh_init.io_cfg); + } + + /* default values if not set */ + if(p_io_cfg->nEthLinePerPort == 0) + p_io_cfg->nEthLinePerPort = 1; + + if(p_io_cfg->nEthLineSpeed == 0) + p_io_cfg->nEthLineSpeed = 25; + + /** at least 1 RX Q */ + if(p_io_cfg->num_rxq == 0) + p_io_cfg->num_rxq = 1; + + if (p_io_cfg->id == 1) { + /* 1 HW for O-RU */ + p_io_cfg->num_rxq = 1; + } + +#if (RTE_VER_YEAR < 21) /* eCPRI flow supported with DPDK 21.02 or later */ + if (p_io_cfg->num_rxq > 1){ + p_io_cfg->num_rxq = 1; + printf("%s does support eCPRI flows. Set rxq to %d\n", version, p_io_cfg->num_rxq); + } +#endif + printf("PF Eth line speed %dG\n",p_io_cfg->nEthLineSpeed); + printf("PF Eth lines per O-xU port %d\n",p_io_cfg->nEthLinePerPort); + printf("RX HW queues per O-xU Eth line %d \n",p_io_cfg->num_rxq); + + if(p_xran_fh_init->xran_ports * p_io_cfg->nEthLinePerPort *(2 - 1* p_io_cfg->one_vf_cu_plane) != p_io_cfg->num_vfs) { + print_err("Incorrect VFs configurations: For %d O-xUs with %d Ethernet ports expected number of VFs is %d. [provided %d]\n", + p_xran_fh_init->xran_ports, p_io_cfg->nEthLinePerPort, + p_xran_fh_init->xran_ports * p_io_cfg->nEthLinePerPort *(2 - 1* p_io_cfg->one_vf_cu_plane), p_io_cfg->num_vfs); + } + xran_if_current_state = XRAN_INIT; xran_register_ethertype_handler(ETHER_TYPE_ECPRI, handle_ecpri_ethertype); if (p_io_cfg->id == 0) xran_ethdi_init_dpdk_io(p_xran_fh_init->filePrefix, p_io_cfg, &lcore_id, (struct rte_ether_addr *)p_xran_fh_init->p_o_du_addr, - (struct rte_ether_addr *)p_xran_fh_init->p_o_ru_addr); + (struct rte_ether_addr *)p_xran_fh_init->p_o_ru_addr, + p_xran_dev_ctx->fh_init.mtu); else xran_ethdi_init_dpdk_io(p_xran_fh_init->filePrefix, p_io_cfg, &lcore_id, (struct rte_ether_addr *)p_xran_fh_init->p_o_ru_addr, - (struct rte_ether_addr *)p_xran_fh_init->p_o_du_addr); + (struct rte_ether_addr *)p_xran_fh_init->p_o_du_addr, + p_xran_dev_ctx->fh_init.mtu); + + for(o_xu_id = 0; o_xu_id < p_xran_fh_init->xran_ports; o_xu_id++){ + p_xran_dev_ctx = xran_dev_get_ctx_by_id(o_xu_id); - for(i = 0; i < 10; i++ ) - rte_timer_init(&tti_to_phy_timer[i]); + for(i = 0; i < MAX_TTI_TO_PHY_TIMER; i++ ) + rte_timer_init(&p_xran_dev_ctx->tti_to_phy_timer[i]); - rte_timer_init(&sym_timer); + rte_timer_init(&p_xran_dev_ctx->sym_timer); for (i = 0; i< MAX_NUM_OF_DPDK_TIMERS; i++) - rte_timer_init(&dpdk_timer[i]); + rte_timer_init(&p_xran_dev_ctx->dpdk_timer[i]); p_xran_dev_ctx->direct_pool = socket_direct_pool; p_xran_dev_ctx->indirect_pool = socket_indirect_pool; - for (i = 0; i< XRAN_MAX_SECTOR_NR; i++){ + for (j = 0; j< XRAN_NUM_OF_SYMBOL_PER_SLOT; j++){ - LIST_INIT (&p_xran_dev_ctx->sym_cb_list_head[i][j]); - } + LIST_INIT (&p_xran_dev_ctx->sym_cb_list_head[j]); } + } + for (i=0; iGPS_Alpha || p_xran_fh_init->GPS_Beta ){ - offset_sec = p_xran_fh_init->GPS_Beta / 100; //resolution of beta is 10ms - offset_nsec = (p_xran_fh_init->GPS_Beta - offset_sec * 100) * 1e7 + p_xran_fh_init->GPS_Alpha; - p_xran_dev_ctx->offset_sec = offset_sec; - p_xran_dev_ctx->offset_nsec = offset_nsec; - }else { - p_xran_dev_ctx->offset_sec = 0; - p_xran_dev_ctx->offset_nsec = 0; + + // The ecpri initialization loop needs to be done per pf and vf (Outer loop pf and inner loop vf) + for (i=0; i< p_io_cfg->num_vfs; i++) + { + /* Initialize ecpri one-way delay measurement info on a per vf port basis */ + xran_initialize_ecpri_owd_meas_per_port (i, p_io_cfg); } - return 0; + return ret; } -int32_t xran_sector_get_instances (void * pDevHandle, uint16_t nNumInstances, +int32_t +xran_sector_get_instances (uint32_t xran_port, void * pDevHandle, uint16_t nNumInstances, xran_cc_handle_t * pSectorInstanceHandles) { xran_status_t nStatus = XRAN_STATUS_FAIL; @@ -2636,6 +1353,8 @@ int32_t xran_sector_get_instances (void * pDevHandle, uint16_t nNumInstances, XranSectorHandleInfo *pCcHandle = NULL; int32_t i = 0; + pDev += xran_port; + /* Check for the Valid Parameters */ CHECK_NOT_NULL (pSectorInstanceHandles, XRAN_STATUS_INVALID_PARAM); @@ -2667,111 +1386,9 @@ int32_t xran_sector_get_instances (void * pDevHandle, uint16_t nNumInstances, return XRAN_STATUS_SUCCESS; } -int32_t xran_mm_init (void * pHandle, uint64_t nMemorySize, - uint32_t nMemorySegmentSize) -{ - /* we use mbuf from dpdk memory */ - return 0; -} - -int32_t xran_bm_init (void * pHandle, uint32_t * pPoolIndex, uint32_t nNumberOfBuffers, uint32_t nBufferSize) -{ - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; - uint32_t nAllocBufferSize; - - char pool_name[RTE_MEMPOOL_NAMESIZE]; - - snprintf(pool_name, RTE_MEMPOOL_NAMESIZE, "ru_%d_cc_%d_idx_%d", - pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex); - - nAllocBufferSize = nBufferSize + sizeof(struct rte_ether_hdr) + - sizeof (struct xran_ecpri_hdr) + - sizeof (struct radio_app_common_hdr) + - sizeof(struct data_section_hdr) + 256; - - if(nAllocBufferSize >= UINT16_MAX) { - rte_panic("nAllocBufferSize is failed [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d nAllocBufferSize %d\n", - pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, nAllocBufferSize); - return -1; - } - - printf("%s: [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d\n", pool_name, - pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize); - - pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] = rte_pktmbuf_pool_create(pool_name, nNumberOfBuffers, - MBUF_CACHE, 0, nAllocBufferSize, rte_socket_id()); - - if(pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] == NULL){ - rte_panic("rte_pktmbuf_pool_create failed [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d errno %s\n", - pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, rte_strerror(rte_errno)); - return -1; - } - - pXranCc->bufferPoolElmSz[pXranCc->nBufferPoolIndex] = nBufferSize; - pXranCc->bufferPoolNumElm[pXranCc->nBufferPoolIndex] = nNumberOfBuffers; - - printf("CC:[ handle %p ru %d cc_idx %d ] [nPoolIndex %d] mb pool %p \n", - pXranCc, pXranCc->nXranPort, pXranCc->nIndex, - pXranCc->nBufferPoolIndex, pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex]); - - *pPoolIndex = pXranCc->nBufferPoolIndex++; - - return 0; -} - -int32_t xran_bm_allocate_buffer(void * pHandle, uint32_t nPoolIndex, void **ppData, void **ppCtrl) -{ - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; - *ppData = NULL; - *ppCtrl = NULL; - - struct rte_mbuf * mb = rte_pktmbuf_alloc(pXranCc->p_bufferPool[nPoolIndex]); - - if(mb){ - char * start = rte_pktmbuf_append(mb, pXranCc->bufferPoolElmSz[nPoolIndex]); - char * ethhdr = rte_pktmbuf_prepend(mb, sizeof(struct rte_ether_hdr)); - - if(start && ethhdr){ - char * iq_offset = rte_pktmbuf_mtod(mb, char * ); - /* skip headers */ - iq_offset = iq_offset + sizeof(struct rte_ether_hdr) + - sizeof (struct xran_ecpri_hdr) + - sizeof (struct radio_app_common_hdr) + - sizeof(struct data_section_hdr); - - if (0) /* if compression */ - iq_offset += sizeof (struct data_section_compression_hdr); - - *ppData = (void *)iq_offset; - *ppCtrl = (void *)mb; - } else { - print_err("[nPoolIndex %d] start ethhdr failed \n", nPoolIndex ); - return -1; - } - } else { - print_err("[nPoolIndex %d] mb alloc failed \n", nPoolIndex ); - return -1; - } - - if (*ppData == NULL){ - print_err("[nPoolIndex %d] rte_pktmbuf_append for %d failed \n", nPoolIndex, pXranCc->bufferPoolElmSz[nPoolIndex]); - return -1; - } - - return 0; -} - -int32_t xran_bm_free_buffer(void * pHandle, void *pData, void *pCtrl) -{ - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; - - if(pCtrl) - rte_pktmbuf_free(pCtrl); - return 0; -} - -int32_t xran_5g_fronthault_config (void * pHandle, +int32_t +xran_5g_fronthault_config (void * pHandle, struct xran_buffer_list *pSrcBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pSrcCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], @@ -2779,28 +1396,25 @@ int32_t xran_5g_fronthault_config (void * pHandle, xran_transport_callback_fn pCallback, void *pCallbackTag) { - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; int j, i = 0, z, k; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - - print_dbg("%s\n",__FUNCTION__); + XranSectorHandleInfo* pXranCc = NULL; + struct xran_device_ctx * p_xran_dev_ctx = NULL; - if(NULL == pHandle) - { + if(NULL == pHandle) { printf("Handle is NULL!\n"); return XRAN_STATUS_FAIL; } - if (pCallback == NULL) - { - printf ("no callback\n"); + pXranCc = (XranSectorHandleInfo*) pHandle; + p_xran_dev_ctx = xran_dev_get_ctx_by_id(pXranCc->nXranPort); + if (p_xran_dev_ctx == NULL) { + printf ("p_xran_dev_ctx is NULL\n"); return XRAN_STATUS_FAIL; } i = pXranCc->nIndex; - for(j=0; jsFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList = *pSrcBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pSrcBuffer[z][j])); + /* C-plane TX */ p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; @@ -2824,7 +1441,8 @@ int32_t xran_5g_fronthault_config (void * pHandle, if(pSrcCpBuffer[z][j]) p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pSrcCpBuffer[z][j]; - + else + memset(&p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pSrcCpBuffer[z][j])); /* U-plane RX */ p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0; @@ -2836,6 +1454,9 @@ int32_t xran_5g_fronthault_config (void * pHandle, if(pDstBuffer[z][j]) p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstBuffer[z][j])); + /* C-plane RX */ p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; @@ -2847,42 +1468,48 @@ int32_t xran_5g_fronthault_config (void * pHandle, if(pDstCpBuffer[z][j]) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pDstCpBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstCpBuffer[z][j])); + } } - p_xran_dev_ctx->pCallback[i] = pCallback; p_xran_dev_ctx->pCallbackTag[i] = pCallbackTag; + print_dbg("%s: [p %d CC %d] Cb %p cb %p\n",__FUNCTION__, + p_xran_dev_ctx->xran_port_id, i, p_xran_dev_ctx->pCallback[i], p_xran_dev_ctx->pCallbackTag[i]); p_xran_dev_ctx->xran2phy_mem_ready = 1; return XRAN_STATUS_SUCCESS; } -int32_t xran_5g_prach_req (void * pHandle, +int32_t +xran_5g_prach_req (void * pHandle, struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], + struct xran_buffer_list *pDstBufferDecomp[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag) { - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; int j, i = 0, z; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + XranSectorHandleInfo* pXranCc = NULL; + struct xran_device_ctx * p_xran_dev_ctx = NULL; - if(NULL == pHandle) - { + if(NULL == pHandle) { printf("Handle is NULL!\n"); return XRAN_STATUS_FAIL; } - if (pCallback == NULL) - { - printf ("no callback\n"); + + pXranCc = (XranSectorHandleInfo*) pHandle; + p_xran_dev_ctx = xran_dev_get_ctx_by_id(pXranCc->nXranPort); + if (p_xran_dev_ctx == NULL) { + printf ("p_xran_dev_ctx is NULL\n"); return XRAN_STATUS_FAIL; } i = pXranCc->nIndex; - for(j=0; jsFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0; p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; @@ -2892,178 +1519,1398 @@ int32_t xran_5g_prach_req (void * pHandle, p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHPrachRxBuffers[j][i][z][0]; if(pDstBuffer[z][j]) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstBuffer[z][j])); + + p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHPrachRxBuffersDecomp[j][i][z][0]; + if(pDstBufferDecomp[z][j]) + p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList = *pDstBufferDecomp[z][j]; + + } + } + + p_xran_dev_ctx->pPrachCallback[i] = pCallback; + p_xran_dev_ctx->pPrachCallbackTag[i] = pCallbackTag; + + print_dbg("%s: [p %d CC %d] Cb %p cb %p\n",__FUNCTION__, + p_xran_dev_ctx->xran_port_id, i, p_xran_dev_ctx->pPrachCallback[i], p_xran_dev_ctx->pPrachCallbackTag[i]); + + return XRAN_STATUS_SUCCESS; +} + +int32_t +xran_5g_srs_req (void * pHandle, + struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN], + struct xran_buffer_list *pDstCpBuffer[XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN], + xran_transport_callback_fn pCallback, + void *pCallbackTag) +{ + int j, i = 0, z; + XranSectorHandleInfo* pXranCc = NULL; + struct xran_device_ctx * p_xran_dev_ctx = NULL; + + if(NULL == pHandle) { + printf("Handle is NULL!\n"); + return XRAN_STATUS_FAIL; + } + + pXranCc = (XranSectorHandleInfo*) pHandle; + p_xran_dev_ctx = xran_dev_get_ctx_by_id(pXranCc->nXranPort); + if (p_xran_dev_ctx == NULL) { + printf ("p_xran_dev_ctx is NULL\n"); + return XRAN_STATUS_FAIL; + } + + i = pXranCc->nIndex; + + for(j=0; jsFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0; + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; // ant number. + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHSrsRxBuffers[j][i][z][0]; + if(pDstBuffer[z][j]) + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstBuffer[z][j])); + + /* C-plane SRS */ + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHSrsRxPrbMapBuffers[j][i][z]; + + if(pDstCpBuffer[z][j]) + p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList = *pDstCpBuffer[z][j]; + else + memset(&p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList, 0, sizeof(*pDstCpBuffer[z][j])); + + } + } + + p_xran_dev_ctx->pSrsCallback[i] = pCallback; + p_xran_dev_ctx->pSrsCallbackTag[i] = pCallbackTag; + + print_dbg("%s: [p %d CC %d] Cb %p cb %p\n",__FUNCTION__, + p_xran_dev_ctx->xran_port_id, i, p_xran_dev_ctx->pSrsCallback[i], p_xran_dev_ctx->pSrsCallbackTag[i]); + + return XRAN_STATUS_SUCCESS; +} + +uint32_t +xran_get_time_stats(uint64_t *total_time, uint64_t *used_time, uint32_t *num_core_used, uint32_t *core_used, uint32_t clear) +{ + uint32_t i; + + *num_core_used = xran_num_cores_used; + for (i = 0; i < xran_num_cores_used; i++) + { + core_used[i] = xran_core_used[i]; + } + + *total_time = xran_total_tick; + *used_time = xran_used_tick; + + if (clear) + { + xran_total_tick = 0; + xran_used_tick = 0; + } + + return 0; +} + +uint8_t* +xran_add_cp_hdr_offset(uint8_t *dst) +{ + dst += (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct xran_cp_radioapp_section1_header) + + sizeof(struct xran_cp_radioapp_section1)); + + dst = RTE_PTR_ALIGN_CEIL(dst, 64); + + return dst; +} + +uint8_t* +xran_add_hdr_offset(uint8_t *dst, int16_t compMethod) +{ + dst+= (RTE_PKTMBUF_HEADROOM + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + if(compMethod != XRAN_COMPMETHOD_NONE) + dst += sizeof (struct data_section_compression_hdr); + dst = RTE_PTR_ALIGN_CEIL(dst, 64); + + return dst; +} + +int32_t +xran_pkt_gen_process_ring(struct rte_ring *r) +{ + assert(r); + int32_t retval = 0; + struct rte_mbuf *mbufs[16]; + int i; + uint32_t remaining; + uint64_t t1; + struct xran_io_cfg *p_io_cfg = &(xran_ethdi_get_ctx()->io_cfg); + const uint16_t dequeued = rte_ring_dequeue_burst(r, (void **)mbufs, + RTE_DIM(mbufs), &remaining); + + if (!dequeued) + return 0; + + t1 = MLogTick(); + for (i = 0; i < dequeued; ++i) { + struct cp_up_tx_desc * p_tx_desc = (struct cp_up_tx_desc *)rte_pktmbuf_mtod(mbufs[i], struct cp_up_tx_desc *); + retval = xran_process_tx_sym_cp_on_opt(p_tx_desc->pHandle, + p_tx_desc->ctx_id, + p_tx_desc->tti, + p_tx_desc->cc_id, + p_tx_desc->ant_id, + p_tx_desc->frame_id, + p_tx_desc->subframe_id, + p_tx_desc->slot_id, + p_tx_desc->sym_id, + (enum xran_comp_hdr_type)p_tx_desc->compType, + (enum xran_pkt_dir) p_tx_desc->direction, + p_tx_desc->xran_port_id, + (PSECTION_DB_TYPE)p_tx_desc->p_sec_db); + + xran_pkt_gen_desc_free(p_tx_desc); + if (XRAN_STOPPED == xran_if_current_state){ + MLogTask(PID_PROCESS_TX_SYM, t1, MLogTick()); + return -1; + } + } + + if(p_io_cfg->io_sleep) + nanosleep(&sleeptime,NULL); + + MLogTask(PID_PROCESS_TX_SYM, t1, MLogTick()); + + return remaining; +} + +int32_t +xran_dl_pkt_ring_processing_func(void* args) +{ + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + uint16_t xran_port_mask = (uint16_t)((uint64_t)args & 0xFFFF); + uint16_t current_port; + + rte_timer_manage(); + + for (current_port = 0; current_port < XRAN_PORTS_NUM; current_port++) { + if( xran_port_mask & (1<up_dl_pkt_gen_ring[current_port]); + } + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + + return 0; +} + +/** Function to peforms serves of DPDK times */ +int32_t +xran_processing_timer_only_func(void* args) +{ + rte_timer_manage(); + if (XRAN_STOPPED == xran_if_current_state) + return -1; + + return 0; +} + +/** Function to peforms parsing of RX packets on all ports and does TX and RX on ETH device */ +int32_t +xran_all_tasks(void* arg) +{ + + ring_processing_func(arg); + process_dpdk_io(arg); + return 0; +} + +/** Function to pefromrm TX and RX on ETH device */ +int32_t +xran_eth_trx_tasks(void* arg) +{ + process_dpdk_io(arg); + return 0; +} + +/** Function to pefromrm RX on ETH device */ +int32_t +xran_eth_rx_tasks(void* arg) +{ + process_dpdk_io_rx(arg); + return 0; +} + +/** Function to porcess ORAN FH packet per port */ +int32_t +ring_processing_func_per_port(void* args) +{ + struct xran_ethdi_ctx *const ctx = xran_ethdi_get_ctx(); + int16_t retPoll = 0; + int32_t i; + uint64_t t1, t2; + uint16_t port_id = (uint16_t)((uint64_t)args & 0xFFFF); + queueid_t qi; + + for (i = 0; i < ctx->io_cfg.num_vfs && i < XRAN_VF_MAX; i = i+1) { + if (ctx->vf2xran_port[i] == port_id) { + for(qi = 0; qi < ctx->rxq_per_port[port_id]; qi++){ + if (process_ring(ctx->rx_ring[i][qi], i, qi)) + return 0; + } + } + } + + if (XRAN_STOPPED == xran_if_current_state) + return -1; + + return 0; +} + +/** Fucntion generate configuration of worker threads and creates them base on sceanrio and used platform */ +int32_t +xran_spawn_workers(void) +{ + uint64_t nWorkerCore = 1LL; + uint32_t coreNum = sysconf(_SC_NPROCESSORS_CONF); + int32_t i = 0; + uint32_t total_num_cores = 1; /*start with timing core */ + uint32_t worker_num_cores = 0; + uint32_t icx_cpu = 0; + int32_t core_map[2*sizeof(uint64_t)*8]; + uint32_t xran_port_mask = 0; + + struct xran_ethdi_ctx *eth_ctx = xran_ethdi_get_ctx(); + struct xran_device_ctx *p_dev = NULL; + struct xran_fh_init *fh_init = NULL; + struct xran_fh_config *fh_cfg = NULL; + struct xran_worker_th_ctx* pThCtx = NULL; + + p_dev = xran_dev_get_ctx_by_id(0); + if(p_dev == NULL) { + print_err("p_dev\n"); + return XRAN_STATUS_FAIL; + } + + fh_init = &p_dev->fh_init; + if(fh_init == NULL) { + print_err("fh_init\n"); + return XRAN_STATUS_FAIL; + } + + fh_cfg = &p_dev->fh_cfg; + if(fh_cfg == NULL) { + print_err("fh_cfg\n"); + return XRAN_STATUS_FAIL; + } + + for (i = 0; i < coreNum && i < 64; i++) { + if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core) { + core_map[worker_num_cores++] = i; + total_num_cores++; + } + nWorkerCore = nWorkerCore << 1; + } + + nWorkerCore = 1LL; + for (i = 64; i < coreNum && i < 128; i++) { + if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core_64_127) { + core_map[worker_num_cores++] = i; + total_num_cores++; + } + nWorkerCore = nWorkerCore << 1; + } + + extern int _may_i_use_cpu_feature(unsigned __int64); + icx_cpu = _may_i_use_cpu_feature(_FEATURE_AVX512IFMA52); + + printf("O-XU %d\n", eth_ctx->io_cfg.id); + printf("HW %d\n", icx_cpu); + printf("Num cores %d\n", total_num_cores); + printf("Num ports %d\n", fh_init->xran_ports); + printf("O-RU Cat %d\n", fh_cfg->ru_conf.xranCat); + printf("O-RU CC %d\n", fh_cfg->nCC); + printf("O-RU eAxC %d\n", fh_cfg->neAxc); + + for (i = 0; i < fh_init->xran_ports; i++){ + xran_port_mask |= 1<xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL){ + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = 1; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = 1; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + + if(fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_A) { + switch(total_num_cores) { + case 1: /** only timing core */ + eth_ctx->time_wrk_cfg.f = xran_all_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + break; + case 2: + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[0].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[0].arg = pThCtx; + break; + case 3: + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 0; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)xran_port_mask; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + break; + default: + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + } else if (fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_B && fh_init->xran_ports == 1) { + switch(total_num_cores) { + case 1: /** only timing core */ + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + break; + case 2: + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + p_dev->tx_sym_gen_func = xran_process_tx_sym_cp_on_opt; + + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[0].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[0].arg = pThCtx; + break; + case 3: + if(icx_cpu) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 0; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)xran_port_mask; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + case 4: + if(icx_cpu) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 1; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + case 5: + if(icx_cpu) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_rx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 1; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + case 6: + if(eth_ctx->io_cfg.id == O_DU) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_rx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 Eth Tx **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_tx", core_map[pThCtx->worker_id]); + pThCtx->task_func = process_dpdk_io_tx; + pThCtx->task_arg = (void*)2; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(((1<<1) | (1<<2) |(1<<0)) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 4 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 4; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 0; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = 0; //pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = 0; //pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + } else if(eth_ctx->io_cfg.id == O_RU) { + /*** O_RU specific config */ + /* timing core */ + eth_ctx->time_wrk_cfg.f = NULL; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 Eth RX */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_rx", core_map[pThCtx->worker_id]); + pThCtx->task_func = process_dpdk_io_rx; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p0", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)0; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p1", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)1; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p2", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)2; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** FH TX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 4; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_tx", core_map[pThCtx->worker_id]); + pThCtx->task_func = process_dpdk_io_tx; + pThCtx->task_arg = (void*)2; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + default: + print_err("unsupported configuration\n"); + return XRAN_STATUS_FAIL; + } + } else if (fh_cfg->ru_conf.xranCat == XRAN_CATEGORY_B && fh_init->xran_ports > 1) { + switch(total_num_cores) { + case 1: + case 2: + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + break; + case 3: + if(icx_cpu) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 1; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)xran_port_mask; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + case 4: + if(icx_cpu) { + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(((1<<1) | (1<<2)) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)((1<<0) & xran_port_mask); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + for (i = 1; i < fh_init->xran_ports; i++) { + struct xran_device_ctx * p_dev_update = xran_dev_get_ctx_by_id(i); + if(p_dev_update == NULL) { + print_err("p_dev_update\n"); + return XRAN_STATUS_FAIL; + } + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL] = pThCtx->worker_id; + p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL] = pThCtx->worker_id; + printf("p:%d XRAN_JOB_TYPE_CP_DL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_DL]); + printf("p:%d XRAN_JOB_TYPE_CP_UL worker id %d\n", i, p_dev_update->job2wrk_id[XRAN_JOB_TYPE_CP_UL]); + } + } else { + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; + } + break; + case 5: + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<0); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_up_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<1); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_up_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<2); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + break; + case 6: + if(eth_ctx->io_cfg.id == O_DU){ + /* timing core */ + eth_ctx->time_wrk_cfg.f = xran_eth_trx_tasks; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_bbdev", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 - CP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_cp_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_processing_timer_only_func; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<0); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<1); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 4 UP GEN **/ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 4; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_tx_gen", core_map[pThCtx->worker_id]); + pThCtx->task_func = xran_dl_pkt_ring_processing_func; + pThCtx->task_arg = (void*)(1<<2); + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + } else { + /*** O_RU specific config */ + /* timing core */ + eth_ctx->time_wrk_cfg.f = NULL; + eth_ctx->time_wrk_cfg.arg = NULL; + eth_ctx->time_wrk_cfg.state = 1; + + /* workers */ + /** 0 Eth RX */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 0; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_rx", core_map[pThCtx->worker_id]); + pThCtx->task_func = process_dpdk_io_rx; + pThCtx->task_arg = NULL; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 1 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 1; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p0", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)0; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 2 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 2; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p1", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)1; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** 3 FH RX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 3; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_rx_p2", core_map[pThCtx->worker_id]); + pThCtx->task_func = ring_processing_func_per_port; + pThCtx->task_arg = (void*)2; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + + /** FH TX and BBDEV */ + pThCtx = (struct xran_worker_th_ctx*) _mm_malloc(sizeof(struct xran_worker_th_ctx), 64); + if(pThCtx == NULL){ + print_err("pThCtx allocation error\n"); + return XRAN_STATUS_FAIL; + } + memset(pThCtx, 0, sizeof(struct xran_worker_th_ctx)); + pThCtx->worker_id = 4; + pThCtx->worker_core_id = core_map[pThCtx->worker_id]; + snprintf(pThCtx->worker_name, RTE_DIM(pThCtx->worker_name), "%s-%d", "fh_eth_tx", core_map[pThCtx->worker_id]); + pThCtx->task_func = process_dpdk_io_tx; + pThCtx->task_arg = (void*)2; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].f = xran_generic_worker_thread; + eth_ctx->pkt_wrk_cfg[pThCtx->worker_id].arg = pThCtx; + } + break; + default: + print_err("unsupported configuration Cat %d numports %d total_num_cores = %d\n", fh_cfg->ru_conf.xranCat, fh_init->xran_ports, total_num_cores); + return XRAN_STATUS_FAIL; } - } - - p_xran_dev_ctx->pPrachCallback[i] = pCallback; - p_xran_dev_ctx->pPrachCallbackTag[i] = pCallbackTag; - - return XRAN_STATUS_SUCCESS; -} - - -int32_t xran_5g_srs_req (void * pHandle, - struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN], - xran_transport_callback_fn pCallback, - void *pCallbackTag) -{ - XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; - int j, i = 0, z; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - - if(NULL == pHandle) - { - printf("Handle is NULL!\n"); - return XRAN_STATUS_FAIL; - } - if (pCallback == NULL) - { - printf ("no callback\n"); + } else { + print_err("unsupported configuration\n"); return XRAN_STATUS_FAIL; } - i = pXranCc->nIndex; - - for(j=0; jsFHSrsRxBbuIoBufCtrl[j][i][z].bValid = 0; - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_MAX_ANT_ARRAY_ELM_NR; // ant number. - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &p_xran_dev_ctx->sFHSrsRxBuffers[j][i][z][0]; - if(pDstBuffer[z][j]) - p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList = *pDstBuffer[z][j]; + nWorkerCore = 1LL; + if(eth_ctx->io_cfg.pkt_proc_core) { + for (i = 0; i < coreNum && i < 64; i++) { + if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core) { + xran_core_used[xran_num_cores_used++] = i; + if (rte_eal_remote_launch(eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f, eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].arg, i)) + rte_panic("eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f() failed to start\n"); + eth_ctx->pkt_wrk_cfg[i].state = 1; + if(eth_ctx->pkt_proc_core_id == 0) + eth_ctx->pkt_proc_core_id = i; + printf("spawn worker %d core %d\n",eth_ctx->num_workers, i); + eth_ctx->worker_core[eth_ctx->num_workers++] = i; + } + nWorkerCore = nWorkerCore << 1; + } + } + + nWorkerCore = 1LL; + if(eth_ctx->io_cfg.pkt_proc_core_64_127) { + for (i = 64; i < coreNum && i < 128; i++) { + if (nWorkerCore & (uint64_t)eth_ctx->io_cfg.pkt_proc_core_64_127) { + xran_core_used[xran_num_cores_used++] = i; + if (rte_eal_remote_launch(eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f, eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].arg, i)) + rte_panic("eth_ctx->pkt_wrk_cfg[eth_ctx->num_workers].f() failed to start\n"); + eth_ctx->pkt_wrk_cfg[i].state = 1; + if(eth_ctx->pkt_proc_core_id == 0) + eth_ctx->pkt_proc_core_id = i; + printf("spawn worker %d core %d\n",eth_ctx->num_workers, i); + eth_ctx->worker_core[eth_ctx->num_workers++] = i; + } + nWorkerCore = nWorkerCore << 1; } } - p_xran_dev_ctx->pSrsCallback[i] = pCallback; - p_xran_dev_ctx->pSrsCallbackTag[i] = pCallbackTag; - return XRAN_STATUS_SUCCESS; } - -uint32_t xran_get_time_stats(uint64_t *total_time, uint64_t *used_time, uint32_t *core_used, uint32_t clear) -{ - *total_time = xran_total_tick; - *used_time = xran_used_tick; - *core_used = xran_core_used; - - if (clear) - { - xran_total_tick = 0; - xran_used_tick = 0; - } - - return 0; -} - -void * xran_malloc(size_t buf_len) -{ - return rte_malloc("External buffer", buf_len, RTE_CACHE_LINE_SIZE); -} - -void xran_free(void *addr) -{ - return rte_free(addr); -} - - -uint8_t *xran_add_cp_hdr_offset(uint8_t *dst) -{ - dst += (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_section1_header) + - sizeof(struct xran_cp_radioapp_section1)); - - dst = RTE_PTR_ALIGN_CEIL(dst, 64); - - return dst; -} - -uint8_t *xran_add_hdr_offset(uint8_t *dst, int16_t compMethod) -{ - dst+= (RTE_PKTMBUF_HEADROOM + - sizeof (struct xran_ecpri_hdr) + - sizeof (struct radio_app_common_hdr) + - sizeof(struct data_section_hdr)); - - if(compMethod != XRAN_COMPMETHOD_NONE) - dst += sizeof (struct data_section_compression_hdr); - - dst = RTE_PTR_ALIGN_CEIL(dst, 64); - - return dst; -} - -int32_t xran_open(void *pHandle, struct xran_fh_config* pConf) +int32_t +xran_open(void *pHandle, struct xran_fh_config* pConf) { + int32_t ret = XRAN_STATUS_SUCCESS; int32_t i; uint8_t nNumerology = 0; int32_t lcore_id = 0; - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - struct xran_fh_config *pFhCfg; - pFhCfg = &(p_xran_dev_ctx->fh_cfg); + struct xran_device_ctx *p_xran_dev_ctx = NULL; + struct xran_fh_config *pFhCfg = NULL; + struct xran_fh_init *fh_init = NULL; + struct xran_ethdi_ctx *eth_ctx = xran_ethdi_get_ctx(); + int32_t wait_time = 10; + int64_t offset_sec, offset_nsec; + + if(pConf->dpdk_port < XRAN_PORTS_NUM) { + p_xran_dev_ctx = xran_dev_get_ctx_by_id(pConf->dpdk_port); + } else { + print_err("@0x%08p [ru %d ] pConf->dpdk_port > XRAN_PORTS_NUM\n", pConf, pConf->dpdk_port); + return XRAN_STATUS_FAIL; + } + + if(p_xran_dev_ctx == NULL) { + print_err("[ru %d] p_xran_dev_ctx == NULL ", pConf->dpdk_port); + return XRAN_STATUS_FAIL; + } + pFhCfg = &p_xran_dev_ctx->fh_cfg; memcpy(pFhCfg, pConf, sizeof(struct xran_fh_config)); - if(pConf->log_level) + fh_init = &p_xran_dev_ctx->fh_init; + if(fh_init == NULL) + return XRAN_STATUS_FAIL; + + if(pConf->log_level) { printf(" %s: %s Category %s\n", __FUNCTION__, (pFhCfg->ru_conf.xranTech == XRAN_RAN_5GNR) ? "5G NR" : "LTE", (pFhCfg->ru_conf.xranCat == XRAN_CATEGORY_A) ? "A" : "B"); + } - nNumerology = xran_get_conf_numerology(pHandle); + p_xran_dev_ctx->enableCP = pConf->enableCP; + p_xran_dev_ctx->enablePrach = pConf->prachEnable; + p_xran_dev_ctx->enableSrs = pConf->srsEnable; + p_xran_dev_ctx->puschMaskEnable = pConf->puschMaskEnable; + p_xran_dev_ctx->puschMaskSlot = pConf->puschMaskSlot; + p_xran_dev_ctx->DynamicSectionEna = pConf->DynamicSectionEna; - if (pConf->nCC > XRAN_MAX_SECTOR_NR) - { + if(pConf->GPS_Alpha || pConf->GPS_Beta ){ + offset_sec = pConf->GPS_Beta / 100; /* resolution of beta is 10ms */ + offset_nsec = (pConf->GPS_Beta - offset_sec * 100) * 1e7 + pConf->GPS_Alpha; + p_xran_dev_ctx->offset_sec = offset_sec; + p_xran_dev_ctx->offset_nsec = offset_nsec; + }else { + p_xran_dev_ctx->offset_sec = 0; + p_xran_dev_ctx->offset_nsec = 0; + } + + + nNumerology = xran_get_conf_numerology(p_xran_dev_ctx); + + if (pConf->nCC > XRAN_MAX_SECTOR_NR) { if(pConf->log_level) printf("Number of cells %d exceeds max number supported %d!\n", pConf->nCC, XRAN_MAX_SECTOR_NR); pConf->nCC = XRAN_MAX_SECTOR_NR; - } - if(pConf->ru_conf.iqOrder != XRAN_I_Q_ORDER - || pConf->ru_conf.byteOrder != XRAN_NE_BE_BYTE_ORDER ){ + if(pConf->ru_conf.iqOrder != XRAN_I_Q_ORDER || pConf->ru_conf.byteOrder != XRAN_NE_BE_BYTE_ORDER ) { print_err("Byte order and/or IQ order is not supported [IQ %d byte %d]\n", pConf->ru_conf.iqOrder, pConf->ru_conf.byteOrder); return XRAN_STATUS_FAIL; } + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU) { + if((ret = xran_ruemul_init(p_xran_dev_ctx)) < 0) { + return ret; + } + } + /* setup PRACH configuration for C-Plane */ - if(pConf->ru_conf.xranTech == XRAN_RAN_5GNR) - xran_init_prach(pConf, p_xran_dev_ctx); - else if (pConf->ru_conf.xranTech == XRAN_RAN_LTE) - xran_init_prach_lte(pConf, p_xran_dev_ctx); + if(pConf->ru_conf.xranTech == XRAN_RAN_5GNR) { + if((ret = xran_init_prach(pConf, p_xran_dev_ctx))< 0){ + return ret; + } + } else if (pConf->ru_conf.xranTech == XRAN_RAN_LTE) { + if((ret = xran_init_prach_lte(pConf, p_xran_dev_ctx))< 0){ + return ret; + } + } + + if((ret = xran_init_srs(pConf, p_xran_dev_ctx))< 0){ + return ret; + } + + if((ret = xran_cp_init_sectiondb(p_xran_dev_ctx)) < 0){ + return ret; + } + + if((ret = xran_init_sectionid(p_xran_dev_ctx)) < 0){ + return ret; + } - xran_init_srs(pConf, p_xran_dev_ctx); + if((ret = xran_init_seqid(p_xran_dev_ctx)) < 0){ + return ret; + } + + if((uint16_t)eth_ctx->io_cfg.port[XRAN_UP_VF] != 0xFFFF){ + if((ret = xran_init_vfs_mapping(p_xran_dev_ctx)) < 0) { + return ret; + } - xran_cp_init_sectiondb(pHandle); - xran_init_sectionid(pHandle); - xran_init_seqid(pHandle); + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU && p_xran_dev_ctx->fh_init.io_cfg.num_rxq > 1) { + if((ret = xran_init_vf_rxq_to_pcid_mapping(p_xran_dev_ctx)) < 0) { + return ret; + } + } + } if(pConf->ru_conf.xran_max_frame) { xran_max_frame = pConf->ru_conf.xran_max_frame; printf("xran_max_frame %d\n", xran_max_frame); } - interval_us = xran_fs_get_tti_interval(nNumerology); - - if(pConf->log_level){ - printf("%s: interval_us=%ld\n", __FUNCTION__, interval_us); + p_xran_dev_ctx->interval_us_local = xran_fs_get_tti_interval(nNumerology); + if (interval_us > p_xran_dev_ctx->interval_us_local) + { + interval_us = xran_fs_get_tti_interval(nNumerology); //only update interval_us based on maximum numerology } + +// if(pConf->log_level){ + printf("%s: interval_us=%ld, interval_us_local=%d\n", __FUNCTION__, interval_us, p_xran_dev_ctx->interval_us_local); +// } + if (nNumerology >= timing_get_numerology()) + { timing_set_numerology(nNumerology); + } for(i = 0 ; i nCC; i++){ - xran_fs_set_slot_type(i, pConf->frame_conf.nFrameDuplexType, pConf->frame_conf.nTddPeriod, + xran_fs_set_slot_type(pConf->dpdk_port, i, pConf->frame_conf.nFrameDuplexType, pConf->frame_conf.nTddPeriod, pConf->frame_conf.sSlotConfig); } - xran_fs_slot_limit_init(xran_fs_get_tti_interval(nNumerology)); - - if(xran_ethdi_get_ctx()->io_cfg.bbdev_mode != XRAN_BBDEV_NOT_USED){ - p_xran_dev_ctx->bbdev_dec = pConf->bbdev_dec; - p_xran_dev_ctx->bbdev_enc = pConf->bbdev_enc; - } + xran_fs_slot_limit_init(pConf->dpdk_port, xran_fs_get_tti_interval(nNumerology)); /* if send_xpmbuf2ring needs to be changed from default functions, * then those should be set between xran_init and xran_open */ @@ -3072,61 +2919,90 @@ int32_t xran_open(void *pHandle, struct xran_fh_config* pConf) if(p_xran_dev_ctx->send_upmbuf2ring == NULL) p_xran_dev_ctx->send_upmbuf2ring = xran_ethdi_mbuf_send; - /* Start packet processing thread */ - if((uint16_t)xran_ethdi_get_ctx()->io_cfg.port[XRAN_UP_VF] != 0xFFFF && - (uint16_t)xran_ethdi_get_ctx()->io_cfg.port[XRAN_CP_VF] != 0xFFFF ){ - if(/*pConf->log_level*/1){ - printf("XRAN_UP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_UP_VF]); - printf("XRAN_CP_VF: 0x%04x\n", xran_ethdi_get_ctx()->io_cfg.port[XRAN_CP_VF]); - } + if(pFhCfg->ru_conf.xranCat == XRAN_CATEGORY_A) { + if(p_xran_dev_ctx->tx_sym_gen_func == NULL ) + p_xran_dev_ctx->tx_sym_gen_func = xran_process_tx_sym_cp_on_opt; + } else { + if(p_xran_dev_ctx->tx_sym_gen_func == NULL ) + p_xran_dev_ctx->tx_sym_gen_func = xran_process_tx_sym_cp_on_dispatch_opt; + } + if(pConf->dpdk_port == 0) { + /* create all thread on open of port 0 */ + xran_num_cores_used = 0; + if(eth_ctx->io_cfg.bbdev_mode != XRAN_BBDEV_NOT_USED){ + eth_ctx->bbdev_dec = pConf->bbdev_dec; + eth_ctx->bbdev_enc = pConf->bbdev_enc; + } - if (rte_eal_remote_launch(xran_timing_source_thread, xran_dev_get_ctx(), xran_ethdi_get_ctx()->io_cfg.timing_core)) + if((uint16_t)eth_ctx->io_cfg.port[XRAN_UP_VF] != 0xFFFF){ + printf("XRAN_UP_VF: 0x%04x\n", eth_ctx->io_cfg.port[XRAN_UP_VF]); + p_xran_dev_ctx->timing_source_thread_running = 0; + xran_core_used[xran_num_cores_used++] = eth_ctx->io_cfg.timing_core; + if (rte_eal_remote_launch(xran_timing_source_thread, xran_dev_get_ctx(), eth_ctx->io_cfg.timing_core)) rte_panic("thread_run() failed to start\n"); + } else if(pConf->log_level) { + printf("Eth port was not open. Processing thread was not started\n"); + } + } else { + if((uint16_t)eth_ctx->io_cfg.port[XRAN_UP_VF] != 0xFFFF) { + if ((ret = xran_timing_create_cbs(p_xran_dev_ctx)) < 0) { + return ret; + } + } + } - /* Start packet processing thread */ - if(xran_ethdi_get_ctx()->io_cfg.pkt_proc_core){ - /* start pkt workers */ - uint64_t nWorkerCore = 1LL; - uint32_t coreNum = sysconf(_SC_NPROCESSORS_CONF); - for (i = 0; i < coreNum; i++) { - if (nWorkerCore & (uint64_t)xran_ethdi_get_ctx()->io_cfg.pkt_proc_core) { - if (rte_eal_remote_launch(ring_processing_thread, NULL, i)) - rte_panic("ring_processing_thread() failed to start\n"); - xran_ethdi_get_ctx()->pkt_wrk_cfg[i].f = ring_processing_thread; - xran_ethdi_get_ctx()->pkt_wrk_cfg[i].arg = NULL; - xran_ethdi_get_ctx()->pkt_wrk_cfg[i].state = 1; - if(p_xran_dev_ctx->pkt_proc_core_id == 0) - p_xran_dev_ctx->pkt_proc_core_id = i; + if((uint16_t)eth_ctx->io_cfg.port[XRAN_UP_VF] != 0xFFFF){ + if(pConf->dpdk_port == (fh_init->xran_ports - 1)) { + if((ret = xran_spawn_workers()) < 0) { + return ret; } - nWorkerCore = nWorkerCore << 1; } + printf("%s [CPU %2d] [PID: %6d]\n", __FUNCTION__, sched_getcpu(), getpid()); + printf("Waiting on Timing thread...\n"); + while (p_xran_dev_ctx->timing_source_thread_running == 0 && wait_time--) { + usleep(100); } - } else if(pConf->log_level){ - printf("Eth port was not open. Processing thread was not started\n"); } - return 0; + print_dbg("%s : %d", __FUNCTION__, pConf->dpdk_port); + return ret; } -int32_t xran_start(void *pHandle) +int32_t +xran_start(void *pHandle) { + struct tm * ptm; + /* ToS = Top of Second start +- 1.5us */ + struct timespec ts; + char buff[100]; + struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); if(xran_get_if_state() == XRAN_RUNNING) { print_err("Already STARTED!!"); return (-1); } - - if(p_xran_dev_ctx->fh_init.debugStop){ - printf("Set debug stop %d, debug stop count %d\n", p_xran_dev_ctx->fh_init.debugStop, p_xran_dev_ctx->fh_init.debugStopCount); - timing_set_debug_stop(p_xran_dev_ctx->fh_init.debugStop, p_xran_dev_ctx->fh_init.debugStopCount); + timespec_get(&ts, TIME_UTC); + ptm = gmtime(&ts.tv_sec); + if(ptm){ + strftime(buff, sizeof(buff), "%D %T", ptm); + printf("%s: XRAN start time: %s.%09ld UTC [%ld]\n", + (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU ? "O-DU": "O-RU"), buff, ts.tv_nsec, interval_us); } + if (p_xran_dev_ctx->fh_init.io_cfg.eowd_cmn[p_xran_dev_ctx->fh_init.io_cfg.id].owdm_enable) + { + xran_if_current_state = XRAN_OWDM; + } + else + { xran_if_current_state = XRAN_RUNNING; + } return 0; } -int32_t xran_stop(void *pHandle) +int32_t +xran_stop(void *pHandle) { if(xran_get_if_state() == XRAN_STOPPED) { print_err("Already STOPPED!!"); @@ -3137,62 +3013,29 @@ int32_t xran_stop(void *pHandle) return 0; } -int32_t xran_close(void *pHandle) +int32_t +xran_close(void *pHandle) { + int32_t ret = XRAN_STATUS_SUCCESS; + struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); + xran_if_current_state = XRAN_STOPPED; - //TODO: fix memory leak xran_cp_free_sectiondb(pHandle); - //rte_eal_mp_wait_lcore(); - //xran_ethdi_ports_stats(); + ret = xran_cp_free_sectiondb(p_xran_dev_ctx); + + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU) + xran_ruemul_release(p_xran_dev_ctx); #ifdef RTE_LIBRTE_PDUMP /* uninitialize packet capture framework */ rte_pdump_uninit(); #endif - return 0; -} - -int32_t xran_mm_destroy (void * pHandle) -{ - if(xran_get_if_state() == XRAN_RUNNING) { - print_err("Please STOP first !!"); - return (-1); - } - - /* functionality is not yet implemented */ - return -1; -} - -int32_t xran_reg_sym_cb(void *pHandle, xran_callback_sym_fn symCb, void * symCbParam, uint8_t symb, uint8_t ant) -{ - if(xran_get_if_state() == XRAN_RUNNING) { - print_err("Cannot register callback while running!!\n"); - return (-1); - } - - /* functionality is not yet implemented */ - print_err("Functionality is not yet implemented !"); - return -1; -} - -int32_t xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id id) -{ - struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); - - if(xran_get_if_state() == XRAN_RUNNING) { - print_err("Cannot register callback while running!!\n"); - return (-1); - } - - p_xran_dev_ctx->ttiCb[id] = Cb; - p_xran_dev_ctx->TtiCbParam[id] = cbParam; - p_xran_dev_ctx->SkipTti[id] = skipTtiNum; - - return 0; + return ret; } /* send_cpmbuf2ring and send_upmbuf2ring should be set between xran_init and xran_open * each cb will be set by default duing open if it is set by NULL */ -int xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_mbuf_send_fn mbuf_send_up) +int32_t +xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_mbuf_send_fn mbuf_send_up) { struct xran_device_ctx *p_xran_dev_ctx; @@ -3206,157 +3049,33 @@ int xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_ p_xran_dev_ctx->send_cpmbuf2ring = mbuf_send_cp; p_xran_dev_ctx->send_upmbuf2ring = mbuf_send_up; + p_xran_dev_ctx->tx_sym_gen_func = xran_process_tx_sym_cp_on_opt; + return (0); } - -int32_t xran_get_slot_idx (uint32_t *nFrameIdx, uint32_t *nSubframeIdx, uint32_t *nSlotIdx, uint64_t *nSecond) +int32_t +xran_get_slot_idx (uint32_t PortId, uint32_t *nFrameIdx, uint32_t *nSubframeIdx, uint32_t *nSlotIdx, uint64_t *nSecond) { int32_t tti = 0; - - tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); - *nSlotIdx = (uint32_t)XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME); - *nSubframeIdx = (uint32_t)XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME, SUBFRAMES_PER_SYSTEMFRAME); - *nFrameIdx = (uint32_t)XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME); - *nSecond = timing_get_current_second(); - - return tti; -} - - -/** - * @brief Get the configuration of eAxC ID - * - * @return the pointer of configuration - */ -inline struct xran_eaxcid_config *xran_get_conf_eAxC(void *pHandle) -{ - return (&(xran_dev_get_ctx()->eAxc_id_cfg)); -} - -/** - * @brief Get the configuration of the total number of beamforming weights on RU - * - * @return Configured the number of beamforming weights - */ -inline uint8_t xran_get_conf_num_bfweights(void *pHandle) -{ - return (xran_dev_get_ctx()->fh_init.totalBfWeights); -} - -/** - * @brief Get the configuration of subcarrier spacing for PRACH - * - * @return subcarrier spacing value for PRACH - */ -inline uint8_t xran_get_conf_prach_scs(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->prach_conf.nPrachSubcSpacing); -} - -/** - * @brief Get the configuration of FFT size for RU - * - * @return FFT size value for RU - */ -inline uint8_t xran_get_conf_fftsize(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->ru_conf.fftSize); -} - -/** - * @brief Get the configuration of nummerology - * - * @return Configured numerology - */ -inline uint8_t xran_get_conf_numerology(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->frame_conf.nNumerology); -} - -/** - * @brief Get the configuration of IQ bit width for RU - * - * @return IQ bit width for RU - */ -inline uint8_t xran_get_conf_iqwidth(void *pHandle) -{ - struct xran_fh_config *pFhCfg; - - pFhCfg = xran_lib_get_ctx_fhcfg(); - return ((pFhCfg->ru_conf.iqWidth==16)?0:pFhCfg->ru_conf.iqWidth); -} - -/** - * @brief Get the configuration of compression method for RU - * - * @return Compression method for RU - */ -inline uint8_t xran_get_conf_compmethod(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->ru_conf.compMeth); -} - - -/** - * @brief Get the configuration of the number of component carriers - * - * @return Configured the number of component carriers - */ -inline uint8_t xran_get_num_cc(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->nCC); -} - -/** - * @brief Get the configuration of the number of antenna for UL - * - * @return Configured the number of antenna - */ -inline uint8_t xran_get_num_eAxc(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->neAxc); -} - -/** - * @brief Get configuration of O-RU (Cat A or Cat B) - * - * @return Configured the number of antenna - */ -inline enum xran_category xran_get_ru_category(void *pHandle) + struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx_by_id(PortId); + if (!p_xran_dev_ctx) { - return (xran_lib_get_ctx_fhcfg()->ru_conf.xranCat); + print_err("Null xRAN context on port id %u!!\n", PortId); + return 0; } -/** - * @brief Get the configuration of the number of antenna - * - * @return Configured the number of antenna - */ -inline uint8_t xran_get_num_eAxcUl(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->neAxcUl); -} + tti = (int32_t)XranGetTtiNum(xran_lib_ota_sym_idx[PortId], XRAN_NUM_OF_SYMBOL_PER_SLOT); + *nSlotIdx = (uint32_t)XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local)); + *nSubframeIdx = (uint32_t)XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local), SUBFRAMES_PER_SYSTEMFRAME); + *nFrameIdx = (uint32_t)XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(p_xran_dev_ctx->interval_us_local)); + *nSecond = timing_get_current_second(); -/** - * @brief Get the configuration of the number of antenna elements - * - * @return Configured the number of antenna - */ -inline uint8_t xran_get_num_ant_elm(void *pHandle) -{ - return (xran_lib_get_ctx_fhcfg()->nAntElmTRx); + return tti; } -int32_t xran_get_common_counters(void *pXranLayerHandle, struct xran_common_counters *pStats) +int32_t +xran_set_debug_stop(int32_t value, int32_t count) { - struct xran_device_ctx* pDev = (struct xran_device_ctx*)pXranLayerHandle; - - if(pStats && pDev) { - *pStats = pDev->fh_counters; - return XRAN_STATUS_SUCCESS; - } else { - return XRAN_STATUS_INVALID_PARAM; + return timing_set_debug_stop(value, count); } -} - diff --git a/fhi_lib/lib/src/xran_main.h b/fhi_lib/lib/src/xran_main.h new file mode 100644 index 0000000..b20c1e5 --- /dev/null +++ b/fhi_lib/lib/src/xran_main.h @@ -0,0 +1,65 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN main module header file + * @file xran_main.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_MAIN_H_ +#define _XRAN_MAIN_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include + +#include "xran_dev.h" + +extern uint32_t xran_lib_ota_tti[]; +extern uint32_t xran_lib_ota_sym[]; +extern uint32_t xran_lib_ota_sym_idx[]; + +extern uint16_t xran_SFN_at_Sec_Start; +extern uint16_t xran_max_frame; + +static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */ + +uint32_t xran_schedule_to_worker(enum xran_job_type_id job_type_id, struct xran_device_ctx * p_xran_dev_ctx); +uint16_t xran_getSfnSecStart(void); +void tx_cp_dl_cb(struct rte_timer *tim, void *arg); +void tx_cp_ul_cb(struct rte_timer *tim, void *arg); +void tti_to_phy_cb(struct rte_timer *tim, void *arg); + +void rx_ul_deadline_full_cb(struct rte_timer *tim, void *arg); +void rx_ul_user_sym_cb(struct rte_timer *tim, void *arg); +void rx_ul_deadline_half_cb(struct rte_timer *tim, void *arg); + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_MAIN_H_ */ diff --git a/fhi_lib/lib/src/xran_mem_mgr.c b/fhi_lib/lib/src/xran_mem_mgr.c new file mode 100644 index 0000000..3e401e6 --- /dev/null +++ b/fhi_lib/lib/src/xran_mem_mgr.c @@ -0,0 +1,185 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN memory management + * @file xran_mem_mgr.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ethernet.h" +#include "xran_mem_mgr.h" +#include "xran_dev.h" +#include "xran_printf.h" + +int32_t +xran_mm_init (void * pHandle, uint64_t nMemorySize, + uint32_t nMemorySegmentSize) +{ + /* we use mbuf from dpdk memory */ + return 0; +} + +int32_t +xran_bm_init (void * pHandle, uint32_t * pPoolIndex, uint32_t nNumberOfBuffers, uint32_t nBufferSize) +{ + XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; + uint32_t nAllocBufferSize; + + char pool_name[RTE_MEMPOOL_NAMESIZE]; + + snprintf(pool_name, RTE_MEMPOOL_NAMESIZE, "ru_%d_cc_%d_idx_%d", + pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex); + + nAllocBufferSize = nBufferSize + sizeof(struct rte_ether_hdr) + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + 256; + + if(nAllocBufferSize >= UINT16_MAX) { + rte_panic("nAllocBufferSize is failed [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d nAllocBufferSize %d\n", + pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, nAllocBufferSize); + return -1; + } + + printf("%s: [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d\n", pool_name, + pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize); + + pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] = rte_pktmbuf_pool_create(pool_name, nNumberOfBuffers, + MBUF_CACHE, 0, nAllocBufferSize, rte_socket_id()); + + if(pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex] == NULL){ + rte_panic("rte_pktmbuf_pool_create failed [ handle %p %d %d ] [nPoolIndex %d] nNumberOfBuffers %d nBufferSize %d errno %s\n", + pXranCc, pXranCc->nXranPort, pXranCc->nIndex, pXranCc->nBufferPoolIndex, nNumberOfBuffers, nBufferSize, rte_strerror(rte_errno)); + return -1; + } + + pXranCc->bufferPoolElmSz[pXranCc->nBufferPoolIndex] = nBufferSize; + pXranCc->bufferPoolNumElm[pXranCc->nBufferPoolIndex] = nNumberOfBuffers; + + printf("CC:[ handle %p ru %d cc_idx %d ] [nPoolIndex %d] mb pool %p \n", + pXranCc, pXranCc->nXranPort, pXranCc->nIndex, + pXranCc->nBufferPoolIndex, pXranCc->p_bufferPool[pXranCc->nBufferPoolIndex]); + + *pPoolIndex = pXranCc->nBufferPoolIndex++; + + return 0; +} + +int32_t +xran_bm_allocate_buffer(void * pHandle, uint32_t nPoolIndex, void **ppData, void **ppCtrl) +{ + XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; + *ppData = NULL; + *ppCtrl = NULL; + + struct rte_mbuf * mb = rte_pktmbuf_alloc(pXranCc->p_bufferPool[nPoolIndex]); + + if(mb){ + char * start = rte_pktmbuf_append(mb, pXranCc->bufferPoolElmSz[nPoolIndex]); + char * ethhdr = rte_pktmbuf_prepend(mb, sizeof(struct rte_ether_hdr)); + + if(start && ethhdr){ + char * iq_offset = rte_pktmbuf_mtod(mb, char * ); + /* skip headers */ + iq_offset = iq_offset + sizeof(struct rte_ether_hdr) + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr); + + if (0) /* if compression */ + iq_offset += sizeof (struct data_section_compression_hdr); + + *ppData = (void *)iq_offset; + *ppCtrl = (void *)mb; + } else { + print_err("[nPoolIndex %d] start ethhdr failed \n", nPoolIndex ); + return -1; + } + } else { + print_err("[nPoolIndex %d] mb alloc failed \n", nPoolIndex ); + return -1; + } + + if (*ppData == NULL){ + print_err("[nPoolIndex %d] rte_pktmbuf_append for %d failed \n", nPoolIndex, pXranCc->bufferPoolElmSz[nPoolIndex]); + return -1; + } + + return 0; +} + +int32_t +xran_bm_free_buffer(void * pHandle, void *pData, void *pCtrl) +{ + XranSectorHandleInfo* pXranCc = (XranSectorHandleInfo*) pHandle; + + if(pCtrl) + rte_pktmbuf_free(pCtrl); + + return 0; +} + +void* +xran_malloc(size_t buf_len) +{ + return rte_malloc("External buffer", buf_len, RTE_CACHE_LINE_SIZE); +} + +void +xran_free(void *addr) +{ + return rte_free(addr); +} + +int32_t +xran_mm_destroy (void * pHandle) +{ + if(xran_get_if_state() == XRAN_RUNNING) { + print_err("Please STOP first !!"); + return (-1); + } + + /* functionality is not yet implemented */ + return 0; +} diff --git a/fhi_lib/lib/src/xran_mem_mgr.h b/fhi_lib/lib/src/xran_mem_mgr.h new file mode 100644 index 0000000..95ef89a --- /dev/null +++ b/fhi_lib/lib/src/xran_mem_mgr.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN memory management module header file + * @file xran_mem_mgr.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_MEM_MGR_H_ +#define _XRAN_MEM_MGR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include + +#include "xran_fh_o_du.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_MEM_MGR_H_ */ + diff --git a/fhi_lib/lib/src/xran_mod_compression.cpp b/fhi_lib/lib/src/xran_mod_compression.cpp new file mode 100644 index 0000000..7d4a5d0 --- /dev/null +++ b/fhi_lib/lib/src/xran_mod_compression.cpp @@ -0,0 +1,941 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ +#include +#include +#include "xran_mod_compression.h" + +#ifdef C_Module_Used +void +mod_compression_qpsk_c(int16_t *pData,int8_t *pOut,int16_t unit, int32_t nSc) +{ + for (int32_t iSc = 0 ; iSc=0 ? 0 :1; + int8_t bit_q = pData[iSc*2+1] >=0 ? 0 :1; + *pOut |= bit_i<<(7-(bit_pos*2))|bit_q<<(6-(bit_pos*2)); + if (3 == bit_pos) + pOut++; + } +} + +void +mod_compression_16qam_c(int16_t *pData,int8_t *pOut,int16_t unit, int32_t nSc) +{ + int16_t bit_unit = unit>>1; + for (int32_t iSc = 0 ; iSc>2; + for (int32_t iSc = 0 ; iSc>1; + pOut++; + *pOut |= bit_i<<7|bit_q<<4; + } + else if (2 == bit_pos) + { + *pOut |= bit_i<<1|bit_q>>2; + pOut++; + *pOut |= bit_q<<6; + } + else if (3 == bit_pos) + { + *pOut |= bit_i<<3|bit_q; + pOut++; + } + } +} + +void +mod_compression_256qam_c(int16_t *pData,int8_t *pOut,int16_t unit,int32_t nSc) +{ + int16_t bit_unit = unit>>3; + for (int32_t iSc = 0 ; iSc>2)+1);idx++) + { + *pOut = *(((int8_t *)&bits)+idx); + pOut++; + } + } +} + +inline __m512i +byte_pack2b(const __m512i comp_data) +{ + const __m512i k_shift_left = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006); + const auto comp_data_packed = _mm512_sllv_epi16(comp_data, k_shift_left); + + const __m512i k_byte_shufflemask1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800); + constexpr uint64_t k_bytemask1 = 0x0003000300030003; + const auto comp_data_shuff1 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask1); + + const __m512i k_byte_shufflemask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02); + const auto comp_data_shuff2 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask2); + + const __m512i k_byte_shufflemask3 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04); + const auto comp_data_shuff3 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask3); + + const __m512i k_byte_shufflemask4 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06); + const auto comp_data_shuff4 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask4); + + /// Ternary blend of the two shuffled results + const __m512i k_ternlog_select1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030); + + const __m512i k_ternlog_select2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C); + + const __m512i k_ternlog_select3 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303); + + auto comp_data_packed2 = _mm512_ternarylogic_epi64(comp_data_shuff1, comp_data_shuff2, k_ternlog_select1, 0xd8); + auto comp_data_packed3 = _mm512_ternarylogic_epi64(comp_data_packed2, comp_data_shuff3, k_ternlog_select2, 0xd8); + return _mm512_ternarylogic_epi64(comp_data_packed3, comp_data_shuff4, k_ternlog_select3, 0xd8); +} + +inline __m512i +byte_pack2b_snc(const __m512i comp_data) +{ + const __m512i k_shift_left = _mm512_set_epi64(0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006, + 0x0000000200040006, 0x0000000200040006); + const auto comp_data_packed = _mm512_sllv_epi16(comp_data, k_shift_left); + + const __m512i k_byte_shufflemask1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800, + 0x0000000000000000, 0x0000000000000800); + constexpr uint64_t k_bytemask1 = 0x0003000300030003; + const auto comp_data_shuff1 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask1); + + const __m512i k_byte_shufflemask2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02, + 0x0000000000000000, 0x0000000000000A02); + const auto comp_data_shuff2 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask2); + + const __m512i k_byte_shufflemask3 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04, + 0x0000000000000000, 0x0000000000000C04); + const auto comp_data_shuff3 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask3); + + const __m512i k_byte_shufflemask4 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06, + 0x0000000000000000, 0x0000000000000E06); + const auto comp_data_shuff4 = _mm512_maskz_shuffle_epi8(k_bytemask1, comp_data_packed, k_byte_shufflemask4); + + /// Ternary blend of the two shuffled results + const __m512i k_ternlog_select1 = _mm512_set_epi64(0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030, + 0x0000000000000000, 0x0000000000003030); + + const __m512i k_ternlog_select2 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C, + 0x0000000000000000, 0x0000000000000C0C); + + const __m512i k_ternlog_select3 = _mm512_set_epi64(0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303, + 0x0000000000000000, 0x0000000000000303); + + auto comp_data_packed2 = _mm512_ternarylogic_epi64(comp_data_shuff1, comp_data_shuff2, k_ternlog_select1, 0xd8); + auto comp_data_packed3 = _mm512_ternarylogic_epi64(comp_data_packed2, comp_data_shuff3, k_ternlog_select2, 0xd8); + auto comp_data_packed4 = _mm512_ternarylogic_epi64(comp_data_packed3, comp_data_shuff4, k_ternlog_select3, 0xd8); + const auto k_byte_permute = + _mm512_setr_epi32( + 0x11100100, 0x31302120, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); + + return _mm512_permutexvar_epi8(k_byte_permute,comp_data_packed4); +} + +void mod_compression_16qam_avx512(int16_t *pData, int8_t *pOut, int16_t unit, int32_t nSc) +{ + int16_t bit_unit = unit>>1; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert,byte_pack; + __mmask32 mask32 ; + __mmask16 mask_store = 0x3; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(3); + for (int32_t iSc = 0 ; iSc>2)&0x1)<<1); + _mm_mask_storeu_epi8(pOut , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 0)); + left_mask = ((k1>>4)&0x1)|(((k1>>6)&0x1)<<1); + _mm_mask_storeu_epi8(pOut+2 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 1)); + left_mask = ((k1>>8)&0x1)|(((k1>>10)&0x1)<<1); + _mm_mask_storeu_epi8(pOut+4 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 2)); + left_mask = ((k1>>12)&0x1)|(((k1>>14)&0x1)<<1); + _mm_mask_storeu_epi8(pOut+6 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 3)); + } +} + +void mod_compression_16qam_snc(int16_t *pData, int8_t *pOut, int16_t unit, int32_t nSc) +{ + int16_t bit_unit = unit>>1; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert,byte_pack; + __mmask32 mask32 ; + __mmask16 mask_store = 0x3; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(3); + for (int32_t iSc = 0 ; iSc>1; + left_mask = ((__mmask16)1<>2; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert,byte_pack; + __mmask32 mask32 ; + __mmask16 mask_store = 0x7; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(7); + for (int32_t iSc = 0 ; iSc>4)&mask_store; + _mm_mask_storeu_epi8(pOut+3 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 1)); + left_mask = (k1>>8)&mask_store; + _mm_mask_storeu_epi8(pOut+6 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 2)); + left_mask = (k1>>12)&mask_store; + _mm_mask_storeu_epi8(pOut+9 , left_mask ,_mm512_extracti64x2_epi64(byte_pack, 3)); + } +} + +void mod_compression_64qam_snc(int16_t *pData, int8_t *pOut, int16_t unit, int32_t nSc) +{ + int16_t bit_unit = unit>>2; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert,byte_pack; + __mmask32 mask32 ; + __mmask16 mask_store = 0x7; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(7); + for (int32_t iSc = 0 ; iSc>2; + left_mask = ((__mmask16)1<>3; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert; + __mmask32 mask32 ; + __mmask16 mask_store =0xF; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(15); + for (int32_t iSc = 0 ; iSc>3; + if (0 == bit_unit) + { + printf("modulation compression unit is too low!\n "); + bit_unit = 1; + } + __m512i symbol,symbol_unit ,bit_convert; + __mmask32 mask32 ; + __mmask16 mask_store =0xF; + int32_t nSc0,nSc1; + nSc0 = nSc&0xfffffff0; + nSc1 = nSc&0xf; + symbol_unit = _mm512_set1_epi16(bit_unit); + bit_convert = _mm512_set1_epi16(15); + for (int32_t iSc = 0 ; iScmodulation) + { + case XRAN_QPSK: + mod_compression_qpsk_avx512(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM16: + mod_compression_16qam_snc(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM64: + mod_compression_64qam_snc(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM256: + mod_compression_256qam_snc(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + default: + printf("Error invalid modulation compression request\n"); + return -1; + } + return 0; +} + +int xranlib_5gnr_mod_compression(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response){ +#ifdef C_Module_Used + return (xranlib_5gnr_mod_compression_c(request, response)); +#else + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + return (xranlib_5gnr_mod_compression_snc(request, response)); + else + return (xranlib_5gnr_mod_compression_avx512(request, response)); +#endif +} + +#ifdef C_Module_Used +int xranlib_5gnr_mod_compression_c(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response){ + + switch(request->modulation) + { + case XRAN_QPSK: + mod_compression_qpsk_c(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM16: + mod_compression_16qam_c(request->data_in, response->data_out, request->unit,request->num_symbols); + break; + case XRAN_QAM64: + mod_compression_64qam_c(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM256: + mod_compression_256qam_c(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + default: + printf("Error invalid modulation compression request\n"); + return -1; + } + return 0; +} +#endif +int xranlib_5gnr_mod_compression_avx512(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response){ + + switch(request->modulation) + { + case XRAN_QPSK: + mod_compression_qpsk_avx512(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM16: + mod_compression_16qam_avx512(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM64: + mod_compression_64qam_avx512(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM256: + mod_compression_256qam_avx512(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + default: + printf("Error invalid modulation compression request\n"); + return -1; + } + return 0; +} + +void +mod_decompression_qpsk_c(int8_t *pData,int16_t *pOut,int16_t unit, int32_t nSc ,int16_t re_mask) +{ + int16_t symbol_unit[2] = {0}; + symbol_unit[0] = (unit>>1); + symbol_unit[1] = (unit>>1)*-1; + for (int32_t iSc = 0 ; iSc> mask_pos)&0x1)) + { + uint8_t symbol_pos= iSc &0x3; + uint32_t byte_pos= iSc >>2; + uint8_t bit_i = (pData[byte_pos]>>(7-(symbol_pos*2)))&0x1; + pOut[iSc*2] = symbol_unit[bit_i]; + uint8_t bit_q = (pData[byte_pos]>>(6-(symbol_pos*2)))&0x1; + pOut[iSc*2+1] = symbol_unit[bit_q]; + } + } +} + +void +mod_decompression_16qam_c(int8_t *pData,int16_t *pOut,int16_t unit, int32_t nSc) +{ + int16_t symbol_unit[4] = {0}; + symbol_unit[0] = (unit>>2); + symbol_unit[1] = (unit>>2)*3; + symbol_unit[3] = (unit>>2)*-1; + symbol_unit[2] = (unit>>2)*-3; + for (int32_t iSc = 0 ; iSc>1; + uint8_t bit_i = (pData[byte_pos]>>(6-(symbol_pos*4)))&0x3; + pOut[iSc*2] = symbol_unit[bit_i]; + uint8_t bit_q = (pData[byte_pos]>>(4-(symbol_pos*4)))&0x3; + pOut[iSc*2+1] = symbol_unit[bit_q]; + } +} + +void +mod_decompression_64qam_c(int8_t *pData,int16_t *pOut,int16_t unit, int32_t nSc) +{ + int16_t symbol_unit[8] = {0}; + symbol_unit[0] = (unit>>3); + symbol_unit[1] = (unit>>3)*3; + symbol_unit[2] = (unit>>3)*5; + symbol_unit[3] = (unit>>3)*7; + symbol_unit[7] = (unit>>3)*-1; + symbol_unit[6] = (unit>>3)*-3; + symbol_unit[5] = (unit>>3)*-5; + symbol_unit[4] = (unit>>3)*-7; + uint8_t bit_i , bit_q ; + for (int32_t iSc = 0 ; iSc>5)&0x7; + bit_q = (pData[0]>>2)&0x7; + } + else if (1 == symbol_pos) + { + bit_i = ((pData[0]&0x3)<<1)|((pData[1]>>7)&0x1); + bit_q = (pData[1]>>4)&0x7; + } + else if (2 == symbol_pos) + { + bit_q = ((pData[1]&0x1)<<2)|((pData[2]>>6)&0x3); + bit_i = (pData[1]>>1)&0x7; + } + else if (3 == symbol_pos) + { + bit_i = (pData[2]>>3)&0x7; + bit_q = pData[2]&0x7; + pData +=3; + } + pOut[iSc*2] = symbol_unit[bit_i]; + pOut[iSc*2+1] = symbol_unit[bit_q]; + } +} + +void +mod_decompression_256qam_c(int8_t *pData,int16_t *pOut,int16_t unit,int32_t nSc) +{ + int16_t symbol_unit[16] = {0}; + symbol_unit[0] = (unit>>4); + symbol_unit[1] = (unit>>4)*3; + symbol_unit[2] = (unit>>4)*5; + symbol_unit[3] = (unit>>4)*7; + symbol_unit[4] = (unit>>4)*9; + symbol_unit[5] = (unit>>4)*11; + symbol_unit[6] = (unit>>4)*13; + symbol_unit[7] = (unit>>4)*15; + symbol_unit[15] = (unit>>4)*-1; + symbol_unit[14] = (unit>>4)*-3; + symbol_unit[13] = (unit>>4)*-5; + symbol_unit[12] = (unit>>4)*-7; + symbol_unit[11] = (unit>>4)*-9; + symbol_unit[10] = (unit>>4)*-11; + symbol_unit[9] = (unit>>4)*-13; + symbol_unit[8] = (unit>>4)*-15; + for (int32_t iSc = 0 ; iSc>4)&0xF; + uint8_t bit_q = pData[iSc]&0xF; + pOut[iSc*2] = symbol_unit[bit_i]; + pOut[iSc*2+1] = symbol_unit[bit_q]; + } +} + +int xranlib_5gnr_mod_decompression(const struct xranlib_5gnr_mod_decompression_request* request, + struct xranlib_5gnr_mod_decompression_response* response){ + + switch(request->modulation) + { + case XRAN_QPSK: + mod_decompression_qpsk_c(request->data_in, response->data_out, request->unit, request->num_symbols, request->re_mask); + break; + case XRAN_QAM16: + mod_decompression_16qam_c(request->data_in, response->data_out, request->unit,request->num_symbols); + break; + case XRAN_QAM64: + mod_decompression_64qam_c(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + case XRAN_QAM256: + mod_decompression_256qam_c(request->data_in, response->data_out, request->unit, request->num_symbols); + break; + default: + printf("Error invalid modulation compression request\n"); + return -1; + } + return 0; +} + + diff --git a/fhi_lib/lib/src/xran_mod_compression.h b/fhi_lib/lib/src/xran_mod_compression.h new file mode 100644 index 0000000..81134bb --- /dev/null +++ b/fhi_lib/lib/src/xran_mod_compression.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ +#include +#include + + +/*! + \struct bblib_llr_demapping_5gnr_mod_compression_request + \brief Structure defining modulation compression lib. +*/ + +enum xran_modulation_order { + XRAN_BPSK = 1, /*!< BPSK */ + XRAN_QPSK = 2, /*!< QPSK */ + XRAN_PAM4 = 3, /*!< PAM4 */ + XRAN_QAM16 = 4, /*!< QAM16 */ + XRAN_PAM8 = 5, /*!< PAM8 */ + XRAN_QAM64 = 6, /*!< QAM64 */ + XRAN_PAM16 = 7, /*!< PAM16 */ + XRAN_QAM256 = 8 /*!< QAM256 */ +}; + +struct xranlib_5gnr_mod_compression_request +{ + /*! Pointer to buffer of the input symbols - buffer must be 64 byte aligned. Format 16Sx. */ + int16_t * data_in; + /*! 16bit shift value used to scale the input samples. */ + int16_t unit; + /*! Supported modulation values are: 2 (QPSK), 4 (16QAM), 6 (64QAM), 8 (256QAM). */ + enum xran_modulation_order modulation; + int32_t num_symbols; /*!< Number of complex input symbols. */ + int16_t re_mask; /*!< RE mask in one RB. */ +}; + +/*! + \struct bblib_llr_demapping_5gnr_mod_compression_response + \brief Structure defining the modualtion compression output. + */ +struct xranlib_5gnr_mod_compression_response +{ + /*! Pointer to output buffer - buffer should be 64 byte aligned.bit sequence*/ + int8_t * data_out; /*!< Pointer to data after compression. */ + int32_t len_out; /*!< Length of output data in bytes. */ +}; + +struct xranlib_5gnr_mod_decompression_request +{ + /*! Pointer to buffer of the input symbols - buffer must be 64 byte aligned. Format 16Sx. */ + int8_t * data_in; + /*! 16bit shift value used to scale the input samples. */ + int16_t unit; + /*! Supported modulation values are: 2 (QPSK), 4 (16QAM), 6 (64QAM), 8 (256QAM). */ + enum xran_modulation_order modulation; + int32_t num_symbols; /*!< Number of complex input symbols. */ + int16_t re_mask; /*!< RE mask in one RB. */ +}; + +/*! + \struct bblib_llr_demapping_5gnr_mod_compression_response + \brief Structure defining the modualtion compression output. + */ +struct xranlib_5gnr_mod_decompression_response +{ + /*! Pointer to output buffer - buffer should be 64 byte aligned.bit sequence*/ + int16_t * data_out; /*!< Pointer to data after compression. */ + int32_t len_out; /*!< Length of output data in bytes. */ +}; + +//! @{ +/*! \brief modulation compression procedures. +*/ +int xranlib_5gnr_mod_compression(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response); +int xranlib_5gnr_mod_compression_avx512(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response); +int xranlib_5gnr_mod_compression_snc(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response); +int xranlib_5gnr_mod_compression_c(const struct xranlib_5gnr_mod_compression_request* request, + struct xranlib_5gnr_mod_compression_response* response); +int xranlib_5gnr_mod_decompression(const struct xranlib_5gnr_mod_decompression_request* request, + struct xranlib_5gnr_mod_decompression_response* response); + diff --git a/fhi_lib/lib/src/xran_prach_cfg.h b/fhi_lib/lib/src/xran_prach_cfg.h new file mode 100644 index 0000000..36c01c2 --- /dev/null +++ b/fhi_lib/lib/src/xran_prach_cfg.h @@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief Header file to PRACH specific config structures + * @file xran_prach_cfg.h + * @author Intel Corporation + **/ + +#ifndef _XRAN_PRACH_CFG_H_ +#define _XRAN_PRACH_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* PRACH configuration table defines */ +#define XRAN_PRACH_CANDIDATE_PREAMBLE (2) +#define XRAN_PRACH_CANDIDATE_Y (2) +#define XRAN_PRACH_CANDIDATE_SLOT (40) +#define XRAN_PRACH_CONFIG_TABLE_SIZE (256) +#define XRAN_PRACH_PREAMBLE_FORMAT_OF_ABC (9) + +typedef enum +{ + FORMAT_0 = 0, + FORMAT_1, + FORMAT_2, + FORMAT_3, + FORMAT_A1, + FORMAT_A2, + FORMAT_A3, + FORMAT_B1, + FORMAT_B2, + FORMAT_B3, + FORMAT_B4, + FORMAT_C0, + FORMAT_C2, + FORMAT_LAST +}PreambleFormatEnum; + +/* add PRACH used config table, same structure as used in refPHY */ +typedef struct +{ + uint8_t prachConfigIdx; + uint8_t preambleFmrt[XRAN_PRACH_CANDIDATE_PREAMBLE]; + uint8_t x; + uint8_t y[XRAN_PRACH_CANDIDATE_Y]; + uint8_t slotNr[XRAN_PRACH_CANDIDATE_SLOT]; + uint8_t slotNrNum; + uint8_t startingSym; + uint8_t nrofPrachInSlot; + uint8_t occassionsInPrachSlot; + uint8_t duration; +} xRANPrachConfigTableStruct; + +typedef struct +{ + uint8_t preambleFmrt; + uint16_t lRALen; + uint8_t fRA; + uint32_t nu; + uint16_t nRaCp; +}xRANPrachPreambleLRAStruct; + +struct xran_prach_cp_config +{ + uint8_t filterIdx; + uint8_t startSymId; + uint16_t startPrbc; + uint8_t numPrbc; + uint8_t numSymbol; + uint16_t timeOffset; + int32_t freqOffset; + uint8_t nrofPrachInSlot; + uint8_t occassionsInPrachSlot; + uint8_t x; + uint8_t y[XRAN_PRACH_CANDIDATE_Y]; + uint8_t isPRACHslot[XRAN_PRACH_CANDIDATE_SLOT]; + uint8_t eAxC_offset; /**< starting eAxC for PRACH stream */ +}; + +extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_fdd[XRAN_PRACH_CONFIG_TABLE_SIZE]; +extern const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_tdd[XRAN_PRACH_CONFIG_TABLE_SIZE]; +extern const xRANPrachConfigTableStruct gxranPrachDataTable_mmw[XRAN_PRACH_CONFIG_TABLE_SIZE]; +extern const xRANPrachPreambleLRAStruct gxranPreambleforLRA[13]; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/fhi_lib/lib/src/xran_printf.h b/fhi_lib/lib/src/xran_printf.h index 8649b01..e2c938b 100644 --- a/fhi_lib/lib/src/xran_printf.h +++ b/fhi_lib/lib/src/xran_printf.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,6 +29,7 @@ #ifdef __cplusplus extern "C" { #endif + #include #include @@ -39,32 +40,32 @@ extern "C" { #ifndef WIN32 #ifdef PRINTF_LOG_OK -#define print_log(fmt, args...) printf("%s:" fmt "\n", __FUNCTION__, ## args) +#define print_log(fmt, args...) printf("%s:%d" fmt "\n", __FUNCTION__, __LINE__, ## args) #else /* PRINTF_LOG_OK */ #define print_log(fmt, args...) #endif /* PRINTF_LOG_OK */ #else -#define print_log(fmt, ...) printf("%s:" fmt "\n", __FUNCTION__, __VA_ARGS__) +#define print_log(fmt, ...) printf("%s:%d" fmt "\n", __FUNCTION__, __LINE__, __VA_ARGS__) #endif #ifndef WIN32 #ifdef PRINTF_DBG_OK -#define print_dbg(fmt, args...) printf("%s:[dbg] " fmt "\n", __FUNCTION__, ## args) +#define print_dbg(fmt, args...) printf("%s:%d[dbg] " fmt "\n", __FUNCTION__, __LINE__, ## args) #else /* PRINTF_LOG_OK */ #define print_dbg(fmt, args...) #endif /* PRINTF_LOG_OK */ #else -#define print_dbg(fmt, ...) printf("%s:[dbg] " fmt "\n", __FUNCTION__, __VA_ARGS__) +#define print_dbg(fmt, ...) printf("%s:%d[dbg] " fmt "\n", __FUNCTION__, __LINE__, __VA_ARGS__) #endif #ifndef WIN32 #ifdef PRINTF_ERR_OK -#define print_err(fmt, args...) printf("%s:[err] " fmt "\n", __FUNCTION__, ## args) +#define print_err(fmt, args...) printf("%s:%d[err] " fmt "\n", __FUNCTION__, __LINE__, ## args) #else /* PRINTF_LOG_OK */ #define print_err(fmt, args...) #endif /* PRINTF_LOG_OK */ #else -#define print_err(fmt, ...) printf("%s:[err] " fmt "\n", __FUNCTION__, __VA_ARGS__) +#define print_err(fmt, ...) printf("%s:%d[err] " fmt "\n", __FUNCTION__, __LINE__, __VA_ARGS__) #endif #ifndef WIN32 diff --git a/fhi_lib/lib/src/xran_rx_proc.c b/fhi_lib/lib/src/xran_rx_proc.c new file mode 100644 index 0000000..36bd72c --- /dev/null +++ b/fhi_lib/lib/src/xran_rx_proc.c @@ -0,0 +1,454 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN RX module + * @file xran_rx.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xran_fh_o_du.h" + +#include "ethdi.h" +#include "xran_pkt.h" +#include "xran_up_api.h" +#include "xran_cp_api.h" +#include "xran_sync_api.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_timer.h" +#include "xran_common.h" +#include "xran_dev.h" +#include "xran_frame_struct.h" +#include "xran_printf.h" +#include "xran_app_frag.h" +#include "xran_rx_proc.h" +#include "xran_cp_proc.h" + +#include "xran_mlog_lnx.h" + +int xran_process_prach_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free) +{ +// char *pos = NULL; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + uint8_t symb_id_offset; + uint32_t tti = 0; + xran_status_t status; + void *pHandle = NULL; + struct rte_mbuf *mb; + uint32_t interval = p_xran_dev_ctx->interval_us_local; + + if(p_xran_dev_ctx->xran2phy_mem_ready == 0) + return 0; + + tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id; + + status = tti << 16 | symb_id; + + if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){ + symb_id_offset = symb_id - p_xran_dev_ctx->prach_start_symbol[CC_ID]; //make the storing of prach packets to start from 0 for easy of processing within PHY +// pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData; + if(iq_data_start && size) { + mb = p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl; + if(mb) + rte_pktmbuf_free(mb); + + if(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { + int idx = 0; + uint16_t *psrc = (uint16_t *)iq_data_start; + uint16_t *pdst = (uint16_t *)iq_data_start; + for (idx = 0; idx < size/sizeof(int16_t); idx++){ + pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); + } + //*mb_free = MBUF_FREE; + } + + p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pData = iq_data_start; + p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrlDecomp[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id_offset].pCtrl = mbuf; + + *mb_free = MBUF_KEEP; + } + else { + //print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); + print_err("iq_data_start %p size %d\n", iq_data_start, size); + } + } else { + print_err("TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); + } + + return size; +} + +int32_t xran_process_srs_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth) +{ + char *pos = NULL; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + uint32_t tti = 0; + xran_status_t status; + void *pHandle = NULL; + struct rte_mbuf *mb = NULL; + struct xran_prb_map * pRbMap = NULL; + struct xran_prb_elm * prbMapElm = NULL; + uint16_t iq_sample_size_bits = 16; + uint16_t sec_desc_idx; + uint32_t interval = p_xran_dev_ctx->interval_us_local; + + if(expect_comp) + iq_sample_size_bits = iqWidth; + + if(p_xran_dev_ctx->xran2phy_mem_ready == 0) + return 0; + + tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id; + + status = tti << 16 | symb_id; + + if(CC_ID != 0) + rte_panic("CC_ID != 0"); + + if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < p_xran_dev_ctx->fh_cfg.nAntElmTRx && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT) { + pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData; + pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData; + if(pRbMap){ + prbMapElm = &pRbMap->prbMap[sect_id]; + if(sect_id >= pRbMap->nPrbElm) { + print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm); + *mb_free = MBUF_FREE; + return size; + } + } else { + print_err("pRbMap==NULL\n"); + *mb_free = MBUF_FREE; + return size; + } + pos += start_prbu * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits); + if(pos && iq_data_start && size){ + if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { + int idx = 0; + uint16_t *psrc = (uint16_t *)iq_data_start; + uint16_t *pdst = (uint16_t *)pos; + rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb); + /* network byte (be) order of IQ to CPU byte order (le) */ + for (idx = 0; idx < size/sizeof(int16_t); idx++){ + pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); + } + } else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){ + /*if (pRbMap->nPrbElm == 1){ + if (likely (p_xran_dev_ctx->fh_init.mtu >= + p_xran_dev_ctx->fh_cfg.nULRBs * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits))) + { + // no fragmentation + mb = p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl; + if(mb){ + rte_pktmbuf_free(mb); + }else{ + print_err("mb==NULL\n"); + } + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData = iq_data_start; + p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pCtrl = mbuf; + *mb_free = MBUF_KEEP; + } else { + // packet can be fragmented copy RBs + memcpy(pos, iq_data_start, size); + *mb_free = MBUF_FREE; + } + } else */{ + struct xran_section_desc *p_sec_desc = NULL; + prbMapElm = &pRbMap->prbMap[sect_id]; + sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id]; + + if (sec_desc_idx < XRAN_MAX_FRAGMENT) { + p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx]; + } else { + print_err("sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n", sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx); + prbMapElm->nSecDesc[symb_id] = 0; + *mb_free = MBUF_FREE; + return size; + } + + if(p_sec_desc){ + mb = p_sec_desc->pCtrl; + if(mb){ + rte_pktmbuf_free(mb); + } + p_sec_desc->pData = iq_data_start; + p_sec_desc->pCtrl = mbuf; + p_sec_desc->start_prbu = start_prbu; + p_sec_desc->num_prbu = num_prbu; + p_sec_desc->iq_buffer_len = size; + p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf); + //prbMapElm->nSecDesc[symb_id] += 1; + } else { + print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx); + *mb_free = MBUF_FREE; + return size; + } + *mb_free = MBUF_KEEP; + } + } + } else { + print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); + } + } else { + print_err("o-xu%d: TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",p_xran_dev_ctx->xran_port_id, tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); + } + + return size; +} + +int32_t xran_pkt_validate(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + union ecpri_seq_id *seq_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id) +{ + struct xran_device_ctx * p_dev_ctx = (struct xran_device_ctx *)arg; + struct xran_common_counters *pCnt = &p_dev_ctx->fh_counters; + + if(p_dev_ctx->fh_init.io_cfg.id == O_DU) { + if(xran_check_upul_seqid(p_dev_ctx, CC_ID, Ant_ID, slot_id, seq_id->bits.seq_id) != XRAN_STATUS_SUCCESS) { + pCnt->Rx_pkt_dupl++; + return (XRAN_STATUS_FAIL); + } + } else if(p_dev_ctx->fh_init.io_cfg.id == O_RU) { + if(xran_check_updl_seqid(p_dev_ctx, CC_ID, Ant_ID, slot_id, seq_id->bits.seq_id) != XRAN_STATUS_SUCCESS) { + pCnt->Rx_pkt_dupl++; + return (XRAN_STATUS_FAIL); + } + }else { + print_err("incorrect dev type %d\n", p_dev_ctx->fh_init.io_cfg.id); + } + + pCnt->rx_counter++; + + pCnt->Rx_on_time++; + pCnt->Total_msgs_rcvd++; + + return XRAN_STATUS_SUCCESS; +} + +int32_t xran_process_rx_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth) +{ + char *pos = NULL; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)arg; + uint32_t tti = 0; + xran_status_t status; + void *pHandle = NULL; + struct rte_mbuf *mb = NULL; + struct xran_prb_map * pRbMap = NULL; + struct xran_prb_elm * prbMapElm = NULL; + uint16_t iq_sample_size_bits = 16; + uint16_t sec_desc_idx; + uint32_t interval = p_xran_dev_ctx->interval_us_local; + + if(expect_comp) + iq_sample_size_bits = iqWidth; + + tti = frame_id * SLOTS_PER_SYSTEMFRAME(interval) + subframe_id * SLOTNUM_PER_SUBFRAME(interval) + slot_id; + + status = tti << 16 | symb_id; + + if(CC_ID < XRAN_MAX_SECTOR_NR && Ant_ID < XRAN_MAX_ANTENNA_NR && symb_id < XRAN_NUM_OF_SYMBOL_PER_SLOT){ + pos = (char*) p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData; + pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData; + if(pRbMap){ + prbMapElm = &pRbMap->prbMap[sect_id]; + if(sect_id >= pRbMap->nPrbElm) { + print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm); + *mb_free = MBUF_FREE; + return size; + } + } else { + print_err("pRbMap==NULL\n"); + *mb_free = MBUF_FREE; + return size; + } + + pos += start_prbu * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits); + if(pos && iq_data_start && size){ + if (p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_CPU_LE_BYTE_ORDER) { + int idx = 0; + uint16_t *psrc = (uint16_t *)iq_data_start; + uint16_t *pdst = (uint16_t *)pos; + rte_panic("XRAN_CPU_LE_BYTE_ORDER is not supported 0x16%lx\n", (long)mb); + /* network byte (be) order of IQ to CPU byte order (le) */ + for (idx = 0; idx < size/sizeof(int16_t); idx++){ + pdst[idx] = (psrc[idx]>>8) | (psrc[idx]<<8); //rte_be_to_cpu_16(psrc[idx]); + } + } else if (likely(p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder == XRAN_NE_BE_BYTE_ORDER)){ + if (pRbMap->nPrbElm == 1){ + prbMapElm = &pRbMap->prbMap[0]; + if (likely (p_xran_dev_ctx->fh_init.mtu >= + prbMapElm->nRBSize * XRAN_PAYLOAD_1_RB_SZ(iq_sample_size_bits))) + { + /* no fragmentation */ + struct xran_section_desc *p_sec_desc = NULL; + sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id]; + p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx]; + + if(p_sec_desc){ + mb = p_sec_desc->pCtrl; + if(mb){ + rte_pktmbuf_free(mb); + } + p_sec_desc->pData = iq_data_start; + p_sec_desc->pCtrl = mbuf; + p_sec_desc->start_prbu = start_prbu; + p_sec_desc->num_prbu = num_prbu; + p_sec_desc->iq_buffer_len = size; + p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf); + } else { + print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx); + *mb_free = MBUF_FREE; + return size; + } + *mb_free = MBUF_KEEP; + } else { + /* packet can be fragmented copy RBs */ + memcpy(pos, iq_data_start, size); + *mb_free = MBUF_FREE; + } + } else { + struct xran_section_desc *p_sec_desc = NULL; + prbMapElm = &pRbMap->prbMap[sect_id]; + sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id]; + + if (sec_desc_idx < XRAN_MAX_FRAGMENT) { + p_sec_desc = prbMapElm->p_sec_desc[symb_id][sec_desc_idx]; + } else { + print_err("sect_id %d: sec_desc_idx %d tti %u ant %d symb_id %d sec_desc_idx %d\n", sect_id, sec_desc_idx, tti, Ant_ID, symb_id, sec_desc_idx); + prbMapElm->nSecDesc[symb_id] = 0; + *mb_free = MBUF_FREE; + return size; + } + + if(p_sec_desc){ + mb = p_sec_desc->pCtrl; + if(mb){ + rte_pktmbuf_free(mb); + } + p_sec_desc->pData = iq_data_start; + p_sec_desc->pCtrl = mbuf; + p_sec_desc->start_prbu = start_prbu; + p_sec_desc->num_prbu = num_prbu; + p_sec_desc->iq_buffer_len = size; + p_sec_desc->iq_buffer_offset = RTE_PTR_DIFF(iq_data_start, mbuf); + //prbMapElm->nSecDesc[symb_id] += 1; + } else { + print_err("p_sec_desc==NULL tti %u ant %d symb_id %d sec_desc_idx %d\n", tti, Ant_ID, symb_id, sec_desc_idx); + *mb_free = MBUF_FREE; + return size; + } + *mb_free = MBUF_KEEP; + } + } + } else { + print_err("pos %p iq_data_start %p size %d\n",pos, iq_data_start, size); + } + } else { + print_err("o-xu%d: TTI %d(f_%d sf_%d slot_%d) CC %d Ant_ID %d symb_id %d\n",p_xran_dev_ctx->xran_port_id, tti, frame_id, subframe_id, slot_id, CC_ID, Ant_ID, symb_id); + } + + return size; +} diff --git a/fhi_lib/lib/src/xran_rx_proc.h b/fhi_lib/lib/src/xran_rx_proc.h new file mode 100644 index 0000000..8596614 --- /dev/null +++ b/fhi_lib/lib/src/xran_rx_proc.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN RX header file + * @file xran_rx.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_RX_PROC_H_ +#define _XRAN_RX_PROC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include +#include +#include + +#include "xran_fh_o_du.h" +#include "xran_prach_cfg.h" +#include "xran_up_api.h" + + +int32_t xran_process_rx_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth); + +int32_t xran_process_prach_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free); + +int32_t xran_process_srs_sym(void *arg, + struct rte_mbuf *mbuf, + void *iq_data_start, + uint16_t size, + uint8_t CC_ID, + uint8_t Ant_ID, + uint8_t frame_id, + uint8_t subframe_id, + uint8_t slot_id, + uint8_t symb_id, + uint16_t num_prbu, + uint16_t start_prbu, + uint16_t sym_inc, + uint16_t rb, + uint16_t sect_id, + uint32_t *mb_free, + int8_t expect_comp, + uint8_t compMeth, + uint8_t iqWidth); + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_TX_PROC_H_ */ diff --git a/fhi_lib/lib/src/xran_sync_api.c b/fhi_lib/lib/src/xran_sync_api.c index c45d83c..71c2b16 100644 --- a/fhi_lib/lib/src/xran_sync_api.c +++ b/fhi_lib/lib/src/xran_sync_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -71,7 +71,7 @@ static int is_process_running(char *pname) long pid = atol(entry->d_name); if (0 == pid) continue; - sprintf(full_path, "%s/%ld/%s", PROC_DIR, pid, COMM_FILE); + snprintf(full_path, sizeof(full_path), "%s/%ld/%s", PROC_DIR, pid, COMM_FILE); FILE *proc_name_file = fopen(full_path, "r"); if (NULL == proc_name_file) continue; diff --git a/fhi_lib/lib/src/xran_timer.c b/fhi_lib/lib/src/xran_timer.c index 0b86f8e..b13101a 100644 --- a/fhi_lib/lib/src/xran_timer.c +++ b/fhi_lib/lib/src/xran_timer.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -29,7 +29,7 @@ #include #include #include - +#include #include "xran_timer.h" #include "xran_printf.h" #include "xran_mlog_lnx.h" @@ -60,12 +60,12 @@ static struct timespec* p_temp_time; static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */ -static unsigned long current_second = 0; +volatile static unsigned long current_second = 0; static unsigned long started_second = 0; static uint8_t numerlogy = 0; -extern uint32_t xran_lib_ota_sym; -extern uint32_t xran_lib_ota_tti; -extern uint32_t xran_lib_ota_sym_idx; +extern uint32_t xran_lib_ota_sym[]; +extern uint32_t xran_lib_ota_tti[]; +extern uint32_t xran_lib_ota_sym_idx[]; static int debugStop = 0; static int debugStopCount = 0; @@ -92,11 +92,20 @@ uint64_t timing_get_current_second(void) return current_second; } +uint32_t xran_max_ota_sym_idx(uint8_t numerlogy) +{ + return (XRAN_NUM_OF_SYMBOL_PER_SLOT * slots_per_subframe[numerlogy] * MSEC_PER_SEC); +} + int timing_set_numerology(uint8_t value) { numerlogy = value; return numerlogy; } +uint8_t timing_get_numerology(void) +{ + return numerlogy; +} int timing_set_debug_stop(int value, int count) { @@ -146,9 +155,12 @@ unsigned long get_ticks_diff(unsigned long curr_tick, unsigned long last_tick) else return (unsigned long)(0xFFFFFFFFFFFFFFFF - last_tick + curr_tick); } +extern uint16_t xran_getSfnSecStart(void); long poll_next_tick(long interval_ns, unsigned long *used_tick) { + struct xran_ethdi_ctx *p_eth = xran_ethdi_get_ctx(); + struct xran_io_cfg *p_io_cfg = &(p_eth->io_cfg); struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx(); struct xran_common_counters* pCnt = &p_xran_dev_ctx->fh_counters; @@ -157,6 +169,7 @@ long poll_next_tick(long interval_ns, unsigned long *used_tick) static int counter = 0; static long sym_acc = 0; static long sym_cnt = 0; + int i; if(counter == 0) { clock_gettime(CLOCK_REALTIME, p_last_time); @@ -187,16 +200,23 @@ long poll_next_tick(long interval_ns, unsigned long *used_tick) if(current_second != p_cur_time->tv_sec){ current_second = p_cur_time->tv_sec; xran_updateSfnSecStart(); - xran_lib_ota_sym_idx = 0; - xran_lib_ota_tti = 0; - xran_lib_ota_sym = 0; + for (i=0; i < XRAN_PORTS_NUM; i++) + { + xran_lib_ota_tti[i] = 0; + xran_lib_ota_sym[i] = 0; + xran_lib_ota_sym_idx[i] = 0; + } sym_cnt = 0; sym_acc = 0; print_dbg("ToS:C Sync timestamp: [%ld.%09ld]\n", p_cur_time->tv_sec, p_cur_time->tv_nsec); if(debugStop){ if(p_cur_time->tv_sec > started_second && ((p_cur_time->tv_sec % SEC_MOD_STOP) == 0)){ uint64_t t1; - printf("STOP:[%ld.%09ld]\n", p_cur_time->tv_sec, p_cur_time->tv_nsec); + uint32_t tti = xran_lib_ota_tti[0]; + uint32_t slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval_us)); + uint32_t subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval_us), SUBFRAMES_PER_SYSTEMFRAME); + uint32_t frame_id = XranGetFrameNum(tti,xran_getSfnSecStart(),SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval_us)); + printf("STOP:[%ld.%09ld] (%d : %d : %d)\n", p_cur_time->tv_sec, p_cur_time->tv_nsec,frame_id, subframe_id, slot_id); t1 = MLogTick(); rte_pause(); MLogTask(PID_TIME_SYSTIME_STOP, t1, MLogTick()); @@ -205,7 +225,12 @@ long poll_next_tick(long interval_ns, unsigned long *used_tick) } p_cur_time->tv_nsec = 0; // adjust to 1pps } else { - xran_lib_ota_sym_idx = XranIncrementSymIdx(xran_lib_ota_sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT*slots_per_subframe[numerlogy]); + xran_lib_ota_sym_idx[0] = XranIncrementSymIdx(xran_lib_ota_sym_idx[0], XRAN_NUM_OF_SYMBOL_PER_SLOT*slots_per_subframe[numerlogy]); + for (i=1; i < p_xran_dev_ctx->fh_init.xran_ports; i++) + { + struct xran_device_ctx * p_other_ctx = xran_dev_get_ctx_by_id(i); + xran_lib_ota_sym_idx[i] = xran_lib_ota_sym_idx[0] >> (numerlogy - xran_get_conf_numerology(p_other_ctx)); + } /* adjust to sym boundary */ if(sym_cnt & 1) sym_acc += fine_tuning[numerlogy][0]; @@ -233,17 +258,14 @@ long poll_next_tick(long interval_ns, unsigned long *used_tick) p_cur_time = p_temp_time; break; } else { - if( likely(xran_if_current_state == XRAN_RUNNING)){ + if(likely((xran_if_current_state == XRAN_RUNNING)||(xran_if_current_state == XRAN_OWDM))){ uint64_t t1, t2; t1 = xran_tick(); - if(p_xran_dev_ctx->fh_init.io_cfg.pkt_proc_core == 0) - ring_processing_func(); - - process_dpdk_io(); + if(p_eth->time_wrk_cfg.f) + p_eth->time_wrk_cfg.f(p_eth->time_wrk_cfg.arg); - /* work around for some kernel */ - if(p_xran_dev_ctx->fh_init.io_cfg.io_sleep) + if(p_io_cfg->io_sleep) nanosleep(&sleeptime,NULL); t2 = xran_tick(); diff --git a/fhi_lib/lib/src/xran_transport.c b/fhi_lib/lib/src/xran_transport.c index 325616b..881f6f6 100644 --- a/fhi_lib/lib/src/xran_transport.c +++ b/fhi_lib/lib/src/xran_transport.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -48,7 +49,7 @@ */ int xran_get_ecpri_hdr_size(void) { - return(sizeof(struct xran_ecpri_hdr) - sizeof(struct xran_ecpri_cmn_hdr)); + return(sizeof(struct xran_ecpri_hdr) - sizeof(union xran_ecpri_cmn_hdr)); } /** @@ -69,6 +70,9 @@ uint16_t xran_compose_cid(uint8_t CU_Port_ID, uint8_t BandSector_ID, uint8_t CC_ conf = xran_get_conf_eAxC(NULL); + if(conf == NULL) + rte_panic("conf == NULL"); + cid = ((CU_Port_ID << conf->bit_cuPortId) & conf->mask_cuPortId) | ((BandSector_ID << conf->bit_bandSectorId) & conf->mask_bandSectorId) | ((CC_ID << conf->bit_ccId) & conf->mask_ccId) @@ -93,6 +97,9 @@ void xran_decompose_cid(uint16_t cid, struct xran_eaxc_info *result) conf = xran_get_conf_eAxC(NULL); cid = rte_be_to_cpu_16(cid); + if(conf == NULL) + rte_panic("conf == NULL"); + result->cuPortId = (cid&conf->mask_cuPortId) >> conf->bit_cuPortId; result->bandSectorId = (cid&conf->mask_bandSectorId) >> conf->bit_bandSectorId; result->ccId = (cid&conf->mask_ccId) >> conf->bit_ccId; @@ -116,7 +123,7 @@ inline void xran_update_ecpri_payload_size(struct rte_mbuf *mbuf, int size) ecpri_hdr = rte_pktmbuf_mtod(mbuf, struct xran_ecpri_hdr *); - ecpri_hdr->cmnhdr.ecpri_payl_size = rte_cpu_to_be_16(size); + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(size); } @@ -155,19 +162,24 @@ int xran_build_ecpri_hdr(struct rte_mbuf *mbuf, } /* Fill common header */ - tmp->cmnhdr.ecpri_ver = XRAN_ECPRI_VER; - tmp->cmnhdr.ecpri_resv = 0; // should be zero - tmp->cmnhdr.ecpri_concat = 0; - tmp->cmnhdr.ecpri_mesg_type = ECPRI_RT_CONTROL_DATA; + /*tmp->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER; + //tmp->cmnhdr.bits.ecpri_resv = 0; // should be zero + //tmp->cmnhdr.bits.ecpri_concat = 0; + //tmp->cmnhdr.bits.ecpri_mesg_type = ECPRI_RT_CONTROL_DATA;*/ + + tmp->cmnhdr.data.data_num_1 = (XRAN_ECPRI_VER << xran_ecpri_cmn_hdr_bitfield_EcpriVer) + | (ECPRI_RT_CONTROL_DATA << xran_ecpri_cmn_hdr_bitfield_EcpriMsgType); tmp->ecpri_xtc_id = xran_compose_cid(0, 0, CC_ID, Ant_ID); /* TODO: Transport layer fragmentation is not supported */ - tmp->ecpri_seq_id.seq_id = seq_id; - tmp->ecpri_seq_id.sub_seq_id = 0; - tmp->ecpri_seq_id.e_bit = 1; + //tmp->ecpri_seq_id.bits.seq_id = seq_id; + //tmp->ecpri_seq_id.bits.sub_seq_id = 0; + //tmp->ecpri_seq_id.bits.e_bit = 1; + tmp->ecpri_seq_id.data.data_num_1 = (seq_id << ecpri_seq_id_bitfield_seq_id) + | (1 << ecpri_seq_id_bitfield_e_bit); /* Starts with eCPRI header size */ - payloadlen = xran_get_ecpri_hdr_size(); + payloadlen = XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size(); *ecpri_hdr = tmp; @@ -193,8 +205,7 @@ int xran_parse_ecpri_hdr(struct rte_mbuf *mbuf, struct xran_ecpri_hdr **ecpri_hdr, struct xran_recv_packet_info *pkt_info) { - int ret; - + int ret = XRAN_STATUS_SUCCESS; *ecpri_hdr = rte_pktmbuf_mtod(mbuf, void *); if(*ecpri_hdr == NULL) { @@ -202,26 +213,32 @@ int xran_parse_ecpri_hdr(struct rte_mbuf *mbuf, return (XRAN_STATUS_INVALID_PACKET); } + if(((*ecpri_hdr)->cmnhdr.bits.ecpri_ver != XRAN_ECPRI_VER) || ((*ecpri_hdr)->cmnhdr.bits.ecpri_resv != 0)){ + print_err("Invalid eCPRI version - %d", (*ecpri_hdr)->cmnhdr.bits.ecpri_ver); + print_err("Invalid reserved field - %d", (*ecpri_hdr)->cmnhdr.bits.ecpri_resv); + return (XRAN_STATUS_INVALID_PACKET); + } + /* Process eCPRI header */ - ret = XRAN_STATUS_SUCCESS; - if((*ecpri_hdr)->cmnhdr.ecpri_ver != XRAN_ECPRI_VER) { + /*if((*ecpri_hdr)->cmnhdr.ecpri_ver != XRAN_ECPRI_VER) { print_err("Invalid eCPRI version - %d", (*ecpri_hdr)->cmnhdr.ecpri_ver); ret = XRAN_STATUS_INVALID_PACKET; - } - if((*ecpri_hdr)->cmnhdr.ecpri_resv != 0) { + }*/ + /*if((*ecpri_hdr)->cmnhdr.ecpri_resv != 0) { print_err("Invalid reserved field - %d", (*ecpri_hdr)->cmnhdr.ecpri_resv); ret = XRAN_STATUS_INVALID_PACKET; - } + }*/ + if(pkt_info != NULL) { /* store the information from header */ - pkt_info->ecpri_version = (*ecpri_hdr)->cmnhdr.ecpri_ver; - pkt_info->msg_type = (enum ecpri_msg_type)(*ecpri_hdr)->cmnhdr.ecpri_mesg_type; - pkt_info->payload_len = rte_be_to_cpu_16((*ecpri_hdr)->cmnhdr.ecpri_payl_size); + pkt_info->ecpri_version = (*ecpri_hdr)->cmnhdr.bits.ecpri_ver; + pkt_info->msg_type = (enum ecpri_msg_type)(*ecpri_hdr)->cmnhdr.bits.ecpri_mesg_type; + pkt_info->payload_len = rte_be_to_cpu_16((*ecpri_hdr)->cmnhdr.bits.ecpri_payl_size); - pkt_info->seq_id = (*ecpri_hdr)->ecpri_seq_id.seq_id; - pkt_info->subseq_id = (*ecpri_hdr)->ecpri_seq_id.sub_seq_id; - pkt_info->ebit = (*ecpri_hdr)->ecpri_seq_id.e_bit; + pkt_info->seq_id = (*ecpri_hdr)->ecpri_seq_id.bits.seq_id; + pkt_info->subseq_id = (*ecpri_hdr)->ecpri_seq_id.bits.sub_seq_id; + pkt_info->ebit = (*ecpri_hdr)->ecpri_seq_id.bits.e_bit; xran_decompose_cid((*ecpri_hdr)->ecpri_xtc_id, &(pkt_info->eaxc)); } diff --git a/fhi_lib/lib/src/xran_tx_proc.c b/fhi_lib/lib/src/xran_tx_proc.c new file mode 100644 index 0000000..3cfb2be --- /dev/null +++ b/fhi_lib/lib/src/xran_tx_proc.c @@ -0,0 +1,1573 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN TX functionality + * @file xran_tx.c + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#define _GNU_SOURCE +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xran_fh_o_du.h" + +#include "ethdi.h" +#include "xran_pkt.h" +#include "xran_up_api.h" +#include "xran_cp_api.h" +#include "xran_sync_api.h" +#include "xran_lib_mlog_tasks_id.h" +#include "xran_timer.h" +#include "xran_main.h" +#include "xran_common.h" +#include "xran_dev.h" +#include "xran_frame_struct.h" +#include "xran_printf.h" +#include "xran_app_frag.h" +#include "xran_tx_proc.h" +#include "xran_cp_proc.h" + +#include "xran_mlog_lnx.h" + +enum xran_in_period +{ + XRAN_IN_PREV_PERIOD = 0, + XRAN_IN_CURR_PERIOD, + XRAN_IN_NEXT_PERIOD +}; + + +struct rte_mbuf * +xran_attach_up_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, + struct rte_mbuf_ext_shared_info * p_share_data, + enum xran_compression_method compMeth, enum xran_comp_hdr_type staticEn); + + +static void +extbuf_free_callback(void *addr __rte_unused, void *opaque __rte_unused) +{ + /*long t1 = MLogTick(); + MLogTask(77777, t1, t1+100);*/ +} + +static inline int32_t XranOffsetSym(int32_t offSym, int32_t otaSym, int32_t numSymTotal, enum xran_in_period* pInPeriod) +{ + int32_t sym; + + // Suppose the offset is usually small + if (unlikely(offSym > otaSym)) + { + sym = numSymTotal - offSym + otaSym; + *pInPeriod = XRAN_IN_PREV_PERIOD; + } + else + { + sym = otaSym - offSym; + + if (unlikely(sym >= numSymTotal)) + { + sym -= numSymTotal; + *pInPeriod = XRAN_IN_NEXT_PERIOD; + } + else + { + *pInPeriod = XRAN_IN_CURR_PERIOD; + } + } + + return sym; +} + +// Return SFN at current second start, 10 bits, [0, 1023] +uint16_t xran_getSfnSecStart(void) +{ + return xran_SFN_at_Sec_Start; +} + +/* Send burst of packets on an output interface */ +static inline int +xran_send_burst(struct xran_device_ctx *dev, struct mbuf_table* p_m_table, uint16_t port) +{ + struct xran_common_counters * pCnt = NULL; + struct rte_mbuf **m_table; + int32_t i = 0; + int32_t n = 0; + int32_t ret = 0; + + if(dev) + pCnt = &dev->fh_counters; + else + rte_panic("incorrect dev\n"); + + m_table = p_m_table->m_table; + n = p_m_table->len; + + for(i = 0; i < n; i++) { + /*rte_mbuf_sanity_check(m_table[i], 0);*/ + /*rte_pktmbuf_dump(stdout, m_table[i], 256);*/ + pCnt->tx_counter++; + pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len(m_table[i]); + ret += dev->send_upmbuf2ring(m_table[i], ETHER_TYPE_ECPRI, port); + } + + if (unlikely(ret < n)) { + print_err("core %d [p: %d-> vf %d] ret [%d] < n[%d] enq %ld\n", + rte_lcore_id(), dev->xran_port_id, port, ret, n, pCnt->tx_counter); + } + + return 0; +} + +/* Send a single 5G symbol over multiple packets */ +static inline int32_t prepare_symbol_opt(enum xran_pkt_dir direction, + uint16_t section_id, + struct rte_mbuf *mb, + struct rb_map *data, + uint8_t compMeth, + uint8_t iqWidth, + const enum xran_input_byte_order iq_buf_byte_order, + int prb_start, + int prb_num, + uint8_t CC_ID, + uint8_t RU_Port_ID, + uint8_t seq_id, + uint32_t do_copy, + struct xran_up_pkt_gen_params *xp, + enum xran_comp_hdr_type staticEn) +{ + int parm_size; + int32_t n_bytes; + int32_t prep_bytes; + int16_t nPktSize; + uint32_t off; + + + iqWidth = (iqWidth==0) ? 16 : iqWidth; + switch(compMeth) { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + n_bytes = (3 * iqWidth + parm_size) * prb_num; + n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN); + + nPktSize = sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + + n_bytes; + if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn ==XRAN_COMP_HDR_TYPE_DYNAMIC)) + nPktSize += sizeof(struct data_section_compression_hdr); + + +#if 0 + /* radio app header */ + xp->app_params.data_direction = direction; + xp->app_params.payl_ver = 1; + xp->app_params.filter_id = 0; + xp->app_params.frame_id = frame_id; + xp->app_params.sf_slot_sym.subframe_id = subframe_id; + xp->app_params.sf_slot_sym.slot_id = xran_slotid_convert(slot_id, 0); + xp->app_params.sf_slot_sym.symb_id = symbol_no; + + /* convert to network byte order */ + xp->app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp->app_params.sf_slot_sym.value); +#endif + + xp->sec_hdr.fields.sect_id = section_id; + xp->sec_hdr.fields.num_prbu = (uint8_t)XRAN_CONVERT_NUMPRBC(prb_num); + xp->sec_hdr.fields.start_prbu = (uint8_t)prb_start; + xp->sec_hdr.fields.sym_inc = 0; + xp->sec_hdr.fields.rb = 0; + + + /* compression */ + xp->compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth; + xp->compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth); + xp->compr_hdr_param.rsrvd = 0; + + /* network byte order */ + xp->sec_hdr.fields.all_bits = rte_cpu_to_be_32(xp->sec_hdr.fields.all_bits); + + if (mb == NULL){ + MLogPrint(NULL); + errx(1, "out of mbufs after %d packets", 1); + } + + prep_bytes = xran_prepare_iq_symbol_portion(mb, + data, + iq_buf_byte_order, + n_bytes, + xp, + CC_ID, + RU_Port_ID, + seq_id, + staticEn, + do_copy); + if (prep_bytes <= 0) + errx(1, "failed preparing symbol"); + + rte_pktmbuf_pkt_len(mb) = nPktSize; + rte_pktmbuf_data_len(mb) = nPktSize; + +#ifdef DEBUG + printf("Symbol %2d prep_bytes (%d packets, %d bytes)\n", symbol_no, i, n_bytes); +#endif + + return prep_bytes; +} + +int32_t xran_process_tx_sym_cp_off(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, + int32_t do_srs) +{ + int32_t retval = 0; + char *pos = NULL; + char *p_sec_iq = NULL; + void *mb = NULL; + void *send_mb = NULL; + int prb_num = 0; + uint16_t iq_sample_size_bits = 16; + uint16_t vf_id = 0; + + struct xran_prb_map *prb_map = NULL; + uint8_t num_ant_elm = 0; + + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)pHandle; + if (p_xran_dev_ctx == NULL) + return retval; + struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters; + struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig); + struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg); + + num_ant_elm = xran_get_num_ant_elm(pHandle); + enum xran_pkt_dir direction; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; + + struct rte_mbuf *eth_oran_hdr = NULL; + char *ext_buff = NULL; + uint16_t ext_buff_len = 0; + struct rte_mbuf *tmp = NULL; + rte_iova_t ext_buff_iova = 0; + uint8_t PortId = p_xran_dev_ctx->xran_port_id; + + staticEn = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + + if(PortId >= XRAN_PORTS_NUM) + rte_panic("incorrect PORT ID\n"); + + struct rte_mbuf_ext_shared_info * p_share_data = NULL; + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { + direction = XRAN_DIR_DL; /* O-DU */ + prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; + } else { + direction = XRAN_DIR_UL; /* RU */ + prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; + } + + if(xran_fs_get_slot_type(PortId, cc_id, tti, ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SLOT_TYPE_DL : XRAN_SLOT_TYPE_UL)) == 1 + || xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_SP) == 1 + || xran_fs_get_slot_type(PortId, cc_id, tti, XRAN_SLOT_TYPE_FDD) == 1){ + + if(xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == ((p_xran_dev_ctx->fh_init.io_cfg.id == O_DU)? XRAN_SYMBOL_TYPE_DL : XRAN_SYMBOL_TYPE_UL) + || xran_fs_get_symbol_type(PortId, cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD){ + + vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_id); + pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + mb = (void*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; + prb_map = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulTxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData; + + + if(prb_map){ + int32_t elmIdx = 0; + for (elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++){ + //print_err("tti is %d, cc_id is %d, ant_id is %d, prb_map->nPrbElm id - %d", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_id, prb_map->nPrbElm); + uint16_t sec_id = elmIdx; + struct xran_prb_elm * prb_map_elm = &prb_map->prbMap[elmIdx]; + struct xran_section_desc * p_sec_desc = NULL; + p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sec_id]; + + if(prb_map_elm == NULL){ + rte_panic("p_sec_desc == NULL\n"); + } + + p_sec_desc = prb_map_elm->p_sec_desc[sym_id][0]; + + p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset); + + /* calculate offset for external buffer */ + ext_buff_len = p_sec_desc->iq_buffer_len; + ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + + ext_buff_len += RTE_PKTMBUF_HEADROOM + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + 18; + + if ((prb_map_elm->compMethod != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)){ + ext_buff -= sizeof (struct data_section_compression_hdr); + ext_buff_len += sizeof (struct data_section_compression_hdr); + } + + eth_oran_hdr = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]); + if (unlikely (( eth_oran_hdr) == NULL)) { + rte_panic("Failed rte_pktmbuf_alloc\n"); + } + + p_share_data->free_cb = extbuf_free_callback; + p_share_data->fcb_opaque = NULL; + rte_mbuf_ext_refcnt_set(p_share_data, 1); + + ext_buff_iova = rte_mempool_virt2iova(mb); + if (unlikely (( ext_buff_iova) == 0)) { + rte_panic("Failed rte_mem_virt2iova \n"); + } + + if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { + rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + } + + rte_pktmbuf_attach_extbuf(eth_oran_hdr, + ext_buff, + ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb), + ext_buff_len, + p_share_data); + + rte_pktmbuf_reset_headroom(eth_oran_hdr); + + tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr)); + if (unlikely (( tmp) == NULL)) { + rte_panic("Failed rte_pktmbuf_prepend \n"); + } + send_mb = eth_oran_hdr; + + + uint8_t seq_id = (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? + xran_get_updl_seqid(pHandle, cc_id, ant_id) : + xran_get_upul_seqid(pHandle, cc_id, ant_id); + + + + /* first all PRBs */ + int32_t num_bytes = prepare_symbol_ex(direction, sec_id, + send_mb, + (uint8_t *)p_sec_iq, + prb_map_elm->compMethod, + prb_map_elm->iqWidth, + p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, + frame_id, subframe_id, slot_id, sym_id, + prb_map_elm->nRBStart, prb_map_elm->nRBSize, + cc_id, ant_id, + seq_id, + 0, + staticEn); + + rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0); + pCnt->tx_counter++; + pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb); + p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, vf_id); + } + } else { + printf("(%d %d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_id, sym_id); + } + + if(p_xran_dev_ctx->enablePrach + && (p_xran_dev_ctx->fh_init.io_cfg.id == O_RU)) { /* Only RU needs to send PRACH I/Q */ + uint32_t is_prach_slot = xran_is_prach_slot(PortId, subframe_id, slot_id); + + if(((frame_id % pPrachCPConfig->x) == pPrachCPConfig->y[0]) + && (is_prach_slot == 1) + && (sym_id >= p_xran_dev_ctx->prach_start_symbol[cc_id]) + && (sym_id <= p_xran_dev_ctx->prach_last_symbol[cc_id])) { + int prach_port_id = ant_id + pPrachCPConfig->eAxC_offset; + int compMethod, parm_size; + uint8_t symb_id_offset = sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]; + + compMethod = p_xran_dev_ctx->fh_cfg.ru_conf.compMeth_PRACH; + switch(compMethod) { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + pos = (char*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[symb_id_offset].pData; + //pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]) * pPrachCPConfig->numPrbc * N_SC_PER_PRB * 4; + /*pos += (sym_id - p_xran_dev_ctx->prach_start_symbol[cc_id]) + * (3*p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth + parm_size) + * pPrachCPConfig->numPrbc;*/ + mb = NULL;//(void*) p_xran_dev_ctx->sFHPrachRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[0].pCtrl; + + send_symbol_ex(pHandle, + direction, + xran_alloc_sectionid(pHandle, direction, cc_id, prach_port_id, slot_id), + (struct rte_mbuf *)mb, + (uint8_t *)pos, + compMethod, + p_xran_dev_ctx->fh_cfg.ru_conf.iqWidth_PRACH, + p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, + frame_id, subframe_id, slot_id, sym_id, + pPrachCPConfig->startPrbc, pPrachCPConfig->numPrbc, + cc_id, prach_port_id, + xran_get_upul_seqid(pHandle, cc_id, prach_port_id)); + retval = 1; + } + } /* if(p_xran_dev_ctx->enablePrach ..... */ + } /* RU mode or C-Plane is not used */ + } + + return retval; +} + +int32_t +xran_process_tx_srs_cp_off(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id) +{ + int32_t retval = 0; + char *pos = NULL; + char *p_sec_iq = NULL; + void *mb = NULL; + void *send_mb = NULL; + int prb_num = 0; + uint16_t iq_sample_size_bits = 16; + + struct xran_prb_map *prb_map = NULL; + uint8_t num_ant_elm = 0; + + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *)pHandle; + struct xran_common_counters * pCnt = &p_xran_dev_ctx->fh_counters; + struct xran_prach_cp_config *pPrachCPConfig = &(p_xran_dev_ctx->PrachCPConfig); + struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg); + + num_ant_elm = xran_get_num_ant_elm(pHandle); + enum xran_pkt_dir direction; + + struct rte_mbuf *eth_oran_hdr = NULL; + char *ext_buff = NULL; + uint16_t ext_buff_len = 0; + struct rte_mbuf *tmp = NULL; + rte_iova_t ext_buff_iova = 0; + int32_t ant_elm_eAxC_id = ant_id + p_srs_cfg->eAxC_offset; + uint32_t vf_id = 0; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; + + if (p_xran_dev_ctx != NULL) + { + + if(p_xran_dev_ctx->xran_port_id >= XRAN_PORTS_NUM) + rte_panic("incorrect PORT ID\n"); + + struct rte_mbuf_ext_shared_info * p_share_data = NULL; + + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { + direction = XRAN_DIR_DL; /* O-DU */ + prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; + rte_panic("incorrect O_DU\n"); + } else { + direction = XRAN_DIR_UL; /* RU */ + prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; + } + + + staticEn = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + +#if 1 + if (tti % 5 == 3) { + { +#else + if(xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_UL) == 1 + || xran_fs_get_slot_type(cc_id, tti, XRAN_SLOT_TYPE_FDD) == 1) { + if(xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_UL + || xran_fs_get_symbol_type(cc_id, tti, sym_id) == XRAN_SYMBOL_TYPE_FDD) { +#endif + pos = (char*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + mb = (void*) p_xran_dev_ctx->sFHSrsRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; + prb_map = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers->pData; + vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_elm_eAxC_id); + + if(prb_map) { + int32_t elmIdx = 0; + for (elmIdx = 0; elmIdx < prb_map->nPrbElm && elmIdx < XRAN_MAX_SECTIONS_PER_SLOT; elmIdx++) { + uint16_t sec_id = elmIdx; + struct xran_prb_elm * prb_map_elm = &prb_map->prbMap[elmIdx]; + struct xran_section_desc * p_sec_desc = NULL; + + if(prb_map_elm == NULL) { + rte_panic("p_sec_desc == NULL\n"); + } + + /* skip, if not scheduled */ + if(sym_id < prb_map_elm->nStartSymb || sym_id >= prb_map_elm->nStartSymb + prb_map_elm->numSymb) + return 0; + + p_share_data = &p_xran_dev_ctx->srs_share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id]; + p_sec_desc = prb_map_elm->p_sec_desc[sym_id][0]; + p_sec_iq = ((char*)pos + p_sec_desc->iq_buffer_offset); + + /* calculate offset for external buffer */ + ext_buff_len = p_sec_desc->iq_buffer_len; + ext_buff = p_sec_iq - (RTE_PKTMBUF_HEADROOM + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + + ext_buff_len += RTE_PKTMBUF_HEADROOM + + sizeof (struct xran_ecpri_hdr) + + sizeof (struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + 18; + + if ((prb_map_elm->compMethod != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)){ + ext_buff -= sizeof (struct data_section_compression_hdr); + ext_buff_len += sizeof (struct data_section_compression_hdr); + } + +// eth_oran_hdr = rte_pktmbuf_alloc(_eth_mbuf_pool_small); + eth_oran_hdr = xran_ethdi_mbuf_indir_alloc(); + + if (unlikely (( eth_oran_hdr) == NULL)) { + rte_panic("Failed rte_pktmbuf_alloc\n"); + } + + p_share_data->free_cb = extbuf_free_callback; + p_share_data->fcb_opaque = NULL; + rte_mbuf_ext_refcnt_set(p_share_data, 1); + + ext_buff_iova = rte_mempool_virt2iova(mb); + if (unlikely (( ext_buff_iova) == 0)) { + rte_panic("Failed rte_mem_virt2iova \n"); + } + + if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { + rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + } + + rte_pktmbuf_attach_extbuf(eth_oran_hdr, + ext_buff, + ext_buff_iova + RTE_PTR_DIFF(ext_buff , mb), + ext_buff_len, + p_share_data); + + rte_pktmbuf_reset_headroom(eth_oran_hdr); + + tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(eth_oran_hdr, sizeof(struct rte_ether_hdr)); + if (unlikely (( tmp) == NULL)) { + rte_panic("Failed rte_pktmbuf_prepend \n"); + } + send_mb = eth_oran_hdr; + + uint8_t seq_id = (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) ? + xran_get_updl_seqid(pHandle, cc_id, ant_elm_eAxC_id) : + xran_get_upul_seqid(pHandle, cc_id, ant_elm_eAxC_id); + /* first all PRBs */ + int32_t num_bytes = prepare_symbol_ex(direction, sec_id, + send_mb, + (uint8_t *)p_sec_iq, + prb_map_elm->compMethod, + prb_map_elm->iqWidth, + p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, + frame_id, subframe_id, slot_id, sym_id, + prb_map_elm->nRBStart, prb_map_elm->nRBSize, + cc_id, ant_elm_eAxC_id, + seq_id, + 0, + staticEn); + + rte_mbuf_sanity_check((struct rte_mbuf *)send_mb, 0); + pCnt->tx_counter++; + pCnt->tx_bytes_counter += rte_pktmbuf_pkt_len((struct rte_mbuf *)send_mb); + p_xran_dev_ctx->send_upmbuf2ring((struct rte_mbuf *)send_mb, ETHER_TYPE_ECPRI, vf_id); + } + } else { + printf("(%d %d %d %d) prb_map == NULL\n", tti % XRAN_N_FE_BUF_LEN, cc_id, ant_elm_eAxC_id, sym_id); + } + } + } + } + + return retval; +} + +struct rte_mbuf * +xran_attach_up_ext_buf(uint16_t vf_id, int8_t* p_ext_buff_start, int8_t* p_ext_buff, uint16_t ext_buff_len, + struct rte_mbuf_ext_shared_info * p_share_data, + enum xran_compression_method compMeth, enum xran_comp_hdr_type staticEn) +{ + struct rte_mbuf *mb_oran_hdr_ext = NULL; + struct rte_mbuf *tmp = NULL; + int8_t *ext_buff = NULL; + rte_iova_t ext_buff_iova = 0; + ext_buff = p_ext_buff - (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + + ext_buff_len += RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + 18; + if ((compMeth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) { + ext_buff -= sizeof (struct data_section_compression_hdr); + ext_buff_len += sizeof (struct data_section_compression_hdr); + } + mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]); + + if (unlikely (( mb_oran_hdr_ext) == NULL)) { + rte_panic("[core %d]Failed rte_pktmbuf_alloc on vf %d\n", rte_lcore_id(), vf_id); + } + + p_share_data->free_cb = extbuf_free_callback; + p_share_data->fcb_opaque = NULL; + rte_mbuf_ext_refcnt_set(p_share_data, 1); + + ext_buff_iova = rte_mempool_virt2iova(p_ext_buff_start); + if (unlikely (( ext_buff_iova) == 0)) { + rte_panic("Failed rte_mem_virt2iova \n"); + } + + if (unlikely (( (rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) { + rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + } + + rte_pktmbuf_attach_extbuf(mb_oran_hdr_ext, + ext_buff, + ext_buff_iova + RTE_PTR_DIFF(ext_buff , p_ext_buff_start), + ext_buff_len, + p_share_data); + + rte_pktmbuf_reset_headroom(mb_oran_hdr_ext); + + tmp = (struct rte_mbuf *)rte_pktmbuf_prepend(mb_oran_hdr_ext, sizeof(struct rte_ether_hdr)); + if (unlikely (( tmp) == NULL)) { + rte_panic("Failed rte_pktmbuf_prepend \n"); + } + + return mb_oran_hdr_ext; +} + +int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, + uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, + uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db) +{ + int32_t retval = 0; + struct cp_up_tx_desc* p_desc = NULL; + struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx(); + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle; + + p_desc = xran_pkt_gen_desc_alloc(); + if(p_desc) { + p_desc->pHandle = pHandle; + p_desc->ctx_id = ctx_id; + p_desc->tti = tti; + p_desc->cc_id = num_cc; + p_desc->ant_id = num_ant; + p_desc->frame_id = frame_id; + p_desc->subframe_id = subframe_id; + p_desc->slot_id = slot_id; + p_desc->sym_id = sym_id; + p_desc->compType = (uint32_t)compType; + p_desc->direction = (uint32_t)direction; + p_desc->xran_port_id = xran_port_id; + p_desc->p_sec_db = (void*)p_sec_db; + + if(likely(p_xran_dev_ctx->xran_port_id < XRAN_PORTS_NUM)) { + if (rte_ring_enqueue(eth_ctx->up_dl_pkt_gen_ring[p_xran_dev_ctx->xran_port_id], p_desc->mb) == 0) + return 1; /* success */ + else + xran_pkt_gen_desc_free(p_desc); + } else { + rte_panic("incorrect port %d", p_xran_dev_ctx->xran_port_id); + } + } else { + print_dbg("xran_pkt_gen_desc_alloc failure %d", p_xran_dev_ctx->xran_port_id); + } + + return retval; +} + +int32_t +xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id) +{ + int32_t retval = 0; + struct cp_up_tx_desc* p_desc = NULL; + struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx(); + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle; + + p_desc = xran_pkt_gen_desc_alloc(); + if(p_desc) { + p_desc->pHandle = pHandle; + p_desc->ctx_id = ctx_id; + p_desc->tti = tti; + p_desc->cc_id = cc_id; + p_desc->ant_id = ant_id; + p_desc->frame_id = frame_id; + p_desc->subframe_id = subframe_id; + p_desc->slot_id = slot_id; + p_desc->sym_id = sym_id; + + if(likely(p_xran_dev_ctx->xran_port_id < XRAN_PORTS_NUM)) { + if (rte_ring_enqueue(eth_ctx->up_dl_pkt_gen_ring[p_xran_dev_ctx->xran_port_id], p_desc->mb) == 0) + return 1; /* success */ + else + xran_pkt_gen_desc_free(p_desc); + } else { + rte_panic("incorrect port %d", p_xran_dev_ctx->xran_port_id); + } + } else { + print_dbg("xran_pkt_gen_desc_alloc failure %d", p_xran_dev_ctx->xran_port_id); + } + + return retval; +} + +int32_t +xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id) +{ + int32_t retval = 0; + + struct rte_mbuf *eth_oran_hdr = NULL; + char *ext_buff = NULL; + uint16_t ext_buff_len = 0; + struct rte_mbuf *tmp = NULL; + rte_iova_t ext_buff_iova = 0; + char *pos = NULL; + char *p_sec_iq = NULL; + void *mb = NULL; + struct rte_mbuf *to_free_mbuf = NULL; + int prb_num = 0; + uint16_t iq_sample_size_bits = 16; + uint32_t next = 0; + int32_t num_sections = 0; + uint16_t len = 0; + int16_t len2 = 0; + uint16_t i = 0; + + uint64_t t1; + struct mbuf_table loc_tx_mbufs; + struct xran_up_pkt_gen_params loc_xp; + + struct xran_section_info *sectinfo = NULL; + struct xran_device_ctx *p_xran_dev_ctx = (struct xran_device_ctx*)pHandle; + enum xran_pkt_dir direction; + uint16_t vf_id = 0; + enum xran_comp_hdr_type compType = XRAN_COMP_HDR_TYPE_DYNAMIC; + + struct rte_mbuf_ext_shared_info * p_share_data = NULL; + + if (p_xran_dev_ctx != NULL) + { + compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { + direction = XRAN_DIR_DL; /* O-DU */ + prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; + } else { + direction = XRAN_DIR_UL; /* RU */ + prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; + } + + vf_id = xran_map_ecpriPcid_to_vf(p_xran_dev_ctx, direction, cc_id, ant_id); + next = 0; + num_sections = xran_cp_getsize_section_info(pHandle, direction, cc_id, ant_id, ctx_id); + /* iterate C-Plane configuration to generate corresponding U-Plane */ + if(num_sections) + prepare_sf_slot_sym(direction, frame_id, subframe_id, slot_id, sym_id, &loc_xp); + + loc_tx_mbufs.len = 0; + while(next < num_sections) { + sectinfo = xran_cp_iterate_section_info(pHandle, direction, cc_id, ant_id, ctx_id, &next); + + if(sectinfo == NULL) + break; + + if(sectinfo->type != XRAN_CP_SECTIONTYPE_1) { /* only supports type 1 */ + print_err("Invalid section type in section DB - %d", sectinfo->type); + continue; + } + + /* skip, if not scheduled */ + if(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol) + continue; + + + if(sectinfo->compMeth) + iq_sample_size_bits = sectinfo->iqWidth; + + print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next, + sectinfo->type, sectinfo->id, sectinfo->startPrbc, + sectinfo->numPrbc,sectinfo->startSymId, sectinfo->numSymbol); + + p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sectinfo->id]; + + len = loc_tx_mbufs.len; + len2 = 0; + i = 0; + + //Added for Klocworks + if (len >= MBUF_TABLE_SIZE) { + len = MBUF_TABLE_SIZE - 1; + rte_panic("len >= MBUF_TABLE_SIZE\n"); + } + + to_free_mbuf = p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id]; + pos = (char*) p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + mb = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; + + if(mb == NULL) { + rte_panic("mb == NULL\n"); + } + + p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset); + ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len; + + mb = xran_attach_up_ext_buf(vf_id, (int8_t *)mb, (int8_t *) p_sec_iq, + (uint16_t) ext_buff_len, + p_share_data, (enum xran_compression_method) sectinfo->compMeth, compType); + p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][sectinfo->id] = mb; + rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */ + + if(to_free_mbuf) { + rte_pktmbuf_free(to_free_mbuf); + } + + /* first all PRBs */ + prepare_symbol_opt(direction, sectinfo->id, + mb, + (struct rb_map *)p_sec_iq, + sectinfo->compMeth, + sectinfo->iqWidth, + p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder, + sectinfo->startPrbc, + sectinfo->numPrbc, + cc_id, + ant_id, + xran_get_updl_seqid(pHandle, cc_id, ant_id), + 0, + &loc_xp, + compType); + + /* if we don't need to do any fragmentation */ + if (likely (p_xran_dev_ctx->fh_init.mtu >= + sectinfo->numPrbc * (3*iq_sample_size_bits + 1))) { + /* no fragmentation */ + loc_tx_mbufs.m_table[len] = mb; + len2 = 1; + } else { + /* fragmentation */ + uint8_t * seq_num = xran_get_updl_seqid_addr(pHandle, cc_id, ant_id); + if(seq_num) + (*seq_num)--; + else + rte_panic("pointer to seq number is NULL [CC %d Ant %d]\n", cc_id, ant_id); + + len2 = xran_app_fragment_packet(mb, + &loc_tx_mbufs.m_table[len], + (uint16_t)(MBUF_TABLE_SIZE - len), + p_xran_dev_ctx->fh_init.mtu, + p_xran_dev_ctx->direct_pool, + p_xran_dev_ctx->indirect_pool, + sectinfo->startPrbc, + sectinfo->numPrbc, + seq_num, + sectinfo->iqWidth, + ((sectinfo->iqWidth == 16)||(compType==XRAN_COMP_HDR_TYPE_STATIC)) ? 0 : 1); + + /* Free input packet */ + rte_pktmbuf_free(mb); + + /* If we fail to fragment the packet */ + if (unlikely (len2 < 0)){ + print_err("len2= %d\n", len2); + return 0; + } + } + if(len2 > 1){ + for (i = len; i < len + len2; i ++) { + struct rte_mbuf *m; + m = loc_tx_mbufs.m_table[i]; + struct rte_ether_hdr *eth_hdr = (struct rte_ether_hdr *) + rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr)); + if (eth_hdr == NULL) { + rte_panic("No headroom in mbuf.\n"); + } + } + } + + len += len2; + if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM)) { + rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n"); + } + loc_tx_mbufs.len = len; + } /* while(section) */ + + /* Transmit packets */ + xran_send_burst(p_xran_dev_ctx, &loc_tx_mbufs, vf_id); + loc_tx_mbufs.len = 0; + retval = 1; + } + + return retval; +} + +//#define TRANSMIT_BURST +//#define ENABLE_DEBUG_COREDUMP + +#define ETHER_TYPE_ECPRI_BE (0xFEAE) + +int32_t xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, + uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, + uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db) +{ + uint8_t seq_id = 0; + int32_t cc_id = 0, ant_id = 0; + char* ext_buff = NULL; + uint16_t ext_buff_len = 0; + rte_iova_t ext_buff_iova = 0; + char* pos = NULL; + char* p_sec_iq = NULL; + void* mb = NULL, *mb_base = NULL; + struct rte_mbuf* to_free_mbuf = NULL; + uint16_t iq_sample_size_bits = 16; + uint32_t next = 0; + int32_t num_sections = 0, total_sections = 0; + uint16_t len = 0, len2 = 0, len_frag = 0; + char* pStart = 0; + uint16_t cid = 0; + uint8_t compMeth = 0; + uint8_t iqWidth = 0; + int parm_size = 0; + int32_t n_bytes = 0, elm_bytes = 0; + uint16_t section_id; + uint16_t prb_num = 0; + uint16_t prb_start = 0; + int16_t nPktSize = 0; + uint16_t ecpri_payl_size = 0; +#ifdef TRANSMIT_BURST + struct mbuf_table loc_tx_mbufs; +#endif + struct mbuf_table loc_tx_mbufs_fragmented; + struct xran_up_pkt_gen_params xp; + struct xran_ethdi_ctx* eth_ctx = xran_ethdi_get_ctx(); + struct xran_section_info* sectinfo = NULL; + struct xran_device_ctx* p_xran_dev_ctx = (struct xran_device_ctx*)pHandle; + uint16_t vf_id = 0; + struct rte_mbuf_ext_shared_info* p_share_data = NULL; + struct xran_sectioninfo_db* ptr_sect_elm = NULL; + struct rte_mbuf* mb_oran_hdr_ext = NULL; + struct rte_mempool_objhdr* iova_hdr = NULL; + struct xran_eaxcid_config* conf = &(p_xran_dev_ctx->eAxc_id_cfg); + struct rte_ether_hdr* ether_hdr = NULL; + struct xran_ecpri_hdr* ecpri_hdr = NULL; + struct radio_app_common_hdr* app_hdr = NULL; + struct data_section_hdr* section_hdr = NULL; + struct data_section_compression_hdr* compression_hdr = NULL; + const int16_t ccid_pos = conf->bit_ccId; + const int16_t ccid_mask = conf->mask_ccId; + const int16_t antid_pos = conf->bit_ruPortId; + const int16_t antid_mask = conf->mask_ruPortId; + + const int16_t rte_ether_hdr_size = sizeof(struct rte_ether_hdr); + const int16_t rte_mempool_objhdr_size = sizeof(struct rte_mempool_objhdr); + uint16_t comp_head_upd = 0; + + const int16_t total_header_size = (RTE_PKTMBUF_HEADROOM + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr)); + + uint16_t* __restrict pSrc = NULL; + uint16_t* __restrict pDst = NULL; + + const enum xran_input_byte_order iq_buf_byte_order = p_xran_dev_ctx->fh_cfg.ru_conf.byteOrder; + + /* radio app header */ + xp.app_params.data_feature.value = 0x10; + xp.app_params.data_feature.data_direction = direction; + xp.app_params.frame_id = frame_id; + xp.app_params.sf_slot_sym.subframe_id = subframe_id; + xp.app_params.sf_slot_sym.slot_id = slot_id; + xp.app_params.sf_slot_sym.symb_id = sym_id; + /* convert to network byte order */ + xp.app_params.sf_slot_sym.value = rte_cpu_to_be_16(xp.app_params.sf_slot_sym.value); + + + for (cc_id = 0; cc_id < num_cc; cc_id++) + { + for (ant_id = 0; ant_id < num_ant; ant_id++) + { + ptr_sect_elm = p_sec_db->p_sectiondb_elm[ctx_id][direction][cc_id][ant_id]; + if (unlikely(ptr_sect_elm == NULL)) + return (0); + num_sections = ptr_sect_elm->cur_index; + + /* iterate C-Plane configuration to generate corresponding U-Plane */ + vf_id = p_xran_dev_ctx->map2vf[direction][cc_id][ant_id][XRAN_UP_VF]; + pos = (char*)p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pData; + mb_base = p_xran_dev_ctx->sFrontHaulTxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id].sBufferList.pBuffers[sym_id].pCtrl; + if (unlikely(mb_base == NULL)) + { + rte_panic("mb == NULL\n"); + } + + cid = ((cc_id << ccid_pos) & ccid_mask) | ((ant_id << antid_pos) & antid_mask); + cid = rte_cpu_to_be_16(cid); + iq_sample_size_bits = 16; + +#ifdef TRANSMIT_BURST + loc_tx_mbufs.len = 0; +#endif + loc_tx_mbufs_fragmented.len = 0; + len_frag = 0; +#pragma loop_count min=1, max=16 + for (next=0; next< num_sections; next++) + { + sectinfo = &ptr_sect_elm->list[next]; + + if (unlikely(sectinfo == NULL)) + break; + if (unlikely(sectinfo->type != XRAN_CP_SECTIONTYPE_1)) + { /* only supports type 1 */ + print_err("Invalid section type in section DB - %d", sectinfo->type); + continue; + } + /* skip, if not scheduled */ + if (unlikely(sym_id < sectinfo->startSymId || sym_id >= sectinfo->startSymId + sectinfo->numSymbol)) + continue; + + compMeth = sectinfo->compMeth; + iqWidth = sectinfo->iqWidth; + section_id = sectinfo->id; + prb_start = sectinfo->startPrbc; + prb_num = sectinfo->numPrbc; + seq_id = xran_updl_seq_id_num[xran_port_id][cc_id][ant_id]++; + len2 = 0; + + if (compMeth) + iq_sample_size_bits = iqWidth; + + comp_head_upd = ((compMeth != XRAN_COMPMETHOD_NONE) && (compType == XRAN_COMP_HDR_TYPE_DYNAMIC)); + + print_dbg(">>> sym %2d [%d] type%d id %d startPrbc=%d numPrbc=%d startSymId=%d numSymbol=%d\n", sym_id, next, + sectinfo->type, sectinfo->id, sectinfo->startPrbc, + sectinfo->numPrbc, sectinfo->startSymId, sectinfo->numSymbol); + + p_share_data = &p_xran_dev_ctx->share_data.sh_data[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][section_id]; + p_share_data->free_cb = extbuf_free_callback; + p_share_data->fcb_opaque = NULL; + rte_mbuf_ext_refcnt_set(p_share_data, 1); + +#ifdef TRANSMIT_BURST + len = loc_tx_mbufs.len; + //Added for Klocworks + if (unlikely(len >= MBUF_TABLE_SIZE)) + { + len = MBUF_TABLE_SIZE - 1; + rte_panic("len >= MBUF_TABLE_SIZE\n"); + } +#endif + p_sec_iq = ((char*)pos + sectinfo->sec_desc[sym_id].iq_buffer_offset); + ext_buff_len = sectinfo->sec_desc[sym_id].iq_buffer_len; + + ext_buff = p_sec_iq - total_header_size; + ext_buff_len += (total_header_size + 18); + + if (comp_head_upd) + { + ext_buff -= sizeof(struct data_section_compression_hdr); + ext_buff_len += sizeof(struct data_section_compression_hdr); + } + + mb_oran_hdr_ext = rte_pktmbuf_alloc(_eth_mbuf_pool_vf_small[vf_id]); + if (unlikely((mb_oran_hdr_ext) == NULL)) + { + rte_panic("[core %d]Failed rte_pktmbuf_alloc on vf %d\n", rte_lcore_id(), vf_id); + } + + iova_hdr = (struct rte_mempool_objhdr*)RTE_PTR_SUB(mb_base, rte_mempool_objhdr_size); + ext_buff_iova = iova_hdr->iova; + +#ifdef ENABLE_DEBUG_COREDUMP + if (unlikely(ext_buff_iova == 0)) + { + rte_panic("Failed rte_mem_virt2iova\n"); + } + if (unlikely(((rte_iova_t)ext_buff_iova) == RTE_BAD_IOVA)) + { + rte_panic("Failed rte_mem_virt2iova RTE_BAD_IOVA \n"); + } +#endif + mb_oran_hdr_ext->buf_addr = ext_buff; + mb_oran_hdr_ext->buf_iova = ext_buff_iova + RTE_PTR_DIFF(ext_buff, mb_base); + mb_oran_hdr_ext->buf_len = ext_buff_len; + mb_oran_hdr_ext->ol_flags |= EXT_ATTACHED_MBUF; + mb_oran_hdr_ext->shinfo = p_share_data; + mb_oran_hdr_ext->data_off = (uint16_t)RTE_MIN((uint16_t)RTE_PKTMBUF_HEADROOM, (uint16_t)mb_oran_hdr_ext->buf_len) - rte_ether_hdr_size; + mb_oran_hdr_ext->data_len = (uint16_t)(mb_oran_hdr_ext->data_len + rte_ether_hdr_size); + mb_oran_hdr_ext->pkt_len = mb_oran_hdr_ext->pkt_len + rte_ether_hdr_size; + mb_oran_hdr_ext->port = eth_ctx->io_cfg.port[vf_id]; + + mb = (void*)mb_oran_hdr_ext; + + to_free_mbuf = p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id]; + p_xran_dev_ctx->to_free_mbuf[tti % XRAN_N_FE_BUF_LEN][cc_id][ant_id][sym_id][section_id] = mb; + rte_pktmbuf_refcnt_update(mb, 1); /* make sure eth won't free our mbuf */ + if (to_free_mbuf) + { + rte_pktmbuf_free(to_free_mbuf); + } + + pStart = (char*)((char*)mb_oran_hdr_ext->buf_addr + mb_oran_hdr_ext->data_off); + + ether_hdr = (struct rte_ether_hdr*)pStart; + + /* Fill in the ethernet header. */ +#ifndef TRANSMIT_BURST + rte_eth_macaddr_get(mb_oran_hdr_ext->port, ðer_hdr->s_addr); /* set source addr */ + ether_hdr->d_addr = eth_ctx->entities[vf_id][ID_O_RU]; /* set dst addr */ + ether_hdr->ether_type = ETHER_TYPE_ECPRI_BE; /* ethertype */ +#endif + iqWidth = (iqWidth == 0) ? 16 : iqWidth; + switch (compMeth) + { + case XRAN_COMPMETHOD_BLKFLOAT: parm_size = 1; break; + case XRAN_COMPMETHOD_MODULATION: parm_size = 0; break; + default: + parm_size = 0; + } + n_bytes = (3 * iqWidth + parm_size) * prb_num; + n_bytes = RTE_MIN(n_bytes, XRAN_MAX_MBUF_LEN); + + nPktSize = sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr) + + n_bytes; + + if (comp_head_upd) + nPktSize += sizeof(struct data_section_compression_hdr); + + xp.sec_hdr.fields.sect_id = section_id; + xp.sec_hdr.fields.num_prbu = (uint8_t)XRAN_CONVERT_NUMPRBC(prb_num); + xp.sec_hdr.fields.start_prbu = (uint8_t)prb_start; + xp.sec_hdr.fields.sym_inc = 0; + xp.sec_hdr.fields.rb = 0; + /* network byte order */ + xp.sec_hdr.fields.all_bits = rte_cpu_to_be_32(xp.sec_hdr.fields.all_bits); + + /* compression */ + xp.compr_hdr_param.ud_comp_hdr.ud_comp_meth = compMeth; + xp.compr_hdr_param.ud_comp_hdr.ud_iq_width = XRAN_CONVERT_IQWIDTH(iqWidth); + xp.compr_hdr_param.rsrvd = 0; + + ecpri_hdr = (struct xran_ecpri_hdr*)(pStart + sizeof(struct rte_ether_hdr)); + + ecpri_payl_size = n_bytes + + sizeof(struct data_section_hdr) + + sizeof(struct radio_app_common_hdr) + + XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size(); + + if (comp_head_upd) + ecpri_payl_size += sizeof(struct data_section_compression_hdr); + + ecpri_hdr->cmnhdr.data.data_num_1 = 0x0; + ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER; + ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ECPRI_IQ_DATA; + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(ecpri_payl_size); + + /* one to one lls-CU to RU only and band sector is the same */ + ecpri_hdr->ecpri_xtc_id = cid; + + /* no transport layer fragmentation supported */ + ecpri_hdr->ecpri_seq_id.data.data_num_1 = 0x8000; + ecpri_hdr->ecpri_seq_id.bits.seq_id = seq_id; + + pSrc = (uint16_t*)&(xp.app_params); + pDst = (uint16_t*)(pStart + sizeof(struct rte_ether_hdr) + sizeof(struct xran_ecpri_hdr)); + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + *pDst++ = *pSrc++; + if (comp_head_upd) + { + *pDst++ = *pSrc++; + } + + rte_pktmbuf_pkt_len(mb_oran_hdr_ext) = nPktSize; + rte_pktmbuf_data_len(mb_oran_hdr_ext) = nPktSize; + + elm_bytes += nPktSize; + + /* Restore fragmentation support in this code version */ + /* if we don't need to do any fragmentation */ + if (likely(p_xran_dev_ctx->fh_init.mtu >= sectinfo->numPrbc * (3 * iq_sample_size_bits + 1))) + { + /* no fragmentation */ + len2 = 1; +#ifdef TRANSMIT_BURST + loc_tx_mbufs.m_table[len++] = mb; + if (unlikely(len > XRAN_MAX_PKT_BURST_PER_SYM)) + { + rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n"); + } + loc_tx_mbufs.len = len; +#else + xran_enqueue_mbuf(mb_oran_hdr_ext, eth_ctx->tx_ring[vf_id]); +#endif + } + else + { + /* fragmentation */ + /* only burst transmission mode is supported for fragmented packets*/ + uint8_t* p_seq_num = &xran_updl_seq_id_num[xran_port_id][cc_id][ant_id]; + (*p_seq_num)--; + + len2 = xran_app_fragment_packet(mb_oran_hdr_ext, + &loc_tx_mbufs_fragmented.m_table[len_frag], + (uint16_t)(MBUF_TABLE_SIZE - len_frag), + p_xran_dev_ctx->fh_init.mtu, + p_xran_dev_ctx->direct_pool, + p_xran_dev_ctx->indirect_pool, + prb_start, + prb_num, + p_seq_num, + iqWidth, + ((iqWidth == 16) || (compType == XRAN_COMP_HDR_TYPE_STATIC)) ? 0 : 1); + + /* Free input packet */ + rte_pktmbuf_free(mb_oran_hdr_ext); + + /* If we fail to fragment the packet */ + if (unlikely(len2 < 0)) + { + print_err("len2= %d\n", len2); + continue; + } + if (unlikely(len2 > 1)) + { + for (int32_t i = len_frag; i < len_frag + len2; i++) + { + struct rte_mbuf* m; + m = loc_tx_mbufs_fragmented.m_table[i]; + struct rte_ether_hdr* eth_hdr = (struct rte_ether_hdr*) + rte_pktmbuf_prepend(m, (uint16_t)sizeof(struct rte_ether_hdr)); + if (eth_hdr == NULL) + { + rte_panic("No headroom in mbuf.\n"); + } + } + } + + len_frag += len2; + if (unlikely(len_frag > XRAN_MAX_PKT_BURST_PER_SYM)) { + rte_panic("XRAN_MAX_PKT_BURST_PER_SYM\n"); + } + loc_tx_mbufs_fragmented.len = len_frag; + } + } /* section loop */ + total_sections += num_sections; + + /* Transmit packets */ +#ifdef TRANSMIT_BURST + if (loc_tx_mbufs.len) + { + for (int32_t i = 0; i < loc_tx_mbufs.len; i++) + { + p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs.m_table[i], ETHER_TYPE_ECPRI, vf_id); + } + loc_tx_mbufs.len = 0; + } +#endif + /* Transmit fragmented packets */ + if (unlikely(loc_tx_mbufs_fragmented.len)) + { + for (int32_t i = 0; i < loc_tx_mbufs_fragmented.len; i++) + { + p_xran_dev_ctx->send_upmbuf2ring(loc_tx_mbufs_fragmented.m_table[i], ETHER_TYPE_ECPRI, vf_id); + } + loc_tx_mbufs_fragmented.len = 0; + } + } /* for(cc_id = 0; cc_id < num_CCPorts; cc_id++) */ + } /* for(ant_id = 0; ant_id < num_eAxc; ant_id++) */ + + struct xran_common_counters* pCnt = &p_xran_dev_ctx->fh_counters; + pCnt->tx_counter += total_sections; + pCnt->tx_bytes_counter += elm_bytes; + + return 1; +} + + +int32_t xran_process_tx_sym(void *arg) +{ + int32_t retval = 0; + uint32_t tti=0; + uint32_t numSlotMu1 = 5; +#if XRAN_MLOG_VAR + uint32_t mlogVar[15]; + uint32_t mlogVarCnt = 0; +#endif + unsigned long t1 = MLogTick(); + + void *pHandle = NULL; + int32_t ant_id = 0; + int32_t cc_id = 0; + uint8_t num_eAxc = 0; + uint8_t num_eAxAntElm = 0; + uint8_t num_CCPorts = 0; + uint32_t frame_id = 0; + uint32_t subframe_id = 0; + uint32_t slot_id = 0; + uint32_t sym_id = 0; + uint32_t sym_idx = 0; + + uint8_t ctx_id; + struct xran_device_ctx * p_xran_dev_ctx = (struct xran_device_ctx *) arg; + enum xran_in_period inPeriod; + uint32_t interval = p_xran_dev_ctx->interval_us_local; + uint8_t PortId = p_xran_dev_ctx->xran_port_id; + + if(p_xran_dev_ctx->xran2phy_mem_ready == 0) + return 0; + + pHandle = p_xran_dev_ctx; + + /* O-RU: send symb after OTA time with delay (UL) */ + /* O-DU: send symb in advance of OTA time (DL) */ + sym_idx = XranOffsetSym(p_xran_dev_ctx->sym_up, xran_lib_ota_sym_idx[PortId], XRAN_NUM_OF_SYMBOL_PER_SLOT*SLOTNUM_PER_SUBFRAME(interval)*1000, &inPeriod); + + tti = XranGetTtiNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); + slot_id = XranGetSlotNum(tti, SLOTNUM_PER_SUBFRAME(interval)); + subframe_id = XranGetSubFrameNum(tti,SLOTNUM_PER_SUBFRAME(interval), SUBFRAMES_PER_SYSTEMFRAME); + + uint16_t sfnSecStart = xran_getSfnSecStart(); + if (unlikely(inPeriod == XRAN_IN_NEXT_PERIOD)) + { + // For DU + sfnSecStart = (sfnSecStart + NUM_OF_FRAMES_PER_SECOND) & 0x3ff; + } + else if (unlikely(inPeriod == XRAN_IN_PREV_PERIOD)) + { + // For RU + if (sfnSecStart >= NUM_OF_FRAMES_PER_SECOND) + { + sfnSecStart -= NUM_OF_FRAMES_PER_SECOND; + } + else + { + sfnSecStart += NUM_OF_FRAMES_PER_SFN_PERIOD - NUM_OF_FRAMES_PER_SECOND; + } + } + frame_id = XranGetFrameNum(tti,sfnSecStart,SUBFRAMES_PER_SYSTEMFRAME, SLOTNUM_PER_SUBFRAME(interval)); + // ORAN frameId, 8 bits, [0, 255] + frame_id = (frame_id & 0xff); + + sym_id = XranGetSymNum(sym_idx, XRAN_NUM_OF_SYMBOL_PER_SLOT); + ctx_id = XranGetSlotNum(tti, SLOTS_PER_SYSTEMFRAME(interval)) % XRAN_MAX_SECTIONDB_CTX; + + print_dbg("[%d]SFN %d sf %d slot %d\n", tti, frame_id, subframe_id, slot_id); + +#if XRAN_MLOG_VAR + mlogVar[mlogVarCnt++] = 0xAAAAAAAA; + mlogVar[mlogVarCnt++] = xran_lib_ota_sym_idx[PortId]; + mlogVar[mlogVarCnt++] = sym_idx; + mlogVar[mlogVarCnt++] = abs(p_xran_dev_ctx->sym_up); + mlogVar[mlogVarCnt++] = tti; + mlogVar[mlogVarCnt++] = frame_id; + mlogVar[mlogVarCnt++] = subframe_id; + mlogVar[mlogVarCnt++] = slot_id; + mlogVar[mlogVarCnt++] = sym_id; + mlogVar[mlogVarCnt++] = PortId; + MLogAddVariables(mlogVarCnt, mlogVar, MLogTick()); +#endif + + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B) { + num_eAxc = xran_get_num_eAxcUl(pHandle); + } else { + num_eAxc = xran_get_num_eAxc(pHandle); + } + + num_CCPorts = xran_get_num_cc(pHandle); + + /* U-Plane */ + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_DU && p_xran_dev_ctx->enableCP) + { + if(p_xran_dev_ctx->tx_sym_gen_func) { + enum xran_comp_hdr_type compType; + enum xran_pkt_dir direction; + uint32_t prb_num, loc_ret = 1; + uint16_t xran_port_id; + PSECTION_DB_TYPE p_sec_db = NULL; + + compType = p_xran_dev_ctx->fh_cfg.ru_conf.xranCompHdrType; + + if (p_xran_dev_ctx->fh_init.io_cfg.id == O_DU) { + direction = XRAN_DIR_DL; /* O-DU */ + prb_num = p_xran_dev_ctx->fh_cfg.nDLRBs; + } + else { + direction = XRAN_DIR_UL; /* RU */ + prb_num = p_xran_dev_ctx->fh_cfg.nULRBs; + } + + if (unlikely(p_xran_dev_ctx->xran_port_id > XRAN_PORTS_NUM)) { + print_err("Invalid Port id - %d", p_xran_dev_ctx->xran_port_id); + loc_ret = 0; + } + + if (unlikely(ctx_id > XRAN_MAX_SECTIONDB_CTX)) { + print_err("Invalid Context id - %d", ctx_id); + loc_ret = 0; + } + + if (unlikely(direction > XRAN_DIR_MAX)) { + print_err("Invalid direction - %d", direction); + loc_ret = 0; + } + + if (unlikely(num_CCPorts > XRAN_COMPONENT_CARRIERS_MAX)) { + print_err("Invalid CC id - %d", num_CCPorts); + loc_ret = 0; + } + + if (unlikely(num_eAxc > (XRAN_MAX_ANTENNA_NR * 2 + XRAN_MAX_ANT_ARRAY_ELM_NR))) { + print_err("Invalid eAxC id - %d", num_eAxc); + loc_ret = 0; + } + + xran_port_id = p_xran_dev_ctx->xran_port_id; + p_sec_db = p_sectiondb[p_xran_dev_ctx->xran_port_id]; + + if (loc_ret) + { + retval = p_xran_dev_ctx->tx_sym_gen_func(pHandle, ctx_id, tti, num_CCPorts, num_eAxc, frame_id, subframe_id, slot_id, sym_id, + compType, direction, xran_port_id, p_sec_db); + } + else + { + retval = 0; + } + } + else + { + rte_panic("p_xran_dev_ctx->tx_sym_gen_func== NULL\n"); + } + } + else + { + for (ant_id = 0; ant_id < num_eAxc; ant_id++) + { + for (cc_id = 0; cc_id < num_CCPorts; cc_id++) + { + struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg); + + if(p_xran_dev_ctx->puschMaskEnable) + { + if((tti % numSlotMu1 == p_xran_dev_ctx->puschMaskSlot)) + ; + else + retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0); + } + else + retval = xran_process_tx_sym_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id, 0); + + if(p_xran_dev_ctx->enableSrs && (p_srs_cfg->symbMask & (1 << sym_id))) + { + retval = xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id); + } + } + } + } + + if(p_xran_dev_ctx->fh_init.io_cfg.id == O_RU && p_xran_dev_ctx->enableSrs && xran_get_ru_category(pHandle) == XRAN_CATEGORY_B) { + num_eAxAntElm = xran_get_num_ant_elm(pHandle); + struct xran_srs_config *p_srs_cfg = &(p_xran_dev_ctx->srs_cfg); + for(num_eAxc = 0; ant_id < num_eAxAntElm; ant_id++) { + for(cc_id = 0; cc_id < num_CCPorts; cc_id++) { + if( p_srs_cfg->symbMask & (1 << sym_id)) { + retval = xran_process_tx_srs_cp_off(pHandle, ctx_id, tti, cc_id, ant_id, frame_id, subframe_id, slot_id, sym_id); + } + } + } + } + + MLogTask(PID_DISPATCH_TX_SYM, t1, MLogTick()); + return retval; +} + +struct cp_up_tx_desc * +xran_pkt_gen_desc_alloc(void) +{ + struct rte_mbuf * mb = rte_pktmbuf_alloc(_eth_mbuf_pkt_gen); + struct cp_up_tx_desc * p_desc = NULL; + char * start = NULL; + + if(mb){ + start = rte_pktmbuf_append(mb, sizeof(struct cp_up_tx_desc)); + if(start) { + p_desc = rte_pktmbuf_mtod(mb, struct cp_up_tx_desc *); + if(p_desc){ + p_desc->mb = mb; + return p_desc; + } + } + } + return p_desc; +} + +int32_t +xran_pkt_gen_desc_free(struct cp_up_tx_desc *p_desc) +{ + if (p_desc){ + if(p_desc->mb){ + rte_pktmbuf_free(p_desc->mb); + return 0; + } else { + rte_panic("p_desc->mb == NULL\n"); + } + } + return -1; +} + diff --git a/fhi_lib/lib/src/xran_tx_proc.h b/fhi_lib/lib/src/xran_tx_proc.h new file mode 100644 index 0000000..6bd84e2 --- /dev/null +++ b/fhi_lib/lib/src/xran_tx_proc.h @@ -0,0 +1,90 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +/** + * @brief XRAN TX header file + * @file xran_tx_proc.h + * @ingroup group_source_xran + * @author Intel Corporation + **/ + +#ifndef _XRAN_TX_PROC_H_ +#define _XRAN_TX_PROC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include +#include +#include + +#include "xran_fh_o_du.h" +#include "xran_prach_cfg.h" +#include "xran_up_api.h" +#include "xran_cp_api.h" + +struct cp_up_tx_desc { + struct rte_mbuf * mb; + void *pHandle; + uint8_t ctx_id; + uint32_t tti; + int32_t cc_id; + int32_t ant_id; + uint32_t frame_id; + uint32_t subframe_id; + uint32_t slot_id; + uint32_t sym_id; + uint32_t compType; + uint32_t direction; + uint16_t xran_port_id; + void *p_sec_db; +}; + +int32_t xran_process_tx_sym(void *arg); + +struct cp_up_tx_desc * xran_pkt_gen_desc_alloc(void); +int32_t xran_pkt_gen_desc_free(struct cp_up_tx_desc *p_desc); +uint16_t xran_getSfnSecStart(void); + +int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id); +int32_t xran_process_tx_sym_cp_on(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id); +int32_t xran_process_tx_sym_cp_on_dispatch(void *pHandle, uint8_t ctx_id, uint32_t tti, int32_t cc_id, int32_t ant_id, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id); +int32_t xran_process_tx_sym_cp_on_dispatch_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, + uint32_t subframe_id, uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, + uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db); + +int32_t xran_process_tx_sym_cp_on_opt(void* pHandle, uint8_t ctx_id, uint32_t tti, int32_t num_cc, int32_t num_ant, uint32_t frame_id, uint32_t subframe_id, + uint32_t slot_id, uint32_t sym_id, enum xran_comp_hdr_type compType, enum xran_pkt_dir direction, uint16_t xran_port_id, PSECTION_DB_TYPE p_sec_db); +extern int rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr* mac_addr); + +extern PSECTION_DB_TYPE p_sectiondb[XRAN_PORTS_NUM]; + +#ifdef __cplusplus +} +#endif + +#endif /* _XRAN_TX_PROC_H_ */ diff --git a/fhi_lib/lib/src/xran_ul_tables.c b/fhi_lib/lib/src/xran_ul_tables.c index 1af11c4..ae71dce 100644 --- a/fhi_lib/lib/src/xran_ul_tables.c +++ b/fhi_lib/lib/src/xran_ul_tables.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -26,7 +26,7 @@ #include #include -#include "xran_common.h" +#include "xran_prach_cfg.h" /* 3GPP 38.211-f20 Table - 6.3.3.2-2 */ const xRANPrachConfigTableStruct gxranPrachDataTable_sub6_fdd[XRAN_PRACH_CONFIG_TABLE_SIZE] = diff --git a/fhi_lib/lib/src/xran_up_api.c b/fhi_lib/lib/src/xran_up_api.c index a69712f..397853a 100644 --- a/fhi_lib/lib/src/xran_up_api.c +++ b/fhi_lib/lib/src/xran_up_api.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -25,8 +25,7 @@ * **/ #include - -#include +#include #include #include "xran_fh_o_du.h" @@ -36,8 +35,6 @@ #include "xran_mlog_lnx.h" #include "xran_common.h" -extern uint32_t xran_lib_ota_tti; - /** * @brief Builds eCPRI header in xRAN packet * @@ -62,30 +59,30 @@ static int build_ecpri_hdr(struct rte_mbuf *mbuf, if (NULL == ecpri_hdr) return 1; - ecpri_hdr->cmnhdr.ecpri_ver = XRAN_ECPRI_VER; - ecpri_hdr->cmnhdr.ecpri_resv = 0; - ecpri_hdr->cmnhdr.ecpri_concat = 0; - ecpri_hdr->cmnhdr.ecpri_mesg_type = ECPRI_IQ_DATA; + ecpri_hdr->cmnhdr.data.data_num_1 = 0x0; + ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER; + //ecpri_hdr->cmnhdr.bits.ecpri_resv = 0; + //ecpri_hdr->cmnhdr.bits.ecpri_concat = 0; + ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ECPRI_IQ_DATA; if (iq_data_offset + iq_samples_bytes_in_mbuf > iq_data_num_bytes) { - ecpri_hdr->cmnhdr.ecpri_payl_size = + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) + sizeof(struct data_section_hdr) + (iq_data_num_bytes - iq_data_offset) + - xran_get_ecpri_hdr_size()); - ecpri_hdr->ecpri_seq_id.e_bit = 1; /* last segment */ + XRAN_ECPRI_HDR_SZ); //xran_get_ecpri_hdr_size()); + ecpri_hdr->ecpri_seq_id.bits.e_bit = 1; /* last segment */ } else { - ecpri_hdr->cmnhdr.ecpri_payl_size = + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(sizeof(struct radio_app_common_hdr) + sizeof(struct data_section_hdr) + iq_samples_bytes_in_mbuf + - xran_get_ecpri_hdr_size()); - ecpri_hdr->ecpri_seq_id.e_bit = 0; + XRAN_ECPRI_HDR_SZ); //xran_get_ecpri_hdr_size()); + ecpri_hdr->ecpri_seq_id.bits.e_bit = 0; } -// ecpri_hdr->ecpri_xtc_id = 0; /* currently not used */ - ecpri_hdr->ecpri_seq_id.seq_id = 0; - ecpri_hdr->ecpri_seq_id.sub_seq_id = iq_data_offset / + ecpri_hdr->ecpri_xtc_id = 0; /* currently not used */ + ecpri_hdr->ecpri_seq_id.bits.sub_seq_id = iq_data_offset / iq_samples_bytes_in_mbuf; return 0; @@ -103,41 +100,43 @@ static int build_ecpri_hdr(struct rte_mbuf *mbuf, * @param comp_meth Compression method * @return int int 0 on success, non zero on failure */ -static int xran_build_ecpri_hdr_ex(struct rte_mbuf *mbuf, +static inline int xran_build_ecpri_hdr_ex(struct rte_mbuf *mbuf, uint8_t ecpri_mesg_type, int payl_size, uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id, - uint8_t comp_meth) + uint8_t comp_meth, + enum xran_comp_hdr_type staticEn) { char *pChar = rte_pktmbuf_mtod(mbuf, char*); struct xran_ecpri_hdr *ecpri_hdr = (struct xran_ecpri_hdr *)(pChar + sizeof(struct rte_ether_hdr)); uint16_t ecpri_payl_size = payl_size + sizeof(struct data_section_hdr) + sizeof(struct radio_app_common_hdr) - + xran_get_ecpri_hdr_size(); - - if (comp_meth != XRAN_COMPMETHOD_NONE) + + XRAN_ECPRI_HDR_SZ; //xran_get_ecpri_hdr_size(); + if ((comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) ecpri_payl_size += sizeof(struct data_section_compression_hdr); - if (NULL == ecpri_hdr) return 1; - ecpri_hdr->cmnhdr.ecpri_ver = XRAN_ECPRI_VER; - ecpri_hdr->cmnhdr.ecpri_resv = 0; // should be zero - ecpri_hdr->cmnhdr.ecpri_concat = 0; - ecpri_hdr->cmnhdr.ecpri_mesg_type = ecpri_mesg_type; - ecpri_hdr->cmnhdr.ecpri_payl_size = rte_cpu_to_be_16(ecpri_payl_size); + ecpri_hdr->cmnhdr.data.data_num_1 = 0x0; + ecpri_hdr->cmnhdr.bits.ecpri_ver = XRAN_ECPRI_VER; + //ecpri_hdr->cmnhdr.bits.ecpri_resv = 0; // should be zero + //ecpri_hdr->cmnhdr.bits.ecpri_concat = 0; + ecpri_hdr->cmnhdr.bits.ecpri_mesg_type = ecpri_mesg_type; + ecpri_hdr->cmnhdr.bits.ecpri_payl_size = rte_cpu_to_be_16(ecpri_payl_size); /* one to one lls-CU to RU only and band sector is the same */ ecpri_hdr->ecpri_xtc_id = xran_compose_cid(0, 0, CC_ID, Ant_ID); - ecpri_hdr->ecpri_seq_id.seq_id = seq_id; + /* no transport layer fragmentation supported */ + ecpri_hdr->ecpri_seq_id.data.data_num_1 = 0x8000; + ecpri_hdr->ecpri_seq_id.bits.seq_id = seq_id; /* no transport layer fragmentation supported */ - ecpri_hdr->ecpri_seq_id.sub_seq_id = 0; - ecpri_hdr->ecpri_seq_id.e_bit = 1; + //ecpri_hdr->ecpri_seq_id.sub_seq_id = 0; + //ecpri_hdr->ecpri_seq_id.e_bit = 1; return 0; } @@ -151,7 +150,7 @@ static int xran_build_ecpri_hdr_ex(struct rte_mbuf *mbuf, * packet. * @return int 0 on success, non zero on failure */ -static int build_application_layer( +static inline int build_application_layer( struct rte_mbuf *mbuf, const struct radio_app_common_hdr *app_hdr_input) { @@ -162,7 +161,7 @@ static int build_application_layer( if (NULL == app_hdr) return 1; - rte_memcpy(app_hdr, app_hdr_input, sizeof(struct radio_app_common_hdr)); + memcpy(app_hdr, app_hdr_input, sizeof(struct radio_app_common_hdr)); return 0; } @@ -174,7 +173,7 @@ static int build_application_layer( * @param sec_hdr Section header structure to be set in mbuf packet * @return int 0 on success, non zero on failure */ -static int build_section_hdr( +static inline int build_section_hdr( struct rte_mbuf *mbuf, const struct data_section_hdr *sec_hdr) { @@ -185,7 +184,7 @@ static int build_section_hdr( if (NULL == section_hdr) return 1; - rte_memcpy(section_hdr, sec_hdr, sizeof(struct data_section_hdr)); + memcpy(section_hdr, sec_hdr, sizeof(struct data_section_hdr)); return 0; } @@ -198,18 +197,18 @@ static int build_section_hdr( * @param iq_data_offset IQ data btyes already sent. * @return uint16_t Bytes that have been appended to the packet. */ -static uint16_t append_iq_samples_ex( +static inline uint16_t append_iq_samples_ex( struct rte_mbuf *mbuf, + int iq_sam_offset, const void *iq_data_start, const uint32_t iq_data_num_bytes, enum xran_input_byte_order iq_buf_byte_order, uint32_t do_copy) { char *pChar = rte_pktmbuf_mtod(mbuf, char*); - void *iq_sam_buf = (pChar + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) - + sizeof(struct radio_app_common_hdr) - + sizeof(struct data_section_hdr)); + void *iq_sam_buf; + iq_sam_buf = (pChar + iq_sam_offset); if (iq_sam_buf == NULL){ print_err("iq_sam_buf == NULL\n"); return 0; @@ -226,7 +225,7 @@ static uint16_t append_iq_samples_ex( else if(iq_buf_byte_order == XRAN_NE_BE_BYTE_ORDER){ if(do_copy) { - rte_memcpy(iq_sam_buf, (uint8_t *)iq_data_start, iq_data_num_bytes); + memcpy(iq_sam_buf, (uint8_t *)iq_data_start, iq_data_num_bytes); } } @@ -262,7 +261,7 @@ static uint16_t append_iq_samples( void *iq_sam_buf = (void *)rte_pktmbuf_append(mbuf, iq_bytes_to_send); - rte_memcpy(iq_sam_buf, (uint8_t *)iq_data_start + iq_data_offset, + memcpy(iq_sam_buf, (uint8_t *)iq_data_start + iq_data_offset, iq_bytes_to_send); return iq_bytes_to_send; @@ -276,7 +275,7 @@ static uint16_t append_iq_samples( * to be set in mbuf packet * @return int 0 on success, non zero on failure */ -static int build_compression_hdr( +static inline int build_compression_hdr( struct rte_mbuf *mbuf, const struct data_section_compression_hdr *compr_hdr) { @@ -288,7 +287,7 @@ static int build_compression_hdr( if (NULL == compression_hdr) return 1; - rte_memcpy(compression_hdr, compr_hdr, sizeof(*compression_hdr)); + memcpy(compression_hdr, compr_hdr, sizeof(*compression_hdr)); return 0; } @@ -308,7 +307,7 @@ static int append_comp_param(struct rte_mbuf *mbuf, union compression_params *ud if (NULL == compr_param) return 1; - rte_memcpy(compr_param, ud_comp_param, sizeof(union compression_params)); + memcpy(compr_param, ud_comp_param, sizeof(union compression_params)); return 0; } @@ -330,13 +329,14 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, uint8_t *subframe_id, uint8_t *slot_id, uint8_t *symb_id, - struct ecpri_seq_id *seq_id, + union ecpri_seq_id *seq_id, uint16_t *num_prbu, uint16_t *start_prbu, uint16_t *sym_inc, uint16_t *rb, uint16_t *sect_id, int8_t expect_comp, + enum xran_comp_hdr_type staticComp, uint8_t *compMeth, uint8_t *iqWidth) { @@ -359,10 +359,13 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, if (seq_id) *seq_id = ecpri_hdr->ecpri_seq_id; + if(*CC_ID == 0xFF && *Ant_ID == 0xFF) { + /* if not classified vi HW Queue parse packet */ xran_decompose_cid((uint16_t)ecpri_hdr->ecpri_xtc_id, &result); *CC_ID = result.ccId; *Ant_ID = result.ruPortId; + } /* Process radio header. */ struct radio_app_common_hdr *radio_hdr = @@ -400,7 +403,10 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, *sect_id = data_hdr->fields.sect_id; if(expect_comp) { - const struct data_section_compression_hdr *data_compr_hdr = + const struct data_section_compression_hdr *data_compr_hdr; + if (staticComp != XRAN_COMP_HDR_TYPE_STATIC) + { + data_compr_hdr = (void *) rte_pktmbuf_adj(mbuf, sizeof(*data_hdr)); if (data_compr_hdr == NULL) @@ -408,11 +414,17 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, *compMeth = data_compr_hdr->ud_comp_hdr.ud_comp_meth; *iqWidth = data_compr_hdr->ud_comp_hdr.ud_iq_width; - const uint8_t *compr_param = (void *)rte_pktmbuf_adj(mbuf, sizeof(*data_compr_hdr)); *iq_data_start = (void *)compr_param; /*rte_pktmbuf_adj(mbuf, sizeof(*compr_param))*/; + } + else + { + *iq_data_start = rte_pktmbuf_adj(mbuf, sizeof(*data_hdr)); + } + + } else { *iq_data_start = rte_pktmbuf_adj(mbuf, sizeof(*data_hdr)); } @@ -422,7 +434,6 @@ int32_t xran_extract_iq_samples(struct rte_mbuf *mbuf, #if XRAN_MLOG_VAR mlogVar[mlogVarCnt++] = 0xBBBBBBBB; - mlogVar[mlogVarCnt++] = xran_lib_ota_tti; mlogVar[mlogVarCnt++] = radio_hdr->frame_id; mlogVar[mlogVarCnt++] = radio_hdr->sf_slot_sym.subframe_id; mlogVar[mlogVarCnt++] = radio_hdr->sf_slot_sym.slot_id; @@ -459,15 +470,19 @@ int32_t xran_prepare_iq_symbol_portion( uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id, + enum xran_comp_hdr_type staticEn, uint32_t do_copy) { + int offset; + if(xran_build_ecpri_hdr_ex(mbuf, ECPRI_IQ_DATA, iq_data_num_bytes, CC_ID, Ant_ID, seq_id, - params->compr_hdr_param.ud_comp_hdr.ud_comp_meth)){ + params->compr_hdr_param.ud_comp_hdr.ud_comp_meth, + staticEn)){ print_err("xran_build_ecpri_hdr_ex return 0\n"); return 0; } @@ -482,18 +497,15 @@ int32_t xran_prepare_iq_symbol_portion( return 0; } - - if(params->compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE) { + offset = sizeof(struct rte_ether_hdr) + + sizeof(struct xran_ecpri_hdr) + + sizeof(struct radio_app_common_hdr) + + sizeof(struct data_section_hdr); + if ((params->compr_hdr_param.ud_comp_hdr.ud_comp_meth != XRAN_COMPMETHOD_NONE)&&(staticEn == XRAN_COMP_HDR_TYPE_DYNAMIC)) { if (build_compression_hdr(mbuf, &(params->compr_hdr_param)) !=0) return 0; - - /* payload expected to start with udCompParam */ - - /*if(append_comp_param(mbuf, &(params->compr_param)) !=0) - return 0;*/ + offset += sizeof(struct data_section_compression_hdr); } - - - return append_iq_samples_ex(mbuf, iq_data_start, iq_data_num_bytes, iq_buf_byte_order, do_copy); + return (do_copy ? append_iq_samples_ex(mbuf, offset, iq_data_start, iq_data_num_bytes, iq_buf_byte_order, do_copy) : iq_data_num_bytes); } diff --git a/fhi_lib/test/common/common.cpp b/fhi_lib/test/common/common.cpp index 82fb28e..3150c8e 100644 --- a/fhi_lib/test/common/common.cpp +++ b/fhi_lib/test/common/common.cpp @@ -1,6 +1,19 @@ /******************************************************************************* * - * + * Copyright (c) 2020 Intel. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * *******************************************************************************/ diff --git a/fhi_lib/test/common/common.hpp b/fhi_lib/test/common/common.hpp index 9b01b06..1efbd87 100644 --- a/fhi_lib/test/common/common.hpp +++ b/fhi_lib/test/common/common.hpp @@ -1,6 +1,19 @@ /******************************************************************************* * - * + * Copyright (c) 2020 Intel. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * *******************************************************************************/ diff --git a/fhi_lib/test/common/common_typedef_xran.h b/fhi_lib/test/common/common_typedef_xran.h index 9e84bd3..d4616f3 100644 --- a/fhi_lib/test/common/common_typedef_xran.h +++ b/fhi_lib/test/common/common_typedef_xran.h @@ -1,6 +1,19 @@ /******************************************************************************* * -* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* * *******************************************************************************/ /*! \file common_typedef_xran.h diff --git a/fhi_lib/test/common/xran_lib_wrap.hpp b/fhi_lib/test/common/xran_lib_wrap.hpp index c92abc7..2829ebd 100644 --- a/fhi_lib/test/common/xran_lib_wrap.hpp +++ b/fhi_lib/test/common/xran_lib_wrap.hpp @@ -1,6 +1,19 @@ /******************************************************************************* * - * + * Copyright (c) 2020 Intel. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * *******************************************************************************/ @@ -42,14 +55,15 @@ extern "C" { -extern uint32_t xran_lib_ota_tti; -extern uint32_t xran_lib_ota_sym; -extern uint32_t xran_lib_ota_sym_idx; +extern uint32_t xran_lib_ota_tti[]; +extern uint32_t xran_lib_ota_sym[]; +extern uint32_t xran_lib_ota_sym_idx[]; void sym_ota_cb(struct rte_timer *tim, void *arg); void tti_ota_cb(struct rte_timer *tim, void *arg); } + class xranLibWraper { public: @@ -65,6 +79,55 @@ public: MAX_SW_XRAN_INTERFACE_NUM } SWXRANInterfaceTypeEnum; +struct xran_io_buf_ctrl { + /* -1-this subframe is not used in current frame format + 0-this subframe can be transmitted, i.e., data is ready + 1-this subframe is waiting transmission, i.e., data is not ready + 10 - DL transmission missing deadline. When FE needs this subframe data but bValid is still 1, + set bValid to 10. + */ + int32_t bValid ; // when UL rx, it is subframe index. + int32_t nSegToBeGen; + int32_t nSegGenerated; // how many date segment are generated by DL LTE processing or received from FE + // -1 means that DL packet to be transmitted is not ready in BS + int32_t nSegTransferred; // number of data segments has been transmitted or received + //struct rte_mbuf *pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK allocated memory pool + struct xran_buffer_list sBufferList; +}; + +struct xran_io_shared_ctrl { + /* io struct */ + struct xran_io_buf_ctrl sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_io_buf_ctrl sFHPrachRxBbuIoBufCtrlDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + + /* Cat B */ + struct xran_io_buf_ctrl sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + struct xran_io_buf_ctrl sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; + + /* buffers lists */ + struct xran_flat_buffer sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_flat_buffer sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; + struct xran_flat_buffer sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHPrachRxBuffersDecomp[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; + + /* Cat B SRS buffers */ + struct xran_flat_buffer sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; + struct xran_flat_buffer sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; +}; + +struct bbu_xran_io_if { + void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /* instance per ORAN port */ + uint32_t nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; /* every api owns unique buffer pool */ + uint16_t nInstanceNum[XRAN_PORTS_NUM]; + struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU port */ +}; + enum nChBw { PHY_BW_5MHZ = 5, PHY_BW_10MHZ = 10, PHY_BW_15MHZ = 15, @@ -91,7 +154,6 @@ public: { 32, 66, 132, 264 } // Numerology 3 (120KHz) }; - protected: char argv[25] = "unittest"; @@ -111,28 +173,7 @@ protected: uint32_t tti_to_process; } m_timer_ctx[MAX_NUM_OF_XRAN_CTX]; - /* io struct */ - BbuIoBufCtrlStruct m_sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct m_sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct m_sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct m_sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - BbuIoBufCtrlStruct m_sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - - /* Cat B */ - BbuIoBufCtrlStruct m_sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR]; - - /* buffers lists */ - struct xran_flat_buffer m_sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer m_sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - struct xran_flat_buffer m_sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - struct xran_flat_buffer m_sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]; - struct xran_flat_buffer m_sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]; - - /* Cat B SRS buffers */ - struct xran_flat_buffer m_sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT]; - - void *m_nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector - uint32_t m_nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]; // every api owns unique buffer pool + struct bbu_xran_io_if m_gsXranIoIf; uint32_t m_nSW_ToFpga_FTH_TxBufferLen; uint32_t m_nFpgaToSW_FTH_RxBufferLen; @@ -152,7 +193,6 @@ protected: int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]; int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]; - private: json m_global_cfg; @@ -185,10 +225,10 @@ private: return (result << shift); } - int init_memory() + int init_memory(uint32_t o_xu_id) { xran_status_t status; - int32_t i, j, k, z; + int32_t i, j, k, z, m; SWXRANInterfaceTypeEnum eInterfaceType; void *ptr; void *mb; @@ -196,6 +236,9 @@ private: uint16_t *u16dptr; uint8_t *u8dptr; + struct bbu_xran_io_if *psBbuIo = (struct bbu_xran_io_if*)&m_gsXranIoIf; + struct xran_io_shared_ctrl *psIoCtrl = (struct xran_io_shared_ctrl *)&psBbuIo->ioCtrl[o_xu_id]; + uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul()); uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr); @@ -208,26 +251,27 @@ private: } /* initialize maximum instances to have flexibility for the tests */ - int nInstanceNum = XRAN_MAX_SECTOR_NR; + /* initialize maximum supported CC to have flexibility on the test */ int32_t nSectorNum = 6;//XRAN_MAX_SECTOR_NR; - for(k = 0; k < XRAN_PORTS_NUM; k++) { - status = xran_sector_get_instances(m_xranhandle, nInstanceNum, &m_nInstanceHandle[k][0]); + k = o_xu_id; + psBbuIo->nInstanceNum[k] = nSectorNum; + status = xran_sector_get_instances(k, m_xranhandle, psBbuIo->nInstanceNum[k], &psBbuIo->nInstanceHandle[k][0]); if(status != XRAN_STATUS_SUCCESS) { - std::cout << "get sector instance failed " << k << " for XRAN nInstanceNum " << nInstanceNum << std::endl; + std::cout << "get sector instance failed " << k << " for XRAN nInstanceNum " << psBbuIo->nInstanceNum[k] << std::endl; return (-1); } - for (i = 0; i < nInstanceNum; i++) - std::cout << __func__ << " [" << k << "]: CC " << i << " handle " << m_nInstanceHandle[0][i] << std::endl; - } + for (i = 0; i < psBbuIo->nInstanceNum[k]; i++) + std::cout << __func__ << " [" << k << "]: CC " << i << " handle " << psBbuIo->nInstanceHandle[k][i] << std::endl; + std::cout << "Sucess xran_mm_init" << std::endl; /* Init Memory */ for(i = 0; inInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT, m_nSW_ToFpga_FTH_TxBufferLen); if(status != XRAN_STATUS_SUCCESS) { @@ -236,24 +280,24 @@ private: } for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) { for(z = 0; z < xran_max_antenna_nr; z++){ - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxBuffers[j][i][z][0]; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulTxBuffers[j][i][z][0]; for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) { - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nSW_ToFpga_FTH_TxBufferLen; // 14 symbols 3200bytes/symbol + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl; return (-1); } - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - m_sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; if(ptr) { u32dptr = (uint32_t*)(ptr); @@ -266,16 +310,16 @@ private: /* C-plane DL */ eInterfaceType = XRANFTHTX_SEC_DESC_OUT; - status = xran_bm_init(m_nInstanceHandle[0][i], - &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc)); + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc)); if(XRAN_STATUS_SUCCESS != status) { std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl; return (-1); } eInterfaceType = XRANFTHTX_PRB_MAP_OUT; - status = xran_bm_init(m_nInstanceHandle[0][i], - &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map)); if(status != XRAN_STATUS_SUCCESS) { @@ -284,37 +328,40 @@ private: } for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) { for(z = 0; z < xran_max_antenna_nr; z++) { - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulTxPrbMapBuffers[j][i][z]; - - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulTxPrbMapBuffers[j][i][z]; + + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; + + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl; return (-1); } - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; - m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; void *sd_ptr; void *sd_mb; int elm_id; struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map)); - for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){ + for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SLOT; elm_id++){ struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT], &sd_ptr, &sd_mb); + for(m = 0; m < XRAN_MAX_FRAGMENT; m++){ + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_OUT], &sd_ptr, &sd_mb); if(XRAN_STATUS_SUCCESS != status){ std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl; return (-1); } - pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr; + pPrbElem->p_sec_desc[k][m] = (struct xran_section_desc *)sd_ptr; + } } } } @@ -323,8 +370,8 @@ private: for(i = 0; inInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT, m_nSW_ToFpga_FTH_TxBufferLen); /* ????, actual alloc size is m_nFpgaToSW_FTH_RxBUfferLen */ if(status != XRAN_STATUS_SUCCESS) { @@ -334,23 +381,23 @@ private: for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) { for(z = 0; z < xran_max_antenna_nr; z++) { - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxBuffers[j][i][z][0]; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulRxBuffers[j][i][z][0]; for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) { - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nFpgaToSW_FTH_RxBufferLen; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],&ptr, &mb); + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = m_nFpgaToSW_FTH_RxBufferLen; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType],&ptr, &mb); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl; return (-1); } - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - m_sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *) mb; if(ptr) { u32dptr = (uint32_t*)(ptr); uint8_t *ptr_temp = (uint8_t *)ptr; @@ -361,16 +408,16 @@ private: } eInterfaceType = XRANFTHTX_SEC_DESC_IN; - status = xran_bm_init(m_nInstanceHandle[0][i], - &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], - XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SYM, sizeof(struct xran_section_desc)); + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], + XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT*XRAN_MAX_SECTIONS_PER_SLOT*XRAN_MAX_FRAGMENT, sizeof(struct xran_section_desc)); if(XRAN_STATUS_SUCCESS != status) { std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl; return (-1); } eInterfaceType = XRANFTHRX_PRB_MAP_IN; - status = xran_bm_init(m_nInstanceHandle[0][i], - &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], + status = xran_bm_init(psBbuIo->nInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT, sizeof(struct xran_prb_map)); if(status != XRAN_STATUS_SUCCESS) { @@ -380,37 +427,39 @@ private: for(j = 0;j < XRAN_N_FE_BUF_LEN; j++) { for(z = 0; z < xran_max_antenna_nr; z++) { - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFrontHaulRxPrbMapBuffers[j][i][z]; - - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i],m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = XRAN_NUM_OF_SYMBOL_PER_SLOT; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFrontHaulRxPrbMapBuffers[j][i][z]; + + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nElementLenInBytes = sizeof(struct xran_prb_map); + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nNumberOfElements = 1; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i],psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer , status " << status << std::endl; return (-1); } - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; - m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pData = (uint8_t *)ptr; + psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList.pBuffers->pCtrl = (void *)mb; void *sd_ptr; void *sd_mb; int elm_id; struct xran_prb_map * p_rb_map = (struct xran_prb_map *)ptr; //memcpy(ptr, &startupConfiguration.PrbMap, sizeof(struct xran_prb_map)); - for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SYM; elm_id++){ + for (elm_id = 0; elm_id < XRAN_MAX_SECTIONS_PER_SLOT; elm_id++){ struct xran_prb_elm *pPrbElem = &p_rb_map->prbMap[elm_id]; for(k = 0; k < XRAN_NUM_OF_SYMBOL_PER_SLOT; k++){ - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN], &sd_ptr, &sd_mb); + for(m = 0; m < XRAN_MAX_FRAGMENT; m++){ + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][XRANFTHTX_SEC_DESC_IN], &sd_ptr, &sd_mb); if(XRAN_STATUS_SUCCESS != status){ std::cout << __LINE__ << "SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl; return (-1); } - pPrbElem->p_sec_desc[k] = (struct xran_section_desc *)sd_ptr; + pPrbElem->p_sec_desc[k][m] = (struct xran_section_desc *)sd_ptr; + } } } } @@ -419,36 +468,37 @@ private: for(i = 0; inInstanceHandle[o_xu_id][i], + &psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], XRAN_N_FE_BUF_LEN * xran_max_antenna_nr * XRAN_NUM_OF_SYMBOL_PER_SLOT, - FPGA_TO_SW_PRACH_RX_BUFFER_LEN); + PRACH_PLAYBACK_BUFFER_BYTES); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_init, status " << status << std::endl; return (-1); } for(j = 0; j < XRAN_N_FE_BUF_LEN; j++) { for(z = 0; z < xran_max_antenna_nr; z++) { - m_sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &m_sFHPrachRxBuffers[j][i][z][0]; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].bValid = 0; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegGenerated = -1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegToBeGen = -1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].nSegTransferred = 0; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.nNumBuffers = xran_max_antenna_nr; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers = &psIoCtrl->sFHPrachRxBuffers[j][i][z][0]; for(k = 0; k< XRAN_NUM_OF_SYMBOL_PER_SLOT; k++) { - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = FPGA_TO_SW_PRACH_RX_BUFFER_LEN; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; - status = xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nElementLenInBytes = PRACH_PLAYBACK_BUFFER_BYTES; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nNumberOfElements = 1; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].nOffsetInBytes = 0; + status = xran_bm_allocate_buffer(psBbuIo->nInstanceHandle[o_xu_id][i], psBbuIo->nBufPoolIndex[o_xu_id][m_nSectorIndex[i]][eInterfaceType], &ptr, &mb); if(status != XRAN_STATUS_SUCCESS) { std::cout << __LINE__ << " Failed at xran_bm_allocate_buffer, status " << status << std::endl; return (-1); } - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; - m_sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pData = (uint8_t *)ptr; + psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList.pBuffers[k].pCtrl = (void *)mb; if(ptr) { u32dptr = (uint32_t*)(ptr); - memset(u32dptr, 0x0, FPGA_TO_SW_PRACH_RX_BUFFER_LEN); + memset(u32dptr, 0x0, PRACH_PLAYBACK_BUFFER_BYTES); } } } @@ -484,6 +534,9 @@ public: m_xranInit.io_cfg.pkt_proc_core = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_proc_core"); m_xranInit.io_cfg.pkt_aux_core = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "pkt_aux_core"); m_xranInit.io_cfg.timing_core = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "timing_core"); + m_xranInit.io_cfg.dpdkMemorySize = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkMemorySize"); + + m_xranInit.xran_ports = 1; std::string bbdev_mode = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "bbdev_mode"); if(bbdev_mode == "sw") @@ -499,6 +552,7 @@ public: m_xranInit.dpdkBasebandFecMode = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandFecMode"); + m_dpdk_bbdev = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "dpdkBasebandDevice"); m_xranInit.dpdkBasebandDevice = (m_dpdk_bbdev == "") ? NULL : (char *)&m_dpdk_bbdev; @@ -520,8 +574,8 @@ public: m_ru_mac[i] = (uint8_t)tmp_mac[i]; m_xranInit.p_o_du_addr = (int8_t *)m_du_mac; m_xranInit.p_o_ru_addr = (int8_t *)m_ru_mac; - m_xranInit.cp_vlan_tag = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "cp_vlan_tag"); - m_xranInit.up_vlan_tag = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "up_vlan_tag"); + m_xranConf.cp_vlan_tag = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "cp_vlan_tag"); + m_xranConf.up_vlan_tag = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_IO, "up_vlan_tag"); /* eAxCID configurations */ int bitnum_cuport = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_EAXCID, "bit_cuPortId"); @@ -539,36 +593,36 @@ public: m_xranInit.eAxCId_conf.mask_ruPortId = get_eaxcid_mask(bitnum_ruport, m_xranInit.eAxCId_conf.bit_ruPortId); m_xranInit.totalBfWeights = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "totalBfWeights"); - - m_xranInit.Tadv_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Tadv_cp_dl"); - m_xranInit.T2a_min_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_dl"); - m_xranInit.T2a_max_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_dl"); - m_xranInit.T2a_min_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_ul"); - m_xranInit.T2a_max_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_ul"); - m_xranInit.T2a_min_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_up"); - m_xranInit.T2a_max_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_up"); - m_xranInit.Ta3_min = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_min"); - m_xranInit.Ta3_max = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_max"); - m_xranInit.T1a_min_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_dl"); - m_xranInit.T1a_max_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_dl"); - m_xranInit.T1a_min_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_ul"); - m_xranInit.T1a_max_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_ul"); - m_xranInit.T1a_min_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_up"); - m_xranInit.T1a_max_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_up"); - m_xranInit.Ta4_min = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_min"); - m_xranInit.Ta4_max = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_max"); - - m_xranInit.enableCP = 1; - m_xranInit.prachEnable = 1; - m_xranInit.debugStop = 0; - m_xranInit.debugStopCount = 0; - m_xranInit.DynamicSectionEna= 0; - m_xranInit.filePrefix = "wls"; m_bSub6 = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "sub6"); memset(&m_xranConf, 0, sizeof(struct xran_fh_config)); + + m_xranConf.Tadv_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Tadv_cp_dl"); + m_xranConf.T2a_min_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_dl"); + m_xranConf.T2a_max_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_dl"); + m_xranConf.T2a_min_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_cp_ul"); + m_xranConf.T2a_max_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_cp_ul"); + m_xranConf.T2a_min_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_min_up"); + m_xranConf.T2a_max_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T2a_max_up"); + m_xranConf.Ta3_min = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_min"); + m_xranConf.Ta3_max = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta3_max"); + m_xranConf.T1a_min_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_dl"); + m_xranConf.T1a_max_cp_dl = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_dl"); + m_xranConf.T1a_min_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_cp_ul"); + m_xranConf.T1a_max_cp_ul = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_cp_ul"); + m_xranConf.T1a_min_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_min_up"); + m_xranConf.T1a_max_up = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "T1a_max_up"); + m_xranConf.Ta4_min = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_min"); + m_xranConf.Ta4_max = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "Ta4_max"); + + m_xranConf.enableCP = 1; + m_xranConf.prachEnable = 1; + m_xranConf.debugStop = 0; + m_xranConf.debugStopCount = 0; + m_xranConf.DynamicSectionEna= 0; + tmpstr = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "duplex"); if(tmpstr == "FDD") { m_xranConf.frame_conf.nFrameDuplexType = 0; @@ -623,6 +677,7 @@ public: m_xranConf.nDLRBs = get_num_rbs(get_numerology(), temp, m_bSub6); temp = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "chbw_ul"); m_xranConf.nULRBs = get_num_rbs(get_numerology(), temp, m_bSub6); + m_xranConf.dpdk_port = 0; m_xranConf.nAntElmTRx = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "ant_elm_trx"); m_xranConf.nDLFftSize = get_globalcfg(XRAN_UT_KEY_GLOBALCFG_RU, "fft_size"); @@ -706,6 +761,8 @@ public: xran_init(0, NULL, &m_xranInit, &argv[0], &m_xranhandle); + + for(i = 0; i < XRAN_MAX_SECTOR_NR; i++) m_nSectorIndex[i] = i; @@ -713,7 +770,7 @@ public: m_nFpgaToSW_FTH_RxBufferLen = 13168; /* 273*12*4 + 64*/ m_nSW_ToFpga_FTH_TxBufferLen = 13168; /* 273*12*4 + 64*/ - if(init_memory() < 0) { + if(init_memory(0) < 0) { std::cout << "Fatal Error on Initialization !!!" << std::endl; std::cout << "INIT FAILED" << std::endl; return (-1); @@ -734,7 +791,7 @@ public: std::cout << "ALREADY CLOSED" << std::endl; } - int Init(struct xran_fh_config *pCfg = nullptr) + int Init(uint32_t o_xu_id, struct xran_fh_config *pCfg = nullptr) { xran_status_t status; int32_t nSectorNum; @@ -750,6 +807,8 @@ public: char *pos = NULL; struct xran_prb_map *pRbMap = NULL; + struct bbu_xran_io_if *psBbuIo = (struct bbu_xran_io_if*)&m_gsXranIoIf; + struct xran_io_shared_ctrl *psIoCtrl = (struct xran_io_shared_ctrl *)&psBbuIo->ioCtrl[o_xu_id]; uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul()); uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr); @@ -760,9 +819,12 @@ public: memcpy(&m_xranConf, pCfg, sizeof(struct xran_fh_config)); /* Init timer context */ - xran_lib_ota_tti = 0; - xran_lib_ota_sym = 0; - xran_lib_ota_sym_idx = 0; + for (i=0; ipData; + pRbMap = (struct xran_prb_map *)psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; if(pRbMap) { pRbMap->dir = XRAN_DIR_DL; pRbMap->xran_port = 0; @@ -842,7 +904,7 @@ public: p_prbMap = &pRbMap->prbMap[idxElm]; for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++) { /* copy BF W IQs for 1 PRB of */ - rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4); + memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4); } } #endif @@ -853,7 +915,7 @@ public: } /* C-plane UL */ - pRbMap = (struct xran_prb_map *)m_sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; + pRbMap = (struct xran_prb_map *)psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->pData; if(pRbMap) { pRbMap->dir = XRAN_DIR_UL; pRbMap->xran_port = 0; @@ -895,7 +957,7 @@ public: p_prbMap = &pRbMap->prbMap[idxElm]; for (iPrb = p_prbMap->nRBStart; iPrb < (p_prbMap->nRBStart + p_prbMap->nRBSize); iPrb++){ /* copy BF W IQs for 1 PRB of */ - rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (ul_bfw_pos + (iPrb*num_antelm)*4), num_antelm*4); + memcpy(&pRbMap->bf_weight.weight[iPrb][0], (ul_bfw_pos + (iPrb*num_antelm)*4), num_antelm*4); } } #endif @@ -934,13 +996,16 @@ public: } - void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up, + void Open(uint32_t o_xu_id, xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up, void *fh_rx_callback, void *fh_rx_prach_callback, void *fh_srs_callback) { struct xran_fh_config *pXranConf; int32_t nSectorNum; int i, j, k, z; + struct bbu_xran_io_if *psBbuIo = (struct bbu_xran_io_if*)&m_gsXranIoIf; + struct xran_io_shared_ctrl *psIoCtrl = (struct xran_io_shared_ctrl *)&psBbuIo->ioCtrl[o_xu_id]; + uint32_t xran_max_antenna_nr = RTE_MAX(get_num_eaxc(), get_num_eaxc_ul()); uint32_t xran_max_ant_array_elm_nr = RTE_MAX(get_num_antelmtrx(), xran_max_antenna_nr); @@ -949,7 +1014,9 @@ public: struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxRachBufferDecomp[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; struct xran_buffer_list *pFthRxSrsBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxSrsPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_N_FE_BUF_LEN]; #if 0 xran_reg_physide_cb(xranHandle, physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI); @@ -958,61 +1025,59 @@ public: #endif nSectorNum = get_num_cc(); - for(i=0; isFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList); + pFthTxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxPrbMapBuffer[i][z][j] = &(psIoCtrl->sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxRachBuffer[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxRachBufferDecomp[i][z][j] = &(psIoCtrl->sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList); } - for(z = 0; z < xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr; z++){ - pFthRxSrsBuffer[i][z][j] = &(m_sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList); + for(z = 0; z < XRAN_MAX_ANT_ARRAY_ELM_NR /*xran_max_ant_array_elm_nr && xran_max_ant_array_elm_nr*/; z++) { + pFthRxSrsBuffer[i][z][j] = &(psIoCtrl->sFHSrsRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxSrsPrbMapBuffer[i][z][j] = &(psIoCtrl->sFHSrsRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); } } } - if(m_nInstanceHandle[0] != NULL) { + if(psBbuIo->nInstanceHandle[o_xu_id] != NULL) { for(i = 0; inInstanceHandle[o_xu_id][i], pFthTxBuffer[i], pFthTxPrbMapBuffer[i], pFthRxBuffer[i], pFthRxPrbMapBuffer[i], (void (*)(void *, xran_status_t))fh_rx_callback, &pFthRxBuffer[i][0]); - - xran_5g_prach_req(m_nInstanceHandle[0][i], pFthRxRachBuffer[i], - (void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i][0]); + xran_5g_prach_req(psBbuIo->nInstanceHandle[o_xu_id][i], pFthRxRachBuffer[i],pFthRxRachBufferDecomp[i], + (void (*)(void *, xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i]); } /* add SRS callback here */ for (i = 0; inInstanceHandle[o_xu_id][i], pFthRxSrsBuffer[i], pFthRxSrsPrbMapBuffer[i], + (void (*)(void *, xran_status_t))fh_srs_callback, pFthRxSrsBuffer[i]); } } - - xran_register_cb_mbuf2ring(send_cp, send_up); - xran_open(m_xranhandle, &m_xranConf); } @@ -1046,14 +1111,19 @@ public: void update_symbol_index() { - xran_lib_ota_sym_idx++; - if((xran_lib_ota_sym_idx % N_SYM_PER_SLOT) == 0) { + int i; + for (i=0; i= N_SYM_PER_SLOT) + xran_lib_ota_sym[i] = 0; + } - xran_lib_ota_sym++; - if(xran_lib_ota_sym >= N_SYM_PER_SLOT) - xran_lib_ota_sym = 0; } int apply_cpenable(bool flag) @@ -1067,11 +1137,11 @@ public: return (-1); if(flag == true) { - m_xranInit.enableCP = 1; + m_xranConf.enableCP = 1; pCtx->enableCP = 1; } else { - m_xranInit.enableCP = 0; + m_xranConf.enableCP = 0; pCtx->enableCP = 0; } @@ -1142,9 +1212,9 @@ public: } void *get_xranhandle() { return(m_xranhandle); } - void *get_timer_ctx() { return((void *)&m_timer_ctx[0]); } + void *get_timer_ctx() { return((void *)xran_dev_get_ctx()); } - int get_symbol_index() { return (xran_lib_ota_sym); } + int get_symbol_index() { return (xran_lib_ota_sym[0]); } bool is_running() { return((xran_get_if_state() == XRAN_RUNNING)?true:false); } @@ -1159,9 +1229,9 @@ public: int get_num_ulrbs() { return(m_xranConf.nULRBs); } int get_num_antelmtrx() { return(m_xranConf.nAntElmTRx); } - bool is_cpenable() { return(m_xranInit.enableCP); }; - bool is_prachenable() { return(m_xranInit.prachEnable); }; - bool is_dynamicsection() { return(m_xranInit.DynamicSectionEna?true:false); } + bool is_cpenable() { return(m_xranConf.enableCP); }; + bool is_prachenable() { return(m_xranConf.prachEnable); }; + bool is_dynamicsection() { return(m_xranConf.DynamicSectionEna?true:false); } void get_cfg_prach(struct xran_prach_config *pCfg) { diff --git a/fhi_lib/test/common/xranlib_unit_test_main.cc b/fhi_lib/test/common/xranlib_unit_test_main.cc index 22c6d16..991dfc4 100644 --- a/fhi_lib/test/common/xranlib_unit_test_main.cc +++ b/fhi_lib/test/common/xranlib_unit_test_main.cc @@ -1,6 +1,19 @@ /******************************************************************************* * - * + * Copyright (c) 2020 Intel. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * * *******************************************************************************/ #include @@ -27,7 +40,6 @@ static int parse_input_parameter(std::string executable, std::string option) } } -//xranLibWraper xranlib; xranLibWraper *xranlib; int main(int argc, char** argv) { diff --git a/fhi_lib/test/master.py b/fhi_lib/test/master.py index 4ad8656..8d43186 100755 --- a/fhi_lib/test/master.py +++ b/fhi_lib/test/master.py @@ -1,7 +1,7 @@ #!/usr/bin/python #****************************************************************************** # -# Copyright (c) 2019 Intel. +# Copyright (c) 2020 Intel. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -23,9 +23,11 @@ import logging import sys import argparse import re +import signal import subprocess import os import shutil +import copy from itertools import dropwhile from datetime import datetime from time import gmtime, strftime @@ -62,69 +64,171 @@ nRChBwOptions_keys_mu2and3 = ['50', '100', '200', '400'] nRChBwOptions_values_mu2and3 = [0,1,2,3] nRChBwOptions_mu2and3 = dict(zip(nRChBwOptions_keys_mu2and3, nRChBwOptions_values_mu2and3)) +vf_addr_o_xu=[] + # values for Jenkins server -eth_cp_dev = ["0000:19:02.1", "0000:19:0a.1"] -eth_up_dev = ["0000:19:02.0", "0000:19:0a.0"] +vf_addr_o_xu_jenkins = [ + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:19:02.0,0000:19:0a.0", "0000:19:02.1,0000:19:0a.1", "0000:19:02.2,0000:19:0a.2" ], #O-DU + ["0000:af:02.0,0000:af:0a.0", "0000:af:02.1,0000:af:0a.1", "0000:af:02.2,0000:af:0a.2" ], #O-RU +] + +vf_addr_o_xu_sc12 = [ # 2x2x25G with loopback FVL0:port0 to FVL1:port 0 FVL0:port1 to FVL1:port 1 + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:88:02.0,0000:88:0a.0", "0000:88:02.1,0000:88:0a.1", "0000:88:02.2,0000:88:0a.2" ], #O-DU + ["0000:86:02.0,0000:86:0a.0", "0000:86:02.1,0000:86:0a.1", "0000:86:02.2,0000:86:0a.2" ], #O-RU +] + +vf_addr_o_xu_sc12_cvl = [ + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:22:01.0,0000:22:09.0" ], #O-DU + ["0000:af:01.0,0000:af:09.0", "0000:af:11.0,0000:af:19.0", "0000:1a:01.0,0000:1a:09.0" ], #O-RU +] + +vf_addr_o_xu_scs1_30 = [ + ["0000:65:01.0,0000:65:01.1,0000:65:01.2,0000:65:01.3", "0000:65:01.4,0000:65:01.5,0000:65:01.6,0000:65:01.7", "0000:65:02.0,0000:65:02.1,0000:65:02.2,0000:65:02.3" ], #O-DU + ["0000:65:09.0,0000:65:09.1,0000:65:09.2,0000:65:09.3", "0000:65:09.4,0000:65:09.5,0000:65:09.6,0000:65:09.7", "0000:65:0a.0,0000:65:0a.1,0000:65:0a.2,0000:65:0a.3" ], #O-RU +] + +vf_addr_o_xu_scs1_repo = [ + ["0000:18:01.0,0000:18:01.1,0000:18:01.2,0000:18:01.3", "0000:18:01.4,0000:18:01.5,0000:18:01.6,0000:18:01.7", "0000:18:02.0,0000:18:02.1,0000:18:02.2,0000:18:02.3" ], #O-DU + ["0000:18:11.0,0000:18:11.1,0000:18:11.2,0000:18:11.3", "0000:18:11.4,0000:18:11.5,0000:18:11.6,0000:18:11.7", "0000:18:12.0,0000:18:12.1,0000:18:12.2,0000:18:12.3" ], #O-RU +] + +vf_addr_o_xu_icelake_scs1_1 = [ + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:18:01.0,0000:18:09.0" ], #O-DU + ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:65:01.0,0000:65:09.0" ], #O-RU +] + +vf_addr_o_xu_icx_npg_scs1_coyote4 = [ + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:51:01.0,0000:51:09.0", "0000:51:11.0,0000:51:19.0", "0000:54:01.0,0000:54:11.0" ], #O-DU + ["0000:17:01.0,0000:17:09.0", "0000:17:11.0,0000:17:19.0", "0000:65:01.0,0000:65:09.0" ], #O-RU +] + +vf_addr_o_xu_scs1_35 = [ + ["0000:88:01.0,0000:88:01.1,0000:88:01.2,0000:88:01.3", "0000:88:01.4,0000:88:01.5,0000:88:01.6,0000:88:01.7", "0000:88:02.0,0000:88:02.1,0000:88:02.2,0000:88:02.3" ], #O-DU + ["0000:88:11.0,0000:88:11.1,0000:88:11.2,0000:88:11.3", "0000:88:11.4,0000:88:11.5,0000:88:11.6,0000:88:11.7", "0000:88:12.0,0000:88:12.1,0000:88:12.2,0000:88:12.3" ], #O-RU +] + +vf_addr_o_xu_csl_npg_scs1_33 = [ + #vf_addr_o_xu_a vf_addr_o_xu_b vf_addr_o_xu_c + ["0000:1a:01.0,0000:1a:01.1", "0000:1a:01.2,0000:1a:01.3", "0000:1a:01.4,0000:1a:01.5" ], #O-DU + ["0000:1a:11.0,0000:1a:11.1", "0000:1a:11.2,0000:1a:11.3", "0000:1a:11.4,0000:1a:11.5" ], #O-RU +] # table of all test cases -# (ran, cat, mu, bw, test case) +# (ran, cat, mu, bw, test case, "test case description") #Cat A -NR_test_cases_A = [(0, 0, 0, 5, 0), - (0, 0, 0, 10, 0), - (0, 0, 0, 10, 12), - (0, 0, 0, 20, 0), - (0, 0, 0, 20, 12), - (0, 0, 1, 100, 0), - (0, 0, 3, 100, 0), +NR_test_cases_A = [(0, 0, 0, 5, 0, "NR_Sub6_Cat_A_5MHz_1_Cell_0"), + (0, 0, 0, 10, 0, "NR_Sub6_Cat_A_10MHz_1_Cell_0"), + (0, 0, 0, 10, 12, "NR_Sub6_Cat_A_10MHz_12_Cell_12"), + (0, 0, 0, 20, 0, "NR_Sub6_Cat_A_20MHz_1_Cell_0"), + (0, 0, 0, 20, 12, "NR_Sub6_Cat_A_20MHz_12_Cell_12"), + (0, 0, 0, 20, 20, "NR_Sub6_Cat_A_20MHz_1_Cell_owd_req_resp"), + (0, 0, 0, 20, 21, "NR_Sub6_Cat_A_20MHz_1_Cell_owd_rem_req"), + (0, 0, 0, 20, 22, "NR_Sub6_Cat_A_20MHz_1_Cell_owd_req_wfup"), + (0, 0, 0, 20, 23, "NR_Sub6_Cat_A_20MHz_1_Cell_owd_rem_req_wfup"), + (0, 0, 1, 100, 0, "NR_Sub6_Cat_A_100MHz_1_Cell_0"), + (0, 0, 3, 100, 0, "NR_mmWave_Cat_A_100MHz_1_Cell_0"), + (0, 0, 3, 100, 7, "NR_mmWave_Cat_A_100MHz_1_Cell_0_sc"), ] -LTE_test_cases_A = [(1, 0, 0, 5, 0), - (1, 0, 0, 10, 0), - (1, 0, 0, 20, 0), +LTE_test_cases_A = [(1, 0, 0, 5, 0, "LTE_Cat_A_5Hz_1_Cell_0"), + (1, 0, 0, 10, 0, "LTE_Cat_A_10Hz_1_Cell_0"), + (1, 0, 0, 20, 0, "LTE_Cat_A_20Hz_1_Cell_0"), ] #Cat B -NR_test_cases_B = [(0, 1, 1, 100, 0), - (0, 1, 1, 100, 2), - (0, 1, 1, 100, 1), - (0, 1, 1, 100, 101), - (0, 1, 1, 100, 102), - (0, 1, 1, 100, 103), - (0, 1, 1, 100, 104), - (0, 1, 1, 100, 105), - #(0, 1, 1, 100, 106), 25G not enough - (0, 1, 1, 100, 107), - (0, 1, 1, 100, 108), - #(0, 1, 1, 100, 109), 25G not enough - (0, 1, 1, 100, 201), - #(0, 1, 1, 100, 202), 25G not enough - #(0, 1, 1, 100, 203), - (0, 1, 1, 100, 204), - (0, 1, 1, 100, 205), - (0, 1, 1, 100, 206), - (0, 1, 1, 100, 211), - #(0, 1, 1, 100, 212), 25G not enough - (0, 1, 1, 100, 213), - (0, 1, 1, 100, 214), - (0, 1, 1, 100, 215), - (0, 1, 1, 100, 216) +NR_test_cases_B = [(0, 1, 1, 100, 0, "NR_Sub6_Cat_B_100MHz_1_Cell_0"), + (0, 1, 1, 100, 2, "NR_Sub6_Cat_B_100MHz_1_Cell_2"), + (0, 1, 1, 100, 1, "NR_Sub6_Cat_B_100MHz_1_Cell_1"), + (0, 1, 1, 100, 101, "NR_Sub6_Cat_B_100MHz_1_Cell_101"), + (0, 1, 1, 100, 102, "NR_Sub6_Cat_B_100MHz_1_Cell_102"), + (0, 1, 1, 100, 103, "NR_Sub6_Cat_B_100MHz_1_Cell_103"), + (0, 1, 1, 100, 104, "NR_Sub6_Cat_B_100MHz_1_Cell_104"), + (0, 1, 1, 100, 105, "NR_Sub6_Cat_B_100MHz_1_Cell_105"), + (0, 1, 1, 100, 106, "NR_Sub6_Cat_B_100MHz_1_Cell_106"), + (0, 1, 1, 100, 107, "NR_Sub6_Cat_B_100MHz_1_Cell_107"), + (0, 1, 1, 100, 108, "NR_Sub6_Cat_B_100MHz_1_Cell_108"), + (0, 1, 1, 100, 109, "NR_Sub6_Cat_B_100MHz_1_Cell_109"), + (0, 1, 1, 100, 201, "NR_Sub6_Cat_B_100MHz_1_Cell_201"), + (0, 1, 1, 100, 202, "NR_Sub6_Cat_B_100MHz_1_Cell_202"), + (0, 1, 1, 100, 203, "NR_Sub6_Cat_B_100MHz_1_Cell_203"), + (0, 1, 1, 100, 204, "NR_Sub6_Cat_B_100MHz_1_Cell_204"), + (0, 1, 1, 100, 205, "NR_Sub6_Cat_B_100MHz_1_Cell_205"), + (0, 1, 1, 100, 206, "NR_Sub6_Cat_B_100MHz_1_Cell_206"), + (0, 1, 1, 100, 211, "NR_Sub6_Cat_B_100MHz_1_Cell_211"), + (0, 1, 1, 100, 212, "NR_Sub6_Cat_B_100MHz_1_Cell_212"), + (0, 1, 1, 100, 213, "NR_Sub6_Cat_B_100MHz_1_Cell_213"), + (0, 1, 1, 100, 214, "NR_Sub6_Cat_B_100MHz_1_Cell_214"), + (0, 1, 1, 100, 215, "NR_Sub6_Cat_B_100MHz_1_Cell_215"), + (0, 1, 1, 100, 216, "NR_Sub6_Cat_B_100MHz_1_Cell_216"), + #(0, 1, 1, 100, 401, "NR_Sub6_Cat_B_100MHz_1_Cell_401") 25G not enough ] -LTE_test_cases_B = [(1, 1, 0, 5, 0), - (1, 1, 0, 10, 0), - (1, 1, 0, 20, 0), +LTE_test_cases_B = [(1, 1, 0, 5, 0, "LTE_Cat_B_5MHz_1_Cell_0"), + (1, 1, 0, 10, 0, "LTE_Cat_B_10MHz_1_Cell_0"), + (1, 1, 0, 20, 0, "LTE_Cat_B_20MHz_1_Cell_0"), + (1, 1, 0, 5, 1, "LTE_Cat_B_5Hz_1_Cell_0_sc"), + (1, 1, 0, 10, 1, "LTE_Cat_B_10Hz_1_Cell_0_sc"), + (1, 1, 0, 20, 1, "LTE_Cat_B_20Hz_1_Cell_0_sc"), + ] V_test_cases_B = [ - # (0, 1, 1, 100, 301), 25G not enough - (0, 1, 1, 100, 302), - (0, 1, 1, 100, 303), - (0, 1, 1, 100, 304), - (0, 1, 1, 100, 305), - (0, 1, 1, 100, 306) + (0, 1, 1, 100, 301, "NR_Sub6_Cat_B_100MHz_1_Cell_301"), + (0, 1, 1, 100, 302, "NR_Sub6_Cat_B_100MHz_1_Cell_302"), + (0, 1, 1, 100, 303, "NR_Sub6_Cat_B_100MHz_1_Cell_303"), + (0, 1, 1, 100, 304, "NR_Sub6_Cat_B_100MHz_1_Cell_304"), + (0, 1, 1, 100, 305, "NR_Sub6_Cat_B_100MHz_1_Cell_305"), + (0, 1, 1, 100, 306, "NR_Sub6_Cat_B_100MHz_1_Cell_306"), + (0, 1, 1, 100, 602, "NR_Sub6_Cat_B_100MHz_1_Cell_602_sc"), ] -all_test_cases = NR_test_cases_A + LTE_test_cases_A + LTE_test_cases_B + NR_test_cases_B + V_test_cases_B +V_test_cases_B_2xUL = [ + (0, 1, 1, 100, 311, "NR_Sub6_Cat_B_100MHz_1_Cell_311"), + (0, 1, 1, 100, 312, "NR_Sub6_Cat_B_100MHz_1_Cell_312"), + (0, 1, 1, 100, 313, "NR_Sub6_Cat_B_100MHz_1_Cell_313"), + (0, 1, 1, 100, 314, "NR_Sub6_Cat_B_100MHz_1_Cell_314"), + (0, 1, 1, 100, 315, "NR_Sub6_Cat_B_100MHz_1_Cell_315"), + (0, 1, 1, 100, 316, "NR_Sub6_Cat_B_100MHz_1_Cell_316"), + (0, 1, 1, 100, 612, "NR_Sub6_Cat_B_100MHz_1_Cell_612_sc"), + +] + +V_test_cases_B_mtu_1500 = [ + (0, 1, 1, 100, 501, "NR_Sub6_Cat_B_100MHz_1_Cell_501"), + (0, 1, 1, 100, 502, "NR_Sub6_Cat_B_100MHz_1_Cell_502"), + (0, 1, 1, 100, 503, "NR_Sub6_Cat_B_100MHz_1_Cell_503"), + (0, 1, 1, 100, 504, "NR_Sub6_Cat_B_100MHz_1_Cell_504"), + (0, 1, 1, 100, 505, "NR_Sub6_Cat_B_100MHz_1_Cell_505"), + (0, 1, 1, 100, 506, "NR_Sub6_Cat_B_100MHz_1_Cell_506"), + (0, 1, 1, 100, 802, "NR_Sub6_Cat_B_100MHz_1_Cell_802_sc"), +] + +V_test_cases_B_mtu_1500_2xUL = [ + (0, 1, 1, 100, 511, "NR_Sub6_Cat_B_100MHz_1_Cell_511"), + (0, 1, 1, 100, 512, "NR_Sub6_Cat_B_100MHz_1_Cell_512"), + (0, 1, 1, 100, 513, "NR_Sub6_Cat_B_100MHz_1_Cell_513"), + (0, 1, 1, 100, 514, "NR_Sub6_Cat_B_100MHz_1_Cell_514"), + (0, 1, 1, 100, 515, "NR_Sub6_Cat_B_100MHz_1_Cell_515"), + (0, 1, 1, 100, 516, "NR_Sub6_Cat_B_100MHz_1_Cell_516"), + (0, 1, 1, 100, 812, "NR_Sub6_Cat_B_100MHz_1_Cell_812_sc"), +] + +V_test_cases_B_3Cells = [ + (0, 1, 1, 100, 3301, "NR_Sub6_Cat_B_100MHz_1_Cell_3301"), + (0, 1, 1, 100, 3311, "NR_Sub6_Cat_B_100MHz_1_Cell_3311") +] + +V_test_cases_B_3Cells_mtu_1500 = [ + (0, 1, 1, 100, 3501, "NR_Sub6_Cat_B_100MHz_1_Cell_3501"), + (0, 1, 1, 100, 3511, "NR_Sub6_Cat_B_100MHz_1_Cell_3511") +] + +all_test_cases = NR_test_cases_A + LTE_test_cases_A + LTE_test_cases_B + NR_test_cases_B + V_test_cases_B + V_test_cases_B_2xUL dic_dir = dict({0:'DL', 1:'UL'}) dic_xu = dict({0:'o-du', 1:'o-ru'}) @@ -150,6 +254,7 @@ def parse_args(args): # Parser configuration parser = argparse.ArgumentParser(description="Run test cases: category numerology bandwidth test_num") + parser.add_argument("--rem_o_ru_host", type=str, default="", help="remot host to run O-RU", metavar="root@10.10.10.1", dest="rem_o_ru_host") parser.add_argument("--ran", type=int, default=0, help="Radio Access Tehcnology 0 (5G NR) or 1 (LTE)", metavar="ran", dest="rantech") parser.add_argument("--cat", type=int, default=0, help="Category: 0 (A) or 1 (B)", metavar="cat", dest="category") parser.add_argument("--mu", type=int, default=0, help="numerology [0,1,3]", metavar="num", dest="numerology") @@ -157,11 +262,12 @@ def parse_args(args): parser.add_argument("--testcase", type=int, default=0, help="test case number", metavar="testcase", dest="testcase") parser.add_argument("--verbose", type=int, default=0, help="enable verbose output", metavar="verbose", dest="verbose") + # Parse arguments options = parser.parse_args(args) #parser.print_help() - logging.debug("Options: ran=%d category=%d num=%d bw=%d testcase=%d", - options.rantech, options.category, options.numerology, options.bandwidth, options.testcase) + logging.info("Options: rem_o_ru_host=%s ran=%d category=%d num=%d bw=%d testcase=%d", + options.rem_o_ru_host, options.rantech, options.category, options.numerology, options.bandwidth, options.testcase) return options def is_comment(s): @@ -208,14 +314,52 @@ def get_re_map(nRB, direction): #print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize))) prb_map = prb_map + list(range(xRBStart*12, xRBStart*12 + xRBSize*12)) else: - nPrbElm = 0; + nPrbElm = 0 + + elif direction == 2: + #UL + if 'nPrbElemSrs' in globals(): + nPrbElm = nPrbElemUl + for i in range(0, nPrbElm): + elm = str('PrbElemSrs'+str(i)) + #print(elm) + if (elm in globals()): + PrbElemContent.insert(i,list(globals()[elm])) + xRBStart = PrbElemContent[i][0] + xRBSize = PrbElemContent[i][1] + #print(PrbElemContent,"RBStart: ", xRBStart, "RBSize: ",xRBSize, list(range(xRBStart, xRBStart + xRBSize))) + prb_map = prb_map + list(range(xRBStart*12, xRBStart*12 + xRBSize*12)) + else: + nPrbElm = 0 if nPrbElm == 0 : prb_map = list(range(0, nRB*12)) return prb_map -def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): +def check_for_string_present_in_file(file_name, search_string): + res = 1 + with open(file_name, 'r') as read_obj: + for line in read_obj: + if search_string in line: + read_obj.close() + res = 0 + return res + read_obj.close() + return res + +def check_owdm_test_results(xran_path, o_xu_id): + res = 0 + file_owd_oru = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-owd_results.txt" + file_owd_odu = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-owd_results.txt" + print("file_owd_oru :", file_owd_oru) + print("file_owd_odu :", file_owd_odu) + res = check_for_string_present_in_file(file_owd_oru, 'passed') + res = res or check_for_string_present_in_file(file_owd_odu, 'passed') + + return res + +def compare_results(o_xu_id, rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): res = 0 re_map = [] if rantech==1: @@ -249,7 +393,12 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): else: srs_enb = 0 - print("compare results: {} [compression {}]\n".format(dic_dir.get(direction), comp)) + if 'rachEanble' in globals(): + rach = rachEanble + else: + rach = 0 + + print("O-RU {} compare results: {} [compression {}]\n".format(o_xu_id, dic_dir.get(direction), comp)) #if cat == 1: # print("WARNING: Skip checking IQs and BF Weights for CAT B for now\n"); @@ -282,6 +431,7 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): else : raise Exception('i should not exceed nTddPeriod %d. The value of i was: {}'.format(nTddPeriod, i)) #print(SlotConfig, type(sSlotConfig0)) + try: if (direction == 1) & (cat == 1): #UL @@ -303,13 +453,13 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): if direction == 0: # DL nRB = nDlRB - file_tst = xran_path+"/app/logs/"+"o-ru-rx_log_ant"+str(i)+".txt" - file_ref = xran_path+"/app/logs/"+"o-du-play_ant"+str(i)+".txt" + file_tst = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-rx_log_ant"+str(i)+".txt" + file_ref = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-play_ant"+str(i)+".txt" elif direction == 1: # UL nRB = nUlRB - file_tst = xran_path+"/app/logs/"+"o-du-rx_log_ant"+str(i)+".txt" - file_ref = xran_path+"/app/logs/"+"o-ru-play_ant"+str(i)+".txt" + file_tst = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-rx_log_ant"+str(i)+".txt" + file_ref = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-play_ant"+str(i)+".txt" else: raise Exception('Direction is not supported %d'.format(direction)) @@ -347,7 +497,130 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): print(numSlots) - for slot_idx in range(0, numSlots): + #skip last slot for UL as we stop on PPS boundary (OTA) and all symbols might not be received by O-DU + for slot_idx in range(0, numSlots - (1*direction)): + for sym_idx in range(0, 14): + if nFrameDuplexType==1: + #skip sym if TDD + if direction == 0: + #DL + sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx] + if(sym_dir != 0): + continue + elif direction == 1: + #UL + sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx] + if(sym_dir != 1): + continue + + #print("Check:","[",i,"]", slot_idx, sym_idx) + for line_idx in re_map: + offset = (slot_idx*nRB*12*14) + sym_idx*nRB*12 + line_idx + try: + line_tst = tst[offset].rstrip() + except IndexError: + res = -1 + print("FAIL:","IndexError on tst: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(tst)) + raise GetOutOfLoops + try: + line_ref = ref[offset].rstrip() + except IndexError: + res = -1 + print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(ref)) + raise GetOutOfLoops + + if comp == 1: + # discard LSB bits as BFP compression is not "bit exact" + tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80 + tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80 + ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80 + ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80 + + #print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ") + if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) : + print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ") + res = -1 + raise GetOutOfLoops + else: + #if line_idx == 0: + #print("Check:", offset,"[",i,"]", slot_idx, sym_idx,":",line_tst, line_ref) + if line_ref != line_tst: + print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst:", line_tst, "ref:", line_ref) + res = -1 + raise GetOutOfLoops + except GetOutOfLoops: + return res + + if (direction == 1) & (rach == 1) & 0: #UL + print("O-RU {} compare results: {} [compression {}]\n".format(o_xu_id, 'PRACH', comp)) + + #rach + try: + if mu == 3: #FR2 + re_map = range(0, 144) + nRB = 12 + elif nFrameDuplexType==0: #FR1 FDD + if prachConfigIndex < 87: + re_map = range(0, 840) + nRB = 70 + else: + re_map = range(0, 144) + nRB = 12 + else: #FR1 TDD + if prachConfigIndex < 67: + re_map = range(0, 144) + nRB = 12 + else: + re_map = range(0, 840) + nRB = 70 + if cat == 1: + flowId = ccNum*antNumUL + else: + flowId = ccNum*antNum + + for i in range(0, flowId): + #read ref and test files + tst = [] + ref = [] + + file_tst = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-prach_log_ant"+str(i)+".txt" + file_ref = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-play_prach_ant"+str(i)+".txt" + print("test result :", file_tst) + print("test reference:", file_ref) + if os.path.exists(file_tst): + try: + file_tst = open(file_tst, 'r') + except OSError: + print ("Could not open/read file:", file_tst) + sys.exit() + else: + print(file_tst, "doesn't exist") + res = -1 + return res + if os.path.exists(file_ref): + try: + file_ref = open(file_ref, 'r') + except OSError: + print ("Could not open/read file:", file_ref) + sys.exit() + else: + print(file_tst, "doesn't exist") + res = -1 + return res + + tst = file_tst.readlines() + ref = file_ref.readlines() + + print(len(tst)) + print(len(ref)) + + file_tst.close(); + file_ref.close(); + + print(numSlots) + + #skip last slot for UL as we stop on PPS boundary (OTA) and all symbols might not be received by O-DU + for slot_idx in range(0, numSlots - (1*direction)): for sym_idx in range(0, 14): if nFrameDuplexType==1: #skip sym if TDD @@ -400,14 +673,15 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): except GetOutOfLoops: return res - #if (direction == 0) | (cat == 0) | (srs_enb == 0): #DL or Cat A + if (direction == 0) | (cat == 0) | (srs_enb == 0): #DL or Cat A #done return res - print("compare results: {} [compression {}]\n".format('SRS', comp)) + print("O-RU {} compare results: {} [compression {}]\n".format(o_xu_id, 'SRS', comp)) #srs symbMask = srsSym + re_map = get_re_map(nUlRB, 2) try: flowId = ccNum*antElmTRx for i in range(0, flowId): @@ -418,8 +692,8 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): if direction == 1: # UL nRB = nUlRB - file_tst = xran_path+"/app/logs/"+"o-du-srs_log_ant"+str(i)+".txt" - file_ref = xran_path+"/app/logs/"+"o-ru-play_srs_ant"+str(i)+".txt" + file_tst = xran_path+"/app/logs/"+"o-du"+str(o_xu_id)+"-srs_log_ant"+str(i)+".txt" + file_ref = xran_path+"/app/logs/"+"o-ru"+str(o_xu_id)+"-play_srs_ant"+str(i)+".txt" else: raise Exception('Direction is not supported %d'.format(direction)) @@ -457,10 +731,10 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): print(numSlots) - for slot_idx in range(0, numSlots): + for slot_idx in range(0, numSlots - (1*direction)): for sym_idx in range(0, 14): - if symbMask & (1 << sym_idx): - print("SRS check sym ", sym_idx) + if symbMask & (1 << sym_idx) and slot_idx%nTddPeriod == 3: + print("SRS check sym ", slot_idx, sym_idx) if nFrameDuplexType==1: #skip sym if TDD if direction == 0: @@ -471,11 +745,12 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): elif direction == 1: #UL sym_dir = SlotConfig[slot_idx%nTddPeriod][sym_idx] - if(sym_dir != 1): - continue + # ignore if DL symbol for now + #if(sym_dir != 1): + # continue - #print("Check:","[",i,"]", slot_idx, sym_idx) - for line_idx in range(0, nRB*12): + print("Check:","[",i,"]", slot_idx, sym_idx) + for line_idx in re_map: offset = (slot_idx*nRB*12*14) + sym_idx*nRB*12 + line_idx try: line_tst = tst[offset].rstrip() @@ -489,15 +764,15 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): res = -1 print("FAIL:","IndexError on ref: ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx, len(ref)) raise GetOutOfLoops - if False : #SRS sent as not compressed - #comp == 1: - # discard LSB bits as BFP compression is not Bit Exact + + if comp == 1: + # discard LSB bits as BFP compression is not "bit exact" tst_i_value = int(line_tst.split(" ")[0]) & 0xFF80 tst_q_value = int(line_tst.split(" ")[1]) & 0xFF80 ref_i_value = int(line_ref.split(" ")[0]) & 0xFF80 ref_q_value = int(line_ref.split(" ")[1]) & 0xFF80 - print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ") + #print("check:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ") if (tst_i_value != ref_i_value) or (tst_q_value != ref_q_value) : print("FAIL:","ant:[",i,"]:",offset, slot_idx, sym_idx, line_idx,":","tst: ", tst_i_value, " ", tst_q_value, " " , "ref: ", ref_i_value, " ", ref_q_value, " ") res = -1 @@ -510,15 +785,52 @@ def compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, direction): res = -1 raise GetOutOfLoops except GetOutOfLoops: - pass + #don't threat SRS as error for now + res = 0 + return res return res +def parse_usecase_cfg(rantech, cat, mu, bw, tcase, xran_path, usecase_cfg): + #parse config files + logging.info("parse config files %s\n", usecase_cfg[0]) + lineList = list() + sep = '#' + with open(usecase_cfg[0],'r') as fh: + for curline in dropwhile(is_comment, fh): + my_line = curline.rstrip().split(sep, 1)[0].strip() + if my_line: + lineList.append(my_line) + + global_env = {} + local_env = {} + + for line in lineList: + exe_line = line.replace(":", ",0x") + if exe_line.find("../") > 0 : + exe_line = exe_line.replace('../', "'../") + exe_line = exe_line+"'" + elif exe_line.find("./") > 0 : + exe_line = exe_line.replace('./', "'./") + exe_line = exe_line+"'" + + code = compile(str(exe_line), '', 'exec') + exec (code, global_env, local_env) + + for k, v in local_env.items(): + globals()[k] = v + print(k, v) + + print("Number of O-RU:", oXuNum) + + return local_env + def parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, test_cfg): #parse config files logging.info("parse config files %s\n", test_cfg[0]) lineList = list() + sep = '#' with open(test_cfg[0],'r') as fh: for curline in dropwhile(is_comment, fh): @@ -529,9 +841,12 @@ def parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, test_cfg): local_env = {} for line in lineList: - exe_line = line.replace(":", ",") - if exe_line.find("/") > 0 : - exe_line = exe_line.replace('./', "'") + exe_line = line.replace(":", ",0x") + if exe_line.find("../") > 0 : + exe_line = exe_line.replace('../', "'../") + exe_line = exe_line+"'" + elif exe_line.find("./") > 0 : + exe_line = exe_line.replace('./', "'./") exe_line = exe_line+"'" code = compile(str(exe_line), '', 'exec') @@ -553,20 +868,20 @@ def del_dat_file_vars(local_env): def make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path): res = 0 - src_bin = xran_path+"/app/mlog-o-du-c0.bin" - src_csv = xran_path+"/app/mlog-o-du-hist.csv" - dst_bin = xran_path+"/app/mlog-o-du-c0-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin" - dst_csv = xran_path+"/app/mlog-o-du-hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv" + src_bin = xran_path+"/app/mlog-o-du.bin" + src_csv = xran_path+"/app/mlog-o-du_hist.csv" + dst_bin = xran_path+"/app/mlog-o-du-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin" + dst_csv = xran_path+"/app/mlog-o-du_hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv" try: d_bin = shutil.copyfile(src_bin, dst_bin) d_csv = shutil.copyfile(src_csv, dst_csv) except IOError: - logging.info("MLog is not present\n") + logging.info("O-DU MLog is not present\n") res = 1 return res else: - logging.info("Mlog was copied\n") + logging.info("O-DU Mlog was copied\n") print("Destination path:", d_bin) @@ -575,10 +890,10 @@ def make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path): d_bin = shutil.copyfile(src_bin, dst_bin) d_csv = shutil.copyfile(src_csv, dst_csv) - src_bin = xran_path+"/app/mlog-o-ru-c0.bin" - src_csv = xran_path+"/app/mlog-o-ru-hist.csv" - dst_bin = xran_path+"/app/mlog-o-ru-c0-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin" - dst_csv = xran_path+"/app/mlog-o-ru-hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv" + src_bin = xran_path+"/app/mlog-o-ru.bin" + src_csv = xran_path+"/app/mlog-o-ru_hist.csv" + dst_bin = xran_path+"/app/mlog-o-ru-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".bin" + dst_csv = xran_path+"/app/mlog-o-ru_hist-ran"+str(rantech)+"-cat"+str(cat)+"-mu"+str(mu)+"-bw"+str(bw)+"-tcase"+str(tcase)+".csv" d_bin = shutil.copyfile(src_bin, dst_bin) d_csv = shutil.copyfile(src_csv, dst_csv) @@ -587,16 +902,16 @@ def make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path): d_bin = shutil.copyfile(src_bin, dst_bin) d_csv = shutil.copyfile(src_csv, dst_csv) except IOError: - logging.info("MLog is not present\n") + logging.info("O-RU MLog is not present\n") res = 1 return res else: - logging.info("Mlog was copied\n") + logging.info("O-RU Mlog was copied\n") return res -def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): +def run_tcase(rem_o_ru_host, rantech, cat, mu, bw, tcase, verbose, xran_path, vf_addr_o_xu): if rantech == 1: #LTE if cat == 1: @@ -610,7 +925,7 @@ def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): if cat == 1: test_config =xran_path+"/app/usecase/cat_b/mu{0:d}_{1:d}mhz".format(mu, bw) elif cat == 0 : - test_config =xran_path+"/app/usecase/mu{0:d}_{1:d}mhz".format(mu, bw) + test_config =xran_path+"/app/usecase/cat_a/mu{0:d}_{1:d}mhz".format(mu, bw) else: print("Incorrect cat argument\n") return -1 @@ -627,9 +942,13 @@ def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): logging.debug("Started script: master.py, XRAN path %s", xran_path) test_cfg = [] + global oXuOwdmEnabled + oXuOwdmEnabled = 0 #Default is owdm measurements are disabled + test_cfg.append(test_config+"/usecase_du.cfg") + test_cfg.append(test_config+"/usecase_ru.cfg") - test_cfg.append(test_config+"/config_file_o_du.dat") - test_cfg.append(test_config+"/config_file_o_ru.dat") + usecase_dirname = os.path.dirname(os.path.realpath(test_cfg[0])) + print(usecase_dirname) wd = os.getcwd() os.chdir(xran_path+"/app/") @@ -642,15 +961,33 @@ def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): os.system('pkill -9 "sample-app"') os.system('rm -rf ./logs') + usecase_cfg = parse_usecase_cfg(rantech, cat, mu, bw, tcase, xran_path, test_cfg) + REM_O_RU_HOST=rem_o_ru_host + for i in range(2): + log_file_name.append("sampleapp_log_{}_{}_cat_{}_mu{}_{}mhz_tst_{}.log".format(dic_ran_tech.get(rantech), dic_xu.get(i),cat, mu, bw, tcase)) with open(log_file_name[i], "w") as f: - run_cmd = [app, "-c", test_cfg[i], "-p", "2", eth_up_dev[i], eth_cp_dev[i]] + run_cmd = [app, "--usecasefile", test_cfg[i], "--num_eth_vfs", "6", "--vf_addr_o_xu_a", vf_addr_o_xu[i][0], "--vf_addr_o_xu_b", vf_addr_o_xu[i][1],"--vf_addr_o_xu_c", vf_addr_o_xu[i][2]] #, stdout=f, stderr=f if (verbose==1): + if i == 0 or REM_O_RU_HOST == "": p = subprocess.Popen(run_cmd) else: + CMD = ' '.join([str(elem) for elem in run_cmd]) + ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs;" + CMD] + print(ssh) + print("my_cmd: ", ' '.join([str(elem) for elem in ssh])) + p = subprocess.Popen(ssh, shell=False) + else: + if i == 0 or REM_O_RU_HOST == "": p = subprocess.Popen(run_cmd, stdout=f, stderr=f) + else : + CMD = ' '.join([str(elem) for elem in run_cmd]) + ssh = ["ssh", "%s" % REM_O_RU_HOST, "cd " + xran_path + "/app"+"; hostname; pwd; pkill -9 sample-app; rm -rf ./logs; " + CMD] + p = subprocess.Popen(ssh, shell=False, stdout=f, stderr=f) + #stdout=subprocess.PIPE, stderr=subprocess.PIPE) + t = Timer(timeout_sec, p.kill) t.start() timer.append(t) @@ -663,8 +1000,18 @@ def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): print(strftime("%a, %d %b %Y %H:%M:%S +0000", gmtime())) i = 0 for p, f in processes: + try: p.communicate()[0] p.wait() + except (KeyboardInterrupt, SystemExit): + for i in range(2): + timer[i].cancel(); + timer[i].cancel(); + for pp, ff in processes: + pp.send_signal(signal.SIGINT) + pp.wait() + raise + if p.returncode != 0: print("Application {} failed p.returncode:{}".format(dic_xu.get(i), p.returncode)) print("FAIL") @@ -680,26 +1027,60 @@ def run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path): logging.info("O-DU and O-RU are done\n") - make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path) - - usecase_cfg = parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, test_cfg) + if REM_O_RU_HOST: + sys_cmd = "scp -r "+REM_O_RU_HOST+":"+ xran_path+"/app/logs/*.txt "+ xran_path+"/app/logs/" + print(sys_cmd) + os.system(sys_cmd) + sys_cmd = "scp -r "+REM_O_RU_HOST+":"+ xran_path+"/app/mlog-o-ru* "+ xran_path+"/app/" + print(sys_cmd) + os.system(sys_cmd) - res = compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, 0) + make_copy_mlog(rantech, cat, mu, bw, tcase, xran_path) + #oXuNum check only O-RU 0 for now + if 'oXuOwdmEnabled==1' in globals(): + OwdmTest=1 + else: + OwdmTest=0 + + for o_xu_id in range(0, oXuNum): + o_xu_test_cfg = [] + if o_xu_id == 0: + o_xu_test_cfg.append(usecase_dirname+"/"+oXuCfgFile0) + elif o_xu_id == 1: + o_xu_test_cfg.append(usecase_dirname+"/"+oXuCfgFile1) + elif o_xu_id == 2: + o_xu_test_cfg.append(usecase_dirname+"/"+oXuCfgFile2) + elif o_xu_id == 3: + o_xu_test_cfg.append(usecase_dirname+"/"+oXuCfgFile3) + + logging.info("O-RU %d parse config files %s\n", o_xu_id, o_xu_test_cfg) + + usecase_cfg_per_o_ru = parse_dat_file(rantech, cat, mu, bw, tcase, xran_path, o_xu_test_cfg) + + res = compare_results(o_xu_id,rantech, cat, mu, bw, tcase, xran_path, o_xu_test_cfg, 0) + if OwdmTest == 1: + # overwrite PASS/FAIL in res if the owd tests have failed + res1 = check_owdm_test_results(xran_path, o_xu_id) + print("res1 :", res1) + if res1 !=0 : + res = -1 if res != 0: os.chdir(wd) print("FAIL") + del_dat_file_vars(usecase_cfg_per_o_ru) return res - res = compare_resuts(rantech, cat, mu, bw, tcase, xran_path, test_cfg, 1) + res = compare_results(o_xu_id, rantech, cat, mu, bw, tcase, xran_path, o_xu_test_cfg, 1) if res != 0: os.chdir(wd) print("FAIL") + del_dat_file_vars(usecase_cfg_per_o_ru) return res os.chdir(wd) print("PASS") - del_dat_file_vars(usecase_cfg) + del_dat_file_vars(usecase_cfg_per_o_ru) return res @@ -707,10 +1088,14 @@ def main(): test_results = [] test_executed_total = 0 run_total = 0 + test_fail_cnt = 0 + test_pass_cnt = 0 cat = 0 mu = 0 bw = 0 tcase = 0 + tcase_description = "n/a" + """Processes input files to produce IACA files""" # Find path to XRAN if os.getenv("XRAN_DIR") is not None: @@ -724,20 +1109,38 @@ def main(): host_name = socket.gethostname() logging.info("host: %s Started script: master.py from XRAN path %s",host_name, xran_path) - #custom config for dev station + options = parse_args(sys.argv[1:]) + rem_o_ru_host = options.rem_o_ru_host + if host_name == "sc12-xran-sub6": - eth_cp_dev[0] = "0000:21:02.1" - eth_cp_dev[1] = "0000:21:0a.1" - eth_up_dev[0] = "0000:21:02.0" - eth_up_dev[1] = "0000:21:0a.0" + if rem_o_ru_host: + vf_addr_o_xu = vf_addr_o_xu_sc12_cvl + else: + vf_addr_o_xu = vf_addr_o_xu_sc12 + elif host_name == "csl-npg-scs1-30": + vf_addr_o_xu = vf_addr_o_xu_scs1_30 + elif host_name == "npg-scs1-repo.la.intel.com": + vf_addr_o_xu = vf_addr_o_xu_scs1_repo + elif host_name == "icelake-scs1-1": + vf_addr_o_xu = vf_addr_o_xu_icelake_scs1_1 + elif host_name == "icx-npg-scs1-coyote4": + vf_addr_o_xu = vf_addr_o_xu_icx_npg_scs1_coyote4 + elif host_name == "csl-npg-scs1-35": + vf_addr_o_xu = vf_addr_o_xu_scs1_35 + elif host_name == "csl-npg-scs1-33": + vf_addr_o_xu = vf_addr_o_xu_csl_npg_scs1_33 + else: + vf_addr_o_xu = vf_addr_o_xu_jenkins + + print(vf_addr_o_xu[0][0],vf_addr_o_xu[0][1],vf_addr_o_xu[0][2]) + print(vf_addr_o_xu[1][0],vf_addr_o_xu[1][1],vf_addr_o_xu[1][2]) # Parse input arguments - if len(sys.argv) == 1 : + if len(sys.argv) == 1 or (len(sys.argv) == 3 and rem_o_ru_host): run_total = len(all_test_cases) print(run_total) print("Run All test cases {}\n".format(run_total)) else: - options = parse_args(sys.argv[1:]) rantech = options.rantech cat = options.category mu = options.numerology @@ -745,6 +1148,7 @@ def main(): tcase = options.testcase verbose = options.verbose + print(rem_o_ru_host) if (run_total): for test_run_ix in range(0, run_total): @@ -753,22 +1157,23 @@ def main(): mu = all_test_cases[test_run_ix][2] bw = all_test_cases[test_run_ix][3] tcase = all_test_cases[test_run_ix][4] + tcase_description = all_test_cases[test_run_ix][5] verbose = 0 - logging.info("Test# %d out of %d: ran %d cat %d mu %d bw %d test case %d\n",test_run_ix, run_total, rantech, cat, mu, bw, tcase) - res = run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path) + logging.info("Test# %d out of %d [PASS %d FAIL %d]: ran %d cat %d mu %d bw %d test case %d [%s]\n",test_run_ix, run_total, test_pass_cnt, test_fail_cnt, rantech, cat, mu, bw, tcase, tcase_description) + res = run_tcase(rem_o_ru_host, rantech, cat, mu, bw, tcase, verbose, xran_path, vf_addr_o_xu) if (res != 0): - test_results.append((rantech, cat, mu, bw, tcase,'FAIL')) + test_fail_cnt += 1 + test_results.append((rantech, cat, mu, bw, tcase,'FAIL', tcase_description)) continue - test_results.append((rantech, cat, mu, bw, tcase,'PASS')) - - with open('testresult.txt', 'w') as reshandle: - json.dump(test_results, reshandle) + test_pass_cnt += 1 + test_results.append((rantech, cat, mu, bw, tcase,'PASS', tcase_description)) else: - res = run_tcase(rantech, cat, mu, bw, tcase, verbose, xran_path) + res = run_tcase(rem_o_ru_host, rantech, cat, mu, bw, tcase, verbose, xran_path, vf_addr_o_xu) if (res != 0): test_results.append((rantech, cat, mu, bw, tcase,'FAIL')) + else: test_results.append((rantech, cat, mu, bw, tcase,'PASS')) with open('testresult.txt', 'w') as reshandle: @@ -777,6 +1182,12 @@ def main(): return res if __name__ == '__main__': + print("Python version") + print (sys.version) + print("Version info.") + print (sys.version_info) + if (sys.version_info[0] < 3): + raise Exception ("Must be Python 3") START_TIME = datetime.now() res = main() END_TIME = datetime.now() diff --git a/fhi_lib/test/test_xran/Makefile b/fhi_lib/test/test_xran/Makefile index d5709b8..ebe415e 100644 --- a/fhi_lib/test/test_xran/Makefile +++ b/fhi_lib/test/test_xran/Makefile @@ -1,6 +1,6 @@ #/****************************************************************************** #* -#* Copyright (c) 2019 Intel. +#* Copyright (c) 2020 Intel. #* #* Licensed under the Apache License, Version 2.0 (the "License"); #* you may not use this file except in compliance with the License. @@ -50,7 +50,9 @@ endif RTE_TARGET ?= x86_64-native-linuxapp-icc -RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +RTE_LIBS = $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --static --libs libdpdk) +RTE_INC := $(shell PKG_CONFIG_PATH=/usr/lib64/pkgconfig:$(RTE_SDK)/build/meson-uninstalled pkgconf --cflags-only-I libdpdk) + # Where to find user code. COMMON_TEST_DIR = $(XRAN_DIR)/test/common @@ -64,7 +66,7 @@ USER_API = $(XRAN_DIR)/lib/api CPPFLAGS += -isystem $(GTEST_ROOT)/include # Flags passed to the C++ compiler. -CXXFLAGS += -g -std=gnu++11 -Wall -Wextra -pthread -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC) +CXXFLAGS += -g -std=c++14 -Wall -Wextra -pthread -mcmodel=large -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I $(COMMON_TEST_DIR) -I$(RTE_INC) # All tests produced by this Makefile. Remember to add new tests you # created to the list. @@ -75,9 +77,6 @@ TESTS = unittests GTEST_HEADERS = $(GTEST_ROOT)/include/gtest/*.h \ $(GTEST_ROOT)/include/gtest/internal/*.h -#RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_mempool_ring -Wl,-lrte_pci -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_net -Wl,-lrte_distributor -Wl,-lrte_reorder -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_jobstats -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,-lrte_vhost -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_cryptodev -Wl,-lrte_mempool -Wl,-lrte_ring -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_null -Wl,-lrte_pdump -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive -RTE_LIBS = -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,-lrte_flow_classify -Wl,--whole-archive -Wl,-lrte_pipeline -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_table -Wl,--no-whole-archive -Wl,--whole-archive -Wl,-lrte_port -Wl,--no-whole-archive -Wl,-lrte_pdump -Wl,-lrte_distributor -Wl,-lrte_ip_frag -Wl,-lrte_meter -Wl,-lrte_lpm -Wl,--whole-archive -Wl,-lrte_acl -Wl,--no-whole-archive -Wl,-lrte_jobstats -Wl,-lrte_metrics -Wl,-lrte_bitratestats -Wl,-lrte_latencystats -Wl,-lrte_power -Wl,-lrte_efd -Wl,-lrte_bpf -Wl,--whole-archive -Wl,-lrte_cfgfile -Wl,-lrte_gro -Wl,-lrte_gso -Wl,-lrte_hash -Wl,-lrte_member -Wl,-lrte_vhost -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_net -Wl,-lrte_ethdev -Wl,-lrte_bbdev -Wl,-lrte_cryptodev -Wl,-lrte_security -Wl,-lrte_compressdev -Wl,-lrte_eventdev -Wl,-lrte_rawdev -Wl,-lrte_timer -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_pci -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_reorder -Wl,-lrte_sched -Wl,-lrte_kni -Wl,-lrte_common_octeontx -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_bus_dpaa -Wl,-lrte_common_dpaax -Wl,-lrte_stack -Wl,-lrte_bus_fslmc -Wl,-lrte_mempool_bucket -Wl,-lrte_mempool_stack -Wl,-lrte_mempool_dpaa -Wl,-lrte_mempool_dpaa2 -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_ark -Wl,-lrte_pmd_iavf -Wl,-lrte_pmd_avp -Wl,-lrte_pmd_axgbe -Wl,-lrte_pmd_bnxt -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_dpaa -Wl,-lrte_pmd_dpaa2 -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ena -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_failsafe -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_kni -Wl,-lrte_pmd_lio -Wl,-lrte_pmd_nfp -Wl,-lrte_pmd_null -Wl,-lrte_pmd_qede -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_softnic -Wl,-lrte_pmd_tap -Wl,-lrte_pmd_thunderx_nicvf -Wl,-lrte_pmd_vdev_netvsc -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_vhost -Wl,-lrte_pmd_ifc -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_bus_vmbus -Wl,-lrte_pmd_netvsc -Wl,-lrte_pmd_bbdev_null -Wl,-lrte_pmd_null_crypto -Wl,-lrte_pmd_crypto_scheduler -Wl,-lrte_pmd_dpaa2_sec -Wl,-lrte_pmd_dpaa_sec -Wl,-lrte_pmd_virtio_crypto -Wl,-lrte_pmd_octeontx_zip -Wl,-lrte_pmd_qat -Wl,-lrte_pmd_skeleton_event -Wl,-lrte_pmd_sw_event -Wl,-lrte_pmd_octeontx_ssovf -Wl,-lrte_pmd_dpaa_event -Wl,-lrte_pmd_dpaa2_event -Wl,-lrte_mempool_octeontx -Wl,-lrte_pmd_octeontx -Wl,-lrte_pmd_opdl_event -Wl,-lrte_rawdev_skeleton -Wl,-lrte_rawdev_dpaa2_cmdif -Wl,-lrte_rawdev_dpaa2_qdma -Wl,-lrte_bus_ifpga -Wl,--no-whole-archive -Wl,-lrt -Wl,-lm -Wl,-lnuma -Wl,-ldl -Wl, - CFLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -fdata-sections \ -ffunction-sections \ @@ -85,23 +84,29 @@ CFLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ -Wall \ -Wimplicit-function-declaration \ -wd1786 \ - -I$(USER_DIR) -I$(USER_API) -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I$(RTE_INC) + -mcmodel=large \ + -I$(USER_API) -I$(USER_DIR) -I$(USER_ETH) -I$(MLOG_DIR)/source -I$(RTE_INC) C_SRC = \ - $(USER_ETH)/ethdi.c \ - $(USER_ETH)/ethernet.c \ - $(USER_DIR)/xran_up_api.c \ - $(USER_DIR)/xran_sync_api.c \ - $(USER_DIR)/xran_timer.c \ - $(USER_DIR)/xran_cp_api.c \ - $(USER_DIR)/xran_transport.c \ - $(USER_DIR)/xran_common.c \ - $(USER_DIR)/xran_ul_tables.c \ - $(USER_DIR)/xran_frame_struct.c \ + $(USER_ETH)/ethdi.c \ + $(USER_ETH)/ethernet.c \ + $(USER_DIR)/xran_up_api.c \ + $(USER_DIR)/xran_sync_api.c \ + $(USER_DIR)/xran_timer.c \ + $(USER_DIR)/xran_cp_api.c \ + $(USER_DIR)/xran_transport.c \ + $(USER_DIR)/xran_common.c \ + $(USER_DIR)/xran_ul_tables.c \ + $(USER_DIR)/xran_frame_struct.c \ $(USER_DIR)/xran_app_frag.c \ - $(USER_DIR)/xran_main.c - -# $(USER_DIR)/xran_compression.c + $(USER_DIR)/xran_dev.c \ + $(USER_DIR)/xran_rx_proc.c \ + $(USER_DIR)/xran_tx_proc.c \ + $(USER_DIR)/xran_cp_proc.c \ + $(USER_DIR)/xran_cb_proc.c \ + $(USER_DIR)/xran_mem_mgr.c \ + $(USER_DIR)/xran_main.c \ + $(USER_DIR)/xran_delay_measurement.c CC_SRC = \ $(COMMON_TEST_DIR)/xranlib_unit_test_main.cc \ @@ -110,8 +115,10 @@ CC_SRC = \ prach_functional.cc \ prach_performance.cc \ u_plane_functional.cc \ + u_plane_performance.cc \ init_sys_functional.cc \ compander_functional.cc \ + mod_compression_unit_test.cc \ unittests.cc # u_plane_performance.cc \ @@ -122,44 +129,125 @@ CPP_SRC = $(COMMON_TEST_DIR)/common.cpp \ $(USER_DIR)/xran_bfp_cplane8.cpp \ $(USER_DIR)/xran_bfp_cplane16.cpp \ $(USER_DIR)/xran_bfp_cplane32.cpp \ - $(USER_DIR)/xran_bfp_cplane64.cpp + $(USER_DIR)/xran_bfp_cplane64.cpp \ + $(USER_DIR)/xran_bfp_uplane_9b16rb.cpp \ + $(USER_DIR)/xran_bfp_uplane.cpp \ + $(USER_DIR)/xran_mod_compression.cpp + +CPP_SRC_SNC = $(USER_DIR)/xran_compression_snc.cpp \ + $(USER_DIR)/xran_bfp_cplane8_snc.cpp \ + $(USER_DIR)/xran_bfp_cplane16_snc.cpp \ + $(USER_DIR)/xran_bfp_cplane32_snc.cpp \ + $(USER_DIR)/xran_bfp_cplane64_snc.cpp \ + $(USER_DIR)/xran_bfp_uplane_snc.cpp + C_OBJS := $(patsubst %.c,%.o,$(C_SRC)) CC_OBJS := $(patsubst %.cc,%.o,$(CC_SRC)) CPP_OBJS := $(patsubst %.cpp,%.o,$(CPP_SRC)) +CPP_SNC_OBJS := $(patsubst %.cpp,%.o,$(CPP_SRC_SNC)) + +CPPFLAGS += -I$(USER_DIR) -I$(USER_API) + +#-qopt-report=5 -qopt-matmul -qopt-report-phase=all +CPP_COMP := -O3 -DNDEBUG -xcore-avx512 -fPIE -restrict -fasm-blocks +CPP_COMP_SNC := -O3 -DNDEBUG -march=icelake-server -fPIE -restrict -fasm-blocks -CPPFLAGS += -I$(USER_DIR) -I$(USER_API) +CPP_COMP := $(CPP_COMP) +CPP_COMP_SNC := $(CPP_COMP_SNC) + +ifeq ($(GEN_ASM), 1) +CPP_ASMS := $(patsubst %.cpp,%.asm,$(CPP_SRC)) +CPP_SNC_ASMS := $(patsubst %.cpp,%.asm,$(CPP_SRC_SNC)) +CPP_COMP += -qopt-report=5 -qopt-matmul -qopt-report-phase=all +CPP_COMP_SNC += -qopt-report=5 -qopt-matmul -qopt-report-phase=all +endif + +PROJECT_DEP_FILE := $(TESTS).dep + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) +GENERATE_DEPS := +else +C_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(C_SRC))) +CC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CC_SRC))) +CPP_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CPP_SRC))) +CPP_SNC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CPP_SRC_SNC))) +GENERATE_DEPS := generate_deps +endif -CPP_COMP = -O3 -xcore-avx512 -restrict -g -fasm-blocks # House-keeping build targets. -all : echo_start_build $(TESTS) +all : echo_start_build $(GENERATE_DEPS) $(TESTS) clean : @echo [CLEAN] - rm -f $(TESTS) *.o $(COMMON_TEST_DIR)/*.o $(USER_DIR)/*.o $(USER_ETH)/*.o + @$(RM) -f $(TESTS) *.o $(COMMON_TEST_DIR)/*.o $(USER_DIR)/*.o $(USER_ETH)/*.o \ + *.asm $(COMMON_TEST_DIR)/*.asm $(USER_DIR)/*.asm $(USER_ETH)/*.asm \ + *.asm $(COMMON_TEST_DIR)/*.asm2 $(USER_DIR)/*.asm2 $(USER_ETH)/*.asm2 \ + *.optrpt $(COMMON_TEST_DIR)/*.optrpt $(USER_DIR)/*.optrpt $(USER_ETH)/*.optrpt;\ + $(RM) $(PROJECT_DEP_FILE) -.PHONY: xclean +.PHONY: xclean xclean: clean +.PHONY : clear_dep +clear_dep: + @$(RM) $(PROJECT_DEP_FILE) + @echo [DEP] $(PROJECT_DEP_FILE) + +$(C_DEPS) : + @$(CC) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(patsubst %.c,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CFLAGS) >> $(PROJECT_DEP_FILE) + +$(CC_DEPS) : + @$(CC) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(patsubst %.cc,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CPPFLAGS) $(CXXFLAGS) >> $(PROJECT_DEP_FILE) + +$(CPP_DEPS) : + @$(CPP) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(patsubst %.cpp,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP) >> $(PROJECT_DEP_FILE) + +$(CPP_SNC_DEPS) : + @$(CPP) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(patsubst %.cpp,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP_SNC) >> $(PROJECT_DEP_FILE) + +.PHONY : generate_deps +generate_deps : clear_dep $(C_DEPS) $(CC_DEPS) $(CPP_DEPS) $(CPP_SNC_DEPS) + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) + +include $(PROJECT_DEP_FILE) + +endif + .PHONY : echo_start_build echo_start_build : @echo Build Tests with @echo $(USER_DIR) @echo $(USER_API) -$(CC_OBJS) : +$(CC_OBJS) : $(CC_SRC) @echo "[CC] $@" @$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o"$@" $(patsubst %.o,%.cc,$@) -$(CPP_OBJS) : +$(CPP_ASMS) : + @echo "[CPP->ASM] $@" + @$(CXX) -S $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP) -fsource-asm -save-temps -o"$@" $(patsubst %.asm,%.cpp,$@) + @cat $@ | grep -v '^..LN' |grep -v ' .loc' > $@2 + +$(CPP_OBJS) : $(CPP_ASMS) @echo "[CPP] $@" @$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP) -o"$@" $(patsubst %.o,%.cpp,$@) +$(CPP_SNC_ASMS) : + @echo "[CPP-SNC->ASM] $@" + @$(CXX) -S $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP_SNC) -fsource-asm -save-temps -o"$@" $(patsubst %.asm,%.cpp,$@) + @cat $@ | grep -v '^..LN' |grep -v ' .loc' > $@2 + +$(CPP_SNC_OBJS) : $(CPP_SNC_ASMS) + @echo "[CPP-SNC] $@" + @$(CXX) -c $(CPPFLAGS) $(CXXFLAGS) $(CPP_COMP_SNC) -o"$@" $(patsubst %.o,%.cpp,$@) + $(C_OBJS) : @echo "[C] $@" @$(CC) -c $(CFLAGS) -o"$@" $(patsubst %.o,%.c,$@) -unittests : $(CC_OBJS) $(CPP_OBJS) $(C_OBJS) $(GTEST_ROOT)/libgtest.a +$(TESTS) : $(CC_OBJS) $(CPP_OBJS) $(CPP_SNC_OBJS) $(C_OBJS) $(GTEST_ROOT)/libgtest.a @echo "[LD] $@" $(CXX) $(CPPFLAGS) $(CXXFLAGS) -L$(MLOG_DIR)/bin -Wl, $(RTE_LIBS) -lpthread -lnuma $^ -o $@ diff --git a/fhi_lib/test/test_xran/c_plane_tests.cc b/fhi_lib/test/test_xran/c_plane_tests.cc index b9f7cf6..df6bd43 100644 --- a/fhi_lib/test/test_xran/c_plane_tests.cc +++ b/fhi_lib/test/test_xran/c_plane_tests.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,7 +28,16 @@ #include -#define DELETE_ARRAY(x) { if(x) { delete[] x; x = nullptr; } } +#define DELETE_ARRAY(x) { if(x) { delete[] x; x = nullptr; } } + +#define XRAN_MAX_BUFLEN_EXT11 (MAX_RX_LEN - \ + (RTE_PKTMBUF_HEADROOM \ + + sizeof(struct xran_ecpri_hdr) \ + + sizeof(struct xran_cp_radioapp_common_header) \ + + sizeof(struct xran_cp_radioapp_section1) \ + + sizeof(union xran_cp_radioapp_section_ext6) \ + + sizeof(union xran_cp_radioapp_section_ext10) \ + )) const std::string module_name = "C-Plane"; @@ -38,13 +47,23 @@ extern "C" { /* wrapper function for performace tests to reset mbuf */ -int xran_ut_prepare_cp(struct rte_mbuf *mbuf, struct xran_cp_gen_params *params, +int xran_ut_prepare_cp(struct xran_cp_gen_params *params, uint8_t cc_id, uint8_t ant_id, uint8_t seq_id) { - rte_pktmbuf_reset(mbuf); - return(xran_prepare_ctrl_pkt(mbuf, params, cc_id, ant_id, seq_id)); -} + register int ret; + register struct rte_mbuf *mbuf; + mbuf = xran_ethdi_mbuf_alloc(); + if(mbuf == NULL) { + printf("Failed to allocate buffer!\n"); + return (-1); + } + + ret = xran_prepare_ctrl_pkt(mbuf, params, cc_id, ant_id, seq_id); + rte_pktmbuf_free(mbuf); + + return (ret); +} void cput_fh_rx_callback(void *pCallbackTag, xran_status_t status) { @@ -64,7 +83,7 @@ class C_plane: public KernelTests { private: struct xran_section_gen_info *m_pSectGenInfo = NULL; - struct xran_section_gen_info *m_pSectResult = NULL; + struct xran_section_recv_info *m_pSectResult = NULL; struct sectinfo { uint16_t sectionId; @@ -88,6 +107,12 @@ private: struct xran_sectionext3_info ext3; struct xran_sectionext4_info ext4; struct xran_sectionext5_info ext5; + struct xran_sectionext6_info ext6; + struct xran_sectionext7_info ext7; + struct xran_sectionext8_info ext8; + struct xran_sectionext9_info ext9; + struct xran_sectionext10_info ext10; + struct xran_sectionext11_info ext11; } u; }; @@ -95,11 +120,11 @@ protected: int m_maxSections = 8; /* not used */ int m_numSections; - struct rte_mbuf *m_pTestBuffer; + struct rte_mbuf *m_pTestBuffer = nullptr; struct xran_cp_gen_params m_params; struct xran_recv_packet_info m_pktInfo; - struct xran_cp_gen_params m_result; + struct xran_cp_recv_params m_result; struct xran_sectionext1_info m_temp_ext1[XRAN_MAX_PRBS]; @@ -129,12 +154,19 @@ protected: struct xran_sectionext1_info m_ext1; - int16_t m_bfwIQ[XRAN_MAX_BFW_N*2]; - + int m_antElmTRx; + struct rte_mbuf_ext_shared_info m_extSharedInfo; + uint8_t *m_pBfwIQ_ext = nullptr; + int16_t *m_pBfw_src[XRAN_MAX_SET_BFWS]; + int16_t m_pBfw_rx[XRAN_MAX_SET_BFWS][MAX_RX_LEN]; + struct xran_ext11_bfw_info m_bfwInfo[XRAN_MAX_SET_BFWS]; void SetUp() override { int i, j; + bool flag_skip; + int ext_type; + std::string ext_name; init_test("C_Plane"); @@ -196,24 +228,38 @@ protected: m_sections[i].exts = get_input_parameter>("sections", i, "exts"); } + /* allocate and prepare required data storage */ + m_pSectGenInfo = new struct xran_section_gen_info [m_numSections]; + ASSERT_NE(m_pSectGenInfo, nullptr); + m_params.sections = m_pSectGenInfo; + + m_pSectResult = new struct xran_section_recv_info [m_numSections]; + ASSERT_NE(m_pSectResult, nullptr); + m_result.sections = m_pSectResult; + /* reading configurations of section extension */ m_nextcfgs = get_input_subsection_size("extensions"); if(m_nextcfgs) { m_extcfgs = new struct extcfginfo [m_nextcfgs]; + flag_skip = false; for(i=0; i < m_nextcfgs; i++) { - std::vector csf; - std::vector mcScaleReMask; - std::vector mcScaleOffset; - - m_extcfgs[i].type = get_input_parameter("extensions", i, "type"); - m_extcfgs[i].name = get_input_parameter("extensions", i, "name"); + std::vector beamIDs; - switch(m_extcfgs[i].type) { + ext_type = get_input_parameter("extensions", i, "type"); + switch(ext_type) { case XRAN_CP_SECTIONEXTCMD_1: - /* Skip section extension type 1 since it has separate function */ - std::cout << "### Skip Extension 1 configuration !!\n" << std::endl; - continue; + /* if section extension type 1 is present, then ignore other extensions */ + if(i != 0 && m_nextcfgs != 1) { + std::cout << "### Extension 1 configuration, ignore other extensions !!\n" << std::endl; + } + flag_skip = true; + m_nextcfgs = 1; + i = 0; + m_extcfgs[i].u.ext1.bfwCompMeth = get_input_parameter ("extensions", i, "bfwCompMeth"); + m_extcfgs[i].u.ext1.bfwIqWidth = get_input_parameter ("extensions", i, "bfwIqWidth"); + m_antElmTRx = get_input_parameter ("extensions", i, "antelm_trx"); + break; case XRAN_CP_SECTIONEXTCMD_2: m_extcfgs[i].u.ext2.bfAzPtWidth = get_input_parameter("extensions", i, "bfAzPtWidth") & 0x7; @@ -248,6 +294,11 @@ protected: break; case XRAN_CP_SECTIONEXTCMD_5: + { + std::vector csf; + std::vector mcScaleReMask; + std::vector mcScaleOffset; + m_extcfgs[i].u.ext5.num_sets = get_input_parameter("extensions", i, "num_sets"); if(m_extcfgs[i].u.ext5.num_sets > XRAN_MAX_MODCOMP_ADDPARMS) FAIL() << "Invalid number of sets in extension 5!"; @@ -261,39 +312,115 @@ protected: || mcScaleOffset.size() != m_extcfgs[i].u.ext5.num_sets) FAIL() << "Invalid configuration in extension 5 - different size!"; - for(int ii=0; ii < m_extcfgs[i].u.ext5.num_sets; ii++) { - m_extcfgs[i].u.ext5.mc[ii].csf = csf[ii]; - m_extcfgs[i].u.ext5.mc[ii].mcScaleReMask = mcScaleReMask[ii]; - m_extcfgs[i].u.ext5.mc[ii].mcScaleOffset = mcScaleOffset[ii]; + for(j=0; j < m_extcfgs[i].u.ext5.num_sets; j++) { + m_extcfgs[i].u.ext5.mc[j].csf = csf[j]; + m_extcfgs[i].u.ext5.mc[j].mcScaleReMask = mcScaleReMask[j]; + m_extcfgs[i].u.ext5.mc[j].mcScaleOffset = mcScaleOffset[j]; } + } + break; + + case XRAN_CP_SECTIONEXTCMD_6: + m_extcfgs[i].u.ext6.rbgSize = get_input_parameter ("extensions", i, "rbgSize"); + m_extcfgs[i].u.ext6.rbgMask = get_input_parameter("extensions", i, "rbgMask"); + m_extcfgs[i].u.ext6.symbolMask = get_input_parameter("extensions", i, "symbolMask"); + break; + + case XRAN_CP_SECTIONEXTCMD_10: + m_extcfgs[i].u.ext10.numPortc = get_input_parameter ("extensions", i, "numPortc"); + m_extcfgs[i].u.ext10.beamGrpType= get_input_parameter ("extensions", i, "beamGrpType"); + switch(m_extcfgs[i].u.ext10.beamGrpType) { + case XRAN_BEAMGT_COMMON: + case XRAN_BEAMGT_MATRIXIND: + break; + case XRAN_BEAMGT_VECTORLIST: + beamIDs = get_input_parameter>("extensions", i, "beamID"); + for(j=0; j < m_extcfgs[i].u.ext10.numPortc; j++) + m_extcfgs[i].u.ext10.beamID[j] = beamIDs[j]; + break; + default: + FAIL() << "Invalid Beam Group Type - " << m_extcfgs[i].u.ext10.beamGrpType << std::endl; + } + break; + + case XRAN_CP_SECTIONEXTCMD_11: + { + int temp; + /* if section extension type 11 is present, then ignore other extensions */ + if(i != 0 && m_nextcfgs != 1) { + std::cout << "### Extension 11 configuration, ignore other extensions !!\n" << std::endl; + } + flag_skip = true; + m_nextcfgs = 1; + i = 0; + + m_extcfgs[i].u.ext11.RAD = get_input_parameter ("extensions", i, "RAD"); + m_extcfgs[i].u.ext11.disableBFWs = get_input_parameter ("extensions", i, "disableBFWs"); + m_extcfgs[i].u.ext11.numBundPrb = get_input_parameter ("extensions", i, "numBundPrb"); + m_extcfgs[i].u.ext11.bfwCompMeth = get_input_parameter ("extensions", i, "bfwCompMeth"); + m_extcfgs[i].u.ext11.bfwIqWidth = get_input_parameter ("extensions", i, "bfwIqWidth"); + m_extcfgs[i].u.ext11.numSetBFWs = get_input_parameter ("extensions", i, "numSetBFWs"); + m_antElmTRx = get_input_parameter ("extensions", i, "antelm_trx"); + beamIDs = get_input_parameter>("extensions", i, "beamID"); + + /* Allocate buffers */ + m_extcfgs[i].u.ext11.maxExtBufSize = MAX_RX_LEN; + m_pBfwIQ_ext = (uint8_t *)xran_malloc(m_extcfgs[i].u.ext11.maxExtBufSize); + m_extcfgs[i].u.ext11.pExtBuf = m_pBfwIQ_ext; + + for(j = 0; j < XRAN_MAX_SET_BFWS; j++) { + m_pBfw_src[j] = new int16_t [XRAN_MAX_BFW_N]; + memset(m_pBfw_src[j], j+1, XRAN_MAX_BFW_N); + } + + for(j=0; j < m_extcfgs[i].u.ext11.numSetBFWs; j++) { + m_bfwInfo[j].pBFWs = (uint8_t *)(m_pBfw_src[j]); + m_bfwInfo[j].beamId = beamIDs[j]; + } + + /* Initialize Shared information for external buffer */ + m_extSharedInfo.free_cb = NULL; + m_extSharedInfo.fcb_opaque = NULL; + rte_mbuf_ext_refcnt_update(&m_extSharedInfo, 0); + m_extcfgs[i].u.ext11.pExtBufShinfo = &m_extSharedInfo; + + /* Check all BFWs can be fit with given buffer */ + temp = xran_cp_estimate_max_set_bfws(m_antElmTRx, m_extcfgs[i].u.ext11.bfwIqWidth, + m_extcfgs[i].u.ext11.bfwCompMeth, m_extcfgs[i].u.ext11.maxExtBufSize); + if(m_extcfgs[i].u.ext11.numSetBFWs > temp) { + FAIL() << "Too many sets of BFWs - " << m_extcfgs[i].u.ext11.numSetBFWs + << " (max " << temp << " for " << m_extcfgs[i].u.ext11.maxExtBufSize << std::endl; + } + + temp = xran_cp_prepare_ext11_bfws(m_extcfgs[i].u.ext11.numSetBFWs, m_antElmTRx, + m_extcfgs[i].u.ext11.bfwIqWidth, m_extcfgs[i].u.ext11.bfwCompMeth, + m_pBfwIQ_ext, XRAN_MAX_BUFLEN_EXT11, m_bfwInfo); + if(temp < 0) { + FAIL() << "Fail to prepare BFWs!" << std::endl; + }; + m_extcfgs[i].u.ext11.totalBfwIQLen = temp; + } break; default: - FAIL() << "Invalid Section Type Extension - " << m_extcfgs[i].type << std::endl; + FAIL() << "Invalid Section Type Extension - " << ext_type << std::endl; continue; - } /* switch(m_extcfgs[i].type) */ + } /* switch(ext_type) */ + + m_extcfgs[i].type = ext_type; + m_extcfgs[i].name = get_input_parameter("extensions", i, "name"); + + if(flag_skip) + break; } /* for(i=0; i < m_nextcfgs; i++) */ } else { m_extcfgs = nullptr; } - /* allocate and prepare required data storage */ - m_pSectGenInfo = new struct xran_section_gen_info [m_numSections]; - ASSERT_NE(m_pSectGenInfo, nullptr); - m_params.sections = m_pSectGenInfo; - - m_pSectResult = new struct xran_section_gen_info [m_numSections]; - ASSERT_NE(m_pSectResult, nullptr); - m_result.sections = m_pSectResult; - m_ext1_dst_len = 9600; m_p_ext1_dst = new int8_t [m_ext1_dst_len]; m_p_bfw_iq_src = new int16_t [9600/2]; - - /* allocating an mbuf for packet generatrion */ - m_pTestBuffer = xran_ethdi_mbuf_alloc(); - ASSERT_FALSE(m_pTestBuffer == nullptr); } void TearDown() override @@ -303,6 +430,14 @@ protected: m_pTestBuffer = nullptr; } + if(m_pBfwIQ_ext){ + xran_free(m_pBfwIQ_ext); + m_pBfwIQ_ext = nullptr; + } + for(int i = 0; i < XRAN_MAX_SET_BFWS; i++) { + DELETE_ARRAY(m_pBfw_src[i]); + } + DELETE_ARRAY(m_extcfgs); DELETE_ARRAY(m_sections); DELETE_ARRAY(m_p_bfw_iq_src); @@ -315,13 +450,14 @@ protected: int prepare_extensions(void); void verify_sections(void); + void test_ext1(void); }; int C_plane::prepare_extensions() { - int i, numext, sect_num; + int i, j, numext, sect_num; int ext_id; for(sect_num=0; sect_num < m_numSections; sect_num++) { @@ -337,7 +473,7 @@ int C_plane::prepare_extensions() switch(m_extcfgs[ext_id].type) { case XRAN_CP_SECTIONEXTCMD_1: - std::cout << "Skip Extension 1 !!" << std::endl; +// std::cout << "Skip Extension 1 !!" << std::endl; continue; case XRAN_CP_SECTIONEXTCMD_2: m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext2); @@ -354,6 +490,23 @@ int C_plane::prepare_extensions() case XRAN_CP_SECTIONEXTCMD_5: m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext5); m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext5; + break; + case XRAN_CP_SECTIONEXTCMD_6: + m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext6); + m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext6; + break; + case XRAN_CP_SECTIONEXTCMD_10: + m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext10); + m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext10; + break; + case XRAN_CP_SECTIONEXTCMD_11: + m_params.sections[sect_num].exData[numext].len = sizeof(m_extcfgs[ext_id].u.ext11); + m_params.sections[sect_num].exData[numext].data = &m_extcfgs[ext_id].u.ext11; + + m_result.sections[sect_num].exts[numext].type = m_extcfgs[ext_id].type; + for(j=0 ; j < XRAN_MAX_SET_BFWS; j++) + m_result.sections[sect_num].exts[numext].u.ext11.bundInfo[j].pBFWs = (uint8_t *)m_pBfw_rx[j]; + break; default: std::cout << "Invalid Section Extension Type - " << (int)m_extcfgs[ext_id].type << std::endl; @@ -411,10 +564,10 @@ int C_plane::prepare_sections(void) } for(numsec=0; numsec < m_numSections; numsec++) { - m_params.sections[numsec].info.type = m_params.sectionType; // for database - m_params.sections[numsec].info.startSymId = m_params.hdr.startSymId; // for database - m_params.sections[numsec].info.iqWidth = m_params.hdr.iqWidth; // for database - m_params.sections[numsec].info.compMeth = m_params.hdr.compMeth; // for database + m_params.sections[numsec].info.type = m_params.sectionType; + m_params.sections[numsec].info.startSymId = m_params.hdr.startSymId; + m_params.sections[numsec].info.iqWidth = m_params.hdr.iqWidth; + m_params.sections[numsec].info.compMeth = m_params.hdr.compMeth; m_params.sections[numsec].info.id = m_sections[numsec].sectionId; m_params.sections[numsec].info.rb = m_sections[numsec].rb; m_params.sections[numsec].info.symInc = m_sections[numsec].symInc; @@ -435,7 +588,7 @@ int C_plane::prepare_sections(void) default: return (-1); } - } + } m_params.numSections = numsec; @@ -445,7 +598,7 @@ int C_plane::prepare_sections(void) void C_plane::verify_sections(void) { - int i,j; + int i,j,k; /* Verify the result */ EXPECT_TRUE(m_result.dir == m_params.dir); @@ -502,10 +655,10 @@ void C_plane::verify_sections(void) if(m_params.sections[i].info.ef) { //printf("[%d] %d == %d\n",i, m_result.sections[i].exDataSize, m_params.sections[i].exDataSize); - EXPECT_TRUE(m_result.sections[i].exDataSize == m_params.sections[i].exDataSize); + EXPECT_TRUE(m_result.sections[i].numExts == m_params.sections[i].exDataSize); for(j=0; j < m_params.sections[i].exDataSize; j++) { - EXPECT_TRUE(m_result.sections[i].exData[j].type == m_params.sections[i].exData[j].type); + EXPECT_TRUE(m_result.sections[i].exts[j].type == m_params.sections[i].exData[j].type); switch(m_params.sections[i].exData[j].type) { case XRAN_CP_SECTIONEXTCMD_1: @@ -514,9 +667,9 @@ void C_plane::verify_sections(void) int iq_size, parm_size, N; ext1_params = (struct xran_sectionext1_info *)m_params.sections[i].exData[j].data; - ext1_result = (struct xran_sectionext1_info *)m_result.sections[i].exData[j].data; + ext1_result = &m_result.sections[i].exts[j].u.ext1; - EXPECT_TRUE(ext1_result->bfwiqWidth == ext1_params->bfwiqWidth); + EXPECT_TRUE(ext1_result->bfwIqWidth == ext1_params->bfwIqWidth); EXPECT_TRUE(ext1_result->bfwCompMeth == ext1_params->bfwCompMeth); N = ext1_params->bfwNumber; @@ -541,7 +694,7 @@ void C_plane::verify_sections(void) } /* Get the number of BF weights */ - iq_size = N*ext1_params->bfwiqWidth*2; // total in bits + iq_size = N*ext1_params->bfwIqWidth*2; // total in bits parm_size = iq_size>>3; // total in bytes (/8) if(iq_size%8) parm_size++; // round up EXPECT_FALSE(std::memcmp(ext1_result->p_bfwIQ, ext1_params->p_bfwIQ, parm_size)); @@ -553,7 +706,7 @@ void C_plane::verify_sections(void) struct xran_sectionext2_info *ext2_params, *ext2_result; ext2_params = (struct xran_sectionext2_info *)m_params.sections[i].exData[j].data; - ext2_result = (struct xran_sectionext2_info *)m_result.sections[i].exData[j].data; + ext2_result = &m_result.sections[i].exts[j].u.ext2; if(ext2_params->bfAzPtWidth) { EXPECT_TRUE(ext2_result->bfAzPtWidth == ext2_params->bfAzPtWidth); @@ -583,7 +736,7 @@ void C_plane::verify_sections(void) struct xran_sectionext3_info *ext3_params, *ext3_result; ext3_params = (struct xran_sectionext3_info *)m_params.sections[i].exData[j].data; - ext3_result = (struct xran_sectionext3_info *)m_result.sections[i].exData[j].data; + ext3_result = &m_result.sections[i].exts[j].u.ext3; EXPECT_TRUE(ext3_result->layerId == ext3_params->layerId); EXPECT_TRUE(ext3_result->codebookIdx== ext3_params->codebookIdx); @@ -613,7 +766,7 @@ void C_plane::verify_sections(void) struct xran_sectionext4_info *ext4_params, *ext4_result; ext4_params = (struct xran_sectionext4_info *)m_params.sections[i].exData[j].data; - ext4_result = (struct xran_sectionext4_info *)m_result.sections[i].exData[j].data; + ext4_result = &m_result.sections[i].exts[j].u.ext4; EXPECT_TRUE(ext4_result->csf == ext4_params->csf); EXPECT_TRUE(ext4_result->modCompScaler == ext4_params->modCompScaler); @@ -626,7 +779,7 @@ void C_plane::verify_sections(void) int idx; ext5_params = (struct xran_sectionext5_info *)m_params.sections[i].exData[j].data; - ext5_result = (struct xran_sectionext5_info *)m_result.sections[i].exData[j].data; + ext5_result = &m_result.sections[i].exts[j].u.ext5; EXPECT_TRUE(ext5_result->num_sets == ext5_params->num_sets); for(idx=0; idx < ext5_params->num_sets; idx++) { @@ -636,150 +789,83 @@ void C_plane::verify_sections(void) } } break; - } - } - } - } - - return; -} - - -/*************************************************************************** - * Functional Test cases - ***************************************************************************/ - -TEST_P(C_plane, Section_Ext1) -{ - int i = 0, idRb; - int16_t *ptr = NULL; - int32_t nRbs = 36; - int32_t nAntElm = 64; - int8_t iqWidth = 16; - int8_t compMethod = XRAN_COMPMETHOD_NONE; - int8_t *p_ext1_dst = NULL; - int8_t *bfw_payload = NULL; - int32_t expected_len = (3+1)*nRbs + nAntElm*nRbs*4; - - int16_t ext_len = 9600; - int16_t ext_sec_total = 0; - int8_t * ext_buf = nullptr; - int8_t * ext_buf_init = nullptr; - - struct xran_section_gen_info* loc_pSectGenInfo = m_params.sections; - struct xran_sectionext1_info m_prep_ext1; - struct xran_cp_radioapp_section_ext1 *p_ext1; - struct rte_mbuf_ext_shared_info share_data; - struct rte_mbuf *mbuf = NULL; - - /* Configure section information */ - if(prepare_sections() < 0) { - FAIL() << "Invalid Section configuration\n"; - } + case XRAN_CP_SECTIONEXTCMD_6: + { + struct xran_sectionext6_info *ext6_params, *ext6_result; - if(prepare_extensions() < 0) { - FAIL() << "Invalid Section extension configuration\n"; - } + ext6_params = (struct xran_sectionext6_info *)m_params.sections[i].exData[j].data; + ext6_result = &m_result.sections[i].exts[j].u.ext6; - if(loc_pSectGenInfo->info.type == XRAN_CP_SECTIONTYPE_1) { - /* extType 1 only with Section 1 for now */ + EXPECT_TRUE(ext6_result->rbgSize == ext6_params->rbgSize); + EXPECT_TRUE(ext6_result->rbgMask == ext6_params->rbgMask); + EXPECT_TRUE(ext6_result->symbolMask == ext6_params->symbolMask); + } + break; + case XRAN_CP_SECTIONEXTCMD_10: + { + struct xran_sectionext10_info *ext10_params, *ext10_result; + int idx; - ext_buf = ext_buf_init = (int8_t*) xran_malloc(ext_len); - if (ext_buf) { - ptr = m_p_bfw_iq_src; + ext10_params = (struct xran_sectionext10_info *)m_params.sections[i].exData[j].data; + ext10_result = &m_result.sections[i].exts[j].u.ext10; - for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){ - ptr[idRb] = i; - i++; + EXPECT_TRUE(ext10_result->numPortc == ext10_params->numPortc); + EXPECT_TRUE(ext10_result->beamGrpType == ext10_params->beamGrpType); + if(ext10_result->beamGrpType == XRAN_BEAMGT_VECTORLIST) { + for(idx=0; idx < ext10_result->numPortc; idx++) + EXPECT_TRUE(ext10_result->beamID[idx] == ext10_params->beamID[idx]); + } + } + break; + case XRAN_CP_SECTIONEXTCMD_11: + { + struct xran_sectionext11_info *ext11_params; + struct xran_sectionext11_recv_info *ext11_result; + + ext11_params = (struct xran_sectionext11_info *)m_params.sections[i].exData[j].data; + ext11_result = &m_result.sections[i].exts[j].u.ext11; + + EXPECT_TRUE(ext11_result->RAD == ext11_params->RAD); + EXPECT_TRUE(ext11_result->disableBFWs == ext11_params->disableBFWs); + EXPECT_TRUE(ext11_result->numBundPrb == ext11_params->numBundPrb); + EXPECT_TRUE(ext11_result->bfwCompMeth == ext11_params->bfwCompMeth); + EXPECT_TRUE(ext11_result->bfwIqWidth == ext11_params->bfwIqWidth); + + + EXPECT_TRUE(ext11_result->numSetBFWs == ext11_params->numSetBFWs); + for(k=0; k < ext11_result->numSetBFWs; k++) { + EXPECT_TRUE(ext11_result->bundInfo[k].beamId == m_bfwInfo[k].beamId); +#if 0 + EXPECT_TRUE(ext11_result->bundInfo[k].BFWSize == ext11_params->BFWSize); + + if(ext11_result->bundInfo[k].pBFWs) + EXPECT_TRUE(memcmp(ext11_result->bundInfo[k].pBFWs, + ext11_params->bundInfo[k].pBFWs + ext11_params->bundInfo[k].offset + 4, + ext11_result->bundInfo[k].BFWSize) == 0); + switch(ext11_result->bfwCompMeth) { + case XRAN_BFWCOMPMETHOD_NONE: + break; + + case XRAN_BFWCOMPMETHOD_BLKFLOAT: + EXPECT_TRUE(ext11_result->bundInfo[k].bfwCompParam.exponent == ext11_params->bundInfo[k].bfwCompParam.exponent); + break; + + default: + FAIL() << "Invalid BfComp method - %d" << ext11_result->bfwCompMeth << std::endl; + } +#endif + } + } + break; + } + } } - - ext_buf += (RTE_PKTMBUF_HEADROOM + - sizeof (struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_common_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_len -= (RTE_PKTMBUF_HEADROOM + - sizeof(struct xran_ecpri_hdr) + - sizeof(struct xran_cp_radioapp_common_header) + - sizeof(struct xran_cp_radioapp_section1)); - - ext_sec_total = xran_cp_populate_section_ext_1((int8_t *)ext_buf, - ext_len, - m_p_bfw_iq_src, - nRbs, - nAntElm, - iqWidth, - compMethod); - - ASSERT_TRUE(ext_sec_total == expected_len); - p_ext1_dst = ext_buf; - - memset(&m_temp_ext1[0], 0, sizeof (struct xran_sectionext1_info)*XRAN_MAX_PRBS); - - idRb = 0; - do { - p_ext1 = (struct xran_cp_radioapp_section_ext1 *)p_ext1_dst; - bfw_payload = (int8_t*)(p_ext1+1); - p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN; - - m_temp_ext1[idRb].bfwNumber = nAntElm; - m_temp_ext1[idRb].bfwiqWidth = iqWidth; - m_temp_ext1[idRb].bfwCompMeth = compMethod; - m_temp_ext1[idRb].p_bfwIQ = (int16_t*)bfw_payload; - m_temp_ext1[idRb].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN; - - loc_pSectGenInfo->exData[idRb].type = XRAN_CP_SECTIONEXTCMD_1; - loc_pSectGenInfo->exData[idRb].len = sizeof(m_temp_ext1[idRb]); - loc_pSectGenInfo->exData[idRb].data = &m_temp_ext1[idRb]; - - idRb++; - }while(p_ext1->ef != XRAN_EF_F_LAST); - ASSERT_TRUE(idRb == nRbs); - - mbuf = xran_attach_cp_ext_buf(ext_buf_init, ext_buf, ext_sec_total, &share_data); - - /* Update section information */ - memset(&m_prep_ext1, 0, sizeof (struct xran_sectionext1_info)); - m_prep_ext1.bfwNumber = nAntElm; - m_prep_ext1.bfwiqWidth = iqWidth; - m_prep_ext1.bfwCompMeth = compMethod; - m_prep_ext1.p_bfwIQ = (int16_t*)ext_buf; - m_prep_ext1.bfwIQ_sz = ext_sec_total; - - - loc_pSectGenInfo->exData[0].type = XRAN_CP_SECTIONEXTCMD_1; - loc_pSectGenInfo->exData[0].len = sizeof(m_prep_ext1); - loc_pSectGenInfo->exData[0].data = &m_prep_ext1; - - loc_pSectGenInfo->info.ef = 1; - loc_pSectGenInfo->exDataSize = 1; /* append all extType1 as one shot - (as generated via xran_cp_populate_section_ext_1)*/ - - m_params.numSections = 1; - - /* Generating C-Plane packet */ - ASSERT_TRUE(xran_prepare_ctrl_pkt(/*m_pTestBuffer*/mbuf, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS); - - /** to match O-RU parsing */ - loc_pSectGenInfo->exDataSize = nRbs; - loc_pSectGenInfo->exData[0].len = sizeof(m_temp_ext1[0]); - loc_pSectGenInfo->exData[0].data = &m_temp_ext1[0]; - - /* Parsing generated packet */ - EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS); - } else { - FAIL() << "xran_malloc failed\n"; } - /* Verify the result */ - verify_sections(); - - if(ext_buf_init) - xran_free(ext_buf_init); - } + return; } -TEST_P(C_plane, Section_Ext1_9bit) +void C_plane::test_ext1(void) { int i = 0, idRb; int16_t *ptr = NULL; @@ -803,14 +889,23 @@ TEST_P(C_plane, Section_Ext1_9bit) struct rte_mbuf_ext_shared_info share_data; struct rte_mbuf *mbuf = NULL; - /* Configure section information */ - if(prepare_sections() < 0) { - FAIL() << "Invalid Section configuration\n"; - } - if(prepare_extensions() < 0) { - FAIL() << "Invalid Section extension configuration\n"; - } + nAntElm = m_antElmTRx; + nRbs = m_params.sections[0].info.numPrbc; + iqWidth = m_extcfgs[0].u.ext1.bfwIqWidth; + compMethod = m_extcfgs[0].u.ext1.bfwCompMeth; + + switch(compMethod) { + case XRAN_BFWCOMPMETHOD_NONE: + expected_len = (3+1)*nRbs + nAntElm*nRbs*4; + break; + case XRAN_BFWCOMPMETHOD_BLKFLOAT: + expected_len = ((nAntElm/16*4*iqWidth)+1)*nRbs + /* bfwCompParam + IQ = */ + sizeof(struct xran_cp_radioapp_section_ext1)*nRbs; /* ext1 Headers */ + break; + default: + FAIL() << "Unsupported Compression Method - " << compMethod << std::endl; + } if(loc_pSectGenInfo->info.type == XRAN_CP_SECTIONTYPE_1) { /* extType 1 only with Section 1 for now */ @@ -822,7 +917,7 @@ TEST_P(C_plane, Section_Ext1_9bit) for (idRb =0; idRb < nRbs*nAntElm*2; idRb++){ ptr[idRb] = i; i++; - } + } ext_buf += (RTE_PKTMBUF_HEADROOM + sizeof (struct xran_ecpri_hdr) + @@ -854,10 +949,12 @@ TEST_P(C_plane, Section_Ext1_9bit) p_ext1_dst += p_ext1->extLen*XRAN_SECTIONEXT_ALIGN; m_temp_ext1[idRb].bfwNumber = nAntElm; - m_temp_ext1[idRb].bfwiqWidth = iqWidth; + m_temp_ext1[idRb].bfwIqWidth = iqWidth; m_temp_ext1[idRb].bfwCompMeth = compMethod; - m_temp_ext1[idRb].bfwCompParam.exponent = *bfw_payload++ & 0xF; + if(compMethod == XRAN_BFWCOMPMETHOD_BLKFLOAT) { + m_temp_ext1[idRb].bfwCompParam.exponent = *bfw_payload++ & 0xF; + } m_temp_ext1[idRb].p_bfwIQ = (int16_t*)bfw_payload; m_temp_ext1[idRb].bfwIQ_sz = p_ext1->extLen*XRAN_SECTIONEXT_ALIGN; @@ -867,15 +964,16 @@ TEST_P(C_plane, Section_Ext1_9bit) loc_pSectGenInfo->exData[idRb].data = &m_temp_ext1[idRb]; idRb++; - }while(p_ext1->ef != XRAN_EF_F_LAST); + } while(p_ext1->ef != XRAN_EF_F_LAST); + ASSERT_TRUE(idRb == nRbs); - mbuf = xran_attach_cp_ext_buf(ext_buf_init, ext_buf, ext_sec_total, &share_data); + mbuf = xran_attach_cp_ext_buf(0, ext_buf_init, ext_buf, ext_sec_total, &share_data); /* Update section information */ memset(&m_prep_ext1, 0, sizeof (struct xran_sectionext1_info)); m_prep_ext1.bfwNumber = nAntElm; - m_prep_ext1.bfwiqWidth = iqWidth; + m_prep_ext1.bfwIqWidth = iqWidth; m_prep_ext1.bfwCompMeth = compMethod; m_prep_ext1.p_bfwIQ = (int16_t*)ext_buf; m_prep_ext1.bfwIQ_sz = ext_sec_total; @@ -901,50 +999,65 @@ TEST_P(C_plane, Section_Ext1_9bit) /* Parsing generated packet */ EXPECT_TRUE(xran_parse_cp_pkt(/*m_pTestBuffer*/mbuf, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS); - } else { + } + else { FAIL() << "xran_malloc failed\n"; - } + } /* Verify the result */ verify_sections(); if(ext_buf_init) xran_free(ext_buf_init); - } + } } +/*************************************************************************** + * Functional Test cases + ***************************************************************************/ -TEST_P(C_plane, PacketGen) +TEST_P(C_plane, CPacketGen) { /* Configure section information */ if(prepare_sections() < 0) { FAIL() << "Invalid Section configuration\n"; - } + } if(prepare_extensions() < 0) { FAIL() << "Invalid Section extension configuration\n"; + } + if(m_nextcfgs) { + if(m_extcfgs[0].type == XRAN_CP_SECTIONEXTCMD_1) { + test_ext1(); + return; } - - /* Generating C-Plane packet */ - ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS); - - /* Parsing generated packet */ - EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS); - - /* Verify the result */ - verify_sections(); -} - - -TEST_P(C_plane, PacketGen_Ext) -{ - /* Configure section information */ - if(prepare_sections() < 0) { - FAIL() << "Invalid Section configuration\n"; + else if(m_extcfgs[0].type == XRAN_CP_SECTIONEXTCMD_11) { + /* use large buffer to linearize external buffer for parsing */ + m_pTestBuffer = xran_ethdi_mbuf_alloc(); + ASSERT_FALSE(m_pTestBuffer == nullptr); + + if(xran_cp_attach_ext_buf(m_pTestBuffer, + m_pBfwIQ_ext, + m_extcfgs[0].u.ext11.maxExtBufSize, + &m_extSharedInfo) < 0) { + rte_pktmbuf_free(m_pTestBuffer); + m_pTestBuffer = nullptr; + FAIL() << "Failed to attach external buffer !!\n"; + } + rte_mbuf_ext_refcnt_update(&m_extSharedInfo, 0); } + } + + if(m_pTestBuffer == nullptr) { + m_pTestBuffer = xran_ethdi_mbuf_alloc(); + ASSERT_FALSE(m_pTestBuffer == nullptr); + } /* Generating C-Plane packet */ ASSERT_TRUE(xran_prepare_ctrl_pkt(m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId) == XRAN_STATUS_SUCCESS); + /* Linearize data in the chain of mbufs to parse generated packet*/ + ASSERT_TRUE(rte_pktmbuf_linearize(m_pTestBuffer) == 0); + /* Parsing generated packet */ EXPECT_TRUE(xran_parse_cp_pkt(m_pTestBuffer, &m_result, &m_pktInfo) == XRAN_STATUS_SUCCESS); @@ -952,7 +1065,6 @@ TEST_P(C_plane, PacketGen_Ext) verify_sections(); } - /*************************************************************************** * Performance Test cases ***************************************************************************/ @@ -969,21 +1081,10 @@ TEST_P(C_plane, Perf) /* using wrapper function to reset mbuf */ performance("C", module_name, - &xran_ut_prepare_cp, m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId); + &xran_ut_prepare_cp, &m_params, m_ccId, m_antId, m_seqId); } -TEST_P(C_plane, Perf_Ext) -{ - /* Configure section information */ - if(prepare_sections() < 0) { - FAIL() << "Invalid Section configuration\n"; - } - - /* using wrapper function to reset mbuf */ - performance("C", module_name, - &xran_ut_prepare_cp, m_pTestBuffer, &m_params, m_ccId, m_antId, m_seqId); -} INSTANTIATE_TEST_CASE_P(UnitTest, C_plane, testing::ValuesIn(get_sequence(C_plane::get_number_of_cases("C_Plane")))); diff --git a/fhi_lib/test/test_xran/chain_tests.cc b/fhi_lib/test/test_xran/chain_tests.cc index 14d062d..6757656 100644 --- a/fhi_lib/test/test_xran/chain_tests.cc +++ b/fhi_lib/test/test_xran/chain_tests.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -42,7 +42,7 @@ extern "C" void tx_cp_dl_cb(struct rte_timer *tim, void *arg); void tx_cp_ul_cb(struct rte_timer *tim, void *arg); int xran_process_tx_sym(void *arg); -int process_mbuf(struct rte_mbuf *pkt); +int process_mbuf(struct rte_mbuf *pkt, void *arg, struct xran_eaxc_info *p_cid); /* wrapper functions for performace tests */ @@ -86,12 +86,14 @@ void xran_ut_rx_up_ul() int send_mbuf_up(struct rte_mbuf *mbuf, uint16_t type, uint16_t vf_id) { rte_pktmbuf_free(mbuf); + return (1); } int send_mbuf_cp_perf(struct rte_mbuf *mbuf, uint16_t type, uint16_t vf_id) { rte_pktmbuf_free(mbuf); + /* TODO: need to free chained mbufs */ return (1); } @@ -230,8 +232,8 @@ protected: /* C-Plane DL chain (tx_cp_dl_cb) only */ TEST_P(TestChain, CPlaneDLPerf) { - xranlib->Init(&m_xranConf); - xranlib->Open(send_mbuf_cp_perf, send_mbuf_up, + xranlib->Init(0, &m_xranConf); + xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up, (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback); performance("C", module_name, xran_ut_tx_cp_dl); @@ -243,8 +245,8 @@ TEST_P(TestChain, CPlaneDLPerf) /* C-Plane UL chain (tx_cp_ul_cb) only */ TEST_P(TestChain, CPlaneULPerf) { - xranlib->Init(&m_xranConf); - xranlib->Open(send_mbuf_cp_perf, send_mbuf_up, + xranlib->Init(0, &m_xranConf); + xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up, (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback); performance("C", module_name, xran_ut_tx_cp_ul); @@ -258,14 +260,14 @@ TEST_P(TestChain, UPlaneDLPerf) { bool flag_cpen; - xranlib->Init(&m_xranConf); + xranlib->Init(0, &m_xranConf); /* save current CP enable flag */ flag_cpen = xranlib->is_cpenable()?true:false; /* need to disable CP to make U-Plane work without CP */ xranlib->apply_cpenable(false); - xranlib->Open(send_mbuf_cp_perf, send_mbuf_up, + xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up, (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback); performance("C", module_name, xran_ut_tx_up_dl); @@ -282,14 +284,14 @@ TEST_P(TestChain, APlaneDLPerf) { bool flag_cpen; - xranlib->Init(&m_xranConf); + xranlib->Init(0, &m_xranConf); /* save current CP enable flag */ flag_cpen = xranlib->is_cpenable()?true:false; /* Enable CP by force to make UP work by CP's section information */ xranlib->apply_cpenable(true); - xranlib->Open(send_mbuf_cp_perf, send_mbuf_up, + xranlib->Open(0, send_mbuf_cp_perf, send_mbuf_up, (void *)utcp_fh_rx_callback, (void *)utcp_fh_rx_prach_callback, (void *)utcp_fh_srs_callback); performance("C", module_name, xran_ut_tx_cpup_dl); diff --git a/fhi_lib/test/test_xran/compander_functional.cc b/fhi_lib/test/test_xran/compander_functional.cc index b738a04..7323a3d 100644 --- a/fhi_lib/test/test_xran/compander_functional.cc +++ b/fhi_lib/test/test_xran/compander_functional.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -30,6 +30,8 @@ const std::string module_name = "bfp"; +extern int _may_i_use_cpu_feature(unsigned __int64); + template int checkData(T* inVec1, T* inVec2, int numVals) { @@ -296,8 +298,47 @@ int checkPass(ErrorData& err, int testType) } } } +template +void timeThis(KERN_TYPE kernel, T1& inData, T2* outData) +{ + uint64_t startTime; + uint64_t finishTime; + uint64_t thisDuration; + uint64_t meanTime = 0; + uint64_t minTime; + int numRuns = 1000000; + for (int cnt = 0; cnt < numRuns; ++cnt) + { + startTime = __rdtsc(); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + kernel(inData, outData); + finishTime = __rdtsc(); + thisDuration = (finishTime - startTime); + meanTime += thisDuration; + if (cnt == 0) + { + minTime = thisDuration; + } + else if (thisDuration < minTime) + { + minTime = thisDuration; + } + } + meanTime = meanTime / numRuns; + //std::cout << "10 Executions: Mean Time = " << meanTime << ", Min Time = " << minTime << "\n"; + printf("10 Executions: Mean Time = %5ld Min Time = %5ld\n", meanTime, minTime); +} + -int runTest(const int iqWidth, const int numRB, const int numDataElements, const int totNumBlocks) +int runTest(const int runMode, const int iqWidth, const int numRB, const int numDataElements, const int totNumBlocks) { BlockFloatCompander::ExpandedData expandedDataInput; BlockFloatCompander::CompressedData compressedDataRef; @@ -315,11 +356,11 @@ int runTest(const int iqWidth, const int numRB, const int numDataElements, const std::uniform_int_distribution randInt16(-32767, 32767); std::uniform_int_distribution randExpShift(0, 4); - expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0]; - compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0]; - compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0]; - expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0]; - expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0]; + // expandedDataInput.dataExpanded = &expandedDataInput.dataExpandedIn[0]; + // compressedDataRef.dataCompressed = &compressedDataRef.dataCompressedDataOut[0]; + // compressedDataKern.dataCompressed = &compressedDataKern.dataCompressedDataOut[0]; + // expandedDataRef.dataExpanded = &expandedDataRef.dataExpandedIn[0]; + // expandedDataKern.dataExpanded = &expandedDataKern.dataExpandedIn[0]; expandedDataInput.iqWidth = iqWidth; expandedDataInput.numBlocks = numRB; @@ -327,7 +368,21 @@ int runTest(const int iqWidth, const int numRB, const int numDataElements, const int totExpValsPerCall = numRB * numDataElements; int totCompValsPerCall = (((numDataElements * iqWidth) >> 3) + 1) * numRB; - // Run kernel verif loop + // Assign pointers to input/output data arrays + CACHE_ALIGNED int16_t DATAEXPANDED_IN[BlockFloatCompander::k_numSampsExpanded] = { 0 }; + CACHE_ALIGNED uint8_t DATACOMPRESSED_REF[BlockFloatCompander::k_numSampsCompressed] = { 0 }; + CACHE_ALIGNED uint8_t DATACOMPRESSED_KERN[BlockFloatCompander::k_numSampsCompressed] = { 0 }; + CACHE_ALIGNED int16_t DATAEXPANDED_REF[BlockFloatCompander::k_numSampsExpanded] = { 0 }; + CACHE_ALIGNED int16_t DATAEXPANDED_KERN[BlockFloatCompander::k_numSampsExpanded] = { 0 }; + expandedDataInput.dataExpanded = DATAEXPANDED_IN; + compressedDataRef.dataCompressed = DATACOMPRESSED_REF; + expandedDataRef.dataExpanded = DATAEXPANDED_REF; + compressedDataKern.dataCompressed = DATACOMPRESSED_KERN; + expandedDataKern.dataExpanded = DATAEXPANDED_KERN; + + //------------------------------------------------------------------------- + // KERNEL VERIFICATION LOOP + //------------------------------------------------------------------------- for (int blk = 0; blk < totNumBlocks; ++blk) { // Generate input data @@ -336,36 +391,75 @@ int runTest(const int iqWidth, const int numRB, const int numDataElements, const auto shiftVal = randExpShift(gen); for (int n = 0; n < numDataElements; ++n) { - expandedDataInput.dataExpanded[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal); + DATAEXPANDED_IN[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal); } } // Generate reference BlockFloatCompander::BFPCompressRef(expandedDataInput, &compressedDataRef); BlockFloatCompander::BFPExpandRef(compressedDataRef, &expandedDataRef); // Generate kernel output - switch (numDataElements) + if (runMode == 1) { - case 16: - BlockFloatCompander::BFPCompressCtrlPlane8Avx512(expandedDataInput, &compressedDataKern); - BlockFloatCompander::BFPExpandCtrlPlane8Avx512(compressedDataRef, &expandedDataKern); - break; - case 24: - BlockFloatCompander::BFPCompressUserPlaneAvx512(expandedDataInput, &compressedDataKern); - BlockFloatCompander::BFPExpandUserPlaneAvx512(compressedDataRef, &expandedDataKern); - break; - case 32: - BlockFloatCompander::BFPCompressCtrlPlane16Avx512(expandedDataInput, &compressedDataKern); - BlockFloatCompander::BFPExpandCtrlPlane16Avx512(compressedDataRef, &expandedDataKern); - break; - case 64: - BlockFloatCompander::BFPCompressCtrlPlane32Avx512(expandedDataInput, &compressedDataKern); - BlockFloatCompander::BFPExpandCtrlPlane32Avx512(compressedDataRef, &expandedDataKern); - break; - case 128: - BlockFloatCompander::BFPCompressCtrlPlane64Avx512(expandedDataInput, &compressedDataKern); - BlockFloatCompander::BFPExpandCtrlPlane64Avx512(compressedDataRef, &expandedDataKern); - break; + // Run Sunny Cove version + switch (numDataElements) + { + case 16: + BlockFloatCompander::BFPCompressCtrlPlane8AvxSnc(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane8AvxSnc(compressedDataRef, &expandedDataKern); + break; + case 24: + BlockFloatCompander::BFPCompressUserPlaneAvxSnc(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandUserPlaneAvxSnc(compressedDataRef, &expandedDataKern); + break; + case 32: + BlockFloatCompander::BFPCompressCtrlPlane16AvxSnc(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane16AvxSnc(compressedDataRef, &expandedDataKern); + break; + case 64: + BlockFloatCompander::BFPCompressCtrlPlane32AvxSnc(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane32AvxSnc(compressedDataRef, &expandedDataKern); + break; + case 128: + BlockFloatCompander::BFPCompressCtrlPlane64AvxSnc(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane64AvxSnc(compressedDataRef, &expandedDataKern); + break; + } + } + else + { + // Default Skylake/Palm Cove AVX512 version + switch (numDataElements) + { + case 16: + BlockFloatCompander::BFPCompressCtrlPlane8Avx512(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane8Avx512(compressedDataRef, &expandedDataKern); + break; + case 24: + if ((iqWidth == 9) && (numRB == 16)) + { + BlockFloatCompander::BFPCompressUserPlaneAvx512_9b16RB(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandUserPlaneAvx512_9b16RB(compressedDataRef, &expandedDataKern); + } + else + { + BlockFloatCompander::BFPCompressUserPlaneAvx512(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandUserPlaneAvx512(compressedDataRef, &expandedDataKern); + } + break; + case 32: + BlockFloatCompander::BFPCompressCtrlPlane16Avx512(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane16Avx512(compressedDataRef, &expandedDataKern); + break; + case 64: + BlockFloatCompander::BFPCompressCtrlPlane32Avx512(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane32Avx512(compressedDataRef, &expandedDataKern); + break; + case 128: + BlockFloatCompander::BFPCompressCtrlPlane64Avx512(expandedDataInput, &compressedDataKern); + BlockFloatCompander::BFPExpandCtrlPlane64Avx512(compressedDataRef, &expandedDataKern); + break; } +} // Check data compareData(expandedDataInput.dataExpanded, expandedDataRef.dataExpanded, errRef, totExpValsPerCall); compareData(compressedDataRef.dataCompressed, compressedDataKern.dataCompressed, errComp, totCompValsPerCall); @@ -381,6 +475,139 @@ int runTest(const int iqWidth, const int numRB, const int numDataElements, const /*std::cout << "Expansion: ";*/ resSum += checkPass(errExp, 0); /*std::cout << "\n";*/ + //------------------------------------------------------------------------- + // KERNEL TIMING LOOP + //------------------------------------------------------------------------- + // Generate input data + + for (int m = 0; m < numRB; ++m) + { + auto shiftVal = randExpShift(gen); + for (int n = 0; n < numDataElements; ++n) + { + DATAEXPANDED_IN[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal); + } + } + // Generate reference + BlockFloatCompander::BFPCompressRef(expandedDataInput, &compressedDataRef); + + if (runMode == 1) + { + // Run Sunny Cove version + switch (numDataElements) + { + case 16: + //std::cout << "Timing Control Plane 8 Antennas (SNC)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane8AvxSnc iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane8AvxSnc, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane8AvxSnc iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane8AvxSnc, compressedDataRef, &expandedDataKern); + break; + case 24: + //std::cout << "Timing User Plane (SNC)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressUserPlaneAvxSnc iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressUserPlaneAvxSnc, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandUserPlaneAvxSnc iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandUserPlaneAvxSnc, compressedDataRef, &expandedDataKern); + break; + case 32: + //std::cout << "Timing Control Plane 16 Antennas (SNC)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane16AvxSnc iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane16AvxSnc, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane16AvxSnc iqWidth %2d numRB %2d numDataElements %3d ", iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane16AvxSnc, compressedDataRef, &expandedDataKern); + break; + case 64: + //std::cout << "Timing Control Plane 32 Antennas (SNC)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane32AvxSnc iqWidth %2d numRB %2d numDataElements %3d ", iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane32AvxSnc, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane32AvxSnc iqWidth %2d numRB %2d numDataElements %3d ", iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane32AvxSnc, compressedDataRef, &expandedDataKern); + break; + case 128: + //std::cout << "Timing Control Plane 64 Antennas (SNC)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane64AvxSnc iqWidth %2d numRB %2d numDataElements %3d ", iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane64AvxSnc, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane64AvxSnc iqWidth %2d numRB %2d numDataElements %3d ", iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane64AvxSnc, compressedDataRef, &expandedDataKern); + break; + } + } + else + { + // Default Skylake/Palm Cove AVX512 version + switch (numDataElements) + { + case 16: + //std::cout << "Timing Control Plane 8 Antennas (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane8Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane8Avx512, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane8Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane8Avx512, compressedDataRef, &expandedDataKern); + break; + case 24: + if ((iqWidth == 9) && (numRB == 16)) + { + //std::cout << "Timing User Plane (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressUserPlaneAvx512_9b16RB iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressUserPlaneAvx512_9b16RB, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandUserPlaneAvx512_9b16RB iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandUserPlaneAvx512_9b16RB, compressedDataRef, &expandedDataKern); + } + else + { + //std::cout << "Timing User Plane (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressUserPlaneAvx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressUserPlaneAvx512, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandUserPlaneAvx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandUserPlaneAvx512, compressedDataRef, &expandedDataKern); + } + break; + case 32: + //std::cout << "Timing Control Plane 16 Antennas (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane16Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane16Avx512, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane16Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane16Avx512, compressedDataRef, &expandedDataKern); + break; + case 64: + //std::cout << "Timing Control Plane 32 Antennas (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane32Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane32Avx512, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane32Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane32Avx512, compressedDataRef, &expandedDataKern); + break; + case 128: + //std::cout << "Timing Control Plane 64 Antennas (AVX512)...\n"; + //std::cout << "Compression: "; + printf("BFPCompressCtrlPlane64Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPCompressCtrlPlane64Avx512, expandedDataInput, &compressedDataKern); + //std::cout << "Expansion : "; + printf("BFPExpandCtrlPlane64Avx512 iqWidth %2d numRB %2d numDataElements %3d ",iqWidth, numRB, numDataElements); + timeThis(BlockFloatCompander::BFPExpandCtrlPlane64Avx512, compressedDataRef, &expandedDataKern); + break; + } + } return resSum; } @@ -397,6 +624,8 @@ TEST_P(BfpCheck, AVX512_bfp_main) int numDataElementsCPlane64 = 128; int totNumBlocks = 100; + ASSERT_EQ(0, bind_to_cpu(BenchmarkParameters::cpu_id)) << "Failed to bind to cpu!"; + for (int iqw = 0; iqw < 4; ++iqw) { for (int nrb = 0; nrb < 3; ++nrb) @@ -405,23 +634,71 @@ TEST_P(BfpCheck, AVX512_bfp_main) // USER PLANE TESTS //std::cout << "U-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsUPlane << ": "; - resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsUPlane, totNumBlocks); + resSum += runTest(0, iqWidth[iqw], numRB[nrb], numDataElementsUPlane, totNumBlocks); // CONTROL PLANE TESTS : 8 Antennas //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane8 << ": "; - resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane8, totNumBlocks); + resSum += runTest(0, iqWidth[iqw], numRB[nrb], numDataElementsCPlane8, totNumBlocks); // CONTROL PLANE TESTS : 16 Antennas //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane16 << ": "; - resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane16, totNumBlocks); + resSum += runTest(0, iqWidth[iqw], numRB[nrb], numDataElementsCPlane16, totNumBlocks); // CONTROL PLANE TESTS : 32 Antennas //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane32 << ": "; - resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane32, totNumBlocks); + resSum += runTest(0, iqWidth[iqw], numRB[nrb], numDataElementsCPlane32, totNumBlocks); // CONTROL PLANE TESTS : 64 Antennas //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane64 << ": "; - resSum += runTest(iqWidth[iqw], numRB[nrb], numDataElementsCPlane64, totNumBlocks); + resSum += runTest(0, iqWidth[iqw], numRB[nrb], numDataElementsCPlane64, totNumBlocks); + } + } + + ASSERT_EQ(0, resSum); +} + +TEST_P(BfpCheck, AVXSNC_bfp_main) +{ + int resSum = 0; + int iqWidth[4] = { 8, 9, 10, 12 }; + int numRB[3] = { 1, 4, 16 }; + int numDataElementsUPlane = 24; + int numDataElementsCPlane8 = 16; + int numDataElementsCPlane16 = 32; + int numDataElementsCPlane32 = 64; + int numDataElementsCPlane64 = 128; + int totNumBlocks = 100; + + ASSERT_EQ(0, bind_to_cpu(BenchmarkParameters::cpu_id)) << "Failed to bind to cpu!"; + + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52) == 0) + return; + + for (int iqw = 0; iqw < 4; ++iqw) + { + for (int nrb = 0; nrb < 3; ++nrb) + { + //std::cout << "\n"; + + // USER PLANE TESTS + //std::cout << "U-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsUPlane << ": "; + resSum += runTest(1, iqWidth[iqw], numRB[nrb], numDataElementsUPlane, totNumBlocks); + + // CONTROL PLANE TESTS : 8 Antennas + //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane8 << ": "; + resSum += runTest(1, iqWidth[iqw], numRB[nrb], numDataElementsCPlane8, totNumBlocks); + + // CONTROL PLANE TESTS : 16 Antennas + //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane16 << ": "; + resSum += runTest(1, iqWidth[iqw], numRB[nrb], numDataElementsCPlane16, totNumBlocks); + + // CONTROL PLANE TESTS : 32 Antennas + //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane32 << ": "; + resSum += runTest(1, iqWidth[iqw], numRB[nrb], numDataElementsCPlane32, totNumBlocks); + + // CONTROL PLANE TESTS : 64 Antennas + //std::cout << "C-Plane: Testing iqWidth = " << iqWidth[iqw] << ", numRB = " << numRB[nrb] << ", numElements = " << numDataElementsCPlane64 << ": "; + resSum += runTest(1, iqWidth[iqw], numRB[nrb], numDataElementsCPlane64, totNumBlocks); } } @@ -511,6 +788,93 @@ TEST_P(BfpCheck, AVX512_sweep_xranlib) } } +TEST_P(BfpCheck, AVXSNC_sweep_xranlib) +{ + int32_t resSum = 0; + int16_t len = 0; + + int16_t compMethod = XRAN_COMPMETHOD_BLKFLOAT; + int16_t iqWidth[] = {8, 9, 10, 12}; + + int16_t numRBs[] = {16, 18, 32, 36, 48, 70, 113, 273}; + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + + struct xranlib_compress_request bfp_com_req; + struct xranlib_compress_response bfp_com_rsp; + + int numDataElements = 24; + + + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52) == 0) + return; + + // Create random number generator + std::random_device rd; + std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd() + std::uniform_int_distribution randInt16(-32768, 32767); + std::uniform_int_distribution randExpShift(0, 4); + + BlockFloatCompander::ExpandedData expandedData; + expandedData.dataExpanded = &loc_dataExpandedIn[0]; + BlockFloatCompander::ExpandedData expandedDataRes; + expandedDataRes.dataExpanded = &loc_dataExpandedRes[0]; + for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){ + for (int tc = 0; tc < sizeof(numRBs)/sizeof(numRBs[0]); tc ++){ + + //printf("[%d]numRBs %d [%d] iqWidth %d\n",tc, numRBs[tc], iq_w_id, iqWidth[iq_w_id]); + // Generate random test data for compression kernel + + for (int m = 0; m < 18*BlockFloatCompander::k_maxNumBlocks; ++m) { + auto shiftVal = randExpShift(gen); + for (int n = 0; n < numDataElements; ++n) { + expandedData.dataExpanded[m*numDataElements+n] = int16_t(randInt16(gen) >> shiftVal); + } + } + + BlockFloatCompander::CompressedData compressedData; + compressedData.dataCompressed = &loc_dataCompressedDataOut[0]; + + std::memset(&loc_dataCompressedDataOut[0], 0, 288*numDataElements); + std::memset(&loc_dataExpandedRes[0], 0, 288*numDataElements); + + std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request)); + std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response)); + std::memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + std::memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + + bfp_com_req.data_in = (int16_t *)expandedData.dataExpanded; + bfp_com_req.numRBs = numRBs[tc]; + bfp_com_req.numDataElements = 24; + bfp_com_req.len = numRBs[tc]*12*2*2; + bfp_com_req.compMethod = compMethod; + bfp_com_req.iqWidth = iqWidth[iq_w_id]; + + bfp_com_rsp.data_out = (int8_t *)(compressedData.dataCompressed); + bfp_com_rsp.len = 0; + + xranlib_compress_avxsnc(&bfp_com_req, &bfp_com_rsp); + + bfp_decom_req.data_in = (int8_t *)(compressedData.dataCompressed); + bfp_decom_req.numRBs = numRBs[tc]; + bfp_decom_req.len = bfp_com_rsp.len; + bfp_decom_req.numDataElements = 24; + bfp_decom_req.compMethod = compMethod; + bfp_decom_req.iqWidth = iqWidth[iq_w_id]; + + bfp_decom_rsp.data_out = (int16_t *)expandedDataRes.dataExpanded; + bfp_decom_rsp.len = 0; + + xranlib_decompress_avxsnc(&bfp_decom_req, &bfp_decom_rsp); + + resSum += checkDataApprox(expandedData.dataExpanded, expandedDataRes.dataExpanded, numRBs[tc]*numDataElements); + + ASSERT_EQ(numRBs[tc]*12*2*2, bfp_decom_rsp.len); + ASSERT_EQ(0, resSum); + } + } +} + TEST_P(BfpCheck, AVX512_cp_sweep_xranlib) { int32_t resSum = 0; @@ -597,6 +961,95 @@ TEST_P(BfpCheck, AVX512_cp_sweep_xranlib) } } +TEST_P(BfpCheck, AVXSNC_cp_sweep_xranlib) +{ + int32_t resSum = 0; + int16_t len = 0; + + int16_t compMethod = XRAN_COMPMETHOD_BLKFLOAT; + int16_t iqWidth[] = {8, 9, 10, 12}; + int16_t numRB = 1; + int16_t antElm[] = {8, 16, 32, 64}; + + struct xranlib_decompress_request bfp_decom_req; + struct xranlib_decompress_response bfp_decom_rsp; + + struct xranlib_compress_request bfp_com_req; + struct xranlib_compress_response bfp_com_rsp; + int32_t numDataElements; + + // Create random number generator + std::random_device rd; + std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd() + std::uniform_int_distribution randInt16(-32768, 32767); + std::uniform_int_distribution randExpShift(0, 4); + + BlockFloatCompander::ExpandedData expandedData; + expandedData.dataExpanded = &loc_dataExpandedIn[0]; + BlockFloatCompander::ExpandedData expandedDataRes; + expandedDataRes.dataExpanded = &loc_dataExpandedRes[0]; + + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52) == 0) + return; + + for (int iq_w_id = 0; iq_w_id < sizeof(iqWidth)/sizeof(iqWidth[0]); iq_w_id ++){ + for (int tc = 0; tc < sizeof(antElm)/sizeof(antElm[0]); tc ++){ + + numDataElements = 2*antElm[tc]; + + // Generate input data + for (int m = 0; m < numRB; ++m) + { + auto shiftVal = randExpShift(gen); + for (int n = 0; n < numDataElements; ++n) + { + expandedData.dataExpanded[m * numDataElements + n] = int16_t(randInt16(gen) >> shiftVal); + } + } + + BlockFloatCompander::CompressedData compressedData; + compressedData.dataCompressed = &loc_dataCompressedDataOut[0]; + + std::memset(&loc_dataCompressedDataOut[0], 0, 288*numDataElements); + std::memset(&loc_dataExpandedRes[0], 0, 288*numDataElements); + + std::memset(&bfp_com_req, 0, sizeof(struct xranlib_compress_request)); + std::memset(&bfp_com_rsp, 0, sizeof(struct xranlib_compress_response)); + std::memset(&bfp_decom_req, 0, sizeof(struct xranlib_decompress_request)); + std::memset(&bfp_decom_rsp, 0, sizeof(struct xranlib_decompress_response)); + + bfp_com_req.data_in = (int16_t *)expandedData.dataExpanded; + bfp_com_req.numRBs = numRB; + bfp_com_req.numDataElements = numDataElements; + bfp_com_req.len = antElm[tc]*4; + bfp_com_req.compMethod = compMethod; + bfp_com_req.iqWidth = iqWidth[iq_w_id]; + + bfp_com_rsp.data_out = (int8_t *)(compressedData.dataCompressed); + bfp_com_rsp.len = 0; + + xranlib_compress_avxsnc_bfw(&bfp_com_req, &bfp_com_rsp); + + bfp_decom_req.data_in = (int8_t *)(compressedData.dataCompressed); + bfp_decom_req.numRBs = numRB; + bfp_decom_req.numDataElements = numDataElements; + bfp_decom_req.len = bfp_com_rsp.len; + bfp_decom_req.compMethod = compMethod; + bfp_decom_req.iqWidth = iqWidth[iq_w_id]; + + bfp_decom_rsp.data_out = (int16_t *)expandedDataRes.dataExpanded; + bfp_decom_rsp.len = 0; + + xranlib_decompress_avxsnc_bfw(&bfp_decom_req, &bfp_decom_rsp); + + resSum += checkDataApprox(expandedData.dataExpanded, expandedDataRes.dataExpanded, numRB*numDataElements); + + ASSERT_EQ(antElm[tc]*4, bfp_decom_rsp.len); + ASSERT_EQ(0, resSum); + } + } +} + TEST_P(BfpPerfEx, AVX512_Comp) { performance("AVX512", module_name, xranlib_compress_avx512, &bfp_com_req, &bfp_com_rsp); @@ -617,6 +1070,30 @@ TEST_P(BfpPerfCp, AVX512_CpDeComp) performance("AVX512", module_name, xranlib_decompress_avx512_bfw, &bfp_decom_req, &bfp_decom_rsp); } +TEST_P(BfpPerfEx, AVXSNC_Comp) +{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + performance("AVXSNC", module_name, xranlib_compress_avxsnc, &bfp_com_req, &bfp_com_rsp); +} + +TEST_P(BfpPerfEx, AVXSNC_DeComp) +{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + performance("AVXSNC", module_name, xranlib_decompress_avxsnc, &bfp_decom_req, &bfp_decom_rsp); +} + +TEST_P(BfpPerfCp, AVXSNC_CpComp) +{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + performance("AVXSNC", module_name, xranlib_compress_avxsnc_bfw, &bfp_com_req, &bfp_com_rsp); +} + +TEST_P(BfpPerfCp, AVXSNC_CpDeComp) +{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + performance("AVXSNC", module_name, xranlib_decompress_avxsnc_bfw, &bfp_decom_req, &bfp_decom_rsp); +} + INSTANTIATE_TEST_CASE_P(UnitTest, BfpCheck, testing::ValuesIn(get_sequence(BfpCheck::get_number_of_cases("bfp_functional")))); diff --git a/fhi_lib/test/test_xran/conf.json b/fhi_lib/test/test_xran/conf.json index c6bef2c..d71253c 100644 --- a/fhi_lib/test/test_xran/conf.json +++ b/fhi_lib/test/test_xran/conf.json @@ -11,7 +11,8 @@ "pkt_aux_core": 0, "dpdkBasebandFecMode": 0, "dpdkBasebandDevice": "", - "mtu": 9600, + "dpdkMemorySize": 8192, + "mtu": 1500, "o_du_macaddr": "00:11:22:33:44:66", "o_ru_macaddr": "00:11:22:33:44:55", "cp_vlan_tag": 1, @@ -695,6 +696,251 @@ ] } }, + { + "name": "DL_SectionType1_SingleSection_Ext6", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 0, + "iq_width": 16, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 273, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext6", + "type": 6, + "rbgSize": 6, + "rbgMask": 173693530, + "symbolMask": 16383 + } + ] + } + }, + { + "name": "DL_SectionType1_SingleSection_Ext10", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 0, + "iq_width": 16, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 273, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext10", + "type": 10, + "numPortc": 15, + "beamGrpType": 2, + "beamID": [ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 ] + } + ] + } + }, + { + "name": "DL_SectionType1_SingleSection_Ext1_NoComp", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 0, + "iq_width": 16, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 36, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext1", + "type": 1, + "bfwCompMeth": 0, + "bfwIqWidth": 16, + "antelm_trx": 64 + } + ] + } + }, + { + "name": "DL_SectionType1_SingleSection_Ext1_BFP9", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 1, + "iq_width": 9, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 36, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext1", + "type": 1, + "bfwCompMeth": 1, + "bfwIqWidth": 9, + "antelm_trx": 64 + } + ] + } + }, + { + "name": "DL_SectionType1_SingleSection_Ext11_NoComp", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 0, + "iq_width": 16, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 270, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext11", + "type": 11, + "RAD": 0, + "disableBFWs": 0, + "numBundPrb": 90, + "numSetBFWs": 3, + "bfwCompMeth": 0, + "bfwIqWidth": 16, + "antelm_trx": 64, + "beamID": [ 31312, 31313, 31314 ] + } + ] + } + }, + { + "name": "DL_SectionType1_SingleSection_Ext11_BFP9", + "parameters": { + "direction": "DL", + "section_type": 1, + "cc_id": 0, + "ant_id": 0, + "seq_id": 0, + "frame_id": 0, + "subframe_id": 0, + "slot_id": 0, + "symbol_start": 0, + "comp_method": 1, + "iq_width": 9, + "sections": [ + { + "sectionId": 1, + "rb": 0, + "symInc": 0, + "startPrbc": 0, + "numPrbc": 18, + "reMask": 4095, + "numSymbol": 14, + "beamId": 0, + "exts": [ 0 ] + } + ], + "extensions": [ + { + "name": "ext11", + "type": 11, + "RAD": 0, + "disableBFWs": 0, + "numBundPrb": 2, + "numSetBFWs": 9, + "bfwCompMeth": 1, + "bfwIqWidth": 9, + "antelm_trx": 64, + "beamID": [ 31315, 31316, 31317, 31318, 31319, 31320, 31321, 31322, + 31323, 31324, 31325, 31326, 31327, 31328, 31329, 31330, + 31331, 31332, 31333, 31334, 31335, 31336, 31337, 31338, + 31339, 31340, 31341, 31342, 31343, 31344, 31345, 31346, + 31347, 31348, 31349, 31350, 31351, 31352, 31353, 31354, + 31355, 31356, 31357, 31358, 31359, 31360, 31361, 31362, + 31363, 31364, 31365, 31366, 31367, 31368, 31369, 31370, + 31371, 31372, 31373, 31374, 31375, 31376, 31377, 31378 ] + } + ] + } + }, { "name": "DL_SectionType1_SingleSection_ExtAll", "parameters": { @@ -719,7 +965,7 @@ "reMask": 4095, "numSymbol": 14, "beamId": 0, - "exts": [ 0, 1, 2, 3 ] + "exts": [ 0, 1, 2, 3, 4, 5 ] } ], "extensions": [ @@ -765,6 +1011,20 @@ "csf": [ 1, 0 ], "mcScaleReMask":[ 15, 7 ], "mcScaleOffset":[ 100, 200 ] + }, + { + "name": "ext6", + "type": 6, + "rbgSize": 6, + "rbgMask": 173693530, + "symbolMask": 16383 + }, + { + "name": "ext10", + "type": 10, + "numPortc": 15, + "beamGrpType": 2, + "beamID": [ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 ] } ] } @@ -1013,7 +1273,7 @@ "dpdkBasebandDevice": "none", "filePrefix": "wls", "xranCat": 0, - "mtu": 9600, + "mtu": 1500, "p_o_du_addr": "00:11:22:33:44:66", "p_o_ru_addr": "00:11:22:33:44:55", "Tadv_cp_dl": 0, @@ -1082,7 +1342,7 @@ "SlotNrNum": 2, "prach_start_symbol": 0, "prach_last_symbol": 13, - "m_params_timeOffset": 108, + "m_params_timeOffset": 124, "id": 0 } } @@ -1851,5 +2111,120 @@ "iqWidth": 14 } } + ], + + "mod_compression_performace": [ + { + "name": "QPSK_1728RE", + "parameters": { + "unit": 8192, + "modulation": 2, + "num_symbols": 1728 + } + }, + { + "name": "QPSK_3276RE", + "parameters": { + "unit": 8192, + "modulation": 2, + "num_symbols": 3276 + } + }, + { + "name": "16QAM_1722RE", + "parameters": { + "unit": 10360, + "modulation": 4, + "num_symbols": 1722 + } + }, + { + "name": "16QAM_3276RE", + "parameters": { + "unit": 10360, + "modulation": 4, + "num_symbols": 3276 + } + }, + { + "name": "64QAM_1728RE", + "parameters": { + "unit": 5064, + "modulation": 6, + "num_symbols": 1728 + } + }, + { + "name": "64QAM_3276RE", + "parameters": { + "unit": 5064, + "modulation": 6, + "num_symbols": 3276 + } + }, + { + "name": "256QAM_1272RE", + "parameters": { + "unit": 7168, + "modulation": 8, + "num_symbols": 1272 + } + }, + { + "name": "256QAM_3276RE", + "parameters": { + "unit": 7168, + "modulation": 8, + "num_symbols": 3276 + } + }, + { + "name": "QPSK_6793X2RE", + "parameters": { + "unit": 8192, + "modulation": 2, + "num_symbols": 13586 + } + }, + { + "name": "16QAM_5284X4RE", + "parameters": { + "unit": 10360, + "modulation": 4, + "num_symbols": 21136 + } + }, + { + "name": "64QAM_3774X8RE", + "parameters": { + "unit": 5064, + "modulation": 6, + "num_symbols": 30192 + } + }, + { + "name": "64QAM_2264X16RE", + "parameters": { + "unit": 5064, + "modulation": 6, + "num_symbols": 36224 + } + }, + { + "name": "256QAM_755X8RE", + "parameters": { + "unit": 7168, + "modulation": 8, + "num_symbols": 6040 + } + }, + { + "name": "256QAM_62899X16RE", + "parameters": { + "unit": 7168, + "modulation": 8, + "num_symbols": 1006384 + } + } ] } diff --git a/fhi_lib/test/test_xran/init_sys_functional.cc b/fhi_lib/test/test_xran/init_sys_functional.cc index 156934e..e00d022 100644 --- a/fhi_lib/test/test_xran/init_sys_functional.cc +++ b/fhi_lib/test/test_xran/init_sys_functional.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -36,10 +36,10 @@ const std::string module_name = "init_sys_functional"; extern enum xran_if_state xran_if_current_state; -void physide_sym_call_back(void * param) +int32_t physide_sym_call_back(void * param, struct xran_sense_of_time *time) { rte_pause(); - return; + return 0; } int physide_dl_tti_call_back(void * param) @@ -85,8 +85,8 @@ protected: void SetUp() override { - xranlib->Init(); - xranlib->Open(nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback); + xranlib->Init(0); + xranlib->Open(0, nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback, (void *)xran_fh_srs_callback); } /* It's called after an execution of the each test case.*/ @@ -148,6 +148,7 @@ TEST_P(Init_Sys_Check, Test_xran_bm_init_alloc_free) struct xran_buffer_list *pFthRxBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; struct xran_buffer_list *pFthRxPrbMapBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; struct xran_buffer_list *pFthRxRachBuffer[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; + struct xran_buffer_list *pFthRxRachBufferDecomp[XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN]; Init_Sys_Check::nInstanceNum = xranlib->get_num_cc(); @@ -183,6 +184,7 @@ TEST_P(Init_Sys_Check, Test_xran_bm_init_alloc_free) pFthRxBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList); pFthRxPrbMapBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList); pFthRxRachBuffer[i][z][j] = &(Init_Sys_Check::sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList); + pFthRxRachBufferDecomp[i][z][j] = &(Init_Sys_Check::sFHPrachRxBbuIoBufCtrlDecomp[j][i][z].sBufferList); } } } @@ -204,7 +206,7 @@ TEST_P(Init_Sys_Check, Test_xran_bm_init_alloc_free) // add prach callback here for (int i = 0; i < xranlib->get_num_cc(); i++) { - ret = xran_5g_prach_req(Init_Sys_Check::nInstanceHandle[0][i], pFthRxRachBuffer[i], + ret = xran_5g_prach_req(Init_Sys_Check::nInstanceHandle[0][i], pFthRxRachBuffer[i], pFthRxRachBufferDecomp[i], xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]); ASSERT_EQ(0, ret); } @@ -240,7 +242,7 @@ TEST_P(Init_Sys_Check, Test_xran_get_slot_idx) uint32_t nSlotIdx; uint64_t nSecond; - uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); + uint32_t nXranTime = xran_get_slot_idx(0, &nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond); nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf + nSubframeIdx*nNrOfSlotInSf + nSlotIdx; @@ -274,14 +276,14 @@ TEST_P(Init_Sys_Check, Test_xran_reg_physide_cb) TEST_P(Init_Sys_Check, Test_xran_reg_sym_cb){ int16_t ret = 0; - ret = xran_reg_sym_cb(xranlib->get_xranhandle(), physide_sym_call_back, NULL, 11, 0); - ASSERT_EQ(-1,ret); + ret = xran_reg_sym_cb(xranlib->get_xranhandle(), physide_sym_call_back, NULL, NULL, 11, XRAN_CB_SYM_RX_WIN_END); + ASSERT_EQ(0,ret); } TEST_P(Init_Sys_Check, Test_xran_mm_destroy){ int16_t ret = 0; ret = xran_mm_destroy(xranlib->get_xranhandle()); - ASSERT_EQ(-1,ret); + ASSERT_EQ(0,ret); } TEST_P(Init_Sys_Check, Test_xran_start_stop){ diff --git a/fhi_lib/test/test_xran/mod_compression_unit_test.cc b/fhi_lib/test/test_xran/mod_compression_unit_test.cc new file mode 100644 index 0000000..3706a7a --- /dev/null +++ b/fhi_lib/test/test_xran/mod_compression_unit_test.cc @@ -0,0 +1,85 @@ +/****************************************************************************** +* +* Copyright (c) 2020 Intel. +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +* +*******************************************************************************/ + +#include "common.hpp" +#include "xran_fh_o_du.h" +#include "xran_mod_compression.h" + +#include +#include +#include +#include +#include +#include + +const std::string module_name = "mod_compression"; + +extern int _may_i_use_cpu_feature(unsigned __int64); + +int16_t loc_ModCompIn[273*12*14*2*16*2]; +int8_t loc_ModCompOut[273*12*14*2*16]; + +class Mod_CompressionPerf : public KernelTests +{ +protected: + struct xranlib_5gnr_mod_compression_request mod_com_req; + struct xranlib_5gnr_mod_compression_response mod_com_rsp; + + void SetUp() override { + init_test("mod_compression_performace"); + // Create random number generator + std::random_device rd; + std::mt19937 gen(rd()); //Standard mersenne_twister_engine seeded with rd() + std::uniform_int_distribution randInt16(-32768, 32767); + std::uniform_int_distribution randExpShift(0, 4); + std::memset(&loc_ModCompOut[0], 0, 273*12); + + std::memset(&mod_com_req, 0, sizeof(struct xranlib_5gnr_mod_compression_request)); + std::memset(&mod_com_rsp, 0, sizeof(struct xranlib_5gnr_mod_compression_response)); + mod_com_req.unit = get_input_parameter("unit"); + mod_com_req.modulation = get_input_parameter("modulation"); + mod_com_req.num_symbols = get_input_parameter("num_symbols"); + + for (int m = 0; m < 2*mod_com_req.num_symbols; ++m) { + loc_ModCompIn[m] = int16_t(randInt16(gen)); + } + + mod_com_req.data_in = (int16_t *)loc_ModCompIn; + mod_com_rsp.data_out = (int8_t *)(loc_ModCompOut); + } + + /* It's called after an execution of the each test case.*/ + void TearDown() override { + + } +}; + +TEST_P(Mod_CompressionPerf, AVX512_Mod_Comp) +{ + performance("AVX512", module_name, xranlib_5gnr_mod_compression_avx512, &mod_com_req, &mod_com_rsp); +} + + +TEST_P(Mod_CompressionPerf, AVXSNC_Mod_Comp) +{ + if(_may_i_use_cpu_feature(_FEATURE_AVX512IFMA52)) + performance("AVXSNC", module_name, xranlib_5gnr_mod_compression_snc, &mod_com_req, &mod_com_rsp); +} + +INSTANTIATE_TEST_CASE_P(UnitTest, Mod_CompressionPerf, + testing::ValuesIn(get_sequence(Mod_CompressionPerf::get_number_of_cases("mod_compression_performace")))); diff --git a/fhi_lib/test/test_xran/prach_functional.cc b/fhi_lib/test/test_xran/prach_functional.cc index e7e1a01..33213a5 100644 --- a/fhi_lib/test/test_xran/prach_functional.cc +++ b/fhi_lib/test/test_xran/prach_functional.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -174,7 +174,7 @@ protected: }; -TEST_P(PrachCheck, PacketGen)//TestCaseName TestName +TEST_P(PrachCheck, PrachPacketGen)//TestCaseName TestName { int ret; int32_t i; @@ -208,9 +208,9 @@ TEST_P(PrachCheck, PacketGen)//TestCaseName TestName ret = xran_open(pHandle, m_xranConf); ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS); - ret = generate_cpmsg_prach(pHandle, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx, + ret = generate_cpmsg_prach(&m_xran_dev_ctx, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx, m_frameId, m_subframeId, m_slotId, - m_beamId, m_ccId, m_antId, 0); + m_beamId, m_ccId, m_antId, 0, 0); ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS); /* Verify the result */ EXPECT_EQ(m_params.sectionType, XRAN_CP_SECTIONTYPE_3); @@ -238,7 +238,7 @@ TEST_P(PrachCheck, PacketGen)//TestCaseName TestName EXPECT_EQ(m_params.sections[0].info.symInc, XRAN_SYMBOLNUMBER_NOTINC); EXPECT_EQ(m_params.sections[0].info.startPrbc, m_startPrbc); EXPECT_EQ(m_params.sections[0].info.numPrbc, m_numPrbc); - EXPECT_EQ(m_params.sections[0].info.numSymbol, m_numSymbol*m_occassionsInPrachSlot); + EXPECT_EQ(m_params.sections[0].info.numSymbol, m_numSymbol); EXPECT_EQ(m_params.sections[0].info.reMask, 0xfff); EXPECT_EQ(m_params.sections[0].info.beamId, m_beamId); EXPECT_EQ(m_params.sections[0].info.freqOffset, m_freqOffset); diff --git a/fhi_lib/test/test_xran/prach_performance.cc b/fhi_lib/test/test_xran/prach_performance.cc index 659950c..f5f5a7e 100644 --- a/fhi_lib/test/test_xran/prach_performance.cc +++ b/fhi_lib/test/test_xran/prach_performance.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -177,16 +177,16 @@ void performance_cp(void *pHandle,struct xran_cp_gen_params *params, struct xran mbuf = (struct rte_mbuf*)rte_pktmbuf_alloc(_eth_mbuf_pool); - generate_cpmsg_prach(pHandle, params, sect_geninfo, mbuf, pxran_lib_ctx, + generate_cpmsg_prach(pxran_lib_ctx, params, sect_geninfo, mbuf, pxran_lib_ctx, frame_id, subframe_id, slot_id, - beam_id, cc_id, prach_port_id, seq_id); + beam_id, cc_id, prach_port_id, 0, seq_id); seq_id++; rte_pktmbuf_free(mbuf); } -TEST_P(PrachPerf, PacketGen)//TestCaseName TestName +TEST_P(PrachPerf, PrachPerfPacketGen)//TestCaseName TestName { int ret; void *pHandle = NULL; @@ -196,9 +196,9 @@ TEST_P(PrachPerf, PacketGen)//TestCaseName TestName ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS); - ret = generate_cpmsg_prach(pHandle, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx, + ret = generate_cpmsg_prach(&m_xran_dev_ctx, &m_params, m_pSectGenInfo, m_pTestBuffer, &m_xran_dev_ctx, m_frameId, m_subframeId, m_slotId, - m_beamId, m_ccId, m_antId, 0); + m_beamId, m_ccId, m_antId, 0, 0); ASSERT_TRUE(ret == XRAN_STATUS_SUCCESS); diff --git a/fhi_lib/test/test_xran/u_plane_functional.cc b/fhi_lib/test/test_xran/u_plane_functional.cc index 5bc1588..13afda3 100644 --- a/fhi_lib/test/test_xran/u_plane_functional.cc +++ b/fhi_lib/test/test_xran/u_plane_functional.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -73,6 +73,7 @@ TEST_P(U_planeCheck, Test_DLUL) uint8_t seq_id =0; uint32_t do_copy = 0; uint8_t compMeth = 0; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; uint8_t iqWidth = 16; int32_t prep_bytes; @@ -87,7 +88,7 @@ TEST_P(U_planeCheck, Test_DLUL) prep_bytes = prepare_symbol_ex(direction, section_id, test_buffer, - (struct rb_map *)iq_offset, + (uint8_t *)iq_offset, compMeth, iqWidth, iq_buf_byte_order, @@ -100,7 +101,8 @@ TEST_P(U_planeCheck, Test_DLUL) CC_ID, RU_Port_ID, seq_id, - do_copy); + do_copy, + staticEn); ASSERT_EQ(prep_bytes, 3168); @@ -113,11 +115,11 @@ TEST_P(U_planeCheck, Test_DLUL) sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr)); - ASSERT_EQ (ecpri_hdr->cmnhdr.ecpri_mesg_type, ECPRI_IQ_DATA); - payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.ecpri_payl_size); + ASSERT_EQ (ecpri_hdr->cmnhdr.bits.ecpri_mesg_type, ECPRI_IQ_DATA); + payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.bits.ecpri_payl_size); ASSERT_EQ (payl_size, 3180); - ASSERT_EQ(app_hdr->data_direction, direction); + ASSERT_EQ(app_hdr->data_feature.data_direction, direction); ASSERT_EQ(app_hdr->frame_id, frame_id); res_sect.fields.all_bits = rte_be_to_cpu_32(section_hdr->fields.all_bits); @@ -127,7 +129,7 @@ TEST_P(U_planeCheck, Test_DLUL) { /* UL direction */ void *iq_samp_buf; - struct ecpri_seq_id seq; + union ecpri_seq_id seq; int num_bytes = 0; uint8_t CC_ID = 0; @@ -167,6 +169,7 @@ TEST_P(U_planeCheck, Test_DLUL) &rb, §_id, 0, + XRAN_COMP_HDR_TYPE_DYNAMIC, &compMeth, &iqWidth); diff --git a/fhi_lib/test/test_xran/u_plane_performance.cc b/fhi_lib/test/test_xran/u_plane_performance.cc index ef31d7e..757a9b9 100644 --- a/fhi_lib/test/test_xran/u_plane_performance.cc +++ b/fhi_lib/test/test_xran/u_plane_performance.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,13 +20,90 @@ #include "common.hpp" #include "xran_common.h" +#include "xran_up_api.h" #include "xran_fh_o_du.h" #include "ethernet.h" #include -const std::string module_name = "u-plane"; +const std::string module_name = "U-Plane"; + + /*union xran_test { + struct { + struct xran_cp_radioapp_common_header cmnhdr; + struct xran_radioapp_udComp_header udComp; + uint8_t reserved; + }field; + struct { + uint32_t data_one; + uint32_t data_two; + }all_data; + };*/ + void fucntional_dl(struct rte_mbuf *test_buffer, char * iq_offset) + { + enum xran_pkt_dir direction = XRAN_DIR_DL; + uint16_t section_id = 7; + enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER; + uint8_t frame_id = 99; + uint8_t subframe_id = 9; + uint8_t slot_id = 10; + uint8_t symbol_no = 7; + int prb_start = 0; + int prb_num = 66; + uint8_t CC_ID = 0; + uint8_t RU_Port_ID = 0; + uint8_t seq_id =0; + uint32_t do_copy = 0; + uint8_t compMeth = 0; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; + uint8_t iqWidth = 16; + int32_t prep_bytes; + + prep_bytes = prepare_symbol_ex(direction, + section_id, + test_buffer, + (uint8_t *)iq_offset, + compMeth, + iqWidth, + iq_buf_byte_order, + frame_id, + subframe_id, + slot_id, + symbol_no, + prb_start, + prb_num, + CC_ID, + RU_Port_ID, + seq_id, + do_copy, + staticEn); + + /*union xran_cp_radioapp_section_ext11 *ext11 = NULL; + struct xran_sectionext11_info *params = NULL; + int i; + ext11 = (union xran_cp_radioapp_section_ext11 *)(iq_offset); + params = (struct xran_sectionext11_info *)(iq_offset+100); + + params->RAD = 1; + params->disableBFWs = 1; + params->numBundPrb = 1; + params->bfwCompMeth = 2; + + for(i = 0; i< 10000; i++) + { + ext11->data_field.data_field1 = (XRAN_CP_SECTIONEXTCMD_11 << 24) | (params->RAD << 7) | (params->disableBFWs << 8); + //ext11->data_field.data_field1 = (XRAN_CP_SECTIONEXTCMD_11 << 24)' + //ext11->all_bits.RAD = params->RAD; + //ext11->all_bits.disableBFWs = params->disableBFWs; + ext11->data_field.data_field2 = (params->bfwCompMeth << 4) | params->numBundPrb; + //ext11->all_bits.numBundPrb = params->numBundPrb; + //ext11->all_bits.bfwCompMeth = params->bfwCompMeth; + + }*/ + //printf("ext11->data_field.data_field1 is %d\n", ext11->data_field.data_field1); + //ASSERT_EQ(prep_bytes, 3168); + } class U_planePerf : public KernelTests { @@ -36,22 +113,21 @@ protected: struct rte_mbuf *test_buffer; char * iq_offset; - struct rte_mempool *test_eth_mbuf_pool; void SetUp() override { /* Parameters stored in the functional section will be used. GTest will call TEST_P (including SetUp and TearDown) for each case in the section. */ init_test("u_plane_performace"); - test_eth_mbuf_pool = rte_pktmbuf_pool_create("mempool", NUM_MBUFS, - MBUF_CACHE, 0, MBUF_POOL_ELEMENT, rte_socket_id()); + test_buffer = (struct rte_mbuf*)rte_pktmbuf_alloc(_eth_mbuf_pool); /* buffer size defined as the maximum size of all inputs/outputs in BYTE */ - const int buffer_size = 9600; - test_buffer = (struct rte_mbuf*)rte_pktmbuf_alloc(test_eth_mbuf_pool); - + if(test_buffer == NULL) { + std::cout << __func__ << ":" << __LINE__ << " Failed to allocatte a packet buffer!" << std::endl; + return; + } iq_offset = rte_pktmbuf_mtod(test_buffer, char * ); - iq_offset = iq_offset + sizeof(struct ether_hdr) + + iq_offset = iq_offset + sizeof(struct rte_ether_hdr) + sizeof (struct xran_ecpri_hdr) + sizeof (struct radio_app_common_hdr) + sizeof(struct data_section_hdr); @@ -63,47 +139,12 @@ protected: rte_pktmbuf_free(test_buffer); } - void fucntional_dl(F function, int32_t* request, int32_t* response) - { - enum xran_pkt_dir direction = XRAN_DIR_DL; - uint16_t section_id = 0; - enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER; - uint8_t frame_id = 0; - uint8_t subframe_id = 0; - uint8_t slot_id = 0; - uint8_t symbol_no = 0; - int prb_start = 0; - int prb_num = 66; - uint8_t CC_ID = 0; - uint8_t RU_Port_ID = 0; - uint8_t seq_id =0; - uint32_t do_copy = 0; - - int32_t prep_bytes; - prep_bytes = prepare_symbol_ex(direction, - section_id, - test_buffer, - (struct rb_map *)iq_offset, - iq_buf_byte_order, - frame_id, - subframe_id, - slot_id, - symbol_no, - prb_start, - prb_num, - CC_ID, - RU_Port_ID, - seq_id, - do_copy); - - //ASSERT_EQ(prep_bytes, 3168); - } }; -TEST_P(U_planePerf, Test_DL) +TEST_P(U_planePerf, Perf) { - performance("C", module_name, fucntional_dl, &request, &response); + performance("C", module_name, &fucntional_dl, test_buffer, iq_offset); } INSTANTIATE_TEST_CASE_P(UnitTest, U_planePerf, diff --git a/fhi_lib/test/test_xran/unittests.cc b/fhi_lib/test/test_xran/unittests.cc index 5b0b02c..7a17c1a 100644 --- a/fhi_lib/test/test_xran/unittests.cc +++ b/fhi_lib/test/test_xran/unittests.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/Makefile b/wls_lib/Makefile index 78262a4..b258e09 100644 --- a/wls_lib/Makefile +++ b/wls_lib/Makefile @@ -1,6 +1,6 @@ ############################################################################### # -# Copyright (c) 2019 Intel. +# Copyright (c) 2021 Intel. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -16,17 +16,146 @@ # ############################################################################### +MYCUSTOMTAB=' ' +MYCUSTOMSPACE='============================================================================================' +MYCUSTOMSPACE1='------------------------------------------------------------' + +############################################################## +# Tools configuration +############################################################## +CC := icc +AS := as +AR := ar +LD := icc +OBJDUMP := objdump + +ifeq ($(SHELL),cmd.exe) +MD := mkdir.exe -p +CP := cp.exe -f +RM := rm.exe -rf +else +MD := mkdir -p +CP := cp -f +RM := rm -rf +endif + +PROJECT_NAME := libwls +PROJECT_TYPE := lib +PROJECT_DIR := ./ +BUILDDIR := make +PROJECT_BINARY := $(PROJECT_NAME).so + ifeq ($(RTE_SDK),) $(error "Please define RTE_SDK environment variable") endif -# Default target, can be overridden by command line or environment -RTE_TARGET ?= x86_64-native-linuxapp-icc -RTE_OUTPUT = ${PWD} -include $(RTE_SDK)/mk/rte.vars.mk -SRCS-y := wls_lib_dpdk.c syslib.c -SHARED = libwls.so +ifeq ($(MESON_BUILD),0) +RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) +endif + +CC_SRC = wls_lib_dpdk.c \ + syslib.c + +CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ + -fdata-sections \ + -ffunction-sections \ + -g \ + -fPIC \ + -Wall \ + -Wimplicit-function-declaration \ + -g -O3 -wd1786 -mcmodel=large + +INC := -I$(RTE_INC) +DEF := + +AS_FLAGS := +AR_FLAGS := rc + +PROJECT_OBJ_DIR := $(BUILDDIR)/obj + +CC_OBJS := $(patsubst %.c,%.o,$(CC_SRC)) +AS_OBJS := $(patsubst %.s,%.o,$(AS_SRC)) +OBJS := $(CC_OBJS) $(AS_OBJS) $(LIBS) +DIRLIST := $(addprefix $(PROJECT_OBJ_DIR)/,$(sort $(dir $(OBJS)))) + +CC_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(CC_OBJS)) + +AS_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(AS_OBJS)) +CC_FLAGS_FULL := $(CC_FLAGS) $(INC) $(DEF) + +AS_FLAGS := $(AS_FLAGS) $(INC) + +PROJECT_DEP_FILE := $(PROJECT_OBJ_DIR)/$(PROJECT_NAME).dep + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) +GENERATE_DEPS := +else + +CC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CC_SRC))) +GENERATE_DEPS := generate_deps +endif + +all : welcome_line $(PROJECT_BINARY) + @echo $(PROJECT_BINARY) + +.PHONY : clear_dep +clear_dep: + @$(RM) $(PROJECT_DEP_FILE) + @echo [DEP] $(subst $(PROJECT_OBJ_DIR)/,,$(PROJECT_DEP_FILE)) + +$(CC_DEPS) : + @$(CC) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(PROJECT_OBJ_DIR)/$(patsubst %.c,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CC_FLAGS_FULL) >> $(PROJECT_DEP_FILE) + +.PHONY : generate_deps +generate_deps : clear_dep $(CC_DEPS) + + +.PHONY : echo_start_build +echo_start_build : + @echo [BUILD] $(PROJECT_TYPE) : $(PROJECT_NAME) + +$(DIRLIST) : + -@$(MD) $@ + +$(CC_OBJTARGETS) : + @echo [CC] $(subst $(PROJECT_OBJ_DIR)/,,$@) + @$(CC) -c $(CC_FLAGS_FULL) -o"$@" $(patsubst %.o,%.c,$(subst $(PROJECT_OBJ_DIR)/,,$@)) + +$(AS_OBJTARGETS) : + @echo [AS] $(subst $(PROJECT_OBJ_DIR)/,,$@) + @$(AS) $(AS_FLAGS) -o"$@" $(patsubst %.o,%.s,$(subst $(PROJECT_OBJ_DIR)/,,$@)) + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) + +include $(PROJECT_DEP_FILE) + +endif + +.PHONY: clean xclean +clean: + @echo [CLEAN] : $(PROJECT_NAME) + @$(RM) $(CC_OBJTARGETS) $(AS_OBJTARGETS) +ifneq ($(wildcard $(PROJECT_DIR)/$(PROJECT_MAKE)),) + @echo [CLEAN] : $(PROJECT_NAME) + @$(RM) $(PROJECT_BINARY) $(PROJECT_BINARY_LIB) $(PROJECT_DEP_FILE) +endif + +xclean: clean + +.PHONY : welcome_line +welcome_line : + @echo $(MYCUSTOMSPACE) + @echo Building $(PROJECT_BINARY) + @echo $(MYCUSTOMSPACE) + +.PHONY : debug release + +debug : all +release : all + +$(PROJECT_BINARY) : $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(AS_OBJTARGETS) + @echo [AR] $(subst $(BUILDDIR)/,,$@) + @$(CC) $(CC_OBJTARGETS) $(AS_OBJTARGETS) -shared -fPIC -o $@ -CFLAGS +=-Wall -fstack-protector -EXTRA_CFLAGS +=-g -include $(RTE_SDK)/mk/rte.extshared.mk diff --git a/wls_lib/build.sh b/wls_lib/build.sh index 2613065..3d1b1de 100755 --- a/wls_lib/build.sh +++ b/wls_lib/build.sh @@ -1,7 +1,7 @@ #!/bin/sh ############################################################################### # -# Copyright (c) 2019 Intel. +# Copyright (c) 2021 Intel. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -22,6 +22,6 @@ # echo "Building dpdk based wls library" -make ${*:2} +make $* cd testapp -make ${*:2} \ No newline at end of file +make $* \ No newline at end of file diff --git a/wls_lib/syslib.c b/wls_lib/syslib.c index ce81c90..f76b6d7 100644 --- a/wls_lib/syslib.c +++ b/wls_lib/syslib.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/syslib.h b/wls_lib/syslib.h index 1b52470..df46896 100644 --- a/wls_lib/syslib.h +++ b/wls_lib/syslib.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/test/bin/fapi/fapi.sh b/wls_lib/test/bin/fapi/fapi.sh index d5a72fa..e606776 100755 --- a/wls_lib/test/bin/fapi/fapi.sh +++ b/wls_lib/test/bin/fapi/fapi.sh @@ -1,8 +1,20 @@ -####################################################################### +############################################################################### # -# +# Copyright (c) 2019 Intel. # -####################################################################### +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################### export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS MACHINE_TYPE=`uname -m` diff --git a/wls_lib/test/bin/mac/mac.sh b/wls_lib/test/bin/mac/mac.sh index 9b0b4e4..0f06dd2 100755 --- a/wls_lib/test/bin/mac/mac.sh +++ b/wls_lib/test/bin/mac/mac.sh @@ -1,8 +1,20 @@ -####################################################################### +############################################################################### # -# +# Copyright (c) 2019 Intel. # -####################################################################### +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################### export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS MACHINE_TYPE=`uname -m` diff --git a/wls_lib/test/bin/phy/phy.sh b/wls_lib/test/bin/phy/phy.sh index 41c1ea8..a300426 100755 --- a/wls_lib/test/bin/phy/phy.sh +++ b/wls_lib/test/bin/phy/phy.sh @@ -1,8 +1,20 @@ -####################################################################### +############################################################################### # -# +# Copyright (c) 2019 Intel. # -####################################################################### +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################### export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS MACHINE_TYPE=`uname -m` diff --git a/wls_lib/test/fapi/fapi_main.c b/wls_lib/test/fapi/fapi_main.c index 7c1a14a..9492ad0 100644 --- a/wls_lib/test/fapi/fapi_main.c +++ b/wls_lib/test/fapi/fapi_main.c @@ -49,7 +49,6 @@ #define WLS_TEST_DEV_NAME "wls" #define WLS_TEST_MSG_ID 1 #define WLS_TEST_MSG_SIZE 100 -#define WLS_TEST_MEM_SIZE 2126512128 #define ALLOC_TRACK_SIZE 16384 #define MIN_UL_BUF_LOCATIONS 50 #define MIN_DL_BUF_LOCATIONS 50 @@ -115,7 +114,7 @@ WLS_HANDLE g_phy_wls = &gphy_wls; WLS_HANDLE g_fapi_wls = &gfapi_wls; uint8_t fapi_dpdk_init(void); -uint8_t fapi_wls_init(const char *dev_name, unsigned long long mem_size); +uint8_t fapi_wls_init(const char *dev_name); uint64_t fapi_mac_recv(); uint8_t fapi_phy_send(); uint64_t fapi_phy_recv(); @@ -391,7 +390,7 @@ int main() printf("\n[FAPI] DPDK Init - Done\n"); // WLS init - ret = fapi_wls_init(WLS_TEST_DEV_NAME, WLS_TEST_MEM_SIZE); + ret = fapi_wls_init(WLS_TEST_DEV_NAME); if(ret) { printf("\n[FAPI] WLS Init - Failed\n"); @@ -474,7 +473,7 @@ uint8_t fapi_dpdk_init(void) int argc = RTE_DIM(argv); /* initialize EAL first */ - sprintf(whitelist, "-w %s", "0000:00:06.0"); + sprintf(whitelist, "-a%s", "0000:00:06.0"); printf("[FAPI] Calling rte_eal_init: "); for (i = 0; i < RTE_DIM(argv); i++) @@ -489,22 +488,24 @@ uint8_t fapi_dpdk_init(void) return SUCCESS; } -uint8_t fapi_wls_init(const char *dev_name, unsigned long long mem_size) +uint8_t fapi_wls_init(const char *dev_name) { + uint64_t nWlsMacMemorySize; + uint64_t nWlsPhyMemorySize; uint8_t *pMemZone; static const struct rte_memzone *mng_memzone; p_nr5g_fapi_wls_context_t p_wls_ctx = nr5g_fapi_wls_context(); wls_drv_ctx_t *pDrv_ctx; p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST] = - WLS_Open_Dual(dev_name, WLS_SLAVE_CLIENT, mem_size, &p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]); + WLS_Open_Dual(dev_name, WLS_SLAVE_CLIENT, &nWlsMacMemorySize, &nWlsPhyMemorySize, &p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]); if((NULL == p_wls_ctx->h_wls[NR5G_FAPI2PHY_WLS_INST]) && (NULL == p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST])) { return FAILURE; } - g_shmem_size = mem_size; - p_wls_ctx->shmem_size = mem_size; + g_shmem_size = nWlsMacMemorySize + nWlsPhyMemorySize; + p_wls_ctx->shmem_size = g_shmem_size; // Issue WLS_Alloc() for FAPI2MAC p_wls_ctx->shmem = WLS_Alloc( p_wls_ctx->h_wls[NR5G_FAPI2MAC_WLS_INST], diff --git a/wls_lib/test/fapi/makefile b/wls_lib/test/fapi/makefile index 4a3aafa..b5cd4b7 100644 --- a/wls_lib/test/fapi/makefile +++ b/wls_lib/test/fapi/makefile @@ -41,15 +41,14 @@ endif ############################################################## # TARGET ############################################################## -ifeq ($(RTE_TARGET),) - RTE_TARGET :=x86_64-native-linuxapp-icc -endif -############################################################## -# DPDK -############################################################## ifeq ($(RTE_SDK),) -$(info Please make sure RTE_SDK points to DPDK folder (current version of DPDK is 18.08)) - RTE_SDK := /opt/dpdk-18.08 + $(error "Please define RTE_SDK environment variable") +endif + +ifeq ($(MESON_BUILD),0) +RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) endif ############################################################## @@ -64,11 +63,9 @@ wls_fapi_app_dep_file = $(BUILDDIR)/dep_file APP := ../bin/fapi/fapi_app INC := \ - $(WLSDIR) \ - $(SRCDIR) \ - $(RTE_SDK)/$(RTE_TARGET)/include \ - -INC := $(addprefix -I,$(INC)) + -I$(WLSDIR) \ + -I$(SRCDIR) \ + $(RTE_INC) \ DEFS := USE_WO_LOCK _GNU_SOURCE NR5G @@ -89,7 +86,11 @@ CFLAGS := $(CFLAGS) -Werror endif #RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +ifeq ($(MESON_BUILD),0) RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +else +RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive +endif LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls LINUX_WLS_FAPI_APP_SRC := \ @@ -113,13 +114,14 @@ endif .PHONY: $(APP) $(APP): $(DIRLIST) echo_options $(GEN_DEP) $(OBJS) @echo [LD] $(APP) - @$(CC) -o $(APP) $(OBJS) $(RTE_LIBS) $(LDFLAGS) + @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS) # $(OBJDUMP) -d $(APP) > $(APP).asm .PHONY : echo_options echo_options: @echo [CFLAGS] $(CFLAGS) @echo [LDFAGS] $(LDFLAGS) + @echo [RTE_LIBS] $(RTE_LIBS) ifneq ($(wildcard $(wls_fapi_app_dep_file)),) diff --git a/wls_lib/test/mac/mac_main.c b/wls_lib/test/mac/mac_main.c index 4d6c902..bc8a235 100644 --- a/wls_lib/test/mac/mac_main.c +++ b/wls_lib/test/mac/mac_main.c @@ -33,7 +33,6 @@ #define WLS_TEST_DEV_NAME "wls" #define WLS_TEST_MSG_ID 1 #define WLS_TEST_MSG_SIZE 100 -#define WLS_TEST_MEM_SIZE 2126512128 #define N_MAC_MSGS 16 @@ -53,7 +52,7 @@ int main() } printf("\n[MAC] DPDK Init - Done\n"); - wls_mac_init(WLS_TEST_DEV_NAME, WLS_TEST_MEM_SIZE); + wls_mac_init(WLS_TEST_DEV_NAME, WLS_MSG_BLOCK_SIZE); printf("\n[MAC] WLS Init - Done\n"); for (i=0; i< N_MAC_MSGS; i++) diff --git a/wls_lib/test/mac/mac_wls.c b/wls_lib/test/mac/mac_wls.c index 07a4f8c..780282f 100644 --- a/wls_lib/test/mac/mac_wls.c +++ b/wls_lib/test/mac/mac_wls.c @@ -62,7 +62,7 @@ #define TOTAL_FREE_BLOCKS ( 50 * 12) #define ALLOC_TRACK_SIZE ( 16384 ) -#define MEMORY_CORRUPTION_DETECT +//#define MEMORY_CORRUPTION_DETECT #define MEMORY_CORRUPTION_DETECT_FLAG (0xAB) typedef struct wls_mac_mem_array @@ -78,9 +78,12 @@ typedef struct wls_mac_ctx { void *hWls; void *pWlsMemBase; + void *pWlsMemBaseUsable; WLS_MAC_MEM_SRUCT sWlsStruct; - uint32_t nTotalMemorySize; + uint64_t nTotalMemorySize; + uint64_t nTotalMemorySizeUsable; + uint32_t nBlockSize; uint32_t nTotalBlocks; uint32_t nAllocBlocks; uint32_t nTotalAllocCnt; @@ -1191,8 +1194,10 @@ p_fapi_api_queue_elem_t wls_mac_create_elem(uint16_t num_msg, uint32_t align_off * **/ //------------------------------------------------------------------------------------------- -uint32_t wls_mac_init(char * wls_device_name, uint64_t nTotalMemorySize) +uint32_t wls_mac_init(char * wls_device_name, uint64_t nBlockSize) { + uint64_t nWlsMacMemSize; + uint64_t nWlsPhyMemSize; uint32_t ret = FAILURE; PWLS_MAC_CTX pWls = wls_mac_get_ctx(); uint8_t *pMemZone; @@ -1211,14 +1216,15 @@ uint32_t wls_mac_init(char * wls_device_name, uint64_t nTotalMemorySize) pWls->nTotalDlBufAllocCnt = 0; pWls->nTotalDlBufFreeCnt = 0; - pWls->hWls = WLS_Open(wls_device_name, WLS_MASTER_CLIENT, nTotalMemorySize); + pWls->hWls = WLS_Open(wls_device_name, WLS_MASTER_CLIENT, &nWlsMacMemSize, &nWlsPhyMemSize); if (pWls->hWls) { /* allocate chuck of memory */ - pWls->pWlsMemBase = WLS_Alloc(pWls->hWls, nTotalMemorySize); + pWls->pWlsMemBase = WLS_Alloc(pWls->hWls, nWlsMacMemSize+nWlsPhyMemSize); if (pWls->pWlsMemBase) { - pWls->nTotalMemorySize = (uint32_t) nTotalMemorySize; + pWls->nTotalMemorySize = nWlsMacMemSize; + // pWls->nBlockSize = wls_mac_check_block_size(nBlockSize); ret = wls_mac_create_partition(pWls); @@ -1306,7 +1312,7 @@ uint8_t mac_dpdk_init() int argc = RTE_DIM(argv); /* initialize EAL first */ - sprintf(whitelist, "-w %s", "0000:00:06.0"); + sprintf(whitelist, "-a%s", "0000:00:06.0"); printf("[MAC] Calling rte_eal_init: "); for (i = 0; i < RTE_DIM(argv); i++) diff --git a/wls_lib/test/mac/mac_wls.h b/wls_lib/test/mac/mac_wls.h index 27b41a6..171ec95 100644 --- a/wls_lib/test/mac/mac_wls.h +++ b/wls_lib/test/mac/mac_wls.h @@ -45,6 +45,8 @@ extern "C" { #define MAX_DL_BUF_LOCATIONS (MIN_DL_BUF_LOCATIONS + MAX_NUM_LOCATIONS) /* Used for stats collection 0-49 */ #define MAX_UL_BUF_LOCATIONS (MIN_UL_BUF_LOCATIONS + MAX_NUM_LOCATIONS) /* Used for stats collection 50-99 */ +#define WLS_MSG_BLOCK_SIZE ( 16384 * 16 ) + typedef struct tagZBC_LIST_ITEM { uint64_t pMsg; @@ -52,7 +54,7 @@ typedef struct tagZBC_LIST_ITEM } ZBC_LIST_ITEM, *PZBC_LIST_ITEM; -uint32_t wls_mac_init(char * wls_device_name, uint64_t nWlsMemorySize); +uint32_t wls_mac_init(char * wls_device_name, uint64_t nBlockSize); void wls_mac_print_thread_info(void); uint32_t wls_mac_destroy(void); void *wls_mac_alloc_buffer(uint32_t size, uint32_t loc); diff --git a/wls_lib/test/mac/makefile b/wls_lib/test/mac/makefile index 882f639..b2271a1 100644 --- a/wls_lib/test/mac/makefile +++ b/wls_lib/test/mac/makefile @@ -41,17 +41,16 @@ endif ############################################################## # TARGET ############################################################## -ifeq ($(RTE_TARGET),) - RTE_TARGET :=x86_64-native-linuxapp-icc -endif -############################################################## -# DPDK -############################################################## ifeq ($(RTE_SDK),) -$(info Please make sure RTE_SDK points to DPDK folder (current version of DPDK is 18.08)) - RTE_SDK := /opt/dpdk-18.08 + $(error "Please define RTE_SDK environment variable") endif +#ifeq ($(MESON_BUILD),0) +#RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +#else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) +#endif + ############################################################## # Projects folders ############################################################## @@ -65,16 +64,14 @@ wls_mac_app_dep_file = $(BUILDDIR)/dep_file APP := ../bin/mac/mac_app INC := \ - $(WLSDIR) \ - $(SRCDIR) \ - $(RTE_SDK)/$(RTE_TARGET)/include \ - $(ORANDIR)/include \ - $(ORANDIR) \ + -I$(WLSDIR) \ + -I$(SRCDIR) \ + -I$(ORANDIR)/include \ + -I$(ORANDIR) \ + -I$(RTE_INC) \ #$(FLEXRANDIR)/source/nr5g/api \ #$(FLEXRANDIR)/source/common \ -INC := $(addprefix -I,$(INC)) - DEFS := USE_WO_LOCK _GNU_SOURCE NR5G ifneq ($(PRINTDBG),) @@ -94,7 +91,11 @@ CFLAGS := $(CFLAGS) -Werror endif #RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive -RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +#ifeq ($(MESON_BUILD),0) +#RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +#else +RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive +#endif LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls LINUX_WLS_MAC_APP_SRC := \ @@ -119,15 +120,15 @@ endif .PHONY: $(APP) $(APP): $(DIRLIST) echo_options $(GEN_DEP) $(OBJS) @echo [LD] $(APP) - @$(CC) -o $(APP) $(OBJS) $(RTE_LIBS) $(LDFLAGS) + @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS) # $(OBJDUMP) -d $(APP) > $(APP).asm .PHONY : echo_options echo_options: @echo [CFLAGS] $(CFLAGS) @echo [LDFAGS] $(LDFLAGS) - - + @echo [RTE_LIBS] $(RTE_LIBS) + @echo [ORANDIR] $(ORANDIR) ifneq ($(wildcard $(wls_mac_app_dep_file)),) include $(wls_mac_app_dep_file) endif diff --git a/wls_lib/test/phy/makefile b/wls_lib/test/phy/makefile index f18d9d2..fc4ae19 100644 --- a/wls_lib/test/phy/makefile +++ b/wls_lib/test/phy/makefile @@ -41,15 +41,14 @@ endif ############################################################## # TARGET ############################################################## -ifeq ($(RTE_TARGET),) - RTE_TARGET :=x86_64-native-linuxapp-icc -endif -############################################################## -# DPDK -############################################################## ifeq ($(RTE_SDK),) -$(info Please make sure RTE_SDK points to DPDK folder (current version of DPDK is 18.08)) - RTE_SDK := /opt/dpdk-18.08 + $(error "Please define RTE_SDK environment variable") +endif + +ifeq ($(MESON_BUILD),0) +RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) endif ############################################################## @@ -64,11 +63,9 @@ wls_phy_app_dep_file = $(BUILDDIR)/dep_file APP := ../bin/phy/phy_app INC := \ - $(WLSDIR) \ - $(SRCDIR) \ - $(RTE_SDK)/$(RTE_TARGET)/include \ - -INC := $(addprefix -I,$(INC)) + -I$(WLSDIR) \ + -I$(SRCDIR) \ + $(RTE_INC) \ DEFS := USE_WO_LOCK _GNU_SOURCE NR5G @@ -88,7 +85,11 @@ ifeq ($(PRINTDBG),) CFLAGS := $(CFLAGS) -Werror endif -RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_port -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +ifeq ($(MESON_BUILD),0) +RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_distributor -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lm -Wl,-lrt -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_mempool -Wl,-lrte_mempool_ring -Wl,-lrte_ring -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_pci -Wl,-lrte_net -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl, -lrte_cryptodev -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +else +RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive +endif LDFLAGS := -g -Wl,-lrt -Wl,-lpthread -Wl,-lhugetlbfs -Wl,-lm -Wl,-lnuma -L $(WLSDIR) -lwls LINUX_WLS_PHY_APP_SRC := \ @@ -112,14 +113,14 @@ endif .PHONY: $(APP) $(APP): $(DIRLIST) echo_options $(GEN_DEP) $(OBJS) @echo [LD] $(APP) - @$(CC) -o $(APP) $(OBJS) $(RTE_LIBS) $(LDFLAGS) + @$(CC) -o $(APP) $(OBJS) $(LDFLAGS) $(RTE_LIBS) # $(OBJDUMP) -d $(APP) > $(APP).asm .PHONY : echo_options echo_options: @echo [CFLAGS] $(CFLAGS) @echo [LDFAGS] $(LDFLAGS) - + @echo [RTE_LIBS] $(RTE_LIBS) ifneq ($(wildcard $(wls_phy_app_dep_file)),) include $(wls_phy_app_dep_file) diff --git a/wls_lib/test/phy/phy_main.c b/wls_lib/test/phy/phy_main.c index cf3dd61..2a48c0b 100644 --- a/wls_lib/test/phy/phy_main.c +++ b/wls_lib/test/phy/phy_main.c @@ -43,7 +43,8 @@ #define WLS_TEST_DEV_NAME "wls" #define WLS_TEST_MSG_ID 1 #define WLS_TEST_MSG_SIZE 100 -#define WLS_TEST_MEM_SIZE 2126512128 +#define WLS_MAC_MEMORY_SIZE 0x3EA80000 +#define WLS_PHY_MEMORY_SIZE 0x18000000 #define NUM_PHY_MSGS 16 typedef void* WLS_HANDLE; @@ -53,7 +54,7 @@ uint64_t g_shmem_size; WLS_HANDLE g_fapi_wls, g_phy_wls; uint8_t phy_dpdk_init(void); -uint8_t phy_wls_init(const char *dev_name, unsigned long long mem_size); +uint8_t phy_wls_init(const char *dev_name, uint64_t nWlsMacMemSize, uint64_t nWlsPhyMemSize); uint64_t phy_fapi_recv(); uint8_t phy_fapi_send(); @@ -72,7 +73,7 @@ int main() printf("\n[PHY] DPDK Init - Done\n"); // WLS init - ret = phy_wls_init(WLS_TEST_DEV_NAME, WLS_TEST_MEM_SIZE); + ret = phy_wls_init(WLS_TEST_DEV_NAME, WLS_MAC_MEMORY_SIZE, WLS_PHY_MEMORY_SIZE); if(ret) { printf("\n[PHY] WLS Init - Failed\n"); @@ -114,7 +115,7 @@ uint8_t phy_dpdk_init(void) int argc = RTE_DIM(argv); /* initialize EAL first */ - sprintf(whitelist, "-w %s", "0000:00:06.0"); + sprintf(whitelist, "-a%s", "0000:00:06.0"); printf("[PHY] Calling rte_eal_init: "); for (i = 0; i < RTE_DIM(argv); i++) @@ -129,14 +130,14 @@ uint8_t phy_dpdk_init(void) return SUCCESS; } -uint8_t phy_wls_init(const char *dev_name, unsigned long long mem_size) +uint8_t phy_wls_init(const char *dev_name, uint64_t nWlsMacMemSize, uint64_t nWlsPhyMemSize) { - g_phy_wls = WLS_Open(dev_name, WLS_SLAVE_CLIENT, mem_size); + g_phy_wls = WLS_Open(dev_name, WLS_SLAVE_CLIENT, &nWlsMacMemSize, &nWlsPhyMemSize); if(NULL == g_phy_wls) { return FAILURE; } - g_shmem_size = mem_size; + g_shmem_size = nWlsMacMemSize+nWlsPhyMemSize; g_shmem = WLS_Alloc(g_phy_wls, g_shmem_size); if (NULL == g_shmem) diff --git a/wls_lib/testapp/Makefile b/wls_lib/testapp/Makefile index ddd1396..bc47f96 100644 --- a/wls_lib/testapp/Makefile +++ b/wls_lib/testapp/Makefile @@ -1,6 +1,6 @@ ############################################################################### # -# Copyright (c) 2019 Intel. +# Copyright (c) 2021 Intel. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -16,25 +16,158 @@ # ############################################################################### +MYCUSTOMTAB=' ' +MYCUSTOMSPACE='============================================================================================' +MYCUSTOMSPACE1='------------------------------------------------------------' + +############################################################## +# Tools configuration +############################################################## +CC := icc +AS := as +AR := ar +LD := icc +OBJDUMP := objdump + +ifeq ($(SHELL),cmd.exe) +MD := mkdir.exe -p +CP := cp.exe -f +RM := rm.exe -rf +else +MD := mkdir -p +CP := cp -f +RM := rm -rf +endif + +PROJECT_NAME := wls_test +PROJECT_TYPE := elf +PROJECT_DIR := ./ +BUILDDIR := make +PROJECT_BINARY := $(PROJECT_NAME) ifeq ($(RTE_SDK),) $(error "Please define RTE_SDK environment variable") endif -# Default target, can be overridden by command line or environment -RTE_TARGET ?= x86_64-native-linuxapp-icc -include $(RTE_SDK)/mk/rte.vars.mk +ifeq ($(MESON_BUILD),0) +RTE_INC := $(RTE_SDK)/$(RTE_TARGET)/include +RTE_LIBS := -L$(RTE_SDK)/$(RTE_TARGET)/lib -Wl,--whole-archive -Wl,-lrte_mempool_ring -Wl,-lrte_pci -Wl,-lrte_bus_pci -Wl,-lrte_bus_vdev -Wl,-lrte_net -Wl,-lrte_distributor -Wl,-lrte_reorder -Wl,-lrte_kni -Wl,-lrte_pipeline -Wl,-lrte_table -Wl,-lrte_timer -Wl,-lrte_hash -Wl,-lrte_jobstats -Wl,-lrte_lpm -Wl,-lrte_power -Wl,-lrte_acl -Wl,-lrte_meter -Wl,-lrte_sched -Wl,-lrte_vhost -Wl,--start-group -Wl,-lrte_kvargs -Wl,-lrte_mbuf -Wl,-lrte_ip_frag -Wl,-lrte_ethdev -Wl,-lrte_cryptodev -Wl,-lrte_mempool -Wl,-lrte_ring -Wl,-lrte_eal -Wl,-lrte_cmdline -Wl,-lrte_cfgfile -Wl,-lrte_pmd_bond -Wl,-lrte_pmd_vmxnet3_uio -Wl,-lrte_pmd_virtio -Wl,-lrte_pmd_cxgbe -Wl,-lrte_pmd_enic -Wl,-lrte_pmd_i40e -Wl,-lrte_pmd_fm10k -Wl,-lrte_pmd_ixgbe -Wl,-lrte_pmd_e1000 -Wl,-lrte_pmd_ring -Wl,-lrte_pmd_af_packet -Wl,-lrte_pmd_null -Wl,-lrt -Wl,-lm -Wl,-ldl -Wl,--end-group -Wl,--no-whole-archive +RTE_LIBS += -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--no-whole-archive +else +RTE_INC := $(shell PKG_CONFIG_PATH=$(RTE_SDK)/build/meson-uninstalled pkg-config --cflags-only-I libdpdk) +RTE_LIBS := -Wl,--whole-archive -Wl,/usr/lib64/libnuma.so -Wl,--as-needed -pthread -L$(RTE_SDK)/build/drivers -L$(RTE_SDK)/build/lib -l:librte_common_cpt.a -l:librte_common_dpaax.a -l:librte_common_iavf.a -l:librte_common_octeontx.a -l:librte_common_octeontx2.a -l:librte_common_sfc_efx.a -l:librte_bus_dpaa.a -l:librte_bus_fslmc.a -l:librte_bus_ifpga.a -l:librte_bus_pci.a -l:librte_bus_vdev.a -l:librte_bus_vmbus.a -l:librte_mempool_bucket.a -l:librte_mempool_dpaa.a -l:librte_mempool_dpaa2.a -l:librte_mempool_octeontx.a -l:librte_mempool_octeontx2.a -l:librte_mempool_ring.a -l:librte_mempool_stack.a -l:librte_net_af_packet.a -l:librte_net_ark.a -l:librte_net_atlantic.a -l:librte_net_avp.a -l:librte_net_axgbe.a -l:librte_net_bond.a -l:librte_net_bnx2x.a -l:librte_net_bnxt.a -l:librte_net_cxgbe.a -l:librte_net_dpaa.a -l:librte_net_dpaa2.a -l:librte_net_e1000.a -l:librte_net_ena.a -l:librte_net_enetc.a -l:librte_net_enic.a -l:librte_net_failsafe.a -l:librte_net_fm10k.a -l:librte_net_i40e.a -l:librte_net_hinic.a -l:librte_net_hns3.a -l:librte_net_iavf.a -l:librte_net_ice.a -l:librte_net_igc.a -l:librte_net_ixgbe.a -l:librte_net_kni.a -l:librte_net_liquidio.a -l:librte_net_memif.a -l:librte_net_netvsc.a -l:librte_net_nfp.a -l:librte_net_null.a -l:librte_net_octeontx.a -l:librte_net_octeontx2.a -l:librte_net_pfe.a -l:librte_net_qede.a -l:librte_net_ring.a -l:librte_net_sfc.a -l:librte_net_tap.a -l:librte_net_thunderx.a -l:librte_net_txgbe.a -l:librte_net_vdev_netvsc.a -l:librte_net_vhost.a -l:librte_net_virtio.a -l:librte_net_vmxnet3.a -l:librte_raw_dpaa2_cmdif.a -l:librte_raw_dpaa2_qdma.a -l:librte_raw_ioat.a -l:librte_raw_ntb.a -l:librte_raw_octeontx2_dma.a -l:librte_raw_octeontx2_ep.a -l:librte_raw_skeleton.a -l:librte_crypto_bcmfs.a -l:librte_crypto_caam_jr.a -l:librte_crypto_dpaa_sec.a -l:librte_crypto_dpaa2_sec.a -l:librte_crypto_nitrox.a -l:librte_crypto_null.a -l:librte_crypto_octeontx.a -l:librte_crypto_octeontx2.a -l:librte_crypto_scheduler.a -l:librte_crypto_virtio.a -l:librte_compress_octeontx.a -l:librte_compress_zlib.a -l:librte_regex_octeontx2.a -l:librte_vdpa_ifc.a -l:librte_event_dlb.a -l:librte_event_dlb2.a -l:librte_event_dpaa.a -l:librte_event_dpaa2.a -l:librte_event_octeontx2.a -l:librte_event_opdl.a -l:librte_event_skeleton.a -l:librte_event_sw.a -l:librte_event_dsw.a -l:librte_event_octeontx.a -l:librte_node.a -l:librte_graph.a -l:librte_bpf.a -l:librte_flow_classify.a -l:librte_pipeline.a -l:librte_table.a -l:librte_fib.a -l:librte_ipsec.a -l:librte_vhost.a -l:librte_stack.a -l:librte_security.a -l:librte_sched.a -l:librte_reorder.a -l:librte_rib.a -l:librte_regexdev.a -l:librte_rawdev.a -l:librte_pdump.a -l:librte_power.a -l:librte_member.a -l:librte_lpm.a -l:librte_latencystats.a -l:librte_kni.a -l:librte_jobstats.a -l:librte_ip_frag.a -l:librte_gso.a -l:librte_gro.a -l:librte_eventdev.a -l:librte_efd.a -l:librte_distributor.a -l:librte_cryptodev.a -l:librte_compressdev.a -l:librte_cfgfile.a -l:librte_bitratestats.a -l:librte_bbdev.a -l:librte_acl.a -l:librte_timer.a -l:librte_hash.a -l:librte_metrics.a -l:librte_cmdline.a -l:librte_pci.a -l:librte_ethdev.a -l:librte_meter.a -l:librte_net.a -l:librte_mbuf.a -l:librte_mempool.a -l:librte_rcu.a -l:librte_ring.a -l:librte_eal.a -l:librte_telemetry.a -l:librte_kvargs.a -lelf -lrte_node -lrte_graph -lrte_bpf -lrte_flow_classify -lrte_pipeline -lrte_table -lrte_fib -lrte_ipsec -lrte_vhost -lrte_stack -lrte_security -lrte_sched -lrte_reorder -lrte_rib -lrte_regexdev -lrte_rawdev -lrte_pdump -lrte_power -lrte_member -lrte_lpm -lrte_latencystats -lrte_kni -lrte_jobstats -lrte_ip_frag -lrte_gso -lrte_gro -lrte_eventdev -lrte_efd -lrte_distributor -lrte_cryptodev -lrte_compressdev -lrte_cfgfile -lrte_bitratestats -lrte_bbdev -lrte_acl -lrte_timer -lrte_hash -lrte_metrics -lrte_cmdline -lrte_pci -lrte_ethdev -lrte_meter -lrte_net -lrte_mbuf -lrte_mempool -lrte_rcu -lrte_ring -lrte_eal -lrte_telemetry -lrte_kvargs -lm -ldl -lnuma -lz -Wl,--no-whole-archive +endif + +CC_SRC = pool.c \ + testapp.c + +CC_FLAGS += -std=gnu11 -Wall -Wno-deprecated-declarations \ + -fdata-sections \ + -ffunction-sections \ + -g \ + -Wall \ + -Wimplicit-function-declaration \ + -g -O3 -wd1786 -mcmodel=large + +INC := -I../ -I$(RTE_INC) +DEF := + +WLS_LIB_DIR=../ +LD_FLAGS += -L$(WLS_LIB_DIR) -lwls -lpthread -lhugetlbfs -lrt + +LD_FLAGS += $(RTE_LIBS) + +AS_FLAGS := +AR_FLAGS := rc + +PROJECT_OBJ_DIR := $(BUILDDIR)/obj + +CC_OBJS := $(patsubst %.c,%.o,$(CC_SRC)) +AS_OBJS := $(patsubst %.s,%.o,$(AS_SRC)) +OBJS := $(CC_OBJS) $(AS_OBJS) $(LIBS) +DIRLIST := $(addprefix $(PROJECT_OBJ_DIR)/,$(sort $(dir $(OBJS)))) + +CC_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(CC_OBJS)) + +AS_OBJTARGETS := $(addprefix $(PROJECT_OBJ_DIR)/,$(AS_OBJS)) + +CC_FLAGS_FULL := $(CC_FLAGS) $(INC) $(DEF) + +AS_FLAGS := $(AS_FLAGS) $(INC) + +PROJECT_DEP_FILE := $(PROJECT_OBJ_DIR)/$(PROJECT_NAME).dep + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) +GENERATE_DEPS := +else + +CC_DEPS := $(addprefix __dep__,$(subst ../,__up__,$(CC_SRC))) +GENERATE_DEPS := generate_deps +endif + +all : welcome_line $(PROJECT_BINARY) + @echo $(PROJECT_BINARY) + +.PHONY : clear_dep +clear_dep: + @$(RM) $(PROJECT_DEP_FILE) + @echo [DEP] $(subst $(PROJECT_OBJ_DIR)/,,$(PROJECT_DEP_FILE)) + +$(CC_DEPS) : + @$(CC) -MM $(subst __up__,../,$(subst __dep__,,$@)) -MT $(PROJECT_OBJ_DIR)/$(patsubst %.c,%.o,$(subst __up__,../,$(subst __dep__,,$@))) $(CC_FLAGS_FULL) >> $(PROJECT_DEP_FILE) + +.PHONY : generate_deps +generate_deps : clear_dep $(CC_DEPS) + + +.PHONY : echo_start_build +echo_start_build : + @echo [BUILD] $(PROJECT_TYPE) : $(PROJECT_NAME) + +$(DIRLIST) : + -@$(MD) $@ + +$(CC_OBJTARGETS) : + @echo [CC] $(subst $(PROJECT_OBJ_DIR)/,,$@) + @$(CC) -c $(CC_FLAGS_FULL) -o"$@" $(patsubst %.o,%.c,$(subst $(PROJECT_OBJ_DIR)/,,$@)) + +$(AS_OBJTARGETS) : + @echo [AS] $(subst $(PROJECT_OBJ_DIR)/,,$@) + @$(AS) $(AS_FLAGS) -o"$@" $(patsubst %.o,%.s,$(subst $(PROJECT_OBJ_DIR)/,,$@)) + +ifeq ($(wildcard $(PROJECT_DEP_FILE)),$(PROJECT_DEP_FILE)) + +include $(PROJECT_DEP_FILE) + +endif + +.PHONY: clean xclean +clean: + @echo [CLEAN] : $(PROJECT_NAME) + @$(RM) $(CC_OBJTARGETS) $(AS_OBJTARGETS) +ifneq ($(wildcard $(PROJECT_DIR)/$(PROJECT_MAKE)),) + @echo [CLEAN] : $(PROJECT_NAME) + @$(RM) $(PROJECT_BINARY) $(PROJECT_BINARY_LIB) $(PROJECT_DEP_FILE) +endif + +xclean: clean + +.PHONY : welcome_line +welcome_line : + @echo $(MYCUSTOMSPACE) + @echo Building $(PROJECT_BINARY) + @echo $(MYCUSTOMSPACE) -# binary name -APP = wls_test -LDFLAGS += -L../.. -l wls -lpthread -lhugetlbfs +.PHONY : debug release -# all source are stored in SRCS-y -SRCS-y := pool.c testapp.c +debug : all +release : all -CFLAGS += $(WERROR_FLAGS) -I../.. -EXTRA_CFLAGS += -g +$(PROJECT_BINARY): $(DIRLIST) echo_start_build $(GENERATE_DEPS) $(PRE_BUILD) $(CC_OBJTARGETS) $(AS_OBJTARGETS) + @echo "[LD] $@ " + @$(LD) -o $@ $(CC_OBJTARGETS) $(AS_OBJTARGETS) $(LD_FLAGS) -Wl,-L $(BUILDDIR) -include $(RTE_SDK)/mk/rte.extapp.mk +#@echo [APP] $@ +#@$(OBJDUMP) -d $(PROJECT_BINARY) > $(PROJECT_BINARY).asm diff --git a/wls_lib/testapp/pool.c b/wls_lib/testapp/pool.c index 015c03b..ec2b3f9 100644 --- a/wls_lib/testapp/pool.c +++ b/wls_lib/testapp/pool.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/testapp/pool.h b/wls_lib/testapp/pool.h index bb1863e..2318c43 100644 --- a/wls_lib/testapp/pool.h +++ b/wls_lib/testapp/pool.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/testapp/testapp.c b/wls_lib/testapp/testapp.c index e80307c..cb35d94 100644 --- a/wls_lib/testapp/testapp.c +++ b/wls_lib/testapp/testapp.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -38,6 +38,10 @@ #include "ttypes.h" #include "wls_lib.h" #include "pool.h" +#include +#include +#include + #define HANDLE PVOID @@ -55,6 +59,8 @@ #define APP_QUEUE_SIZE 255 /* number of elements each queue of the WLS being registered will have */ #define MAX_MESSAGES 1000 /* per ms */ +U32 nCRC_Fail = 0; +U32 nCRC_Pass = 0; #ifndef TRUE #define TRUE 1 @@ -269,9 +275,6 @@ static int App_MemoryInit(void* h, unsigned long size, U32 BlockSize) /********************************/ -#define FAST_CRC16 1 - -#if (FAST_CRC16) const U8 mb_table_level1[] = { 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, @@ -342,102 +345,6 @@ const U8 mb_table_level2[] = { 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 }; -#if 0 -// big endian CPU - -U16 -crc16(U16 crc, U8 data) -{ - U8 index; - U8 crc_Low = crc & 0xFF; - U8 crc_High = crc >> 8; - - index = (crc_High ^ data) & 0xFF; - crc_High = crc_Low ^ mb_table_level1[ index ]; - crc_Low = mb_table_level2[ index ]; - - return (crc_High << 8) | crc_Low; -} -#else -// little endian CPU -#if 0 -static U16 CRC16_Update(U16 crc, U8 data) -{ - U8 index; - U8 crc_High = crc >> 8; - U8 crc_Low = crc & 0xFF; - - index = crc_Low ^ data; - crc_Low = crc_High ^ mb_table_level1[ index ]; - crc_High = mb_table_level2[ index ]; - - return (crc_High << 8) | crc_Low; -} -#endif -#endif - -#if 0 -/*********************************************** - * CRC16 polynomial : X16 + X15 + X2 + 1 * - * FAST CRC16 routine * - * ---> pData - msg to be protected * - * ---> size - msg size in bytes * - * ---> aCRC - initializer (0xFFFF for 1st page)* - * <--- crc16 * - ***********************************************/ -static U16 CRC16_NoInit(U16 aCRC, U8 *pData, U16 size) -{ - - if (!size) - return aCRC; - else { - U8 index; - U8 crc_High = aCRC >> 8; - U8 crc_Low = aCRC & 0xFF; - - do { - index = crc_Low ^ *pData++; - crc_Low = crc_High ^ mb_table_level1[ index ]; - crc_High = mb_table_level2[ index ]; - } while (--size); - - return (crc_High << 8) | crc_Low; - } -} -#endif - -#else // SLOW (canonic CRC16 calculation) - -/*********************************************** - * CRC16 polynomial : X16 + X15 + X2 + 1 * - * ---> pData - msg to be protected * - * ---> size - msg size in bytes * - * ---> aCRC - initializer (0xFFFF for 1st page)* - * <--- crc16 * - ***********************************************/ -U16 CRC16_NoInit(U16 aCRC, U8 *pData, U16 size) -{ - U8 i, tmp; - - if (!size) - return aCRC; - - do { - aCRC ^= *pData++; - for (i = 0; i < 8; i++) { - tmp = aCRC & 0x01; - aCRC >>= 1; - if (tmp) { - aCRC ^= CRC16_DIVISOR; - } - } - } while (--size); - return aCRC; -} - -#endif // FAST_CRC16 - - #define CRC32_INIT_VAL 0xFFFFFFFF #define CRC32_DIVISOR 0xA0000001 @@ -461,14 +368,6 @@ static U32 ICC_CRC32(U8 *pData, U32 size) return retval; } -#if 0 - -static U16 ICC_CRC16(U8 *pData, U16 size) -{ -#define CRC16_ERROR (0xffff) - return CRC16_NoInit(CRC16_ERROR, pData, size); // use 0xFFFF as first initializer -} -#endif static int app_PutMessageCRC(void* h, unsigned long long pMsg, unsigned int MsgSize, unsigned short MsgTypeID, unsigned short Flags) { @@ -480,19 +379,14 @@ static int app_PutMessageCRC(void* h, unsigned long long pMsg, unsigned int MsgS return 0; } p = (U8 *) pMsgVa; -#if 1 + U32 crc = ICC_CRC32((U8 *) pMsgVa, MsgSize - sizeof (crc)); + // CRC32 p[MsgSize - 4] = (crc >> 0) & 0xff; p[MsgSize - 3] = (crc >> 8) & 0xff; p[MsgSize - 2] = (crc >> 16) & 0xff; p[MsgSize - 1] = (crc >> 24) & 0xff; -#else - U16 crc = ICC_CRC16((U8 *) pMsg, MsgSize - sizeof (crc)); - // CRC16 - p[MsgSize - 2] = (crc >> 0) & 0xff; - p[MsgSize - 1] = (crc >> 8) & 0xff; -#endif return WLS_Put(h, (unsigned long long) pMsg, MsgSize, MsgTypeID, Flags); } @@ -500,20 +394,27 @@ static int app_PutMessageCRC(void* h, unsigned long long pMsg, unsigned int MsgS static unsigned long long app_GetMessageCRC(void* h, unsigned int *MsgSize, unsigned short *MsgTypeID, unsigned short *Flags) { U64 pMsgPa = WLS_Get(h, MsgSize, MsgTypeID, Flags); + + if (pMsgPa) { U64 pMsg = (U64) WlsPaToVa((void*) pMsgPa); if (pMsg) { U32 size = *MsgSize; -#if 1 U32 crc = ICC_CRC32((U8*) pMsg, size); -#else - U16 crc = ICC_CRC16((U8*) pMsg, size); -#endif if (crc != 0) { + nCRC_Fail++; printf("CRC error detected for message %p, size_%lu\n", (void*) pMsg, (long) size); ShowData((U8*) pMsg, size); } + else { + if (nCRC_Pass == 0) { + printf("Example of Msg Size and Content being sent: %d\n", size); + ShowData((U8*) pMsg, size); + } + nCRC_Pass++; + } + } } return pMsgPa; } @@ -521,20 +422,27 @@ static unsigned long long app_GetMessageCRC(void* h, unsigned int *MsgSize, unsi static unsigned long long app_WGetMessageCRC(void* h, unsigned int *MsgSize, unsigned short *MsgTypeID, unsigned short *Flags) { U64 pMsgPa = WLS_WGet(h, MsgSize, MsgTypeID, Flags); + + if (pMsgPa) { U64 pMsg = (U64) WlsPaToVa((void*) pMsgPa); if (pMsg) { U32 size = *MsgSize; -#if 1 U32 crc = ICC_CRC32((U8*) pMsg, size); -#else - U16 crc = ICC_CRC16((U8*) pMsg, size); -#endif if (crc != 0) { + nCRC_Fail++; printf("CRC error detected for message %p, size_%lu\n", (void*) pMsg, (long) size); ShowData((U8*) pMsg, size); } + else { + if (nCRC_Pass == 0) { + printf("Example of Msg Size and Content being sent: %d\n", size); + ShowData((U8*) pMsg, size); + } + nCRC_Pass++; + } + } } return pMsgPa; } @@ -686,144 +594,6 @@ static void app_SanityTestTransmitter(HANDLE hWls) } } -#if 0 -/** - ******************************************************************************* - * - * @fn app_ScatterGatherTransmitter - * @brief transmitter of default test case (15/16). - * - * @param[h] hWls - app thread WLS handle - * @return void - * - * @description - * The routine is used in test case 0 (non-blocking sanity unit test) - * The transmitter does allocate multiple blocks of the same size from the ICC - * service. Then it fills each block with incremental counter and transfers - * to other application specified by parameter TxID. - * - * @references - * MS-111070-SP - * - * @ingroup icc_service_unit_test - * - ******************************************************************************/ -static void app_ScatterGatherTransmitter(HANDLE hWls) -{ - U8 *pMsg; - unsigned n = app_AllocMultiple(hWls, AppContext.TxMessages, AppContext.TxMessageSizes, AppContext.MsgPerMs + 2); - unsigned i, cnt = 0, flags = 0; - U8 *p, *pOriginMsg = (U8 *)App_Alloc(hWls, AppContext.MaxMsgSize); - unsigned TotalSize = 0; - - unsigned fn = n; - unsigned k = 0; - unsigned alloc = n; - - if (!pOriginMsg) { - printf("No memory for App_Alloc()\n"); - return; - } - - flags = rand() & 0xff; - - for(i = 0; i < AppContext.MaxMsgSize; i++) - pOriginMsg[i] = (flags + i) & 0xff; - - // scatter original message among several blocks - for(i = 0; i < n; i++) - { - U32 size = (rand() % (AppContext.MaxMsgSize / n)); - - if (size < AppContext.MinMsgSize) - size = AppContext.MinMsgSize; - - TotalSize += size; - AppContext.TxMessageSizes[i] = size; - //printf("size%d=%lu\n", i, size); - } - - // adjust size of the last block - if (TotalSize < AppContext.MaxMsgSize) - { - AppContext.TxMessageSizes[n - 1] += AppContext.MaxMsgSize - TotalSize; - } - else if (TotalSize > AppContext.MaxMsgSize) - { - printf("error: size of the scatted blocks exceeding size of the original message\n"); - } - - p = pOriginMsg; - for(i = 0; i < n; i++) - { - // copy data into the scattered blocks - pMsg = AppContext.TxMessages[i]; - memcpy(pMsg, p, AppContext.TxMessageSizes[i]); - p += AppContext.TxMessageSizes[i]; - } - - // transmit original message first - if (AppContext.wls_put(hWls, (U64)WlsVaToPa(pOriginMsg), AppContext.MaxMsgSize, AppContext.TxID, 0) != 0) - { - printf("could not send the message_%p\n", pOriginMsg); - if (App_Free(hWls, pOriginMsg) != 0) - printf("could not release the message_%p\n", pOriginMsg); - } - else - { - AppContext.nTxOctets += AppContext.MaxMsgSize; - AppContext.nTxMsgs += 1; - } - - if(pOriginMsg){ - if (App_Free(hWls, pOriginMsg) != 0) - printf("could not release the message_%p\n", pMsg); - } - else - printf("pOriginMsg is NULL \n"); - - // transmit scattered messages following their creation order - while (n--) - { - pMsg = AppContext.TxMessages[cnt]; - if (!cnt) - flags = WLS_SG_FIRST; - else if (n == 0) - flags = WLS_SG_LAST; - else - flags = WLS_SG_NEXT; - - if (AppContext.wls_put(hWls, (U64)WlsVaToPa(pMsg), AppContext.TxMessageSizes[cnt], AppContext.TxID, flags) != 0) - { - printf("could not send the message_%p\n", pMsg); - if (App_Free(hWls, pMsg) != 0) - printf("could not release the message_%p\n", pMsg); - } - else - k++; - - AppContext.nTxOctets += AppContext.TxMessageSizes[cnt]; - AppContext.nTxMsgs += 1; - cnt++; - } - if(alloc != k) - printf("inorrect sent %d alloc %d \n", k, alloc); - - cnt = 0; - while (fn--) - { - pMsg = AppContext.TxMessages[cnt++]; - if(pMsg){ - if (App_Free(hWls, pMsg) != 0) - printf("could not release the message_%p\n", pMsg); - } - else - printf("pMsg is NULL [%d]\n", cnt); - } - if(cnt != k) - printf("inorrect free sent %d free %d \n", k, cnt); -} -#endif /** ******************************************************************************* @@ -903,105 +673,6 @@ static void app_SanityTestReceiver(HANDLE hWls) } } -#if 0 -/** - ******************************************************************************* - * - * @fn app_ScatterGatherReceiver - * @brief scatter gather test receiver - * - * @param[h] hWls - app thread WLS handle - * @return void - * - * @description - * The routine takes received messages and checks the sanity incremental - * counter to confirm the order. In case the counter does not correspond to - * expected counter (misordered message or incorrect message) an error is - * printed to STDOUT. - * - * @references - * MS-111070-SP - * - * @ingroup icc_service_unit_test - * - ******************************************************************************/ -static void app_ScatterGatherReceiver(HANDLE hWls) -{ - (void)hWls; - U32 MsgSize; - U8 *pMsg; - U8 *pMsgPa; - U8 *pMsgVa; - U32 size; - U8 err = 0; - unsigned short MsgTypeID; - unsigned short Flags; - - // handle RX receiver - while ((pMsgPa = (U8*) AppContext.wls_get(AppContext.hWls, &MsgSize, &MsgTypeID, &Flags)) != NULL) - { - pMsgVa = (U8 *)WlsPaToVa(pMsgPa); - - pMsg = pMsgVa; - - AppContext.nRxOcters += MsgSize; - AppContext.nRxMsgs += 1; - - if (!AppContext.pLastRx) - { - AppContext.pLastRx = pMsg; - AppContext.LastRxSize = MsgSize; - } - else // compare with received and release both - { - U32 i; - if (AppContext.LastRxSize != MsgSize) - printf("received wrong size, unsync? try to re-run app both clusters\n"); - - size = MsgSize; - if (size > AppContext.LastRxSize) - size = AppContext.LastRxSize; - - for(i = 0; i < size; i++) - { - if (pMsg[i] != AppContext.pLastRx[i]) - { - // error content doesn't match - err = TRUE; - break; - } - } - - if (err) - { - printf("content verification failed, scatter-gather test FAIL\n"); - // terminate - AppContext.Receive = NULL; - AppContext.Transmit = NULL; - App_Free(AppContext.hWls, pMsg); - App_Free(AppContext.hWls, AppContext.pLastRx); - return; - } - - App_Free(AppContext.hWls, pMsg); - App_Free(AppContext.hWls, AppContext.pLastRx); - AppContext.pLastRx = NULL; - } - - } -} - - - -static U32 app_GetTime(void) -{ - struct timeval tv; - U32 time_ms = 0; - if (gettimeofday(&tv, NULL) == 0) - time_ms = tv.tv_sec * 1000 + tv.tv_usec / 1000; - return time_ms; -} -#endif /****************************************************************************** * * @@ -1415,12 +1086,18 @@ int main(int argc, char* argv[]) { int retval = 0; APP_PARAMS params; + uint64_t nWlsMacMemorySize = DEFAULT_TEST_MEMORY_SIZE, nWlsPhyMemorySize = 0; + uint32_t nLoop = 30000; + uint32_t nNumBlks = 0; signal(SIGINT, App_SigExitCallback); memset(&AppContext, 0, sizeof (AppContext)); memset(¶ms, 0, sizeof (params)); + nCRC_Fail = 0; + nCRC_Pass = 0; + int ret = rte_eal_init(argc, argv); if (ret < 0) rte_exit(EXIT_FAILURE, "Error with EAL initialization\n"); @@ -1433,7 +1110,7 @@ int main(int argc, char* argv[]) AppContext.InitQueueSize = APP_QUEUE_SIZE; - AppContext.hWls = WLS_Open(params.wls_dev_name, AppContext.master, DEFAULT_TEST_MEMORY_SIZE); + AppContext.hWls = WLS_Open(params.wls_dev_name, !AppContext.master, &nWlsMacMemorySize, &nWlsPhyMemorySize); if (!AppContext.hWls) { printf("could not register WLS client\n"); @@ -1442,6 +1119,7 @@ int main(int argc, char* argv[]) printf("WLS has been registered\n"); } + WLS_SetMode(AppContext.hWls, AppContext.master); AppContext.shm_memory = WLS_Alloc(AppContext.hWls, DEFAULT_TEST_MEMORY_SIZE); if (AppContext.shm_memory == NULL) { @@ -1462,8 +1140,20 @@ int main(int argc, char* argv[]) } + ret = WLS_Ready(AppContext.hWls); + if (ret) { + printf("wls not ready\n"); + return -1; + } + + nNumBlks = WLS_Check(AppContext.hWls); + printf("There are %d blocks in queue from WLS_Check\n", nNumBlks); + + nNumBlks = WLS_NumBlocks(AppContext.hWls); + printf("There are %d blocks in queue from WLS_NumBlocks\n", nNumBlks); + // APPLICATION MAIN LOOP - while (!AppContext.ExitStatus && (AppContext.Receive || AppContext.Transmit)) { + while (!AppContext.ExitStatus && (AppContext.Receive || AppContext.Transmit) && nLoop) { if (AppContext.Receive) AppContext.Receive(AppContext.hWls); @@ -1477,10 +1167,17 @@ int main(int argc, char* argv[]) AppContext.Transmit(AppContext.hWls); app_UpdateStatistics(); + nLoop--; } app_ReleaseAllocatedBuffers(); - printf("deregistering WLS (TxTotal_%llu, RxTotal_%llu)\n", (long long) AppContext.nTxMsgs, (long long) AppContext.nRxMsgs); + printf("deregistering WLS (TxTotal_%lld, RxTotal_%lld)\n", (long long) AppContext.nTxMsgs, (long long) AppContext.nRxMsgs); + if (params.crc) + { + printf("Number of CRC Pass %d\n", nCRC_Pass); + printf("Number of CRC Fail %d\n", nCRC_Fail); + printf("Total Message sent: %d\n", (nCRC_Pass + nCRC_Fail)); + } WLS_Free(AppContext.hWls, AppContext.shm_memory); WLS_Close(AppContext.hWls); return retval; diff --git a/wls_lib/testapp/wls_test.sh b/wls_lib/testapp/wls_test.sh index 79f154f..4a7bc86 100755 --- a/wls_lib/testapp/wls_test.sh +++ b/wls_lib/testapp/wls_test.sh @@ -1,7 +1,7 @@ #!/bin/bash ############################################################################### # -# Copyright (c) 2019 Intel. +# Copyright (c) 2021 Intel. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -19,10 +19,10 @@ COREMASK=2 SECONDARY=1 -FPREFIX="wls" -DPDK_WLS=0 +FPREFIX="wls_test" +WLS_TEST_HELP=0 -while getopts ":mpa:w:" opt; do +while getopts ":mhpa:w:" opt; do case ${opt} in m ) SECONDARY=0 @@ -42,41 +42,29 @@ while getopts ":mpa:w:" opt; do echo "Invalid option: $OPTARG requires dev wls path" exit 1 ;; - p ) - DPDK_WLS=1 + h ) + echo "invoking help" + WLS_TEST_HELP=1 ;; esac done wlsTestBinary="wls_test" -if [ $DPDK_WLS -eq 1 ]; then +if [ $WLS_TEST_HELP -eq 0 ]; then if [ $SECONDARY -eq 0 ]; then - wlsTestBinary="build/wls_test -c $COREMASK -n 4 " + wlsTestBinary="wls_test -c $COREMASK -n 4 " wlsTestBinary+="--file-prefix=$FPREFIX --socket-mem=3072 --" else - wlsTestBinary="build/wls_test -c $COREMASK -n 4 " + wlsTestBinary="wls_test -c $COREMASK -n 4 " wlsTestBinary+="--proc-type=secondary --file-prefix=$FPREFIX --" fi +else + wlsTestBinary+=" --" fi ulimit -c unlimited -export RTE_WLS=$PWD/.. - -MACHINE_TYPE=`uname -m` - -if [ ${MACHINE_TYPE} == 'x86_64' ]; then - export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RTE_WLS - - grep Huge /proc/meminfo - - ulimit -c unlimited - echo 1 > /proc/sys/kernel/core_uses_pid - sysctl -w kernel.sched_rt_runtime_us=-1 - for c in $(ls -d /sys/devices/system/cpu/cpu[0-9]*); do echo performance >$c/cpufreq/scaling_governor; done - sysctl -w kernel.shmmax=2147483648 - sysctl -w kernel.shmall=2147483648 -fi +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$PWD/.. wlsCmd="./${wlsTestBinary} $*" echo "Running... ${wlsCmd}" diff --git a/wls_lib/ttypes.h b/wls_lib/ttypes.h index 4130efc..d4e1b84 100644 --- a/wls_lib/ttypes.h +++ b/wls_lib/ttypes.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/wls_lib/wls.h b/wls_lib/wls.h index 0237aba..4f5d531 100644 --- a/wls_lib/wls.h +++ b/wls_lib/wls.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -45,7 +45,8 @@ #ifdef _DEBUG_ #define WLS_DEBUG(format, args...) \ -do { \ +do \ +{ \ printk(KERN_INFO "wls debug: " format,##args); \ }while(0) #else /*_DEBUG_*/ @@ -99,7 +100,17 @@ enum { }; -#define WLS_US_CLIENTS_MAX 64 +#define WLS_RUP512B(x) (((x)+511)&(~511)) +#define WLS_RUP256B(x) (((x)+255)&(~255)) +#define WLS_RUP128B(x) (((x)+127)&(~127)) +#define WLS_RUP64B(x) (((x)+63)&(~63)) +#define WLS_RUP32B(x) (((x)+31)&(~31)) +#define WLS_RUP16B(x) (((x)+15)&(~15)) +#define WLS_RUP8B(x) (((x)+7)&(~7)) +#define WLS_RUP4B(x) (((x)+3)&(~3)) +#define WLS_RUP2B(x) (((x)+1)&(~1)) + +#define WLS_US_CLIENTS_MAX 4 #define CACHE_LINE_SIZE 64 /**< Cache line size. */ #define CACHE_LINE_MASK (CACHE_LINE_SIZE-1) /**< Cache line mask. */ @@ -126,23 +137,20 @@ enum { typedef struct hugepage_tabl_s { - union { - void *pageVa; - uint64_t padding_pageVa; - }; + uint64_t pageVa; uint64_t pagePa; }hugepage_tabl_t; #define DMA_MAP_MAX_BLOCK_SIZE 64*1024 -#define MAX_N_HUGE_PAGES 512 -#define UL_FREE_BLOCK_QUEUE_SIZE 384 +#define MAX_N_HUGE_PAGES 32 +#define UL_FREE_BLOCK_QUEUE_SIZE 1200 -#define WLS_GET_QUEUE_N_ELEMENTS 384 -#define WLS_PUT_QUEUE_N_ELEMENTS 384 +#define WLS_GET_QUEUE_N_ELEMENTS 1024 +#define WLS_PUT_QUEUE_N_ELEMENTS 1024 #define WLS_DEV_SHM_NAME_LEN RTE_MEMZONE_NAMESIZE -#define FIFO_LEN 384 +#define FIFO_LEN 1024 typedef struct wls_wait_req_s { uint64_t wls_us_kernel_va; @@ -211,7 +219,7 @@ typedef struct wls_us_ctx_s // dst userspace context address (local user sapce va) volatile uint64_t dst_pa; - uint32_t alloc_size; + uint32_t nHugePage; wls_us_priv_t wls_us_private; uint32_t mode; uint32_t secmode; @@ -239,6 +247,8 @@ typedef struct wls_drv_ctx_s wls_us_ctx_t p_wls_us_ctx[WLS_US_CLIENTS_MAX]; wls_us_ctx_t p_wls_us_pa_ctx[WLS_US_CLIENTS_MAX]; uint32_t nWlsClients; + uint32_t nMacBufferSize; + uint32_t nPhyBufferSize; pthread_mutex_t mng_mutex; }wls_drv_ctx_t; @@ -278,12 +288,7 @@ typedef struct wls_wake_up_req_s { }wls_wake_up_req_t; -#define SYS_CPU_CLOCK (2300000000L) -#define CLOCK_PER_MS (SYS_CPU_CLOCK/1000) -#define CLOCK_PER_US (SYS_CPU_CLOCK/1000000) - -static inline uint64_t -wls_rdtsc(void) +static inline uint64_t wls_rdtsc(void) { union { uint64_t tsc_64; @@ -299,17 +304,5 @@ wls_rdtsc(void) return tsc.tsc_64; } -static inline uint64_t rdtsc_ticks_diff(unsigned long curr, unsigned long prev) -{ - if (curr >= prev) - return (unsigned long)(curr - prev); - else - return (unsigned long)(0xFFFFFFFFFFFFFFFF - prev + curr); -} - -void wls_show_data(void* ptr, unsigned int size); -void *wls_get_sh_ctx(void); -void *wls_get_sh_ctx_pa(void); - #endif /* __WLS_H__*/ diff --git a/wls_lib/wls_lib.h b/wls_lib/wls_lib.h index e38ea43..7b781d1 100644 --- a/wls_lib/wls_lib.h +++ b/wls_lib/wls_lib.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,6 +23,8 @@ extern "C" { #endif +#include + /** WLS driver client operates as slave in terms of management of shared memory */ #define WLS_SLAVE_CLIENT 0 /** WLS driver client operates as master in terms of management of shared memory */ @@ -53,7 +55,9 @@ extern "C" { /** @ingroup wls_mod * * @param[in] ifacename - pointer to string with device driver name (/dev/wls) - * @param[in] modef - mode of operation (Master or Slave) + * @param[in] mode - mode of operation (Master or Slave) + * @param[in] nWlsMacMemorySize - Pointer with size of Memory blocks managed by MAC + * @param[in] nWlsPhyMemorySize - Pointer with size of Memory blocks managed by L1 (SRS Channel Estimates) * * @return pointer to WLS handle * @@ -64,8 +68,9 @@ extern "C" { * **/ //------------------------------------------------------------------------------------------- -void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWlsMemorySize); +void* WLS_Open(const char *ifacename, unsigned int mode, uint64_t *nWlsMacMemorySize, uint64_t *nWlsPhyMemorySize); +uint32_t WLS_SetMode(void* h, unsigned int mode); //------------------------------------------------------------------------------------------- /** @ingroup wls_mod * @@ -81,7 +86,7 @@ void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWls * **/ //------------------------------------------------------------------------------------------- -void* WLS_Open_Dual(const char *ifacename, unsigned int mode, unsigned long long nWlsMemorySize, void** handle1); +void* WLS_Open_Dual(const char *ifacename, unsigned int mode, uint64_t *nWlsMacMemorySize, uint64_t *nWlsPhyMemorySize, void** handle1); //------------------------------------------------------------------------------------------- /** @ingroup wls_mod @@ -155,7 +160,7 @@ int WLS_Ready1(void* h); * **/ //------------------------------------------------------------------------------------------- -void* WLS_Alloc(void* h, unsigned int size); +void* WLS_Alloc(void* h, uint64_t size); //------------------------------------------------------------------------------------------- /** @ingroup wls_mod diff --git a/wls_lib/wls_lib_dpdk.c b/wls_lib/wls_lib_dpdk.c index dcabfb8..5574801 100644 --- a/wls_lib/wls_lib_dpdk.c +++ b/wls_lib/wls_lib_dpdk.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2021 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -108,9 +108,7 @@ static pthread_mutex_t wls_get_lock1; static wls_us_ctx_t* wls_us_ctx = NULL; static wls_us_ctx_t* wls_us_ctx1 = NULL; -static const struct rte_memzone *hp_memzone = NULL; static long hugePageSize = WLS_HUGE_DEF_PAGE_SIZE; -static uint64_t gWlsMemorySize = 0; static inline int wls_check_ctx(void *h) { @@ -166,29 +164,34 @@ static int wls_initialize(const char *ifacename, uint64_t nWlsMemorySize) { int ret; pthread_mutexattr_t attr; - - uint64_t nSize = nWlsMemorySize + sizeof(wls_drv_ctx_t); - uint8_t *pMemZone; - const struct rte_memzone *mng_ctx_memzone; + uint64_t nSize = nWlsMemorySize + WLS_RUP512B(sizeof(wls_drv_ctx_t)); + struct rte_memzone *mng_memzone; wls_drv_ctx_t *mng_ctx; - mng_ctx_memzone = rte_memzone_reserve_aligned(ifacename, nSize, rte_socket_id(), get_hugepagesz_flag(hugePageSize), hugePageSize); - if (mng_ctx_memzone == NULL) { + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + { + PLIB_ERR("Only DPDK primary process can perform initialization \n"); + return -1; + } + + // Get memory from 1GB huge page and align by 4 Cache Lines + mng_memzone = (struct rte_memzone *)rte_memzone_reserve_aligned(ifacename, nSize, rte_socket_id(), get_hugepagesz_flag(hugePageSize), hugePageSize); + if (mng_memzone == NULL) { PLIB_ERR("Cannot reserve memory zone[%s]: %s\n", ifacename, rte_strerror(rte_errno)); return -1; } - pMemZone = ((uint8_t *)mng_ctx_memzone->addr) + nWlsMemorySize; - memset(pMemZone, 0, sizeof(wls_drv_ctx_t)); - mng_ctx = (wls_drv_ctx_t *)pMemZone; + mng_ctx = (wls_drv_ctx_t *)(mng_memzone->addr); + memset(mng_ctx, 0, sizeof(wls_drv_ctx_t)); pthread_mutexattr_init(&attr); pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED); if (ret = pthread_mutex_init(&mng_ctx->mng_mutex, &attr)) { - PLIB_ERR("Failed to initialize mng_mutex %d\n", ret); pthread_mutexattr_destroy(&attr); + PLIB_ERR("Failed to initialize mng_mutex %d\n", ret); return ret; } + pthread_mutexattr_destroy(&attr); PLIB_DEBUG("Run wls_initialized\n"); return 0; @@ -462,12 +465,13 @@ static int wls_process_wait1(void* h) } -void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWlsMemorySize) +void *WLS_Open(const char *ifacename, unsigned int mode, uint64_t *nWlsMacMemorySize, uint64_t *nWlsPhyMemorySize) { wls_us_ctx_t* pWls_us = NULL; + wls_drv_ctx_t *pWlsDrvCtx; int i, len; char temp[WLS_DEV_SHM_NAME_LEN] = {0}; - uint8_t *pMemZone; + static const struct rte_memzone *mng_memzone; gethugepagesizes(&hugePageSize, 1); @@ -477,22 +481,41 @@ void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWls strncpy(temp, ifacename, WLS_DEV_SHM_NAME_LEN - 1); PLIB_INFO("Open %s (DPDK memzone)\n", temp); - static const struct rte_memzone *mng_memzone; - mng_memzone = rte_memzone_lookup(temp); - if ((mng_memzone == NULL)&&(RTE_PROC_PRIMARY==rte_eal_process_type())) { - wls_initialize(temp, nWlsMemorySize); - } - - mng_memzone = rte_memzone_lookup(temp); - if (mng_memzone == NULL) { + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(temp); + if (mng_memzone == NULL) + { + if (mode == WLS_SLAVE_CLIENT) + { + wls_initialize(temp, *nWlsMacMemorySize+*nWlsPhyMemorySize); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(temp); + if (mng_memzone == NULL) + { PLIB_ERR("Cannot initialize wls shared memory: %s\n", temp); return NULL; } + } + else + { + PLIB_ERR("Cannot locate memory zone: %s. Is the Primary Process running?\n", temp); + return NULL; + } + } - pMemZone = ((uint8_t *)mng_memzone->addr) + nWlsMemorySize; + pWlsDrvCtx = (wls_drv_ctx_t *)(mng_memzone->addr); + PLIB_INFO("WLS_Open %p\n", pWlsDrvCtx); + if (mode == WLS_SLAVE_CLIENT) + { + pWlsDrvCtx->nMacBufferSize = *nWlsMacMemorySize; + pWlsDrvCtx->nPhyBufferSize = *nWlsPhyMemorySize; + } + else + { + *nWlsMacMemorySize = pWlsDrvCtx->nMacBufferSize; + *nWlsPhyMemorySize = pWlsDrvCtx->nPhyBufferSize; + } - PLIB_INFO("WLS_Open %p\n", pMemZone); - if ((pWls_us = wls_create_us_ctx((wls_drv_ctx_t *)pMemZone)) == NULL) { + if ((pWls_us = wls_create_us_ctx(pWlsDrvCtx)) == NULL) + { PLIB_ERR("WLS_Open failed to create context\n"); return NULL; } @@ -502,7 +525,6 @@ void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWls pWls_us->padding_wls_us_user_space_va = 0LL; pWls_us->wls_us_user_space_va = pWls_us; pWls_us->wls_us_ctx_size = sizeof (*pWls_us); - gWlsMemorySize = nWlsMemorySize; wls_mutex_init(&wls_put_lock); wls_mutex_init(&wls_get_lock); @@ -519,13 +541,14 @@ void* WLS_Open(const char *ifacename, unsigned int mode, unsigned long long nWls return wls_us_ctx; } -void* WLS_Open_Dual(const char *ifacename, unsigned int mode, unsigned long long nWlsMemorySize, void** handle1) +void *WLS_Open_Dual(const char *ifacename, unsigned int mode, uint64_t *nWlsMacMemorySize, uint64_t *nWlsPhyMemorySize, void** handle1) { wls_us_ctx_t* pWls_us = NULL; wls_us_ctx_t* pWls_us1 = NULL; + wls_drv_ctx_t *pWlsDrvCtx; int i, len; char temp[WLS_DEV_SHM_NAME_LEN] = {0}; - uint8_t *pMemZone; + static const struct rte_memzone *mng_memzone; gethugepagesizes(&hugePageSize, 1); @@ -535,22 +558,34 @@ void* WLS_Open_Dual(const char *ifacename, unsigned int mode, unsigned long long strncpy(temp, ifacename, WLS_DEV_SHM_NAME_LEN - 1); PLIB_INFO("Open %s (DPDK memzone)\n", temp); - static const struct rte_memzone *mng_memzone; - mng_memzone = rte_memzone_lookup(temp); - if ((mng_memzone == NULL)&&(RTE_PROC_PRIMARY==rte_eal_process_type())) { - wls_initialize(temp, nWlsMemorySize); - } - - mng_memzone = rte_memzone_lookup(temp); - if (mng_memzone == NULL) { + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(temp); + if (mng_memzone == NULL) + { + if (mode == WLS_SLAVE_CLIENT) + { + wls_initialize(temp, *nWlsMacMemorySize+*nWlsPhyMemorySize); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(temp); + if (mng_memzone == NULL) + { PLIB_ERR("Cannot initialize wls shared memory: %s\n", temp); return NULL; } + } + else + { + PLIB_ERR("Cannot locate memory zone: %s. Is the Primary Process running?\n", temp); + return NULL; + } + } + + pWlsDrvCtx = (wls_drv_ctx_t *)(mng_memzone->addr); + *nWlsMacMemorySize = pWlsDrvCtx->nMacBufferSize; + *nWlsPhyMemorySize = pWlsDrvCtx->nPhyBufferSize; + PLIB_INFO("nWlsMemorySize is %lu\n", *nWlsMacMemorySize+*nWlsPhyMemorySize); + PLIB_INFO("WLS_Open Dual 1 %p\n", pWlsDrvCtx); - pMemZone = ((uint8_t *)mng_memzone->addr) + nWlsMemorySize; - PLIB_INFO("nWlsMemorySize is %llu\n", nWlsMemorySize); - PLIB_INFO("WLS_Open Dual 1 %p\n", pMemZone); - if ((pWls_us = wls_create_us_ctx((wls_drv_ctx_t *)pMemZone)) == NULL) { + if ((pWls_us = wls_create_us_ctx(pWlsDrvCtx)) == NULL) + { PLIB_ERR("WLS_Open Dual 1 failed to create context\n"); return NULL; } @@ -561,7 +596,6 @@ void* WLS_Open_Dual(const char *ifacename, unsigned int mode, unsigned long long pWls_us->padding_wls_us_user_space_va = 0LL; pWls_us->wls_us_user_space_va = pWls_us; pWls_us->wls_us_ctx_size = sizeof (*pWls_us); - gWlsMemorySize = nWlsMemorySize; wls_mutex_init(&wls_put_lock); wls_mutex_init(&wls_get_lock); @@ -579,32 +613,31 @@ void* WLS_Open_Dual(const char *ifacename, unsigned int mode, unsigned long long } // Create second context to support the second wls shared memory interface - if ((pWls_us1 = wls_create_us_ctx((wls_drv_ctx_t *)pMemZone)) == NULL) { + if ((pWls_us1 = wls_create_us_ctx(pWlsDrvCtx)) == NULL) + { PLIB_ERR("WLS_Open Dual failed to create context 1\n"); return NULL; } else { PLIB_DEBUG("Local: pWls_us1 %p\n", pWls_us1); + pWls_us1->padding_wls_us_user_space_va = 0LL; pWls_us1->wls_us_user_space_va = pWls_us1; pWls_us1->wls_us_ctx_size = sizeof (*pWls_us1); - gWlsMemorySize = nWlsMemorySize; wls_mutex_init(&wls_put_lock1); wls_mutex_init(&wls_get_lock1); pWls_us1->mode = mode; pWls_us1->secmode = WLS_SEC_NA; - PLIB_INFO("Mode %d Secmode %d\n", pWls_us1->mode, pWls_us1->secmode); + PLIB_INFO("Mode %d SecMode %d \n", pWls_us1->mode, pWls_us1->secmode); PLIB_INFO("WLS shared management memzone 2: %s\n", temp); strncpy(pWls_us1->wls_dev_name, temp, WLS_DEV_SHM_NAME_LEN - 1); wls_us_ctx1 = pWls_us1; // Now the second context is for the L2-FT_fapi PLIB_INFO("pWLs_us1 is %p\n", wls_us_ctx1); - } - return wls_us_ctx1; // returning second context preserves the L2 legacy code } @@ -643,9 +676,9 @@ int WLS_Ready1(void* h) int WLS_Close(void* h) { wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h; - int ret = 0; - uint8_t *pMemZone; wls_drv_ctx_t *pDrv_ctx; + struct rte_memzone *mng_memzone; + int ret = 0; if (!wls_us_ctx) { PLIB_ERR("Library was not opened\n"); @@ -655,16 +688,13 @@ int WLS_Close(void* h) if (wls_check_ctx(h)) return -1; - static const struct rte_memzone *mng_memzone; - mng_memzone = rte_memzone_lookup(pWls_us->wls_dev_name); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(pWls_us->wls_dev_name); if (mng_memzone == NULL) { PLIB_ERR("Cannot find mng memzone: %s %s\n", pWls_us->wls_dev_name, rte_strerror(rte_errno)); return -1; } - - pMemZone = ((uint8_t *)mng_memzone->addr) + gWlsMemorySize; - pDrv_ctx = (wls_drv_ctx_t *)pMemZone; + pDrv_ctx = (wls_drv_ctx_t *)(mng_memzone->addr); PLIB_INFO("WLS_Close\n"); if ((ret = wls_destroy_us_ctx(pWls_us, pDrv_ctx)) < 0) { @@ -677,7 +707,9 @@ int WLS_Close(void* h) wls_us_ctx = NULL; + printf("WLS_Close: nWlsClients[%d]\n", pDrv_ctx->nWlsClients); if (0 == pDrv_ctx->nWlsClients) { + printf("WLS_Close: Freeing Allocated MemZone\n"); wls_mutex_destroy(&pDrv_ctx->mng_mutex); rte_memzone_free(mng_memzone); } @@ -687,9 +719,9 @@ int WLS_Close(void* h) int WLS_Close1(void* h) { wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h; - int ret = 0; - uint8_t *pMemZone; wls_drv_ctx_t *pDrv_ctx; + struct rte_memzone *mng_memzone; + int ret = 0; if (!wls_us_ctx1) { PLIB_ERR("Library was not opened\n"); @@ -699,16 +731,13 @@ int WLS_Close1(void* h) if (wls_check_ctx1(h)) return -1; - static const struct rte_memzone *mng_memzone; - mng_memzone = rte_memzone_lookup(pWls_us->wls_dev_name); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(pWls_us->wls_dev_name); if (mng_memzone == NULL) { PLIB_ERR("Cannot find mng memzone: %s %s\n", pWls_us->wls_dev_name, rte_strerror(rte_errno)); return -1; } - - pMemZone = ((uint8_t *)mng_memzone->addr) + gWlsMemorySize; - pDrv_ctx = (wls_drv_ctx_t *)pMemZone; + pDrv_ctx = (wls_drv_ctx_t *)(mng_memzone->addr); PLIB_INFO("WLS_Close1\n"); if ((ret = wls_destroy_us_ctx1(pWls_us, pDrv_ctx)) < 0) { @@ -721,74 +750,77 @@ int WLS_Close1(void* h) wls_us_ctx1 = NULL; + printf("WLS_Close1: nWlsClients[%d]\n", pDrv_ctx->nWlsClients); if (0 == pDrv_ctx->nWlsClients) { + printf("WLS_Close1: Freeing Allocated MemZone\n"); wls_mutex_destroy(&pDrv_ctx->mng_mutex); rte_memzone_free(mng_memzone); } return 0; } -void* WLS_Alloc(void* h, unsigned int size) +uint32_t WLS_SetMode(void* h, unsigned int mode) { wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h; - static const struct rte_memzone *mng_memzone; - long nHugePage; - void *pvirtAddr = NULL; - int count; - - if ((NULL != hp_memzone)&&(pWls_us->dualMode != WLS_DUAL_MODE)) { - PLIB_ERR("Memory zone already reserved\n"); - return hp_memzone->addr; + pWls_us->mode = mode; + return 0; } +void* WLS_Alloc(void* h, uint64_t size) +{ + wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h; + wls_drv_ctx_t *pDrv_ctx; hugepage_tabl_t* pHugePageTlb = &pWls_us->hugepageTbl[0]; - hugepage_tabl_t* pHugePageTlb1 = &pWls_us->hugepageTbl[1]; - hugepage_tabl_t* pHugePageTlb2 = &pWls_us->hugepageTbl[2]; - - PLIB_INFO("hugePageSize on the system is %ld\n", hugePageSize); - - /* calculate total number of hugepages */ - nHugePage = DIV_ROUND_OFFSET(size, hugePageSize); + void *pvirtAddr = NULL; + struct rte_memzone *mng_memzone; + uint32_t nHugePage; + uint64_t HugePageMask, alloc_base, alloc_end; - if (nHugePage >= MAX_N_HUGE_PAGES) { - PLIB_INFO("not enough hugepages: need %ld system has %d\n", nHugePage, MAX_N_HUGE_PAGES); - return NULL; - } + // TODOINFO null/value check was removed. Check if it works properly. + PLIB_INFO("hugePageSize on the system is %ld 0x%08lx\n", hugePageSize, hugePageSize); - mng_memzone = rte_memzone_lookup(pWls_us->wls_dev_name); - if (mng_memzone == NULL) { - PLIB_ERR("Cannot initialize wls shared memory: %s\n", pWls_us->wls_dev_name); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(pWls_us->wls_dev_name); + if (mng_memzone == NULL) + { + PLIB_ERR("Cannot find mng memzone: %s %s\n", + pWls_us->wls_dev_name, rte_strerror(rte_errno)); return NULL; } - hp_memzone = (struct rte_memzone *)mng_memzone; - pvirtAddr = (void *)hp_memzone->addr; + pDrv_ctx = mng_memzone->addr; - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - memset(pvirtAddr, 0, sizeof (wls_drv_ctx_t)); - } + pvirtAddr = (void *)((uint8_t *)pDrv_ctx + WLS_RUP512B(sizeof(wls_drv_ctx_t))); + HugePageMask = ((unsigned long) hugePageSize - 1); + alloc_base = (uint64_t) pvirtAddr & ~HugePageMask; + alloc_end = (uint64_t) pvirtAddr + (size - WLS_RUP512B(sizeof(wls_drv_ctx_t))); - for (count = 0; count < nHugePage; count++) { + nHugePage = 0; + while(1) + { /*Increment virtual address to next hugepage to create table*/ - pHugePageTlb[count].pageVa = ((unsigned char*) pvirtAddr + \ - (count * hugePageSize)); - /*Creating dummy page fault in process for each page - inorder to get pagemap*/ - *(unsigned char*) pHugePageTlb[count].pageVa = 1; - - if (wls_VirtToIova((uint64_t*) pHugePageTlb[count].pageVa, - &pHugePageTlb[count].pagePa) == -1) { + pHugePageTlb[nHugePage].pageVa = (alloc_base + (nHugePage * hugePageSize)); + + if (pHugePageTlb[nHugePage].pageVa > alloc_end) + break; + + /* Creating dummy page fault in process for each page inorder to get pagemap */ + (*(unsigned char*) pHugePageTlb[nHugePage].pageVa) = 1; + + if (wls_VirtToIova((uint64_t*) pHugePageTlb[nHugePage].pageVa, &pHugePageTlb[nHugePage].pagePa) == -1) + { PLIB_ERR("Virtual to physical conversion failed\n"); return NULL; } + + nHugePage++; } PLIB_DEBUG("count is %d, pHugePageTlb->pageVa is %p pHugePageTlb1->pageVa is %p pHugePageTlb2->pageVa is %p\n",count, pHugePageTlb->pageVa, pHugePageTlb1->pageVa, pHugePageTlb2->pageVa); - PLIB_INFO("WLS_Alloc [%d] bytes\n", size); + PLIB_INFO("WLS_Alloc Size Requested [%ld] bytes HugePageSize [0x%08lx] nHugePagesMapped[%d]\n", size, hugePageSize, nHugePage); pWls_us->HugePageSize = (uint32_t) hugePageSize; pWls_us->alloc_buffer = pvirtAddr; - pWls_us->alloc_size = (uint32_t) (nHugePage * hugePageSize); + pWls_us->nHugePage = nHugePage; if ((pWls_us->mode == WLS_MASTER_CLIENT)||(pWls_us->secmode == WLS_SEC_MASTER)) { wls_us_ctx_t *pWls_usRem = (wls_us_ctx_t*) pWls_us->dst_user_va; @@ -804,11 +836,11 @@ void* WLS_Alloc(void* h, unsigned int size) int WLS_Free(void* h, PVOID pMsg) { - static const struct rte_memzone *mng_memzone; wls_us_ctx_t* pWls_us = (wls_us_ctx_t*) h; wls_drv_ctx_t *pDrv_ctx; + struct rte_memzone *mng_memzone; - mng_memzone = rte_memzone_lookup(pWls_us->wls_dev_name); + mng_memzone = (struct rte_memzone *)rte_memzone_lookup(pWls_us->wls_dev_name); if (mng_memzone == NULL) { PLIB_ERR("Cannot find mng memzone: %s %s\n", pWls_us->wls_dev_name, rte_strerror(rte_errno)); @@ -828,8 +860,7 @@ int WLS_Free(void* h, PVOID pMsg) } PLIB_DEBUG("WLS_Free %s\n", shm_name); - if ( (1 == pDrv_ctx->nWlsClients) && hp_memzone) - hp_memzone = NULL; + return 0; } @@ -1143,7 +1174,7 @@ unsigned long long WLS_VA2PA(void* h, PVOID pMsg) return (uint64_t) ret; } - alloc_base = (unsigned long) pWls_us->alloc_buffer; + alloc_base = (uint64_t) pWls_us->alloc_buffer & ~HugePageMask; pHugePageTlb = &pWls_us->hugepageTbl[0]; @@ -1154,7 +1185,16 @@ unsigned long long WLS_VA2PA(void* h, PVOID pMsg) PLIB_DEBUG("WLS_VA2PA %lx base %llx off %llx count %u\n", (unsigned long) pMsg, (uint64_t) hugePageBase, (uint64_t) hugePageOffet, count); + if (count < MAX_N_HUGE_PAGES) + { + ret = pHugePageTlb[count].pagePa + hugePageOffet; + } + else + { + PLIB_ERR("WLS_VA2PA: Out of range [%p]\n", pMsg); + return 0; + } //printf(" WLS_VA2PA: %p -> %p HugePageSize[%d] HugePageMask[%p] count[%d] pagePa[%p] hugePageBase[%p] alloc_buffer[%p] hugePageOffet[%lld]\n", // pMsg, (void*)ret, pWls_us->HugePageSize, (void*)HugePageMask, count, (void*)pHugePageTlb[count].pagePa, (void*)hugePageBase, pWls_us->alloc_buffer, hugePageOffet); @@ -1170,7 +1210,7 @@ void* WLS_PA2VA(void* h, unsigned long long pMsg) hugepage_tabl_t* pHugePageTlb; uint64_t hugePageBase; uint64_t hugePageOffet; - unsigned int count; + unsigned int nHugePage; int i; uint64_t HugePageMask = ((uint64_t) pWls_us->HugePageSize - 1); @@ -1184,12 +1224,12 @@ void* WLS_PA2VA(void* h, unsigned long long pMsg) hugePageBase = (uint64_t) pMsg & ~HugePageMask; hugePageOffet = (uint64_t) pMsg & HugePageMask; - count = pWls_us->alloc_size / pWls_us->HugePageSize; + nHugePage = pWls_us->nHugePage; - PLIB_DEBUG("WLS_PA2VA %llx base %llx off %llx count %d\n", (uint64_t) pMsg, - (uint64_t) hugePageBase, (uint64_t) hugePageOffet, count); + PLIB_DEBUG("WLS_PA2VA %llx base %llx off %llx nHugePage %d\n", (uint64_t) pMsg, + (uint64_t) hugePageBase, (uint64_t) hugePageOffet, nHugePage); - for (i = 0; i < count; i++) { + for (i = 0; i < nHugePage; i++) { if (pHugePageTlb[i].pagePa == hugePageBase) { ret = (unsigned long) pHugePageTlb[i].pageVa; ret += hugePageOffet; @@ -1197,8 +1237,9 @@ void* WLS_PA2VA(void* h, unsigned long long pMsg) } } - //printf(" WLS_VA2PA: %p -> %p HugePageSize[%d] HugePageMask[%p] count[%d] pagePa[%p] hugePageBase[%p] alloc_buffer[%p] hugePageOffet[%lld]\n", - // (void*)pMsg, (void*)ret, pWls_us->HugePageSize, (void*)HugePageMask, count, (void*)pHugePageTlb[count].pagePa, (void*)hugePageBase, pWls_us->alloc_buffer, hugePageOffet); + //printf(" WLS_VA2PA: %p -> %p HugePageSize[%d] HugePageMask[%p] nHugePage[%d] pagePa[%p] hugePageBase[%p] alloc_buffer[%p] hugePageOffet[%lld]\n", + // (void*)pMsg, (void*)ret, pWls_us->HugePageSize, (void*)HugePageMask, nHugePage, (void*)pHugePageTlb[nHugePage].pagePa, (void*)hugePageBase, pWls_us->alloc_buffer, hugePageOffet); + PLIB_ERR("WLS_PA2VA: Out of range [%p]\n", (void*)pMsg); return (void*) (ret); } -- 2.16.6

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