o-du/phy
Intel O-RAN/X-RAN Generated Doxygen Documentation
xran_pkt.h
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1 /******************************************************************************
2 *
3 * Copyright (c) 2019 Intel.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *******************************************************************************/
18 
26 /* ORAN-WG4.CUS.0-v01.00 O-RAN Fronthaul Working Group
27  Control, User and Synchronization Plane Specification
28 */
29 
30 /*
31  * Layer common to data and control packets
32  */
33 
34 #ifndef _XRAN_PKT_H_
35 #define _XRAN_PKT_H_
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 #include <rte_common.h>
42 #include <rte_ether.h>
43 #include <rte_byteorder.h>
44 
56 #define ECPRI_MAX_PAYLOAD_SIZE 65535
58 /* XRAN spec: For this encapsulation, either the eCPRI Ethertype or the IEEE 1914.3 Ethertype shall be use */
59 #define XRAN_ETHER_TYPE 0xAEFE
61 #define XRAN_ECPRI_VER 0x0001
62 #define XRAN_PAYLOAD_VER 0x0001
64 #define VLAN_ID 0
65 #define VLAN_PCP 7
75 enum ecpri_msg_type
76 {
77  ECPRI_IQ_DATA = 0x00,
78  ECPRI_BIT_SEQUENCE = 0x01, /* msg type is not supported */
81  /* Below msg types are not supported */
88 };
89 
98 {
99  uint8_t seq_id:8;
100  uint8_t sub_seq_id:7;
101  uint8_t e_bit:1;
102 } __rte_packed;
103 
104 
114 {
115  uint8_t ecpri_concat:1;
116  uint8_t ecpri_resv:3;
117  uint8_t ecpri_ver:4;
118  uint8_t ecpri_mesg_type;
119  uint16_t ecpri_payl_size;
120 } __rte_packed;
121 
131 {
133  rte_be16_t ecpri_xtc_id;
135 } __rte_packed;
136 
137 
147 {
151 };
152 
163 {
164  /* Octet 9 */
165  uint8_t filter_id:4;
170  uint8_t payl_ver:3;
173  uint8_t data_direction:1;
175  /* Octet 10 */
176  uint8_t frame_id:8;
178  /* Octet 11 */
179  /* Octet 12 */
180  union {
181  uint16_t value;
182  struct {
183  uint16_t symb_id:6;
185  uint16_t slot_id:6;
189  uint16_t subframe_id:4;
190  };
191  }sf_slot_sym;
192 
193 } __rte_packed;
194 
207 {
208  uint8_t ud_iq_width:4;
213  uint8_t ud_comp_meth:4;
223 } __rte_packed;
224 
234 {
235  struct ether_hdr eth_hdr;
236  struct xran_ecpri_hdr ecpri_hdr;
237 } __rte_packed;
238 
239 #ifdef __cplusplus
240 }
241 #endif
242 
243 #endif
uint8_t data_direction
Definition: xran_pkt.h:173
uint8_t ecpri_concat
Definition: xran_pkt.h:115
xran_pkt_dir
Definition: xran_pkt.h:146
uint8_t seq_id
Definition: xran_pkt.h:99
struct xran_cp_radioapp_common_header cmnhdr
Definition: xran_pkt_cp.h:214
uint8_t ecpri_ver
Definition: xran_pkt.h:117
uint8_t ecpri_resv
Definition: xran_pkt.h:116
uint8_t ud_iq_width
Definition: xran_pkt.h:208
uint8_t e_bit
Definition: xran_pkt.h:101
uint8_t sub_seq_id
Definition: xran_pkt.h:100
uint8_t ud_comp_meth
Definition: xran_pkt.h:213
struct ecpri_seq_id __rte_packed
rte_be16_t ecpri_xtc_id
Definition: xran_pkt.h:133
uint16_t subframe_id
Definition: xran_pkt.h:189
uint8_t ecpri_mesg_type
Definition: xran_pkt.h:118
uint16_t ecpri_payl_size
Definition: xran_pkt.h:119