20 #ifndef XRAN_LIB_WRAP_HPP 21 #define XRAN_LIB_WRAP_HPP 38 #define XRAN_UT_CFG_FILENAME "conf.json" 40 #define XRAN_UT_KEY_GLOBALCFG "GLOBAL" 41 #define XRAN_UT_KEY_GLOBALCFG_IO "io_cfg" 42 #define XRAN_UT_KEY_GLOBALCFG_EAXCID "eAxCId_cfg" 43 #define XRAN_UT_KEY_GLOBALCFG_PRACH "prach_cfg" 44 #define XRAN_UT_KEY_GLOBALCFG_RU "ru_cfg" 45 #define XRAN_UT_KEY_GLOBALCFG_SLOT "slotcfg_" 47 #define MAX_NUM_OF_XRAN_CTX (2) 49 #define SW_FPGA_TOTAL_BUFFER_LEN (4*1024*1024*1024) 50 #define SW_FPGA_SEGMENT_BUFFER_LEN (1*1024*1024*1024) 51 #define SW_FPGA_FH_TOTAL_BUFFER_LEN (1*1024*1024*1024) 52 #define FPGA_TO_SW_PRACH_RX_BUFFER_LEN (8192) 54 #define MAX_ANT_CARRIER_SUPPORTED (XRAN_MAX_SECTOR_NR*XRAN_MAX_ANTENNA_NR) 62 void sym_ota_cb(
struct rte_timer *tim,
void *arg);
63 void tti_ota_cb(
struct rte_timer *tim,
void *arg);
94 { 25, 52, 79, 106, 133, 160, 216, 270, 0, 0, 0, 0, 0 },
95 { 11, 24, 38, 51, 65, 78, 106, 133, 162, 0, 217, 245, 273 },
96 { 0, 11, 18, 24, 31, 38, 51, 65, 79, 0, 107, 121, 135 }
115 uint8_t
m_du_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x66 };
116 uint8_t
m_ru_mac[6] = { 0x00,0x11, 0x22, 0x33, 0x44, 0x55 };
167 T get_globalcfg(
const std::string &type,
const std::string ¶meter_name)
173 std::vector<T> get_globalcfg_array(
const std::string &type,
const std::string ¶meter_name)
177 std::vector<T> result(array_size);
179 for(
unsigned number = 0; number < array_size; number++)
185 uint16_t get_eaxcid_mask(
int numbit,
int shift)
189 for(
int i=0; i < numbit; i++) {
190 result = result << 1; result +=1;
192 return (result << shift);
199 SWXRANInterfaceTypeEnum eInterfaceType;
207 std::cout <<
"XRAN front haul xran_mm_init" << std::endl;
210 std::cout <<
"Failed at XRAN front haul xran_mm_init" << std::endl;
217 int32_t nSectorNum = 6;
222 std::cout <<
"get sector instance failed " << k <<
" for XRAN nInstanceNum " << nInstanceNum << std::endl;
225 for (i = 0; i < nInstanceNum; i++)
226 std::cout << __func__ <<
" [" << k <<
"]: CC " << i <<
" handle " << m_nInstanceHandle[0][i] << std::endl;
228 std::cout <<
"Sucess xran_mm_init" << std::endl;
231 for(i = 0; i<nSectorNum; i++) {
234 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
236 m_nSW_ToFpga_FTH_TxBufferLen);
238 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
243 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].
bValid = 0;
245 m_sFrontHaulTxBbuIoBufCtrl[j][i][z].
nSegToBeGen = -1;
254 status =
xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
256 std::cout << __LINE__ <<
" Failed at xran_bm_allocate_buffer, status " << status << std::endl;
263 u32dptr = (uint32_t*)(ptr);
264 uint8_t *ptr_temp = (uint8_t *)ptr;
265 memset(u32dptr, 0x0, m_nSW_ToFpga_FTH_TxBufferLen);
274 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
277 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
282 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
286 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
291 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].
bValid = 0;
292 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].
nSegGenerated = -1;
293 m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].
nSegToBeGen = -1;
301 status =
xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
303 std::cout << __LINE__ <<
" Failed at xran_bm_allocate_buffer, status " << status << std::endl;
318 std::cout << __LINE__ <<
"SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
328 for(i = 0; i<nSectorNum; i++) {
331 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
333 m_nSW_ToFpga_FTH_TxBufferLen);
335 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
341 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].
bValid = 0;
343 m_sFrontHaulRxBbuIoBufCtrl[j][i][z].
nSegToBeGen = -1;
351 status =
xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],&ptr, &mb);
353 std::cout << __LINE__ <<
" Failed at xran_bm_allocate_buffer, status " << status << std::endl;
359 u32dptr = (uint32_t*)(ptr);
360 uint8_t *ptr_temp = (uint8_t *)ptr;
361 memset(u32dptr, 0x0, m_nFpgaToSW_FTH_RxBufferLen);
369 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
372 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
377 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
381 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
387 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].
bValid = 0;
388 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].
nSegGenerated = -1;
389 m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].
nSegToBeGen = -1;
397 status =
xran_bm_allocate_buffer(m_nInstanceHandle[0][i],m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
399 std::cout << __LINE__ <<
" Failed at xran_bm_allocate_buffer , status " << status << std::endl;
414 std::cout << __LINE__ <<
"SD Failed at xran_bm_allocate_buffer , status %d\n" << status << std::endl;
424 for(i = 0; i<nSectorNum; i++) {
427 &m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType],
431 std::cout << __LINE__ <<
" Failed at xran_bm_init, status " << status << std::endl;
436 m_sFHPrachRxBbuIoBufCtrl[j][i][z].
bValid = 0;
438 m_sFHPrachRxBbuIoBufCtrl[j][i][z].
nSegToBeGen = -1;
446 status =
xran_bm_allocate_buffer(m_nInstanceHandle[0][i], m_nBufPoolIndex[m_nSectorIndex[i]][eInterfaceType], &ptr, &mb);
448 std::cout << __LINE__ <<
" Failed at xran_bm_allocate_buffer, status " << status << std::endl;
454 u32dptr = (uint32_t*)(ptr);
471 unsigned int tmp_mac[6];
492 if(bbdev_mode ==
"sw")
494 else if(bbdev_mode ==
"hw")
496 else if(bbdev_mode ==
"none")
499 std::cout <<
"Invalid BBDev mode [" << bbdev_mode <<
"], bbdev won't be used." << std::endl;
514 std::sscanf(du_mac_str.c_str(),
"%02x:%02x:%02x:%02x:%02x:%02x",
515 &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],
516 &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);
518 m_du_mac[i] = (uint8_t)tmp_mac[i];
519 std::sscanf(du_mac_str.c_str(),
"%02x:%02x:%02x:%02x:%02x:%02x",
520 &tmp_mac[0], &tmp_mac[1], &tmp_mac[2],
521 &tmp_mac[3], &tmp_mac[4], &tmp_mac[5]);
523 m_ru_mac[i] = (uint8_t)tmp_mac[i];
576 if(tmpstr ==
"FDD") {
579 else if(tmpstr ==
"TDD") {
584 int numcfg = get_globalcfg<int>(slotcfg_key,
"period");
587 for(
int i=0; i< numcfg; i++) {
588 std::stringstream slotcfgname;
589 slotcfgname <<
"slot" << i;
590 std::vector<int> slotcfg = get_globalcfg_array<int>(slotcfg_key, slotcfgname.str());
591 for(
int j=0; j < slotcfg.size(); j++) {
599 std::cout <<
"*** Invalid Duplex type [" << tmpstr <<
"] !!!" << std::endl;
600 std::cout <<
"****** Set it to FDD... " << std::endl;
613 std::cout <<
"*** Exceeds maximum number of carriers supported [" <<
m_xranConf.
nCC <<
"] !!!" << std::endl;
615 std::cout <<
"****** Adjusted to " <<
m_xranConf.
nCC <<
"..." << std::endl;
619 std::cout <<
"*** Exceeds maximum number of antenna supported [" <<
m_xranConf.
neAxc <<
"] !!!" << std::endl;
621 std::cout <<
"****** Adjusted to " <<
m_xranConf.
neAxc <<
"..." << std::endl;
646 else if(tmpstr ==
"B")
649 std::cout <<
"*** Invalid RU Category [" << tmpstr <<
"] !!!" << std::endl;
650 std::cout <<
"****** Set it to Category A... " << std::endl;
682 printf(
"O-DU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
690 printf(
"O-RU MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
698 printf(
"eAxCID - %d:%d:%d:%d (%04x, %04x, %04x, %04x)\n",
713 m_nSectorIndex[i] = i;
716 m_nFpgaToSW_FTH_RxBufferLen = 13168;
717 m_nSW_ToFpga_FTH_TxBufferLen = 13168;
719 if(init_memory() < 0) {
720 std::cout <<
"Fatal Error on Initialization !!!" << std::endl;
721 std::cout <<
"INIT FAILED" << std::endl;
725 std::cout <<
"INIT DONE" << std::endl;
733 m_xranhandle =
nullptr;
734 std::cout <<
"CLOSE DONE" << std::endl;
737 std::cout <<
"ALREADY CLOSED" << std::endl;
750 SWXRANInterfaceTypeEnum eInterfaceType;
751 int32_t cc_id, ant_id, sym_id, tti;
777 p_tx_dl_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_dl);
778 tx_dl_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_dl;
779 if(p_tx_dl_bfw_buffer[i] == NULL)
782 memset(p_tx_dl_bfw_buffer[i],
'D', iq_bfw_buffer_size_dl);
783 tx_dl_bfw_buffer_position[i] = 0;
785 p_tx_ul_bfw_buffer[i] = (int16_t*)malloc(iq_bfw_buffer_size_ul);
786 tx_ul_bfw_buffer_size[i] = (int32_t)iq_bfw_buffer_size_ul;
787 if(p_tx_ul_bfw_buffer[i] == NULL)
790 memset(p_tx_ul_bfw_buffer[i],
'U', iq_bfw_buffer_size_ul);
791 tx_ul_bfw_buffer_position[i] = 0;
796 for(cc_id = 0; cc_id <nSectorNum; cc_id++) {
799 flowId = XRAN_MAX_ANTENNA_NR*cc_id + ant_id;
802 pRbMap = (
struct xran_prb_map *)m_sFrontHaulTxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->
pData;
829 char *dl_bfw_pos = ((
char*)p_tx_dl_bfw_buffer[flowId]) + tx_dl_bfw_buffer_position[flowId];
839 pRbMap->bf_weight.nAntElmTRx = num_antelm;
840 for(idxElm = 0; idxElm < pRbMap->
nPrbElm; idxElm++){
841 p_prbMap = &pRbMap->
prbMap[idxElm];
844 rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (dl_bfw_pos + (iPrb * num_antelm)*4), num_antelm*4);
851 std::cout <<
"DL pRbMap ==NULL" << std::endl;
855 pRbMap = (
struct xran_prb_map *)m_sFrontHaulRxPrbMapBbuIoBufCtrl[tti][cc_id][ant_id].sBufferList.pBuffers->
pData;
882 char *ul_bfw_pos = ((
char*)p_tx_ul_bfw_buffer[flowId]) + tx_ul_bfw_buffer_position[flowId];
892 pRbMap->bf_weight.nAntElmTRx = num_antelm;
893 for (idxElm = 0; idxElm < pRbMap->
nPrbElm; idxElm++){
894 p_prbMap = &pRbMap->
prbMap[idxElm];
897 rte_memcpy(&pRbMap->bf_weight.weight[iPrb][0], (ul_bfw_pos + (iPrb*num_antelm)*4), num_antelm*4);
905 std::cout <<
"UL: pRbMap ==NULL" << std::endl;
920 if(p_tx_dl_bfw_buffer[i]) {
921 free(p_tx_dl_bfw_buffer[i]);
922 p_tx_dl_bfw_buffer[i] == NULL;
925 if(p_tx_ul_bfw_buffer[i]) {
926 free(p_tx_ul_bfw_buffer[i]);
927 p_tx_ul_bfw_buffer[i] == NULL;
937 void *fh_rx_callback,
void *fh_rx_prach_callback)
955 for(i=0; i<nSectorNum; i++) {
958 pFthTxBuffer[i][z][j] = &(m_sFrontHaulTxBbuIoBufCtrl[j][i][z].
sBufferList);
959 pFthTxPrbMapBuffer[i][z][j] = &(m_sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].
sBufferList);
960 pFthRxBuffer[i][z][j] = &(m_sFrontHaulRxBbuIoBufCtrl[j][i][z].
sBufferList);
961 pFthRxPrbMapBuffer[i][z][j] = &(m_sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].
sBufferList);
962 pFthRxRachBuffer[i][z][j] = &(m_sFHPrachRxBbuIoBufCtrl[j][i][z].
sBufferList);
967 if(m_nInstanceHandle[0] != NULL) {
968 for(i = 0; i<nSectorNum; i++) {
970 pFthTxBuffer[i], pFthTxPrbMapBuffer[i],
971 pFthRxBuffer[i], pFthRxPrbMapBuffer[i],
972 (
void (*)(
void *,
xran_status_t))fh_rx_callback, &pFthRxBuffer[i][0]);
975 (
void (*)(
void *,
xran_status_t))fh_rx_prach_callback, &pFthRxRachBuffer[i][0]);
1050 std::vector<int> slotcfg;
1052 numcfg = get_globalcfg<int>(cfgname,
"period");
1054 for(i=0; i < numcfg; i++) {
1055 std::stringstream slotcfgname;
1057 slotcfgname <<
"slot" << i;
1058 std::vector<int> slotcfg = get_globalcfg_array<int>(cfgname, slotcfgname.str());
1060 for(j=0; j < slotcfg.size(); j++)
1068 int get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth,
bool nSub6)
1074 if (nNumerology < 3) {
1076 switch(nBandwidth) {
1077 case PHY_BW_5MHZ:
return(nNumRbsPerSymF1[nNumerology][0]);
1078 case PHY_BW_10MHZ:
return(nNumRbsPerSymF1[nNumerology][1]);
1079 case PHY_BW_15MHZ:
return(nNumRbsPerSymF1[nNumerology][2]);
1080 case PHY_BW_20MHZ:
return(nNumRbsPerSymF1[nNumerology][3]);
1081 case PHY_BW_25MHZ:
return(nNumRbsPerSymF1[nNumerology][4]);
1082 case PHY_BW_30MHZ:
return(nNumRbsPerSymF1[nNumerology][5]);
1083 case PHY_BW_40MHZ:
return(nNumRbsPerSymF1[nNumerology][6]);
1084 case PHY_BW_50MHZ:
return(nNumRbsPerSymF1[nNumerology][7]);
1085 case PHY_BW_60MHZ:
return(nNumRbsPerSymF1[nNumerology][8]);
1086 case PHY_BW_70MHZ:
return(nNumRbsPerSymF1[nNumerology][9]);
1087 case PHY_BW_80MHZ:
return(nNumRbsPerSymF1[nNumerology][10]);
1088 case PHY_BW_90MHZ:
return(nNumRbsPerSymF1[nNumerology][11]);
1089 case PHY_BW_100MHZ:
return(nNumRbsPerSymF1[nNumerology][12]);
1094 if((nNumerology >= 2) && (nNumerology <= 3)) {
1097 switch(nBandwidth) {
1098 case PHY_BW_50MHZ:
return(nNumRbsPerSymF2[nNumerology][0]);
break;
1099 case PHY_BW_100MHZ:
return(nNumRbsPerSymF2[nNumerology][1]);
break;
1100 case PHY_BW_200MHZ:
return(nNumRbsPerSymF2[nNumerology][2]);
break;
1101 case PHY_BW_400MHZ:
return(nNumRbsPerSymF2[nNumerology][3]);
break;
1161 #endif //XRAN_LIB_WRAP_HPP
int physide_ul_full_slot_call_back(void *param)
#define XRAN_MAX_SECTIONS_PER_SYM
#define SW_FPGA_FH_TOTAL_BUFFER_LEN
struct xran_flat_buffer m_sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]
int xran_register_cb_mbuf2ring(xran_ethdi_mbuf_send_fn mbuf_send_cp, xran_ethdi_mbuf_send_fn mbuf_send_up)
uint32_t m_nSW_ToFpga_FTH_TxBufferLen
#define XRAN_N_FE_BUF_LEN
#define XRAN_STATUS_SUCCESS
void tti_ota_cb(struct rte_timer *tim, void *arg)
int16_t * p_tx_dl_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]
int32_t xran_open(void *pHandle, struct xran_fh_config *pConf)
int32_t tx_dl_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]
struct xran_fh_config m_xranConf
#define FPGA_TO_SW_PRACH_RX_BUFFER_LEN
void sym_ota_cb(struct rte_timer *tim, void *arg)
int get_slot_config(const std::string &cfgname, struct xran_frame_config *pCfg)
int32_t xran_init(int argc, char *argv[], struct xran_fh_init *p_xran_fh_init, char *appName, void **pHandle)
#define XRAN_UT_KEY_GLOBALCFG_IO
int32_t xran_mm_init(void *pHandle, uint64_t nMemorySize, uint32_t nMemorySegmentSize)
json read_json_from_file(const std::string &filename)
Read JSON from the given file.
uint16_t mask_bandSectorId
void get_cfg_frame(struct xran_frame_config *pCfg)
uint32_t m_nBufPoolIndex[XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM]
uint8_t nPrachRestrictSet
void update_symbol_index()
size_type size() const noexcept
returns the number of elements
int physide_ul_half_slot_call_back(void *param)
a class to store JSON values
BbuIoBufCtrlStruct m_sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
enum xran_input_byte_order byteOrder
struct xran_fh_config * pXranConf
BbuIoBufCtrlStruct m_sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
int32_t xran_bm_init(void *pHandle, uint32_t *pPoolIndex, uint32_t nNumberOfBuffers, uint32_t nBufferSize)
#define XRAN_MAX_SECTOR_NR
int32_t tx_ul_bfw_buffer_size[MAX_ANT_CARRIER_SUPPORTED]
int iq_bfw_buffer_size_dl
#define XRAN_UT_KEY_GLOBALCFG_RU
struct xran_eaxcid_config eAxCId_conf
int32_t xran_start(void *pHandle)
BbuIoBufCtrlStruct m_sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
#define XRAN_MAX_ANTENNA_NR
#define XRAN_UT_KEY_GLOBALCFG
void get_cfg_ru(struct xran_ru_config *pCfg)
enum xran_if_state xran_get_if_state(void)
void get_cfg_fh(struct xran_fh_config *pCfg)
uint8_t nSymbolType[XRAN_NUM_OF_SYMBOL_PER_SLOT]
int physide_dl_tti_call_back(void *param)
uint32_t nNumberOfElements
std::string m_dpdk_dev_up
uint8_t nPrachZeroCorrConf
uint32_t xran_lib_ota_sym
enum xran_input_i_q_order iqOrder
#define MAX_ANT_CARRIER_SUPPORTED
#define XRAN_UT_CFG_FILENAME
struct xran_io_cfg io_cfg
uint32_t m_nFpgaToSW_FTH_RxBufferLen
uint32_t dpdkBasebandFecMode
uint16_t nPrachRootSeqIdx
int32_t xran_5g_prach_req(void *pHandle, struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag)
struct xran_frame_config frame_conf
struct xran_device_ctx * xran_dev_get_ctx(void)
int32_t xran_close(void *pHandle)
int apply_cpenable(bool flag)
void * m_nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]
struct xran_flat_buffer * pBuffers
const uint16_t nNumRbsPerSymF2[2][4]
struct xranLibWraper::xran_timer_ctx m_timer_ctx[MAX_NUM_OF_XRAN_CTX]
int32_t xran_bm_allocate_buffer(void *pHandle, uint32_t nPoolIndex, void **ppData, void **ppCtrl)
Header file for function to work with 5G NR frame structure and related routines. ...
struct xran_prach_config prach_conf
adjust channel per each RB for iPrb
enum xran_category get_rucategory()
int32_t tx_ul_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]
enum xran_category xranCat
int32_t xran_stop(void *pHandle)
struct xran_slot_config sSlotConfig[XRAN_MAX_TDD_PERIODICITY]
#define MAX_NUM_OF_XRAN_CTX
XRAN layer common functionality for both lls-CU and RU as well as C-plane and U-plane.
BbuIoBufCtrlStruct m_sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
struct xran_ru_config ru_conf
struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT]
#define XRAN_UT_KEY_GLOBALCFG_EAXCID
struct xran_flat_buffer m_sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]
struct rte_mbuf * pData[N_MAX_BUFFER_SEGMENT]
#define XRAN_NUM_OF_SYMBOL_PER_SLOT
BbuIoBufCtrlStruct m_sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
int32_t DynamicSectionEna
char * dpdk_dev[XRAN_VF_MAX]
This file provides public interface to xRAN Front Haul layer implementation as defined in the ORAN-WG...
struct xran_flat_buffer m_sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
int32_t xran_sector_get_instances(void *pHandle, uint16_t nNumInstances, xran_cc_handle_t *pSectorInstanceHandles)
int get_num_rbs(uint32_t nNumerology, uint32_t nBandwidth, bool nSub6)
int Init(struct xran_fh_config *pCfg=nullptr)
struct xran_buffer_list sBufferList
uint32_t xran_lib_ota_sym_idx
#define XRAN_UT_KEY_GLOBALCFG_PRACH
char * dpdkBasebandDevice
struct xran_flat_buffer m_sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT]
struct xran_fh_init m_xranInit
void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up, void *fh_rx_callback, void *fh_rx_prach_callback)
int16_t * p_tx_ul_bfw_buffer[MAX_ANT_CARRIER_SUPPORTED]
struct xran_prb_elm prbMap[XRAN_MAX_PRBS]
const uint16_t nNumRbsPerSymF1[3][13]
void get_cfg_prach(struct xran_prach_config *pCfg)
int(* xran_ethdi_mbuf_send_fn)(struct rte_mbuf *mb, uint16_t ethertype)
uint32_t xran_lib_ota_tti
#define SW_FPGA_SEGMENT_BUFFER_LEN
int32_t m_nSectorIndex[XRAN_MAX_SECTOR_NR]
struct xran_flat_buffer m_sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
int32_t xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id)
std::string m_dpdk_dev_cp
int32_t tx_dl_bfw_buffer_position[MAX_ANT_CARRIER_SUPPORTED]
int32_t xran_5g_fronthault_config(void *pHandle, struct xran_buffer_list *pSrcBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pSrcCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pDstCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag)
uint8_t nPrachSubcSpacing
int iq_bfw_buffer_size_ul
uint32_t nElementLenInBytes