From: lal.harshita Date: Thu, 9 Feb 2023 08:04:04 +0000 (+0530) Subject: [Epic-ID: ODUHIGH-488][Task-ID: ODUHIGH-492] WG8 Alignment [DL Broadcast Allocation] X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?p=o-du%2Fl2.git;a=commitdiff_plain;h=5f7ef2d1a1d4b8167b5fbdefd96b576d520d9678 [Epic-ID: ODUHIGH-488][Task-ID: ODUHIGH-492] WG8 Alignment [DL Broadcast Allocation] Signed-off-by: lal.harshita Change-Id: I25facae3897c06a1548a9d936eceb4dc9b2815e8 Signed-off-by: lal.harshita --- diff --git a/src/5gnrmac/lwr_mac_fsm.c b/src/5gnrmac/lwr_mac_fsm.c index cb8c02e56..a7c087b94 100644 --- a/src/5gnrmac/lwr_mac_fsm.c +++ b/src/5gnrmac/lwr_mac_fsm.c @@ -2446,9 +2446,9 @@ uint8_t fillSsbPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacCellCfg *macCellCfg, dlTtiReqPdu->pdu.ssb_pdu.physCellId = macCellCfg->phyCellId; dlTtiReqPdu->pdu.ssb_pdu.betaPss = macCellCfg->ssbCfg.betaPss; dlTtiReqPdu->pdu.ssb_pdu.ssbBlockIndex = currDlSlot->dlInfo.brdcstAlloc.ssbInfo[ssbIdxCount].ssbIdx; - dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset; + dlTtiReqPdu->pdu.ssb_pdu.ssbSubCarrierOffset = macCellCfg->ssbCfg.ssbScOffset;; /* ssbOfPdufstA to be filled in ssbCfg */ - dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA; + dlTtiReqPdu->pdu.ssb_pdu.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;; dlTtiReqPdu->pdu.ssb_pdu.bchPayloadFlag = macCellCfg->ssbCfg.bchPayloadFlag; /* Bit manipulation for SFN */ setMibPdu(macCellCfg->ssbCfg.mibPdu, &mibPayload, sfn); @@ -2460,7 +2460,6 @@ uint8_t fillSsbPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, MacCellCfg *macCellCfg, dlTtiReqPdu->pdu.ssb_pdu.preCodingAndBeamforming. \ pmi_bfi[0].beamIdx[0].beamidx = macCellCfg->ssbCfg.beamId[0]; dlTtiReqPdu->pduSize = sizeof(fapi_dl_ssb_pdu_t); /* Size of SSB PDU */ - return ROK; } return RFAILED; @@ -2522,7 +2521,7 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces; dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.powerValue; + dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size @@ -2532,8 +2531,8 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) * Spec 38.214 Sec 5.1.2.2.2 */ coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize; - rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb; - rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb; + rbStart = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb; + rbLen = sib1PdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coreset0Size - rbStart)) { @@ -2662,7 +2661,7 @@ void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc) dlDciPtr->pc_and_bform.digBfInterfaces = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.digBfInterfaces; dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].pmIdx; dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = dlPageAlloc->pagePdcchCfg.dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerValue; + dlDciPtr->beta_pdcch_1_0 = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.beta_pdcch_1_0; dlDciPtr->powerControlOffsetSS = dlPageAlloc->pagePdcchCfg.dci.txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size @@ -2672,8 +2671,8 @@ void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc) * Spec 38.214 Sec 5.1.2.2.2 */ coreset0Size = dlPageAlloc->pagePdcchCfg.coresetCfg.coreSetSize; - rbStart = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb; - rbLen = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb; + rbStart = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.startPrb; + rbLen = dlPageAlloc->pagePdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coreset0Size - rbStart)) { @@ -2815,7 +2814,7 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) uint8_t modNCodSchemeSize = 5; uint8_t tbScalingSize = 2; uint8_t reservedSize = 16; - + dlDciPtr->rnti = rarPdcchInfo->dci.rnti; dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId; dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti; @@ -2826,7 +2825,7 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces; dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.powerValue; + dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size @@ -2838,8 +2837,8 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) /* TODO: Fill values of coreset0Size, rbStart and rbLen */ coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize; - rbStart = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb; - rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb; + rbStart = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb; + rbLen = rarPdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coreset0Size - rbStart)) { @@ -2968,7 +2967,7 @@ void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\ dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces; dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.powerValue; + dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size @@ -2978,8 +2977,8 @@ void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\ * Spec 38.214 Sec 5.1.2.2.2 */ coresetSize = pdcchInfo->coresetCfg.coreSetSize; - rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.startPrb; - rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.freqAlloc.numPrb; + rbStart = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.startPrb; + rbLen = pdcchInfo->dci.pdschCfg->pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coresetSize - rbStart)) { @@ -3216,11 +3215,11 @@ void fillPdschPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu dlTtiReqPdu->pdu.pdsch_pdu.dmrsPorts = pdschInfo->dmrs.dmrsPorts; dlTtiReqPdu->pdu.pdsch_pdu.resourceAlloc = pdschInfo->pdschFreqAlloc.resourceAllocType; /* since we are using type-1, hence rbBitmap excluded */ - dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.freqAlloc.startPrb; - dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.freqAlloc.numPrb; + dlTtiReqPdu->pdu.pdsch_pdu.rbStart = pdschInfo->pdschFreqAlloc.startPrb; + dlTtiReqPdu->pdu.pdsch_pdu.rbSize = pdschInfo->pdschFreqAlloc.numPrb; dlTtiReqPdu->pdu.pdsch_pdu.vrbToPrbMapping = pdschInfo->pdschFreqAlloc.vrbPrbMapping; - dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.timeAlloc.startSymb; - dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.timeAlloc.numSymb; + dlTtiReqPdu->pdu.pdsch_pdu.startSymbIndex = pdschInfo->pdschTimeAlloc.startSymb; + dlTtiReqPdu->pdu.pdsch_pdu.nrOfSymbols = pdschInfo->pdschTimeAlloc.numSymb; dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.numPrgs = pdschInfo->beamPdschInfo.numPrgs; dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.prgSize = pdschInfo->beamPdschInfo.prgSize; dlTtiReqPdu->pdu.pdsch_pdu.preCodingAndBeamforming.digBfInterfaces = pdschInfo->beamPdschInfo.digBfInterfaces; @@ -3269,7 +3268,7 @@ uint8_t calcDlTtiReqPduCount(MacDlSlot *dlSlot) if(dlSlot->dlInfo.isBroadcastPres) { - if(dlSlot->dlInfo.brdcstAlloc.ssbTrans) + if(dlSlot->dlInfo.brdcstAlloc.ssbTransmissionMode) { for(idx = 0; idx < dlSlot->dlInfo.brdcstAlloc.ssbIdxSupported; idx++) { @@ -3277,7 +3276,7 @@ uint8_t calcDlTtiReqPduCount(MacDlSlot *dlSlot) count++; } } - if(dlSlot->dlInfo.brdcstAlloc.sib1Trans) + if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode) { /* PDCCH and PDSCH PDU is filled */ count += 2; @@ -3335,7 +3334,7 @@ uint8_t calcTxDataReqPduCount(MacDlSlot *dlSlot) { uint8_t idx = 0, count = 0, ueIdx=0; - if(dlSlot->dlInfo.isBroadcastPres && dlSlot->dlInfo.brdcstAlloc.sib1Trans) + if(dlSlot->dlInfo.isBroadcastPres && dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode) { count++; } @@ -3382,7 +3381,7 @@ uint8_t calcTxDataReqPduCount(MacDlSlot *dlSlot) * * ********************************************************************/ uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCellCfg *macCellCfg, - PdschCfg pdschCfg) + PdschCfg *pdschCfg) { uint32_t payloadSize = 0; uint8_t *sib1Payload = NULLP; @@ -3395,7 +3394,7 @@ uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCel pduDesc[pduIndex].num_tlvs = 1; /* fill the TLV */ - payloadSize = pdschCfg.codeword[0].tbSize; + payloadSize = pdschCfg->codeword[0].tbSize; pduDesc[pduIndex].tlvs[0].tl.tag = ((payloadSize & 0xff0000) >> 8) | FAPI_TX_DATA_PTR_TO_PAYLOAD_64; pduDesc[pduIndex].tlvs[0].tl.length = (payloadSize & 0x0000ffff); LWR_MAC_ALLOC(sib1Payload, payloadSize); @@ -3709,7 +3708,7 @@ uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo) { if(currDlSlot->dlInfo.isBroadcastPres) { - if(currDlSlot->dlInfo.brdcstAlloc.ssbTrans) + if(currDlSlot->dlInfo.brdcstAlloc.ssbTransmissionMode) { if(dlTtiReq->pdus != NULLP) { @@ -3725,12 +3724,13 @@ uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo) DU_LOG("\033[0m"); } - if(currDlSlot->dlInfo.brdcstAlloc.sib1Trans) + if(currDlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode) { /* Filling SIB1 param */ if(numPduEncoded != nPdu) { - rntiType = SI_RNTI_TYPE; + if(currDlSlot->dlInfo.brdcstAlloc.crnti == SI_RNTI) + rntiType = SI_RNTI_TYPE; /* PDCCH PDU */ fillPdcchPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded], @@ -3739,7 +3739,7 @@ uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo) /* PDSCH PDU */ fillPdschPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded], - &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg, + currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg.dci.pdschCfg, currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp, pduIndex); dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex; @@ -3985,10 +3985,10 @@ uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_ txDataReq->sfn = currTimingInfo.sfn; txDataReq->slot = currTimingInfo.slot; - if(dlSlot->dlInfo.brdcstAlloc.sib1Trans) + if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode) { fillSib1TxDataReq(txDataReq->pdu_desc, pduIndex, &macCb.macCell[cellIdx]->macCellCfg, \ - dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg); + dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg.dci.pdschCfg); pduIndex++; txDataReq->num_pdus++; } @@ -4496,7 +4496,7 @@ void fillUlDciPdu(fapi_dl_dci_t *ulDciPtr, DciInfo *schDciInfo) ulDciPtr->pc_and_bform.digBfInterfaces = schDciInfo->dciInfo.beamPdcchInfo.digBfInterfaces; ulDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx; ulDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = schDciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0]; - ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.powerValue; + ulDciPtr->beta_pdcch_1_0 = schDciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0; ulDciPtr->powerControlOffsetSS = schDciInfo->dciInfo.txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size diff --git a/src/5gnrmac/mac_slot_ind.c b/src/5gnrmac/mac_slot_ind.c index fdd2669e3..d18588da1 100644 --- a/src/5gnrmac/mac_slot_ind.c +++ b/src/5gnrmac/mac_slot_ind.c @@ -69,8 +69,6 @@ uint8_t MacProcDlAlloc(Pst *pst, DlSchedInfo *dlSchedInfo) dlSlot[dlSchedInfo->schSlotValue.broadcastTime.slot]; currDlSlot->dlInfo.isBroadcastPres = true; memcpy(&currDlSlot->dlInfo.brdcstAlloc, &dlSchedInfo->brdcstAlloc, sizeof(DlBrdcstAlloc)); - currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg.dci.pdschCfg = \ - &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdschCfg; } for(ueIdx=0; ueIdxsib1PdcchCfg); - PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); - BwpCfg *bwp = &(sib1SchCfg->bwp); + pdcch = &(sib1SchCfg->sib1PdcchCfg); + bwp = &(sib1SchCfg->bwp); coreset0Idx = sib1SchCfg->coresetZeroIndex; searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex; @@ -690,11 +692,17 @@ void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.beta_pdcch_1_0= 0; pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; /* Storing pdschCfg pointer here. Required to access pdsch config while fillig up pdcch pdu */ - pdcch->dci.pdschCfg = pdsch; + SCH_ALLOC(pdcch->dci.pdschCfg, sizeof(PdschCfg)); + if(pdcch->dci.pdschCfg == NULLP) + { + DU_LOG("\nERROR --> SCH : Memory allocation failed in %s ", __func__); + return RFAILED; + } + pdsch = pdcch->dci.pdschCfg; /* fill the PDSCH PDU */ uint8_t cwCount = 0; @@ -728,13 +736,13 @@ void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB; - pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs, NUM_PDSCH_SYMBOL); + pdsch->pdschFreqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB; + pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs, NUM_PDSCH_SYMBOL); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pdsch->pdschTimeAlloc.rowIndex = 1; /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */ - pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ - pdsch->pdschTimeAlloc.timeAlloc.numSymb = NUM_PDSCH_SYMBOL; + pdsch->pdschTimeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ + pdsch->pdschTimeAlloc.numSymb = NUM_PDSCH_SYMBOL; pdsch->beamPdschInfo.numPrgs = 1; pdsch->beamPdschInfo.prgSize = 1; pdsch->beamPdschInfo.digBfInterfaces = 0; @@ -743,6 +751,7 @@ void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg pdsch->txPdschPower.powerControlOffset = 0; pdsch->txPdschPower.powerControlOffsetSS = 0; + return ROK; } /** @@ -778,11 +787,15 @@ uint8_t SchProcCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, + ret = fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); - + if(ret != ROK) + { + DU_LOG("\nERROR --> SCH : Failed to fill sib1 configuration"); + return RFAILED; + } memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); schProcPagingCfg(cellCb); @@ -934,6 +947,8 @@ void deleteSchCellCb(SchCellCb *cellCb) SCH_FREE(cellCb->cellCfg.plmnInfoList.snssai, cellCb->cellCfg.plmnInfoList.numSliceSupport*sizeof(Snssai*)); } + SCH_FREE(cellCb->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg, sizeof(PdschCfg)); + for(uint16_t idx =0; idxpageCb.pageIndInfoRecord[idx]; @@ -1293,7 +1308,7 @@ uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \ if(ssbOccasion && sib1Occasion) { broadcastPrbStart = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; - broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB + cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1; + broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB + cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb -1; } else if(ssbOccasion) { @@ -1302,8 +1317,8 @@ uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \ } else if(sib1Occasion) { - broadcastPrbStart = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.startPrb; - broadcastPrbEnd = broadcastPrbStart + cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1; + broadcastPrbStart = cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.startPrb; + broadcastPrbEnd = broadcastPrbStart + cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb -1; } /* Iterate through all free PRB blocks */ @@ -1571,7 +1586,7 @@ uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_ { reservedPrbStart = cell->cellCfg.ssbSchCfg.ssbOffsetPointA; reservedPrbEnd = reservedPrbStart + SCH_SSB_NUM_PRB + \ - cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1; + cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb -1; } else if(ssbOccasion) { @@ -1580,8 +1595,8 @@ uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_ } else if(sib1Occasion) { - reservedPrbStart = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.startPrb; - reservedPrbEnd = reservedPrbStart + cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc.numPrb -1; + reservedPrbStart = cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.startPrb; + reservedPrbEnd = reservedPrbStart + cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc.numPrb -1; } else { diff --git a/src/5gnrsch/sch_common.c b/src/5gnrsch/sch_common.c index cfeb92c4e..8e7b588e6 100644 --- a/src/5gnrsch/sch_common.c +++ b/src/5gnrsch/sch_common.c @@ -121,8 +121,8 @@ uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcst { uint8_t dmrsStartSymbol, startSymbol, numSymbol ; DmrsInfo dmrs; - ResAllocType1 freqAlloc; - TimeDomainAlloc timeAlloc; + PdschFreqAlloc freqAlloc; + PdschTimeAlloc timeAlloc; SchDlSlotInfo *schDlSlotInfo = NULLP; if(cell == NULL) @@ -136,10 +136,11 @@ uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcst DU_LOG("\nERROR --> SCH: schBroadcastSsbAlloc() : dlBrdcstAlloc is NULL"); return RFAILED; } - - dmrs = cell->cellCfg.sib1SchCfg.sib1PdschCfg.dmrs; - freqAlloc = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschFreqAlloc.freqAlloc; - timeAlloc = cell->cellCfg.sib1SchCfg.sib1PdschCfg.pdschTimeAlloc.timeAlloc; + + dlBrdcstAlloc->crnti = SI_RNTI; + dmrs = cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->dmrs; + freqAlloc = cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschFreqAlloc; + timeAlloc = cell->cellCfg.sib1SchCfg.sib1PdcchCfg.dci.pdschCfg->pdschTimeAlloc; schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot]; /* Find total symbols used including DMRS */ @@ -167,8 +168,6 @@ uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcst memcpy(&dlBrdcstAlloc->sib1Alloc.bwp, &cell->cellCfg.sib1SchCfg.bwp, sizeof(BwpCfg)); memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(PdcchCfg)); - memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(PdschCfg)); - dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg.dci.pdschCfg = &dlBrdcstAlloc->sib1Alloc.sib1PdschCfg; schDlSlotInfo->sib1Pres = true; return ROK; } @@ -639,7 +638,7 @@ uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueI pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; pdcch->dci.pdschCfg = pdsch; @@ -682,12 +681,12 @@ uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueI pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS; pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; - pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschStartSymbol; - pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschNumSymbols; + pdsch->pdschTimeAlloc.startSymb = pdschStartSymbol; + pdsch->pdschTimeAlloc.numSymb = pdschNumSymbols; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = MAX_NUM_RB; - pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, pdschNumSymbols); + pdsch->pdschFreqAlloc.startPrb = MAX_NUM_RB; + pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, pdschNumSymbols); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ /* Find total symbols occupied including DMRS */ @@ -696,19 +695,19 @@ uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueI * in that case only PDSCH symbols are marked as occupied */ if(dmrsStartSymbol == MAX_SYMB_PER_SLOT) { - startSymbol = pdsch->pdschTimeAlloc.timeAlloc.startSymb; - numSymbol = pdsch->pdschTimeAlloc.timeAlloc.numSymb; + startSymbol = pdsch->pdschTimeAlloc.startSymb; + numSymbol = pdsch->pdschTimeAlloc.numSymb; } /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */ else { startSymbol = dmrsStartSymbol; - numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.timeAlloc.numSymb; + numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.numSymb; } /* Allocate the number of PRBs required for RAR PDSCH */ if((allocatePrbDl(cell, msg4Time, startSymbol, numSymbol,\ - &pdsch->pdschFreqAlloc.freqAlloc.startPrb, pdsch->pdschFreqAlloc.freqAlloc.numPrb)) != ROK) + &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK) { DU_LOG("\nERROR --> SCH : Resource allocation failed for MSG4"); return RFAILED; @@ -837,7 +836,7 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; /* fill the PDSCH PDU */ @@ -875,13 +874,13 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS; pdsch->dmrs.dmrsAddPos = pdschCfg.dmrsDlCfgForPdschMapTypeA.addPos; - pdsch->pdschTimeAlloc.timeAlloc.startSymb = pdschStartSymbol; - pdsch->pdschTimeAlloc.timeAlloc.numSymb = pdschNumSymbols; + pdsch->pdschTimeAlloc.startSymb = pdschStartSymbol; + pdsch->pdschTimeAlloc.numSymb = pdschNumSymbols; pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = startPRB; /*Start PRB will be already known*/ - pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, pdschNumSymbols); + pdsch->pdschFreqAlloc.startPrb = startPRB; /*Start PRB will be already known*/ + pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, ueCb.ueCfg.dlModInfo.mcsIndex, pdschNumSymbols); /* Find total symbols occupied including DMRS */ dmrsStartSymbol = findDmrsStartSymbol(pdsch->dmrs.dlDmrsSymbPos); @@ -889,19 +888,19 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c * in that case only PDSCH symbols are marked as occupied */ if(dmrsStartSymbol == MAX_SYMB_PER_SLOT) { - startSymbol = pdsch->pdschTimeAlloc.timeAlloc.startSymb; - numSymbol = pdsch->pdschTimeAlloc.timeAlloc.numSymb; + startSymbol = pdsch->pdschTimeAlloc.startSymb; + numSymbol = pdsch->pdschTimeAlloc.numSymb; } /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */ else { startSymbol = dmrsStartSymbol; - numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.timeAlloc.numSymb; + numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.numSymb; } /* Allocate the number of PRBs required for DL PDSCH */ if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\ - &pdsch->pdschFreqAlloc.freqAlloc.startPrb, pdsch->pdschFreqAlloc.freqAlloc.numPrb)) != ROK) + &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK) { DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG"); return RFAILED; @@ -2090,13 +2089,13 @@ uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingI pagePdschCfg->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ - pagePdschCfg->pdschFreqAlloc.freqAlloc.startPrb = startPrb; - pagePdschCfg->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, NUM_PDSCH_SYMBOL); + pagePdschCfg->pdschFreqAlloc.startPrb = startPrb; + pagePdschCfg->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, mcs, NUM_PDSCH_SYMBOL); pagePdschCfg->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pagePdschCfg->pdschTimeAlloc.rowIndex = 1; /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */ - pagePdschCfg->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ - pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb = NUM_PDSCH_SYMBOL; + pagePdschCfg->pdschTimeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ + pagePdschCfg->pdschTimeAlloc.numSymb = NUM_PDSCH_SYMBOL; /* Find total symbols occupied including DMRS */ dmrsStartSymbol = findDmrsStartSymbol(pagePdschCfg->dmrs.dlDmrsSymbPos); @@ -2104,19 +2103,19 @@ uint8_t schFillPagePdschCfg(SchCellCb *cell, PdschCfg *pagePdschCfg, SlotTimingI * in that case only PDSCH symbols are marked as occupied */ if(dmrsStartSymbol == MAX_SYMB_PER_SLOT) { - startSymbol = pagePdschCfg->pdschTimeAlloc.timeAlloc.startSymb; - numSymbol = pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb; + startSymbol = pagePdschCfg->pdschTimeAlloc.startSymb; + numSymbol = pagePdschCfg->pdschTimeAlloc.numSymb; } /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */ else { startSymbol = dmrsStartSymbol; - numSymbol = pagePdschCfg->dmrs.nrOfDmrsSymbols + pagePdschCfg->pdschTimeAlloc.timeAlloc.numSymb; + numSymbol = pagePdschCfg->dmrs.nrOfDmrsSymbols + pagePdschCfg->pdschTimeAlloc.numSymb; } /* Allocate the number of PRBs required for DL PDSCH */ if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\ - &pagePdschCfg->pdschFreqAlloc.freqAlloc.startPrb, pagePdschCfg->pdschFreqAlloc.freqAlloc.numPrb)) != ROK) + &pagePdschCfg->pdschFreqAlloc.startPrb, pagePdschCfg->pdschFreqAlloc.numPrb)) != ROK) { DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG"); return RFAILED; diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c index 7694acb7d..7f6ab3225 100644 --- a/src/5gnrsch/sch_rach.c +++ b/src/5gnrsch/sch_rach.c @@ -913,7 +913,7 @@ uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAl pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; pdcch->dci.pdschCfg = pdsch; @@ -949,13 +949,13 @@ uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAl pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschTimeAlloc.rowIndex = k0Index; - pdsch->pdschTimeAlloc.timeAlloc.startSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[k0Index].startSymbol; - pdsch->pdschTimeAlloc.timeAlloc.numSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[k0Index].lengthSymbol; + pdsch->pdschTimeAlloc.startSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[k0Index].startSymbol; + pdsch->pdschTimeAlloc.numSymb = initialBwp->pdschCommon.timeDomRsrcAllocList[k0Index].lengthSymbol; pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = MAX_NUM_RB; - pdsch->pdschFreqAlloc.freqAlloc.numPrb = \ + pdsch->pdschFreqAlloc.startPrb = MAX_NUM_RB; + pdsch->pdschFreqAlloc.numPrb = \ schCalcNumPrb(tbSize, mcs, initialBwp->pdschCommon.timeDomRsrcAllocList[k0Index].lengthSymbol); /* Find total symbols occupied including DMRS */ @@ -964,19 +964,19 @@ uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAl * in that case only PDSCH symbols are marked as occupied */ if(dmrsStartSymbol == MAX_SYMB_PER_SLOT) { - startSymbol = pdsch->pdschTimeAlloc.timeAlloc.startSymb; - numSymbol = pdsch->pdschTimeAlloc.timeAlloc.numSymb; + startSymbol = pdsch->pdschTimeAlloc.startSymb; + numSymbol = pdsch->pdschTimeAlloc.numSymb; } /* If DMRS symbol is found, mark DMRS and PDSCH symbols as occupied */ else { startSymbol = dmrsStartSymbol; - numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.timeAlloc.numSymb; + numSymbol = pdsch->dmrs.nrOfDmrsSymbols + pdsch->pdschTimeAlloc.numSymb; } /* Allocate the number of PRBs required for RAR PDSCH */ if((allocatePrbDl(cell, rarTime, startSymbol, numSymbol,\ - &pdsch->pdschFreqAlloc.freqAlloc.startPrb, pdsch->pdschFreqAlloc.freqAlloc.numPrb)) != ROK) + &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK) { DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for RAR"); return RFAILED; diff --git a/src/5gnrsch/sch_slot_ind.c b/src/5gnrsch/sch_slot_ind.c index b5a345201..3b0bf5d30 100644 --- a/src/5gnrsch/sch_slot_ind.c +++ b/src/5gnrsch/sch_slot_ind.c @@ -633,8 +633,8 @@ uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd) memset(&dlSchedInfo, 0, sizeof(DlSchedInfo)); schCalcSlotValues(*slotInd, &dlSchedInfo.schSlotValue, cell->numSlots); dlBrdcstAlloc = &dlSchedInfo.brdcstAlloc; - dlBrdcstAlloc->ssbTrans = NO_TRANSMISSION; - dlBrdcstAlloc->sib1Trans = NO_TRANSMISSION; + dlBrdcstAlloc->ssbTransmissionMode = NO_TRANSMISSION; + dlBrdcstAlloc->sib1TransmissionMode = NO_TRANSMISSION; memcpy(&cell->slotInfo, slotInd, sizeof(SlotTimingInfo)); dlBrdcstAlloc->ssbIdxSupported = SSB_IDX_SUPPORTED; @@ -647,35 +647,35 @@ uint8_t SchProcSlotInd(Pst *pst, SlotTimingInfo *slotInd) #endif /* Check for SSB occassion */ - dlBrdcstAlloc->ssbTrans = schCheckSsbOcc(cell, dlSchedInfo.schSlotValue.broadcastTime); - if(dlBrdcstAlloc->ssbTrans) + dlBrdcstAlloc->ssbTransmissionMode = schCheckSsbOcc(cell, dlSchedInfo.schSlotValue.broadcastTime); + if(dlBrdcstAlloc->ssbTransmissionMode) { if(schBroadcastSsbAlloc(cell, dlSchedInfo.schSlotValue.broadcastTime, dlBrdcstAlloc) != ROK) { DU_LOG("\nERROR --> SCH : schBroadcastSsbAlloc failed"); - dlBrdcstAlloc->ssbTrans = NO_TRANSMISSION; + dlBrdcstAlloc->ssbTransmissionMode = NO_TRANSMISSION; } else { dlSchedInfo.isBroadcastPres = true; - if((dlBrdcstAlloc->ssbTrans == NEW_TRANSMISSION) && (!cell->firstSsbTransmitted)) + if((dlBrdcstAlloc->ssbTransmissionMode == NEW_TRANSMISSION) && (!cell->firstSsbTransmitted)) cell->firstSsbTransmitted = true; } } /* Check for SIB1 occassion */ - dlBrdcstAlloc->sib1Trans = schCheckSib1Occ(cell, dlSchedInfo.schSlotValue.broadcastTime); - if(dlBrdcstAlloc->sib1Trans) + dlBrdcstAlloc->sib1TransmissionMode = schCheckSib1Occ(cell, dlSchedInfo.schSlotValue.broadcastTime); + if(dlBrdcstAlloc->sib1TransmissionMode) { if(schBroadcastSib1Alloc(cell, dlSchedInfo.schSlotValue.broadcastTime, dlBrdcstAlloc) != ROK) { DU_LOG("\nERROR --> SCH : schBroadcastSib1Alloc failed"); - dlBrdcstAlloc->sib1Trans = NO_TRANSMISSION; + dlBrdcstAlloc->sib1TransmissionMode = NO_TRANSMISSION; } else { dlSchedInfo.isBroadcastPres = true; - if((dlBrdcstAlloc->sib1Trans == NEW_TRANSMISSION) && (!cell->firstSib1Transmitted)) + if((dlBrdcstAlloc->sib1TransmissionMode == NEW_TRANSMISSION) && (!cell->firstSib1Transmitted)) cell->firstSib1Transmitted = true; } } diff --git a/src/5gnrsch/sch_ue_mgr.c b/src/5gnrsch/sch_ue_mgr.c index 0d84ba58a..254d21277 100644 --- a/src/5gnrsch/sch_ue_mgr.c +++ b/src/5gnrsch/sch_ue_mgr.c @@ -1025,7 +1025,7 @@ uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo dciInfo->dciInfo.beamPdcchInfo.digBfInterfaces = 0; dciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx = 0; dciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0] = 0; - dciInfo->dciInfo.txPdcchPower.powerValue = 0; + dciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0 = 0; dciInfo->dciInfo.txPdcchPower.powerControlOffsetSS = 0; dciInfo->dciInfo.pdschCfg = NULL; /* No DL data being sent */ msg3HqProc->tbInfo.txCntr++; @@ -1132,7 +1132,7 @@ uint8_t schFillUlDci(SchUeCb *ueCb, SchPuschInfo *puschInfo, DciInfo *dciInfo, b dciInfo->dciInfo.beamPdcchInfo.digBfInterfaces = 0; dciInfo->dciInfo.beamPdcchInfo.prg[0].pmIdx = 0; dciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0] = 0; - dciInfo->dciInfo.txPdcchPower.powerValue = 0; + dciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0 = 0; dciInfo->dciInfo.txPdcchPower.powerControlOffsetSS = 0; dciInfo->dciInfo.pdschCfg = NULL; /* No DL data being sent */ diff --git a/src/cm/mac_sch_interface.h b/src/cm/mac_sch_interface.h index ef8b485b5..5e977247c 100644 --- a/src/cm/mac_sch_interface.h +++ b/src/cm/mac_sch_interface.h @@ -453,6 +453,8 @@ typedef struct resAllocType1 uint16_t numPrb; }ResAllocType1; +typedef struct resAllocType1 FreqDomainRsrc; + typedef struct { uint32_t ssbPbchPwr; /* SSB block power */ @@ -471,7 +473,7 @@ typedef struct bwpCfg { uint8_t subcarrierSpacing; uint8_t cyclicPrefix; - ResAllocType1 freqAlloc; + FreqDomainRsrc freqAlloc; }BwpCfg; typedef struct prg @@ -517,14 +519,17 @@ typedef struct pdschFreqAlloc { uint8_t resourceAllocType; /* since we are using type-1, rbBitmap excluded */ - ResAllocType1 freqAlloc; + uint8_t rbBitmap[36]; + uint16_t startPrb; + uint16_t numPrb; uint8_t vrbPrbMapping; -} PdschFreqAlloc; +}PdschFreqAlloc; typedef struct pdschTimeAlloc { - uint8_t rowIndex; - TimeDomainAlloc timeAlloc; + uint8_t rowIndex; + uint16_t startSymb; + uint16_t numSymb; } PdschTimeAlloc; typedef struct txPowerPdschInfo @@ -533,6 +538,7 @@ typedef struct txPowerPdschInfo uint8_t powerControlOffsetSS; } TxPowerPdschInfo; +/* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-43 PDSCH Configuration */ typedef struct pdschCfg { uint16_t pduBitmap; @@ -554,6 +560,7 @@ typedef struct pdschCfg /* SIB1 interface structure */ +/* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-35 CORESET Configuration */ typedef struct coresetCfg { uint8_t coreSetSize; @@ -563,8 +570,9 @@ typedef struct coresetCfg uint8_t cceRegMappingType; uint8_t regBundleSize; uint8_t interleaverSize; - uint8_t coreSetType; uint16_t shiftIndex; + uint8_t coreSetType; + uint8_t coresetPoolIndex; uint8_t precoderGranularity; uint8_t cceIndex; uint8_t aggregationLevel; @@ -572,10 +580,11 @@ typedef struct coresetCfg typedef struct txPowerPdcchInfo { - uint8_t powerValue; + uint8_t beta_pdcch_1_0; uint8_t powerControlOffsetSS; -} TxPowerPdcchInfo; +}TxPowerPdcchInfo; +/* Reference -> O-RAN.WG8.AAD.0-v07.00, Table 9-42 DL-DCI Configuration */ typedef struct dlDCI { uint16_t rnti; @@ -586,15 +595,14 @@ typedef struct dlDCI BeamformingInfo beamPdcchInfo; TxPowerPdcchInfo txPdcchPower; PdschCfg *pdschCfg; -} DlDCI; +}DlDCI; typedef struct pdcchCfg { /* coreset-0 configuration */ CoresetCfg coresetCfg; - - uint16_t numDlDci; - DlDCI dci; /* as of now its only one DCI, later it will be numDlCi */ + uint16_t numDlDci; + DlDCI dci; /* as of now its only one DCI, later it will be numDlCi */ } PdcchCfg; /* end of SIB1 PDCCH structures */ @@ -618,7 +626,6 @@ typedef struct uint8_t n0; BwpCfg bwp; PdcchCfg sib1PdcchCfg; - PdschCfg sib1PdschCfg; PageCfg pageCfg; /*Config of Paging*/ }SchSib1Cfg; @@ -644,7 +651,7 @@ typedef struct schRachCfg typedef struct schBwpParams { - ResAllocType1 freqAlloc; + FreqDomainRsrc freqAlloc; uint8_t scs; uint8_t cyclicPrefix; }SchBwpParams; @@ -848,16 +855,15 @@ typedef struct schCellCfgCfm typedef struct ssbInfo { uint8_t ssbIdx; /* SSB Index */ - TimeDomainAlloc tdAlloc; /* Time domain allocation */ - ResAllocType1 fdAlloc; /* Freq domain allocation */ + TimeDomainAlloc tdAlloc; /* Time domain allocation */ + FreqDomainRsrc fdAlloc; /* Freq domain allocation */ }SsbInfo; typedef struct sib1AllocInfo { BwpCfg bwp; PdcchCfg sib1PdcchCfg; - PdschCfg sib1PdschCfg; -} Sib1AllocInfo; +}Sib1AllocInfo; typedef struct prachSchInfo { @@ -870,18 +876,21 @@ typedef struct prachSchInfo /* Interface structure signifying DL broadcast allocation for SSB, SIB1 */ typedef struct dlBrdcstAlloc { + uint16_t crnti; /* SI-RNTI */ /* Ssb transmission is determined as follows: * 0 : No tranamission * 1 : SSB Transmission * 2 : SSB Repetition */ - uint8_t ssbTrans; + uint8_t ssbTransmissionMode; uint8_t ssbIdxSupported; SsbInfo ssbInfo[MAX_SSB_IDX]; + bool systemInfoIndicator; + uint8_t *siContent; /* Sib1 transmission is determined as follows: * 0 : No tranamission * 1 : SIB1 Transmission * 2 : SIB1 Repetition */ - uint8_t sib1Trans; + uint8_t sib1TransmissionMode; Sib1AllocInfo sib1Alloc; }DlBrdcstAlloc; @@ -889,7 +898,7 @@ typedef struct msg3UlGrant { uint8_t freqHopFlag; uint16_t bwpSize; - ResAllocType1 msg3FreqAlloc; + FreqDomainRsrc msg3FreqAlloc; uint8_t k2Index; uint8_t mcs; uint8_t tpc; @@ -971,7 +980,7 @@ typedef struct format0_0 { uint8_t resourceAllocType; /* since we are using type-1, hence rbBitmap excluded */ - ResAllocType1 freqAlloc; + FreqDomainRsrc freqAlloc; TimeDomainAlloc timeAlloc; uint16_t rowIndex; uint8_t mcs; @@ -1020,9 +1029,10 @@ typedef struct dciInfo }DciInfo; +/* Reference -> O-RAN.WG8.AAD.0-v07.00, Section 11.2.4.3.8 DL Scheduling Information */ typedef struct dlSchedInfo { - uint16_t cellId; /* Cell Id */ + uint16_t cellId; /* Cell Id */ SchSlotValue schSlotValue; /* Allocation for broadcast messages */