#define PAGING_SCHED_DELTA 4
+#ifdef NR_DRX
+/* Macros for Drx configuration */
+#define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
+#define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 1
+#define DRX_INACTIVITY_TIMER 2
+#define DRX_HARQ_RTT_TIMER_DL 56
+#define DRX_HARQ_RTT_TIMER_UL 56
+#define DRX_RETRANSMISSION_TIMER_DL 4
+#define DRX_RETRANSMISSION_TIMER_UL 4
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 20
+#define DRX_LONG_CYCLE_START_OFFSET_VAL 8
+#define DRX_SHORT_CYCLE 2
+#define DRX_SHORT_CYCLE_TIMER 2
+#define DRX_SLOT_OFFSET 0
+#endif
+
typedef enum
{
MAC_DU_APP_RSP_NOK,
Snssai **snssai; /* List of supporting snssai*/
}PlmnInfoList;
+#ifdef NR_DRX
+/* The following list of structures is taken from the DRX-Config section of specification 33.331. */
+typedef struct drxOnDurationTimer
+{
+ bool onDurationTimerValInMs;
+ union
+ {
+ uint8_t subMilliSeconds;
+ uint16_t milliSeconds;
+ }onDurationtimerValue;
+}DrxOnDurationTimer;
+
+typedef struct drxLongCycleStartOffset
+{
+ uint16_t drxLongCycleStartOffsetChoice;
+ uint16_t drxLongCycleStartOffsetVal;
+}DrxLongCycleStartOffset;
+
+typedef struct shortDrx
+{
+ uint16_t drxShortCycle;
+ uint8_t drxShortCycleTimer;
+}ShortDrx;
+
+typedef struct drxInfo
+{
+ DrxOnDurationTimer drxOnDurationTimer;
+ uint16_t drxInactivityTimer;
+ uint8_t drxHarqRttTimerDl;
+ uint8_t drxHarqRttTimerUl;
+ uint16_t drxRetransmissionTimerDl;
+ uint16_t drxRetransmissionTimerUl;
+ DrxLongCycleStartOffset drxLongCycleStartOffset;
+ ShortDrx shortDrx;
+ uint8_t drxSlotOffset;
+}DrxInfo;
+#endif
+
typedef struct macCellCfg
{
uint16_t cellId; /* Cell Id */
uint8_t dmrsTypeAPos; /* DMRS Type A position */
PlmnInfoList plmnInfoList; /* Consits of PlmnId and Snssai list */
//RrmPolicy *rrmPolicy; /* RRM policy details */
+#ifdef NR_DRX
+ DrxInfo drxInfo; /* Drx info */
+#endif
}MacCellCfg;
typedef struct macCellCfgCfm