#define HQ_ACK 0
#define HQ_NACK 1
#define HQ_DTX 2
+#define ROOT_SEQ_LEN_1 139
+#define ROOT_SEQ_LEN_2 839
#ifdef NR_DRX
/* As per 38.331 the largest offset which can be used in of size 10240.
HQ_TB_WAITING
}SchHqTbState;
+#ifdef NR_TDD
+typedef enum
+{
+ DL_SLOT,
+ UL_SLOT,
+ FLEXI_SLOT
+}SlotConfig;
+#endif
+
/*Following structures to keep record and estimations of PRB allocated for each
* LC taking into consideration the RRM policies*/
typedef struct lcInfo
uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \
uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP);
}SchAllApis;
+
+typedef struct schHqCfgParam
+{
+ uint8_t maxDlDataHqTx;
+ uint8_t maxMsg4HqTx;
+ uint8_t maxUlDataHqTx;
+}SchHqCfg;
+
+typedef struct
+{
+ /* parameters derived in scheduler */
+ uint8_t n0;
+ BwpCfg bwp;
+ PdcchCfg sib1PdcchCfg;
+ PdschCfg sib1PdschCfg;
+}SchSib1Cfg;
+
/**
* @brief
* Cell Control block per cell.
#ifdef NR_TDD
uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
- uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
+ uint8_t slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT];
#endif
#ifdef NR_DRX
SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/
SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/
SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/
void *schSpcCell; /*Ref of Scheduler specific structure*/
+ SchHqCfg schHqCfg;
+ SchK0K1TimingInfoTbl k0K1InfoTbl;
+ SchK2TimingInfoTbl msg3K2InfoTbl;
+ SchK2TimingInfoTbl k2InfoTbl;
+ SchSib1Cfg sib1SchCfg; /* SIB1 config */
+ uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/
}SchCellCb;