From 8667f33257157045e9066470c657cb903adb285f Mon Sep 17 00:00:00 2001 From: svaidhya Date: Tue, 10 Jun 2025 04:41:14 +0000 Subject: [PATCH] [Epic-ID:ODUHIGH-189][Task-ID:ODUHIGH-642] SIB1 decoding issue at TM500 with FLexRAN + xFAPI Change-Id: Iaaefb93ad4fff4beefc7308b261519f1ba141f12 Signed-off-by: svaidhya --- build/config/tdd_odu_config.xml | 8 +- build/odu/makefile | 4 +- src/5gnrmac/lwr_mac_fsm.c | 18 ++- src/5gnrmac/lwr_mac_util.c | 23 ++++ src/5gnrsch/sch.c | 44 ++----- src/5gnrsch/sch.h | 7 +- src/5gnrsch/sch_utils.c | 280 ++++++++++++++++++++++++++++++++++++++++ src/cm/common_def.h | 2 +- 8 files changed, 344 insertions(+), 42 deletions(-) diff --git a/build/config/tdd_odu_config.xml b/build/config/tdd_odu_config.xml index 66db107dd..b6f354f62 100644 --- a/build/config/tdd_odu_config.xml +++ b/build/config/tdd_odu_config.xml @@ -70,7 +70,7 @@ 2 - 0 + 10 0 1 0 @@ -374,7 +374,7 @@ 0 0 0 - 0 + 10 0 1 1 @@ -440,7 +440,7 @@ 44 - 0 + 10 0 @@ -454,7 +454,7 @@ 1 - 0 + 10 0 0 8192 diff --git a/build/odu/makefile b/build/odu/makefile index f72ada986..c0792ad1f 100644 --- a/build/odu/makefile +++ b/build/odu/makefile @@ -74,7 +74,7 @@ endif # macro for output file name and makefile name # -PLTFRM_FLAGS=-UMSPD -DODU -DINTEL_FAPI -UODU_MEMORY_DEBUG_LOG -DDEBUG_ASN_PRINT -UDEBUG_PRINT -DERROR_PRINT -USTART_DL_UL_DATA -UNR_DRX -UCALL_FLOW_DEBUG_LOG -UODU_SLOT_IND_DEBUG_LOG -UNFAPI_ENABLED -DTHREAD_AFFINITY -UMEM_SIZE_CHECK -UFAPI_DECODER -UCONTAINERIZE +PLTFRM_FLAGS=-UMSPD -DODU -DINTEL_FAPI -UODU_MEMORY_DEBUG_LOG -DDEBUG_ASN_PRINT -UDEBUG_PRINT -DERROR_PRINT -USTART_DL_UL_DATA -UNR_DRX -UCALL_FLOW_DEBUG_LOG -UODU_SLOT_IND_DEBUG_LOG -UNFAPI_ENABLED -UTHREAD_AFFINITY -UMEM_SIZE_CHECK -UFAPI_DECODER -UCONTAINERIZE -DINTEL_XFAPI ifeq ($(MODE),TDD) PLTFRM_FLAGS += -DNR_TDD @@ -88,7 +88,7 @@ ifeq ($(NODE),TEST_STUB) endif ifeq ($(PHY), INTEL_L1) - PLTFRM_FLAGS+=-DSS_USE_WLS_MEM -DINTEL_WLS_MEM -DDEBUG_MODE -DINTEL_L1_V20_03_ONWARDS -UOAI_TESTING + PLTFRM_FLAGS+=-DSS_USE_WLS_MEM -DINTEL_WLS_MEM -DDEBUG_MODE -DINTEL_L1_V20_03_ONWARDS -UOAI_TESTING ifeq ($(PHY_MODE),TIMER) PLTFRM_FLAGS+=-DINTEL_TIMER_MODE endif diff --git a/src/5gnrmac/lwr_mac_fsm.c b/src/5gnrmac/lwr_mac_fsm.c index 0262be6a8..dd0e2c688 100644 --- a/src/5gnrmac/lwr_mac_fsm.c +++ b/src/5gnrmac/lwr_mac_fsm.c @@ -3611,12 +3611,14 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) /* Reversing bits in each DCI field */ #ifndef OAI_TESTING +#ifndef INTEL_XFAPI freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize); timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize); VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize); modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize); redundancyVer = reverseBits(redundancyVer, redundancyVerSize); sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize); +#endif #endif /* Calulating total number of bytes in buffer */ @@ -3639,7 +3641,11 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) for(bytePos = 0; bytePos < numBytes; bytePos++) dlDciPtr[0].payload[bytePos] = 0; - bytePos = numBytes - 1; +#ifndef INTEL_XFAPI + bytePos = numBytes - 1; +#else + bytePos = 0; /*For XFAPI, DCI is filled from 0th Index*/ +#endif #ifndef OAI_TESTING bitPos = 0; #else @@ -3661,7 +3667,6 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) sysInfoInd, sysInfoIndSize); fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ reserved, reservedSize); - } } /* fillSib1DlDciPdu */ @@ -4317,8 +4322,13 @@ uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_ dlTtiReqPdu->pdu.pdcch_pdu.bwpStart =(bwp->freqAlloc.startPrb); dlTtiReqPdu->pdu.pdcch_pdu.shiftIndex = (pdcchInfo->coresetCfg.shiftIndex); dlTtiReqPdu->pdu.pdcch_pdu.numDlDci = (pdcchInfo->numDlDci); +#ifndef INTEL_XFAPI convertFreqDomRsrcMapToIAPIFormat(pdcchInfo->coresetCfg.freqDomainResource,\ dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource); +#else + memcpy(dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource, pdcchInfo->coresetCfg.freqDomainResource, \ + sizeof(uint8_t)*6); +#endif #endif dlTtiReqPdu->pdu.pdcch_pdu.subCarrierSpacing = bwp->subcarrierSpacing; dlTtiReqPdu->pdu.pdcch_pdu.cyclicPrefix = bwp->cyclicPrefix; @@ -4737,7 +4747,11 @@ uint8_t fillSib1TxDataReq(fapi_tx_pdu_desc_t *pduDesc, uint16_t pduIndex, MacCel payloadElem = (fapi_api_queue_elem_t *)sib1Payload; FILL_FAPI_LIST_ELEM(payloadElem, NULLP, FAPI_VENDOR_MSG_PHY_ZBC_BLOCK_REQ, 1, \ macCellCfg->cellCfg.sib1Cfg.sib1PduLen); +#ifndef INTEL_XFAPI memcpy(sib1Payload + TX_PAYLOAD_HDR_LEN, macCellCfg->cellCfg.sib1Cfg.sib1Pdu, macCellCfg->cellCfg.sib1Cfg.sib1PduLen); +#else + memcpy(sib1Payload, macCellCfg->cellCfg.sib1Cfg.sib1Pdu, macCellCfg->cellCfg.sib1Cfg.sib1PduLen); +#endif #ifdef INTEL_WLS_MEM mtGetWlsHdl(&wlsHdlr); diff --git a/src/5gnrmac/lwr_mac_util.c b/src/5gnrmac/lwr_mac_util.c index 98fcd151f..895848eb5 100644 --- a/src/5gnrmac/lwr_mac_util.c +++ b/src/5gnrmac/lwr_mac_util.c @@ -113,6 +113,7 @@ void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\ #ifndef OAI_TESTING +#ifndef INTEL_XFAPI uint8_t temp; if(*bitPos + valSize <= 8) { @@ -150,6 +151,28 @@ void fillDlDciPayload(uint8_t *buf, uint8_t *bytePos, uint8_t *bitPos,\ bytePart1 = val >> bytePart2Size; + buf[*bytePos] |= bytePart1; + (*bytePos)++; + *bitPos = 0; + fillDlDciPayload(buf, bytePos, bitPos, val, bytePart2Size); + } + +#endif +#else + if(*bitPos + valSize <= 8) + { + bytePart1 = (uint8_t)val; + bytePart1 = ((~((~0) << valSize)) & bytePart1)<< (8 - (*bitPos + valSize)); + buf[*bytePos] |= bytePart1; + *bitPos += valSize; + } + else if(*bitPos + valSize > 8) + { + bytePart1Size = 8 - *bitPos; + bytePart2Size = valSize - bytePart1Size; + + bytePart1 = val >> bytePart2Size; + buf[*bytePos] |= bytePart1; (*bytePos)--; *bitPos = 0; diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index f95d1fe95..759669881 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -665,29 +665,8 @@ uint8_t fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots,SchPdcchC slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots; sib1SchCfg->n0 = slotIndex; -#ifndef OAI_TESTING - /* fill BWP */ - switch(bandwidth) - { - case BANDWIDTH_20MHZ: - { - bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0; - } - break; - case BANDWIDTH_100MHZ: - { - bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1; - } - break; - default: - DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth); - - } - bwp->freqAlloc.startPrb = 0; -#else bwp->freqAlloc.numPrb = numRbs; bwp->freqAlloc.startPrb = ((offsetPointA >> mu) - offset); -#endif bwp->subcarrierSpacing = mu; /* 15Khz */ bwp->cyclicPrefix = 0; /* normal */ @@ -698,7 +677,7 @@ uint8_t fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots,SchPdcchC /* Fill Bitmap for PRBs in coreset */ #ifndef OAI_TESTING - fillCoresetFeqDomAllocMap(((offsetPointA-offset)/6), (numRbs/6), freqDomainResource); + fillCoresetFeqDomAllocMap((((offsetPointA >> mu) - offset)/6), (numRbs/6), freqDomainResource); #else freqDomainResource[0] = (numRbs < 48) ? 0xf0 : 0xff; for(freqIdx = 1; freqIdx < FREQ_DOM_RSRC_SIZE; freqIdx++) @@ -791,26 +770,31 @@ uint8_t fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots,SchPdcchC pdsch->dmrs.dlDmrsScramblingId = pci; pdsch->dmrs.scid = 0; pdsch->dmrs.dmrsPorts = 0x0001; + pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */ pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS; pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ -#ifndef OAI_TESTING - pdsch->pdschFreqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB; - pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, DEFAULT_MCS, NUM_PDSCH_SYMBOL); -#endif pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ - pdsch->pdschTimeAlloc.rowIndex = 1; + pdsch->pdschTimeAlloc.rowIndex = 12; /* Index used for 38.214, Table 5.1.2.1.1-2 till Table 5.1.2.1.1-5*/ + if(getTdaInfo(&pdsch->pdschTimeAlloc, 0, DMRS_ADDITIONAL_POS, bwp->cyclicPrefix) != ROK) + { + DU_LOG("\nERROR --> SCH: fillSchSib1Cfg: getTdaInfo for PDSCH failed"); + return RFAILED; + } /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */ - pdsch->pdschTimeAlloc.numSymb = NUM_PDSCH_SYMBOL; #ifndef OAI_TESTING - pdsch->pdschTimeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ +#ifndef INTEL_XFAPI + pdsch->pdschFreqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB; + pdsch->pdschFreqAlloc.numPrb = schCalcNumPrb(tbSize, DEFAULT_MCS, pdsch->pdschTimeAlloc.numSymb); +#endif pdsch->beamPdschInfo.numPrgs = 1; pdsch->beamPdschInfo.prgSize = 1; pdsch->beamPdschInfo.digBfInterfaces = 0; #else + pdsch->pdschTimeAlloc.numSymb = NUM_PDSCH_SYMBOL; pdsch->pdschTimeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */ pdsch->beamPdschInfo.numPrgs = 0; pdsch->beamPdschInfo.prgSize = 0; @@ -1521,7 +1505,7 @@ uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \ } /* Update bitmap to allocate PRBs */ - for(symbol=startSymbol; symbol < (startSymbol+symbolLength); symbol++) + for(symbol=startSymbol; symbol < symbolLength; symbol++) { if(fillPrbBitmap(prbAlloc->prbBitMap[symbol], *startPrb, numPrb) != ROK) { diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index f9523867a..b7bda6233 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -49,16 +49,16 @@ #ifdef OAI_TESTING #define NUM_PDSCH_SYMBOL 10 #else - #define NUM_PDSCH_SYMBOL 11 + #define NUM_PDSCH_SYMBOL 13 #endif #define PUSCH_START_RB 15 #define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */ #define SI_RNTI 0xFFFF #define P_RNTI 0xFFFE -#define DMRS_MAP_TYPE_A 1 +#define DMRS_MAP_TYPE_A 0 #define NUM_DMRS_SYMBOLS 1 -#define DMRS_ADDITIONAL_POS 0 +#define DMRS_ADDITIONAL_POS 2 #define SCH_DEFAULT_K1 1 #define SSB_IDX_SUPPORTED 1 @@ -867,6 +867,7 @@ uint8_t schCalcAndSendGrpStats(SchStatsGrp *grpInfo); uint8_t SchProcStatsDeleteReq(Pst *pst, SchStatsDeleteReq *statsDeleteReq); uint8_t SchProcStatsModificationReq(Pst *pst, SchStatsModificationReq *statsModificationReq); void deleteStatsGrpInfo(Inst inst, SchStatsGrp *statsGrpInfo); +uint8_t getTdaInfo(PdschTimeAlloc *pdschTimeAlloc,uint8_t tableType, uint8_t dmrsTypeAPos, uint8_t cyclicPrefix); /********************************************************************** End of file **********************************************************************/ diff --git a/src/5gnrsch/sch_utils.c b/src/5gnrsch/sch_utils.c index 76d6ae050..e5b7ee4e2 100644 --- a/src/5gnrsch/sch_utils.c +++ b/src/5gnrsch/sch_utils.c @@ -806,6 +806,173 @@ uint8_t minMsg3SchTime[MAX_NUM_MU] = {6, 6, 6, 6}; uint8_t defaultUlAckTbl[DEFAULT_UL_ACK_LIST_COUNT]= {1, 2, 3 , 4, 5, 6, 7, 8}; uint8_t schCmnDlRvTbl[4] = {0, 2, 3, 1}; + +/* Following tables are for PDSCH Time Domain Allocation from TS 38.214 subclause 5.1.2.1.1*/ + +/*Table 5.1.2.1.1-2 for PDSCH time domain Allocation table-type as DefaultA + * Cyclic Prefix = Normal and dmrs_TypeA_position = 2*/ +const uint8_t tda_DefaultA_NormalCP_dmrsTypeApos2[16][4]={ + {1,0,2,12}, // row index 1 + {1,0,2,10}, // row index 2 + {1,0,2,9}, // row index 3 + {1,0,2,7}, // row index 4 + {1,0,2,5}, // row index 5 + {0,0,9,4}, // row index 6 + {0,0,4,4}, // row index 7 + {0,0,5,7}, // row index 8 + {0,0,5,2}, // row index 9 + {0,0,9,2}, // row index 10 + {0,0,12,2}, // row index 11 + {1,0,1,13}, // row index 12 + {1,0,1,6}, // row index 13 + {1,0,2,4}, // row index 14 + {0,0,4,7}, // row index 15 + {0,0,8,4} // row index 16 +}; + +/*Table 5.1.2.1.1-2 for PDSCH time domain Allocation table-type as DefaultA, + * Cyclic Prefix = Normal and dmrs_TypeA_position = 3*/ +const uint8_t tda_DefaultA_NormalCP_dmrsTypeApos3[16][4]={ + {1,0,3,11}, // row index 1 + {1,0,3,9}, // row index 2 + {1,0,3,8}, // row index 3 + {1,0,3,6}, // row index 4 + {1,0,3,4}, // row index 5 + {0,0,10,4}, // row index 6 + {0,0,6,4}, // row index 7 + {0,0,5,7}, // row index 8 + {0,0,5,2}, // row index 9 + {0,0,9,2}, // row index 10 + {0,0,12,2}, // row index 11 + {1,0,1,13}, // row index 12 + {1,0,1,6}, // row index 13 + {1,0,2,4}, // row index 14 + {0,0,4,7}, // row index 15 + {0,0,8,4} // row index 16 +}; + +/*Table 5.1.2.1.1-3 for PDSCH time domain Allocation table-type as DefaultA, + * Cyclic Prefix = Extended and dmrs_TypeA_position = 2*/ +const uint8_t tda_DefaultA_ExtCP_dmrsTypeApos2[16][4]={ + {1,0,2,6}, // row index 1 + {1,0,2,10}, // row index 2 + {1,0,2,9}, // row index 3 + {1,0,2,7}, // row index 4 + {1,0,2,5}, // row index 5 + {0,0,6,4}, // row index 6 + {0,0,4,4}, // row index 7 + {0,0,5,6}, // row index 8 + {0,0,5,2}, // row index 9 + {0,0,9,2}, // row index 10 + {0,0,10,2}, // row index 11 + {1,0,1,11}, // row index 12 + {1,0,1,6}, // row index 13 + {1,0,2,4}, // row index 14 + {0,0,4,6}, // row index 15 + {0,0,8,4} // row index 16 +}; + +/*Table 5.1.2.1.1-3 for PDSCH time domain Allocation table-type as DefaultA, + * Cyclic Prefix = Extended and dmrs_TypeA_position = 3*/ +const uint8_t tda_DefaultA_ExtCP_dmrsTypeApos3[16][4]={ + {1,0,3,5}, // row index 1 + {1,0,3,9}, // row index 2 + {1,0,3,8}, // row index 3 + {1,0,3,6}, // row index 4 + {1,0,3,4}, // row index 5 + {0,0,8,2}, // row index 6 + {0,0,6,4}, // row index 7 + {0,0,5,6}, // row index 8 + {0,0,5,2}, // row index 9 + {0,0,9,2}, // row index 10 + {0,0,10,2}, // row index 11 + {1,0,1,11}, // row index 12 + {1,0,1,6}, // row index 13 + {1,0,2,4}, // row index 14 + {0,0,4,6}, // row index 15 + {0,0,8,4} // row index 16 +}; + +/*Table 5.1.2.1.1-4 for PDSCH time domain Allocation table-type as DefaultB, dmrs_TypeA_position = 2*/ +const uint8_t tda_DefaultB_dmrsTypeApos2[16][4]={ + {0,0,2,2}, // row index 1 + {0,0,4,2}, // row index 2 + {0,0,6,2}, // row index 3 + {0,0,8,2}, // row index 4 + {0,0,10,2}, // row index 5 + {0,1,2,2}, // row index 6 + {0,1,4,2}, // row index 7 + {0,0,2,4}, // row index 8 + {0,0,4,4}, // row index 9 + {0,0,6,4}, // row index 10 + {0,0,8,4}, // row index 11 + {0,0,10,4}, // row index 12 + {0,0,2,7}, // row index 13 + {1,0,2,12}, // row index 14 + {0,1,2,4}, // row index 15 + {0,0,0,0} // row index 16 +}; + +/*Table 5.1.2.1.1-4 for PDSCH time domain Allocation table-type as DefaultB, dmrs_TypeA_position = 3*/ +const uint8_t tda_DefaultB_dmrsTypeApos3[16][4]={ + {0,0,2,2}, // row index 1 + {0,0,4,2}, // row index 2 + {0,0,6,2}, // row index 3 + {0,0,8,2}, // row index 4 + {0,0,10,2}, // row index 5 + {0,1,2,2}, // row index 6 + {0,1,4,2}, // row index 7 + {0,0,2,4}, // row index 8 + {0,0,4,4}, // row index 9 + {0,0,6,4}, // row index 10 + {0,0,8,4}, // row index 11 + {0,0,10,4}, // row index 12 + {0,0,2,7}, // row index 13 + {1,0,3,11}, // row index 14 + {0,1,2,4}, // row index 15 + {0,0,0,0} // row index 16 +}; + +/*Table 5.1.2.1.1-5 for PDSCH time domain Allocation table-type as DefaultC, dmrs_TypeA_position = 2*/ +const uint8_t tda_DefaultC_dmrsTypeApos2[16][4]={ + {0,0,2,2}, // row index 1 + {0,0,4,2}, // row index 2 + {0,0,6,2}, // row index 3 + {0,0,8,2}, // row index 4 + {0,0,10,2}, // row index 5 + {0,0,0,0}, // row index 6 + {0,0,0,0}, // row index 7 + {0,0,2,4}, // row index 8 + {0,0,4,4}, // row index 9 + {0,0,6,4}, // row index 10 + {0,0,8,4}, // row index 11 + {0,0,10,4}, // row index 12 + {0,0,2,7}, // row index 13 + {1,0,2,12}, // row index 14 + {1,0,0,6}, // row index 15 + {1,0,2,6} // row index 16 +}; + +/*Table 5.1.2.1.1-5 for PDSCH time domain Allocation table-type as DefaultC, dmrs_TypeA_position = 3*/ +const uint8_t tda_DefaultC_dmrsTypeApos3[16][4]={ + {0,0,2,2}, // row index 1 + {0,0,4,2}, // row index 2 + {0,0,6,2}, // row index 3 + {0,0,8,2}, // row index 4 + {0,0,10,2}, // row index 5 + {0,0,0,0}, // row index 6 + {0,0,0,0}, // row index 7 + {0,0,2,4}, // row index 8 + {0,0,4,4}, // row index 9 + {0,0,6,4}, // row index 10 + {0,0,8,4}, // row index 11 + {0,0,10,4}, // row index 12 + {0,0,2,7}, // row index 13 + {1,0,3,11}, // row index 14 + {1,0,0,6}, // row index 15 + {1,0,2,6} // row index 16 +}; + /** * @brief Function to find first DMRS symbol in PDSCH * @@ -2305,6 +2472,119 @@ uint8_t extractNumOfCandForAggLvl(SchSearchSpace *searchSpace, uint8_t aggLvl) } return numCand; } + +/* + * @brief Function to calculate the PDSCH Time Domain Allocation parameters based on + * Spec 38.214 Section 5.1.2.1.1 + * + * Function: getTdaInfo + * + * As per Spec 38.214, Sec 5.1.2.1.1 Based on Either a default PDSCH time domain allocation A, B or C + * + * + * @params[in] : pdschTimeAlloc.rowIndex, tableType[default A(0), B(1), C(2)], dmrsTypeAPos(2/3) + * [return] : uint8_t ROK, RFAILED : Time Domain allocation status + * pdschTimeAlloc.startSymbolIndex and pdschTimeAlloc.numSymbols + * + * */ +uint8_t getTdaInfo(PdschTimeAlloc *pdschTimeAlloc,uint8_t tableType, uint8_t dmrsTypeAPos, uint8_t cyclicPrefix) +{ + uint8_t rowIndex = pdschTimeAlloc->rowIndex -1; + switch(tableType) + { + case 0: /*Default-A*/ + { + if(cyclicPrefix == 0)/*Normal-CP*/ + { + if(dmrsTypeAPos == 2) + { + pdschTimeAlloc->startSymb = tda_DefaultA_NormalCP_dmrsTypeApos2[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultA_NormalCP_dmrsTypeApos2[rowIndex][3]; + } + else if(dmrsTypeAPos == 3) + { + pdschTimeAlloc->startSymb = tda_DefaultA_NormalCP_dmrsTypeApos3[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultA_NormalCP_dmrsTypeApos3[rowIndex][3]; + } + else + { + DU_LOG("\nERROR --> SCH_UTILS: getTdaInfo: Incorrect dmrsTypeAPos:%d",dmrsTypeAPos); + return RFAILED; + } + } + else if(cyclicPrefix == 1) /*extended-CP*/ + { + if(dmrsTypeAPos == 2) + { + pdschTimeAlloc->startSymb = tda_DefaultA_ExtCP_dmrsTypeApos2[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultA_ExtCP_dmrsTypeApos2[rowIndex][3]; + } + else if(dmrsTypeAPos == 3) + { + pdschTimeAlloc->startSymb = tda_DefaultA_ExtCP_dmrsTypeApos3[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultA_ExtCP_dmrsTypeApos3[rowIndex][3]; + } + else + { + DU_LOG("\nERROR --> SCH_UTILS: getTdaInfo: Incorrect dmrsTypeAPos:%d",dmrsTypeAPos); + return RFAILED; + } + } + else + { + DU_LOG("\nERROR --> SCH: getTdaInfo: Invalid CyclicPrefix:%d",cyclicPrefix); + return RFAILED; + } + break; + } + case 1:/*Default-B*/ + { + if(dmrsTypeAPos == 2) + { + pdschTimeAlloc->startSymb = tda_DefaultB_dmrsTypeApos2[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultB_dmrsTypeApos2[rowIndex][3]; + } + else if(dmrsTypeAPos == 3) + { + pdschTimeAlloc->startSymb = tda_DefaultB_dmrsTypeApos3[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultB_dmrsTypeApos3[rowIndex][3]; + + } + else + { + DU_LOG("\nERROR --> SCH_UTILS: getTdaInfo: Incorrect dmrsTypeAPos:%d",dmrsTypeAPos); + return RFAILED; + } + break; + } + case 2:/*Default-C*/ + { + if(dmrsTypeAPos == 2) + { + pdschTimeAlloc->startSymb = tda_DefaultC_dmrsTypeApos2[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultC_dmrsTypeApos2[rowIndex][3]; + } + else if(dmrsTypeAPos == 3) + { + pdschTimeAlloc->startSymb = tda_DefaultC_dmrsTypeApos3[rowIndex][2]; + pdschTimeAlloc->numSymb = tda_DefaultC_dmrsTypeApos3[rowIndex][3]; + + } + else + { + DU_LOG("\nERROR --> SCH_UTILS: getTdaInfo: Incorrect dmrsTypeAPos:%d",dmrsTypeAPos); + return RFAILED; + } + break; + } + default: + { + DU_LOG("\nERROR --> SCH_UTILS: getTdaInfo: Invalid dmrsTypeAPos:%d",dmrsTypeAPos); + return RFAILED; + } + } + return ROK; +} /********************************************************************** End of file **********************************************************************/ diff --git a/src/cm/common_def.h b/src/cm/common_def.h index ca4a7b85f..bb1ebab24 100644 --- a/src/cm/common_def.h +++ b/src/cm/common_def.h @@ -95,7 +95,7 @@ #define PUCCH_FORMAT_3 3 #define PUCCH_FORMAT_4 4 -#define DEFAULT_MCS 4 +#define DEFAULT_MCS 9 #define BANDWIDTH_20MHZ 20 #define BANDWIDTH_100MHZ 100 -- 2.16.6