From: svaidhya Date: Thu, 14 Dec 2023 04:34:52 +0000 (+0530) Subject: [Epic-ID: ODUHIGH-517][Task-ID: ODUHIGH-540][Sub-Task-ID: ODUHIGH-548]| MUlti UE... X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=fcf583c575025651191abc59b4a4535a9d01eab1;p=o-du%2Fl2.git [Epic-ID: ODUHIGH-517][Task-ID: ODUHIGH-540][Sub-Task-ID: ODUHIGH-548]| MUlti UE | Multiple DCI Change-Id: I118f7f7e229e65700e4413c86e30b5c0cb67d067 Signed-off-by: svaidhya --- diff --git a/src/5gnrmac/lwr_mac_fsm.c b/src/5gnrmac/lwr_mac_fsm.c index b05d963ee..4c2de0ac5 100644 --- a/src/5gnrmac/lwr_mac_fsm.c +++ b/src/5gnrmac/lwr_mac_fsm.c @@ -2530,18 +2530,18 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) uint8_t sysInfoIndSize = 1; uint8_t reservedSize = 15; - dlDciPtr->rnti = sib1PdcchInfo->dci.rnti; - dlDciPtr->scramblingId = sib1PdcchInfo->dci.scramblingId; - dlDciPtr->scramblingRnti = sib1PdcchInfo->dci.scramblingRnti; - dlDciPtr->cceIndex = sib1PdcchInfo->dci.cceIndex; - dlDciPtr->aggregationLevel = sib1PdcchInfo->dci.aggregLevel; - dlDciPtr->pc_and_bform.numPrgs = sib1PdcchInfo->dci.beamPdcchInfo.numPrgs; - dlDciPtr->pc_and_bform.prgSize = sib1PdcchInfo->dci.beamPdcchInfo.prgSize; - dlDciPtr->pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci.beamPdcchInfo.digBfInterfaces; - dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; - dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = sib1PdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; - dlDciPtr->powerControlOffsetSS = sib1PdcchInfo->dci.txPdcchPower.powerControlOffsetSS; + dlDciPtr[0].rnti = sib1PdcchInfo->dci[0].rnti; + dlDciPtr[0].scramblingId = sib1PdcchInfo->dci[0].scramblingId; + dlDciPtr[0].scramblingRnti = sib1PdcchInfo->dci[0].scramblingRnti; + dlDciPtr[0].cceIndex = sib1PdcchInfo->dci[0].cceIndex; + dlDciPtr[0].aggregationLevel = sib1PdcchInfo->dci[0].aggregLevel; + dlDciPtr[0].pc_and_bform.numPrgs = sib1PdcchInfo->dci[0].beamPdcchInfo.numPrgs; + dlDciPtr[0].pc_and_bform.prgSize = sib1PdcchInfo->dci[0].beamPdcchInfo.prgSize; + dlDciPtr[0].pc_and_bform.digBfInterfaces = sib1PdcchInfo->dci[0].beamPdcchInfo.digBfInterfaces; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = sib1PdcchInfo->dci[0].beamPdcchInfo.prg[0].pmIdx; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = sib1PdcchInfo->dci[0].beamPdcchInfo.prg[0].beamIdx[0]; + dlDciPtr[0].beta_pdcch_1_0 = sib1PdcchInfo->dci[0].txPdcchPower.beta_pdcch_1_0; + dlDciPtr[0].powerControlOffsetSS = sib1PdcchInfo->dci[0].txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size * coreset0Size = Size of coreset 0 @@ -2550,8 +2550,8 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) * Spec 38.214 Sec 5.1.2.2.2 */ coreset0Size= sib1PdcchInfo->coresetCfg.coreSetSize; - rbStart = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb; - rbLen = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb; + rbStart = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.startPrb; + rbLen = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coreset0Size - rbStart)) { @@ -2565,10 +2565,10 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) } /* Fetching DCI field values */ - timeDomResAssign = sib1PdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1; - VRB2PRBMap = sib1PdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping; - modNCodScheme = sib1PdcchInfo->dci.pdschCfg.codeword[0].mcsIndex; - redundancyVer = sib1PdcchInfo->dci.pdschCfg.codeword[0].rvIndex; + timeDomResAssign = sib1PdcchInfo->dci[0].pdschCfg.pdschTimeAlloc.rowIndex -1; + VRB2PRBMap = sib1PdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.vrbPrbMapping; + modNCodScheme = sib1PdcchInfo->dci[0].pdschCfg.codeword[0].mcsIndex; + redundancyVer = sib1PdcchInfo->dci[0].pdschCfg.codeword[0].rvIndex; sysInfoInd = 0; /* 0 for SIB1; 1 for SI messages */ reserved = 0; @@ -2581,12 +2581,12 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) sysInfoInd = reverseBits(sysInfoInd, sysInfoIndSize); /* Calulating total number of bytes in buffer */ - dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\ + dlDciPtr[0].payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\ + VRB2PRBMapSize + modNCodSchemeSize + redundancyVerSize\ + sysInfoIndSize + reservedSize; - numBytes = dlDciPtr->payloadSizeBits / 8; - if(dlDciPtr->payloadSizeBits % 8) + numBytes = dlDciPtr[0].payloadSizeBits / 8; + if(dlDciPtr[0].payloadSizeBits % 8) numBytes += 1; if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN) @@ -2597,25 +2597,25 @@ void fillSib1DlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *sib1PdcchInfo) /* Initialize buffer */ for(bytePos = 0; bytePos < numBytes; bytePos++) - dlDciPtr->payload[bytePos] = 0; + dlDciPtr[0].payload[bytePos] = 0; bytePos = numBytes - 1; bitPos = 0; /* Packing DCI format fields */ - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ freqDomResAssign, freqDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ timeDomResAssign, timeDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ VRB2PRBMap, VRB2PRBMapSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ modNCodScheme, modNCodSchemeSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ redundancyVer, redundancyVerSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ sysInfoInd, sysInfoIndSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ reserved, reservedSize); } @@ -2670,18 +2670,18 @@ void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc, MacCell uint8_t tbScalingSize = 2; uint8_t reservedSize = 6; - dlDciPtr->rnti = P_RNTI; - dlDciPtr->scramblingId = macCellCfg->cellCfg.phyCellId; - dlDciPtr->scramblingRnti = 0; - dlDciPtr->cceIndex = dlPageAlloc->pageDlDci.cceIndex; - dlDciPtr->aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel; - dlDciPtr->pc_and_bform.numPrgs = 1; - dlDciPtr->pc_and_bform.prgSize = 1; - dlDciPtr->pc_and_bform.digBfInterfaces = 0; - dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = 0; - dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0; - dlDciPtr->beta_pdcch_1_0 = 0; - dlDciPtr->powerControlOffsetSS = 0; + dlDciPtr[0].rnti = P_RNTI; + dlDciPtr[0].scramblingId = macCellCfg->cellCfg.phyCellId; + dlDciPtr[0].scramblingRnti = 0; + dlDciPtr[0].cceIndex = dlPageAlloc->pageDlDci.cceIndex; + dlDciPtr[0].aggregationLevel = dlPageAlloc->pageDlDci.aggregLevel; + dlDciPtr[0].pc_and_bform.numPrgs = 1; + dlDciPtr[0].pc_and_bform.prgSize = 1; + dlDciPtr[0].pc_and_bform.digBfInterfaces = 0; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = 0; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = 0; + dlDciPtr[0].beta_pdcch_1_0 = 0; + dlDciPtr[0].powerControlOffsetSS = 0; /* Calculating freq domain resource allocation field value and size * coreset0Size = Size of coreset 0 @@ -2746,12 +2746,12 @@ void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc, MacCell tbScaling = reverseBits(tbScaling, tbScalingSize); /* Calulating total number of bytes in buffer */ - dlDciPtr->payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\ + dlDciPtr[0].payloadSizeBits = shortMsgIndSize + shortMsgSize + freqDomResAssignSize\ + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\ + tbScaling + reservedSize; - numBytes = dlDciPtr->payloadSizeBits / 8; - if(dlDciPtr->payloadSizeBits % 8) + numBytes = dlDciPtr[0].payloadSizeBits / 8; + if(dlDciPtr[0].payloadSizeBits % 8) { numBytes += 1; } @@ -2765,28 +2765,28 @@ void fillPageDlDciPdu(fapi_dl_dci_t *dlDciPtr, DlPageAlloc *dlPageAlloc, MacCell /* Initialize buffer */ for(bytePos = 0; bytePos < numBytes; bytePos++) { - dlDciPtr->payload[bytePos] = 0; + dlDciPtr[0].payload[bytePos] = 0; } bytePos = numBytes - 1; bitPos = 0; /* Packing DCI format fields */ - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ shortMsgInd, shortMsgIndSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ shortMsg, shortMsgSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ freqDomResAssign, freqDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ timeDomResAssign, timeDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ VRB2PRBMap, VRB2PRBMapSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ modNCodScheme, modNCodSchemeSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ tbScaling, tbScalingSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ reserved, reservedSize); } } /* fillPageDlDciPdu */ @@ -2834,18 +2834,18 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) uint8_t tbScalingSize = 2; uint8_t reservedSize = 16; - dlDciPtr->rnti = rarPdcchInfo->dci.rnti; - dlDciPtr->scramblingId = rarPdcchInfo->dci.scramblingId; - dlDciPtr->scramblingRnti = rarPdcchInfo->dci.scramblingRnti; - dlDciPtr->cceIndex = rarPdcchInfo->dci.cceIndex; - dlDciPtr->aggregationLevel = rarPdcchInfo->dci.aggregLevel; - dlDciPtr->pc_and_bform.numPrgs = rarPdcchInfo->dci.beamPdcchInfo.numPrgs; - dlDciPtr->pc_and_bform.prgSize = rarPdcchInfo->dci.beamPdcchInfo.prgSize; - dlDciPtr->pc_and_bform.digBfInterfaces = rarPdcchInfo->dci.beamPdcchInfo.digBfInterfaces; - dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; - dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = rarPdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; - dlDciPtr->powerControlOffsetSS = rarPdcchInfo->dci.txPdcchPower.powerControlOffsetSS; + dlDciPtr[0].rnti = rarPdcchInfo->dci[0].rnti; + dlDciPtr[0].scramblingId = rarPdcchInfo->dci[0].scramblingId; + dlDciPtr[0].scramblingRnti = rarPdcchInfo->dci[0].scramblingRnti; + dlDciPtr[0].cceIndex = rarPdcchInfo->dci[0].cceIndex; + dlDciPtr[0].aggregationLevel = rarPdcchInfo->dci[0].aggregLevel; + dlDciPtr[0].pc_and_bform.numPrgs = rarPdcchInfo->dci[0].beamPdcchInfo.numPrgs; + dlDciPtr[0].pc_and_bform.prgSize = rarPdcchInfo->dci[0].beamPdcchInfo.prgSize; + dlDciPtr[0].pc_and_bform.digBfInterfaces = rarPdcchInfo->dci[0].beamPdcchInfo.digBfInterfaces; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].pmIdx = rarPdcchInfo->dci[0].beamPdcchInfo.prg[0].pmIdx; + dlDciPtr[0].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = rarPdcchInfo->dci[0].beamPdcchInfo.prg[0].beamIdx[0]; + dlDciPtr[0].beta_pdcch_1_0 = rarPdcchInfo->dci[0].txPdcchPower.beta_pdcch_1_0; + dlDciPtr[0].powerControlOffsetSS = rarPdcchInfo->dci[0].txPdcchPower.powerControlOffsetSS; /* Calculating freq domain resource allocation field value and size * coreset0Size = Size of coreset 0 @@ -2856,8 +2856,8 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) /* TODO: Fill values of coreset0Size, rbStart and rbLen */ coreset0Size= rarPdcchInfo->coresetCfg.coreSetSize; - rbStart = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb; - rbLen = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb; + rbStart = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.startPrb; + rbLen = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.numPrb; if((rbLen >=1) && (rbLen <= coreset0Size - rbStart)) { @@ -2871,9 +2871,9 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) } /* Fetching DCI field values */ - timeDomResAssign = rarPdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex; - VRB2PRBMap = rarPdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping; - modNCodScheme = rarPdcchInfo->dci.pdschCfg.codeword[0].mcsIndex; + timeDomResAssign = rarPdcchInfo->dci[0].pdschCfg.pdschTimeAlloc.rowIndex; + VRB2PRBMap = rarPdcchInfo->dci[0].pdschCfg.pdschFreqAlloc.vrbPrbMapping; + modNCodScheme = rarPdcchInfo->dci[0].pdschCfg.codeword[0].mcsIndex; tbScaling = 0; /* configured to 0 scaling */ reserved = 0; @@ -2885,11 +2885,11 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) tbScaling = reverseBits(tbScaling, tbScalingSize); /* Calulating total number of bytes in buffer */ - dlDciPtr->payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\ + dlDciPtr[0].payloadSizeBits = freqDomResAssignSize + timeDomResAssignSize\ + VRB2PRBMapSize + modNCodSchemeSize + tbScalingSize + reservedSize; - numBytes = dlDciPtr->payloadSizeBits / 8; - if(dlDciPtr->payloadSizeBits % 8) + numBytes = dlDciPtr[0].payloadSizeBits / 8; + if(dlDciPtr[0].payloadSizeBits % 8) numBytes += 1; if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN) @@ -2900,23 +2900,23 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) /* Initialize buffer */ for(bytePos = 0; bytePos < numBytes; bytePos++) - dlDciPtr->payload[bytePos] = 0; + dlDciPtr[0].payload[bytePos] = 0; bytePos = numBytes - 1; bitPos = 0; /* Packing DCI format fields */ - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ freqDomResAssign, freqDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ timeDomResAssign, timeDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ VRB2PRBMap, VRB2PRBMapSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ modNCodScheme, modNCodSchemeSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ tbScaling, tbScalingSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ + fillDlDciPayload(dlDciPtr[0].payload, &bytePos, &bitPos,\ reserved, reservedSize); } } /* fillRarDlDciPdu */ @@ -2940,6 +2940,7 @@ void fillRarDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *rarPdcchInfo) void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\ DlMsgSchInfo *dlMsgSchInfo) { + uint8_t dciIndex = 0; if(dlDciPtr != NULLP) { uint8_t numBytes; @@ -2976,118 +2977,121 @@ void fillDlMsgDlDciPdu(fapi_dl_dci_t *dlDciPtr, PdcchCfg *pdcchInfo,\ uint8_t pucchResoIndSize = 3; uint8_t harqFeedbackIndSize = 3; - dlDciPtr->rnti = pdcchInfo->dci.rnti; - dlDciPtr->scramblingId = pdcchInfo->dci.scramblingId; - dlDciPtr->scramblingRnti = pdcchInfo->dci.scramblingRnti; - dlDciPtr->cceIndex = pdcchInfo->dci.cceIndex; - dlDciPtr->aggregationLevel = pdcchInfo->dci.aggregLevel; - dlDciPtr->pc_and_bform.numPrgs = pdcchInfo->dci.beamPdcchInfo.numPrgs; - dlDciPtr->pc_and_bform.prgSize = pdcchInfo->dci.beamPdcchInfo.prgSize; - dlDciPtr->pc_and_bform.digBfInterfaces = pdcchInfo->dci.beamPdcchInfo.digBfInterfaces; - dlDciPtr->pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci.beamPdcchInfo.prg[0].pmIdx; - dlDciPtr->pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci.beamPdcchInfo.prg[0].beamIdx[0]; - dlDciPtr->beta_pdcch_1_0 = pdcchInfo->dci.txPdcchPower.beta_pdcch_1_0; - dlDciPtr->powerControlOffsetSS = pdcchInfo->dci.txPdcchPower.powerControlOffsetSS; - - /* Calculating freq domain resource allocation field value and size - * coreset0Size = Size of coreset 0 - * RBStart = Starting Virtual Rsource block - * RBLen = length of contiguously allocted RBs - * Spec 38.214 Sec 5.1.2.2.2 - */ - coresetSize = pdcchInfo->coresetCfg.coreSetSize; - rbStart = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.startPrb; - rbLen = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.numPrb; - - if((rbLen >=1) && (rbLen <= coresetSize - rbStart)) + for(dciIndex = 0; dciIndex < pdcchInfo->numDlDci; dciIndex++) { - if((rbLen - 1) <= floor(coresetSize / 2)) - freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart; - else - freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \ - + (coresetSize - 1 - rbStart); - - freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2)); - } - - /* Fetching DCI field values */ - dciFormatId = dlMsgSchInfo->dciFormatId; /* Always set to 1 for DL */ - timeDomResAssign = pdcchInfo->dci.pdschCfg.pdschTimeAlloc.rowIndex -1; - VRB2PRBMap = pdcchInfo->dci.pdschCfg.pdschFreqAlloc.vrbPrbMapping; - modNCodScheme = pdcchInfo->dci.pdschCfg.codeword[0].mcsIndex; - ndi = dlMsgSchInfo->transportBlock[0].ndi; - redundancyVer = pdcchInfo->dci.pdschCfg.codeword[0].rvIndex; - harqProcessNum = dlMsgSchInfo->harqProcNum; - dlAssignmentIdx = dlMsgSchInfo->dlAssignIdx; - pucchTpc = dlMsgSchInfo->pucchTpc; - pucchResoInd = dlMsgSchInfo->pucchResInd; - harqFeedbackInd = dlMsgSchInfo->harqFeedbackInd; + dlDciPtr[dciIndex].rnti = pdcchInfo->dci[dciIndex].rnti; + dlDciPtr[dciIndex].scramblingId = pdcchInfo->dci[dciIndex].scramblingId; + dlDciPtr[dciIndex].scramblingRnti = pdcchInfo->dci[dciIndex].scramblingRnti; + dlDciPtr[dciIndex].cceIndex = pdcchInfo->dci[dciIndex].cceIndex; + dlDciPtr[dciIndex].aggregationLevel = pdcchInfo->dci[dciIndex].aggregLevel; + dlDciPtr[dciIndex].pc_and_bform.numPrgs = pdcchInfo->dci[dciIndex].beamPdcchInfo.numPrgs; + dlDciPtr[dciIndex].pc_and_bform.prgSize = pdcchInfo->dci[dciIndex].beamPdcchInfo.prgSize; + dlDciPtr[dciIndex].pc_and_bform.digBfInterfaces = pdcchInfo->dci[dciIndex].beamPdcchInfo.digBfInterfaces; + dlDciPtr[dciIndex].pc_and_bform.pmi_bfi[0].pmIdx = pdcchInfo->dci[dciIndex].beamPdcchInfo.prg[0].pmIdx; + dlDciPtr[dciIndex].pc_and_bform.pmi_bfi[0].beamIdx[0].beamidx = pdcchInfo->dci[dciIndex].beamPdcchInfo.prg[0].beamIdx[0]; + dlDciPtr[dciIndex].beta_pdcch_1_0 = pdcchInfo->dci[dciIndex].txPdcchPower.beta_pdcch_1_0; + dlDciPtr[dciIndex].powerControlOffsetSS = pdcchInfo->dci[dciIndex].txPdcchPower.powerControlOffsetSS; + + /* Calculating freq domain resource allocation field value and size + * coreset0Size = Size of coreset 0 + * RBStart = Starting Virtual Rsource block + * RBLen = length of contiguously allocted RBs + * Spec 38.214 Sec 5.1.2.2.2 + */ + coresetSize = pdcchInfo->coresetCfg.coreSetSize; + rbStart = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.startPrb; + rbLen = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.numPrb; + + if((rbLen >=1) && (rbLen <= coresetSize - rbStart)) + { + if((rbLen - 1) <= floor(coresetSize / 2)) + freqDomResAssign = (coresetSize * (rbLen-1)) + rbStart; + else + freqDomResAssign = (coresetSize * (coresetSize - rbLen + 1)) \ + + (coresetSize - 1 - rbStart); - /* Reversing bits in each DCI field */ - dciFormatId = reverseBits(dciFormatId, dciFormatIdSize); - freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize); - timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize); - VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize); - modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize); - ndi = reverseBits(ndi, ndiSize); - redundancyVer = reverseBits(redundancyVer, redundancyVerSize); - harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize); - dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize); - pucchTpc = reverseBits(pucchTpc, pucchTpcSize); - pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize); - harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize); + freqDomResAssignSize = ceil(log2(coresetSize * (coresetSize + 1) / 2)); + } + /* Fetching DCI field values */ + dciFormatId = dlMsgSchInfo->dciFormatId; /* Always set to 1 for DL */ + timeDomResAssign = pdcchInfo->dci[dciIndex].pdschCfg.pdschTimeAlloc.rowIndex -1; + VRB2PRBMap = pdcchInfo->dci[dciIndex].pdschCfg.pdschFreqAlloc.vrbPrbMapping; + modNCodScheme = pdcchInfo->dci[dciIndex].pdschCfg.codeword[0].mcsIndex; + ndi = dlMsgSchInfo->transportBlock[0].ndi; + redundancyVer = pdcchInfo->dci[dciIndex].pdschCfg.codeword[0].rvIndex; + harqProcessNum = dlMsgSchInfo->harqProcNum; + dlAssignmentIdx = dlMsgSchInfo->dlAssignIdx; + pucchTpc = dlMsgSchInfo->pucchTpc; + pucchResoInd = dlMsgSchInfo->pucchResInd; + harqFeedbackInd = dlMsgSchInfo->harqFeedbackInd; - /* Calulating total number of bytes in buffer */ - dlDciPtr->payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\ - + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\ - + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\ - + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize); + /* Reversing bits in each DCI field */ + dciFormatId = reverseBits(dciFormatId, dciFormatIdSize); + freqDomResAssign = reverseBits(freqDomResAssign, freqDomResAssignSize); + timeDomResAssign = reverseBits(timeDomResAssign, timeDomResAssignSize); + VRB2PRBMap = reverseBits(VRB2PRBMap, VRB2PRBMapSize); + modNCodScheme = reverseBits(modNCodScheme, modNCodSchemeSize); + ndi = reverseBits(ndi, ndiSize); + redundancyVer = reverseBits(redundancyVer, redundancyVerSize); + harqProcessNum = reverseBits(harqProcessNum, harqProcessNumSize); + dlAssignmentIdx = reverseBits(dlAssignmentIdx , dlAssignmentIdxSize); + pucchTpc = reverseBits(pucchTpc, pucchTpcSize); + pucchResoInd = reverseBits(pucchResoInd, pucchResoIndSize); + harqFeedbackInd = reverseBits(harqFeedbackInd, harqFeedbackIndSize); - numBytes = dlDciPtr->payloadSizeBits / 8; - if(dlDciPtr->payloadSizeBits % 8) - numBytes += 1; - if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN) - { - DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected"); - return; - } + /* Calulating total number of bytes in buffer */ + dlDciPtr[dciIndex].payloadSizeBits = (dciFormatIdSize + freqDomResAssignSize\ + + timeDomResAssignSize + VRB2PRBMapSize + modNCodSchemeSize\ + + ndiSize + redundancyVerSize + harqProcessNumSize + dlAssignmentIdxSize\ + + pucchTpcSize + pucchResoIndSize + harqFeedbackIndSize); - /* Initialize buffer */ - for(bytePos = 0; bytePos < numBytes; bytePos++) - dlDciPtr->payload[bytePos] = 0; + numBytes = dlDciPtr[dciIndex].payloadSizeBits / 8; + if(dlDciPtr[dciIndex].payloadSizeBits % 8) + numBytes += 1; - bytePos = numBytes - 1; - bitPos = 0; + if(numBytes > FAPI_DCI_PAYLOAD_BYTE_LEN) + { + DU_LOG("\nERROR --> LWR_MAC : Total bytes for DCI is more than expected"); + return; + } - /* Packing DCI format fields */ - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - dciFormatId, dciFormatIdSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - freqDomResAssign, freqDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - timeDomResAssign, timeDomResAssignSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - VRB2PRBMap, VRB2PRBMapSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - modNCodScheme, modNCodSchemeSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - ndi, ndiSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - redundancyVer, redundancyVerSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - redundancyVer, redundancyVerSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - harqProcessNum, harqProcessNumSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - dlAssignmentIdx, dlAssignmentIdxSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - pucchTpc, pucchTpcSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - pucchResoInd, pucchResoIndSize); - fillDlDciPayload(dlDciPtr->payload, &bytePos, &bitPos,\ - harqFeedbackInd, harqFeedbackIndSize); + /* Initialize buffer */ + for(bytePos = 0; bytePos < numBytes; bytePos++) + dlDciPtr[dciIndex].payload[bytePos] = 0; + + bytePos = numBytes - 1; + bitPos = 0; + + /* Packing DCI format fields */ + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + dciFormatId, dciFormatIdSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + freqDomResAssign, freqDomResAssignSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + timeDomResAssign, timeDomResAssignSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + VRB2PRBMap, VRB2PRBMapSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + modNCodScheme, modNCodSchemeSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + ndi, ndiSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + redundancyVer, redundancyVerSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + redundancyVer, redundancyVerSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + harqProcessNum, harqProcessNumSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + dlAssignmentIdx, dlAssignmentIdxSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + pucchTpc, pucchTpcSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + pucchResoInd, pucchResoIndSize); + fillDlDciPayload(dlDciPtr[dciIndex].payload, &bytePos, &bitPos,\ + harqFeedbackInd, harqFeedbackIndSize); + } } } @@ -3168,6 +3172,8 @@ void fillPagePdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_pdu_t *dlTtiVendorPdu, MacDlSlot *dlSlot, int8_t dlMsgSchInfoIdx, \ RntiType rntiType, uint8_t coreSetType, uint8_t ueIdx) { + uint8_t dciIndex = 0; + if(dlTtiReqPdu != NULLP) { PdcchCfg *pdcchInfo = NULLP; @@ -3198,7 +3204,7 @@ uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_ DU_LOG("\nERROR --> LWR_MAC: Failed filling PDCCH Pdu"); return RFAILED; } - + dlTtiReqPdu->pduType = PDCCH_PDU_TYPE; dlTtiReqPdu->pdu.pdcch_pdu.bwpSize = bwp->freqAlloc.numPrb; dlTtiReqPdu->pdu.pdcch_pdu.bwpStart = bwp->freqAlloc.startPrb; @@ -3208,7 +3214,7 @@ uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_ dlTtiReqPdu->pdu.pdcch_pdu.startSymbolIndex = pdcchInfo->coresetCfg.startSymbolIndex; dlTtiReqPdu->pdu.pdcch_pdu.durationSymbols = pdcchInfo->coresetCfg.durationSymbols; convertFreqDomRsrcMapToIAPIFormat(pdcchInfo->coresetCfg.freqDomainResource,\ - dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource); + dlTtiReqPdu->pdu.pdcch_pdu.freqDomainResource); dlTtiReqPdu->pdu.pdcch_pdu.cceRegMappingType = pdcchInfo->coresetCfg.cceRegMappingType; dlTtiReqPdu->pdu.pdcch_pdu.regBundleSize = pdcchInfo->coresetCfg.regBundleSize; dlTtiReqPdu->pdu.pdcch_pdu.interleaverSize = pdcchInfo->coresetCfg.interleaverSize; @@ -3224,8 +3230,11 @@ uint8_t fillPdcchPdu(fapi_dl_tti_req_pdu_t *dlTtiReqPdu, fapi_vendor_dl_tti_req_ dlTtiVendorPdu->pdu_type = FAPI_PDCCH_PDU_TYPE; dlTtiVendorPdu->pdu_size = sizeof(fapi_vendor_dl_pdcch_pdu_t); dlTtiVendorPdu->pdu.pdcch_pdu.num_dl_dci = dlTtiReqPdu->pdu.pdcch_pdu.numDlDci; - dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_pdcch_to_ssb = 0; - dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[0].epre_ratio_of_dmrs_to_ssb = 0; + for(dciIndex = 0; dciIndex < dlTtiReqPdu->pdu.pdcch_pdu.numDlDci; dciIndex++) + { + dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[dciIndex].epre_ratio_of_pdcch_to_ssb = 0; + dlTtiVendorPdu->pdu.pdcch_pdu.dl_dci[dciIndex].epre_ratio_of_dmrs_to_ssb = 0; + } } return ROK; @@ -3888,7 +3897,7 @@ uint16_t fillDlTtiReq(SlotTimingInfo currTimingInfo) /* PDSCH PDU */ fillPdschPdu(&dlTtiReq->pdus[numPduEncoded], &vendorMsg->p7_req_vendor.dl_tti_req.pdus[numPduEncoded], - &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci.pdschCfg, + &currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci[0].pdschCfg, currDlSlot->dlInfo.brdcstAlloc.sib1Alloc.bwp, pduIndex); dlTtiReq->ue_grp_info[dlTtiReq->nGroup].pduIdx[pduIndex] = pduIndex; @@ -4119,7 +4128,7 @@ uint16_t sendTxDataReq(SlotTimingInfo currTimingInfo, MacDlSlot *dlSlot, p_fapi_ if(dlSlot->dlInfo.brdcstAlloc.sib1TransmissionMode) { fillSib1TxDataReq(txDataReq->pdu_desc, pduIndex, &macCb.macCell[cellIdx]->macCellCfg, \ - &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci.pdschCfg); + &dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg->dci[0].pdschCfg); pduIndex++; MAC_FREE(dlSlot->dlInfo.brdcstAlloc.sib1Alloc.sib1PdcchCfg,sizeof(PdcchCfg)); txDataReq->num_pdus++; diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 1043e6de3..ebd0eafe8 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -665,21 +665,21 @@ uint8_t fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots,SchPdcchC pdcch->coresetCfg.shiftIndex = pci; pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */ pdcch->numDlDci = 1; - pdcch->dci.rnti = SI_RNTI; - pdcch->dci.scramblingId = pci; - pdcch->dci.scramblingRnti = 0; - pdcch->dci.cceIndex = 0; - pdcch->dci.aggregLevel = 4; - pdcch->dci.beamPdcchInfo.numPrgs = 1; - pdcch->dci.beamPdcchInfo.prgSize = 1; - pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; - pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; - pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.beta_pdcch_1_0= 0; - pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; + pdcch->dci[0].rnti = SI_RNTI; + pdcch->dci[0].scramblingId = pci; + pdcch->dci[0].scramblingRnti = 0; + pdcch->dci[0].cceIndex = 0; + pdcch->dci[0].aggregLevel = 4; + pdcch->dci[0].beamPdcchInfo.numPrgs = 1; + pdcch->dci[0].beamPdcchInfo.prgSize = 1; + pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci[0].txPdcchPower.beta_pdcch_1_0= 0; + pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0; /* Storing pdschCfg pointer here. Required to access pdsch config while fillig up pdcch pdu */ - pdsch = &pdcch->dci.pdschCfg; + pdsch = &pdcch->dci[0].pdschCfg; /* fill the PDSCH PDU */ uint8_t cwCount = 0; @@ -1297,7 +1297,7 @@ uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \ if(ssbOccasion && sib1Occasion) { broadcastPrbStart = cell->cellCfg.dlCfgCommon.schFreqInfoDlSib.offsetToPointA; - broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB + cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.numPrb -1; + broadcastPrbEnd = broadcastPrbStart + SCH_SSB_NUM_PRB + cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.numPrb -1; } else if(ssbOccasion) { @@ -1306,8 +1306,8 @@ uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, \ } else if(sib1Occasion) { - broadcastPrbStart = cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.startPrb; - broadcastPrbEnd = broadcastPrbStart + cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.numPrb -1; + broadcastPrbStart = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.startPrb; + broadcastPrbEnd = broadcastPrbStart + cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.numPrb -1; } /* Iterate through all free PRB blocks */ @@ -1583,7 +1583,7 @@ uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_ { reservedPrbStart = cell->cellCfg.dlCfgCommon.schFreqInfoDlSib.offsetToPointA; reservedPrbEnd = reservedPrbStart + SCH_SSB_NUM_PRB + \ - cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.numPrb -1; + cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.numPrb -1; } else if(ssbOccasion) { @@ -1592,8 +1592,8 @@ uint16_t searchLargestFreeBlock(SchCellCb *cell, SlotTimingInfo slotTime,uint16_ } else if(sib1Occasion) { - reservedPrbStart = cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.startPrb; - reservedPrbEnd = reservedPrbStart + cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc.numPrb -1; + reservedPrbStart = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.startPrb; + reservedPrbEnd = reservedPrbStart + cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc.numPrb -1; } else { diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 1e3f9c7ce..7ab06e4b2 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -314,6 +314,15 @@ typedef struct schPrbAlloc uint16_t numPrbAlloc; }SchPrbAlloc; + +typedef struct schPdcchAllocInfo +{ + uint8_t cRSetId; + uint8_t ssId; + uint8_t aggLvl; + uint16_t cceIndex; +}SchPdcchAllocInfo; + /** * @brief * scheduler allocationsfor DL per cell. @@ -772,15 +781,15 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, u uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId,bool isRetxMsg4, SchDlHqProcCb **hqP); uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index); bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool isRetx, SchDlHqProcCb **hqP); -uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti, -uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP); +uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti, uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc,\ + uint16_t startPRB, uint8_t pdschStartSymbol, uint8_t pdschNumSymbols,bool isRetx, SchDlHqProcCb* hqP, SchPdcchAllocInfo pdcchAllocInfo); uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueId, DlMsgSchInfo *msg4Alloc,\ uint8_t pdschStartSymbol, uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP); uint8_t allocatePrbDl(SchCellCb *cell, SlotTimingInfo slotTime, uint8_t startSymbol, uint8_t symbolLength, \ uint16_t *startPrb, uint16_t numPrb); void fillDlMsgInfo(DlMsgSchInfo *dlMsgInfo, uint16_t crnti, bool isRetx, SchDlHqProcCb* hqP); /*AS per 38.473 V15.3.0, Section 9.3.1.32 crnti value range is b/w 0..65535*/ -bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol,\ -uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP); +bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol, uint8_t *pdschSymblLen,\ + SlotTimingInfo *pdcchTime, SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP, SchPdcchAllocInfo *pdcchAllocInfo); RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, uint16_t numSlotsPerSystemFrame); /* UL scheduling related function declarations */ @@ -804,7 +813,7 @@ void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx, uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd); void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status); uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue); -bool schDlCandidateSelection(SchUeCb *ue, SlotTimingInfo slotTime); +bool schDlCandidateSelection(SchUeCb *ue, SlotTimingInfo slotTime, SchPdcchAllocInfo *pdcchAllocInfo); /*Paging Functions*/ void schProcPagingCfg(SchCellCb *cell); diff --git a/src/5gnrsch/sch_common.c b/src/5gnrsch/sch_common.c index d8c677fca..94156ae3a 100644 --- a/src/5gnrsch/sch_common.c +++ b/src/5gnrsch/sch_common.c @@ -139,9 +139,9 @@ uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcst } dlBrdcstAlloc->crnti = SI_RNTI; - dmrs = cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.dmrs; - freqAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschFreqAlloc; - timeAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci.pdschCfg.pdschTimeAlloc; + dmrs = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.dmrs; + freqAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschFreqAlloc; + timeAlloc = cell->sib1SchCfg.sib1PdcchCfg.dci[0].pdschCfg.pdschTimeAlloc; schDlSlotInfo = cell->schDlSlotInfo[slotTime.slot]; /* Find total symbols used including DMRS */ @@ -658,19 +658,19 @@ uint8_t schDlRsrcAllocMsg4(SchCellCb *cell, SlotTimingInfo msg4Time, uint8_t ueI pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId; pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */ pdcch->numDlDci = 1; - pdcch->dci.rnti = cell->raCb[ueId-1].tcrnti; - pdcch->dci.scramblingId = cell->cellCfg.phyCellId; - pdcch->dci.scramblingRnti = 0; - pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */ - pdcch->dci.aggregLevel = 4; - pdcch->dci.beamPdcchInfo.numPrgs = 1; - pdcch->dci.beamPdcchInfo.prgSize = 1; - pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; - pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; - pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; - pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; - pdsch = &pdcch->dci.pdschCfg; + pdcch->dci[0].rnti = cell->raCb[ueId-1].tcrnti; + pdcch->dci[0].scramblingId = cell->cellCfg.phyCellId; + pdcch->dci[0].scramblingRnti = 0; + pdcch->dci[0].cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */ + pdcch->dci[0].aggregLevel = 4; + pdcch->dci[0].beamPdcchInfo.numPrgs = 1; + pdcch->dci[0].beamPdcchInfo.prgSize = 1; + pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci[0].txPdcchPower.beta_pdcch_1_0 = 0; + pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0; + pdsch = &pdcch->dci[0].pdschCfg; /* fill the PDSCH PDU */ uint8_t cwCount = 0; @@ -816,9 +816,9 @@ uint16_t schAllocPucchResource(SchCellCb *cell, SlotTimingInfo pucchTime, uint16 * ****************************************************************/ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti, uint32_t tbSize, DlMsgSchInfo *dlMsgAlloc, uint16_t startPRB, uint8_t pdschStartSymbol, - uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP) + uint8_t pdschNumSymbols, bool isRetx, SchDlHqProcCb *hqP, SchPdcchAllocInfo pdcchAllocInfo) { - uint8_t ueId=0; + uint8_t ueId=0, ssIdx = 0, cRSetIdx = 0;; uint8_t cwCount = 0, rbgCount = 0, pdcchStartSymbol = 0; PdcchCfg *pdcch = NULLP; PdschCfg *pdsch = NULLP; @@ -840,8 +840,25 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c GET_UE_ID(crnti, ueId); ueCb = cell->ueCb[ueId-1]; - coreset1 = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.cRSetToAddModList[0]; - searchSpace = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.searchSpcToAddModList[0]; + + for(cRSetIdx = 0; cRSetIdx < ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.numCRsetToAddMod; cRSetIdx++) + { + if(ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.cRSetToAddModList[cRSetIdx].cRSetId\ + == pdcchAllocInfo.cRSetId) + { + coreset1 = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.cRSetToAddModList[cRSetIdx]; + break; + } + } + for(ssIdx = 0; ssIdx < ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.numSearchSpcToAddMod; ssIdx++) + { + if(ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.searchSpcToAddModList[ssIdx].searchSpaceId\ + == pdcchAllocInfo.ssId) + { + searchSpace = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdcchCfg.searchSpcToAddModList[ssIdx]; + break; + } + } pdschCfg = ueCb.ueCfg.spCellCfg.servCellRecfg.initDlBwp.pdschCfg; /* fill BWP */ @@ -881,25 +898,31 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId; pdcch->coresetCfg.precoderGranularity = coreset1.precoderGranularity; - pdcch->numDlDci = 1; - pdcch->dci.rnti = ueCb.crnti; - pdcch->dci.scramblingId = cell->cellCfg.phyCellId; - pdcch->dci.scramblingRnti = 0; + if(pdcch->numDlDci >= MAX_NUM_PDCCH) + { + DU_LOG("\nERROR --> SCH: MAX number of PDCCH allocted for this slot."); + return RFAILED; + } + pdcch->dci[pdcch->numDlDci].rnti = ueCb.crnti; + pdcch->dci[pdcch->numDlDci].scramblingId = cell->cellCfg.phyCellId; + pdcch->dci[pdcch->numDlDci].scramblingRnti = 0; /*TODO below assumptions of CCE Index is wrong: * Range 0 to 135 as per ORAN.WG8.AAD Table 9-35 CORESET configuration and * it has to be calculated using the formula given in 3GPP TS 38.213, Sec 10.1 */ - pdcch->dci.cceIndex = 0; /* 0-3 for UL and 4-7 for DL */ - pdcch->dci.aggregLevel = 4; - pdcch->dci.beamPdcchInfo.numPrgs = 1; - pdcch->dci.beamPdcchInfo.prgSize = 1; - pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; - pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; - pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; - pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; - - pdsch = &pdcch->dci.pdschCfg; + pdcch->dci[pdcch->numDlDci].cceIndex = pdcchAllocInfo.cceIndex; + pdcch->dci[pdcch->numDlDci].aggregLevel = pdcchAllocInfo.aggLvl; + pdcch->dci[pdcch->numDlDci].beamPdcchInfo.numPrgs = 1; + pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prgSize = 1; + pdcch->dci[pdcch->numDlDci].beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci[pdcch->numDlDci].beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci[pdcch->numDlDci].txPdcchPower.beta_pdcch_1_0 = 0; + pdcch->dci[pdcch->numDlDci].txPdcchPower.powerControlOffsetSS = 0; + + pdsch = &pdcch->dci[pdcch->numDlDci].pdschCfg; + pdcch->numDlDci++; + pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */ pdsch->rnti = ueCb.crnti; pdsch->pduIndex = 0; @@ -959,7 +982,7 @@ uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t c /* Allocate the number of PRBs required for DL PDSCH */ if((allocatePrbDl(cell, slotTime, startSymbol, numSymbol,\ - &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK) + &pdsch->pdschFreqAlloc.startPrb, pdsch->pdschFreqAlloc.numPrb)) != ROK) { DU_LOG("\nERROR --> SCH : allocatePrbDl() failed for DL MSG"); SCH_FREE(dlMsgAlloc->dlMsgPdcchCfg, sizeof(PdcchCfg)); @@ -1797,7 +1820,7 @@ uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId } if(findValidK0K1Value(cell, currTime, ueId, false, &pdschStartSymbol, &pdschNumSymbols, &pdcchTime, &pdschTime,\ - &pucchTime, isRetxMsg4, *msg4HqProc) != true ) + &pucchTime, isRetxMsg4, *msg4HqProc, NULLP) != true ) { DU_LOG("\nERROR --> SCH: schProcessMsg4Req() : k0 k1 not found"); return RFAILED; @@ -1843,7 +1866,7 @@ uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP; return RFAILED; } - memcpy(dciSlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci.pdschCfg, sizeof(PdschCfg)); + memcpy(dciSlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg)); } else { @@ -1874,7 +1897,7 @@ uint8_t schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId SCH_ALLOC(msg4SlotAlloc->dlMsgPdschCfg, sizeof(PdschCfg)); if(msg4SlotAlloc->dlMsgPdschCfg) { - memcpy(msg4SlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci.pdschCfg, sizeof(PdschCfg)); + memcpy(msg4SlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg)); } else { @@ -2525,7 +2548,7 @@ bool schCheckPdcchAvail(SchCellCb *cellCb, SlotTimingInfo slotTime, uint8_t cceI * [RETURN]: isPDCCHAllocted flag(true = UE can be selected as a * candidate ) * */ -bool schDlCandidateSelection(SchUeCb *ueCb, SlotTimingInfo pdcchTime) +bool schDlCandidateSelection(SchUeCb *ueCb, SlotTimingInfo pdcchTime, SchPdcchAllocInfo *pdcchAllocInfo) { uint8_t cRSetIdx = 0, cceIndex = 0; uint8_t cqi = 0, candIdx = 0; @@ -2582,6 +2605,10 @@ bool schDlCandidateSelection(SchUeCb *ueCb, SlotTimingInfo pdcchTime) if(schCheckPdcchAvail(ueCb->cellCb, pdcchTime, cceIndex, pdcchInfo,nextLowerAggLvl) == true) { DU_LOG("\nINFO --> SCH: PDCCH allocation is successful at cceIndex:%d",cceIndex); + pdcchAllocInfo->cRSetId = pdcchInfo->cRSetRef->cRSetId; + pdcchAllocInfo->aggLvl = nextLowerAggLvl; + pdcchAllocInfo->cceIndex = cceIndex; + pdcchAllocInfo->ssId = pdcchInfo->ssRef->searchSpaceId; return true; } } diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c index e4f6fb468..de3a6e473 100644 --- a/src/5gnrsch/sch_rach.c +++ b/src/5gnrsch/sch_rach.c @@ -731,7 +731,7 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin SCH_ALLOC(dciSlotAlloc->rarPdschCfg, sizeof(PdschCfg)); if(dciSlotAlloc->rarPdschCfg) { - memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg, sizeof(PdschCfg)); + memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg)); } else { @@ -766,7 +766,7 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin SCH_ALLOC(rarSlotAlloc->rarPdschCfg, sizeof(PdschCfg)); if(rarSlotAlloc->rarPdschCfg) { - memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg,sizeof(PdschCfg)); + memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg,sizeof(PdschCfg)); } else { @@ -945,20 +945,20 @@ uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAl pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId; pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */ pdcch->numDlDci = 1; - pdcch->dci.rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */ - pdcch->dci.scramblingId = cell->cellCfg.phyCellId; - pdcch->dci.scramblingRnti = 0; - pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */ - pdcch->dci.aggregLevel = 4; - pdcch->dci.beamPdcchInfo.numPrgs = 1; - pdcch->dci.beamPdcchInfo.prgSize = 1; - pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; - pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; - pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0; - pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; - - pdsch = &pdcch->dci.pdschCfg; + pdcch->dci[0].rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */ + pdcch->dci[0].scramblingId = cell->cellCfg.phyCellId; + pdcch->dci[0].scramblingRnti = 0; + pdcch->dci[0].cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */ + pdcch->dci[0].aggregLevel = 4; + pdcch->dci[0].beamPdcchInfo.numPrgs = 1; + pdcch->dci[0].beamPdcchInfo.prgSize = 1; + pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci[0].txPdcchPower.beta_pdcch_1_0 = 0; + pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0; + + pdsch = &pdcch->dci[0].pdschCfg; /* fill the PDSCH PDU */ uint8_t cwCount = 0; pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */ diff --git a/src/5gnrsch/sch_slot_ind.c b/src/5gnrsch/sch_slot_ind.c index 4830bd17f..0e2c7f1a1 100644 --- a/src/5gnrsch/sch_slot_ind.c +++ b/src/5gnrsch/sch_slot_ind.c @@ -100,6 +100,7 @@ bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t SchUeCb *ueCb = NULLP; DlMsgSchInfo *dciSlotAlloc, *dlMsgAlloc; SlotTimingInfo pdcchTime, pdschTime, pucchTime; + SchPdcchAllocInfo pdcchAllocInfo; GET_CRNTI(crnti,ueId); ueCb = &cell->ueCb[ueId-1]; @@ -112,8 +113,10 @@ bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t } } + memset(&pdcchAllocInfo,0,sizeof(SchPdcchAllocInfo)); if(findValidK0K1Value(cell, currTime, ueId, ueCb->k0K1TblPrsnt,\ - &pdschStartSymbol, &pdschNumSymbols, &pdcchTime, &pdschTime, &pucchTime, isRetx, *hqP) != true ) + &pdschStartSymbol, &pdschNumSymbols, &pdcchTime, &pdschTime, \ + &pucchTime, isRetx, *hqP, &pdcchAllocInfo) != true ) { /* If a valid combination of slots to scheduled PDCCH, PDSCH and PUCCH is * not found, do not perform resource allocation. Return from here. */ @@ -148,7 +151,8 @@ bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t return false; /*[Step6]: pdcch and pdsch data is filled */ - if((schDlRsrcAllocDlMsg(cell, pdschTime, crnti, accumalatedSize, dciSlotAlloc, startPrb, pdschStartSymbol, pdschNumSymbols, isRetx, *hqP)) != ROK) + if((schDlRsrcAllocDlMsg(cell, pdschTime, crnti, accumalatedSize, dciSlotAlloc, startPrb,\ + pdschStartSymbol, pdschNumSymbols, isRetx, *hqP, pdcchAllocInfo)) != ROK) { DU_LOG("\nERROR --> SCH : Scheduling of DL dedicated message failed"); @@ -187,7 +191,8 @@ bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t cell->schDlSlotInfo[pdcchTime.slot]->dlMsgAlloc[ueId-1] = NULLP; return false; } - memcpy(dciSlotAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci.pdschCfg, sizeof(PdschCfg)); + memcpy(dciSlotAlloc->dlMsgPdschCfg,\ + &dciSlotAlloc->dlMsgPdcchCfg->dci[dciSlotAlloc->dlMsgPdcchCfg->numDlDci - 1].pdschCfg, sizeof(PdschCfg)); } else { @@ -218,7 +223,8 @@ bool schFillBoGrantDlSchedInfo(SchCellCb *cell, SlotTimingInfo currTime, uint8_t SCH_ALLOC(dlMsgAlloc->dlMsgPdschCfg, sizeof(PdschCfg)); if(dlMsgAlloc->dlMsgPdschCfg) { - memcpy(dlMsgAlloc->dlMsgPdschCfg, &dciSlotAlloc->dlMsgPdcchCfg->dci.pdschCfg, sizeof(PdschCfg)); + memcpy(dlMsgAlloc->dlMsgPdschCfg,\ + &dciSlotAlloc->dlMsgPdcchCfg->dci[dciSlotAlloc->dlMsgPdcchCfg->numDlDci - 1].pdschCfg, sizeof(PdschCfg)); } else { @@ -412,7 +418,8 @@ PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime) *******************************************************************/ bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, bool dedMsg, uint8_t *pdschStartSymbol, uint8_t *pdschSymblLen, SlotTimingInfo *pdcchTime, - SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP) + SlotTimingInfo *pdschTime, SlotTimingInfo *pucchTime, bool isRetx, SchDlHqProcCb *hqP, + SchPdcchAllocInfo *pdcchAllocInfo) { uint8_t numK0 = 0, k0TblIdx = 0, k0Val = 0, k0Index =0 ; uint8_t k1TblIdx = 0, k1Index = 0, k1Val = 0, numK1 = 0; @@ -432,7 +439,7 @@ bool findValidK0K1Value(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId, { ueCb = &cell->ueCb[ueId-1]; k0K1InfoTbl = &ueCb->k0K1InfoTbl; - if(schDlCandidateSelection(ueCb, *pdcchTime) == false) + if(schDlCandidateSelection(ueCb, *pdcchTime, pdcchAllocInfo) == false) { DU_LOG("\nDEBUG --> SCH: DL candidate Selection failed bcz PDCCH is unavailable for this slot"); return false; @@ -590,8 +597,8 @@ uint8_t schProcDlPageAlloc(SchCellCb *cell, SlotTimingInfo currTime, Inst schIns dlPageAlloc.pageDlDci.cceReg.interleaved.interleaverSize = cell->sib1SchCfg.sib1PdcchCfg.coresetCfg.interleaverSize; dlPageAlloc.pageDlDci.cceReg.interleaved.shiftIndex = cell->sib1SchCfg.sib1PdcchCfg.coresetCfg.shiftIndex; dlPageAlloc.pageDlDci.ssStartSymbolIndex = cell->sib1SchCfg.sib1PdcchCfg.coresetCfg.startSymbolIndex; - dlPageAlloc.pageDlDci.cceIndex = cell->sib1SchCfg.sib1PdcchCfg.dci.cceIndex; - dlPageAlloc.pageDlDci.aggregLevel = cell->sib1SchCfg.sib1PdcchCfg.dci.aggregLevel; + dlPageAlloc.pageDlDci.cceIndex = cell->sib1SchCfg.sib1PdcchCfg.dci[0].cceIndex; + dlPageAlloc.pageDlDci.aggregLevel = cell->sib1SchCfg.sib1PdcchCfg.dci[0].aggregLevel; dlPageAlloc.pageDlDci.precoderGranularity = cell->sib1SchCfg.sib1PdcchCfg.coresetCfg.precoderGranularity; dlPageAlloc.pageDlDci.coreSetSize = cell->sib1SchCfg.sib1PdcchCfg.coresetCfg.coreSetSize; /*Fill BWP*/ diff --git a/src/cm/mac_sch_interface.h b/src/cm/mac_sch_interface.h index 4166a8e9c..52591b69b 100644 --- a/src/cm/mac_sch_interface.h +++ b/src/cm/mac_sch_interface.h @@ -123,6 +123,13 @@ #define MAX_PHR_REPORT 1 /*TODO: Range of PHR reports in multiple PHR.*/ #define MAX_FAILURE_DET_RESOURCES 10 /*Spec 38.331 'maxNrofFailureDetectionResources'*/ +/*As per SCF222_5GFAPI, 'MaxDciPerSlot' defines this value but this parameter value is missing in Spec.*/ +#ifdef INTEL_FAPI + #define MAX_NUM_PDCCH 1 +#else + #define MAX_NUM_PDCCH 2 +#endif + #define ADD_DELTA_TO_TIME(crntTime, toFill, incr, numOfSlot) \ { \ if ((crntTime.slot + incr) > (numOfSlot - 1)) \ @@ -617,7 +624,7 @@ typedef struct pdcchCfg /* coreset-0 configuration */ CoresetCfg coresetCfg; uint16_t numDlDci; - DlDCI dci; /* as of now its only one DCI, later it will be numDlCi */ + DlDCI dci[MAX_NUM_PDCCH]; } PdcchCfg; /* end of SIB1 PDCCH structures */