From: Sphoorthi Dayanand Date: Thu, 15 Apr 2021 13:08:57 +0000 (+0000) Subject: Merge "JIRA ID - ODUHIGH-324 Resource allocation for SIB1" X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=d74291a3d7dadc783460e134b0e24f2b9ae07b2a;hp=961451a0bce182239c9e0b07541ab4c43552b4d9;p=o-du%2Fl2.git Merge "JIRA ID - ODUHIGH-324 Resource allocation for SIB1" --- diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 9c10ceb41..5c8d88993 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -704,7 +704,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) * uint8_t offsetPointA : offset * @return void **/ -void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) +void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; @@ -720,6 +720,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint8_t FreqDomainResource[6] = {0}; uint16_t tbSize = 0; uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ + uint8_t ssbIdx = 0; PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); @@ -745,7 +746,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe * assuming u = 0, i = 0, numSlotsPerSubframe = 10 * Also, from this configuration, coreset0 is only on even subframe */ - slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots; + slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots; sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ @@ -831,7 +832,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ @@ -876,7 +877,7 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots, + fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index c8863994a..4ca3bc636 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -25,7 +25,11 @@ #define SCH_MU3_NUM_SLOTS 40 #define SCH_MU4_NUM_SLOTS 50 #define SCH_MAX_SFN 1024 -#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */ +#ifdef NR_TDD +#define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */ +#else +#define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */ +#endif #define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */ #define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */ #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */ diff --git a/src/5gnrsch/sch_utils.c b/src/5gnrsch/sch_utils.c index 3b9ef66b7..4cb93c66f 100644 --- a/src/5gnrsch/sch_utils.c +++ b/src/5gnrsch/sch_utils.c @@ -44,7 +44,30 @@ #include "sch_utils.h" #include "math.h" -/* spec-38.213 Table 13-1 */ +#ifdef NR_TDD +/* spec-38.213 Table 13-4 for SCS=30KHz */ +/* Note: Picking Table 13-4 and not 13-6 since band supported is n78 and + * corresponding minimum B/W is 10 MHz */ +int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = { +{ 1, 24, 2, 0}, /* index 0 */ +{ 1, 24, 2, 1}, /* index 1 */ +{ 1, 24, 2, 2}, /* index 2 */ +{ 1, 24, 2, 3}, /* index 3 */ +{ 1, 24, 2, 4}, /* index 4 */ +{ 1, 24, 3, 0}, /* index 5 */ +{ 1, 24, 3, 1}, /* index 6 */ +{ 1, 24, 3, 2}, /* index 7 */ +{ 1, 24, 3, 3}, /* index 8 */ +{ 1, 24, 3, 4}, /* index 9 */ +{ 1, 48, 1, 12}, /* index 10 */ +{ 1, 48, 1, 14}, /* index 11 */ +{ 1, 48, 1, 16}, /* index 12 */ +{ 1, 48, 2, 12}, /* index 13 */ +{ 1, 48, 2, 14}, /* index 14 */ +{ 1, 48, 2, 16}, /* index 15 */ +}; +#else +/* spec-38.213 Table 13-1 for SCS=15KHz */ int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = { { 1, 24, 2, 0}, /* index 0 */ { 1, 24, 2, 2}, /* index 1 */ @@ -63,6 +86,7 @@ int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = { { 1, 96, 3, 38}, /* index 14 */ { 0, 0, 0, 0}, /* index 15 */ }; +#endif /* spec-38.213 Table 13-11 */ /* m value is scaled to 2, when using it in formula, divide by 2 */ @@ -514,8 +538,8 @@ uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols) tbSize = tbSize * 8; //Calculate tbSize in bits - /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 * - * Ninfo = Nre . R . Qm . v * + /* formula used for calculation of rbSize, 38.214 section 5.1.3.2 * + * Ninfo = S . Nre . R . Qm . v * * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh * * Nre = min(156,Nre') . nPrb */ @@ -647,6 +671,14 @@ void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo) { memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo)); } +#if 0 + //make allocation for SSB + if(cell->firstSsbTransmitted) + { + //TODO check if this slot and sfn are for ssb + + } +#endif } #ifdef NR_TDD diff --git a/src/du_app/du_cfg.c b/src/du_app/du_cfg.c index e94e1f0e0..f4da32f30 100644 --- a/src/du_app/du_cfg.c +++ b/src/du_app/du_cfg.c @@ -619,8 +619,12 @@ uint8_t readCfg() /* Mib Params */ mib.sysFrmNum = SYS_FRAME_NUM; +#ifdef NR_TDD + mib.subCarrierSpacingCommon = MIB__subCarrierSpacingCommon_scs30or120; +#else mib.subCarrierSpacingCommon = MIB__subCarrierSpacingCommon_scs15or60; - mib.ssb_SubcarrierOffset = SSB_SC_OFFSET; +#endif + mib.ssb_SubcarrierOffset = SSB_SC_OFFSET; //Kssb mib.dmrs_TypeA_Position = MIB__dmrs_TypeA_Position_pos2; mib.controlResourceSetZero = CORESET_0_INDEX; mib.searchSpaceZero = SEARCHSPACE_0_INDEX;