From: sphoorthi Date: Thu, 24 Dec 2020 08:47:04 +0000 (+0530) Subject: Changes to make number of slots and BW generic X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=cad4905437d02b16c3916903a42f501eb8f7b1ac;hp=15c1e4f846f9935150615a5e9e7f94500bd62790;p=o-du%2Fl2.git Changes to make number of slots and BW generic Change-Id: I68f676939366766e0f783f46d4d8bf5320887af2 Signed-off-by: sphoorthi --- diff --git a/Dockerfile b/Dockerfile index ddb9446f2..ee130dcb7 100644 --- a/Dockerfile +++ b/Dockerfile @@ -1,4 +1,4 @@ -FROM nexus3.o-ran-sc.org:10004/o-ran-sc/bldr-ubuntu18-c-go:9-u18.04 as ubuntu +FROM nexus3.o-ran-sc.org:10002/o-ran-sc/bldr-ubuntu18-c-go:1.9.0 # ====================================================================== # add netconf user diff --git a/Dockerfile-cu-stub b/Dockerfile-cu-stub index 1e0796aa9..e1efcd59d 100644 --- a/Dockerfile-cu-stub +++ b/Dockerfile-cu-stub @@ -1,4 +1,4 @@ -FROM nexus3.o-ran-sc.org:10004/o-ran-sc/bldr-ubuntu18-c-go:9-u18.04 as ubuntu +FROM nexus3.o-ran-sc.org:10002/o-ran-sc/bldr-ubuntu18-c-go:1.9.0 ADD . /opt/o-du-l2 WORKDIR /opt/o-du-l2 diff --git a/src/5gnrmac/mac_cfg_hdl.c b/src/5gnrmac/mac_cfg_hdl.c index 25b783ba4..41e82c937 100644 --- a/src/5gnrmac/mac_cfg_hdl.c +++ b/src/5gnrmac/mac_cfg_hdl.c @@ -199,6 +199,7 @@ uint8_t MacSchCellCfgReq(Pst *pst, MacCellCfg *macCellCfg) schCellCfg.cellId = macCellCfg->cellId; schCellCfg.phyCellId = macCellCfg->phyCellId; schCellCfg.bandwidth = macCellCfg->dlCarrCfg.bw; + schCellCfg.numerology = macCellCfg->numerology; schCellCfg.dupMode = macCellCfg->dupType; /* fill ssb scheduler parameters */ diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 1b1daed42..c4cc663d8 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -200,12 +200,12 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) if(pst->dstInst < SCH_INST_START) { - DU_LOG("\nInvalid inst ID"); - DU_LOG("\nSchProcGenCfgReq(): " + DU_LOG("\nERROR --> SCH : Invalid inst ID"); + DU_LOG("\nERROR --> SCH : SchProcGenCfgReq(): " "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START); return ROK; } - printf("\nReceived scheduler gen config"); + printf("\nSCH : Received scheduler gen config"); /* Fill the post structure for sending the confirmation */ memset(&cfmPst, 0 , sizeof(Pst)); SchFillCfmPst(pst, &cfmPst, cfg); @@ -226,7 +226,7 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) default: ret = LCM_PRIM_NOK; reason = LCM_REASON_INVALID_ELMNT; - DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt); + DU_LOG("\nERROR --> SCH : Invalid Elmnt=%d", cfg->hdr.elmId.elmnt); break; } @@ -288,7 +288,7 @@ uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd) uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd) { Inst inst = pst->dstInst-SCH_INST_START; - DU_LOG("\nSCH : Received Rach indication"); + DU_LOG("\nINFO --> SCH : Received Rach indication"); schProcessRachInd(rachInd, inst); return ROK; } @@ -315,13 +315,13 @@ uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd) switch(crcInd->crcInd[0]) { case CRC_FAILED: - DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]"); + DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [FAILURE]"); break; case CRC_PASSED: - DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]"); + DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [PASS]"); break; default: - DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]); + DU_LOG("\nDEBUG --> SCH : Invalid CRC state %d", crcInd->crcInd[0]); return RFAILED; } return ROK; @@ -349,24 +349,58 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) SCH_ALLOC(cell, sizeof(SchCellCb)); if(!cell) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } cell->cellId = schCellCfg->cellId; cell->instIdx = inst; - switch(schCellCfg->ssbSchCfg.scsCommon) + switch(schCellCfg->numerology) { - case SCH_SCS_15KHZ: + case SCH_NUMEROLOGY_0: + { + cell->numSlots = SCH_MU0_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_1: + { + cell->numSlots = SCH_MU1_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_2: + { + cell->numSlots = SCH_MU2_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_3: + { + cell->numSlots = SCH_MU3_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_4: { - cell->numSlots = SCH_NUM_SLOTS; + cell->numSlots = SCH_MU4_NUM_SLOTS; } break; default: - DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon); + DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology); } - for(uint8_t idx=0; idxschDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*)); + if(!cell->schDlSlotInfo) + { + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schDlSlotInfo"); + return RFAILED; + } + + SCH_ALLOC(cell->schUlSlotInfo, cell->numSlots * sizeof(SchUlSlotInfo*)); + if(!cell->schUlSlotInfo) + { + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schUlSlotInfo"); + return RFAILED; + } + + for(uint8_t idx=0; idxnumSlots; idx++) { SchDlSlotInfo *schDlSlotInfo; SchUlSlotInfo *schUlSlotInfo; @@ -375,7 +409,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo)); if(!schDlSlotInfo) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } @@ -383,7 +417,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo)); if(!schUlSlotInfo) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } @@ -396,7 +430,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) } schCb[inst].cells[inst] = cell; - DU_LOG("\nCell init completed for cellId:%d", cell->cellId); + DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId); return ROK; } @@ -410,14 +444,14 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) * * Fill SIB1 configuration * - * @param[in] Inst schInst : scheduler instance + * @param[in] uint8_t bandwidth : total available bandwidth + * uint8_t numSlots : total slots per SFN * SchSib1Cfg *sib1SchCfg : cfg to be filled * uint16_t pci : physical cell Id * uint8_t offsetPointA : offset * @return void **/ -void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ - uint8_t offsetPointA) +void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; @@ -458,14 +492,29 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe * assuming u = 0, i = 0, numSlotsPerSubframe = 10 * Also, from this configuration, coreset0 is only on even subframe */ - slotIndex = ((oValue * 1) + (0 * mValue)) % 10; + slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots; sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); /* fill BWP */ - bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */ + switch(bandwidth) + { + case BANDWIDTH_20MHZ: + { + bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0; + } + break; + case BANDWIDTH_100MHZ: + { + bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1; + } + break; + default: + DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth); + + } bwp->freqAlloc.startPrb = 0; bwp->subcarrierSpacing = 0; /* 15Khz */ bwp->cyclicPrefix = 0; /* normal */ @@ -578,13 +627,13 @@ void fillSsbStartSymb(SchCellCb *cellCb) for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); } memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); @@ -619,10 +668,8 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg( - inst, - &(schCellCfg->sib1SchCfg), - schCellCfg->phyCellId, + fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots, + &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); @@ -670,7 +717,7 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) SchDlSlotInfo *schDlSlotInfo = NULLP; Inst inst = pst->dstInst-SCH_INST_START; - DU_LOG("\nSCH : Received RLC BO Status indication"); + DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication"); cell = schCb[inst].cells[inst]; GET_UE_IDX(dlBoInfo->crnti, ueIdx); @@ -685,17 +732,17 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) } else if(lcId != SRB0_LCID) { - DU_LOG("\nSCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId); + DU_LOG("\nERROR --> SCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId); return RFAILED; } - slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % SCH_NUM_SLOTS; + slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % cell->numSlots; schDlSlotInfo = cell->schDlSlotInfo[slot]; SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo)); if(!schDlSlotInfo->dlMsgInfo) { - DU_LOG("\nSCH : Memory allocation failed for dlMsgInfo"); + DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo"); schDlSlotInfo = NULL; return RFAILED; } @@ -737,7 +784,7 @@ uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd) SchUeCb *ueCb = NULLP; uint8_t lcgIdx; - DU_LOG("\nSCH : Received BSR"); + DU_LOG("\nDEBUG --> SCH : Received BSR"); cellCb = schCb[schInst].cells[schInst]; ueCb = schGetUeCb(cellCb, bsrInd->crnti); @@ -774,7 +821,7 @@ uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd) SchUeCb *ueCb; SchCellCb *cellCb = schCb[inst].cells[inst]; - DU_LOG("\nSCH : Received SR"); + DU_LOG("\nDEBUG --> SCH : Received SR"); ueCb = schGetUeCb(cellCb, uciInd->crnti); diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 3621feeeb..8734f65cf 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -19,7 +19,11 @@ /* macros */ #define SCH_INST_START 1 #define SCH_MAX_INST 1 -#define SCH_NUM_SLOTS 10 /*forcing this to 10 */ +#define SCH_MU0_NUM_SLOTS 10 +#define SCH_MU1_NUM_SLOTS 20 +#define SCH_MU2_NUM_SLOTS 30 +#define SCH_MU3_NUM_SLOTS 40 +#define SCH_MU4_NUM_SLOTS 50 #define SCH_MAX_SFN 1024 #define MAX_NUM_RB 106 /* value for numerology 0 15Khz */ #define SCH_MIB_TRANS 80 @@ -51,6 +55,15 @@ typedef struct schCellCb SchCellCb; typedef struct schUeCb SchUeCb; +typedef enum +{ + SCH_NUMEROLOGY_0, + SCH_NUMEROLOGY_1, + SCH_NUMEROLOGY_2, + SCH_NUMEROLOGY_3, + SCH_NUMEROLOGY_4 +}SchNumerology; + typedef enum { SCH_UE_STATE_INACTIVE, @@ -184,15 +197,15 @@ typedef struct schCellCb Inst macInst; /*!< Index of the MAC instance */ uint8_t numSlots; /*!< Number of slots in current frame */ SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/ - SchDlSlotInfo *schDlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in DL */ - SchUlSlotInfo *schUlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in UL */ + SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */ + SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */ SchCellCfg cellCfg; /*!< Cell ocnfiguration */ uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!numSlots; SchUlSlotInfo *schUlSlotInfo = NULLP; schUlSlotInfo = cell->schUlSlotInfo[pucchSlot]; diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c index d9ed2d399..3db381636 100644 --- a/src/5gnrsch/sch_rach.c +++ b/src/5gnrsch/sch_rach.c @@ -132,7 +132,7 @@ uint8_t schAllocMsg3Pusch(Inst schInst, uint16_t slot, uint16_t crnti, \ /* Slot allocation for msg3 based on 38.214 section 6.1.2.1 */ msg3SlotAlloc = slot + k2 + delta; - msg3SlotAlloc = msg3SlotAlloc % SCH_NUM_SLOTS; + msg3SlotAlloc = msg3SlotAlloc % cell->numSlots; startRb = cell->schUlSlotInfo[msg3SlotAlloc]->puschCurrentPrb; tbSize = schCalcTbSize(8); /* 6 bytes msg3 and 2 bytes header */ @@ -206,7 +206,7 @@ uint8_t schProcessRachInd(RachIndInfo *rachInd, Inst schInst) uint8_t ret = ROK; /* RAR will sent with a delay of RAR_DELAY */ - rarSlot = (rachInd->timingInfo.slot+RAR_DELAY+PHY_DELTA)%SCH_NUM_SLOTS; + rarSlot = (rachInd->timingInfo.slot+RAR_DELAY+PHY_DELTA)%cell->numSlots; SchDlSlotInfo *schDlSlotInfo = cell->schDlSlotInfo[rarSlot]; /* RAR will sent in the next slot */ diff --git a/src/5gnrsch/sch_slot_ind.c b/src/5gnrsch/sch_slot_ind.c index 9579bec54..bd3e642a2 100644 --- a/src/5gnrsch/sch_slot_ind.c +++ b/src/5gnrsch/sch_slot_ind.c @@ -240,8 +240,8 @@ uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst schInst) memcpy(&cell->slotInfo, slotInd, sizeof(SlotIndInfo)); dlBrdcstAlloc->ssbIdxSupported = 1; - sfnSlot = ((dlSchedInfo.schSlotValue.broadcastTime.sfn * 10) + - dlSchedInfo.schSlotValue.broadcastTime.slot); + sfnSlot = dlSchedInfo.schSlotValue.broadcastTime.sfn * cell->numSlots + + dlSchedInfo.schSlotValue.broadcastTime.slot; slot = dlSchedInfo.schSlotValue.currentTime.slot; diff --git a/src/5gnrsch/sch_ue_mgr.c b/src/5gnrsch/sch_ue_mgr.c index f21361d84..3e5001083 100644 --- a/src/5gnrsch/sch_ue_mgr.c +++ b/src/5gnrsch/sch_ue_mgr.c @@ -394,7 +394,7 @@ uint8_t schFillPuschAlloc(SchUeCb *ueCb, uint16_t pdcchSlot, uint32_t dataVol, S uint8_t startSymb = ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.puschCfg.timeDomRsrcAllocList[0].startSymbol; uint8_t symbLen = ueCb->ueCfg.spCellCfg.servCellCfg.initUlBwp.puschCfg.timeDomRsrcAllocList[0].symbolLength; - puschSlot = (pdcchSlot + k2) % SCH_NUM_SLOTS; + puschSlot = (pdcchSlot + k2) % cellCb->numSlots; startRb = cellCb->schUlSlotInfo[puschSlot]->puschCurrentPrb; tbSize = schCalcTbSize(dataVol + buffer); /* 2 bytes header + some buffer */ diff --git a/src/5gnrsch/sch_utils.c b/src/5gnrsch/sch_utils.c index a18df4810..9ecb73395 100644 --- a/src/5gnrsch/sch_utils.c +++ b/src/5gnrsch/sch_utils.c @@ -641,9 +641,8 @@ void schInitDlSlot(SchDlSlotInfo *schDlSlotInfo) { memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo)); } - - } + /********************************************************************** End of file **********************************************************************/ diff --git a/src/cm/common_def.h b/src/cm/common_def.h index 60a8ac903..0bd7491ab 100644 --- a/src/cm/common_def.h +++ b/src/cm/common_def.h @@ -80,6 +80,13 @@ #define FREQ_DOM_RSRC_SIZE 6 /* i.e. 6 bytes because Size of frequency domain resource is 45 bits */ +#define BANDWIDTH_20MHZ 20 +#define BANDWIDTH_100MHZ 100 + +/* PRB allocation as per 38.101, Section 5.3.2 */ +#define TOTAL_PRB_20MHZ_MU0 106 +#define TOTAL_PRB_100MHZ_MU1 273 + /* Defining macros for common utility functions */ #define ODU_GET_MSG_BUF SGetMsg #define ODU_PUT_MSG_BUF SPutMsg diff --git a/src/cm/du_app_mac_inf.h b/src/cm/du_app_mac_inf.h index 45db1b85e..acc2f6496 100644 --- a/src/cm/du_app_mac_inf.h +++ b/src/cm/du_app_mac_inf.h @@ -646,9 +646,10 @@ typedef struct bwpUlConfig typedef struct macCellCfg { - uint16_t cellId; /* Cell Id */ - uint8_t carrierId; /* Carrired Index */ - uint16_t phyCellId; /* Physical cell id */ + uint16_t cellId; /* Cell Id */ + uint8_t carrierId; /* Carrired Index */ + uint16_t phyCellId; /* Physical cell id */ + uint8_t numerology; /* Supported numerology */ DuplexMode dupType; /* Duplex type: TDD/FDD */ CarrierCfg dlCarrCfg; /* DL Carrier configuration */ CarrierCfg ulCarrCfg; /* UL Carrier configuration */ diff --git a/src/cm/mac_sch_interface.h b/src/cm/mac_sch_interface.h index a35bddd38..76145f9b4 100644 --- a/src/cm/mac_sch_interface.h +++ b/src/cm/mac_sch_interface.h @@ -622,16 +622,16 @@ typedef struct schBwpUlCfg typedef struct schCellCfg { - uint16_t cellId; /* Cell Id */ - uint16_t phyCellId; /* Physical cell id */ - uint8_t bandwidth; /* Supported B/W */ + uint16_t cellId; /* Cell Id */ + uint16_t phyCellId; /* Physical cell id */ + uint8_t bandwidth; /* Supported B/W */ + uint8_t numerology; /* Supported numerology */ SchDuplexMode dupMode; /* Duplex type: TDD/FDD */ - SchSsbCfg ssbSchCfg; /* SSB config */ - SchSib1Cfg sib1SchCfg; /* SIB1 config */ - SchRachCfg schRachCfg; /* PRACH config */ - SchBwpDlCfg schInitialDlBwp; /* Initial DL BWP */ - SchBwpUlCfg schInitialUlBwp; /* Initial UL BWP */ - uint8_t puschMu; /* PUSCH MU */ + SchSsbCfg ssbSchCfg; /* SSB config */ + SchSib1Cfg sib1SchCfg; /* SIB1 config */ + SchRachCfg schRachCfg; /* PRACH config */ + SchBwpDlCfg schInitialDlBwp; /* Initial DL BWP */ + SchBwpUlCfg schInitialUlBwp; /* Initial UL BWP */ }SchCellCfg; typedef struct schCellCfgCfm diff --git a/src/du_app/du_cfg.c b/src/du_app/du_cfg.c index 3d19355eb..d2c758c15 100644 --- a/src/du_app/du_cfg.c +++ b/src/du_app/du_cfg.c @@ -128,11 +128,12 @@ uint8_t readMacCfg() /* Cell configuration */ duCfgParam.macCellCfg.cellId = NR_CELL_ID; duCfgParam.macCellCfg.phyCellId = NR_PCI; + duCfgParam.macCellCfg.numerology = NR_NUMEROLOGY; duCfgParam.macCellCfg.dupType = DUPLEX_MODE; /* DL carrier configuration */ duCfgParam.macCellCfg.dlCarrCfg.pres = TRUE; - duCfgParam.macCellCfg.dlCarrCfg.bw = BANDWIDTH; + duCfgParam.macCellCfg.dlCarrCfg.bw = BANDWIDTH_20MHZ; duCfgParam.macCellCfg.dlCarrCfg.freq = NR_DL_ARFCN; duCfgParam.macCellCfg.dlCarrCfg.k0[0] = 1; duCfgParam.macCellCfg.dlCarrCfg.k0[1] = 1; @@ -148,7 +149,7 @@ uint8_t readMacCfg() /* UL Carrier configuration */ duCfgParam.macCellCfg.ulCarrCfg.pres = TRUE; - duCfgParam.macCellCfg.ulCarrCfg.bw = BANDWIDTH; + duCfgParam.macCellCfg.ulCarrCfg.bw = BANDWIDTH_20MHZ; duCfgParam.macCellCfg.ulCarrCfg.freq = NR_UL_ARFCN; duCfgParam.macCellCfg.ulCarrCfg.k0[0] = 1; duCfgParam.macCellCfg.ulCarrCfg.k0[1] = 1; @@ -243,7 +244,7 @@ uint8_t readMacCfg() /* fill Intial DL BWP */ duCfgParam.macCellCfg.initialDlBwp.bwp.firstPrb = 0; - duCfgParam.macCellCfg.initialDlBwp.bwp.numPrb = TOTAL_PRB_BW; /* configured to total BW */ + duCfgParam.macCellCfg.initialDlBwp.bwp.numPrb = TOTAL_PRB_20MHZ_MU0; /* configured to total BW */ duCfgParam.macCellCfg.initialDlBwp.bwp.scs = SUBCARRIER_SPACING; /* numerology is 0, 15Khz */ duCfgParam.macCellCfg.initialDlBwp.bwp.cyclicPrefix = NORMAL_CYCLIC_PREFIX; duCfgParam.macCellCfg.initialDlBwp.pdcchCommon.commonSearchSpace.searchSpaceId = SEARCHSPACE_1_INDEX; @@ -275,7 +276,7 @@ uint8_t readMacCfg() /* fill Intial UL BWP */ duCfgParam.macCellCfg.initialUlBwp.bwp.firstPrb = 0; - duCfgParam.macCellCfg.initialUlBwp.bwp.numPrb = TOTAL_PRB_BW; /* configured to total BW */ + duCfgParam.macCellCfg.initialUlBwp.bwp.numPrb = TOTAL_PRB_20MHZ_MU0; /* configured to total BW */ duCfgParam.macCellCfg.initialUlBwp.bwp.scs = SUBCARRIER_SPACING; /* numerology is 0, 15Khz */ duCfgParam.macCellCfg.initialUlBwp.bwp.cyclicPrefix = NORMAL_CYCLIC_PREFIX; duCfgParam.macCellCfg.initialUlBwp.puschCommon.k2 = PUSCH_K2; @@ -381,7 +382,7 @@ uint8_t fillServCellCfgCommSib(SrvCellCfgCommSib *srvCellCfgComm) srvCellCfgComm->dlCfg.offsetToPointA = OFFSET_TO_POINT_A; srvCellCfgComm->dlCfg.dlScsCarrier.scsOffset = SSB_SUBCARRIER_OFFSET; srvCellCfgComm->dlCfg.dlScsCarrier.scs = SUBCARRIER_SPACING; - srvCellCfgComm->dlCfg.dlScsCarrier.scsBw = SCS_CARRIER_BANDWIDTH; + srvCellCfgComm->dlCfg.dlScsCarrier.scsBw = BANDWIDTH_20MHZ; srvCellCfgComm->dlCfg.locAndBw = FREQ_LOC_BW; /* Configuring PDCCH Config Common For SIB1 */ @@ -430,7 +431,7 @@ uint8_t fillServCellCfgCommSib(SrvCellCfgCommSib *srvCellCfgComm) /* Configuring UL Config Common */ srvCellCfgComm->ulCfg.ulScsCarrier.scsOffset = SSB_SUBCARRIER_OFFSET; srvCellCfgComm->ulCfg.ulScsCarrier.scs = SUBCARRIER_SPACING; - srvCellCfgComm->ulCfg.ulScsCarrier.scsBw = SCS_CARRIER_BANDWIDTH; + srvCellCfgComm->ulCfg.ulScsCarrier.scsBw = BANDWIDTH_20MHZ; srvCellCfgComm->ulCfg.pMax = UL_P_MAX; srvCellCfgComm->ulCfg.locAndBw = FREQ_LOC_BW; srvCellCfgComm->ulCfg.timeAlignTimerComm = TimeAlignmentTimer_infinity; diff --git a/src/du_app/du_cfg.h b/src/du_app/du_cfg.h index 836eec583..9244f42c1 100644 --- a/src/du_app/du_cfg.h +++ b/src/du_app/du_cfg.h @@ -32,6 +32,7 @@ #define CU_EGTP_PORT 39002 #define NR_PCI 1 #define NR_CELL_ID 1 +#define NR_NUMEROLOGY 0 #define DU_NAME "ORAN_OAM_DU" #define CELL_TYPE SMALL #define DUPLEX_MODE DUP_MODE_FDD @@ -59,10 +60,8 @@ #define FREQ_SHIFT_7P5KHZ FALSE #define SSB_PBCH_PWR 0 #define BCH_PAYLOAD PHY_GEN_TIMING_PBCH_BIT -#define TOTAL_PRB_BW 106 #define SUBCARRIER_SPACING 0 #define NORMAL_CYCLIC_PREFIX 0 -#define SCS_CARRIER_BANDWIDTH 273 /* Subcarrier spacing- carrier bandwidth */ #define OFFSET_TO_POINT_A 24 /* PRB Offset to Point A */ #define BETA_PSS BETA_PSS_0DB #define SSB_PERIODICITY_5MS 5 @@ -76,7 +75,6 @@ #define MULT_CELL_CARRIER FALSE #define FREQ_LOC_BW 1099 /* DL frequency location and bandwidth */ #define UL_P_MAX 23 -#define BANDWIDTH 20 #define DMRS_TYPE_A_POS 2 #define NUM_SYMBOLS_PER_SLOT 14 /* Number of symbols within a slot */ #define CORESET0_END_PRB 48