From: svaidhya <svaidhya@radisys.com>
Date: Thu, 7 Mar 2024 07:24:17 +0000 (+0530)
Subject: [Epic-ID: ODUHIGH-475][Task-ID: ODUHIGH-572] Fix LWR_MAC creation during PHY as INTEL_L1
X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=993b48af478fd194a8ea49cd43bb0b635cacc2f4;p=o-du%2Fl2.git

[Epic-ID: ODUHIGH-475][Task-ID: ODUHIGH-572] Fix LWR_MAC creation during PHY as INTEL_L1

Change-Id: Iabcebcfe0d348729f638d5c9982fa96655577891
Signed-off-by: svaidhya <svaidhya@radisys.com>
---

diff --git a/src/mt/mt_ss.h b/src/mt/mt_ss.h
index 68c021354..e213b7df4 100755
--- a/src/mt/mt_ss.h
+++ b/src/mt/mt_ss.h
@@ -66,7 +66,7 @@
 #ifndef INTEL_WLS_MEM
 #define SS_MAX_STSKS                    9
 #else
-#define SS_MAX_STSKS                    7 
+#define SS_MAX_STSKS                    8 
 #endif
 #endif 
 #endif /* SS_MULTICORE_SUPPORT */