From: lal.harshita Date: Thu, 24 Feb 2022 11:50:14 +0000 (+0530) Subject: [Epic-ID: ODUHIGH-406][Task-ID: ODUHIGH-423]Fix for incorrect access of schCb instance X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=545c7a4a13972142fb36962323556dcad7119710;hp=660b885601aea1d15dd9d61e7b255946b2f237ba;p=o-du%2Fl2.git [Epic-ID: ODUHIGH-406][Task-ID: ODUHIGH-423]Fix for incorrect access of schCb instance Signed-off-by: lal.harshita Change-Id: I26e3cd60deea949e58fd2203ca4ed1430ac94690 Signed-off-by: lal.harshita --- diff --git a/src/5gnrmac/mac_cfg_hdl.c b/src/5gnrmac/mac_cfg_hdl.c index 6205e5ba3..e46308e56 100644 --- a/src/5gnrmac/mac_cfg_hdl.c +++ b/src/5gnrmac/mac_cfg_hdl.c @@ -94,9 +94,12 @@ MacDuSliceReCfgRspFunc macDuSliceReCfgRspOpts[] = **/ uint8_t MacSchGenCfgReq(Pst *pst, RgMngmt *cfg) { + Pst schPst; + printf("\nReceived Scheduler gen config at MAC"); - pst->dstInst = DEFAULT_CELLS + 1; - SchProcGenCfgReq(pst, cfg); + memset(&schPst, 0, sizeof(Pst)); + FILL_PST_MAC_TO_SCH(schPst, EVENT_SCH_GEN_CFG); + SchProcGenCfgReq(&schPst, cfg); return ROK; } diff --git a/src/5gnrmac/rg_lmm.c b/src/5gnrmac/rg_lmm.c index a8fc28a3a..51742fbe2 100755 --- a/src/5gnrmac/rg_lmm.c +++ b/src/5gnrmac/rg_lmm.c @@ -186,7 +186,7 @@ Reason reason /* reason */ #endif /* Initialize Scheduler as well */ - schActvInit(ENTMAC, (DEFAULT_CELLS + SCH_INST_START), DFLT_REGION, PWR_UP); + schActvInit(ENTMAC, SCH_INST_START, DFLT_REGION, PWR_UP); /* Initialize lower mac */ lwrMacLayerInit(region, 0); diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index a0ff77603..69e7c19d3 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -142,9 +142,7 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) return LCM_REASON_INVALID_MSGTYPE; } /* Update the Pst structure for LM interface */ - memcpy(&schCb[inst].schInit.lmPst, - &cfg->s.schInstCfg.genCfg.lmPst, - sizeof(Pst)); + memcpy(&schCb[inst].schInit.lmPst, &cfg->s.schInstCfg.genCfg.lmPst, sizeof(Pst)); schCb[inst].schInit.inst = inst; schCb[inst].schInit.lmPst.srcProcId = schCb[inst].schInit.procId; @@ -170,8 +168,7 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */ /* Timer Registration request to system services */ - if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst, - (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK) + if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst, (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK) { DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to " "register timer."); @@ -868,7 +865,7 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) SchCellCb *cellCb; SchCellCfgCfm schCellCfgCfm; Pst rspPst; - Inst inst = pst->dstInst-1; + Inst inst = pst->dstInst - SCH_INST_START; uint8_t coreset0Idx = 0; uint8_t numRbs = 0; uint8_t offset = 0; @@ -1818,7 +1815,7 @@ void freeSchSliceCfgReq(SchSliceCfgReq *cfgReq) uint8_t MacSchSliceCfgReq(Pst *pst, SchSliceCfgReq *schSliceCfgReq) { uint8_t count = 0; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; SchSliceCfgRsp sliceCfgRsp; DU_LOG("\nINFO --> SCH : Received Slice Cfg request from MAC"); @@ -1944,7 +1941,7 @@ void SchSendSliceReCfgRspToMac(Inst inst, SchSliceCfgRsp schSliceReCfgRsp) uint8_t MacSchSliceReCfgReq(Pst *pst, SchSliceCfgReq *schSliceReCfgReq) { uint8_t count = 0; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; SchSliceCfgRsp schSliceReCfgRsp; DU_LOG("\nINFO --> SCH : Received Slice ReCfg request from MAC"); diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 5c46b6e51..5295b0f16 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -397,7 +397,7 @@ PduTxOccsaion schCheckSsbOcc(SchCellCb *cell, SlotTimingInfo slotTime); PduTxOccsaion schCheckSib1Occ(SchCellCb *cell, SlotTimingInfo slotTime); uint8_t schBroadcastSsbAlloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc); uint8_t schBroadcastSib1Alloc(SchCellCb *cell, SlotTimingInfo slotTime, DlBrdcstAlloc *dlBrdcstAlloc); -bool schProcessRaReq(SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId); +bool schProcessRaReq(Inst schInst, SchCellCb *cellCb, SlotTimingInfo currTime, uint8_t ueId); bool schProcessMsg4Req(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId); uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAlloc *rarAlloc, uint8_t k0Index); uint8_t schDlRsrcAllocDlMsg(SchCellCb *cell, SlotTimingInfo slotTime, uint16_t crnti, diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c index d9c8e9bb5..28517e82b 100644 --- a/src/5gnrsch/sch_rach.c +++ b/src/5gnrsch/sch_rach.c @@ -350,7 +350,7 @@ RaRspWindowStatus isInRaRspWindow(SchRaReq *raReq, SlotTimingInfo frameToCheck, * @param[in] Current timing of the cell * @return ROK **/ -bool schProcessRaReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId) +bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId) { bool k2Found = false; uint8_t k0TblIdx = 0, k2TblIdx = 0; @@ -469,7 +469,7 @@ bool schProcessRaReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId) } /* Allocate resources for msg3 */ - msg3PuschInfo = schAllocMsg3Pusch(cell->instIdx, cell->raReq[ueId-1]->rachInd->crnti, k2Index, msg3Time); + msg3PuschInfo = schAllocMsg3Pusch(schInst, cell->raReq[ueId-1]->rachInd->crnti, k2Index, msg3Time); if(msg3PuschInfo) { /* Fill RAR info */ @@ -523,7 +523,7 @@ bool schProcessRaReq(SchCellCb *cell, SlotTimingInfo currTime, uint8_t ueId) cell->schUlSlotInfo[msg3Time.slot]->puschUe = ueId; /* Create raCb at SCH */ - createSchRaCb(cell->raReq[ueId-1]->rachInd->crnti, cell->instIdx); + createSchRaCb(cell->raReq[ueId-1]->rachInd->crnti, schInst); /* Remove RachInd from pending RA request list */ SCH_FREE(cell->raReq[ueId-1]->rachInd, sizeof(RachIndInfo)); diff --git a/src/5gnrsch/sch_slot_ind.c b/src/5gnrsch/sch_slot_ind.c index 29a948024..b0a5bbd73 100644 --- a/src/5gnrsch/sch_slot_ind.c +++ b/src/5gnrsch/sch_slot_ind.c @@ -664,7 +664,7 @@ uint8_t schProcessSlotInd(SlotTimingInfo *slotInd, Inst schInst) if(cell->raReq[ueId-1] != NULLP) { isRarPending = true; - isRarScheduled = schProcessRaReq(cell, *slotInd, ueId); + isRarScheduled = schProcessRaReq(schInst, cell, *slotInd, ueId); } /* If MSG4 is pending for this UE, schedule PDCCH,PDSCH to send MSG4 and diff --git a/src/5gnrsch/sch_ue_mgr.c b/src/5gnrsch/sch_ue_mgr.c index 91d53589c..9008dff4c 100644 --- a/src/5gnrsch/sch_ue_mgr.c +++ b/src/5gnrsch/sch_ue_mgr.c @@ -180,7 +180,8 @@ void fillSchUlLcCtxt(SchUlLcCtxt *ueCbLcCfg, SchLcCfg *lcCfg) * * Functionality: Function to fill DLDedLcInfo * - * @params[arg] snssai pointer, + * @params[arg] scheduler instance, + * snssai pointer, * SchRrmPolicy pointer, * SchLcPrbEstimate pointer , It will be filled * isDedicated pointer,(Address of isDedicated flag in LC Context) @@ -191,11 +192,10 @@ void fillSchUlLcCtxt(SchUlLcCtxt *ueCbLcCfg, SchLcCfg *lcCfg) * * ****************************************************************/ -uint8_t updateDedLcInfo(Snssai *snssai, SchLcPrbEstimate *lcPrbEst,\ - bool *isDedicated) +uint8_t updateDedLcInfo(Inst inst, Snssai *snssai, SchLcPrbEstimate *lcPrbEst, bool *isDedicated) { uint8_t sliceCfgIdx =0; - SchSliceCfg sliceCfg = schCb[0].sliceCfg; + SchSliceCfg sliceCfg = schCb[inst].sliceCfg; if(sliceCfg.numOfSliceConfigured) { @@ -241,13 +241,14 @@ uint8_t updateDedLcInfo(Snssai *snssai, SchLcPrbEstimate *lcPrbEst,\ * * Functionality: Function to fill SchUeCb * - * @params[in] SchUeCb pointer, + * @params[in] Scheduler instance, + * SchUeCb pointer, * SchUeCfg pointer * @return ROK/RFAILED * * ****************************************************************/ -uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) +uint8_t fillSchUeCb(Inst inst, SchUeCb *ueCb, SchUeCfg *ueCfg) { uint8_t lcIdx, ueLcIdx; uint8_t freqDomainResource[FREQ_DOM_RSRC_SIZE] = {0}; @@ -328,12 +329,12 @@ uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) * and Create the Dedicated LC List & Update the Reserve PRB number*/ if(ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai != NULLP) { - retDL = updateDedLcInfo(ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai, &(ueCb->dlLcPrbEst),\ + retDL = updateDedLcInfo(inst, ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai, &(ueCb->dlLcPrbEst),\ &(ueCb->dlInfo.dlLcCtxt[ueLcIdx].isDedicated)); } if(ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai != NULLP) { - retUL = updateDedLcInfo(ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai, &(ueCb->ulLcPrbEst),\ + retUL = updateDedLcInfo(inst, ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai, &(ueCb->ulLcPrbEst),\ &(ueCb->ulInfo.ulLcCtxt[ueLcIdx].isDedicated)); } @@ -353,7 +354,7 @@ uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) /*Updating the RRM reserved pool PRB count*/ if(ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai != NULLP) { - retUL = updateDedLcInfo(ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai, &(ueCb->ulLcPrbEst),\ + retUL = updateDedLcInfo(inst, ueCb->ulInfo.ulLcCtxt[ueLcIdx].snssai, &(ueCb->ulLcPrbEst),\ &(ueCb->ulInfo.ulLcCtxt[ueLcIdx].isDedicated)); } if(retUL == RFAILED) @@ -396,7 +397,7 @@ uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) /*Updating the RRM policy*/ if(ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai != NULLP) { - retDL = updateDedLcInfo(ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai, &(ueCb->dlLcPrbEst), \ + retDL = updateDedLcInfo(inst, ueCb->dlInfo.dlLcCtxt[ueLcIdx].snssai, &(ueCb->dlLcPrbEst), \ &(ueCb->dlInfo.dlLcCtxt[ueLcIdx].isDedicated)); } if(retDL == RFAILED) @@ -508,7 +509,7 @@ uint8_t MacSchAddUeConfigReq(Pst *pst, SchUeCfg *ueCfg) SchCellCb *cellCb = NULLP; SchUeCb *ueCb = NULLP; SchUeCfgRsp cfgRsp; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; memset(&cfgRsp, 0, sizeof(SchUeCfgRsp)); #ifdef CALL_FLOW_DEBUG_LOG @@ -547,7 +548,7 @@ uint8_t MacSchAddUeConfigReq(Pst *pst, SchUeCfg *ueCfg) ueCb->ueId = ueId; ueCb->crnti = ueCfg->crnti; ueCb->state = SCH_UE_STATE_ACTIVE; - ret = fillSchUeCb(ueCb, ueCfg); + ret = fillSchUeCb(inst, ueCb, ueCfg); if(ret == ROK) { cellCb->numActvUe++; @@ -741,7 +742,7 @@ uint8_t MacSchModUeConfigReq(Pst *pst, SchUeCfg *ueCfg) SchCellCb *cellCb = NULLP; SchUeCb *ueCb = NULLP; SchUeCfgRsp cfgRsp; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; memset(&cfgRsp, 0, sizeof(SchUeCfgRsp)); #ifdef CALL_FLOW_DEBUG_LOG @@ -769,7 +770,7 @@ uint8_t MacSchModUeConfigReq(Pst *pst, SchUeCfg *ueCfg) if((ueCb->crnti == ueCfg->crnti) && (ueCb->state == SCH_UE_STATE_ACTIVE)) { /* Found the UeCb to Reconfig */ - ret = fillSchUeCb(ueCb, ueCfg); + ret = fillSchUeCb(inst, ueCb, ueCfg); if(ret == ROK) { ueCb->cellCb = cellCb; @@ -1004,7 +1005,7 @@ uint8_t MacSchUeDeleteReq(Pst *pst, SchUeDelete *ueDelete) uint8_t idx=0, ueId=0, ueIdToDel=0, ret=ROK; ErrorCause result; SchCellCb *cellCb = NULLP; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; CmLList *node = NULL, *next = NULL; #ifdef CALL_FLOW_DEBUG_LOG @@ -1208,7 +1209,7 @@ void deleteSchCellCb(SchCellCb *cellCb) uint8_t MacSchCellDeleteReq(Pst *pst, SchCellDelete *cellDelete) { uint8_t cellIdx=0, ret = RFAILED; - Inst inst = pst->dstInst - 1; + Inst inst = pst->dstInst - SCH_INST_START; SchMacRsp result= RSP_OK; #ifdef CALL_FLOW_DEBUG_LOG diff --git a/src/cm/mac_sch_interface.h b/src/cm/mac_sch_interface.h index 3424bfd8a..bd76cc7fa 100644 --- a/src/cm/mac_sch_interface.h +++ b/src/cm/mac_sch_interface.h @@ -17,29 +17,30 @@ *******************************************************************************/ /* events */ -#define EVENT_SCH_CELL_CFG 1 -#define EVENT_SCH_CELL_CFG_CFM 2 -#define EVENT_DL_SCH_INFO 3 -#define EVENT_UL_SCH_INFO 4 -#define EVENT_RACH_IND_TO_SCH 5 -#define EVENT_CRC_IND_TO_SCH 6 -#define EVENT_DL_RLC_BO_INFO_TO_SCH 7 -#define EVENT_ADD_UE_CONFIG_REQ_TO_SCH 8 -#define EVENT_UE_CONFIG_RSP_TO_MAC 9 -#define EVENT_SLOT_IND_TO_SCH 10 -#define EVENT_SHORT_BSR 11 -#define EVENT_UCI_IND_TO_SCH 12 -#define EVENT_MODIFY_UE_CONFIG_REQ_TO_SCH 13 -#define EVENT_UE_RECONFIG_RSP_TO_MAC 14 -#define EVENT_UE_DELETE_REQ_TO_SCH 15 -#define EVENT_UE_DELETE_RSP_TO_MAC 16 -#define EVENT_CELL_DELETE_REQ_TO_SCH 17 -#define EVENT_CELL_DELETE_RSP_TO_MAC 18 -#define EVENT_LONG_BSR 19 -#define EVENT_SLICE_CFG_REQ_TO_SCH 20 -#define EVENT_SLICE_CFG_RSP_TO_MAC 21 -#define EVENT_SLICE_RECFG_REQ_TO_SCH 22 -#define EVENT_SLICE_RECFG_RSP_TO_MAC 23 +#define EVENT_SCH_GEN_CFG 1 +#define EVENT_SCH_CELL_CFG 2 +#define EVENT_SCH_CELL_CFG_CFM 3 +#define EVENT_DL_SCH_INFO 4 +#define EVENT_UL_SCH_INFO 5 +#define EVENT_RACH_IND_TO_SCH 6 +#define EVENT_CRC_IND_TO_SCH 7 +#define EVENT_DL_RLC_BO_INFO_TO_SCH 8 +#define EVENT_ADD_UE_CONFIG_REQ_TO_SCH 9 +#define EVENT_UE_CONFIG_RSP_TO_MAC 10 +#define EVENT_SLOT_IND_TO_SCH 11 +#define EVENT_SHORT_BSR 12 +#define EVENT_UCI_IND_TO_SCH 13 +#define EVENT_MODIFY_UE_CONFIG_REQ_TO_SCH 14 +#define EVENT_UE_RECONFIG_RSP_TO_MAC 15 +#define EVENT_UE_DELETE_REQ_TO_SCH 16 +#define EVENT_UE_DELETE_RSP_TO_MAC 17 +#define EVENT_CELL_DELETE_REQ_TO_SCH 18 +#define EVENT_CELL_DELETE_RSP_TO_MAC 19 +#define EVENT_LONG_BSR 20 +#define EVENT_SLICE_CFG_REQ_TO_SCH 21 +#define EVENT_SLICE_CFG_RSP_TO_MAC 22 +#define EVENT_SLICE_RECFG_REQ_TO_SCH 23 +#define EVENT_SLICE_RECFG_RSP_TO_MAC 24 /*macros*/ #define MAX_SSB_IDX 1 /* forcing it as 1 for now. Right value is 64 */