From: pborla <pborla@radisys.com>
Date: Wed, 27 Nov 2024 06:28:59 +0000 (+0530)
Subject: Modifying tdd_odu_config.xml and fdd_odu_config.xml
X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=3bb3dfeca4099e26d4ae964186798841e523f509;p=o-du%2Fl2.git

Modifying tdd_odu_config.xml and fdd_odu_config.xml

Change-Id: I9bd0ff14aa03fcc0492820ea3280d59aa03de932
Signed-off-by: pborla <pborla@radisys.com>
---

diff --git a/build/config/fdd_odu_config.xml b/build/config/fdd_odu_config.xml
index d61ad427d..7a45f37dc 100644
--- a/build/config/fdd_odu_config.xml
+++ b/build/config/fdd_odu_config.xml
@@ -190,6 +190,16 @@
          </TDD_UL_DL_CFG_COMMON>
       </SRV_CELL_CFG_COM_SIB>
    </SIB1_PARAMS>
+   <MIB_PARAMS>
+      <SYS_FRAME_NUM>0</SYS_FRAME_NUM>
+      <SUB_CARR_SPACE>0</SUB_CARR_SPACE>
+      <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
+      <DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
+      <CORESET_0_INDEX>0</CORESET_0_INDEX>
+      <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
+      <CELL_BARRED>1</CELL_BARRED>
+      <INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
+   </MIB_PARAMS>
    <F1_DU_SRVD_CELL_INFO>
       <F1_DU_CELL_INFO>
          <F1_CELL_INFO>
@@ -369,16 +379,6 @@
          </F1_BRDCST_PLMN_INFO>
       </F1_DU_CELL_INFO>
    </F1_DU_SRVD_CELL_INFO>
-   <MIB_PARAMS>
-      <SYS_FRAME_NUM>0</SYS_FRAME_NUM>
-      <SUB_CARR_SPACE>0</SUB_CARR_SPACE>
-      <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
-      <DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
-      <CORESET_0_INDEX>0</CORESET_0_INDEX>
-      <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
-      <CELL_BARRED>1</CELL_BARRED>
-      <INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
-   </MIB_PARAMS>
    <MAC_CELL_CFG>
       <CELL_ID>1</CELL_ID>
       <CARRIER_CFG>
diff --git a/build/config/tdd_odu_config.xml b/build/config/tdd_odu_config.xml
index b8a1d4c1a..409caf826 100644
--- a/build/config/tdd_odu_config.xml
+++ b/build/config/tdd_odu_config.xml
@@ -190,6 +190,16 @@
          </TDD_UL_DL_CFG_COMMON>
       </SRV_CELL_CFG_COM_SIB>
    </SIB1_PARAMS>
+   <MIB_PARAMS>
+      <SYS_FRAME_NUM>0</SYS_FRAME_NUM>
+      <SUB_CARR_SPACE>1</SUB_CARR_SPACE>
+      <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
+      <DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
+      <CORESET_0_INDEX>0</CORESET_0_INDEX>
+      <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
+      <CELL_BARRED>1</CELL_BARRED>
+      <INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
+   </MIB_PARAMS>
    <F1_DU_SRVD_CELL_INFO>
       <F1_DU_CELL_INFO>
          <F1_CELL_INFO>
@@ -369,16 +379,6 @@
          </F1_BRDCST_PLMN_INFO>
       </F1_DU_CELL_INFO>
    </F1_DU_SRVD_CELL_INFO>
-   <MIB_PARAMS>
-      <SYS_FRAME_NUM>0</SYS_FRAME_NUM>
-      <SUB_CARR_SPACE>1</SUB_CARR_SPACE>
-      <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
-      <DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
-      <CORESET_0_INDEX>0</CORESET_0_INDEX>
-      <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
-      <CELL_BARRED>1</CELL_BARRED>
-      <INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
-   </MIB_PARAMS>
    <MAC_CELL_CFG>
       <CELL_ID>1</CELL_ID>
       <CARRIER_CFG>