From: lal.harshita Date: Thu, 29 Jul 2021 13:09:11 +0000 (+0530) Subject: Implementation of function for filling k0 and k1 table [Issue-ID: ODUHIGH-341] X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=commitdiff_plain;h=3ba126e9d0aff0ceca5012c27ffd4a3722fdbc4e;p=o-du%2Fl2.git Implementation of function for filling k0 and k1 table [Issue-ID: ODUHIGH-341] Change-Id: Ibb1def0cde6001f9325b8627490bcd25dd979432 Signed-off-by: lal.harshita --- diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 63a0ec862..9d115f134 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -50,7 +50,6 @@ SchCb schCb[SCH_MAX_INST]; void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm); - /* local defines */ SchCellCfgCfmFunc SchCellCfgCfmOpts[] = { @@ -857,6 +856,7 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) SchCellCfgCfm schCellCfgCfm; Pst rspPst; Inst inst = pst->dstInst-1; + SchPdschConfig pdschCfg; #ifdef CALL_FLOW_DEBUG_LOG DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SCH_CELL_CFG\n"); @@ -872,6 +872,10 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); + /* Fill K0 - K1 table for common cfg*/ + BuildK0K1Table(cellCb, &cellCb->cellCfg.schInitialDlBwp.k0K1InfoTbl, true, cellCb->cellCfg.schInitialDlBwp.pdschCommon, + pdschCfg, DEFAULT_UL_ACK_LIST_COUNT, defaultUlAckTbl); + /* Initializing global variables */ cellCb->actvUeBitMap = 0; cellCb->boIndBitMap = 0; diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index d05d77b40..da957a1f7 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -274,6 +274,8 @@ uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t cr uint32_t *accumalatedSize, uint16_t slot); uint16_t schAccumalateLcBoSize(SchCellCb *cell, uint16_t ueIdx); uint8_t schFillRar(RarAlloc *rarAlloc, uint16_t raRnti, uint16_t pci, uint8_t offsetPointA, bool ssbPresent, bool sib1Present); +void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\ +SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl); /********************************************************************** End of file diff --git a/src/5gnrsch/sch_common.c b/src/5gnrsch/sch_common.c index 448434cad..c077ec02d 100644 --- a/src/5gnrsch/sch_common.c +++ b/src/5gnrsch/sch_common.c @@ -841,6 +841,282 @@ uint8_t schDlRsrcAllocDlMsg(DlMsgAlloc *dlMsgAlloc, SchCellCb *cell, uint16_t cr return ROK; } +/******************************************************************* + * + * @brief Fills k0 and k1 information table for FDD + * + * @details + * + * Function : BuildK0K1TableForFdd + * + * Functionality: + * Fills k0 and k1 information table for FDD + * + * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool + * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc + * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc + * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +void BuildK0K1TableForFdd(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres,SchPdschCfgCmn pdschCmnCfg,\ +SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl) +{ + uint8_t k0TmpVal = 0, k1TmpVal =0, cfgIdx=0; + uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, numTimeDomAlloc=0; + SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC]; + SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC]; + + /* Initialization the structure and storing the total slot values. */ + memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl)); + k0K1InfoTbl->tblSize = cell->numSlots; + + /* Storing time domain resource allocation list based on common or dedicated configuration. */ + if(pdschCfgCmnPres == true) + { + numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc; + for(cfgIdx = 0; cfgIdxnumSlots; slotIdx++) + { + numK0 = 0; + /* Storing the values of k0 based on time domain resource + * allocation list. If the value is unavailable then fill default values, + * As per 38.331 PDSCH-TimeDomainResourceAllocation field descriptions. */ + for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++) + { + if(pdschCfgCmnPres == true) + { + k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0; + } + else + { + if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP) + { + k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0); + } + else + { + k0TmpVal = DEFAULT_K0_VALUE; + } + } + + /* Checking all the Ul Alloc values. If value is less than MIN_NUM_K1_IDX + * then skip else continue storing the values. */ + numK1 = 0; + for(k1Index = 0; k1Index < ulAckListCount; k1Index++) + { + k1TmpVal = UlAckTbl[k1Index]; + if(k1TmpVal <= MIN_NUM_K1_IDX) + { + continue; + } + + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index; + /* TODO Store K1 index where harq feedback will be received in harq table. */ + } + if(numK1) + { + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1; + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index; + numK0++; + } + } + if(numK0) + { + k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0; + } + } +} + +/******************************************************************* + * + * @brief Fills k0 and k1 information table + * + * @details + * + * Function : BuildK0K1Table + * + * Functionality: + * Fills K0 and k1 information table + * + * @params[in] SchCellCb *cell,SchK0K1TimingInfoTbl *k0K1InfoTbl,bool + * pdschCfgCmnPres,uint8_t numTimeDomAlloc, SchPdschCfgCmnTimeDomRsrcAlloc + * cmnTimeDomRsrcAllocList[], SchPdschTimeDomRsrcAlloc + * dedTimeDomRsrcAllocList[], uint8_t ulAckListCount, uint8_t *UlAckTbl + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +void BuildK0K1Table(SchCellCb *cell, SchK0K1TimingInfoTbl *k0K1InfoTbl, bool pdschCfgCmnPres, SchPdschCfgCmn pdschCmnCfg,\ +SchPdschConfig pdschDedCfg, uint8_t ulAckListCount, uint8_t *UlAckTbl) +{ + +#ifdef NR_TDD + SlotConfig slotCfg; + bool ulSlotPresent = false; + uint8_t k0TmpVal = 0, k1TmpVal =0, tmpSlot=0, startSymbol=0, endSymbol=0, checkSymbol=0; + uint8_t slotIdx=0, k0Index=0, k1Index=0, numK0=0, numK1=0, cfgIdx=0, numTimeDomAlloc =0, totalCfgSlot =0; + SchPdschCfgCmnTimeDomRsrcAlloc cmnTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC]; + SchPdschTimeDomRsrcAlloc dedTimeDomRsrcAllocList[MAX_NUM_DL_ALLOC]; +#endif + + if(cell->cellCfg.dupMode == DUPLEX_MODE_FDD) + { + BuildK0K1TableForFdd(cell, k0K1InfoTbl, pdschCfgCmnPres, pdschCmnCfg, pdschDedCfg, ulAckListCount, UlAckTbl); + } + else + { +#ifdef NR_TDD + + /* Initialization the K0K1 structure, total num of slot and calculating the slot pattern length. */ + memset(k0K1InfoTbl, 0, sizeof(SchK0K1TimingInfoTbl)); + k0K1InfoTbl->tblSize = cell->numSlots; + totalCfgSlot = calculateSlotPatternLength(cell->cellCfg.ssbSchCfg.scsCommon, cell->cellCfg.tddCfg.tddPeriod); + + /* Storing time domain resource allocation list based on common or + * dedicated configuration availability. */ + if(pdschCfgCmnPres == true) + { + numTimeDomAlloc = pdschCmnCfg.numTimeDomAlloc; + for(cfgIdx = 0; cfgIdxnumSlots; slotIdx++) + { + /* If current slot is UL or FLEXI then Skip because PDCCH is sent only in DL slots. */ + slotCfg = schGetSlotSymbFrmt(slotIdx%totalCfgSlot, cell->slotFrmtBitMap); + if(slotCfg == UL_SLOT || slotCfg == FLEXI_SLOT) + { + continue; + } + + /* Storing K0 , start symbol and length symbol for further processing. + * If K0 value is not available then we can fill the default values + * given in spec 38.331. */ + numK0 = 0; + for(k0Index = 0; ((k0Index < numTimeDomAlloc) && (k0Index < MAX_NUM_K0_IDX)); k0Index++) + { + if(pdschCfgCmnPres == true) + { + k0TmpVal = cmnTimeDomRsrcAllocList[k0Index].k0; + startSymbol = cmnTimeDomRsrcAllocList[k0Index].startSymbol; + endSymbol = startSymbol + cmnTimeDomRsrcAllocList[k0Index].lengthSymbol; + } + else + { + if(dedTimeDomRsrcAllocList[k0Index].k0 != NULLP) + { + k0TmpVal = *(dedTimeDomRsrcAllocList[k0Index].k0); + } + else + { + k0TmpVal = DEFAULT_K0_VALUE; + } + startSymbol = dedTimeDomRsrcAllocList[k0Index].startSymbol; + endSymbol = startSymbol + dedTimeDomRsrcAllocList[k0Index].symbolLength; + } + + /* If current slot + k0 is UL then skip the slot + * else if it is DL slot then continue the next steps + * else if it is a FLEXI slot then check symbols of slot, It should not + * contain any UL slot. */ + tmpSlot = (slotIdx+k0TmpVal) % totalCfgSlot; + slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap); + if(slotCfg == UL_SLOT) + { + continue; + } + if(slotCfg == FLEXI_SLOT) + { + for(checkSymbol = startSymbol; checkSymbolcellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol]; + if(slotCfg == UL_SLOT) + { + continue; + } + } + } + + /* If current slot + k0 + k1 is a DL slot then skip the slot + * else if it is UL slot then store the information + * else if it is FLEXI slot then check the symbols, it must have + * at least one UL symbol. */ + numK1 = 0; + for(k1Index = 0; k1Index < ulAckListCount; k1Index++) + { + k1TmpVal = UlAckTbl[k1Index]; + if(k1TmpVal > MIN_NUM_K1_IDX) + { + tmpSlot = (slotIdx+k0TmpVal+k1TmpVal) % totalCfgSlot; + slotCfg = schGetSlotSymbFrmt(tmpSlot, cell->slotFrmtBitMap); + if(slotCfg == DL_SLOT) + { + continue; + } + if(slotCfg == FLEXI_SLOT) + { + for(checkSymbol = 0; checkSymbolcellCfg.tddCfg.slotCfg[tmpSlot][checkSymbol] == UL_SLOT) + { + ulSlotPresent = true; + break; + } + } + } + if(ulSlotPresent == true || slotCfg == UL_SLOT) + { + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.k1Indexes[numK1++] = k1Index; + /* TODO Store K1 index where harq feedback will be received + * in harq table. */ + } + } + } + + /* Store all the values if all condition satisfies. */ + if(numK1) + { + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k1TimingInfo.numK1 = numK1; + k0K1InfoTbl->k0k1TimingInfo[slotIdx].k0Indexes[numK0].k0Index = k0Index; + numK0++; + } + } + if(numK0) + { + k0K1InfoTbl->k0k1TimingInfo[slotIdx].numK0 = numK0; + } + } +#endif + } +} /********************************************************************** End of file **********************************************************************/ diff --git a/src/5gnrsch/sch_slot_ind.c b/src/5gnrsch/sch_slot_ind.c index 2b1bf5702..4df452ad5 100644 --- a/src/5gnrsch/sch_slot_ind.c +++ b/src/5gnrsch/sch_slot_ind.c @@ -180,6 +180,12 @@ uint8_t schFillBoGrantDlSchedInfo(SchCellCb *cell, DlSchedInfo *dlSchedInfo, DlM } ueCb->dlInfo.dlLcCtxt[lcIdx].bo = 0; } + + if (!dlMsgAlloc->numLc) + { + DU_LOG("\nDEBUG --> SCH : No bo for any lcid\n"); + return ROK; + } /* pdcch and pdsch data is filled */ schDlRsrcAllocDlMsg(dlMsgAlloc, cell, crnti, &accumalatedSize, slot); diff --git a/src/5gnrsch/sch_ue_mgr.c b/src/5gnrsch/sch_ue_mgr.c index e2ce9f9d4..8b8428156 100644 --- a/src/5gnrsch/sch_ue_mgr.c +++ b/src/5gnrsch/sch_ue_mgr.c @@ -213,7 +213,9 @@ void updateSchDlCb(uint8_t delIdx, SchDlCb *dlInfo) uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) { uint8_t lcIdx, ueLcIdx; - + SchPdschCfgCmn pdschCfg; + SchPucchDlDataToUlAck *dlDataToUlAck; + ueCb->ueCfg.cellId = ueCfg->cellId; ueCb->ueCfg.crnti = ueCfg->crnti; if(ueCfg->macCellGrpCfgPres == true) @@ -232,6 +234,13 @@ uint8_t fillSchUeCb(SchUeCb *ueCb, SchUeCfg *ueCfg) { memcpy(&ueCb->ueCfg.spCellCfg , &ueCfg->spCellCfg, sizeof(SchSpCellCfg)); ueCb->ueCfg.spCellCfgPres = true; + dlDataToUlAck = ueCfg->spCellCfg.servCellCfg.initUlBwp.pucchCfg.dlDataToUlAck; + if(dlDataToUlAck) + { + BuildK0K1Table(ueCb->cellCb, &ueCb->ueCfg.spCellCfg.servCellCfg.initDlBwp.k0K1InfoTbl, false, pdschCfg,\ + ueCfg->spCellCfg.servCellCfg.initDlBwp.pdschCfg, dlDataToUlAck->dlDataToUlAckListCount,\ + dlDataToUlAck->dlDataToUlAckList); + } } ueCb->state = SCH_UE_STATE_ACTIVE; diff --git a/src/5gnrsch/sch_utils.c b/src/5gnrsch/sch_utils.c index e1809fa86..600297da8 100644 --- a/src/5gnrsch/sch_utils.c +++ b/src/5gnrsch/sch_utils.c @@ -765,6 +765,7 @@ uint8_t pucchResourceSet[MAX_PUCCH_RES_SET_IDX][4] = { { 1, 0, 14, 0 }, /* index 15 */ }; +uint8_t defaultUlAckTbl[DEFAULT_UL_ACK_LIST_COUNT]= {1, 2, 3 , 4, 5, 6, 7, 8}; /** * @brief frequency domain allocation function. * @@ -1032,6 +1033,69 @@ SlotConfig schGetSlotSymbFrmt(uint16_t slot, uint32_t bitMap) #endif } +/** + * @brief Determine total length of configured slot pattern for specific + * periodicity for TDD + * + * @details + * + * Function : calculateSlotPatternLength + * + * Determine total length of configured slot pattern for specific periodicity based + * on slot duration for TDD + * + * @param[in] uint8_t scs, uint8_t periodicity + * + * @return uint8_t slotPatternLength + **/ + +uint8_t calculateSlotPatternLength(uint8_t scs, uint8_t periodicity) +{ + uint8_t slotPatternLength =0; + float slotDuration = 0; + + /* Calculating the slot duration with the help of SCS. + * This will provides the slot duration in ms like 1, 0.5, 0.25, 0.125. + * If scs value is SCS_30KHZ its enum value is 1, + * slotDuration = pow(0.5, 1); + * slotDuration = 0.5 */ + + slotDuration = pow(0.5,scs); + + /* Calculating length of pattern based on Transmission Periodicity. + * If periodicity = TX_PRDCTY_MS_5, + * slotPatternLength = 5/0.5 + * slotPatternLength = 10 i.e. {length of slot pattern DDDDDDDFUU}*/ + + switch(periodicity) + { + case TX_PRDCTY_MS_0P5: + slotPatternLength = 0.5/slotDuration; + break; + case TX_PRDCTY_MS_0P625: + slotPatternLength = 0.625/slotDuration; + break; + case TX_PRDCTY_MS_1: + slotPatternLength = 1/slotDuration; + break; + case TX_PRDCTY_MS_1P25: + slotPatternLength = 1.25/slotDuration; + break; + case TX_PRDCTY_MS_2: + slotPatternLength = 2/slotDuration; + break; + case TX_PRDCTY_MS_2P5: + slotPatternLength = 2.5/slotDuration; + break; + case TX_PRDCTY_MS_5: + slotPatternLength = 5/slotDuration; + break; + case TX_PRDCTY_MS_10: + slotPatternLength = 10/slotDuration; + break; + } + return slotPatternLength; +} #endif /********************************************************************** End of file diff --git a/src/5gnrsch/sch_utils.h b/src/5gnrsch/sch_utils.h index a287413e4..fb1bb2c1e 100644 --- a/src/5gnrsch/sch_utils.h +++ b/src/5gnrsch/sch_utils.h @@ -31,6 +31,7 @@ #define MAX_PRACH_CONFIG_IDX 256 #define MAX_MU_PUSCH 4 #define TOTAL_TBSIZE_VALUES 93 +#define DEFAULT_UL_ACK_LIST_COUNT 8 /* Max number of pusch time domain uplink allocation */ #define SET_BITS_MSB(_startBit, _numBits, _byte) \ { \ @@ -97,6 +98,7 @@ int8_t coresetIdxTable[MAX_CORESET_INDEX][4]; int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4]; +uint8_t defaultUlAckTbl[DEFAULT_UL_ACK_LIST_COUNT]; /* functions declarations */ void freqDomRscAllocType0(uint16_t startPrb, uint16_t prbSize, uint8_t *freqDomain); @@ -105,6 +107,7 @@ uint16_t schCalcNumPrb(uint16_t tbSize, uint16_t mcs, uint8_t numSymbols); uint16_t schCalcTbSizeFromNPrb(uint16_t numPrb, uint16_t mcs, uint8_t numSymbols); #ifdef NR_TDD SlotConfig schGetSlotSymbFrmt(uint16_t slot, uint32_t bitMap); +uint8_t calculateSlotPatternLength(uint8_t scs, uint8_t periodicity); #endif /********************************************************************** diff --git a/src/cm/mac_sch_interface.h b/src/cm/mac_sch_interface.h index 85da85c40..321b12e48 100644 --- a/src/cm/mac_sch_interface.h +++ b/src/cm/mac_sch_interface.h @@ -95,6 +95,11 @@ #define RAR_PAYLOAD_SIZE 10 /* As per spec 38.321, sections 6.1.5 and 6.2.3, RAR PDU is 8 bytes long and 2 bytes of padding */ #define TX_PAYLOAD_HDR_LEN 32 /* Intel L1 requires adding a 32 byte header to transmitted payload */ +#define MAX_NUM_CONFIG_SLOTS 160 /*Max number of slots as per the numerology*/ +#define MAX_NUM_K0_IDX 16 /* Max number of pdsch time domain downlink allocation */ +#define MAX_NUM_K1_IDX 8 /* As per spec 38.213 section 9.2.3 Max number of PDSCH-to-HARQ resource indication */ +#define MIN_NUM_K1_IDX 4 /* Min K1 values */ +#define DEFAULT_K0_VALUE 0 /*As per 38.331, PDSCH-TimeDomainResourceAllocation field descriptions*/ #define ADD_DELTA_TO_TIME(crntTime, toFill, incr) \ { \ @@ -645,11 +650,36 @@ typedef struct schPuschCfgCmn SchPuschTimeDomRsrcAlloc timeDomRsrcAllocList[MAX_NUM_UL_ALLOC]; /* PUSCH time domain UL resource allocation list */ }SchPuschCfgCmn; +typedef struct schK1TimingInfo +{ + uint8_t numK1; + uint8_t k1Indexes[MAX_NUM_K1_IDX]; +}SchK1TimingInfo; + +typedef struct schK0TimingInfo +{ + uint8_t k0Index; + SchK1TimingInfo k1TimingInfo; +}SchK0TimingInfo; + +typedef struct schK0K1TimingInfo +{ + uint8_t numK0; + SchK0TimingInfo k0Indexes[MAX_NUM_K0_IDX]; +}SchK0K1TimingInfo; + +typedef struct schK0K1TimingInfoTbl +{ + uint16_t tblSize; + SchK0K1TimingInfo k0k1TimingInfo[MAX_NUM_CONFIG_SLOTS]; +}SchK0K1TimingInfoTbl; + typedef struct schBwpDlCfg { SchBwpParams bwp; SchPdcchCfgCmn pdcchCommon; SchPdschCfgCmn pdschCommon; + SchK0K1TimingInfoTbl k0K1InfoTbl; }SchBwpDlCfg; typedef struct schBwpUlCfg @@ -1110,6 +1140,7 @@ typedef struct schInitalDlBwp SchPdcchConfig pdcchCfg; bool pdschCfgPres; SchPdschConfig pdschCfg; + SchK0K1TimingInfoTbl k0K1InfoTbl; }SchInitalDlBwp; /* BWP Downlink common */