* uint8_t offsetPointA : offset
* @return void
**/
-void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
+void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA)
{
uint8_t coreset0Idx = 0;
uint8_t searchSpace0Idx = 0;
uint8_t FreqDomainResource[6] = {0};
uint16_t tbSize = 0;
uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */
+ uint8_t ssbIdx = 0;
PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
* [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
* assuming u = 0, i = 0, numSlotsPerSubframe = 10
* Also, from this configuration, coreset0 is only on even subframe */
- slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots;
+ slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots;
sib1SchCfg->n0 = slotIndex;
/* calculate the PRBs */
pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS;
pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */
- pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0,
+ pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0,
and PDSCH is always above SSB */
pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols);
pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
cellCb->macInst = pst->srcInst;
/* derive the SIB1 config parameters */
- fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots,
+ fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots,
&(schCellCfg->sib1SchCfg), schCellCfg->phyCellId,
schCellCfg->ssbSchCfg.ssbOffsetPointA);
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
#include "sch_utils.h"
#include "math.h"
-/* spec-38.213 Table 13-1 */
+#ifdef NR_TDD
+/* spec-38.213 Table 13-4 for SCS=30KHz */
+/* Note: Picking Table 13-4 and not 13-6 since band supported is n78 and
+ * corresponding minimum B/W is 10 MHz */
+int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = {
+{ 1, 24, 2, 0}, /* index 0 */
+{ 1, 24, 2, 1}, /* index 1 */
+{ 1, 24, 2, 2}, /* index 2 */
+{ 1, 24, 2, 3}, /* index 3 */
+{ 1, 24, 2, 4}, /* index 4 */
+{ 1, 24, 3, 0}, /* index 5 */
+{ 1, 24, 3, 1}, /* index 6 */
+{ 1, 24, 3, 2}, /* index 7 */
+{ 1, 24, 3, 3}, /* index 8 */
+{ 1, 24, 3, 4}, /* index 9 */
+{ 1, 48, 1, 12}, /* index 10 */
+{ 1, 48, 1, 14}, /* index 11 */
+{ 1, 48, 1, 16}, /* index 12 */
+{ 1, 48, 2, 12}, /* index 13 */
+{ 1, 48, 2, 14}, /* index 14 */
+{ 1, 48, 2, 16}, /* index 15 */
+};
+#else
+/* spec-38.213 Table 13-1 for SCS=15KHz */
int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = {
{ 1, 24, 2, 0}, /* index 0 */
{ 1, 24, 2, 2}, /* index 1 */
{ 1, 96, 3, 38}, /* index 14 */
{ 0, 0, 0, 0}, /* index 15 */
};
+#endif
/* spec-38.213 Table 13-11 */
/* m value is scaled to 2, when using it in formula, divide by 2 */
tbSize = tbSize * 8; //Calculate tbSize in bits
- /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
- * Ninfo = Nre . R . Qm . v *
+ /* formula used for calculation of rbSize, 38.214 section 5.1.3.2 *
+ * Ninfo = S . Nre . R . Qm . v *
* Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
* Nre = min(156,Nre') . nPrb */
{
memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo));
}
+#if 0
+ //make allocation for SSB
+ if(cell->firstSsbTransmitted)
+ {
+ //TODO check if this slot and sfn are for ssb
+
+ }
+#endif
}
#ifdef NR_TDD