-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-Architecture Overview
-=====================
-
-.. contents::
- :depth: 3
- :local:
-
-This section provides an overview of the xRAN architecture.
-
-.. _introduction-1:
-
-Introduction
-------------
-
-The front haul interface, according to the ORAN Fronthaul specification,
-performs communication between O-RAN Distributed Unit (O-DU) and O-RAN
-Radio Unit (O-RU) and consists of multiple HW and SW components.
-
-The logical representation of HW and SW components is shown in Figure 1.
-
-.. image:: images/Architecture-Block-Diagram.jpg
- :width: 600
- :alt: Figure 1. Architecture Block Diagram
-
-Figure 1. Architecture Block Diagram
-
-|br|
-|br|
-
-From the hardware perspective, two networking ports are used to
-communicate to the Front Haul and Back (Mid) Haul network as well as to
-receive PTP synchronization. The system timer is used to provide a
-“sense” of time to the gNB application.
-
-From the software perspective, the following components are used:
-
-* Linux PTP provides synchronization of system timer to GPS time:
-
- - Ptp4l is used to synchronize oscillator on Network Interface
- Controller (NIC) to PTP GM.
-
- - Phc2sys is used to synchronize system timer to oscillator on NIC.
-
-* DPDK to provide the interface to the Ethernet port.
-
-* xRAN library is built on top of DPDK to perform U-plane and C-plane
- functionality according to the ORAN Fronthaul specification.
-
-* 5GNR reference PHY uses the xRAN library to access interface to O-RU.
- The interface between the library and PHY is defined to communicate
- TTI event, symbol time, C-plane information as well as IQ sample
- data.
-
-* 5G NR PHY communicates with the L2 application using the set of
- MAC/PHY APIs and the shared memory interface defined as WLS.
-
-* L2, in turn, can use Back (Mid) Haul networking port to connect to
- the CU unit in the context of 3GPP specification.
-
-In this document, we focus on the details of the design and
-implementation of the xRAN library with respect to providing Front Haul
-functionality for both mmWave and Sub-6 scenarios.
-
-The xRAN M-plane is not implemented and is outside of the scope of this
-description. Configuration files are used to specify selected M-plane
-level parameters.
-
-ORAN FH Threads
----------------
-
-ORAN FH Thread Performs:
-
-- Symbol base “time event” to the rest of the system based on System
- Clock synchronized to GPS time via PTP.
-
-- Baseline polling mode driver performing TX and RX of Ethernet packets.
-
-- Most of the packet processing such as Transport header, Application
- header, Data section header and interactions with the rest of the PHY
- processing pipeline.
-
-- Polling of other call back function that was registered.
-
-ORAN FH thread created the independent of usage of xRAN as an interface
-to the Radio.
-
-Communication between L1 and xRAN layer is performed using a set of
-callback functions where L1 assigned callback and xRAN layer executes
-those functions at a particular event or time moment. Detailed
-information on callback function options and setting as well as design,
-can be found in the sections below.
-
-Sample Application Thread Model
--------------------------------
-
-Configuration of a sample application for both O-DU and O-RU follows the
-model of 5G NR l1app application in the section of xRAN only. No BBU or
-FEC related threads are needed as minimal xRAN functionality is used
-only.
-
-.. image:: images/Sample-Application-Threads.jpg
- :width: 600
- :alt: Figure 3. Sample Application Threads
-
-Figure 3. Sample Application Threads
-
-|br|
-|br|
-
-In this scenario, the main thread is used only for initializing and
-closing the application. No execution happens on core 0 during run time.
-
-Functional Split
-----------------
-
-Figure 1 corresponds to the O-RU part of the xRAN split. Implementation
-of the RU side of the xRAN protocol is not covered in this document.
-
-.. image:: images/eNB-gNB-Architecture-with-O-DU-and-RU.jpg
- :width: 600
- :alt: Figure 4. eNB/gNB Architecture with O-DU and RU
-
-Figure 4. eNB/gNB Architecture with O-DU and RU
-
-|br|
-|br|
-
-More than one RU can be supported with the same implementation of the
-xRAN library and depends on the configuration of gNB in general. In this
-document, we address details of implementation for single O-DU – O-RU
-connection.
-
-The ORAN Fronthaul specification provides two categories of the split of
-Layer 1 functionality between O-DU and O‑RU: Category A and Category B.
-
-.. image:: images/Functional-Split.jpg
- :width: 600
- :alt: Figure 5. Functional Split
-
-Figure 5. Functional Split
-
-|br|
-
-Data Flow
----------
-
-|br|
-
-Table 3 lists the data flows supported for a single RU with a single
-Component Carrier.
-
-|br|
-|br|
-
-Table 3. Supported Data Flow
-
-+---------+----+-----------------+-----------------+----------------+
-| Plane | ID | Name | Contents | Periodicity |
-+---------+----+-----------------+-----------------+----------------+
-| U-Plane | 1a | DL Frequency | DL user data | symbol |
-| | | Domain IQ Data | (PDSCH), | |
-| | | | control channel | |
-| | | | data (PDCCH, | |
-| | | | etc.) | |
-+---------+----+-----------------+-----------------+----------------+
-| | 1b | UL Frequency | UL user data | symbol |
-| | | Domain IQ Data | (PUSCH), | |
-| | | | control channel | |
-| | | | data (PUCCH, | |
-| | | | etc.) | |
-+---------+----+-----------------+-----------------+----------------+
-| | 1c | PRACH Frequency | UL PRACH data | slot or symbol |
-| | | Domain IQ Data | | |
-+---------+----+-----------------+-----------------+----------------+
-| C-Plane | 2a | Scheduling | Scheduling | ~ slot |
-| | | Commands | information, | |
-| | | | FFT size, CP | |
-| | | (Beamforming is | length, | |
-| | | not supported) | Subcarrier | |
-| | | | spacing, UL | |
-| | | | PRACH | |
-| | | | scheduling | |
-+---------+----+-----------------+-----------------+----------------+
-| S-Plane | S | Timing and | IEEE 1588 PTP | |
-| | | Synchronization | packets | |
-+---------+----+-----------------+-----------------+----------------+
-
-|br|
-|br|
-
-.. image:: images/Data-Flows.jpg
- :width: 600
- :alt: Figure 6. Data Flows
-
-Figure 6. Data Flows
-
-|br|
-|br|
-
-Information on specific features of C-Plane and U-plane provided in
-Section 6.0. Configuration of S-plane used on test setup for simulation
-is provided in Appendix Appendix 2.
-
-Data flow separation is based on VLAN (applicable when layer 2 or layer
-3 is used for the C/U-plane transport.)
-
-#. The mechanism for assigning VLAN ID to U-Plane and C-Plane is assumed
-to be via the M-Plane.
-
-VLAN Tag is configurable via the standard Linux IP tool (refer to
-Appendix Appendix 1).
-
-No Quality of Service (QoS) is supported.
-
-|br|
-|br|
-
-.. image:: images/C-plane-and-U-plane-Packet-Exchange.jpg
- :width: 600
- :alt: Figure 7. C-plane and U-plane Packet Exchange
-
-Figure 7. C-plane and U-plane Packet Exchange
-
-|br|
-|br|
-
-Timing, Latency, and Synchronization to GPS
--------------------------------------------
-
-The ORAN Fronthaul specification defines the latency model of the front
-haul interface and interaction between O-DU and O-RU. This
-implementation of the xRAN library supports only the category with fixed
-timing advance and Defined Transport method. It determines O-DU transmit
-and receive windows based on pre-defined transport network characteristics, and the delay characteristics of the RUs within the
-timing domain.
-
-Table 4 below provides default values used for the implementation of
-O-DU – O-RU simulation with mmWave scenario. Table 5 and Table 6 below
-provide default values used for the implementation of O-DU – O-RU
-simulation with numerology 0 and numerology 1 for Sub6 scenarios.
-Configuration can be adjusted via configuration files for sample |br|
-application and reference PHY. However, simulation of the different
-range of the settings was not performed, and additional implementation changes might be required as well as testing with actual O-RU. The
-parameters for the front haul network are out of scope as a direct connection between O-DU and 0-RU is used for simulation.
-
-|br|
-|br|
-
-Table 4. Front Haul Interface Latency (numerology 3 - mmWave)
-
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Model | C-Plane | U-Plane | | |
-| | Parameters | | | | |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | | DL | UL | DL | UL |
-+------+------------+-------------------+-------------------+----------------+------------+
-| O-RU | T2amin | T2a_min_cp_dl=50 | T2a_min_cp_ul=50 | T2a_min_up=25 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | T2amax | T2a_max_cp_dl=140 | T2a_max_cp_ul=140 | T2a_max_up=140 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | | Tadv_cp_dl | NA | NA | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta3min | NA | NA | NA | Ta3_min=20 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta3max | NA | NA | NA | Ta3_max=32 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| O-DU | T1amin | T1a_min_cp_dl=70 | T1a_min_cp_ul=60 | T1a_min_up=35 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | T1amax | T1a_max_cp_dl=100 | T1a_max_cp_ul=70 | T1a_max_up=50 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta4min | NA | NA | NA | Ta4_min=0 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta4max | NA | NA | NA | Ta4_max=45 |
-+------+------------+-------------------+-------------------+----------------+------------+
-
-|br|
-|br|
-|br|
-
-Table 5. Front Haul Interface Latency (numerology 0 - Sub6)
-
-+------+----------+----------+----------+----------+----------+
-| | Model | C-Plane | U-Plane | | |
-| | Pa | | | | |
-| | rameters | | | | |
-+------+----------+----------+----------+----------+----------+
-| | | DL | UL | DL | UL |
-+------+----------+----------+----------+----------+----------+
-| O-RU | T2amin | T | T | T2a_mi | NA |
-| | | 2a_min_c | 2a_min_c | n_up=200 | |
-| | | p_dl=400 | p_ul=400 | | |
-+------+----------+----------+----------+----------+----------+
-| | T2amax | T2 | T2 | T2a_max | NA |
-| | | a_max_cp | a_max_cp | _up=1120 | |
-| | | _dl=1120 | _ul=1120 | | |
-+------+----------+----------+----------+----------+----------+
-| | | Ta | NA | NA | NA |
-| | | dv_cp_dl | | | |
-+------+----------+----------+----------+----------+----------+
-| | Ta3min | NA | NA | NA | Ta3 |
-| | | | | | _min=160 |
-+------+----------+----------+----------+----------+----------+
-| | Ta3max | NA | NA | NA | Ta3 |
-| | | | | | _max=256 |
-+------+----------+----------+----------+----------+----------+
-| O-DU | T1amin | T | T | T1a_mi | NA |
-| | | 1a_min_c | 1a_min_c | n_up=280 | |
-| | | p_dl=560 | p_ul=480 | | |
-+------+----------+----------+----------+----------+----------+
-| | T1amax | T | T | T1a_ma | NA |
-| | | 1a_max_c | 1a_max_c | x_up=400 | |
-| | | p_dl=800 | p_ul=560 | | |
-+------+----------+----------+----------+----------+----------+
-| | Ta4min | NA | NA | NA | T |
-| | | | | | a4_min=0 |
-+------+----------+----------+----------+----------+----------+
-| | Ta4max | NA | NA | NA | Ta4 |
-| | | | | | _max=360 |
-+------+----------+----------+----------+----------+----------+
-
-|br|
-|br|
-|br|
-
-Table 6. Front Haul Interface Latency (numerology 1 - Sub6)
-
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Model | C-Plane | U-Plane | | |
-| | Parameters | | | | |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | | DL | UL | DL | UL |
-+------+------------+-------------------+-------------------+----------------+------------+
-| O-RU | T2amin | T2a_min_cp_dl=285 | T2a_min_cp_ul=285 | T2a_min_up=71 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | T2amax | T2a_max_cp_dl=429 | T2a_max_cp_ul=429 | T2a_max_up=428 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | | Tadv_cp_dl | NA | NA | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta3min | NA | NA | NA | Ta3_min=20 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta3max | NA | NA | NA | Ta3_max=32 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| O-DU | T1amin | T1a_min_cp_dl=285 | T1a_min_cp_ul=285 | T1a_min_up=96 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | T1amax | T1a_max_cp_dl=429 | T1a_max_cp_ul=300 | T1a_max_up=196 | NA |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta4min | NA | NA | NA | Ta4_min=0 |
-+------+------------+-------------------+-------------------+----------------+------------+
-| | Ta4max | NA | NA | NA | Ta4_max=75 |
-+------+------------+-------------------+-------------------+----------------+------------+
-
-|br|
-|br|
-|br|
-
-IEEE 1588 protocol and PTP for Linux\* implementations are used to
-synchronize local time to GPS time. Details of the configuration used
-are provided in Appendix Appendix 2. Local time is used to get Top of
-the Second (ToS) as a 1pps event for SW implementation. Timing event is
-obtained by performing polling of local time using clock_gettime(CLOCK_REALTIME,..)
-
-All-time intervals are specified with respect to GPS time which
-corresponds to OTA time.
-
-|br|
-|br|
-|br|
-
-Virtualization and Container-Based Usage
-----------------------------------------
-
-xRAN implementation is deployment agnostic and does not require special
-changes to be used in virtualized or |br|
-container-based deployment options.
-The only requirement is to provide one SRIOV base virtual port for
-C-plane and one port for U-plane traffic per O-DU instance. This can be
-achieved with the default Virtual Infrastructure Manager (VIM) as well
-as using standard container networking.
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+Architecture Overview\r
+=====================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+This section provides an overview of the O-RAN architecture.\r
+\r
+.. _introduction-1:\r
+\r
+Introduction\r
+------------\r
+\r
+The front haul interface, according to the O-RAN Fronthaul\r
+specification, is part of the 5G NR L1 reference implementation provided\r
+with the FlexRAN software package. It performs communication between\r
+O-RAN Distributed Unit (O-DU) and O-RAN Radio Unit (O-RU) and consists\r
+of multiple HW and SW components.\r
+\r
+The logical representation of HW and SW components is shown in *Figure\r
+1*.\r
+\r
+The same architecture design is applicable for LTE; however, the FH\r
+library is not integrated with the PHY pipeline for FlexRAN LTE.\r
+\r
+.. image:: images/Architecture-Block-Diagram.jpg\r
+ :width: 600\r
+ :alt: Figure 1. Architecture Block Diagram\r
+\r
+Figure 1. Architecture Block Diagram\r
+\r
+\r
+\r
+\r
+From the hardware perspective, two networking ports are used to\r
+communicate to the Front Haul and Back (Mid) Haul network as well as to\r
+receive PTP synchronization. The system timer is used to provide a\r
+“sense” of time to the gNB application.\r
+\r
+From the software perspective, the following components are used:\r
+\r
+* Linux\* PTP provides synchronization of system timer to GPS time:\r
+ - ptp4l is used to synchronize oscillator on Network Interface Controller (NIC) to PTP GM.\r
+ - phc2sys is used to synchronize system timer to oscillator on NIC.\r
+\r
+* The DPDK to provide the interface to the Ethernet port.\r
+\r
+* xRAN library is built on top of DPDK to perform U-plane and C-plane functionality according to the O-RAN Fronthaul specification.\r
+\r
+* 5GNR reference PHY uses the xRAN library to access interface to O-RU. The interface between the library and PHY is defined to communicate TTI event, symbol time, C-plane information as well as IQ sample data.\r
+\r
+* 5G NR PHY communicates with the L2 application using the set of MAC/PHY APIs and the shared memory interface defined as WLS.\r
+\r
+* L2, in turn, can use Back (Mid) Haul networking port to connect to the CU unit in the context of 3GPP specification.\r
+\r
+In this document, we focus on details of the design and implementation\r
+of the xRAN library for providing Front Haul functionality for both\r
+mmWave and Sub-6 scenarios as well as LTE.\r
+\r
+The xRAN M-plane is not implemented and is outside of the scope of this\r
+description. Configuration files are used to specify selected M-plane\r
+level parameters.\r
+\r
+5G NR L1 Application Threads\r
+----------------------------\r
+\r
+The specifics of the L1 application design and configuration for the\r
+given scenario can be found in document 603577, *FlexRAN 5G NR Reference\r
+Solution RefPHY* (Doxygen) (refer to *Table 2*) Only information\r
+relevant to front haul is presented in this section.\r
+\r
+Configuration of l1app with xRAN interface for Front Haul is illustrated\r
+acting as an O-DU in *Figure 2*.\r
+\r
+.. image:: images/5G-NR-L1app-Threads.jpg\r
+ :width: 600\r
+ :alt: Figure 2. 5G NR L1app Threads\r
+\r
+Figure 2. 5G NR L1app Threads\r
+\r
+In this configuration of L1app, the base architecture of 5G NR L1 is not\r
+changed. The original Front Haul FPGA interface was updated with the\r
+O-RAN fronthaul interface abstracted via the xRAN library.\r
+\r
+O-RAN FH Thread Performs:\r
+\r
+- Symbol base “time event” to the rest of the system based on System Clock synchronized to GPS time via PTP\r
+\r
+- Baseline polling mode driver performing TX and RX of Ethernet packets\r
+\r
+- Most of the packet processing such as Transport header, Application header, Data section header, and interactions with the rest of the PHY processing pipeline.\r
+\r
+- Polling of BBDev for FEC on PAC N3000 acceleration card\r
+\r
+The other threads are standard for the L1app and created the independent\r
+usage of O-RAN as an interface to the Radio.\r
+\r
+Communication between L1 and O-RAN layer is performed using a set of\r
+callback functions where L1 assigned callback and O-RAN layer executes\r
+those functions at a particular event or time moment. Detailed\r
+information on callback function options and setting, as well as design,\r
+can be found in the sections below.\r
+\r
+Design and installation of the l1app do not depend on the Host, VM, or\r
+container environment and the same for all cases.\r
+\r
+Sample Application Thread Model\r
+-------------------------------\r
+\r
+Configuration of a sample application for both the O-DU and O-RU follows\r
+the model of 5G NR l1app application in *Figure 2*, but no BBU or FEC\r
+related threads are needed as minimal O-RAN FH functionality is used\r
+only.\r
+\r
+.. image:: images/Sample-Application-Threads.jpg\r
+ :width: 600\r
+ :alt: Figure 3. Sample Application Threads\r
+\r
+Figure 3. Sample Application Threads\r
+\r
+In this scenario, the main thread is used only for initializing and\r
+closing the application. No execution happens on core 0 during run time.\r
+\r
+Functional Split\r
+----------------\r
+\r
+Figure 1 corresponds to the O-RU part of the O-RAN split.\r
+Implementation of the RU side of the O-RAN protocol is not covered in\r
+this document.\r
+\r
+.. image:: images/eNB-gNB-Architecture-with-O-DU-and-RU.jpg\r
+ :width: 600\r
+ :alt: Figure 4. eNB/gNB Architecture with O-DU and RU\r
+\r
+Figure 4. eNB/gNB Architecture with O-DU and RU\r
+\r
+\r
+\r
+\r
+More than one RU can be supported with the same implementation of the\r
+xRAN library and depends on the configuration of gNB in general. In this\r
+document, we address details of implementation for a single O-DU – O-RU\r
+connection.\r
+\r
+The O-RAN Fronthaul specification provides two categories of the split\r
+of Layer 1 functionality between O-DU and O-RU: Category A and Category\r
+B.\r
+\r
+.. image:: images/Functional-Split.jpg\r
+ :width: 600\r
+ :alt: Figure 5. Functional Split\r
+\r
+Figure 5. Functional Split\r
+\r
+\r
+\r
+Data Flow\r
+---------\r
+\r
+\r
+\r
+Table 3 lists the data flows supported for a single RU with a single\r
+Component Carrier.\r
+\r
+\r
+\r
+\r
+Table 3. Supported Data Flow\r
+\r
++---------+----+-----------------+-----------------+----------------+\r
+| Plane | ID | Name | Contents | Periodicity |\r
++=========+====+=================+=================+================+\r
+| U-Plane | 1a | DL Frequency | DL user data | symbol |\r
+| | | Domain IQ Data | (PDSCH), | |\r
+| | | | control channel | |\r
+| | | | data (PDCCH, | |\r
+| | | | etc.) | |\r
++---------+----+-----------------+-----------------+----------------+\r
+| | 1b | UL Frequency | UL user data | symbol |\r
+| | | Domain IQ Data | (PUSCH), | |\r
+| | | | control channel | |\r
+| | | | data (PUCCH, | |\r
+| | | | etc.) | |\r
++---------+----+-----------------+-----------------+----------------+\r
+| | 1c | PRACH Frequency | UL PRACH data | slot or symbol |\r
+| | | Domain IQ Data | | |\r
++---------+----+-----------------+-----------------+----------------+\r
+| C-Plane | 2a | Scheduling | Scheduling | ~ slot |\r
+| | | Commands | information, | |\r
+| | | | FFT size, CP | |\r
+| | | (Beamforming is | length, | |\r
+| | | not supported) | Subcarrier | |\r
+| | | | spacing, UL | |\r
+| | | | PRACH | |\r
+| | | | scheduling | |\r
++---------+----+-----------------+-----------------+----------------+\r
+| S-Plane | S | Timing and | IEEE 1588 PTP | - |\r
+| | | Synchronization | packets | |\r
++---------+----+-----------------+-----------------+----------------+\r
+\r
+.. image:: images/Data-Flows.jpg\r
+ :width: 600\r
+ :alt: Figure 6. Data Flows\r
+\r
+Figure 6. Data Flows\r
+\r
+\r
+\r
+\r
+Information on specific features of C-Plane and U-plane provided in\r
+Sample Application Section Configuration of S-plane used on\r
+test setup for simulation is provided in Appendix 2.\r
+\r
+Data flow separation is based on VLAN (applicable when layer 2 or layer\r
+3 is used for the C/U-plane transport.)\r
+\r
+* The mechanism for assigning VLAN ID to U-Plane and C-Plane is assumed to be via the M-Plane.\r
+\r
+* VLAN Tag is configurable via the standard Linux IP tool, refer to Appendix A, Setup Configuration.\r
+\r
+* No Quality of Service (QoS) is implemented as part of xRAN library. Standard functionality of ETH port can be used to implement QoS.\r
+\r
+.. image:: images/C-plane-and-U-plane-Packet-Exchange.jpg\r
+ :width: 600\r
+ :alt: Figure 7. C-plane and U-plane Packet Exchange\r
+\r
+Figure 7. C-plane and U-plane Packet Exchange\r
+\r
+\r
+\r
+\r
+Timing, Latency, and Synchronization to GPS\r
+-------------------------------------------\r
+\r
+The O-RAN Fronthaul specification defines the latency model of the front\r
+haul interface and interaction between O-DU and 0-RU. This\r
+implementation of the xRAN library supports only the category with fixed\r
+timing advance and Defined Transport methods. It determines O-DU\r
+transmit and receive windows based on pre-defined transport network\r
+characteristics, and the delay characteristics of the RUs within the\r
+timing domain.\r
+\r
+Table 4 below provides default values used for the implementation of\r
+O-DU – O-RU simulation with mmWave scenario. Table 5 and *Table 6* below\r
+provide default values used for the implementation of O-DU – O-RU\r
+simulation with numerology 0 and numerology 1 for Sub6 scenarios.\r
+Configuration can be adjusted via configuration files for sample\r
+application and reference PHY.\r
+\r
+However, simulation of the different range of the settings was not\r
+performed, and additional implementation changes might be required as\r
+well as testing with actual O-RU. The parameters for the front haul\r
+network are out of scope as a direct connection between O-DU and 0-RU\r
+is used for simulation.\r
+\r
+Table 4. Front Haul Interface Latency (numerology 3 - mmWave)\r
+\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| | Model | C-Plane | U-Plane |\r
+| | Parameters | | |\r
++ + +-------------------+-------------------+----------------+------------+\r
+| | | DL | UL | DL | UL |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| O-RU | T2amin | T2a_min_cp_dl=50 | T2a_min_cp_ul=50 | T2a_min_up=25 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | T2amax | T2a_max_cp_dl=140 | T2a_max_cp_ul=140 | T2a_max_up=140 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | | Tadv_cp_dl | NA | NA | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta3min | NA | NA | NA | Ta3_min=20 |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta3max | NA | NA | NA | Ta3_max=32 |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| O-DU | T1amin | T1a_min_cp_dl=70 | T1a_min_cp_ul=60 | T1a_min_up=35 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | T1amax | T1a_max_cp_dl=100 | T1a_max_cp_ul=70 | T1a_max_up=50 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta4min | NA | NA | NA | Ta4_min=0 |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta4max | NA | NA | NA | Ta4_max=45 |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+\r
+Table 5. Front Haul Interface Latency (numerology 0 - Sub6)\r
+\r
++------+----------+----------+----------+----------+----------+\r
+| | Model | C-Plane | | U-Plane | |\r
+| | Pa | | | | |\r
+| | rameters | | | | |\r
++ + +----------+----------+----------+----------+\r
+| | | DL | UL | DL | UL |\r
++------+----------+----------+----------+----------+----------+\r
+| O-RU | T2amin | T | T | T2a_mi | NA |\r
+| | | 2a_min_c | 2a_min_c | n_up=200 | |\r
+| | | p_dl=400 | p_ul=400 | | |\r
++ +----------+----------+----------+----------+----------+\r
+| | T2amax | T2 | T2 | T2a_max | NA |\r
+| | | a_max_cp | a_max_cp | _up=1120 | |\r
+| | | _dl=1120 | _ul=1120 | | |\r
++ +----------+----------+----------+----------+----------+\r
+| | | Ta | NA | NA | NA |\r
+| | | dv_cp_dl | | | |\r
++ +----------+----------+----------+----------+----------+\r
+| | Ta3min | NA | NA | NA | Ta3 |\r
+| | | | | | _min=160 |\r
++ +----------+----------+----------+----------+----------+\r
+| | Ta3max | NA | NA | NA | Ta3 |\r
+| | | | | | _max=256 |\r
++------+----------+----------+----------+----------+----------+\r
+| O-DU | T1amin | T | T | T1a_mi | NA |\r
+| | | 1a_min_c | 1a_min_c | n_up=280 | |\r
+| | | p_dl=560 | p_ul=480 | | |\r
++ +----------+----------+----------+----------+----------+\r
+| | T1amax | T | T | T1a_ma | NA |\r
+| | | 1a_max_c | 1a_max_c | x_up=400 | |\r
+| | | p_dl=800 | p_ul=560 | | |\r
++ +----------+----------+----------+----------+----------+\r
+| | Ta4min | NA | NA | NA | T |\r
+| | | | | | a4_min=0 |\r
++ +----------+----------+----------+----------+----------+\r
+| | Ta4max | NA | NA | NA | Ta4 |\r
+| | | | | | _max=360 |\r
++------+----------+----------+----------+----------+----------+\r
+\r
+\r
+\r
+\r
+\r
+Table 6. Front Haul Interface Latency (numerology 1 - Sub6)\r
+\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| | Model | C-Plane | U-Plane | | |\r
+| | Parameters | | | | |\r
++ + +-------------------+-------------------+----------------+------------+\r
+| | | DL | UL | DL | UL |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| O-RU | T2amin | T2a_min_cp_dl=285 | T2a_min_cp_ul=285 | T2a_min_up=71 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | T2amax | T2a_max_cp_dl=429 | T2a_max_cp_ul=429 | T2a_max_up=428 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | | Tadv_cp_dl | NA | NA | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta3min | NA | NA | NA | Ta3_min=20 |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta3max | NA | NA | NA | Ta3_max=32 |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+| O-DU | T1amin | T1a_min_cp_dl=285 | T1a_min_cp_ul=285 | T1a_min_up=96 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | T1amax | T1a_max_cp_dl=429 | T1a_max_cp_ul=300 | T1a_max_up=196 | NA |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta4min | NA | NA | NA | Ta4_min=0 |\r
++ +------------+-------------------+-------------------+----------------+------------+\r
+| | Ta4max | NA | NA | NA | Ta4_max=75 |\r
++------+------------+-------------------+-------------------+----------------+------------+\r
+\r
+\r
+\r
+\r
+\r
+IEEE 1588 protocol and PTP for Linux\* implementations are used to\r
+synchronize local time to GPS time. Details of the configuration used\r
+are provided in Appendix B, PTP Configuration. Local time is used to get\r
+Top of the Second (ToS) as a 1 PPS event for SW implementation. Timing\r
+event is obtained by performing polling of local time using\r
+clock_gettime(CLOCK_REALTIME,..)\r
+\r
+All-time intervals are specified concerning the GPS time, which\r
+corresponds to OTA time.\r
+\r
+Virtualization and Container-Based Usage\r
+----------------------------------------\r
+\r
+xRAN implementation is deployment agnostic and does not require special\r
+changes to be used in virtualized or container-based deployment options.\r
+The only requirement is to provide one SRIOV base virtual port for\r
+C-plane and one port for U-plane traffic per O-DU instance. This can be\r
+achieved with the default Virtual Infrastructure Manager (VIM) as well\r
+as using standard container networking.\r
+\r
+\r
+\r
+To configure the networking ports, refer to the FlexRAN and Mobile Edge\r
+Compute (MEC) Platform Setup Guide (*Table 2*) and readme.md in xRAN\r
+library or Appendix A.\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-
-Assumptions and Dependencies
-===============================
-
-.. contents::
- :depth: 3
- :local:
-
-This chapter contains the assumptions, requirements and dependencies for the O-DU Low current implementation.
-
-Assumptions
------------
-
-An L1 with a proprietary interface and a testmac supporting the FAPI interface are available through the Open Source Community(OSC) github in binary blob form and with the reference
-files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU
-High to check network functionality are available from the same site.
-The L1 App and Testmac repository is at https://github.com/intel/FlexRAN/
-
-Requirements
-------------
-* Only Xeon® series Processor with Intel Architecture are supported and the platform should be |br|
- either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency.
-* FPGA/ASIC card for FEC acceleration that is compliant with the BBDev framework and interface. Only needed to run high throughput cases with the HW FEC card assistance.
-* Bios setting steps and options may have differences, however at least you should have the same Bios setting as decribed in the README.md file available at https://github.com/intel/FlexRAN Bios settings section.
-* Running with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.
-
-Dependencies
-------------
-
-* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries).
-
-* RT Kernel kernel-rt-3.10.0-1062.12.1.rt56.1042
-
-* Data Plane Development Kit (DPDK v19.11) with corresponding DPDK patch according to |br| O-RAN FH setup configuration section.
-
-* FEC SDK lib which is needed when you run the FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules
-
-* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you get is always the latest ICC version, the verification for that version might not have been performed yet, please feedback through O-DU Low WIKI page if you meet any issues.
- https://software.intel.com/en-us/system-studio/choose-download
-
-* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App. Only needed to run the sample APP for O-RAN FHI.
-
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+Assumptions, Dependencies, and Constraints\r
+==========================================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+This chapter contains limitations on the scope of the document.\r
+\r
+Assumptions\r
+-----------\r
+\r
+An L1 with a proprietary interface and a testmac supporting the FAPI interface are available through the Open Source Community(OSC) github in binary blob form and with the reference\r
+files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU\r
+High to check network functionality are available from the same site.\r
+The L1 App and Testmac repository is at https://github.com/intel/FlexRAN/\r
+\r
+\r
+Requirements\r
+------------\r
+* Only Xeon® series Processor with Intel Architecture are supported and the platform should be either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency.\r
+* FPGA/ASIC card for FEC acceleration that is compliant with the BBDev framework and interface. Only needed to run high throughput cases with the HW FEC card assistance.\r
+* Bios setting steps and options may have differences, however at least you should have the same Bios setting as decribed in the README.md file available at https://github.com/intel/FlexRAN Bios settings section.\r
+* Running with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.\r
+\r
+\r
+Dependencies\r
+------------\r
+\r
+xRAN library implementation depends on the Data Plane Development Kit\r
+(DPDK v20.11).\r
+\r
+DPDK v20.11 should be patched with corresponding DPDK patch provided\r
+with FlexRAN release (see *Table 1*, FlexRAN Reference Solution Software\r
+Release Notes)\r
+\r
+Intel® C++ Compiler v19.0.3 is used.\r
+\r
+- Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64).\r
+\r
+Constraints\r
+-----------\r
+\r
+This release has been designed and implemented to support the following\r
+numerologies defined in the 3GPP specifications for LTE and 5GNR (refer\r
+to *Table 2*):\r
+\r
+5G NR\r
+~~~~~\r
+\r
+Category A support:\r
+\r
+- Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells\r
+\r
+- Numerology 1 with bandwidth 100 MHz with up to 1 cell\r
+\r
+- Numerology 3 with bandwidth 100 MHz with up to 1 cell\r
+\r
+Category B support:\r
+\r
+Numerology 1 with bandwidth 100 MHz where the antenna panel is up to\r
+64T64R with up to 3 cells.\r
+\r
+LTE\r
+~~~\r
+\r
+Category A support:\r
+\r
+Bandwidth 5/10/20 MHz with up to 12 cells\r
+\r
+Category B support:\r
+\r
+Bandwidth 5/10/20 MHz for 1 cell\r
+\r
+The feature set of O-RAN protocol should be aligned with Radio Unit\r
+(O-RU) implementation. Inter-operability testing (IoT) is required to\r
+confirm the correctness of functionality on both sides. The exact\r
+feature set supported is described in Chapter *4.0* *Transport Layer and\r
+O-RAN Fronthaul Protocol Implementation* of this document.\r
+\r
+-\r
+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-
-O-RAN FH Lib Introduction
-==========================
-
-.. toctree::
- :maxdepth: 2
- :caption: Contents:
-
- Architecture-Overview_fh.rst
- Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst
- xRAN-Library-Design_fh.rst
- Sample-Application_fh.rst
- Setup-Configuration_fh.rst
- PTP-configuration_fh.rst
-
-
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+O-RAN FH Lib Introduction\r
+==========================\r
+\r
+.. toctree::\r
+ :maxdepth: 2\r
+ :caption: Contents:\r
+\r
+ Architecture-Overview_fh.rst\r
+ Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst\r
+ xRAN-Library-Design_fh.rst\r
+ Sample-Application_fh.rst\r
+ Setup-Configuration_fh.rst\r
+ PTP-configuration_fh.rst\r
+ ecpri_ddp_profile.rst\r
+ \r
+\r
+\r
+\r
+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-PTP configuration
-=================
-
-A.5 PTP Synchronization
------------------------
-Precision Time Protocol (PTP) provides an efficient way to synchronize
-time on the network nodes. This protocol uses Primary-Slave architecture.
-Main Reference Clock (Primary) is a reference clock for the other nodes,
-which adapt their clocks to the Primary.
-
-Using Physical Hardware Clock (PHC) from the Main Reference Clock, NIC port
-precision timestamp packets can be served for other network nodes. Secondary
-nodes adjust their PHC to the Primary following the IEEE 1588
-specification.
-
-There are existing implementations of PTP protocol that are widely used
-in the industry. One of them is PTP for Linux, which is a set of tools
-providing necessary PTP functionality. There is no need to re-implement
-the 1588 protocol because PTP for Linux is precise and efficient enough
-to be used out of the box.
-
-To meet xRAN requirements, two tools from PTP for Linux package are
-required: ptp4l and phc2sys.
-
-PTP for Linux\* Requirements
-----------------------------
-
-PTP for Linux\* introduces some software and hardware requirements. The
-machine on which the tools will be run needs to use at least a 3.10
-Kernel version (built-in PTP support). There are several Kernel options
-that need to be enabled in Kernel configuration:
-
-- CONFIG_PPS
-
-- CONFIG_NETWORK_PHY_TIMESTAMPING
-
-- PTP_1588_CLOCK
-
-Be sure that the Kernel is compiled with these options.
-
-For the best precision, PTP uses hardware timestamping. NIC has its own
-clock, called Physical Hardware Clock (PHC) to read current time just a
-moment before the packet is sent to minimalize the delays added by the
-Kernel processing the packet. Not every NIC supports that feature. To
-confirm that currently attached NIC support Hardware Timestamps, use
-ethtool with the command:
-
-ethtool -T eth0
-
-where eth0 is the potential PHC port. The output from the command should
-say that there is Hardware Timestamps support.
-
-To set up PTP for Linux*:
-
-1.Download source code::
-
- git clone http://git.code.sf.net/p/linuxptp/code linuxptp
-
- git checkout v2.0
-
-2.Apply patch (this is required to work around issue with some of the
-GM PTP packet size.)::
-
- diff --git a/msg.c b/msg.c
-
- old mode 100644
-
- new mode 100755
-
- index d1619d4..40d1538
-
- --- a/msg.c
-
- +++ b/msg.c
-
- @@ -399,9 +399,11 @@ int msg_post_recv(struct ptp_message \*m, int cnt)
-
- port_id_post_recv(&m->pdelay_resp.requestingPortIdentity);
-
- break;
-
- case FOLLOW_UP:
-
- + cnt -= 4;
-
- timestamp_post_recv(m, &m->follow_up.preciseOriginTimestamp);
-
- break;
-
- case DELAY_RESP:
-
- + cnt -= 4;
-
- timestamp_post_recv(m, &m->delay_resp.receiveTimestamp);
-
- port_id_post_recv(&m->delay_resp.requestingPortIdentity);
-
- break;
-
-3.Build and install ptp41::
-
- # make && make install
-
-4.Modify configs/default.cfg to control frequency of Sync interval to
-0.0625s::
-
- logSyncInterval -4
-
-ptp4l
-----------
-
-This tool handles all PTP traffic on the provided NIC port and updated
-PHC. It also determines the Primary Reference Clock and tracks synchronization
-status. This tool can be run as a daemon or as a regular Linux\*
-application. When the synchronization is reached, it gives output on the
-screen for precision tracking. The configuration file of ptp4l contains
-many options that can be set to get the best synchronization precision.
-Although, even with default.cfg the synchronization quality is good.
-
-To start the synchronization process run::
-
- cd linuxptp
-
- ./ptp4l -f ./configs/default.cfg -2 -i <if_name> -m
-
-The output below shows what the output on non-Primary node should look
-like when synchronization is started. This means that PHC on this
-machine is synchronized to the Primary PHC::
-
- ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[1434166.384]: port 1: new foreign primary fcaf6a.fffe.029708-1
-
- ptp4l[1434170.352]: selected best primary clock fcaf6a.fffe.029708
-
- ptp4l[1434170.352]: updating UTC offset to 37
-
- ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
-
- ptp4l[1434171.763]: primary offset -5873 s0 freq -18397 path delay 2778
-
- ptp4l[1434172.763]: primary offset -6088 s2 freq -18612 path delay 2778
-
- ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on
- MASTER_CLOCK_SELECTED
-
- ptp4l[1434173.763]: primary offset -5886 s2 freq -24498 path delay 2732
-
- ptp4l[1434174.763]: primary offset 221 s2 freq -20157 path delay 2728
-
- ptp4l[1434175.763]: primary offset 1911 s2 freq -18401 path delay 2724
-
- ptp4l[1434176.763]: primary offset 1774 s2 freq -17964 path delay 2728
-
- ptp4l[1434177.763]: primary offset 1198 s2 freq -18008 path delay 2728
-
- ptp4l[1434178.763]: primary offset 746 s2 freq -18101 path delay 2755
-
- ptp4l[1434179.763]: primary offset 218 s2 freq -18405 path delay 2792
-
- ptp4l[1434180.763]: primary offset 103 s2 freq -18454 path delay 2792
-
- ptp4l[1434181.763]: primary offset -13 s2 freq -18540 path delay 2813
-
- ptp4l[1434182.763]: primary offset 9 s2 freq -18521 path delay 2813
-
- ptp4l[1434183.763]: primary offset 11 s2 freq -18517 path delay 2813
-
-phc2sys
------------
-
-The PHC clock is independent from the system clock. Synchronizing only
-PHC does not make the system clock exactly the same as the primary. The
-xRAN library requires use of the system clock to determine a common
-point in time on two machines (O-DU and RU) to start transmission at the
-same moment and keep time frames defined by ORAN Fronthaul specification.
-
-This application keeps the system clock updated to PHC. It makes it
-possible to use POSIX timers as a time reference in xRAN application.
-
-Run phc2sys with the command::
-
- cd linuxptp
-
- ./phc2sys -s enp25s0f0 -w -m -R 8
-
-Command output will look like::
-
- ptp4l[1434165.342]: selected /dev/ptp4 as PTP
-
- phc2sys[1434344.651]: CLOCK_REALTIME phc offset 450 s2 freq -39119 delay
- 1354
-
- phc2sys[1434344.776]: CLOCK_REALTIME phc offset 499 s2 freq -38620 delay
- 1344
-
- phc2sys[1434344.902]: CLOCK_REALTIME phc offset 485 s2 freq -38484 delay
- 1347
-
- phc2sys[1434345.027]: CLOCK_REALTIME phc offset 476 s2 freq -38348 delay
- 1346
-
- phc2sys[1434345.153]: CLOCK_REALTIME phc offset 392 s2 freq -38289 delay
- 1340
-
- phc2sys[1434345.278]: CLOCK_REALTIME phc offset 319 s2 freq -38244 delay
- 1340
-
- phc2sys[1434345.404]: CLOCK_REALTIME phc offset 278 s2 freq -38190 delay
- 1349
-
- phc2sys[1434345.529]: CLOCK_REALTIME phc offset 221 s2 freq -38163 delay
- 1343
-
- phc2sys[1434345.654]: CLOCK_REALTIME phc offset 97 s2 freq -38221 delay
- 1342
-
- phc2sys[1434345.780]: CLOCK_REALTIME phc offset 67 s2 freq -38222 delay
- 1344
-
- phc2sys[1434345.905]: CLOCK_REALTIME phc offset 68 s2 freq -38201 delay
- 1341
-
- phc2sys[1434346.031]: CLOCK_REALTIME phc offset 104 s2 freq -38144 delay
- 1340
-
- phc2sys[1434346.156]: CLOCK_REALTIME phc offset 58 s2 freq -38159 delay
- 1340
-
- phc2sys[1434346.281]: CLOCK_REALTIME phc offset 12 s2 freq -38188 delay
- 1343
-
- phc2sys[1434346.407]: CLOCK_REALTIME phc offset -36 s2 freq -38232 delay
- 1342
-
- phc2sys[1434346.532]: CLOCK_REALTIME phc offset -103 s2 freq -38310
- delay 1348
-
-Configuration C3
-------------------
-
-Configuration C3 27 can be simulated for O-DU using a separate server
-acting as Fronthaul Network and O-RU at the same time. O-RU server can
-be configured to relay PTP and act as PTP primary for O-DU. Settings
-below can be used to instantiate this scenario. The difference is that
-on the O-DU side, the Fronthaul port can be used as the source of PTP as
-well as for U-plane and C-plane traffic.
-
-1.Follow the steps in Section A.6.1 to install PTP on the O-RU server.
-
-2.Copy configs/default.cfg to configs/default_slave.cfg and modify the
-copied file as below::
-
- diff --git a/configs/default.cfg b/configs/default.cfg
-
- old mode 100644
-
- new mode 100755
-
- index e23dfd7..f1ecaf1
-
- --- a/configs/default.cfg
-
- +++ b/configs/default.cfg
-
- @@ -3,26 +3,26 @@
-
- # Default Data Set
-
- #
-
- twoStepFlag 1
-
- -slaveOnly 0
-
- +slaveOnly 1
-
- priority1 128
-
- -priority2 128
-
- +priority2 255
-
- domainNumber 0
-
- #utc_offset 37
-
- -clockClass 248
-
- +clockClass 255
-
- clockAccuracy 0xFE
-
- offsetScaledLogVariance 0xFFFF
-
- free_running 0
-
- freq_est_interval 1
-
- dscp_event 0
-
- dscp_general 0
-
- -dataset_comparison ieee1588
-
- +dataset_comparison G.8275.x
-
- G.8275.defaultDS.localPriority 128
-
- maxStepsRemoved 255
-
- #
-
- # Port Data Set
-
- #
-
- logAnnounceInterval 1
-
- -logSyncInterval 0
-
- +logSyncInterval -4
-
- operLogSyncInterval 0
-
- logMinDelayReqInterval 0
-
- logMinPdelayReqInterval 0
-
- @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128
-
- asCapable auto
-
- BMCA ptp
-
- inhibit_announce 0
-
- -inhibit_pdelay_req 0
-
- +#inhibit_pdelay_req 0
-
- ignore_source_id 0
-
- #
-
- # Run time options
-
-1.Start secondary port toward PTP GM::
-
- ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 –m
-
-Example of output::
-
- ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 -m
-
- ptp4l[3904470.256]: selected /dev/ptp6 as PTP clock
-
- ptp4l[3904470.274]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[3904470.275]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[3904471.085]: port 1: new foreign primary fcaf6a.fffe.029708-1
-
- ptp4l[3904475.053]: selected best primary clock fcaf6a.fffe.029708
-
- ptp4l[3904475.053]: updating UTC offset to 37
-
- ptp4l[3904475.053]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
-
- ptp4l[3904477.029]: primary offset 196 s0 freq -18570 path delay 1109
-
- ptp4l[3904478.029]: primary offset 212 s2 freq -18554 path delay 1109
-
- ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on
- MASTER_CLOCK_SELECTED
-
- ptp4l[3904479.029]: primary offset 86 s2 freq -18468 path delay 1109
-
- ptp4l[3904480.029]: primary offset 23 s2 freq -18505 path delay 1124
-
- ptp4l[3904481.029]: primary offset 3 s2 freq -18518 path delay 1132
-
- ptp4l[3904482.029]: primary offset -169 s2 freq -18689 path delay 1141
-
-2.Synchronize local timer clock on O-RU for sample application::
-
- ./phc2sys -s enp25s0f0 -w -m -R 8
-
-Example of output::
-
- ./phc2sys -s enp25s0f0 -w -m -R 8
-
- phc2sys[3904510.892]: CLOCK_REALTIME phc offset 343 s0 freq -38967 delay
- 1530
-
- phc2sys[3904511.017]: CLOCK_REALTIME phc offset 368 s2 freq -38767 delay
- 1537
-
- phc2sys[3904511.142]: CLOCK_REALTIME phc offset 339 s2 freq -38428 delay
- 1534
-
- phc2sys[3904511.267]: CLOCK_REALTIME phc offset 298 s2 freq -38368 delay
- 1532
-
- phc2sys[3904511.392]: CLOCK_REALTIME phc offset 239 s2 freq -38337 delay
- 1534
-
- phc2sys[3904511.518]: CLOCK_REALTIME phc offset 145 s2 freq -38360 delay
- 1530
-
- phc2sys[3904511.643]: CLOCK_REALTIME phc offset 106 s2 freq -38355 delay
- 1527
-
- phc2sys[3904511.768]: CLOCK_REALTIME phc offset -30 s2 freq -38459 delay
- 1534
-
- phc2sys[3904511.893]: CLOCK_REALTIME phc offset -92 s2 freq -38530 delay
- 1530
-
- phc2sys[3904512.018]: CLOCK_REALTIME phc offset -173 s2 freq -38639
- delay 1528
-
- phc2sys[3904512.143]: CLOCK_REALTIME phc offset -246 s2 freq -38764
- delay 1530
-
- phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892
- delay 1532
-
-3. Modify configs/default.cfg as shown below to run PTP primary on
-Fronthaul of O-RU::
-
- diff --git a/configs/default.cfg b/configs/default.cfg
-
- old mode 100644
-
- new mode 100755
-
- index e23dfd7..c9e9d4c
-
- --- a/configs/default.cfg
-
- +++ b/configs/default.cfg
-
- @@ -15,14 +15,14 @@ free_running 0
-
- freq_est_interval 1
-
- dscp_event 0
-
- dscp_general 0
-
- -dataset_comparison ieee1588
-
- +dataset_comparison G.8275.x
-
- G.8275.defaultDS.localPriority 128
-
- maxStepsRemoved 255
-
- #
-
- # Port Data Set
-
- #
-
- logAnnounceInterval 1
-
- -logSyncInterval 0
-
- +logSyncInterval -4
-
- operLogSyncInterval 0
-
- logMinDelayReqInterval 0
-
- logMinPdelayReqInterval 0
-
- @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128
-
- asCapable auto
-
- BMCA ptp
-
- inhibit_announce 0
-
- -inhibit_pdelay_req 0
-
- +#inhibit_pdelay_req 0
-
- ignore_source_id 0
-
- #
-
- # Run time options
-
-4.Start PTP primary toward O-DU::
-
- ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 –m
-
-Example of output::
-
- ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 -m
-
- ptp4l[3903857.249]: selected /dev/ptp3 as PTP clock
-
- ptp4l[3903857.266]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[3903857.267]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[3903863.734]: port 1: LISTENING to MASTER on
- ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
-
- ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best
- primary
-
- ptp4l[3903863.734]: assuming the main reference role
-
-5.Synchronize local NIC PTP primary clock to local NIC PTP secondary clock::
-
- ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
-
-Example of output::
-
- ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
-
- phc2sys[3904600.332]: enp175s0f1 phc offset 2042 s0 freq -2445 delay
- 4525
-
- phc2sys[3904600.458]: enp175s0f1 phc offset 2070 s2 freq -2223 delay
- 4506
-
- phc2sys[3904600.584]: enp175s0f1 phc offset 2125 s2 freq -98 delay 4505
-
- phc2sys[3904600.710]: enp175s0f1 phc offset 1847 s2 freq +262 delay 4518
-
- phc2sys[3904600.836]: enp175s0f1 phc offset 1500 s2 freq +469 delay 4515
-
- phc2sys[3904600.961]: enp175s0f1 phc offset 1146 s2 freq +565 delay 4547
-
- phc2sys[3904601.086]: enp175s0f1 phc offset 877 s2 freq +640 delay 4542
-
- phc2sys[3904601.212]: enp175s0f1 phc offset 517 s2 freq +543 delay 4517
-
- phc2sys[3904601.337]: enp175s0f1 phc offset 189 s2 freq +370 delay 4510
-
- phc2sys[3904601.462]: enp175s0f1 phc offset -125 s2 freq +113 delay 4554
-
- phc2sys[3904601.587]: enp175s0f1 phc offset -412 s2 freq -212 delay 4513
-
- phc2sys[3904601.712]: enp175s0f1 phc offset -693 s2 freq -617 delay 4519
-
- phc2sys[3904601.837]: enp175s0f1 phc offset -878 s2 freq -1009 delay
- 4515
-
- phc2sys[3904601.962]: enp175s0f1 phc offset -965 s2 freq -1360 delay
- 4518
-
- phc2sys[3904602.088]: enp175s0f1 phc offset -1048 s2 freq -1732 delay
- 4510
-
- phc2sys[3904602.213]: enp175s0f1 phc offset -1087 s2 freq -2086 delay
- 4531
-
- phc2sys[3904602.338]: enp175s0f1 phc offset -1014 s2 freq -2339 delay
- 4528
-
- phc2sys[3904602.463]: enp175s0f1 phc offset -1009 s2 freq -2638 delay
- 4531
-
-6. On O-DU Install PTP for Linux tools from source code the same way as
-on O-RU above but no need to apply the patch for msg.c
-
-7. Start secondary port toward PTP primary from O-RU using the same
-default_slave.cfg as on O-RU (see above)::
-
- ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 –m
-
-Example of output::
-
- ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 -m
-
- ptp4l[809092.918]: selected /dev/ptp6 as PTP clock
-
- ptp4l[809092.934]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[809092.934]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
-
- ptp4l[809092.949]: port 1: new foreign primary 3cfdfe.fffe.bd005d-1
-
- ptp4l[809096.949]: selected best primary clock 3cfdfe.fffe.bd005d
-
- ptp4l[809096.950]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
-
- ptp4l[809098.363]: port 1: UNCALIBRATED to SLAVE on
- MASTER_CLOCK_SELECTED
-
- ptp4l[809099.051]: rms 38643 max 77557 freq +719 +/- 1326 delay 1905 +/-
- 0
-
- ptp4l[809100.051]: rms 1134 max 1935 freq -103 +/- 680 delay 1891 +/- 4
-
- ptp4l[809101.051]: rms 453 max 855 freq +341 +/- 642 delay 1888 +/- 0
-
- ptp4l[809102.052]: rms 491 max 772 freq +1120 +/- 752 delay 1702 +/- 0
-
- ptp4l[809103.052]: rms 423 max 654 freq +1352 +/- 653 delay 1888 +/- 0
-
- ptp4l[809104.052]: rms 412 max 579 freq +1001 +/- 672 delay 1702 +/- 0
-
- ptp4l[809105.053]: rms 441 max 672 freq +807 +/- 709 delay 1826 +/- 88
-
- ptp4l[809106.053]: rms 422 max 607 freq +1353 +/- 636 delay 1702 +/- 0
-
- ptp4l[809107.054]: rms 401 max 466 freq +946 +/- 646 delay 1702 +/- 0
-
- ptp4l[809108.055]: rms 401 max 502 freq +912 +/- 659
-
-8. Synchronize local clock on O-DU for sample application or l1
-application::
-
- ./phc2sys -s enp181s0f0 -w -m -R 8
-
-Example of output::
-
- ./phc2sys -s enp181s0f0 -w -m -R 8
-
- phc2sys[809127.123]: CLOCK_REALTIME phc offset 675 s0 freq -37379 delay
- 1646
-
- phc2sys[809127.249]: CLOCK_REALTIME phc offset 696 s2 freq -37212 delay
- 1654
-
- phc2sys[809127.374]: CLOCK_REALTIME phc offset 630 s2 freq -36582 delay
- 1648
-
- phc2sys[809127.500]: CLOCK_REALTIME phc offset 461 s2 freq -36562 delay
- 1642
-
- phc2sys[809127.625]: CLOCK_REALTIME phc offset 374 s2 freq -36510 delay
- 1643
-
- phc2sys[809127.751]: CLOCK_REALTIME phc offset 122 s2 freq -36650 delay
- 1649
-
- phc2sys[809127.876]: CLOCK_REALTIME phc offset 34 s2 freq -36702 delay
- 1650
-
- phc2sys[809128.002]: CLOCK_REALTIME phc offset -112 s2 freq -36837 delay
- 1645
-
- phc2sys[809128.127]: CLOCK_REALTIME phc offset -160 s2 freq -36919 delay
- 1643
-
- phc2sys[809128.252]: CLOCK_REALTIME phc offset -270 s2 freq -37077 delay
- 1657
-
- phc2sys[809128.378]: CLOCK_REALTIME phc offset -285 s2 freq -37173 delay
- 1644
-
- phc2sys[809128.503]: CLOCK_REALTIME phc offset -349 s2 freq -37322 delay
- 1644
-
- phc2sys[809128.629]: CLOCK_REALTIME phc offset -402 s2 freq -37480 delay
- 1641
-
- phc2sys[809128.754]: CLOCK_REALTIME phc offset -377 s2 freq -37576 delay
- 1648
-
- phc2sys[809128.879]: CLOCK_REALTIME phc offset -467 s2 freq -37779 delay
- 1650
-
- phc2sys[809129.005]: CLOCK_REALTIME phc offset -408 s2 freq -37860 delay
- 1648
-
- phc2sys[809129.130]: CLOCK_REALTIME phc offset -480 s2 freq -38054 delay
- 1655
-
- phc2sys[809129.256]: CLOCK_REALTIME phc offset -350 s2 freq -38068 delay
- 1650
-
-Support in xRAN Library
-----------------------------
-
-The xRAN library provides an API to check whether PTP for Linux is
-running correctly. There is a function called xran_is_synchronized(). It
-checks if ptp4l and phc2sys are running in the system by making PMC tool
-requests for current port state and comparing it with the expected
-value. This verification should be done before initialization.
-
-*notes. “SECONDARY” is the only expected value in this release; only a
-non-primary scenario is supported currently.*
-
-*notes1. Inclusive language terms were used except for the PTP traces where the source code has
-not been updated to support the inclusive language terms yet.*
-
-.. |image0| image:: media/image3.png
- :width: 2.52364in
- :height: 3.77174in
-.. |image1| image:: media/image8.png
- :width: 6.258in
- :height: 1.40538in
-.. |image2| image:: media/image10.emf
- :width: 6.18493in
- :height: 0.53448in
-.. |image3| image:: media/image15.png
- :width: 6.27856in
- :height: 2.672in
-.. |image4| image:: media/image21.JPG
- :width: 6.17708in
- :height: 6.09375in
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+PTP Configuration\r
+=================\r
+\r
+PTP Synchronization\r
+===================\r
+\r
+Precision Time Protocol (PTP) provides an efficient way to synchronize\r
+time on the network nodes. This protocol uses Master-Slave architecture.\r
+Grandmaster Clock (Master) is a reference clock for the other nodes,\r
+which adapt their clocks to the master.\r
+\r
+Using Physical Hardware Clock (PHC) from the Grandmaster Clock, NIC port\r
+precision timestamp packets can be served for other network nodes. Slave\r
+nodes adjust their PHC to the master following the IEEE 1588\r
+specification.\r
+\r
+There are existing implementations of PTP protocol that are widely used\r
+in the industry. One of them is PTP for Linux, which is a set of tools\r
+providing necessary PTP functionality. There is no need to re-implement\r
+the 1588 protocol because PTP for Linux is precise and efficient enough\r
+to be used out of the box.\r
+\r
+To meet O-RAN requirements, two tools from PTP for Linux package are\r
+required: ptp4l and phc2sys.\r
+\r
+PTP for Linux\* Requirements\r
+============================\r
+\r
+PTP for Linux\* introduces some software and hardware requirements. The\r
+machine on which the tools will be run needs to use at least a 3.10\r
+Kernel version (built-in PTP support). Several Kernel options need to be\r
+enabled in Kernel configuration:\r
+\r
+- CONFIG_PPS\r
+\r
+- CONFIG_NETWORK_PHY_TIMESTAMPING\r
+\r
+- PTP_1588_CLOCK\r
+\r
+Be sure that the Kernel is compiled with these options.\r
+\r
+For the best precision, PTP uses hardware timestamping. NIC has its own\r
+clock, called Physical Hardware Clock (PHC), to read current time just a\r
+moment before the packet is sent to minimalize the delays added by the\r
+Kernel processing the packet. Not every NIC supports that feature. To\r
+confirm that currently attached NIC support Hardware Timestamps, use\r
+ethtool with the command::\r
+\r
+ ethtool -T eth0\r
+\r
+Where the eth0 is the potential PHC port. The output from the command\r
+should say that there is Hardware Timestamps support.\r
+\r
+To set up PTP for Linux*:\r
+\r
+1. Download source code::\r
+\r
+ git clone http://git.code.sf.net/p/linuxptp/code linuxptp\r
+ git checkout v2.0\r
+\r
+*Note* Apply patch (this is required to work around an issue with some of the GM PTP packet sizes.) ::\r
+\r
+ diff --git a/msg.c b/msg.c\r
+ old mode 100644\r
+ new mode 100755\r
+ index d1619d4..40d1538\r
+ --- a/msg.c\r
+ +++ b/msg.c\r
+ @@ -399,9 +399,11 @@ int msg_post_recv(struct ptp_message *m, int cnt)\r
+ port_id_post_recv(&m->pdelay_resp.requestingPortIdentity);\r
+ break;\r
+ case FOLLOW_UP:\r
+ + cnt -= 4;\r
+ timestamp_post_recv(m, &m->follow_up.preciseOriginTimestamp);\r
+ break;\r
+ case DELAY_RESP:\r
+ + cnt -= 4;\r
+ timestamp_post_recv(m, &m->delay_resp.receiveTimestamp);\r
+ port_id_post_recv(&m->delay_resp.requestingPortIdentity);\r
+ break;\r
+\r
+2. Build and install ptp41. ::\r
+\r
+ # make && make install\r
+\r
+22. Modify configs/default.cfg to control frequency of Sync interval to 0.0625 s. ::\r
+\r
+ logSyncInterval -4\r
+\r
+ptp4l\r
+=====\r
+\r
+This tool handles all PTP traffic on the provided NIC port and updated\r
+PHC. It also determines the Grandmaster Clock and tracks synchronization\r
+status. This tool can be run as a daemon or as a regular Linux\*\r
+application. When the synchronization is reached, it gives output on the\r
+screen for precision tracking. The configuration file of ptp4l contains\r
+many options that can be set to get the best synchronization precision.\r
+Although, even with default.cfg the synchronization quality is\r
+excellent.\r
+\r
+To start the synchronization process run::\r
+\r
+ cd linuxptp\r
+ ./ptp4l -f ./configs/default.cfg -2 -i <if_name> -m\r
+\r
+The output below shows what the output on non-master node should look\r
+like when synchronization is started. This means that PHC on this\r
+machine is synchronized to the master PHC. ::\r
+\r
+ ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[1434166.384]: port 1: new foreign master fcaf6a.fffe.029708-1\r
+ ptp4l[1434170.352]: selected best master clock fcaf6a.fffe.029708\r
+ ptp4l[1434170.352]: updating UTC offset to 37\r
+ ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE\r
+ ptp4l[1434171.763]: master offset -5873 s0 freq -18397 path delay 2778\r
+ ptp4l[1434172.763]: master offset -6088 s2 freq -18612 path delay 2778\r
+ ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED\r
+ ptp4l[1434173.763]: master offset -5886 s2 freq -24498 path delay 2732\r
+ ptp4l[1434174.763]: master offset 221 s2 freq -20157 path delay 2728\r
+ ptp4l[1434175.763]: master offset 1911 s2 freq -18401 path delay 2724\r
+ ptp4l[1434176.763]: master offset 1774 s2 freq -17964 path delay 2728\r
+ ptp4l[1434177.763]: master offset 1198 s2 freq -18008 path delay 2728\r
+ ptp4l[1434178.763]: master offset 746 s2 freq -18101 path delay 2755\r
+ ptp4l[1434179.763]: master offset 218 s2 freq -18405 path delay 2792\r
+ ptp4l[1434180.763]: master offset 103 s2 freq -18454 path delay 2792\r
+ ptp4l[1434181.763]: master offset -13 s2 freq -18540 path delay 2813\r
+ ptp4l[1434182.763]: master offset 9 s2 freq -18521 path delay 2813\r
+ ptp4l[1434183.763]: master offset 11 s2 freq -18517 path delay 2813\r
+\r
+phc2sys\r
+=======\r
+\r
+The PHC clock is independent from the system clock. Synchronizing only\r
+PHC does not make the system clock exactly the same as the master. The\r
+xRAN library requires use of the system clock to determine a common\r
+point in time on two machines (O-DU and RU) to start transmission at the\r
+same moment and keep time frames defined by O-RAN Fronthaul\r
+specification.\r
+\r
+This application keeps the system clock updated to PHC. It makes it\r
+possible to use POSIX timers as a time reference in xRAN application.\r
+\r
+Run phc2sys with the command::\r
+\r
+ cd linuxptp\r
+ ./phc2sys -s enp25s0f0 -w -m -R 8\r
+\r
+Command output will look like::\r
+\r
+ ptp4l[1434165.342]: selected /dev/ptp4 as PTP \r
+ phc2sys[1434344.651]: CLOCK_REALTIME phc offset 450 s2 freq -39119 delay 1354\r
+ phc2sys[1434344.776]: CLOCK_REALTIME phc offset 499 s2 freq -38620 delay 1344\r
+ phc2sys[1434344.902]: CLOCK_REALTIME phc offset 485 s2 freq -38484 delay 1347\r
+ phc2sys[1434345.027]: CLOCK_REALTIME phc offset 476 s2 freq -38348 delay 1346\r
+ phc2sys[1434345.153]: CLOCK_REALTIME phc offset 392 s2 freq -38289 delay 1340\r
+ phc2sys[1434345.278]: CLOCK_REALTIME phc offset 319 s2 freq -38244 delay 1340\r
+ phc2sys[1434345.404]: CLOCK_REALTIME phc offset 278 s2 freq -38190 delay 1349\r
+ phc2sys[1434345.529]: CLOCK_REALTIME phc offset 221 s2 freq -38163 delay 1343\r
+ phc2sys[1434345.654]: CLOCK_REALTIME phc offset 97 s2 freq -38221 delay 1342\r
+ phc2sys[1434345.780]: CLOCK_REALTIME phc offset 67 s2 freq -38222 delay 1344\r
+ phc2sys[1434345.905]: CLOCK_REALTIME phc offset 68 s2 freq -38201 delay 1341\r
+ phc2sys[1434346.031]: CLOCK_REALTIME phc offset 104 s2 freq -38144 delay 1340\r
+ phc2sys[1434346.156]: CLOCK_REALTIME phc offset 58 s2 freq -38159 delay 1340\r
+ phc2sys[1434346.281]: CLOCK_REALTIME phc offset 12 s2 freq -38188 delay 1343\r
+ phc2sys[1434346.407]: CLOCK_REALTIME phc offset -36 s2 freq -38232 delay 1342\r
+ phc2sys[1434346.532]: CLOCK_REALTIME phc offset -103 s2 freq -38310 delay 1348\r
+\r
+Configuration C3\r
+================\r
+\r
+Configuration C3 27 can be simulated for O-DU using a separate server\r
+acting as Fronthaul Network and O-RU at the same time. O-RU server can\r
+be configured to relay PTP and act as PTP master for O-DU. Settings\r
+below can be used to instantiate this scenario. The difference is that\r
+on the O-DU side, the Fronthaul port can be used as the source of PTP as\r
+well as for U-plane and C-plane traffic.\r
+\r
+1. Follow the steps in Appendix *B.1.1,* *PTP for Linux\* Requirements*\r
+to install PTP on the O-RU server.\r
+\r
+2. Copy configs/default.cfg to configs/default_slave.cfg and modify the\r
+Copied file as below::\r
+\r
+ diff --git a/configs/default.cfg b/configs/default.cfg\r
+ old mode 100644\r
+ new mode 100755\r
+ index e23dfd7..f1ecaf1\r
+ --- a/configs/default.cfg\r
+ +++ b/configs/default.cfg\r
+ @@ -3,26 +3,26 @@\r
+ # Default Data Set\r
+ #\r
+ twoStepFlag 1\r
+ -slaveOnly 0\r
+ +slaveOnly 1\r
+ priority1 128\r
+ -priority2 128\r
+ +priority2 255\r
+ domainNumber 0\r
+ #utc_offset 37\r
+ -clockClass 248\r
+ +clockClass 255\r
+ clockAccuracy 0xFE\r
+ offsetScaledLogVariance 0xFFFF\r
+ free_running 0\r
+ freq_est_interval 1\r
+ dscp_event 0\r
+ dscp_general 0\r
+ -dataset_comparison ieee1588\r
+ +dataset_comparison G.8275.x\r
+ G.8275.defaultDS.localPriority 128\r
+ maxStepsRemoved 255\r
+ #\r
+ # Port Data Set\r
+ #\r
+ logAnnounceInterval 1\r
+ -logSyncInterval 0\r
+ +logSyncInterval -4\r
+ operLogSyncInterval 0\r
+ logMinDelayReqInterval 0\r
+ logMinPdelayReqInterval 0\r
+ @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128\r
+ asCapable auto\r
+ BMCA ptp\r
+ inhibit_announce 0\r
+ -inhibit_pdelay_req 0\r
+ +#inhibit_pdelay_req 0\r
+ ignore_source_id 0\r
+ #\r
+ # Run time options\r
+\r
+\r
+3. Start slave port toward PTP GM::\r
+\r
+ ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 –m\r
+\r
+Example of output::\r
+\r
+ ./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 -m\r
+ ptp4l[3904470.256]: selected /dev/ptp6 as PTP clock\r
+ ptp4l[3904470.274]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[3904470.275]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[3904471.085]: port 1: new foreign master fcaf6a.fffe.029708-1\r
+ ptp4l[3904475.053]: selected best master clock fcaf6a.fffe.029708\r
+ ptp4l[3904475.053]: updating UTC offset to 37\r
+ ptp4l[3904475.053]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE\r
+ ptp4l[3904477.029]: master offset 196 s0 freq -18570 path delay 1109\r
+ ptp4l[3904478.029]: master offset 212 s2 freq -18554 path delay 1109\r
+ ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED\r
+ ptp4l[3904479.029]: master offset 86 s2 freq -18468 path delay 1109\r
+ ptp4l[3904480.029]: master offset 23 s2 freq -18505 path delay 1124\r
+ ptp4l[3904481.029]: master offset 3 s2 freq -18518 path delay 1132\r
+ ptp4l[3904482.029]: master offset -169 s2 freq -18689 path delay 1141\r
+\r
+4. Synchronize local timer clock on O-RU for sample application ::\r
+\r
+ ./phc2sys -s enp25s0f0 -w -m -R 8\r
+\r
+Example of output::\r
+\r
+ ./phc2sys -s enp25s0f0 -w -m -R 8\r
+ phc2sys[3904510.892]: CLOCK_REALTIME phc offset 343 s0 freq -38967 delay 1530\r
+ phc2sys[3904511.017]: CLOCK_REALTIME phc offset 368 s2 freq -38767 delay 1537\r
+ phc2sys[3904511.142]: CLOCK_REALTIME phc offset 339 s2 freq -38428 delay 1534\r
+ phc2sys[3904511.267]: CLOCK_REALTIME phc offset 298 s2 freq -38368 delay 1532\r
+ phc2sys[3904511.392]: CLOCK_REALTIME phc offset 239 s2 freq -38337 delay 1534\r
+ phc2sys[3904511.518]: CLOCK_REALTIME phc offset 145 s2 freq -38360 delay 1530\r
+ phc2sys[3904511.643]: CLOCK_REALTIME phc offset 106 s2 freq -38355 delay 1527\r
+ phc2sys[3904511.768]: CLOCK_REALTIME phc offset -30 s2 freq -38459 delay 1534\r
+ phc2sys[3904511.893]: CLOCK_REALTIME phc offset -92 s2 freq -38530 delay 1530\r
+ phc2sys[3904512.018]: CLOCK_REALTIME phc offset -173 s2 freq -38639 delay 1528\r
+ phc2sys[3904512.143]: CLOCK_REALTIME phc offset -246 s2 freq -38764 delay 1530\r
+ phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892 delay 1532\r
+\r
+5. Modify configs/default.cfg as shown below to run PTP master on Fronthaul of O-RU. ::\r
+\r
+ diff --git a/configs/default.cfg b/configs/default.cfg\r
+ old mode 100644\r
+ new mode 100755\r
+ index e23dfd7..c9e9d4c\r
+ --- a/configs/default.cfg\r
+ +++ b/configs/default.cfg\r
+ @@ -15,14 +15,14 @@ free_running 0\r
+ freq_est_interval 1\r
+ dscp_event 0\r
+ dscp_general 0\r
+ -dataset_comparison ieee1588\r
+ +dataset_comparison G.8275.x\r
+ G.8275.defaultDS.localPriority 128\r
+ maxStepsRemoved 255\r
+ #\r
+ # Port Data Set\r
+ #\r
+ logAnnounceInterval 1\r
+ -logSyncInterval 0\r
+ +logSyncInterval -4\r
+ operLogSyncInterval 0\r
+ logMinDelayReqInterval 0\r
+ logMinPdelayReqInterval 0\r
+ @@ -37,7 +37,7 @@ G.8275.portDS.localPriority 128\r
+ asCapable auto\r
+ BMCA ptp\r
+ inhibit_announce 0\r
+ -inhibit_pdelay_req 0\r
+ +#inhibit_pdelay_req 0\r
+ ignore_source_id 0\r
+ # \r
+ # Run time options\r
+\r
+6. Start PTP master toward O-DU::\r
+\r
+ ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 –m\r
+\r
+Example of output::\r
+\r
+ ./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 -m\r
+ ptp4l[3903857.249]: selected /dev/ptp3 as PTP clock\r
+ ptp4l[3903857.266]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[3903857.267]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[3903863.734]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES\r
+ ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best master\r
+ ptp4l[3903863.734]: assuming the grand master role\r
+\r
+7. Synchronize local NIC PTP master clock to local NIC PTP slave clock. ::\r
+\r
+ ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8\r
+\r
+Example of output::\r
+\r
+ ./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8\r
+ phc2sys[3904600.332]: enp175s0f1 phc offset 2042 s0 freq -2445 delay 4525\r
+ phc2sys[3904600.458]: enp175s0f1 phc offset 2070 s2 freq -2223 delay 4506\r
+ phc2sys[3904600.584]: enp175s0f1 phc offset 2125 s2 freq -98 delay 4505\r
+ phc2sys[3904600.710]: enp175s0f1 phc offset 1847 s2 freq +262 delay 4518\r
+ phc2sys[3904600.836]: enp175s0f1 phc offset 1500 s2 freq +469 delay 4515\r
+ phc2sys[3904600.961]: enp175s0f1 phc offset 1146 s2 freq +565 delay 4547\r
+ phc2sys[3904601.086]: enp175s0f1 phc offset 877 s2 freq +640 delay 4542\r
+ phc2sys[3904601.212]: enp175s0f1 phc offset 517 s2 freq +543 delay 4517\r
+ phc2sys[3904601.337]: enp175s0f1 phc offset 189 s2 freq +370 delay 4510\r
+ phc2sys[3904601.462]: enp175s0f1 phc offset -125 s2 freq +113 delay 4554\r
+ phc2sys[3904601.587]: enp175s0f1 phc offset -412 s2 freq -212 delay 4513\r
+ phc2sys[3904601.712]: enp175s0f1 phc offset -693 s2 freq -617 delay 4519\r
+ phc2sys[3904601.837]: enp175s0f1 phc offset -878 s2 freq -1009 delay 4515\r
+ phc2sys[3904601.962]: enp175s0f1 phc offset -965 s2 freq -1360 delay 4518\r
+ phc2sys[3904602.088]: enp175s0f1 phc offset -1048 s2 freq -1732 delay 4510\r
+ phc2sys[3904602.213]: enp175s0f1 phc offset -1087 s2 freq -2086 delay 4531\r
+ phc2sys[3904602.338]: enp175s0f1 phc offset -1014 s2 freq -2339 delay 4528\r
+ phc2sys[3904602.463]: enp175s0f1 phc offset -1009 s2 freq -2638 delay 4531\r
+\r
+8. On O-DU Install PTP for Linux tools from source code the same way as\r
+on O-RU above but no need to apply the patch for msg.c\r
+\r
+9. Start slave port toward PTP master from O-RU using the same\r
+default_slave.cfg as on O-RU (see above) ::\r
+\r
+ ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 –m\r
+\r
+Example of output::\r
+\r
+ ./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 -m\r
+ ptp4l[809092.918]: selected /dev/ptp6 as PTP clock\r
+ ptp4l[809092.934]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[809092.934]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE\r
+ ptp4l[809092.949]: port 1: new foreign master 3cfdfe.fffe.bd005d-1\r
+ ptp4l[809096.949]: selected best master clock 3cfdfe.fffe.bd005d\r
+ ptp4l[809096.950]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE\r
+ ptp4l[809098.363]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED\r
+ ptp4l[809099.051]: rms 38643 max 77557 freq +719 +/- 1326 delay 1905 +/- 0\r
+ ptp4l[809100.051]: rms 1134 max 1935 freq -103 +/- 680 delay 1891 +/- 4\r
+ ptp4l[809101.051]: rms 453 max 855 freq +341 +/- 642 delay 1888 +/- 0\r
+ ptp4l[809102.052]: rms 491 max 772 freq +1120 +/- 752 delay 1702 +/- 0\r
+ ptp4l[809103.052]: rms 423 max 654 freq +1352 +/- 653 delay 1888 +/- 0\r
+ ptp4l[809104.052]: rms 412 max 579 freq +1001 +/- 672 delay 1702 +/- 0\r
+ ptp4l[809105.053]: rms 441 max 672 freq +807 +/- 709 delay 1826 +/- 88\r
+ ptp4l[809106.053]: rms 422 max 607 freq +1353 +/- 636 delay 1702 +/- 0\r
+ ptp4l[809107.054]: rms 401 max 466 freq +946 +/- 646 delay 1702 +/- 0\r
+ ptp4l[809108.055]: rms 401 max 502 freq +912 +/- 659\r
+\r
+10. Synchronize local clock on O-DU for sample application or l1\r
+Application. ::\r
+\r
+ ./phc2sys -s enp181s0f0 -w -m -R 8\r
+\r
+Example of output::\r
+\r
+ ./phc2sys -s enp181s0f0 -w -m -R 8\r
+ phc2sys[809127.123]: CLOCK_REALTIME phc offset 675 s0 freq -37379 delay 1646\r
+ phc2sys[809127.249]: CLOCK_REALTIME phc offset 696 s2 freq -37212 delay 1654\r
+ phc2sys[809127.374]: CLOCK_REALTIME phc offset 630 s2 freq -36582 delay 1648\r
+ phc2sys[809127.500]: CLOCK_REALTIME phc offset 461 s2 freq -36562 delay 1642\r
+ phc2sys[809127.625]: CLOCK_REALTIME phc offset 374 s2 freq -36510 delay 1643\r
+ phc2sys[809127.751]: CLOCK_REALTIME phc offset 122 s2 freq -36650 delay 1649\r
+ phc2sys[809127.876]: CLOCK_REALTIME phc offset 34 s2 freq -36702 delay 1650\r
+ phc2sys[809128.002]: CLOCK_REALTIME phc offset -112 s2 freq -36837 delay 1645\r
+ phc2sys[809128.127]: CLOCK_REALTIME phc offset -160 s2 freq -36919 delay 1643\r
+ phc2sys[809128.252]: CLOCK_REALTIME phc offset -270 s2 freq -37077 delay 1657\r
+ phc2sys[809128.378]: CLOCK_REALTIME phc offset -285 s2 freq -37173 delay 1644\r
+ phc2sys[809128.503]: CLOCK_REALTIME phc offset -349 s2 freq -37322 delay 1644\r
+ phc2sys[809128.629]: CLOCK_REALTIME phc offset -402 s2 freq -37480 delay 1641\r
+ phc2sys[809128.754]: CLOCK_REALTIME phc offset -377 s2 freq -37576 delay 1648\r
+ phc2sys[809128.879]: CLOCK_REALTIME phc offset -467 s2 freq -37779 delay 1650\r
+ phc2sys[809129.005]: CLOCK_REALTIME phc offset -408 s2 freq -37860 delay 1648\r
+ phc2sys[809129.130]: CLOCK_REALTIME phc offset -480 s2 freq -38054 delay 1655\r
+ phc2sys[809129.256]: CLOCK_REALTIME phc offset -350 s2 freq -38068 delay 1650\r
+\r
+Support in xRAN Library\r
+=======================\r
+\r
+The xRAN library provides an API to check whether PTP for Linux is\r
+running correctly. There is a function called xran_is_synchronized(). It\r
+checks if ptp4l and phc2sys are running in the system by making PMC tool\r
+requests for the current port state and comparing it with the expected\r
+value. This verification should be done before initialization.\r
+\r
+- “SLAVE” is the only expected value in this release; only a non-master scenario is supported currently.\r
+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-Sample Application
-==================
-
-.. contents::
- :depth: 3
- :local:
-
-Figure 25 illustrates a sample xRAN application.
-
-.. image:: images/Sample-Application.jpg
- :width: 600
- :alt: Figure 25. Sample Application
-
-Figure 25. Sample Application
-
-The sample application was created to execute test scenarios with
-features of the xRAN library and test external API as well as timing.
-The sample application is named sample-app, and depending on
-configuration file settings can act as O-DU or simplified simulation of
-O-RU. The first O-DU should be run on the machine that acts as O-DU and
-the second as O-RU. Both machines are connected via ETH. The sample
-application on both sides executes using a constant configuration |br|
-according to settings in corresponding config files
-(./app/usecase/mu0_10mhz/config_file_o_du.dat and |br|
-./app/usecase/mu0_10mhz/config_file_o_ru.dat) and uses binary files
-(ant.bin) with IQ samples as input. Multiple-use |br|
-cases for different
-numerologies and different BW are available as examples. Configuration
-files provide descriptions of each |br|
-parameter and in general, those are
-related to M-plane level settings as per the ORAN Fronthaul
-specification.
-
-From the start of the process, the application (O-DU) sends DL packets
-for the U-plane and C-plane and receives U-plane UL packets.
-Synchronization of O-DU and O-RU sides is achieved via IEEE 1588.
-
-U-plane packets for UL and DL direction are constructed the same way
-except for the direction field.
-
-The several default configurations used with the sample app for v20.02
-release are:
-
-1 Cell mmWave 100MHz TDD DDDS:
-
-
-- Numerology 3 (mmWave)
-
-- TTI period 125 µs
-
-- 100 Mhz Bandwidth: 792 subcarriers (all 66 RB utilized at all times)
-
-- 4x4 MIMO
-
-- No beamforming
-
-- 1 Component carrier
-
-- Jumbo Frame for Ethernet (up to 9728 bytes)
-
-- Front haul throughput ~11.5 Gbps.
-
-12 Cells Sub6 10MHz FDD:
-
-
-- Numerology 0 (Sub-6)
-
-- TTI period 1000 µs
-
-- 10Mhz Bandwidth: 624 subcarriers (all 52 RB utilized at all times)
-
-- 4x4 MIMO
-
-- No beamforming
-
-- 12 Component carrier
-
-- Jumbo Frame for Ethernet (up to 9728 bytes)
-
-- Front haul throughput ~13.7Gbps.
-
-1 Cell Sub6 100MHz TDD:
-
-
-- Numerology 1 (Sub-6)
-
-- TTI period 500us
-
-- 100Mhz Bandwidth: 3276 subcarriers (all 273RB utilized at all times)
-
-- 4x4 MIMO
-
-- No beamforming
-
-- 1 Component carrier
-
-- Jumbo Frame for Ethernet (up to 9728 bytes)
-
-- Front haul throughput ~11.7 Gbps.
-
-.. _cell-sub6-100mhz-tdd-1:
-
-1 Cell Sub6 100MHz TDD:
-
-
-- Numerology 1 (Sub-6)
-
-- TTI period 500 µs
-
-- 100 Mhz Bandwidth: 3276 subcarriers (all 273RB utilized at all
- times). 8 UEs per TTI per layer
-
-- 8DL /4UL MIMO Layers
-
-- Digital beamforming with 32T32R
-
-- 1 Component carrier
-
-- Jumbo Frame for Ethernet (up to 9728 bytes)
-
-- Front haul throughput ~23.5 Gbps.
-
-Other configurations can be constructed by modifying config files
-(please see app/usecase/)
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+Sample Application\r
+==================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+Figure 26 illustrates a sample xRAN application.\r
+\r
+.. image:: images/Sample-Application.jpg\r
+ :width: 600\r
+ :alt: Figure 26. Sample Application\r
+\r
+Figure 26. Sample Application\r
+\r
+The sample application was created to execute test scenarios with\r
+features of the xRAN library and test external API as well as timing.\r
+The sample application is named sample-app, and depending on\r
+configuration file settings can act as O-DU or simplified simulation of\r
+O-RU. The first O-DU should be run on the machine that acts as O-DU and\r
+the second as O-RU. Both machines are connected via ETH. The sample\r
+application on both sides executes using a constant configuration\r
+according to settings in corresponding config files\r
+(./app/usecase/mu0_10mhz/config_file_o_du.dat and\r
+./app/usecase/mu0_10mhz/config_file_o_ru.dat) and uses binary files\r
+(ant.bin) with IQ samples as input. Multiple-use cases for different\r
+numerologies and different BW are available as examples. Configuration\r
+files provide descriptions of each parameter, and in general, those are\r
+related to M-plane level settings as per the O-RAN Fronthaul\r
+specification, refer to *Table 2*.\r
+\r
+From the start of the process, the application (O-DU) sends DL packets\r
+for the U-plane and C-plane and receives U-plane UL packets.\r
+Synchronization of O-DU and O-RU sides is achieved via IEEE 1588.\r
+\r
+U-plane packets for UL and DL direction are constructed the same way\r
+except for the direction field.\r
+\r
+Examples of default configurations used with the sample application for\r
+v20.04 release provided below:\r
+\r
+1 Cell mmWave 100MHz TDD DDDS:\r
+------------------------------\r
+\r
+- Numerology 3 (mmWave)\r
+\r
+- TTI period 125 µs\r
+\r
+- 100 MHz Bandwidth: 792 subcarriers (all 66 RB utilized at all times)\r
+\r
+- 4x4 MIMO\r
+\r
+- No beamforming\r
+\r
+- 1 Component carrier\r
+\r
+- Jumbo Frame for Ethernet (up to 9728 bytes)\r
+\r
+- Front haul throughput ~11.5 Gbps.\r
+\r
+12 Cells Sub6 10MHz FDD:\r
+------------------------\r
+\r
+- Numerology 0 (Sub-6)\r
+\r
+- TTI period 1000 µs\r
+\r
+- 10 MHz Bandwidth: 624 subcarriers (all 52 RB utilized at all times)\r
+\r
+- 4x4 MIMO\r
+\r
+- No beamforming\r
+\r
+- 12 Component carrier\r
+\r
+- Jumbo Frame for Ethernet (up to 9728 bytes)\r
+\r
+- Front haul throughput ~13.7Gbps.\r
+\r
+1 Cell Sub6 100 MHz TDD\r
+-----------------------\r
+\r
+- Numerology 1 (Sub-6)\r
+\r
+- TTI period 500 µs\r
+\r
+- 100 MHz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times)\r
+\r
+- 4x4 MIMO\r
+\r
+- No beamforming\r
+\r
+- 1 Component carrier\r
+\r
+- Jumbo Frame for Ethernet (up to 9728 bytes)\r
+\r
+- Front haul throughput ~11.7 Gbps.\r
+\r
+1 Cell Sub6 100 MHz TDD (Category B):\r
+-------------------------------------\r
+\r
+- Numerology 1 (Sub-6)\r
+\r
+- TTI period 500 µs\r
+\r
+- 100 MHz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times). 8 UEs per TTI per layer\r
+\r
+- 8DL /4UL MIMO Layers\r
+\r
+- Digital beamforming with 32T32R\r
+\r
+- 1 Component carrier\r
+\r
+- Jumbo Frame for Ethernet (up to 9728 bytes)\r
+\r
+- Front haul throughput ~23.5 Gbps.\r
+\r
+3 Cell Sub6 100MHz TDD Massive MIMO (Category B):\r
+-------------------------------------------------\r
+\r
+- Numerology 1 (Sub-6)\r
+\r
+- TTI period 500 µs\r
+\r
+- 100 Mhz Bandwidth: 3276 subcarriers (all 273 RB utilized at all times). 8 UEs per TTI per layer\r
+\r
+- 16DL /8UL MIMO Layers\r
+\r
+- Digital beamforming with 64T64R\r
+\r
+- 1 Component carrier for each Cell\r
+\r
+- Jumbo Frame for Ethernet (up to 9728 bytes)\r
+\r
+- Front haul throughput ~44 Gbps.\r
+\r
+Other configurations can be constructed by modifying the config files\r
+(see app/usecase/)\r
+\r
+One_way Delay Measurements:\r
+---------------------------\r
+\r
+There are 4 usecases defined that are based on cat a, numerology 0 and\r
+20 MHz Bw:\r
+\r
+Common to all cases the following parameters are needed in the\r
+usecase_xu.cfg files where x=r for ORU and x=d for ODU.\r
+\r
+oXuOwdmNumSamps=8 # Run 8 samples per port\r
+\r
+oXuOwdmFltrType=0 # Simple average\r
+\r
+oXuOwdmRespTimeOut=10000000 # 10 ms expressed in ns (Currently not\r
+enforced)\r
+\r
+oXuOwdmMeasState=0 # Measurement state is INIT\r
+\r
+oXuOwdmMeasId=0 # Measurement Id seed\r
+\r
+oXuOwdmEnabled=1 # Measurements are enabled\r
+\r
+oXuOwdmPlLength= n # with 40 <= n <= 1400 bytes\r
+\r
+For the ORU\r
+\r
+oXuOwdmInitEn=0 #O-RU is always the recipient\r
+\r
+For the ODU\r
+\r
+oXuOwdmInitEn=1 #O-DU is always initiator\r
+\r
+20 Corresponds to the Request/Response usecase with Payload Size 40\r
+bytes\r
+\r
+oXuOwdmMeasMeth=0 # Measurement Method REQUEST\r
+\r
+21 Corresponds to the Remote Request usecase with Payload Size 512 bytes\r
+\r
+oXuOwdmMeasMeth=1 # Measurement Method REM_REQ\r
+\r
+22 Corresponds to the Request with Follow Up usecase with Payload Size\r
+1024 bytes\r
+\r
+oXuOwdmMeasMeth=2 # Measurement Method REQUESTwFUP\r
+\r
+23 Corresponds to the Remote Request with Follow Up usecase with default\r
+Payload Size\r
+\r
+oXuOwdmMeasMeth=3 # Measurement Method REM_REQ_WFUP\r
+\r
+-\r
+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-Setup Configuration
-===================
-
-A.1 Setup Configuration
------------------------
-The configuration shown in Figure 26 shows how to set up a test
-environment to execute xRAN scenarios where O-DU and 0-RU are simulated
-using the sample application. This setup allows development and
-prototyping as well as testing of xRAN specific functionality. The O-DU
-side can be instantiated with a full 5G NR L1 reference as well. The
-configuration differences of the 5G NR l1app configuration are provided
-below. Steps for running the sample application on the O-DU side and
-0-RU side are the same, except configuration file options may be
-different.
-
-.. image:: images/Setup-for-xRAN-Testing.jpg
- :width: 400
- :alt: Figure 26. Setup for xRAN Testing
-
-Figure 26. Setup for xRAN Testing
-
-.. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg
- :width: 400
- :alt: Figure 27. Setup for xRAN Testing with PHY and Configuration C3
-
-Figure 27. Setup for xRAN Testing with PHY and Configuration C3
-
-A.2 Prerequisites
------------------
-Each server in Figure 26 requires the following:
-
-- Wolfpass server according to recommended BOM for FlexRAN such as
- Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20
- cores (two sockets)
-
-- BIOS settings:
-
-- Intel(R) Virtualization Technology Enabled
-
-- Intel(R) VT for Directed I/O - Enabled
-
-- ACS Control - Enabled
-
-- Coherency Support - Disabled
-
-- Front Haul networking cards:
-
-- Intel® Ethernet Converged Network Adapter XL710-QDA2
-
-- Intel® Ethernet Converged Network Adapter XXV710-DA2
-
-- Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000
-
-**The Front Haul NIC requires support for PTP HW timestamping.**
-
-The recommended configuration for NICs is::
-
-
- ethtool -i enp33s0f0
- driver: i40e
- version: 2.10.19.82
- firmware-version: 7.20 0x80007949 1.2585.0
- expansion-rom-version:
- bus-info: 0000:21:00.0
- supports-statistics: yes
- supports-test: yes
- supports-eeprom-access: yes
- supports-register-dump: yes
- supports-priv-flags: yes
- ethtool -T enp33s0f0
- Time stamping parameters for enp33s0f0:
- Capabilities:
- hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
- software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
- hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
- software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
- software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
- hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
- PTP Hardware Clock: 4
- Hardware Transmit Timestamp Modes:
- off (HWTSTAMP_TX_OFF)
- on (HWTSTAMP_TX_ON)
- Hardware Receive Filter Modes:
- none (HWTSTAMP_FILTER_NONE)
- ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
- ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
- ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
- ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
- ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
- ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
- ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
- ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
- ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
- ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
- ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
-
-
-A PTP Main Reference Clock is required to be available in the network to provide
-synchronization of both O-DU and RU to GPS time.
-
-1.Installing Intel® C++ Compiler v19.0.3 is preferred. or you could get
-Intel® C++ Compiler through below link with community license,
-however the version you could get is always latest version, the
-verification for that version might not be performed yet, please
-feedback through O-DU Low project WIKI page if you meet an issue. |br|
-`https://software.intel.com/en-us/system-studio/choose-download <https://software.intel.com/en-us/system-studio/choose-download%20>`__
-
-2.Download DPDK 19.11.
-
-3.Change DPDK files according to below diff information which relevant to O-RAN FH::
-
- diff --git a/drivers/net/i40e/i40e_ethdev.c
- b/drivers/net/i40e/i40e_ethdev.c
-
- index 85a6a86..236fbe0 100644
-
- --- a/drivers/net/i40e/i40e_ethdev.c
-
- +++ b/drivers/net/i40e/i40e_ethdev.c
-
- @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct
- i40e_hw \*hw)
-
- /\* Map queues with MSIX interrupt \*/
-
- main_vsi->nb_used_qps = dev->data->nb_rx_queues -
-
- pf->nb_cfg_vmdq_vsi \* RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
-
- - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
-
- + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);
-
- i40e_vsi_enable_queues_intr(main_vsi);
-
- /\* Map VMDQ VSI queues with MSIX interrupt \*/
-
- @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct
- i40e_hw \*hw)
-
- i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
-
- }
-
- + i40e_aq_debug_write_global_register(hw,
-
- + 0x0012A504,
-
- + 0, NULL);
-
- +
-
- /\* enable FDIR MSIX interrupt \*/
-
- if (pf->fdir.fdir_vsi) {
-
- i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
-
- diff --git a/drivers/net/i40e/i40e_ethdev_vf.c
- b/drivers/net/i40e/i40e_ethdev_vf.c
-
- index 001c301..6f9ffdb 100644
-
- --- a/drivers/net/i40e/i40e_ethdev_vf.c
-
- +++ b/drivers/net/i40e/i40e_ethdev_vf.c
-
- @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {
-
- map_info = (struct virtchnl_irq_map_info \*)cmd_buffer;
-
- map_info->num_vectors = 1;
-
- - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
-
- + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;
-
- map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
-
- /\* Alway use default dynamic MSIX interrupt \*/
-
- map_info->vecmap[0].vector_id = vector_id;
-
- diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c
- b/drivers/net/ixgbe/ixgbe_ethdev.c
-
- index 26b1927..018eb8f 100644
-
- --- a/drivers/net/ixgbe/ixgbe_ethdev.c
-
- +++ b/drivers/net/ixgbe/ixgbe_ethdev.c
-
- @@ -3705,7 +3705,7 @@ static int
- ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev \*dev,
-
- \* except for 82598EB, which remains constant.
-
- \*/
-
- if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
-
- - hw->mac.type != ixgbe_mac_82598EB)
-
- + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type !=
- ixgbe_mac_82599EB)
-
- dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
-
- }
-
- dev_info->min_rx_bufsize = 1024; /\* cf BSIZEPACKET in SRRCTL register
- \*/
-
- diff --git a/lib/librte_eal/common/include/rte_dev.h
- b/lib/librte_eal/common/include/rte_dev.h
-
- old mode 100644
-
- new mode 100755
-
-5.Build and install DPDK::
-
- [root@xran dpdk]# ./usertools/dpdk-setup.sh
-
- select [39] x86_64-native-linuxapp-icc
-
- select [46] Insert VFIO module
-
- exit [62] Exit Script
-
-6.Make below file changes in dpdk that assure i40e to get best
-latency of packet processing::
-
- --- i40e.h 2018-11-30 11:27:00.000000000 +0000
-
- +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000
-
- @@ -451,7 +451,7 @@
-
- #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \\
-
- (I40E_QINT_RQCTL_CAUSE_ENA_MASK \| \\
-
- - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) \| \\
-
- + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) \| \\
-
- ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) \| \\
-
- ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) \| \\
-
- (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
-
- --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000
-
- +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000
-
- @@ -15296,6 +15296,9 @@
-
- pf->hw_features \|= I40E_HW_HAVE_CRT_RETIMER;
-
- /\* print a string summarizing features \*/
-
- i40e_print_features(pf);
-
- +
-
- + /\* write to this register to clear rx descriptor \*/
-
- + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);
-
- return 0;
-
-A.3 Configuration of System
----------------------------
-1.Boot Linux with the following arguments::
-
- cat /proc/cmdline
-
- BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
- crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
- usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
- intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
- hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
- isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
- nohz_full=1-19,21-39
-
-2.Download from Intel Website and install updated version of i40e
-driver if needed. The current recommended version of i40e is 2.10.19.82.
-However, any latest version of i40e after x2.9.21 expected to be functional for ORAN FH.
-
-3.Identify PCIe Bus address of the Front Haul NIC::
-
- lspci |grep Eth
- 19:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
- 19:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
- 1d:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
- 1d:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
- 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
- 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
- 67:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722 for 10GBASE-T (rev 09)
-
-
-4.Identify the Ethernet device name::
-
- ethtool -i enp33s0f0
- driver: i40e
- version: 2.10.19.82
- firmware-version: 7.20 0x80007949 1.2585.0
- expansion-rom-version:
- bus-info: 0000:21:00.0
- supports-statistics: yes
- supports-test: yes
- supports-eeprom-access: yes
- supports-register-dump: yes
- supports-priv-flags: yes
- Enable
-
-
-5.Enable two virtual functions (VF) on the device::
-
- echo 2 > /sys/class/net/enp33s0f0/device/sriov_numvfs
-
-More information about VFs supported by Intel NICs can be found at
-https://doc.dpdk.org/guides/nics/intel_vf.html.
-
-The resulting configuration can look like the listing below, where two
-new VFs were added::
-
- lspci|grep Eth
-
- 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
- 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
- 21:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
- 21:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
-
-
-6.Configure MAC address and VLAN settings for VFs for XRAN, based on
-requirements for xRAN scenario and assignment of VLAN ID using IP
-tool perform configuration of VF.
-
- Example where O-DU and O-RU simulation run on the same sytem::
-
- #!/bin/bash
-
- echo 2 > /sys/bus/pci/devices/0000\:21\:00.0/sriov_numvfs
- ip link set enp33s0f0 vf 1 mac 00:11:22:33:44:66 vlan 1
- ip link set enp33s0f0 vf 0 mac 00:11:22:33:44:66 vlan 2
- echo 2 > /sys/bus/pci/devices/0000\:21\:00.1/sriov_numvfs
- ip link set enp33s0f1 vf 1 mac 00:11:22:33:44:55 vlan 1
- ip link set enp33s0f1 vf 0 mac 00:11:22:33:44:55 vlan 2
-
- where output is next::
-
- [root@xran app]# ip link show
-
- 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
-
- link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
-
- 2: enp25s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 64:4c:36:10:1f:30 brd ff:ff:ff:ff:ff:ff
-
- 3: enp25s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 64:4c:36:10:1f:31 brd ff:ff:ff:ff:ff:ff
-
- 4: enp29s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 64:4c:36:10:1f:34 brd ff:ff:ff:ff:ff:ff
-
- 5: enp29s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 64:4c:36:10:1f:35 brd ff:ff:ff:ff:ff:ff
-
- 6: enp33s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
-
- vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto, trust off
-
- vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto, trust off
-
- 7: enp33s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
-
- vf 0 MAC 00:11:22:33:44:55, vlan 2, spoof checking on, link-state auto, trust off
-
- vf 1 MAC 00:11:22:33:44:55, vlan 1, spoof checking on, link-state auto, trust off
-
- 8: eno1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether a4:bf:01:3e:1f:be brd ff:ff:ff:ff:ff:ff
-
- 9: eno2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
-
- link/ether a4:bf:01:3e:1f:bf brd ff:ff:ff:ff:ff:ff
-
- 10: npacf0g0l0: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
-
- link/generic
-
- 11: npacf0g0l1: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
-
- link/generic
-
- 12: npacf0g0l2: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
-
- link/generic
-
- 13: npacf0g0l3: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
-
- link/generic
-
-After this step FH NIC is configured.
-
-O-DU
-
-VF for C-plane is VF1 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is 21d8:02.1
-
-VF for U-plane is VF0 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is 21d8:02.0
-
-O-RU
-
-VF for C-plane is VF1 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 1. PCIe Bus address is VF1 is 21:0a.1
-
-VF for U-plane is VF0 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 2. PCIe Bus address is VF1 is 21:0a.0
-
-
-A.4 Install and Configure Sample Application
---------------------------------------------
-To install and configure the sample application:
-
-1. Set up the environment:
-
- export GTEST_ROOT=`pwd`/gtest-1.7.0
-
- export RTE_SDK=`pwd`/dpdk-19.11
-
- export RTE_TARGET=x86_64-native-linuxapp-icc
-
- export MLOG_DIR=`pwd`/flexran_l1_sw/libs/mlog
-
- export XRAN_DIR=`pwd`/flexran_xran
-
-2. Compile xRAN library and test the application:
-
- [turner@xran home]$ cd $XRAN_DIR
-
- [turner@xran xran]$ ./build.sh
-
-3. Configure the sample app.
-
-IQ samples can be generated using Octave\* and script
-libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64
-compatible with get_test.m)
-
-Other IQ sample test vectors can be used as well. The format of IQ
-samples is binary int16_t I and Q for N slots of the OTA RF signal. For
-example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =
-3548160 bytes per antenna. Refer to comments in gen_test.m to correctly
-specify the configuration for IQ test vector generation.
-
-Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable
-configuration for your scenario.
-
-Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
-used for U-plane and C-plane correspondingly::
-
- ./build/sample-app -c ./usecase/mu0_10mhz/config_file_o_du.dat -p 2 0000:21d8:02.0 0000:21d8:02.1
-
-4. Run application using run_o_du.sh (run_o_ru.sh).
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+.. |br| raw:: html\r
+\r
+ <br />\r
+\r
+Setup Configuration\r
+===================\r
+\r
+A.1 Setup Configuration\r
+-----------------------\r
+The configuration shown in Figure 26 shows how to set up a test\r
+environment to execute xRAN scenarios where O-DU and 0-RU are simulated\r
+using the sample application. This setup allows development and\r
+prototyping as well as testing of xRAN specific functionality. The O-DU\r
+side can be instantiated with a full 5G NR L1 reference as well. The\r
+configuration differences of the 5G NR l1app configuration are provided\r
+below. Steps for running the sample application on the O-DU side and\r
+0-RU side are the same, except configuration file options may be\r
+different.\r
+\r
+.. image:: images/Setup-for-xRAN-Testing.jpg\r
+ :width: 400\r
+ :alt: Figure 26. Setup for xRAN Testing\r
+\r
+Figure 26. Setup for xRAN Testing\r
+\r
+.. image:: images/Setup-for-xRAN-Testing-with-PHY-and-Configuration-C3.jpg\r
+ :width: 400\r
+ :alt: Figure 27. Setup for xRAN Testing with PHY and Configuration C3\r
+\r
+Figure 27. Setup for xRAN Testing with PHY and Configuration C3\r
+\r
+A.2 Prerequisites\r
+-----------------\r
+Each server in Figure 26 requires the following:\r
+\r
+- Wolfpass server according to recommended BOM for FlexRAN such as\r
+ Intel® Xeon® Skylake Gold 6148 FC-LGA3647 2.4 GHz 27.5 MB 150W 20\r
+ cores (two sockets)\r
+\r
+- BIOS settings:\r
+\r
+ - Intel® Virtualization Technology Enabled\r
+\r
+ - Intel® VT for Directed I/O - Enabled\r
+\r
+ - ACS Control - Enabled\r
+\r
+ - Coherency Support - Disabled\r
+\r
+- Front Haul networking cards:\r
+\r
+ - Intel® Ethernet Converged Network Adapter XL710-QDA2\r
+\r
+ - Intel® Ethernet Converged Network Adapter XXV710-DA2\r
+\r
+ - Intel® Ethernet Converged Network Adapter E810-CQDA2\r
+\r
+ - Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000\r
+\r
+- Back (Mid) Haul networking card can be either:\r
+\r
+ - Intel® Ethernet Connection X722 for 10GBASE-T\r
+\r
+ - Intel® 82599ES 10-Gigabit SFI/SFP+ Network Connection\r
+\r
+ - Other networking cards capable of HW timestamping for PTP synchronization.\r
+\r
+ - Both Back (mid) Haul and Front Haul NIC require support for PTP HW timestamping.\r
+\r
+The recommended configuration for NICs is::\r
+\r
+ ethtool -i enp33s0f0\r
+ driver: i40e\r
+ version: 2.14.13\r
+ firmware-version: 8.20 0x80009bd4 1.2879.0\r
+ expansion-rom-version:\r
+ bus-info: 0000:21:00.0\r
+ supports-statistics: yes\r
+ supports-test: yes\r
+ supports-eeprom-access: yes\r
+ supports-register-dump: yes\r
+ supports-priv-flags: yes\r
+ ethtool -T enp33s0f0\r
+ Time stamping parameters for enp33s0f0:\r
+ Capabilities:\r
+ hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)\r
+ software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)\r
+ hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)\r
+ software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)\r
+ software-system-clock (SOF_TIMESTAMPING_SOFTWARE)\r
+ hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)\r
+ PTP Hardware Clock: 4\r
+ Hardware Transmit Timestamp Modes:\r
+ off (HWTSTAMP_TX_OFF)\r
+ on (HWTSTAMP_TX_ON)\r
+ Hardware Receive Filter Modes:\r
+ none (HWTSTAMP_FILTER_NONE)\r
+ ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)\r
+ ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)\r
+ ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)\r
+ ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)\r
+ ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)\r
+ ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)\r
+ ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)\r
+ ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)\r
+ ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)\r
+ ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)\r
+ ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)\r
+\r
+The recommended configuration for Columbiaville NICs (base on Intel®\r
+Ethernet 800 Series (Columbiaville) CVL 2.3 release is::\r
+\r
+ ethtool -i enp81s0f0\r
+ driver: ice\r
+ version: 1.3.2\r
+ firmware-version: 2.3 0x80005D18\r
+ expansion-rom-version:\r
+ bus-info: 0000:51:00.0\r
+ supports-statistics: yes\r
+ supports-test: yes\r
+ supports-eeprom-access: yes\r
+ supports-register-dump: yes\r
+ supports-priv-flags: yes\r
+ ethtool -T enp81s0f0\r
+ Time stamping parameters for enp81s0f0:\r
+ Capabilities:\r
+ hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)\r
+ software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)\r
+ hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)\r
+ software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)\r
+ software-system-clock (SOF_TIMESTAMPING_SOFTWARE)\r
+ hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)\r
+ PTP Hardware Clock: 1\r
+ Hardware Transmit Timestamp Modes:\r
+ off (HWTSTAMP_TX_OFF)\r
+ on (HWTSTAMP_TX_ON)\r
+ Hardware Receive Filter Modes:\r
+ none (HWTSTAMP_FILTER_NONE)\r
+ all (HWTSTAMP_FILTER_ALL)\r
+\r
+ Recommended version of\r
+ iavf driver 4.0.2\r
+ ICE COMMS Package version 1.3.24.0\r
+\r
+*Note*. If your firmware version does not match with the ones in the output\r
+images, you can download the correct version from the Intel Download\r
+Center. It is Intel's repository for the latest software and drivers\r
+for Intel products. The NVM Update Packages for Windows*, Linux*,\r
+ESX*, FreeBSD*, and EFI/EFI2 are located at:\r
+\r
+..\r
+\r
+https://downloadcenter.intel.com/download/24769 (700 series)\r
+\r
+https://downloadcenter.intel.com/download/29736 (E810 series)\r
+\r
+PTP Grand Master is required to be available in the network to provide\r
+synchronization of both O-DU and RU to GPS time.\r
+\r
+The software package includes Linux\* CentOS\* operating system and RT\r
+patch according to FlexRAN Reference Solution Cloud-Native Setup\r
+document (refer to Table 2). Only real-time HOST is required.\r
+\r
+1. Install Intel® C++ Compiler v19.0.3\r
+\r
+2. Download DPDK v20.11\r
+\r
+3. Patch DPDK with FlexRAN BBDev patch as per given release.\r
+\r
+4. Double check that FlexRAN DPDK patch includes changes below relevant\r
+to O-RAN Front haul::\r
+\r
+ For Fortville: \r
+ diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\r
+ index 85a6a86..236fbe0 100644\r
+ --- a/drivers/net/i40e/i40e_ethdev.c\r
+ +++ b/drivers/net/i40e/i40e_ethdev.c\r
+ @@ -2207,7 +2207,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\r
+ /* Map queues with MSIX interrupt */\r
+ main_vsi->nb_used_qps = dev->data->nb_rx_queues -\r
+ pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;\r
+ - i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);\r
+ + i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_NONE);\r
+ i40e_vsi_enable_queues_intr(main_vsi);\r
+ \r
+ /* Map VMDQ VSI queues with MSIX interrupt */\r
+ @@ -2218,6 +2218,10 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)\r
+ i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);\r
+ }\r
+ + i40e_aq_debug_write_global_register(hw,\r
+ + 0x0012A504,\r
+ + 0, NULL);\r
+ +\r
+ /* enable FDIR MSIX interrupt */\r
+ if (pf->fdir.fdir_vsi) {\r
+ i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,\r
+ diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c\r
+ index 001c301..6f9ffdb 100644\r
+ --- a/drivers/net/i40e/i40e_ethdev_vf.c\r
+ +++ b/drivers/net/i40e/i40e_ethdev_vf.c\r
+ @@ -640,7 +640,7 @@ struct rte_i40evf_xstats_name_off {\r
+ \r
+ map_info = (struct virtchnl_irq_map_info *)cmd_buffer;\r
+ map_info->num_vectors = 1;\r
+ - map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;\r
+ + map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_NONE;\r
+ map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;\r
+ /* Alway use default dynamic MSIX interrupt */\r
+ map_info->vecmap[0].vector_id = vector_id;\r
+ diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\r
+ index 26b1927..018eb8f 100644\r
+ --- a/drivers/net/ixgbe/ixgbe_ethdev.c\r
+ +++ b/drivers/net/ixgbe/ixgbe_ethdev.c\r
+ @@ -3705,7 +3705,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,\r
+ * except for 82598EB, which remains constant.\r
+ */\r
+ if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&\r
+ - hw->mac.type != ixgbe_mac_82598EB)\r
+ + hw->mac.type != ixgbe_mac_82598EB && hw->mac.type != ixgbe_mac_82599EB)\r
+ dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;\r
+ }\r
+ dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */\r
+ diff --git a/lib/librte_eal/common/include/rte_dev.h b/lib/librte_eal/common/include/rte_dev.h\r
+ old mode 100644\r
+ new mode 100755\r
+\r
+ for Columbiaville\r
+ diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\r
+ index de189daba..d9aff341c 100644\r
+ --- a/drivers/net/ice/ice_ethdev.c\r
+ +++ b/drivers/net/ice/ice_ethdev.c\r
+ @@ -2604,8 +2604,13 @@ __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,\r
+\r
+ PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",\r
+ base_queue + i, msix_vect);\r
+ - /* set ITR0 value */\r
+ - ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);\r
+ + /* set ITR0 value\r
+ + * Empirical configuration for optimal real time latency\r
+ + * reduced interrupt throttling to 2 ms\r
+ + * Columbiaville pre-PRQ : local patch subject to change\r
+ + */\r
+ + ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x1);\r
+ + ICE_WRITE_REG(hw, QRX_ITR(base_queue + i), QRX_ITR_NO_EXPR_M);\r
+ ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);\r
+ ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);\r
+ }\r
+\r
+5.Build and install DPDK::\r
+\r
+ See https://doc.dpdk.org/guides/prog_guide/build-sdk-meson.html\r
+\r
+6.Make below file changes in dpdk that assure i40e to get best\r
+latency of packet processing::\r
+\r
+ --- i40e.h 2018-11-30 11:27:00.000000000 +0000\r
+ +++ i40e_patched.h 2019-03-06 15:49:06.877522427 +0000\r
+ @@ -451,7 +451,7 @@\r
+ \r
+ #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \\r
+ (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \\r
+ - (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \\r
+ + (I40E_ITR_NONE << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \\r
+ ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \\r
+ ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \\r
+ (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))\r
+\r
+ --- i40e_main.c 2018-11-30 11:27:00.000000000 +0000\r
+ +++ i40e_main_patched.c 2019-03-06 15:46:13.521518062 +0000\r
+ @@ -15296,6 +15296,9 @@\r
+ pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;\r
+ /* print a string summarizing features */\r
+ i40e_print_features(pf);\r
+ + \r
+ + /* write to this register to clear rx descriptor */\r
+ + i40e_aq_debug_write_register(hw, 0x0012A504, 0, NULL);\r
+ \r
+ return 0;\r
+\r
+A.3 Configuration of System\r
+---------------------------\r
+1.Boot Linux with the following arguments::\r
+\r
+ cat /proc/cmdline\r
+ BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro\r
+ crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt\r
+ usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0\r
+ intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll\r
+ hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G\r
+ isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20\r
+ nohz_full=1-19,21-39\r
+\r
+2. Boot Linux with the following arguments for Icelake CPU::\r
+\r
+ cat /proc/cmdline\r
+ BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64\r
+ root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root\r
+ rd.lvm.lv=centos/swap rhgb quiet intel_iommu=off usbcore.autosuspend=-1\r
+ selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0\r
+ intel_pstate=disable cgroup_disable=memory mce=off hugepagesz=1G\r
+ hugepages=40 hugepagesz=2M hugepages=0 default_hugepagesz=1G\r
+ isolcpus=1-23,25-47 rcu_nocbs=1-23,25-47 kthread_cpus=0 irqaffinity=0\r
+ nohz_full=1-23,25-47\r
+\r
+3. Download from Intel Website and install updated version of i40e\r
+driver if needed. The current recommended version of i40e is 2.14.13.\r
+However, any latest version of i40e after 2.9.21 expected to be\r
+functional for O-RAN FH.\r
+\r
+4. For Columbiaville download Intel® Ethernet 800 Series (Columbiaville)\r
+CVL2.3 B0/C0 Sampling Sample Validation Kit (SVK) from Intel Customer\r
+Content Library. The current recommended version of ICE driver is\r
+1.3.2 with ICE COMMS Package version 1.3.24.0. IAVF recommended\r
+version 4.0.2\r
+\r
+5. Identify PCIe Bus address of the Front Haul NIC (Fortville)::\r
+\r
+ lspci|grep Eth\r
+ 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+\r
+6. Identify PCIe Bus address of the Front Haul NIC (Columbiaville)::\r
+\r
+ lspci \|grep Eth\r
+ 18:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 18:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 18:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 18:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 51:00.0 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 51:00.1 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 51:00.2 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+ 51:00.3 Ethernet controller: Intel Corporation Device 1593 (rev 02)\r
+\r
+7. Identify the Ethernet device name::\r
+\r
+ ethtool -i enp33s0f0\r
+ driver: i40e\r
+ version: 2.14.13\r
+ firmware-version: 8.20 0x80009bd4 1.2879.0 \r
+ expansion-rom-version:\r
+ bus-info: 0000:21:00.0\r
+ supports-statistics: yes\r
+ supports-test: yes\r
+ supports-eeprom-access: yes\r
+ supports-register-dump: yes\r
+ supports-priv-flags: yesEnable \r
+\r
+or ::\r
+\r
+ ethtool -i enp81s0f0\r
+ driver: ice\r
+ version: 1.3.2\r
+ firmware-version: 2.3 0x80005D18\r
+ expansion-rom-version:\r
+ bus-info: 0000:51:00.0\r
+ supports-statistics: yes\r
+ supports-test: yes\r
+ supports-eeprom-access: yes\r
+ supports-register-dump: yes\r
+ supports-priv-flags: yes \r
+\r
+8. Enable 3 virtual functions (VFs) on the each of two ports of each\r
+NIC::\r
+\r
+ #!/bin/bash\r
+\r
+ echo 0 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs\r
+ echo 0 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs\r
+\r
+ echo 0 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs\r
+ echo 0 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs\r
+\r
+ modprobe -r iavf\r
+ modprobe iavf\r
+\r
+ echo 3 > /sys/bus/pci/devices/0000\:88\:00.0/sriov_numvfs\r
+ echo 3 > /sys/bus/pci/devices/0000\:88\:00.1/sriov_numvfs\r
+\r
+ echo 3 > /sys/bus/pci/devices/0000\:86\:00.0/sriov_numvfs\r
+ echo 3 > /sys/bus/pci/devices/0000\:86\:00.1/sriov_numvfs\r
+\r
+ a=8\r
+\r
+ if [ -z "$1" ]\r
+ then\r
+ b=0\r
+ elif [ $1 -lt $a ]\r
+ then\r
+ b=$1\r
+ else\r
+ echo " Usage $0 qos with 0<= qos <= 7 with 0 as a default if no qos is provided"\r
+ exit 1\r
+ fi\r
+\r
+ #O-DU\r
+ ip link set enp136s0f0 vf 0 mac 00:11:22:33:00:00 vlan 1 qos $b\r
+ ip link set enp136s0f1 vf 0 mac 00:11:22:33:00:10 vlan 1 qos $b\r
+\r
+ ip link set enp136s0f0 vf 1 mac 00:11:22:33:01:00 vlan 2 qos $b\r
+ ip link set enp136s0f1 vf 1 mac 00:11:22:33:01:10 vlan 2 qos $b\r
+\r
+ ip link set enp136s0f0 vf 2 mac 00:11:22:33:02:00 vlan 3 qos $b\r
+ ip link set enp136s0f1 vf 2 mac 00:11:22:33:02:10 vlan 3 qos $b\r
+\r
+ #O-RU\r
+ ip link set enp134s0f0 vf 0 mac 00:11:22:33:00:01 vlan 1 qos $b\r
+ ip link set enp134s0f1 vf 0 mac 00:11:22:33:00:11 vlan 1 qos $b\r
+\r
+ ip link set enp134s0f0 vf 1 mac 00:11:22:33:01:01 vlan 2 qos $b\r
+ ip link set enp134s0f1 vf 1 mac 00:11:22:33:01:11 vlan 2 qos $b\r
+\r
+ ip link set enp134s0f0 vf 2 mac 00:11:22:33:02:01 vlan 3 qos $b\r
+ ip link set enp134s0f1 vf 2 mac 00:11:22:33:02:11 vlan 3 qos $b\r
+\r
+where output is next::\r
+\r
+ ip link show\r
+ ...\r
+ 9: enp134s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r
+ link/ether 3c:fd:fe:b9:f9:60 brd ff:ff:ff:ff:ff:ff\r
+ vf 0 MAC 00:11:22:33:00:01, vlan 1, spoof checking on, link-state auto, trust off\r
+ vf 1 MAC 00:11:22:33:01:01, vlan 2, spoof checking on, link-state auto, trust off\r
+ vf 2 MAC 00:11:22:33:02:01, vlan 3, spoof checking on, link-state auto, trust off\r
+ 11: enp134s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r
+ link/ether 3c:fd:fe:b9:f9:61 brd ff:ff:ff:ff:ff:ff\r
+ vf 0 MAC 00:11:22:33:00:11, vlan 1, spoof checking on, link-state auto, trust off\r
+ vf 1 MAC 00:11:22:33:01:11, vlan 2, spoof checking on, link-state auto, trust off\r
+ vf 2 MAC 00:11:22:33:02:11, vlan 3, spoof checking on, link-state auto, trust off\r
+ 12: enp136s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r
+ link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff\r
+ vf 0 MAC 00:11:22:33:00:00, vlan 1, spoof checking on, link-state auto, trust off\r
+ vf 1 MAC 00:11:22:33:01:00, vlan 2, spoof checking on, link-state auto, trust off\r
+ vf 2 MAC 00:11:22:33:02:00, vlan 3, spoof checking on, link-state auto, trust off\r
+ 14: enp136s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000\r
+ link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff\r
+ vf 0 MAC 00:11:22:33:00:10, vlan 1, spoof checking on, link-state auto, trust off\r
+ vf 1 MAC 00:11:22:33:01:10, vlan 2, spoof checking on, link-state auto, trust off\r
+ vf 2 MAC 00:11:22:33:02:10, vlan 3, spoof checking on, link-state auto, trust off\r
+ ...\r
+\r
+\r
+\r
+\r
+More information about VFs supported by Intel NICs can be found at\r
+https://doc.dpdk.org/guides/nics/intel_vf.html.\r
+\r
+The resulting configuration can look like the listing below, where six\r
+new VFs were added for each O-DU and O-RU port:::\r
+\r
+ lspci|grep Eth\r
+ 86:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 86:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 86:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) \r
+ 86:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 86:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02) \r
+ 86:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 86:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 86:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 88:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)\r
+ 88:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:02.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:0a.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:0a.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+ 88:0a.2 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)\r
+\r
+9. Example where O-DU and O-RU simulation run on the same system:\r
+\r
+O-DU:::\r
+\r
+ cat ./run_o_du.sh\r
+ #! /bin/bash\r
+\r
+ ulimit -c unlimited\r
+ echo 1 > /proc/sys/kernel/core_uses_pid\r
+\r
+ ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_du.cfg --num_eth_vfs 6 \\r
+ --vf_addr_o_xu_a "0000:88:02.0,0000:88:0a.0" \\r
+ --vf_addr_o_xu_b "0000:88:02.1,0000:88:0a.1" \\r
+ --vf_addr_o_xu_c "0000:88:02.2,0000:88:0a.2"\r
+\r
+\r
+O-RU::\r
+\r
+ cat ./run_o_ru.sh\r
+ #! /bin/bash\r
+ ulimit -c unlimited\r
+ echo 1 > /proc/sys/kernel/core_uses_pid\r
+\r
+ ./build/sample-app --usecasefile ./usecase/cat_b/mu1_100mhz/301/usecase_ru.cfg --num_eth_vfs 6 \\r
+ --vf_addr_o_xu_a "0000:86:02.0,0000:86:0a.0" \\r
+ --vf_addr_o_xu_b "0000:86:02.1,0000:86:0a.1" \\r
+ --vf_addr_o_xu_c "0000:86:02.2,0000:86:0a.2"\r
+\r
+\r
+Install and Configure Sample Application\r
+========================================\r
+\r
+To install and configure the sample application:\r
+\r
+1. Set up the environment::\r
+\r
+ For Skylake and Cascadelake\r
+ export GTEST_ROOT=pwd/gtest-1.7.0\r
+ export RTE_SDK=pwd/dpdk-20.11\r
+ export RTE_TARGET=x86_64-native-linuxapp-icc\r
+ export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk\r
+ export WIRELESS_SDK_TARGET_ISA=avx512\r
+ export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc\r
+ export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}\r
+ export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog\r
+ export XRAN_DIR=pwd/flexran_xran\r
+\r
+ for Icelake\r
+ export GTEST_ROOT=pwd/gtest-1.7.0\r
+ export RTE_SDK=pwd/dpdk-20.11\r
+ export RTE_TARGET=x86_64-native-linuxapp-icc\r
+ export DIR_WIRELESS_SDK_ROOT=pwd/wireless_sdk\r
+ export WIRELESS_SDK_TARGET_ISA=snc\r
+ export SDK_BUILD=build-${WIRELESS_SDK_TARGET_ISA}-icc\r
+ export DIR_WIRELESS_SDK=${DIR_WIRELESS_SDK_ROOT}/${SDK_BUILD}\r
+ export MLOG_DIR=pwd/flexran_l1_sw/libs/mlog\r
+ export XRAN_DIR=pwd/flexran_xran\r
+\r
+2. export FLEXRAN_SDK=${DIR_WIRELESS_SDK}/install Compile mlog library::\r
+\r
+ [turner@xran home]$ cd $MLOG_DIR\r
+ [turner@xran xran]$ ./build.sh\r
+\r
+3. Compile xRAN library and test the application::\r
+\r
+ [turner@xran home]$ cd $XRAN_DIR\r
+ [turner@xran xran]$ ./build.sh\r
+\r
+4. Configure the sample app.\r
+\r
+IQ samples can be generated using Octave\* and script\r
+libs/xran/app/gen_test.m. (CentOS\* has octave-3.8.2-20.el7.x86_64\r
+compatible with get_test.m)\r
+\r
+Other IQ sample test vectors can be used as well. The format of IQ\r
+samples is binary int16_t I and Q for N slots of the OTA RF signal. For\r
+example, for mmWave, it corresponds to 792RE*2*14symbol*8slots*10 ms =\r
+3548160 bytes per antenna. Refer to comments in gen_test.m to correctly\r
+specify the configuration for IQ test vector generation.\r
+\r
+Update usecase_du.dat (or usecase_ru.cfg) with a suitable configuration\r
+for your scenario.\r
+\r
+Update config_file_o_du.dat (or config_file_o_ru.dat) with a suitable\r
+configuration for your scenario.\r
+\r
+Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1\r
+used for U-plane and C-plane correspondingly.\r
+\r
+5. Run the application using run_o_du.sh (run_o_ru.sh).\r
+\r
+Install and Configure FlexRAN 5G NR L1 Application\r
+==================================================\r
+\r
+The 5G NR layer 1 application can be used for executing the scenario for\r
+mmWave with either the RU sample application or just the O-DU side. The\r
+current release supports the constant configuration of the slot pattern\r
+and RB allocation on the PHY side. The build process follows the same\r
+basic steps as for the sample application above and is similar to\r
+compiling 5G NR l1app for mmWave with Front Haul FPGA. Please follow the\r
+general build process in the FlexRAN 5G NR Reference Solution L1 User\r
+Guide (refer to *Table 2*.)\r
+\r
+1. xRAN library is enabled by default l1 application:\r
+\r
+2. Build the 5G NR L1 application using the command::\r
+\r
+ ./flexran_build.sh -r 5gnr_mmw -i avx512 -m sdk -m fb -m mlog –m wls -m\r
+ 5gnr_l1app_mmw -m xran -m 5gnr_testmac\r
+\r
+3. Configure the L1app using bin/nr5g/gnb/l1/phycfg_xran.xml and\r
+xrancfg_sub6.xml (or other xml if it is mmwave or massive MIMO). ::\r
+\r
+ <XranConfig>\r
+ <version>20.08</version>\r
+ <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->\r
+ <oRuNum>1</oRuNum>\r
+ <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->\r
+ <oRuEthLinkSpeed>25</oRuEthLinkSpeed>\r
+ <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->\r
+ <oRuLinesNumber>1</oRuLinesNumber>\r
+\r
+ <!-- O-RU 0 -->\r
+ <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>\r
+ <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>\r
+ <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>\r
+ <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>\r
+\r
+ <!-- O-RU 1 -->\r
+ <PciBusAddoRu1Vf0>0000:51:01.4</PciBusAddoRu1Vf0>\r
+ <PciBusAddoRu1Vf1>0000:51:01.5</PciBusAddoRu1Vf1>\r
+ <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>\r
+ <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>\r
+\r
+ <!-- O-RU 2 -->\r
+ <PciBusAddoRu2Vf0>0000:51:02.0</PciBusAddoRu2Vf0>\r
+ <PciBusAddoRu2Vf1>0000:51:02.1</PciBusAddoRu2Vf1>\r
+ <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>\r
+ <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>\r
+\r
+ <!-- O-RU 4 -->\r
+ <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>\r
+ <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>\r
+ <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>\r
+ <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>\r
+\r
+ <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->\r
+ <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>\r
+ <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>\r
+ <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->\r
+ <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>\r
+ <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>\r
+\r
+ <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->\r
+ <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>\r
+ <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>\r
+ <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->\r
+ <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>\r
+ <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>\r
+\r
+ <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->\r
+ <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>\r
+ <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>\r
+ <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->\r
+ <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>\r
+ <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>\r
+\r
+ <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->\r
+ <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>\r
+ <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>\r
+ <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->\r
+ <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>\r
+ <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu0NumCc>1</oRu0NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu0Cc0PhyId>0</oRu0Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu0Cc1PhyId>1</oRu0Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu0Cc2PhyId>2</oRu0Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu0Cc3PhyId>3</oRu0Cc3PhyId>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu0Cc4PhyId>4</oRu0Cc4PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu0Cc5PhyId>5</oRu0Cc5PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu0Cc6PhyId>6</oRu0Cc6PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu0Cc7PhyId>7</oRu0Cc7PhyId>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu0Cc8PhyId>8</oRu0Cc8PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu0Cc9PhyId>9</oRu0Cc9PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu0Cc10PhyId>10</oRuCc10PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu0Cc11PhyId>11</oRu0Cc11PhyId>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu1NumCc>1</oRu1NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu1Cc0PhyId>1</oRu1Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu1Cc1PhyId>1</oRu1Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu1Cc2PhyId>2</oRu1Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu1Cc3PhyId>3</oRu1Cc3PhyId>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu2NumCc>1</oRu2NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu2Cc0PhyId>2</oRu2Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu2Cc1PhyId>1</oRu2Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu2Cc2PhyId>2</oRu2Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu2Cc3PhyId>3</oRu2Cc3PhyId>\r
+\r
+ <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->\r
+ <xRANThread>19, 96, 0</xRANThread>\r
+\r
+ <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->\r
+ <xRANWorker>0x0, 96, 0</xRANWorker>\r
+ <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->\r
+ <Category>0</Category>\r
+\r
+ <!-- XRAN: enable sleep on PMD cores -->\r
+ <xranPmdSleep>0</xranPmdSleep>\r
+\r
+\r
+ <!-- RU Settings -->\r
+ <Tadv_cp_dl>25</Tadv_cp_dl>\r
+ <!-- Reception Window C-plane DL-->\r
+ <T2a_min_cp_dl>50</T2a_min_cp_dl>\r
+ <T2a_max_cp_dl>140</T2a_max_cp_dl>\r
+ <!-- Reception Window C-plane UL-->\r
+ <T2a_min_cp_ul>50</T2a_min_cp_ul>\r
+ <T2a_max_cp_ul>140</T2a_max_cp_ul>\r
+ <!-- Reception Window U-plane -->\r
+ <T2a_min_up>25</T2a_min_up>\r
+ <T2a_max_up>140</T2a_max_up>\r
+ <!-- Transmission Window U-plane -->\r
+ <Ta3_min>20</Ta3_min>\r
+ <Ta3_max>32</Ta3_max>\r
+\r
+ <!-- O-DU Settings -->\r
+ <!-- MTU size -->\r
+ <MTU>9600</MTU>\r
+ <!-- VLAN Tag used for C-Plane -->\r
+ <c_plane_vlan_tag>1</c_plane_vlan_tag>\r
+ <u_plane_vlan_tag>2</u_plane_vlan_tag>\r
+\r
+ <!-- Transmission Window Fast C-plane DL -->\r
+ <T1a_min_cp_dl>70</T1a_min_cp_dl>\r
+ <T1a_max_cp_dl>100</T1a_max_cp_dl>\r
+ <!-- Transmission Window Fast C-plane UL -->\r
+ <T1a_min_cp_ul>60</T1a_min_cp_ul>\r
+ <T1a_max_cp_ul>70</T1a_max_cp_ul>\r
+ <!-- Transmission Window U-plane -->\r
+ <T1a_min_up>35</T1a_min_up>\r
+ <T1a_max_up>50</T1a_max_up>\r
+ <!-- Reception Window U-Plane-->\r
+ <Ta4_min>0</Ta4_min>\r
+ <Ta4_max>45</Ta4_max>\r
+\r
+ <!-- Enable Control Plane -->\r
+ <EnableCp>1</EnableCp>\r
+\r
+ <DynamicSectionEna>0</DynamicSectionEna>\r
+ <!-- Enable Dynamic section allocation for UL -->\r
+ <DynamicSectionEnaUL>0</DynamicSectionEnaUL>\r
+ <xRANSFNWrap>0</xRANSFNWrap>\r
+ <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->\r
+ <xRANNumDLPRBs>0</xRANNumDLPRBs>\r
+ <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->\r
+ <xRANNumULPRBs>0</xRANNumULPRBs>\r
+ <!-- refer to alpha as defined in section 9.7.2 of O-RAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->\r
+ <Gps_Alpha>0</Gps_Alpha>\r
+ <!-- beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767 -->\r
+ <Gps_Beta>0</Gps_Beta>\r
+\r
+ <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->\r
+ <xranCompMethod>0</xranCompMethod>\r
+\r
+ <oRu0nPrbElemDl>1</oRu0nPrbElemDl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>\r
+ <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>\r
+ <oRu0PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu0PrbElemDl2>\r
+ <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>\r
+ <oRu0PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>\r
+ <oRu0PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>\r
+ <oRu0PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>\r
+ <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>\r
+ <oRu0nPrbElemUl>1</nPrbElemUl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>\r
+ <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>\r
+ <oRu0PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu0PrbElemUl2>\r
+ <oRu0PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>\r
+ <oRu0PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>\r
+ <oRu0PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>\r
+ <oRu0PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>\r
+ <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>\r
+\r
+ </XranConfig>\r
+\r
+4. Modify bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::\r
+\r
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.0\r
+ $RTE_SDK/usertools/dpdk-devbind.py --bind=vfio-pci 0000:21:02.1\r
+\r
+5. Use configuration of test mac per::\r
+\r
+ /bin/nr5g/gnb.testmac/cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r
+ phystart 4 0 40200\r
+ <!-- mmWave mu 3 100MHz -->\r
+ TEST_FD, 1002, 1, fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r
+\r
+\r
+6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::\r
+\r
+ [root@xran flexran] cd ./bin/nr5g/gnb/l1\r
+ [root@xran l1]#./l1.sh –xran\r
+\r
+where output corresponding L1 is::\r
+\r
+ [root@sc12-xran-sub6 l1]# ./l1.sh -xranmmw\r
+ Radio mode with XRAN - mmWave 100Mhz\r
+ DPDK WLS MODE\r
+ kernel.sched_rt_runtime_us = -1\r
+ kernel.shmmax = 2147483648\r
+ kernel.shmall = 2147483648\r
+ Note: Forwarding request to 'systemctl disable irqbalance.service'.\r
+ using configuration file phycfg_xran_mmw.xml\r
+ >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran_mmw.xml\r
+ FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_llr_demapping version #DIRTY#\r
+ FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r
+ FlexRAN SDK bblib_reed_muller version #DIRTY#\r
+ FlexRAN SDK bblib_lte_modulation version #DIRTY#\r
+ FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r
+ FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fd_correlation version #DIRTY#\r
+ FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r
+ FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fft_ifft version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_common version #DIRTY#\r
+ FlexRAN SDK bblib_lte_crc version #DIRTY#\r
+ FlexRAN SDK bblib_lte_dft_idft version #DIRTY#\r
+ FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#\r
+ FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#\r
+ =========================\r
+ 5GNR PHY Application\r
+ =========================\r
+ ---------------------------\r
+ PhyCfg.xml Version: 20.04\r
+ ---------------------------\r
+ --version=20.04\r
+ --successiveNoApi=15\r
+ --wls_dev_name=wls0\r
+ --wlsMemorySize=0x3F600000\r
+ --dlIqLog=0\r
+ --ulIqLog=0\r
+ --iqLogDumpToFile=0x0\r
+ --phyMlog=1\r
+ --phyStats=1\r
+ --dpdkMemorySize=8192\r
+ --dpdkIovaMode=0\r
+ --dpdkBasebandFecMode=1\r
+ --dpdkBasebandDevice=0000:1f:00.1\r
+ --radioEnable=4\r
+ --ferryBridgeMode=1\r
+ --ferryBridgeEthPort=1\r
+ --ferryBridgeSyncPorts=0\r
+ --ferryBridgeOptCableLoopback=0\r
+ --radioCfg0PCIeEthDev=0000:19:00.0\r
+ --radioCfg0DpdkRx=1\r
+ --radioCfg0DpdkTx=2\r
+ --radioCfg0TxAnt=2\r
+ --radioCfg0RxAnt=2\r
+ --radioCfg0RxAgc=0\r
+ --radioCfg0NumCell=1\r
+ --radioCfg0Cell0PhyId=0\r
+ --radioCfg0Cell1PhyId=1\r
+ --radioCfg0Cell2PhyId=2\r
+ --radioCfg0Cell3PhyId=3\r
+ --radioCfg0Cell4PhyId=4\r
+ --radioCfg0Cell5PhyId=5\r
+ --radioCfg0riuMac=11:22:33:44:55:66\r
+ --radioCfg1PCIeEthDev=0000:03:00.1\r
+ --radioCfg1DpdkRx=1\r
+ --radioCfg1DpdkTx=1\r
+ --radioCfg1TxAnt=4\r
+ --radioCfg1RxAnt=4\r
+ --radioCfg1RxAgc=0\r
+ --radioCfg1NumCell=1\r
+ --radioCfg1Cell0PhyId=2\r
+ --radioCfg1Cell1PhyId=3\r
+ --radioCfg1Cell2PhyId=2\r
+ --radioCfg1Cell3PhyId=3\r
+ --radioCfg1riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg2PCIeEthDev=0000:05:00.0\r
+ --radioCfg2DpdkRx=10\r
+ --radioCfg2DpdkTx=11\r
+ --radioCfg2TxAnt=4\r
+ --radioCfg2RxAnt=4\r
+ --radioCfg2RxAgc=0\r
+ --radioCfg2NumCell=2\r
+ --radioCfg2Cell0PhyId=4\r
+ --radioCfg2Cell1PhyId=5\r
+ --radioCfg2Cell2PhyId=2\r
+ --radioCfg2Cell3PhyId=3\r
+ --radioCfg2riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg3PCIeEthDev=0000:05:00.1\r
+ --radioCfg3DpdkRx=12\r
+ --radioCfg3DpdkTx=13\r
+ --radioCfg3TxAnt=4\r
+ --radioCfg3RxAnt=4\r
+ --radioCfg3RxAgc=0\r
+ --radioCfg3NumCell=2\r
+ --radioCfg3Cell0PhyId=6\r
+ --radioCfg3Cell1PhyId=7\r
+ --radioCfg3Cell2PhyId=2\r
+ --radioCfg3Cell3PhyId=3\r
+ --radioCfg3riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg4PCIeEthDev=0000:00:08.0\r
+ --radioCfg4DpdkRx=14\r
+ --radioCfg4DpdkTx=15\r
+ --radioCfg4TxAnt=4\r
+ --radioCfg4RxAnt=4\r
+ --radioCfg4RxAgc=0\r
+ --radioCfg4NumCell=2\r
+ --radioCfg4Cell0PhyId=8\r
+ --radioCfg4Cell1PhyId=9\r
+ --radioCfg4Cell2PhyId=2\r
+ --radioCfg4Cell3PhyId=3\r
+ --radioCfg4riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg5PCIeEthDev=0000:08:00.0\r
+ --radioCfg5DpdkRx=16\r
+ --radioCfg5DpdkTx=16\r
+ --radioCfg5TxAnt=4\r
+ --radioCfg5RxAnt=4\r
+ --radioCfg5RxAgc=0\r
+ --radioCfg5NumCell=2\r
+ --radioCfg5Cell0PhyId=10\r
+ --radioCfg5Cell1PhyId=11\r
+ --radioCfg5Cell2PhyId=2\r
+ --radioCfg5Cell3PhyId=3\r
+ --radioCfg5riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg6PCIeEthDev=0000:00:05.0\r
+ --radioCfg6DpdkRx=16\r
+ --radioCfg6DpdkTx=16\r
+ --radioCfg6TxAnt=4\r
+ --radioCfg6RxAnt=4\r
+ --radioCfg1RxAgc=0\r
+ --radioCfg6NumCell=2\r
+ --radioCfg6Cell0PhyId=12\r
+ --radioCfg6Cell1PhyId=13\r
+ --radioCfg6Cell2PhyId=2\r
+ --radioCfg6Cell3PhyId=3\r
+ --radioCfg6riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg7PCIeEthDev=0000:00:06.0\r
+ --radioCfg7DpdkRx=16\r
+ --radioCfg7DpdkTx=16\r
+ --radioCfg7TxAnt=4\r
+ --radioCfg7RxAnt=4\r
+ --radioCfg7RxAgc=0\r
+ --radioCfg7NumCell=2\r
+ --radioCfg7Cell0PhyId=14\r
+ --radioCfg7Cell1PhyId=15\r
+ --radioCfg7Cell2PhyId=2\r
+ --radioCfg7Cell3PhyId=3\r
+ --radioCfg7riuMac=ac:1f:6b:2c:9f:07\r
+ --radioPort0=0\r
+ --radioPort1=1\r
+ --radioPort2=2\r
+ --radioPort3=3\r
+ --radioPort4=4\r
+ --radioPort5=5\r
+ --radioPort6=6\r
+ --radioPort7=7\r
+ --PdschSymbolSplit=0\r
+ --PdschDlWeightSplit=0\r
+ --FecEncSplit=4\r
+ --PuschChanEstSplit=0\r
+ --PuschMmseSplit=0\r
+ --PuschLlrRxSplit=0\r
+ --PuschUlWeightSplit=0\r
+ --FecDecEarlyTermDisable=0\r
+ --FecDecNumIter=0\r
+ --FecDecSplit=4\r
+ --llrOutDecimalDigit=2\r
+ --IrcEnableThreshold=-10\r
+ --CEInterpMethod=0\r
+ --PucchSplit=0\r
+ --SrsCeSplit=0\r
+ --prachDetectThreshold=10000\r
+ --MlogSubframes=128\r
+ --MlogCores=20\r
+ --MlogSize=3084\r
+ --systemThread=0, 0, 0\r
+ --timerThread=0, 96, 0\r
+ --xRANThread=4, 96, 0\r
+ --xRANWorker=0x0, 96, 0\r
+ --FpgaDriverCpuInfo=2, 96, 0\r
+ --FrontHaulCpuInfo=3, 96, 0\r
+ --radioDpdkMaster=2, 99, 0\r
+ --BbuPoolSleepEnable=1\r
+ --BbuPoolThreadCorePriority=94\r
+ --BbuPoolThreadCorePolicy=0\r
+ --BbuPoolThreadDefault_0_63=0x68\r
+ --BbuPoolThreadDefault_64_127=0x0\r
+ --BbuPoolThreadSrs_0_63=0x0\r
+ --BbuPoolThreadSrs_64_127=0x0\r
+ --BbuPoolThreadDlbeam_0_63=0x0\r
+ --BbuPoolThreadDlbeam_64_127=0x0\r
+ --BbuPoolThreadUrllc=8\r
+ --FrontHaulTimeAdvance=9450\r
+ --nEthPorts=459523\r
+ --nPhaseCompFlag=1\r
+ --nFecFpgaVersionMu3=0xFC101800\r
+ --nFecFpgaVersionMu0_1=0x0319d420\r
+ --nFhFpgaVersionMu3=0x8001000F\r
+ --nFhFpgaVersionMu0_1=0x90010008\r
+ --dpdkXranDeviceCP=0000:21:02.1\r
+ --dpdkXranDeviceUP=0000:21:02.0\r
+ --DuMac=00:11:22:33:44:66\r
+ --RuMac=00:11:22:33:44:55\r
+ --Category=0\r
+ --xranPmdSleep=0\r
+ --Tadv_cp_dl=25\r
+ --T2a_min_cp_dl=50\r
+ --T2a_max_cp_dl=140\r
+ --T2a_min_cp_ul=50\r
+ --T2a_max_cp_ul=140\r
+ --T2a_min_up=25\r
+ --T2a_max_up=140\r
+ --Ta3_min=20\r
+ --Ta3_max=32\r
+ --MTU=9600\r
+ --c_plane_vlan_tag=1\r
+ --u_plane_vlan_tag=2\r
+ --T1a_min_cp_dl=70\r
+ --T1a_max_cp_dl=100\r
+ --T1a_min_cp_ul=60\r
+ --T1a_max_cp_ul=70\r
+ --T1a_min_up=35\r
+ --T1a_max_up=50\r
+ --Ta4_min=0\r
+ --Ta4_max=45\r
+ --DynamicSectionEna=0\r
+ --xRANSFNWrap=0\r
+ --xRANNumDLPRBs=0\r
+ --xRANNumULPRBs=0\r
+ --Gps_Alpha=0\r
+ --Gps_Beta=0\r
+ --xranCompMethod=0\r
+ --nPrbElemDl=0\r
+ --PrbElemDl0=0,48,0,14,1,1,1,9,1\r
+ --PrbElemDl1=48,48,0,14,2,1,1,9,1\r
+ --PrbElemDl2=96,48,0,14,3,1,1,9,1\r
+ --PrbElemDl3=144,48,0,14,4,1,1,9,1\r
+ --PrbElemDl4=144,36,0,14,5,1,1,9,1\r
+ --PrbElemDl5=180,36,0,14,6,1,1,9,1\r
+ --PrbElemDl6=216,36,0,14,7,1,1,9,1\r
+ --PrbElemDl7=252,21,0,14,8,1,1,9,1\r
+ --nPrbElemUl=0\r
+ --PrbElemUl0=0,48,0,14,1,1,1,9,1\r
+ --PrbElemUl1=48,48,0,14,2,1,1,9,1\r
+ --PrbElemUl2=72,36,0,14,3,1,1,9,1\r
+ --PrbElemUl3=108,36,0,14,4,1,1,9,1\r
+ --PrbElemUl4=144,36,0,14,5,1,1,9,1\r
+ --PrbElemUl5=180,36,0,14,6,1,1,9,1\r
+ --PrbElemUl6=216,36,0,14,7,1,1,9,1\r
+ --PrbElemUl7=252,21,0,14,8,1,1,9,1\r
+ --StreamStats=0\r
+ --StreamIp=127.0.0.1\r
+ --StreamPort=2000\r
+\r
+ wls_dev_filename: wls0\r
+ phycfg_apply: Initialize Radio Interface with XRAN library\r
+ Setting FecEncSplit to 1 to run on HW accelerator\r
+ Setting FecDecSplit to 1 to run on HW accelerator\r
+\r
+ timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596249953 [Hz]\r
+ Ticks per usec 1596\r
+ MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(20), mlogSize(3084) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(20), mlogSize(3084)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1596250020 [Hz]\r
+ Ticks per us 1596\r
+ MLog Storage: 0x7f6e5b0e3100 -> 0x7f6e5b86b52c [ 7898156 bytes ]\r
+ localMLogFreqReg: 1596. Storing: 1596\r
+ Mlog Open successful\r
+\r
+ di_xran_init\r
+ di_xran_cfg_setup successful\r
+ xran_init: MTU 9600\r
+ BBDEV_FEC_ACCL_NR5G\r
+ hw-accelerated bbdev 0000:1f:00.1\r
+ total cores 40 c_mask 0x14 core 4 [id] system_core 2 [id] pkt_proc_core 0x0 [mask] pkt_aux_core 0 [id] timing_core 4 [id]\r
+ xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x14 -n2 --iova-mode=pa --socket-mem=8192 --socket-limit=8192 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:1f:00.1\r
+ EAL: Detected 40 lcore(s)\r
+ EAL: Detected 1 NUMA nodes\r
+ EAL: Auto-detected process type: PRIMARY\r
+ EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket\r
+ EAL: Selected IOVA mode 'PA'\r
+ EAL: No available hugepages reported in hugepages-2048kB\r
+ EAL: Probing VFIO support...\r
+ EAL: VFIO support initialized\r
+ EAL: PCI device 0000:1f:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:d90 intel_fpga_5gnr_fec_vf\r
+ EAL: using IOMMU type 1 (Type 1)\r
+ EAL: PCI device 0000:21:02.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ initializing port 0 for TX, drv=net_i40e_vf\r
+ Port 0 MAC: 00 11 22 33 44 66\r
+ Port 0: nb_rxd 4096 nb_txd 4096\r
+\r
+ Checking link status portid [0] EAL: PCI device 0000:21:02.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ initializing port 1 for TX, drv=net_i40e_vf\r
+ Port 1 MAC: 00 11 22 33 44 66\r
+ Port 1: nb_rxd 4096 nb_txd 4096\r
+ Checking link status portid [1] vf 0 local SRC MAC: 00 11 22 33 44 66\r
+ vf 0 remote DST MAC: 00 11 22 33 44 55\r
+ vf 1 local SRC MAC: 00 11 22 33 44 66\r
+ vf 1 remote DST MAC: 00 11 22 33 44 55\r
+ xran_init successful, pHandle = 0x5581f440\r
+ bbdev_init:\r
+ Socket ID: 0\r
+ FEC is accelerated through BBDEV: 0000:1f:00.1\r
+ wls_layer_init[wls0] nWlsMemorySize[1063256064]\r
+ wls_lib: Open wls0 (DPDK memzone)\r
+ wls_lib: WLS_Open 0x2bf600000\r
+ wls_lib: link: 0 <-> 1\r
+ wls_lib: Mode 0\r
+ wls_lib: WLS shared management memzone: wls0\r
+ wls_lib: hugePageSize on the system is 1073741824\r
+ wls_lib: WLS_Alloc [1063256064] bytes\r
+\r
+\r
+ ===========================================================================================================\r
+ PHY VERSION\r
+ ===========================================================================================================\r
+ Version: #DIRTY#\r
+ IMG-date: Apr 27 2020\r
+ IMG-time: 12:54:54\r
+ ===========================================================================================================\r
+ DEPENDENCIES VERSIONS\r
+ ===========================================================================================================\r
+ FlexRAN BBU pooling version #DIRTY#\r
+ FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_llr_demapping version #DIRTY#\r
+ FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r
+ FlexRAN SDK bblib_reed_muller version #DIRTY#\r
+ FlexRAN SDK bblib_lte_modulation version #DIRTY#\r
+ FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r
+ FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fd_correlation version #DIRTY#\r
+ FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r
+ FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fft_ifft version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_lte_crc version #DIRTY#\r
+ FlexRAN SDK bblib_common version #DIRTY#\r
+ ===========================================================================================================\r
+\r
+ ===========================================================================================================\r
+ Non BBU threads in application\r
+ ===========================================================================================================\r
+ nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 112583] binding on [CPU 0] [PRIO: 0] [POLICY: 1]\r
+ wls_rx_handler (non-rt): [PID: 112587] binding on [CPU 0]\r
+ ===========================================================================================================\r
+ PHY>welcome to application console\r
+ PHY>Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r
+ Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0\r
+ phydi_read_write_iq_samples: direction[1] nNumerologyMult[8] fftSize[1024, 11088, SRS: 792] numSubframe[80] numAntenna[2] numPorts[2] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/mu3_100mhz/2/../../../ul/mu3_100mhz/1/uliq00_tst1.bin] filename_in_prach_iq[]\r
+ Received MSG_TYPE_PHY_CONFIG_REQ: 0\r
+ Processing MSG_TYPE_PHY_CONFIG_REQ: 0\r
+ phy_bbupool_set_config: Using cores: 0x0000000000000068 for BBU Pool nBbuPoolSleepEnable: 1\r
+ BBU Pooling: queueId = 0, the according nCoreNum = 3, the according cpuSetMask = 0x68\r
+ BBU Pooling: gCoreIdxMap[0] = 3 is available!\r
+ BBU Pooling: gCoreIdxMap[1] = 5 is available!\r
+ BBU Pooling: gCoreIdxMap[2] = 6 is available!\r
+ BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered\r
+ BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered\r
+ BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered\r
+ BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered\r
+ BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered\r
+ BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered\r
+ BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered\r
+ BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered\r
+ BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered\r
+ BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered\r
+ BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered\r
+ BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered\r
+ BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered\r
+ BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered\r
+ BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered\r
+ BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered\r
+ BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered\r
+ BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered\r
+ BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered\r
+ BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered\r
+ BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered\r
+ BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A\r
+\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX\r
+ BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A\r
+\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_SRS: UL_L1_POST\r
+ BBU Pooling: next taskList of DL_L1_POST: N/A\r
+\r
+ BBU Pooling: next taskList of UL_L1_POST: N/A\r
+\r
+ enter RtThread Launch\r
+ 3 thread associated with queue 0:coreIdx 0 1 2\r
+ Leave RtThread Launch\r
+ launching Thread 0 Queue 0 uCoreIdx 0 CoreId 3 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ bbupool_core_main: the server's coreNum = 40, the nCore = 3,nRtCoreMask = 0x68, the nFeIfCore = 0,nFeIfCoreMask = 0x0\r
+ bbupool_core_main pthread_setaffinity_np succeed: coreId = 0, result = 0\r
+ nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:\r
+ nCarrierIdx: 0\r
+ nDMRSTypeAPos: 2\r
+ nPhyCellId: 100\r
+ nDLAbsFrePointA: 27968160\r
+ nULAbsFrePointA: 27968160\r
+ nDLBandwidth: 100\r
+ nULBandwidth: 100\r
+ nDLFftSize: 1024\r
+ nULFftSize: 1024\r
+ nSSBPwr: 0\r
+ nSSBAbsFre: 0\r
+ nSSBPeriod: 2\r
+ nSSBSubcSpacing: 3\r
+ nSSBSubcOffset: 0\r
+ nSSBPrbOffset: 0\r
+ nMIB[0]: 255\r
+ nMIB[1]: 255\r
+ nMIB[2]: 255\r
+ nDLK0: 0\r
+ nULK0: 0\r
+ nSSBMask[0]: 63\r
+ nSSBMask[1]: 0\r
+ nNrOfTxAnt: 2\r
+ nNrOfRxAnt: 2\r
+ nNrOfDLPorts: 2\r
+ nNrOfULPorts: 2\r
+ nCarrierAggregationLevel: 0\r
+ nFrameDuplexType: 1\r
+ nSubcCommon: 3\r
+ nTddPeriod: 5 (TDD)\r
+ SlotConfig:\r
+ Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r
+ 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+\r
+ nPrachConfIdx: 81\r
+ nPrachSubcSpacing: 3\r
+ nPrachZeroCorrConf: 2\r
+ nPrachRestrictSet: 0\r
+ nPrachRootSeqIdx: 0\r
+ nPrachFreqStart: 0\r
+ nPrachFdm: 1\r
+ nPrachSsbRach: 0\r
+ nPrachNrofRxRU: 2\r
+ nCyclicPrefix: 0\r
+ nGroupHopFlag: 0\r
+ nSequenceHopFlag: 0\r
+ nHoppingId: 0\r
+ read_table: File table/common/pss_table.bin of size 381 read_size: 381\r
+ read_table: File table/common/sss_table.bin of size 128016 read_size: 128016\r
+ read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916\r
+ read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040\r
+ read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216\r
+ read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216\r
+ BBU Pooling Info: maximum period length was configured, preMaxSF = 8000, postMasSF = 8000\r
+ set_slot_type SlotPattern:\r
+ Slot: 0 1 2 3 4\r
+ 0 DL DL DL SP UL\r
+\r
+ PHYDI-INIT[from 0] PhyInstance: 0\r
+\r
+ ---------------------------------------------------------\r
+ Global Variables:\r
+ ---------------------------------------------------------\r
+ gCarrierAggLevel: 0\r
+ gCarrierAggLevelInit: 1\r
+ gSupportedAVX2 1\r
+ ---------------------------------------------------------\r
+\r
+ Received MSG_TYPE_PHY_START_REQ: 0\r
+ Processing MSG_TYPE_PHY_START_REQ: 0\r
+\r
+ xran_max_frame 99\r
+ XRAN_UP_VF: 0x0000\r
+ XRAN_CP_VF: 0x0001\r
+ xran_timing_source_thread [CPU 4] [PID: 112582]\r
+ O-DU: thread_run start time: 04/27/20 20:20:33.000000010 UTC [125]\r
+ Start C-plane DL 25 us after TTI [trigger on sym 3]\r
+ Start C-plane UL 55 us after TTI [trigger on sym 7]\r
+ Start U-plane DL 50 us before OTA [offset in sym -5]\r
+ Start U-plane UL 45 us OTA [offset in sym 6]\r
+ C-plane to U-plane delay 25 us after TTI\r
+ Start Sym timer 8928 ns\r
+ interval_us 125\r
+ PHYDI-START[from 0] PhyInstance: 0, Mode: 4, Count: 100040207, Period: 0, NumSlotPerSfn: 80\r
+ gnb_start_xran: gxRANStarted[0] CC 1 Ant 4 AntElm 0\r
+ XRAN front haul xran_mm_init\r
+ xran_sector_get_instances [0]: CC 0 handle 0x7f6e397307c0\r
+ Handle: 0x1994ce00 Instance: 0x7f6e397307c0\r
+ gnb_start_xran [0]: CC 0 handle 0x7f6e397307c0\r
+ Sucess xran_mm_init Instance 0x7f6e397307c0\r
+ nSectorNum 1\r
+ ru_0_cc_0_idx_0: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 0] nNumberOfBuffers 2240 nBufferSize 5856\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2e817b900\r
+ ru_0_cc_0_idx_1: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 1] nNumberOfBuffers 35840 nBufferSize 24\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x2e7266c40\r
+ ru_0_cc_0_idx_2: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 2] nNumberOfBuffers 2240 nBufferSize 48416\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x2e5cb4600\r
+ ru_0_cc_0_idx_3: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 3] nNumberOfBuffers 2240 nBufferSize 5856\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x2df2872c0\r
+ ru_0_cc_0_idx_4: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 4] nNumberOfBuffers 35840 nBufferSize 24\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x2de372600\r
+ ru_0_cc_0_idx_5: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 5] nNumberOfBuffers 2240 nBufferSize 48416\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x2dcdbffc0\r
+ ru_0_cc_0_idx_6: [ handle 0x7f6e397307c0 0 0 ] [nPoolIndex 6] nNumberOfBuffers 2240 nBufferSize 8192\r
+ CC:[ handle 0x7f6e397307c0 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x2d6392c80\r
+ gnb_init_xran_cp\r
+ init xran successfully\r
+ ----------------------------------------------------------------------------\r
+ mem_mgr_display_size:\r
+ Num Memory Alloc: 5,186\r
+ Total Memory Size: 4,389,524,920\r
+ ----------------------------------------------------------------------------\r
+\r
+\r
+ BBU Pooling: enter multicell Activate!\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 547270377116554 at sf=0 with queue 0 successfully\r
+ BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 1\r
+ BBU Pooling: multiCell Activate sucessfully!\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 3 at 547270377104408 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 547270377117634 at sf=0 with queue 0 successfully\r
+ phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[80]\r
+ ==== l1app Time: 5001 ms NumCarrier: 1 NumBbuCores: 3 rxPcktCnt: 93621 rachPcktCnt 46811 Total Proc Time: [ 62.00.. 98.39..209.00] usces====\r
+ ==== [o-du][rx 619683 pps 123936 kbps 2621619][tx 1996407 pps 399281 kbps 9181862] [on_time 619683 early 0 late 0 corrupt 0 pkt_dupl 16 Total 619683] IO Util: 79.61 %\r
+\r
+\r
+7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::\r
+\r
+ [root@xran flexran] cd ./bin/nr5g/gnb/testmac\r
+\r
+\r
+8. To execute test case type::\r
+\r
+ ./l2.sh\r
+ --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r
+\r
+\r
+where output corresponding to Test MAC::\r
+\r
+ [root@sc12-xran-sub6 testmac]# ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r
+ kernel.sched_rt_runtime_us = -1\r
+ kernel.shmmax = 2147483648\r
+ kernel.shmall = 2147483648\r
+ Note: Forwarding request to 'systemctl disable irqbalance.service'.\r
+ start 5GNR Test MAC\r
+ =========================\r
+ 5GNR Testmac Application\r
+ =========================\r
+ testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml\r
+ ---------------------------\r
+ TestMacCfg.xml Version: 20.04\r
+ ---------------------------\r
+ --version=20.04\r
+ --wls_dev_name=wls0\r
+ --wlsMemorySize=0x3F600000\r
+ --dpdkIovaMode=0\r
+ --PhyStartMode=1\r
+ --PhyStartPeriod=40\r
+ --PhyStartCount=0\r
+ --MlogSubframes=128\r
+ --MlogCores=3\r
+ --MlogSize=2048\r
+ --wlsRxThread=1, 90, 0\r
+ --systemThread=0, 0, 0\r
+ --runThread=0, 89, 0\r
+ --urllcThread=19, 90, 0\r
+\r
+ wls_dev_filename: wls0\r
+ sys_reg_signal_handler:[err] signal handler in NULL\r
+ sys_reg_signal_handler:[err] signal handler in NULL\r
+ timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1596245684 [Hz]\r
+ Ticks per usec 1596\r
+ MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(3), mlogSize(2048)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1596250375 [Hz]\r
+ Ticks per us 1596\r
+ MLog Storage: 0x7f84cae86100 -> 0x7f84caf46920 [ 788512 bytes ]\r
+ localMLogFreqReg: 1596. Storing: 1596\r
+ Mlog Open successful\r
+ Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa\r
+ EAL: Detected 40 lcore(s)\r
+ EAL: Detected 1 NUMA nodes\r
+ EAL: Auto-detected process type: SECONDARY\r
+ EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_112640_1f1baf0a9b316\r
+ EAL: Selected IOVA mode 'PA'\r
+ EAL: Probing VFIO support...\r
+ EAL: VFIO support initialized\r
+ EAL: PCI device 0000:19:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:19:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:1d:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:1d:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:21:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:158b net_i40e\r
+ EAL: PCI device 0000:21:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:158b net_i40e\r
+ EAL: PCI device 0000:21:02.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ EAL: using IOMMU type 1 (Type 1)\r
+ EAL: PCI device 0000:21:02.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ EAL: PCI device 0000:21:0a.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ EAL: 0000:21:0a.0 cannot find TAILQ entry for PCI device!\r
+ EAL: Requested device 0000:21:0a.0 cannot be used\r
+ EAL: PCI device 0000:21:0a.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:154c net_i40e_vf\r
+ EAL: 0000:21:0a.1 cannot find TAILQ entry for PCI device!\r
+ EAL: Requested device 0000:21:0a.1 cannot be used\r
+ EAL: PCI device 0000:67:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:37d2 net_i40e\r
+ EAL: PCI device 0000:67:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:37d2 net_i40e\r
+ wls_lib: Open wls0 (DPDK memzone)\r
+ wls_lib: WLS_Open 0x2bf600000\r
+ wls_lib: link: 1 <-> 0\r
+ wls_lib: Mode 1\r
+ wls_lib: WLS shared management memzone: wls0\r
+ wls_lib: hugePageSize on the system is 1073741824\r
+ wls_lib: WLS_Alloc [1063256064] bytes\r
+ wls_lib: Connecting to remote peer ...\r
+ wls_lib: Connected to remote peer\r
+ wls_mac_create_mem_array: pMemArray[0xf3500f0] pMemArrayMemory[0x280000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056]\r
+ WLS_EnqueueBlock [1]\r
+ WLS inited ok [383]\r
+ ===========================================================================================================\r
+ TESTMAC VERSION\r
+ ===========================================================================================================\r
+ $Version: #DIRTY# $ (x86)\r
+ IMG-date: Apr 27 2020\r
+ IMG-time: 12:55:58\r
+ ===========================================================================================================\r
+ ===========================================================================================================\r
+ Testmac threads in application\r
+ ===========================================================================================================\r
+ testmac_run_thread: [PID: 112644] binding on [CPU 0] [PRIO: 89] [POLICY: 1]\r
+ wls_mac_rx_task: [PID: 112643] binding on [CPU 1] [PRIO: 90] [POLICY: 1]\r
+ ===========================================================================================================\r
+\r
+ testmac_set_phy_start: mode[1], period[40], count[0]\r
+\r
+ testmac_run_load_files:\r
+ Loading DL Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg\r
+ Loading UL Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg\r
+ Loading FD Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg\r
+\r
+ TESTMAC DL TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[0] Bandwidth[20]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[1] Bandwidth[100]\r
+ 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211\r
+ 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221\r
+ 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241\r
+ 1242 1243 1244 1245 1250 1251 1252 1300 1301 1302\r
+ 1303 1304 1305 1402 1404 1408 1416 1500 1501 1502\r
+ 1503 1504 1505 1506 2213 2214 2215 2217 2218 2219\r
+ 2223 2224 2225 2227 2228 2229 2500 2501 2502 2503\r
+ 2504 3213 3214 3215 3217 3218 3219 3223 3224 3225\r
+ 3227 3228 3229\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011\r
+ 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031\r
+ 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003\r
+ 3030\r
+\r
+ TESTMAC UL TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 1002 1003\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 1002\r
+ Numerology[0] Bandwidth[20]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[1] Bandwidth[100]\r
+ 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038\r
+ 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074\r
+ 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092\r
+ 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105\r
+ 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117\r
+ 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132\r
+ 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142\r
+ 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160\r
+ 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170\r
+ 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206\r
+ 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216\r
+ 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233\r
+ 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421\r
+ 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431\r
+ 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504\r
+ 1505 1506 1507 1508 1511 1512 1513 1514 1515 1516\r
+ 1540 1541 1542 1563 1564 1565 1566 1567 1568 1569\r
+ 1570 1571 1572 1573 1574 1600 1601 1602 1603 1604\r
+ 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614\r
+ 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624\r
+ 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634\r
+ 1635 1636 1637 1638 1639 1640 1641 1642 1700 1701\r
+ 2236 2237 3236 3237\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012\r
+ 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026\r
+ 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036\r
+ 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051\r
+ 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065\r
+ 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084\r
+ 1085 1086 2001 2002 2003 3001 3002 3003\r
+\r
+ TESTMAC FD TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 6001 8001 10001 12001\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002\r
+ 6002 8002 10002 12002 1003\r
+ Numerology[0] Bandwidth[20]\r
+ 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021\r
+ 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201\r
+ 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221\r
+ 1222 1223 1224 1225 1226 1227 1228\r
+ Numerology[1] Bandwidth[40]\r
+ 1001 1002 1003\r
+ Numerology[1] Bandwidth[100]\r
+ 1001 1200 1201 1202 1203 1204 1205 1206 1207 1208\r
+ 1209 1210 1300 1301 1302 1303 1304 1305 1306 1307\r
+ 1308 1350 1351 1352 1353 1354 1355 1356 1357 1358\r
+ 1370 1371 1372 1373 1401 1402 1403 1404 1405 1406\r
+ 1411 1412 1490 1494 1500 1501 1502 1503 1504 1510\r
+ 1511 1512 1513 1514 1515 1520 1521 1522 1523 1524\r
+ 1525 1526 1527 1528 1529 1530 1531 1532 1540 1541\r
+ 1700 1701 1702 2520 2521 2522 2523 2524 2525 2526\r
+ 2527 2528 2529 2530 2531 2532 3524 3525 3526 3527\r
+ 3528 3529 3530 3531 3532 4524 4525 4526 4527 4528\r
+ 4529 4530 4531 4532\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011\r
+ 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080\r
+ 1081 1082 2001 3001\r
+ testmac_run_parse_file Parsing config file: ./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r
+ testmac_set_phy_start: mode[4], period[0], count[100040200]\r
+ Adding Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/\r
+ Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r
+ ----------------------------------------------------------------------------------------\r
+ Running Test[1002]. NumCarr[1], Current Directory: /home/turner/xran/master/npg_wireless-flexran_l1_5g_test/\r
+ Carrier[0]: ConfigFile: fd/mu3_100mhz/2/fd_testconfig_tst2.cfg\r
+ TESTMAC>welcome to application console\r
+\r
+ MLogRestart\r
+ MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(3), mlogSize(2048)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1596249901 [Hz]\r
+ Ticks per us 1596\r
+ MLog Storage: 0x7f84bc000900 -> 0x7f84bc0c1120 [ 788512 bytes ]\r
+ localMLogFreqReg: 1596. Storing: 1596\r
+ Mlog Open successful\r
+\r
+ testmac_mac2phy_set_num_cells: Setting Max Cells: 1\r
+ testmac_config_parse: test_num[1002] test_type[2] numcarrier[1]\r
+ host_config_set_int Error(nPrachSsbRach, 3): Out of range: [min(0), max(1)]\r
+ Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r
+ Queueing MSG_TYPE_PHY_CONFIG_REQ(0) and sending list\r
+ Received MSG_TYPE_PHY_CONFIG_RESP(0)\r
+ Queueing MSG_TYPE_PHY_START_REQ(0) and sending list\r
+ Received MSG_TYPE_PHY_START_RESP(0)\r
+ ==== testmac Time: 5000 ms NumCarrier: 1 Total Proc Time: [ 0.00.. 4.11.. 14.00] usces====\r
+ Core Utilization [Core: 1] [Util %: 2.97%]\r
+ ==== testmac Time: 10000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 13.00] usces====\r
+ Core Utilization [Core: 1] [Util %: 4.81%]\r
+ ==== testmac Time: 15000 ms NumCarrier: 1 Total Proc Time: [ 2.00.. 4.10.. 6.00] usces====\r
+\r
+\r
+Configure FlexRAN 5G NR L1 Application for multiple O-RUs with multiple numerologies\r
+====================================================================================\r
+\r
+The 5G NR layer 1 application can be used for executing the scenario for\r
+multiple cells with multiple numerologies. The current release supports\r
+the constant configuration of different numerologies on different O-RU\r
+ports. It is required that the first O-RU (O-RU0) to be configured with\r
+highest numerology. The configuration procedure is similar as described\r
+in above section. Please refer to the configuration file located in\r
+bin\nr5g\gnb\l1\orancfg\sub3_mu0_20mhz_sub6_mu1_100mhz_4x4\gnb\xrancfg_sub6_oru.xml\r
+\r
+Install and Configure FlexRAN 5G NR L1 Application for Massive - MIMO\r
+=====================================================================\r
+\r
+The 5G NR layer 1 application can be used for executing the scenario for\r
+Massive-MIMO with either the RU sample application or just the O-DU\r
+side. 3 cells scenario with 64T64R Massive MIMO is targeted for Icelake\r
+system with Columbiavile NIC. The current release supports the constant\r
+configuration of the slot pattern and RB allocation on the PHY side.\r
+Please follow the general build process in the FlexRAN 5G NR Reference\r
+Solution L1 User Guide (refer to Table 2.)\r
+\r
+1. xRAN library is enabled by default l1 application\r
+\r
+2. Build the 5G NR L1 application using the command::\r
+\r
+ ./flexran_build.sh -r 5gnr_l1app_sub6 -i snc -m sdk -m fb -m mlog –m wls\r
+ -m 5gnr_l1app_mmw -m xran -m 5gnr_testmac\r
+\r
+3. Configure the L1app using bin/nr5g/gnb/l1/xrancfg_sub6_mmimo.xml. ::\r
+\r
+ <XranConfig>\r
+ <version>20.08</version>\r
+ <!-- numbers of O-RU connected to O-DU. All O-RUs are the same capabilities. Max O-RUs is per XRAN_PORTS_NUM i.e. 4 -->\r
+ <oRuNum>3</oRuNum>\r
+ <!-- # 10G,25G,40G,100G speed of Physical connection on O-RU -->\r
+ <oRuEthLinkSpeed>25</oRuEthLinkSpeed>\r
+ <!-- # 1, 2, 3 total number of links per O-RU (Fronthaul Ethernet link in IOT spec) -->\r
+ <oRuLinesNumber>2</oRuLinesNumber>\r
+ <!-- (1) - C- plane and U-plane on the same set of VFs. (0) - C-plane and U-Plane use dedicated VFs -->\r
+ <oRuCUon1Vf>1</oRuCUon1Vf>\r
+\r
+ <!-- O-RU 0 -->\r
+ <PciBusAddoRu0Vf0>0000:51:01.0</PciBusAddoRu0Vf0>\r
+ <PciBusAddoRu0Vf1>0000:51:01.1</PciBusAddoRu0Vf1>\r
+ <PciBusAddoRu0Vf2>0000:51:01.2</PciBusAddoRu0Vf2>\r
+ <PciBusAddoRu0Vf3>0000:51:01.3</PciBusAddoRu0Vf3>\r
+\r
+ <!-- O-RU 1 -->\r
+ <PciBusAddoRu1Vf0>0000:51:01.2</PciBusAddoRu1Vf0>\r
+ <PciBusAddoRu1Vf1>0000:51:01.3</PciBusAddoRu1Vf1>\r
+ <PciBusAddoRu1Vf2>0000:51:01.6</PciBusAddoRu1Vf2>\r
+ <PciBusAddoRu1Vf3>0000:51:01.7</PciBusAddoRu1Vf3>\r
+\r
+ <!-- O-RU 2 -->\r
+ <PciBusAddoRu2Vf0>0000:51:01.4</PciBusAddoRu2Vf0>\r
+ <PciBusAddoRu2Vf1>0000:51:01.5</PciBusAddoRu2Vf1>\r
+ <PciBusAddoRu2Vf2>0000:51:02.2</PciBusAddoRu2Vf2>\r
+ <PciBusAddoRu2Vf3>0000:51:02.3</PciBusAddoRu2Vf3>\r
+\r
+ <!-- O-RU 4 -->\r
+ <PciBusAddoRu3Vf0>0000:00:00.0</PciBusAddoRu3Vf0>\r
+ <PciBusAddoRu3Vf1>0000:00:00.0</PciBusAddoRu3Vf1>\r
+ <PciBusAddoRu3Vf2>0000:00:00.0</PciBusAddoRu3Vf2>\r
+ <PciBusAddoRu3Vf3>0000:00:00.0</PciBusAddoRu3Vf3>\r
+\r
+ <!-- remote O-RU 0 Eth Link 0 VF0, VF1-->\r
+ <oRuRem0Mac0>00:11:22:33:00:01<oRuRem0Mac0>\r
+ <oRuRem0Mac1>00:11:22:33:00:11<oRuRem0Mac1>\r
+ <!-- remote O-RU 0 Eth Link 1 VF2, VF3 -->\r
+ <oRuRem0Mac2>00:11:22:33:00:21<oRuRem0Mac2>\r
+ <oRuRem0Mac3>00:11:22:33:00:31<oRuRem0Mac3>\r
+\r
+ <!-- remote O-RU 1 Eth Link 0 VF4, VF5-->\r
+ <oRuRem1Mac0>00:11:22:33:01:01<oRuRem1Mac0>\r
+ <oRuRem1Mac1>00:11:22:33:01:11<oRuRem1Mac1>\r
+ <!-- remote O-RU 1 Eth Link 1 VF6, VF7 -->\r
+ <oRuRem1Mac2>00:11:22:33:01:21<oRuRem1Mac2>\r
+ <oRuRem1Mac3>00:11:22:33:01:31<oRuRem1Mac3>\r
+\r
+ <!-- remote O-RU 2 Eth Link 0 VF8, VF9 -->\r
+ <oRuRem2Mac0>00:11:22:33:02:01<oRuRem2Mac0>\r
+ <oRuRem2Mac1>00:11:22:33:02:11<oRuRem2Mac1>\r
+ <!-- remote O-RU 2 Eth Link 1 VF10, VF11-->\r
+ <oRuRem2Mac2>00:11:22:33:02:21<oRuRem2Mac2>\r
+ <oRuRem2Mac3>00:11:22:33:02:31<oRuRem2Mac3>\r
+\r
+ <!-- remote O-RU 2 Eth Link 0 VF12, VF13 -->\r
+ <oRuRem3Mac0>00:11:22:33:03:01<oRuRem3Mac0>\r
+ <oRuRem3Mac1>00:11:22:33:03:11<oRuRem3Mac1>\r
+ <!-- remote O-RU 2 Eth Link 1 VF14, VF15-->\r
+ <oRuRem3Mac2>00:11:22:33:03:21<oRuRem3Mac2>\r
+ <oRuRem3Mac3>00:11:22:33:03:31<oRuRem3Mac3>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu0NumCc>1</oRu0NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu0Cc0PhyId>0</oRu0Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu0Cc1PhyId>1</oRu0Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu0Cc2PhyId>2</oRu0Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu0Cc3PhyId>3</oRu0Cc3PhyId>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu1NumCc>1</oRu1NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu1Cc0PhyId>1</oRu1Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu1Cc1PhyId>1</oRu1Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu1Cc2PhyId>2</oRu1Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu1Cc3PhyId>3</oRu1Cc3PhyId>\r
+\r
+ <!-- Number of cells (CCs) running on this O-RU [1 - Cell , 2 - Cells, 3 - Cells , 4 - Cells ] -->\r
+ <oRu2NumCc>1</oRu2NumCc>\r
+ <!-- First Phy instance ID mapped to this O-RU CC0 -->\r
+ <oRu2Cc0PhyId>2</oRu2Cc0PhyId>\r
+ <!-- Second Phy instance ID mapped to this O-RU CC1 -->\r
+ <oRu2Cc1PhyId>1</oRu2Cc1PhyId>\r
+ <!-- Third Phy instance ID mapped to this O-RU CC2 -->\r
+ <oRu2Cc2PhyId>2</oRu2Cc2PhyId>\r
+ <!-- Forth Phy instance ID mapped to this O-RU CC3 -->\r
+ <oRu2Cc3PhyId>3</oRu2Cc3PhyId>\r
+\r
+ <!-- XRAN Thread (core where the XRAN polling function is pinned: Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->\r
+ <xRANThread>22, 96, 0</xRANThread>\r
+\r
+ <!-- core mask for XRAN Packets Worker (core where the XRAN packet processing is pinned): Core, priority, Policy [0: SCHED_FIFO 1: SCHED_RR] -->\r
+ <xRANWorker>0x3800000, 96, 0</xRANWorker>\r
+ <!-- XRAN: Category of O-RU 0 - Category A, 1 - Category B -->\r
+ <Category>1</Category>\r
+\r
+ <!-- XRAN: enable sleep on PMD cores -->\r
+ <xranPmdSleep>0</xranPmdSleep>\r
+\r
+ <!-- RU Settings -->\r
+ <Tadv_cp_dl>25</Tadv_cp_dl>\r
+ <!-- Reception Window C-plane DL-->\r
+ <T2a_min_cp_dl>285</T2a_min_cp_dl>\r
+ <T2a_max_cp_dl>429</T2a_max_cp_dl>\r
+ <!-- Reception Window C-plane UL-->\r
+ <T2a_min_cp_ul>285</T2a_min_cp_ul>\r
+ <T2a_max_cp_ul>429</T2a_max_cp_ul>\r
+ <!-- Reception Window U-plane -->\r
+ <T2a_min_up>71</T2a_min_up>\r
+ <T2a_max_up>428</T2a_max_up>\r
+ <!-- Transmission Window U-plane -->\r
+ <Ta3_min>20</Ta3_min>\r
+ <Ta3_max>32</Ta3_max>\r
+\r
+ <!-- O-DU Settings -->\r
+ <!-- MTU size -->\r
+ <MTU>9600</MTU>\r
+ <!-- VLAN Tag used for C-Plane -->\r
+ <c_plane_vlan_tag>1</c_plane_vlan_tag>\r
+ <u_plane_vlan_tag>2</u_plane_vlan_tag>\r
+\r
+ <!-- Transmission Window Fast C-plane DL -->\r
+ <T1a_min_cp_dl>258</T1a_min_cp_dl>\r
+ <T1a_max_cp_dl>429</T1a_max_cp_dl>\r
+ <!-- Transmission Window Fast C-plane UL -->\r
+ <T1a_min_cp_ul>285</T1a_min_cp_ul>\r
+ <T1a_max_cp_ul>300</T1a_max_cp_ul>\r
+ <!-- Transmission Window U-plane -->\r
+ <T1a_min_up>96</T1a_min_up>\r
+ <T1a_max_up>196</T1a_max_up>\r
+ <!-- Reception Window U-Plane-->\r
+ <Ta4_min>0</Ta4_min>\r
+ <Ta4_max>75</Ta4_max>\r
+\r
+ <!-- Enable Control Plane -->\r
+ <EnableCp>1</EnableCp>\r
+\r
+ <DynamicSectionEna>0</DynamicSectionEna>\r
+ <!-- Enable Dynamic section allocation for UL -->\r
+ <DynamicSectionEnaUL>0</DynamicSectionEnaUL>\r
+ <xRANSFNWrap>1</xRANSFNWrap>\r
+ <!-- Total Number of DL PRBs per symbol (starting from RB 0) that is transmitted (used for testing. If 0, then value is used from PHY_CONFIG_API) -->\r
+ <xRANNumDLPRBs>0</xRANNumDLPRBs>\r
+ <!-- Total Number of UL PRBs per symbol (starting from RB 0) that is received (used for testing. If 0, then value is used from PHY_CONFIG_API) -->\r
+ <xRANNumULPRBs>0</xRANNumULPRBs>\r
+ <!-- refer to alpha as defined in section 9.7.2 of O-RAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns) -->\r
+ <Gps_Alpha>0</Gps_Alpha>\r
+ <!-- beta value as defined in section 9.7.2 of O-RAN spec. range -32767 ~ +32767 -->\r
+ <Gps_Beta>0</Gps_Beta>\r
+\r
+ <!-- XRAN: Compression mode on O-DU <-> O-RU 0 - no comp 1 - BFP -->\r
+ <xranCompMethod>1</xranCompMethod>\r
+\r
+ <oRu0nPrbElemDl>6</oRu0nPrbElemDl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu0PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemDl0>\r
+ <oRu0PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl1>\r
+ <oRu0PrbElemDl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemDl2>\r
+ <oRu0PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemDl3>\r
+ <oRu0PrbElemDl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemDl4>\r
+ <oRu0PrbElemDl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemDl5>\r
+ <oRu0PrbElemDl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemDl6>\r
+ <oRu0PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemDl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu0ExtBfwDl0>2,24,0,0,9,1</oRu0ExtBfwDl0>\r
+ <oRu0ExtBfwDl1>2,24,0,0,9,1</oRu0ExtBfwDl1>\r
+ <oRu0ExtBfwDl2>2,24,0,0,9,1</oRu0ExtBfwDl2>\r
+ <oRu0ExtBfwDl3>2,24,0,0,9,1</oRu0ExtBfwDl3>\r
+ <oRu0ExtBfwDl4>2,24,0,0,9,1</oRu0ExtBfwDl4>\r
+ <oRu0ExtBfwDl5>2,17,0,0,9,1</oRu0ExtBfwDl5>\r
+\r
+ <oRu0nPrbElemUl>6</oRu0nPrbElemUl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu0PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu0PrbElemUl0>\r
+ <oRu0PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl1>\r
+ <oRu0PrbElemUl2>96,48,0,14,2,1,1,9,1,0,0</oRu0PrbElemUl2>\r
+ <oRu0PrbElemUl3>144,48,0,14,4,1,1,9,1,0,0</oRu0PrbElemUl3>\r
+ <oRu0PrbElemUl4>192,48,0,14,5,1,1,9,1,0,0</oRu0PrbElemUl4>\r
+ <oRu0PrbElemUl5>240,33,0,14,6,1,1,9,1,0,0</oRu0PrbElemUl5>\r
+ <oRu0PrbElemUl6>240,33,0,14,7,1,1,9,1,0,0</oRu0PrbElemUl6>\r
+ <oRu0PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu0PrbElemUl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu0ExtBfwUl0>2,24,0,0,9,1</oRu0ExtBfwUl0>\r
+ <oRu0ExtBfwUl1>2,24,0,0,9,1</oRu0ExtBfwUl1>\r
+ <oRu0ExtBfwUl2>2,24,0,0,9,1</oRu0ExtBfwUl2>\r
+ <oRu0ExtBfwUl3>2,24,0,0,9,1</oRu0ExtBfwUl3>\r
+ <oRu0ExtBfwUl4>2,24,0,0,9,1</oRu0ExtBfwUl4>\r
+ <oRu0ExtBfwUl5>2,17,0,0,9,1</oRu0ExtBfwUl5>\r
+\r
+ <oRu0nPrbElemSrs>1</oRu0nPrbElemSrs>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu0PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu0PrbElemSrs0>\r
+\r
+ <oRu1nPrbElemDl>2</oRu1nPrbElemDl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu1PrbElemDl0>0,48,0,14,0,1,1,9,1,0,0</oRu1PrbElemDl0>\r
+ <oRu1PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemDl1>\r
+ <oRu1PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu1PrbElemDl2>\r
+ <oRu1PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu1PrbElemDl3>\r
+ <oRu1PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemDl4>\r
+ <oRu1PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemDl5>\r
+ <oRu1PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemDl6>\r
+ <oRu1PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemDl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu1ExtBfwDl0>2,24,0,0,9,1</oRu1ExtBfwDl0>\r
+ <oRu1ExtBfwDl1>2,24,0,0,9,1</oRu1ExtBfwDl1>\r
+\r
+ <oRu1nPrbElemUl>2</oRu1nPrbElemUl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu1PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu1PrbElemUl0>\r
+ <oRu1PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu1PrbElemUl1>\r
+ <oRu1PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu1PrbElemUl2>\r
+ <oRu1PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu1PrbElemUl3>\r
+ <oRu1PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu1PrbElemUl4>\r
+ <oRu1PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu1PrbElemUl5>\r
+ <oRu1PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu1PrbElemUl6>\r
+ <oRu1PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu1PrbElemUl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu1ExtBfwUl0>2,24,0,0,9,1</oRu1ExtBfwUl0>\r
+ <oRu1ExtBfwUl1>2,24,0,0,9,1</oRu1ExtBfwUl1>\r
+\r
+ <oRu1nPrbElemSrs>1</oRu1nPrbElemSrs>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu1PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu1PrbElemSrs0>\r
+\r
+ <oRu2nPrbElemDl>2</oRu2nPrbElemDl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu2PrbElemDl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemDl0>\r
+ <oRu2PrbElemDl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemDl1>\r
+ <oRu2PrbElemDl2>96,48,0,14,3,1,1,9,1,0,0</oRu2PrbElemDl2>\r
+ <oRu2PrbElemDl3>144,48,0,14,4,1,1,9,1,0,0</oRu2PrbElemDl3>\r
+ <oRu2PrbElemDl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemDl4>\r
+ <oRu2PrbElemDl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemDl5>\r
+ <oRu2PrbElemDl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemDl6>\r
+ <oRu2PrbElemDl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemDl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu2ExtBfwDl0>2,24,0,0,9,1</oRu2ExtBfwDl0>\r
+ <oRu2ExtBfwDl1>2,24,0,0,9,1</oRu2ExtBfwDl1>\r
+\r
+ <oRu2nPrbElemUl>2</oRu2nPrbElemUl>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu2PrbElemUl0>0,48,0,14,1,1,1,9,1,0,0</oRu2PrbElemUl0>\r
+ <oRu2PrbElemUl1>48,48,0,14,2,1,1,9,1,0,0</oRu2PrbElemUl1>\r
+ <oRu2PrbElemUl2>72,36,0,14,3,1,1,9,1,0,0</oRu2PrbElemUl2>\r
+ <oRu2PrbElemUl3>108,36,0,14,4,1,1,9,1,0,0</oRu2PrbElemUl3>\r
+ <oRu2PrbElemUl4>144,36,0,14,5,1,1,9,1,0,0</oRu2PrbElemUl4>\r
+ <oRu2PrbElemUl5>180,36,0,14,6,1,1,9,1,0,0</oRu2PrbElemUl5>\r
+ <oRu2PrbElemUl6>216,36,0,14,7,1,1,9,1,0,0</oRu2PrbElemUl6>\r
+ <oRu2PrbElemUl7>252,21,0,14,8,1,1,9,1,0,0</oRu2PrbElemUl7>\r
+\r
+ <!-- extType = 11 -->\r
+ <oRu2ExtBfwUl0>2,24,0,0,9,1</oRu2ExtBfwUl0>\r
+ <oRu2ExtBfwUl1>2,24,0,0,9,1</oRu2ExtBfwUl1>\r
+\r
+ <oRu2nPrbElemSrs>1</oRu2nPrbElemSrs>\r
+ <!--nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask -->\r
+ <!-- weight base beams -->\r
+ <oRu2PrbElemSrs0>0,273,0,14,1,1,1,9,1,0,0</oRu2PrbElemSrs0>\r
+\r
+ </XranConfig>\r
+\r
+\r
+4. Modify ./bin/nr5g/gnb/l1/dpdk.sh (change PCIe addresses from VFs). ::\r
+\r
+ ethDevice0=0000:51:01.0\r
+ ethDevice1=0000:51:01.1\r
+ ethDevice2=0000:51:01.2\r
+ ethDevice3=0000:51:01.3\r
+ ethDevice4=0000:51:01.4\r
+ ethDevice5=0000:51:01.5\r
+ ethDevice6=\r
+ ethDevice7=\r
+ ethDevice8=\r
+ ethDevice9=\r
+ ethDevice10=\r
+ ethDevice11=\r
+ fecDevice0=0000:92:00.0\r
+\r
+5. Use configuration of test mac per::\r
+\r
+ /bin/nr5g/gnb/testmac/icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r
+ phystart 4 0 100200\r
+ TEST_FD, 3370, 3, fd/mu1_100mhz/376/fd_testconfig_tst376.cfg,\r
+ fd/mu1_100mhz/377/fd_testconfig_tst377.cfg,\r
+ fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r
+\r
+6. To execute l1app with O-DU functionality according to O-RAN Fronthaul specification, enter::\r
+\r
+ [root@xran flexran] cd ./bin/nr5g/gnb/l1\r
+ ./l1.sh -xranmmimo\r
+ Radio mode with XRAN - Sub6 100Mhz Massive-MIMO (CatB)\r
+ DPDK WLS MODE\r
+ kernel.sched_rt_runtime_us = -1\r
+ kernel.shmmax = 2147483648\r
+ kernel.shmall = 2147483648\r
+ Note: Forwarding request to 'systemctl disable irqbalance.service'.\r
+ using configuration file phycfg_xran.xml\r
+ using configuration file xrancfg_sub6_mmimo.xml\r
+ >> Running... ./l1app table 0 1 --cfgfile=phycfg_xran.xml --xranfile=xrancfg_sub6_mmimo.xml\r
+ FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_llr_demapping version #DIRTY#\r
+ FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r
+ FlexRAN SDK bblib_reed_muller version #DIRTY#\r
+ FlexRAN SDK bblib_lte_modulation version #DIRTY#\r
+ FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r
+ FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fd_correlation version #DIRTY#\r
+ FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r
+ FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fft_ifft version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_lte_ldpc_decoder version #DIRTY#\r
+ FlexRAN SDK bblib_lte_ldpc_encoder version #DIRTY#\r
+ FlexRAN SDK bblib_lte_LDPC_ratematch version #DIRTY#\r
+ FlexRAN SDK bblib_lte_rate_dematching_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_common version #DIRTY#\r
+ FlexRAN SDK bblib_lte_crc version #DIRTY#\r
+ FlexRAN SDK bblib_lte_dft_idft version #DIRTY#\r
+ FlexRAN SDK bblib_irc_rnn_calculation_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_mmse_irc_mimo_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_srs_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_zf_matrix_gen version #DIRTY#\r
+ FlexRAN SDK bblib_beamforming_dl_expand version #DIRTY#\r
+ =========================\r
+ 5GNR PHY Application\r
+ =========================\r
+\r
+\r
+ --------------------------------------------------------\r
+ File[phycfg_xran.xml] Version: 20.08\r
+ --------------------------------------------------------\r
+ --version=20.08\r
+ --successiveNoApi=15\r
+ --wls_dev_name=wls0\r
+ --wlsMemorySize=0x3F600000\r
+ --dlIqLog=0\r
+ --ulIqLog=0\r
+ --iqLogDumpToFile=0\r
+ --phyMlog=1\r
+ --phyStats=1\r
+ --dpdkMemorySize=18432\r
+ --dpdkIovaMode=0\r
+ --dpdkBasebandFecMode=1\r
+ --dpdkBasebandDevice=0000:92:00.0\r
+ --radioEnable=4\r
+ --ferryBridgeMode=1\r
+ --ferryBridgeEthPort=1\r
+ --ferryBridgeSyncPorts=0\r
+ --ferryBridgeOptCableLoopback=0\r
+ --radioCfg0PCIeEthDev=0000:19:00.0\r
+ --radioCfg0DpdkRx=1\r
+ --radioCfg0DpdkTx=2\r
+ --radioCfg0TxAnt=2\r
+ --radioCfg0RxAnt=2\r
+ --radioCfg0RxAgc=0\r
+ --radioCfg0NumCell=1\r
+ --radioCfg0Cell0PhyId=0\r
+ --radioCfg0Cell1PhyId=1\r
+ --radioCfg0Cell2PhyId=2\r
+ --radioCfg0Cell3PhyId=3\r
+ --radioCfg0Cell4PhyId=4\r
+ --radioCfg0Cell5PhyId=5\r
+ --radioCfg0riuMac=11:22:33:44:55:66\r
+ --radioCfg1PCIeEthDev=0000:03:00.1\r
+ --radioCfg1DpdkRx=1\r
+ --radioCfg1DpdkTx=1\r
+ --radioCfg1TxAnt=4\r
+ --radioCfg1RxAnt=4\r
+ --radioCfg1RxAgc=0\r
+ --radioCfg1NumCell=1\r
+ --radioCfg1Cell0PhyId=2\r
+ --radioCfg1Cell1PhyId=3\r
+ --radioCfg1Cell2PhyId=2\r
+ --radioCfg1Cell3PhyId=3\r
+ --radioCfg1riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg2PCIeEthDev=0000:05:00.0\r
+ --radioCfg2DpdkRx=10\r
+ --radioCfg2DpdkTx=11\r
+ --radioCfg2TxAnt=4\r
+ --radioCfg2RxAnt=4\r
+ --radioCfg2RxAgc=0\r
+ --radioCfg2NumCell=2\r
+ --radioCfg2Cell0PhyId=4\r
+ --radioCfg2Cell1PhyId=5\r
+ --radioCfg2Cell2PhyId=2\r
+ --radioCfg2Cell3PhyId=3\r
+ --radioCfg2riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg3PCIeEthDev=0000:05:00.1\r
+ --radioCfg3DpdkRx=12\r
+ --radioCfg3DpdkTx=13\r
+ --radioCfg3TxAnt=4\r
+ --radioCfg3RxAnt=4\r
+ --radioCfg3RxAgc=0\r
+ --radioCfg3NumCell=2\r
+ --radioCfg3Cell0PhyId=6\r
+ --radioCfg3Cell1PhyId=7\r
+ --radioCfg3Cell2PhyId=2\r
+ --radioCfg3Cell3PhyId=3\r
+ --radioCfg3riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg4PCIeEthDev=0000:00:08.0\r
+ --radioCfg4DpdkRx=14\r
+ --radioCfg4DpdkTx=15\r
+ --radioCfg4TxAnt=4\r
+ --radioCfg4RxAnt=4\r
+ --radioCfg4RxAgc=0\r
+ --radioCfg4NumCell=2\r
+ --radioCfg4Cell0PhyId=8\r
+ --radioCfg4Cell1PhyId=9\r
+ --radioCfg4Cell2PhyId=2\r
+ --radioCfg4Cell3PhyId=3\r
+ --radioCfg4riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg5PCIeEthDev=0000:08:00.0\r
+ --radioCfg5DpdkRx=16\r
+ --radioCfg5DpdkTx=16\r
+ --radioCfg5TxAnt=4\r
+ --radioCfg5RxAnt=4\r
+ --radioCfg5RxAgc=0\r
+ --radioCfg5NumCell=2\r
+ --radioCfg5Cell0PhyId=10\r
+ --radioCfg5Cell1PhyId=11\r
+ --radioCfg5Cell2PhyId=2\r
+ --radioCfg5Cell3PhyId=3\r
+ --radioCfg5riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg6PCIeEthDev=0000:00:05.0\r
+ --radioCfg6DpdkRx=16\r
+ --radioCfg6DpdkTx=16\r
+ --radioCfg6TxAnt=4\r
+ --radioCfg6RxAnt=4\r
+ --radioCfg1RxAgc=0\r
+ --radioCfg6NumCell=2\r
+ --radioCfg6Cell0PhyId=12\r
+ --radioCfg6Cell1PhyId=13\r
+ --radioCfg6Cell2PhyId=2\r
+ --radioCfg6Cell3PhyId=3\r
+ --radioCfg6riuMac=ac:1f:6b:2c:9f:07\r
+ --radioCfg7PCIeEthDev=0000:00:06.0\r
+ --radioCfg7DpdkRx=16\r
+ --radioCfg7DpdkTx=16\r
+ --radioCfg7TxAnt=4\r
+ --radioCfg7RxAnt=4\r
+ --radioCfg7RxAgc=0\r
+ --radioCfg7NumCell=2\r
+ --radioCfg7Cell0PhyId=14\r
+ --radioCfg7Cell1PhyId=15\r
+ --radioCfg7Cell2PhyId=2\r
+ --radioCfg7Cell3PhyId=3\r
+ --radioCfg7riuMac=ac:1f:6b:2c:9f:07\r
+ --radioPort0=0\r
+ --radioPort1=1\r
+ --radioPort2=2\r
+ --radioPort3=3\r
+ --radioPort4=4\r
+ --radioPort5=5\r
+ --radioPort6=6\r
+ --radioPort7=7\r
+ --PdschSymbolSplit=0\r
+ --PdschDlWeightSplit=0\r
+ --FecEncSplit=4\r
+ --PuschChanEstSplit=0\r
+ --PuschMmseSplit=0\r
+ --PuschLlrRxSplit=0\r
+ --PuschUlWeightSplit=0\r
+ --FecDecEarlyTermDisable=0\r
+ --FecDecNumIter=12\r
+ --FecDecSplit=4\r
+ --llrOutDecimalDigit=2\r
+ --IrcEnableThreshold=-10\r
+ --PuschNoiseScale=2\r
+ --CEInterpMethod=0\r
+ --PucchSplit=0\r
+ --SrsCeSplit=0\r
+ --prachDetectThreshold=0\r
+ --MlogSubframes=128\r
+ --MlogCores=40\r
+ --MlogSize=10000\r
+ --systemThread=2, 0, 0\r
+ --timerThread=0, 96, 0\r
+ --FpgaDriverCpuInfo=3, 96, 0\r
+ --FrontHaulCpuInfo=3, 96, 0\r
+ --radioDpdkMaster=2, 99, 0\r
+ --BbuPoolSleepEnable=1\r
+ --BbuPoolThreadCorePriority=94\r
+ --BbuPoolThreadCorePolicy=0\r
+ --BbuPoolThreadDefault_0_63=0xF0\r
+ --BbuPoolThreadDefault_64_127=0x0\r
+ --BbuPoolThreadSrs_0_63=0x0\r
+ --BbuPoolThreadSrs_64_127=0x0\r
+ --BbuPoolThreadDlbeam_0_63=0x0\r
+ --BbuPoolThreadDlbeam_64_127=0x0\r
+ --BbuPoolThreadUrllc=0x100\r
+ --FrontHaulTimeAdvance=7450\r
+ --nEthPorts=462607\r
+ --nPhaseCompFlag=0\r
+ --nFecFpgaVersionMu3=0x20010900\r
+ --nFecFpgaVersionMu0_1=0x0423D420\r
+ --nFhFpgaVersionMu3=0x8001000F\r
+ --nFhFpgaVersionMu0_1=0x90010008\r
+ --StreamStats=0\r
+ --StreamIp=10.255.83.5\r
+ --StreamPort=4010\r
+\r
+ wls_dev_filename: wls0\r
+ phycfg_apply: Initialize Radio Interface with XRAN library\r
+ Setting FecEncSplit to 1 to run on HW accelerator\r
+ Setting FecDecSplit to 1 to run on HW accelerator\r
+\r
+\r
+\r
+ --------------------------------------------------------\r
+ File[xrancfg_sub6_mmimo.xml] Version: 20.08\r
+ --------------------------------------------------------\r
+ --version=20.08\r
+ --oRuNum=3\r
+ --oRuEthLinkSpeed=25\r
+ --oRuLinesNumber=2\r
+ --oRuCUon1Vf=1\r
+ --PciBusAddoRu0Vf0=0000:51:01.0\r
+ --PciBusAddoRu0Vf1=0000:51:01.1\r
+ --PciBusAddoRu0Vf2=0000:51:01.2\r
+ --PciBusAddoRu0Vf3=0000:51:01.3\r
+ --PciBusAddoRu1Vf0=0000:51:01.2\r
+ --PciBusAddoRu1Vf1=0000:51:01.3\r
+ --PciBusAddoRu1Vf2=0000:51:01.6\r
+ --PciBusAddoRu1Vf3=0000:51:01.7\r
+ --PciBusAddoRu2Vf0=0000:51:01.4\r
+ --PciBusAddoRu2Vf1=0000:51:01.5\r
+ --PciBusAddoRu2Vf2=0000:51:02.2\r
+ --PciBusAddoRu2Vf3=0000:51:02.3\r
+ --PciBusAddoRu3Vf0=0000:00:00.0\r
+ --PciBusAddoRu3Vf1=0000:00:00.0\r
+ --PciBusAddoRu3Vf2=0000:00:00.0\r
+ --PciBusAddoRu3Vf3=0000:00:00.0\r
+ --oRuRem0Mac0=00:11:22:33:00:01\r
+ --oRuRem0Mac1=00:11:22:33:00:11\r
+ --oRuRem0Mac2=00:11:22:33:00:21\r
+ --oRuRem0Mac3=00:11:22:33:00:31\r
+ --oRuRem1Mac0=00:11:22:33:01:01\r
+ --oRuRem1Mac1=00:11:22:33:01:11\r
+ --oRuRem1Mac2=00:11:22:33:01:21\r
+ --oRuRem1Mac3=00:11:22:33:01:31\r
+ --oRuRem2Mac0=00:11:22:33:02:01\r
+ --oRuRem2Mac1=00:11:22:33:02:11\r
+ --oRuRem2Mac2=00:11:22:33:02:21\r
+ --oRuRem2Mac3=00:11:22:33:02:31\r
+ --oRuRem3Mac0=00:11:22:33:03:01\r
+ --oRuRem3Mac1=00:11:22:33:03:11\r
+ --oRuRem3Mac2=00:11:22:33:03:21\r
+ --oRuRem3Mac3=00:11:22:33:03:31\r
+ --oRu0NumCc=1\r
+ --oRu0Cc0PhyId=0\r
+ --oRu0Cc1PhyId=1\r
+ --oRu0Cc2PhyId=2\r
+ --oRu0Cc3PhyId=3\r
+ --oRu1NumCc=1\r
+ --oRu1Cc0PhyId=1\r
+ --oRu1Cc1PhyId=1\r
+ --oRu1Cc2PhyId=2\r
+ --oRu1Cc3PhyId=3\r
+ --oRu2NumCc=1\r
+ --oRu2Cc0PhyId=2\r
+ --oRu2Cc1PhyId=1\r
+ --oRu2Cc2PhyId=2\r
+ --oRu2Cc3PhyId=3\r
+ --xRANThread=22, 96, 0\r
+ --xRANWorker=0x3800000, 96, 0\r
+ --Category=1\r
+ --xranPmdSleep=0\r
+ --Tadv_cp_dl=25\r
+ --T2a_min_cp_dl=285\r
+ --T2a_max_cp_dl=429\r
+ --T2a_min_cp_ul=285\r
+ --T2a_max_cp_ul=429\r
+ --T2a_min_up=71\r
+ --T2a_max_up=428\r
+ --Ta3_min=20\r
+ --Ta3_max=32\r
+ --MTU=9600\r
+ --c_plane_vlan_tag=1\r
+ --u_plane_vlan_tag=2\r
+ --T1a_min_cp_dl=258\r
+ --T1a_max_cp_dl=429\r
+ --T1a_min_cp_ul=285\r
+ --T1a_max_cp_ul=300\r
+ --T1a_min_up=96\r
+ --T1a_max_up=196\r
+ --Ta4_min=0\r
+ --Ta4_max=75\r
+ --EnableCp=1\r
+ --DynamicSectionEna=0\r
+ --DynamicSectionEnaUL=0\r
+ --xRANSFNWrap=1\r
+ --xRANNumDLPRBs=0\r
+ --xRANNumULPRBs=0\r
+ --Gps_Alpha=0\r
+ --Gps_Beta=0\r
+ --xranCompMethod=1\r
+ --oRu0nPrbElemDl=6\r
+ --oRu0PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0\r
+ --oRu0PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu0PrbElemDl2=96,48,0,14,2,1,1,9,1,0,0\r
+ --oRu0PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r
+ --oRu0PrbElemDl4=192,48,0,14,5,1,1,9,1,0,0\r
+ --oRu0PrbElemDl5=240,33,0,14,6,1,1,9,1,0,0\r
+ --oRu0PrbElemDl6=240,33,0,14,7,1,1,9,1,0,0\r
+ --oRu0PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu0ExtBfwDl0=2,24,0,0,9,1\r
+ --oRu0ExtBfwDl1=2,24,0,0,9,1\r
+ --oRu0ExtBfwDl2=2,24,0,0,9,1\r
+ --oRu0ExtBfwDl3=2,24,0,0,9,1\r
+ --oRu0ExtBfwDl4=2,24,0,0,9,1\r
+ --oRu0ExtBfwDl5=2,17,0,0,9,1\r
+ --oRu0nPrbElemUl=6\r
+ --oRu0PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r
+ --oRu0PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu0PrbElemUl2=96,48,0,14,2,1,1,9,1,0,0\r
+ --oRu0PrbElemUl3=144,48,0,14,4,1,1,9,1,0,0\r
+ --oRu0PrbElemUl4=192,48,0,14,5,1,1,9,1,0,0\r
+ --oRu0PrbElemUl5=240,33,0,14,6,1,1,9,1,0,0\r
+ --oRu0PrbElemUl6=240,33,0,14,7,1,1,9,1,0,0\r
+ --oRu0PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu0ExtBfwUl0=2,24,0,0,9,1\r
+ --oRu0ExtBfwUl1=2,24,0,0,9,1\r
+ --oRu0ExtBfwUl2=2,24,0,0,9,1\r
+ --oRu0ExtBfwUl3=2,24,0,0,9,1\r
+ --oRu0ExtBfwUl4=2,24,0,0,9,1\r
+ --oRu0ExtBfwUl5=2,17,0,0,9,1\r
+ --oRu0nPrbElemSrs=1\r
+ --oRu0PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r
+ --oRu1nPrbElemDl=2\r
+ --oRu1PrbElemDl0=0,48,0,14,0,1,1,9,1,0,0\r
+ --oRu1PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu1PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0\r
+ --oRu1PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r
+ --oRu1PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0\r
+ --oRu1PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0\r
+ --oRu1PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0\r
+ --oRu1PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu1ExtBfwDl0=2,24,0,0,9,1\r
+ --oRu1ExtBfwDl1=2,24,0,0,9,1\r
+ --oRu1nPrbElemUl=2\r
+ --oRu1PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r
+ --oRu1PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu1PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0\r
+ --oRu1PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0\r
+ --oRu1PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0\r
+ --oRu1PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0\r
+ --oRu1PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0\r
+ --oRu1PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu1ExtBfwUl0=2,24,0,0,9,1\r
+ --oRu1ExtBfwUl1=2,24,0,0,9,1\r
+ --oRu1nPrbElemSrs=1\r
+ --oRu1PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r
+ --oRu2nPrbElemDl=2\r
+ --oRu2PrbElemDl0=0,48,0,14,1,1,1,9,1,0,0\r
+ --oRu2PrbElemDl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu2PrbElemDl2=96,48,0,14,3,1,1,9,1,0,0\r
+ --oRu2PrbElemDl3=144,48,0,14,4,1,1,9,1,0,0\r
+ --oRu2PrbElemDl4=144,36,0,14,5,1,1,9,1,0,0\r
+ --oRu2PrbElemDl5=180,36,0,14,6,1,1,9,1,0,0\r
+ --oRu2PrbElemDl6=216,36,0,14,7,1,1,9,1,0,0\r
+ --oRu2PrbElemDl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu2ExtBfwDl0=2,24,0,0,9,1\r
+ --oRu2ExtBfwDl1=2,24,0,0,9,1\r
+ --oRu2nPrbElemUl=2\r
+ --oRu2PrbElemUl0=0,48,0,14,1,1,1,9,1,0,0\r
+ --oRu2PrbElemUl1=48,48,0,14,2,1,1,9,1,0,0\r
+ --oRu2PrbElemUl2=72,36,0,14,3,1,1,9,1,0,0\r
+ --oRu2PrbElemUl3=108,36,0,14,4,1,1,9,1,0,0\r
+ --oRu2PrbElemUl4=144,36,0,14,5,1,1,9,1,0,0\r
+ --oRu2PrbElemUl5=180,36,0,14,6,1,1,9,1,0,0\r
+ --oRu2PrbElemUl6=216,36,0,14,7,1,1,9,1,0,0\r
+ --oRu2PrbElemUl7=252,21,0,14,8,1,1,9,1,0,0\r
+ --oRu2ExtBfwUl0=2,24,0,0,9,1\r
+ --oRu2ExtBfwUl1=2,24,0,0,9,1\r
+ --oRu2nPrbElemSrs=1\r
+ --oRu2PrbElemSrs0=0,273,0,14,1,1,1,9,1,0,0\r
+\r
+\r
+ timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496526035 [Hz]\r
+ Ticks per usec 1496\r
+ MLogOpen: filename(l1mlog.bin) mlogSubframes (128), mlogCores(40), mlogSize(10000) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(40), mlogSize(10000)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1496525824 [Hz]\r
+ Ticks per us 1496\r
+ MLog Storage: 0x7f7403835100 -> 0x7f740690b830 [ 51210032 bytes ]\r
+ localMLogFreqReg: 1496. Storing: 1496\r
+ Mlog Open successful\r
+\r
+ gnb_io_xran_init\r
+ num_o_ru 3 EthLinesNumber 2 where VFs 1 per EthLine\r
+ VF[0] 0000:51:01.0 [C+U Plane]\r
+ VF[1] 0000:51:01.1 [C+U Plane]\r
+ VF[2] 0000:51:01.2 [C+U Plane]\r
+ VF[3] 0000:51:01.3 [C+U Plane]\r
+ VF[4] 0000:51:01.4 [C+U Plane]\r
+ VF[5] 0000:51:01.5 [C+U Plane]\r
+ oRu0nPrbElemDl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemDl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemDl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemDl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemDl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemDl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl0: oRu0: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl1: oRu0: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl2: oRu0: nRBStart 96,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):2 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl3: oRu0: nRBStart 144,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 4, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):3 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl4: oRu0: nRBStart 192,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 5, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):4 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemUl5: oRu0: nRBStart 240,nRBSize 33,nStartSymb 0,numSymb 14,nBeamIndex 6, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,17,0,0,9,1):5 numBundPrb 2, numSetBFW 17, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu0nPrbElemSrs0: oRu0: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ oRu1nPrbElemDl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 0, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu1nPrbElemDl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu1nPrbElemUl0: oRu1: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu1nPrbElemUl1: oRu1: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu1nPrbElemSrs0: oRu1: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ oRu2nPrbElemDl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu2nPrbElemDl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu2nPrbElemUl0: oRu2: nRBStart 0,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):0 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu2nPrbElemUl1: oRu2: nRBStart 48,nRBSize 48,nStartSymb 0,numSymb 14,nBeamIndex 2, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ (2,24,0,0,9,1):1 numBundPrb 2, numSetBFW 24, RAD 0, disableBFW 0, bfwIqWidth 9, bfwCompMeth 1\r
+ oRu2nPrbElemSrs0: oRu2: nRBStart 0,nRBSize 273,nStartSymb 0,numSymb 14,nBeamIndex 1, bf_weight_update 1 compMethod 1, iqWidth 9 BeamFormingType 1 scaler 0 remask 0x0\r
+ gnb_io_xran_cfg_setup successful\r
+ xran_init: MTU 9600\r
+ xran_init: MTU 9600\r
+ xran_init: MTU 9600\r
+ PF Eth line speed 25G\r
+ PF Eth lines per O-xU port 2\r
+ BBDEV_FEC_ACCL_NR5G\r
+ hw-accelerated bbdev 0000:92:00.0\r
+ total cores 48 c_mask 0x3c00004 core 22 [id] system_core 2 [id] pkt_proc_core 0x3800000 [mask] pkt_aux_core 0 [id] timing_core 22 [id]\r
+ xran_ethdi_init_dpdk_io: Calling rte_eal_init:wls0 -c 0x3c00004 -n2 --iova-mode=pa --socket-mem=18432 --socket-limit=18432 --proc-type=auto --file-prefix wls0 -w 0000:00:00.0 -w 0000:92:00.0\r
+ EAL: Detected 48 lcore(s)\r
+ EAL: Detected 1 NUMA nodes\r
+ EAL: Auto-detected process type: PRIMARY\r
+ EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket\r
+ EAL: Selected IOVA mode 'PA'\r
+ EAL: No available hugepages reported in hugepages-2048kB\r
+ EAL: Probing VFIO support...\r
+ EAL: PCI device 0000:92:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:d8f intel_fpga_5gnr_fec_pf\r
+ xran_init_mbuf_pool: socket 0\r
+ EAL: PCI device 0000:51:01.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 0 for TX, drv=net_iavf\r
+ Port 0 MAC: 00 11 22 33 00 00\r
+ Port 0: nb_rxd 4096 nb_txd 4096\r
+ [0] mempool_rx__0\r
+ [0] mempool_small__0\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [0] ... done\r
+ Port 0 Link Up - speed 100000 Mbps - full-duplex\r
+ EAL: PCI device 0000:51:01.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 1 for TX, drv=net_iavf\r
+ Port 1 MAC: 00 11 22 33 00 10\r
+ Port 1: nb_rxd 4096 nb_txd 4096\r
+ [1] mempool_rx__1\r
+ [1] mempool_small__1\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [1] ... done\r
+ Port 1 Link Up - speed 100000 Mbps - full-duplex\r
+ EAL: PCI device 0000:51:01.2 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 2 for TX, drv=net_iavf\r
+ Port 2 MAC: 00 11 22 33 01 00\r
+ Port 2: nb_rxd 4096 nb_txd 4096\r
+ [2] mempool_rx__2\r
+ [2] mempool_small__2\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [2] ... done\r
+ Port 2 Link Up - speed 100000 Mbps - full-duplex\r
+ EAL: PCI device 0000:51:01.3 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 3 for TX, drv=net_iavf\r
+ Port 3 MAC: 00 11 22 33 01 10\r
+ Port 3: nb_rxd 4096 nb_txd 4096\r
+ [3] mempool_rx__3\r
+ [3] mempool_small__3\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [3] ... done\r
+ Port 3 Link Up - speed 100000 Mbps - full-duplex\r
+ EAL: PCI device 0000:51:01.4 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 4 for TX, drv=net_iavf\r
+ Port 4 MAC: 00 11 22 33 02 00\r
+ Port 4: nb_rxd 4096 nb_txd 4096\r
+ [4] mempool_rx__4\r
+ [4] mempool_small__4\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [4] ... done\r
+ Port 4 Link Up - speed 100000 Mbps - full-duplex\r
+ EAL: PCI device 0000:51:01.5 on NUMA socket 0\r
+ EAL: probe driver: 8086:1889 net_iavf\r
+ initializing port 5 for TX, drv=net_iavf\r
+ Port 5 MAC: 00 11 22 33 02 10\r
+ Port 5: nb_rxd 4096 nb_txd 4096\r
+ [5] mempool_rx__5\r
+ [5] mempool_small__5\r
+ iavf_init_rss(): RSS is enabled by PF by default\r
+\r
+ Checking link status portid [5] ... done\r
+ Port 5 Link Up - speed 100000 Mbps - full-duplex\r
+ [ 0] vf 0 local SRC MAC: 00 11 22 33 00 00\r
+ [ 0] vf 0 remote DST MAC: 00 11 22 33 00 01\r
+ [ 0] vf 1 local SRC MAC: 00 11 22 33 00 10\r
+ [ 0] vf 1 remote DST MAC: 00 11 22 33 00 11\r
+ [ 1] vf 2 local SRC MAC: 00 11 22 33 01 00\r
+ [ 1] vf 2 remote DST MAC: 00 11 22 33 01 01\r
+ [ 1] vf 3 local SRC MAC: 00 11 22 33 01 10\r
+ [ 1] vf 3 remote DST MAC: 00 11 22 33 01 11\r
+ [ 2] vf 4 local SRC MAC: 00 11 22 33 02 00\r
+ [ 2] vf 4 remote DST MAC: 00 11 22 33 02 01\r
+ [ 2] vf 5 local SRC MAC: 00 11 22 33 02 10\r
+ [ 2] vf 5 remote DST MAC: 00 11 22 33 02 11\r
+ created dl_gen_ring_up_0\r
+ created dl_gen_ring_up_1\r
+ created dl_gen_ring_up_2\r
+ xran_init successful, pHandle = 0x7f7393b23040\r
+\r
+\r
+ bbdev_init:\r
+ Socket ID: 0\r
+ FEC is accelerated through BBDEV: 0000:92:00.0\r
+ wls_layer_init[wls0] nWlsMemorySize[1063256064]\r
+ wls_lib: Open wls0 (DPDK memzone)\r
+ wls_lib: WLS_Open 0x43f600000\r
+ wls_lib: link: 0 <-> 1\r
+ wls_lib: Mode 0\r
+ wls_lib: WLS shared management memzone: wls0\r
+ wls_lib: hugePageSize on the system is 1073741824\r
+ wls_lib: WLS_Alloc [1063256064] bytes\r
+\r
+\r
+ ===========================================================================================================\r
+ PHY VERSION\r
+ ===========================================================================================================\r
+ Version: #DIRTY#\r
+ IMG-date: Aug 5 2020\r
+ IMG-time: 18:31:18\r
+ ===========================================================================================================\r
+ DEPENDENCIES VERSIONS\r
+ ===========================================================================================================\r
+ FlexRAN BBU pooling version #DIRTY#\r
+ FlexRAN SDK bblib_layerdemapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_layermapping_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_cestimate_5gnr_version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_cestimate_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_llr_demapping version #DIRTY#\r
+ FlexRAN SDK bblib_pdcch_remapping_5gnr_version version #DIRTY#\r
+ FlexRAN SDK bblib_reed_muller version #DIRTY#\r
+ FlexRAN SDK bblib_lte_modulation version #DIRTY#\r
+ FlexRAN SDK bblib_polar_decoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_polar_rate_dematching_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_PhaseNoise_5G version #DIRTY#\r
+ FlexRAN SDK bblib_mimo_mmse_detection_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fd_correlation version #DIRTY#\r
+ FlexRAN SDK bblib_scramble_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_equ_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_ta_compensation_version_5gnr #DIRTY#\r
+ FlexRAN SDK bblib_polar_encoder_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_prach_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_fft_ifft version #DIRTY#\r
+ FlexRAN SDK bblib_pucch_5gnr version #DIRTY#\r
+ FlexRAN SDK bblib_lte_crc version #DIRTY#\r
+ FlexRAN SDK bblib_common version #DIRTY#\r
+ ===========================================================================================================\r
+\r
+ ===========================================================================================================\r
+ Non BBU threads in application\r
+ ===========================================================================================================\r
+ nr5g_gnb_phy2mac_api_proc_stats_thread: [PID: 29438] binding on [CPU 2] [PRIO: 0] [POLICY: 1]\r
+ wls_rx_handler (non-rt): [PID: 29445] binding on [CPU 2]\r
+ ===========================================================================================================\r
+\r
+ PHY>welcome to application console\r
+\r
+\r
+ PHY>\r
+ PHY>\r
+ PHY>Received MSG_TYPE_PHY_ADD_REMOVE_CORE\r
+ Processing MSG_TYPE_PHY_ADD_REMOVE_CORE\r
+ phy_bbupool_set_core[0] (add): 137170526192 [0x0000001ff0001ff0] Current: 0 [0x0000000000000000]\r
+ nr5g_gnb_mac2phy_api_set_options: PDSCH_SPLIT[4] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: PDSCH_DL_WEIGHT_SPLIT[4] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: PUSCH_CHANEST_SPLIT[2] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: PUSCH_MMSE_SPLIT[4] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: PUSCH_LLR_RX_SPLIT[2] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: PUSCH_UL_WEIGHT_SPLIT[2] nCellMask[0x00000001]\r
+ nr5g_gnb_mac2phy_api_set_options: FEC_DEC_NUM_ITER[3] nCellMask[0x00ffffff]\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES\r
+ Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 0\r
+ phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[0] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/376/uliq00_tst376.bin] filename_in_prach_iq[]\r
+ Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 1\r
+ phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[1] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[]\r
+ Processing MSG_TYPE_PHY_UL_IQ_SAMPLES: 2\r
+ phydi_read_write_iq_samples: direction[1] nNumerologyMult[2] fftSize[4096, 45864, SRS: 3276] numSubframe[20] numAntenna[64] numPorts[8] nIsRadioMode[1] carrNum[2] TimerModeFreqDomain[1] PhaseCompensationEnable[0] filename_in_ul_iq[/home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/mu1_100mhz/377/uliq00_tst377.bin] filename_in_prach_iq[]\r
+ Received MSG_TYPE_PHY_CONFIG_REQ: 0\r
+ Received MSG_TYPE_PHY_CONFIG_REQ: 1\r
+ Received MSG_TYPE_PHY_CONFIG_REQ: 2\r
+ Processing MSG_TYPE_PHY_CONFIG_REQ: 0\r
+ phy_bbupool_init: Changing Core Mask0 [0xf0] to [0x1ff0001ff0]\r
+ phy_bbupool_set_config: Using cores: 0x0000001ff0001ff0 for BBU Pool nBbuPoolSleepEnable: 1\r
+ BBU Pooling: queueId = 0, the according nCoreNum = 18, the according cpuSetMask = 0x1ff0001ff0\r
+ BBU Pooling: gCoreIdxMap[0] = 4 is available!\r
+ BBU Pooling: gCoreIdxMap[1] = 5 is available!\r
+ BBU Pooling: gCoreIdxMap[2] = 6 is available!\r
+ BBU Pooling: gCoreIdxMap[3] = 7 is available!\r
+ BBU Pooling: gCoreIdxMap[4] = 8 is available!\r
+ BBU Pooling: gCoreIdxMap[5] = 9 is available!\r
+ BBU Pooling: gCoreIdxMap[6] = 10 is available!\r
+ BBU Pooling: gCoreIdxMap[7] = 11 is available!\r
+ BBU Pooling: gCoreIdxMap[8] = 12 is available!\r
+ BBU Pooling: gCoreIdxMap[9] = 28 is available!\r
+ BBU Pooling: gCoreIdxMap[10] = 29 is available!\r
+ BBU Pooling: gCoreIdxMap[11] = 30 is available!\r
+ BBU Pooling: gCoreIdxMap[12] = 31 is available!\r
+ BBU Pooling: gCoreIdxMap[13] = 32 is available!\r
+ BBU Pooling: gCoreIdxMap[14] = 33 is available!\r
+ BBU Pooling: gCoreIdxMap[15] = 34 is available!\r
+ BBU Pooling: gCoreIdxMap[16] = 35 is available!\r
+ BBU Pooling: gCoreIdxMap[17] = 36 is available!\r
+ phy_bbupool_init: Changing SrsCore Mask0 [(nil)] to [0x10000010]\r
+ phy_bbupool_init: Changing DlbeamCore Mask0 [(nil)] to [0x7e0]\r
+ Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoSrsCoresMask[0x10000010] nTotalSrsCores[2]\r
+ Setting aside core[4] for SRS\r
+ Setting aside core[28] for SRS\r
+ Massive Mimo Config: nCarrierAggregationLevel[3], nMassiveMimoDlbeamCoresMask[0x7e0] nTotalDlbeamCores[6]\r
+ Setting aside core[5] for DL beam\r
+ Setting aside core[6] for DL beam\r
+ Setting aside core[7] for DL beam\r
+ Setting aside core[8] for DL beam\r
+ Setting aside core[9] for DL beam\r
+ Setting aside core[10] for DL beam\r
+ BBU Pooling: taskId = 0 taskName = DL_L1_CONFIG is registered\r
+ BBU Pooling: taskId = 1 taskName = DL_L1_PDSCH_TB is registered\r
+ BBU Pooling: taskId = 2 taskName = DL_L1_PDSCH_SCRAMBLER is registered\r
+ BBU Pooling: taskId = 3 taskName = DL_L1_PDSCH_SYMBOL_TX is registered\r
+ BBU Pooling: taskId = 4 taskName = DL_L1_PDSCH_RS_GEN is registered\r
+ BBU Pooling: taskId = 5 taskName = DL_L1_CONTROL_CHANNELS is registered\r
+ BBU Pooling: taskId = 6 taskName = UL_L1_CONFIG is registered\r
+ BBU Pooling: taskId = 7 taskName = UL_L1_PUSCH_CE0 is registered\r
+ BBU Pooling: taskId = 8 taskName = UL_L1_PUSCH_CE7 is registered\r
+ BBU Pooling: taskId = 9 taskName = UL_L1_PUSCH_MMSE0_PRE is registered\r
+ BBU Pooling: taskId = 10 taskName = UL_L1_PUSCH_MMSE7_PRE is registered\r
+ BBU Pooling: taskId = 11 taskName = UL_L1_PUSCH_MMSE0 is registered\r
+ BBU Pooling: taskId = 12 taskName = UL_L1_PUSCH_MMSE7 is registered\r
+ BBU Pooling: taskId = 13 taskName = UL_L1_PUSCH_LLR is registered\r
+ BBU Pooling: taskId = 14 taskName = UL_L1_PUSCH_DECODE is registered\r
+ BBU Pooling: taskId = 15 taskName = UL_L1_PUSCH_TB is registered\r
+ BBU Pooling: taskId = 16 taskName = UL_L1_PUCCH is registered\r
+ BBU Pooling: taskId = 17 taskName = UL_L1_PRACH is registered\r
+ BBU Pooling: taskId = 18 taskName = UL_L1_SRS is registered\r
+ BBU Pooling: taskId = 19 taskName = DL_L1_POST is registered\r
+ BBU Pooling: taskId = 20 taskName = UL_L1_POST is registered\r
+ BBU Pooling: taskId = 21 taskName = DL_L1_BEAM_WEIGHT_GEN is registered\r
+ BBU Pooling: taskId = 22 taskName = DL_L1_BEAM_WEIGHT_TX is registered\r
+ BBU Pooling: taskId = 23 taskName = UL_L1_BEAM_WEIGHT_GEN is registered\r
+ BBU Pooling: taskId = 24 taskName = UL_L1_BEAM_WEIGHT_TX is registered\r
+ BBU Pooling: taskId = 25 taskName = UL_L1_SRS_CE is registered\r
+ BBU Pooling: taskId = 26 taskName = UL_L1_SRS_REPORT is registered\r
+ BBU Pooling: taskId = 27 taskName = UL_L1_PUSCH_CE0_PRE is registered\r
+ BBU Pooling: taskId = 28 taskName = UL_L1_PUSCH_CE7_PRE is registered\r
+ BBU Pooling: next taskList of DL_L1_CONFIG: DL_L1_PDSCH_TB DL_L1_PDSCH_RS_GEN DL_L1_CONTROL_CHANNELS\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_TB: N/A\r
+\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_SCRAMBLER: DL_L1_PDSCH_SYMBOL_TX\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_SYMBOL_TX: DL_L1_POST\r
+ BBU Pooling: next taskList of DL_L1_PDSCH_RS_GEN: DL_L1_PDSCH_SYMBOL_TX\r
+ BBU Pooling: next taskList of DL_L1_CONTROL_CHANNELS: DL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_CONFIG: UL_L1_POST UL_L1_BEAM_WEIGHT_GEN\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE0: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE7: UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0_PRE: UL_L1_PUSCH_MMSE0 UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7_PRE: UL_L1_PUSCH_MMSE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE0: UL_L1_PUSCH_LLR\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_MMSE7: UL_L1_PUSCH_LLR\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_LLR: UL_L1_PUSCH_DECODE\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_DECODE: N/A\r
+\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_TB: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_PUCCH: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_PRACH: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_SRS: UL_L1_SRS_CE\r
+ BBU Pooling: next taskList of DL_L1_POST: N/A\r
+\r
+ BBU Pooling: next taskList of UL_L1_POST: N/A\r
+\r
+ BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_GEN: DL_L1_BEAM_WEIGHT_TX\r
+ BBU Pooling: next taskList of DL_L1_BEAM_WEIGHT_TX: DL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_GEN: UL_L1_BEAM_WEIGHT_TX\r
+ BBU Pooling: next taskList of UL_L1_BEAM_WEIGHT_TX: UL_L1_POST\r
+ BBU Pooling: next taskList of UL_L1_SRS_CE: UL_L1_SRS_REPORT\r
+ BBU Pooling: next taskList of UL_L1_SRS_REPORT: N/A\r
+\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE0_PRE: UL_L1_PUSCH_CE0 UL_L1_PUSCH_CE7\r
+ BBU Pooling: next taskList of UL_L1_PUSCH_CE7_PRE: UL_L1_PUSCH_CE7\r
+ enter RtThread Launch\r
+ Allocated gpThreadWorker[coreIdx: 0][CoreNum: 4]: [0x7f738c000b70]\r
+ Allocated gpThreadWorker[coreIdx: 1][CoreNum: 5]: [0x7f738c000e20]\r
+ Allocated gpThreadWorker[coreIdx: 2][CoreNum: 6]: [0x7f738c0010d0]\r
+ Allocated gpThreadWorker[coreIdx: 3][CoreNum: 7]: [0x7f738c001380]\r
+ Allocated gpThreadWorker[coreIdx: 4][CoreNum: 8]: [0x7f738c001630]\r
+ Allocated gpThreadWorker[coreIdx: 5][CoreNum: 9]: [0x7f738c0018e0]\r
+ launching Thread 1 Queue 0 uCoreIdx 1 CoreId 5 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 0 Queue 0 uCoreIdx 0 CoreId 4 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 2 Queue 0 uCoreIdx 2 CoreId 6 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 3 Queue 0 uCoreIdx 3 CoreId 7 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 6][CoreNum: 10]: [0x7f738c001b90]\r
+ launching Thread 4 Queue 0 uCoreIdx 4 CoreId 8 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 5 Queue 0 uCoreIdx 5 CoreId 9 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 7][CoreNum: 11]: [0x7f738c001e40]\r
+ Allocated gpThreadWorker[coreIdx: 8][CoreNum: 12]: [0x7f738c0020f0]\r
+ bbupool_core_main: the server's coreNum = 48, the nCore = 18,nRtCoreMask = 0x1ff0001ff0, the nFeIfCore = 0,nFeIfCoreMask = 0x0\r
+ bbupool_core_main pthread_setaffinity_np succeed: coreId = 2, result = 0\r
+ Allocated gpThreadWorker[coreIdx: 9][CoreNum: 28]: [0x7f738c0023a0]\r
+ launching Thread 6 Queue 0 uCoreIdx 6 CoreId 10 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 10][CoreNum: 29]: [0x7f738c002650]\r
+ launching Thread 7 Queue 0 uCoreIdx 7 CoreId 11 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 11][CoreNum: 30]: [0x7f738c002900]\r
+ launching Thread 8 Queue 0 uCoreIdx 8 CoreId 12 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 9 Queue 0 uCoreIdx 9 CoreId 28 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 12][CoreNum: 31]: [0x7f738c002bb0]\r
+ Allocated gpThreadWorker[coreIdx: 13][CoreNum: 32]: [0x7f738c002e60]\r
+ launching Thread 10 Queue 0 uCoreIdx 10 CoreId 29 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 11 Queue 0 uCoreIdx 11 CoreId 30 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 14][CoreNum: 33]: [0x7f738c003110]\r
+ Allocated gpThreadWorker[coreIdx: 15][CoreNum: 34]: [0x7f738c0033c0]\r
+ launching Thread 12 Queue 0 uCoreIdx 12 CoreId 31 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 16][CoreNum: 35]: [0x7f738c003670]\r
+ launching Thread 13 Queue 0 uCoreIdx 13 CoreId 32 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ Allocated gpThreadWorker[coreIdx: 17][CoreNum: 36]: [0x7f738c003920]\r
+ 18 thread associated with queue 0:coreIdx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17\r
+ Leave RtThread Launch\r
+ launching Thread 14 Queue 0 uCoreIdx 14 CoreId 33 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 15 Queue 0 uCoreIdx 15 CoreId 34 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 16 Queue 0 uCoreIdx 16 CoreId 35 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ launching Thread 17 Queue 0 uCoreIdx 17 CoreId 36 Priority 94 Policy 1 nRtCoreSleep 1 nFriendCnt 0 nCurrentSfIdx -1\r
+\r
+ nr5g_gnb_mac2phy_api_proc_print_phy_init [0]:\r
+ nCarrierIdx: 0\r
+ nDMRSTypeAPos: 2\r
+ nPhyCellId: 50\r
+ nDLAbsFrePointA: 3500000\r
+ nULAbsFrePointA: 3500000\r
+ nDLBandwidth: 100\r
+ nULBandwidth: 100\r
+ nDLFftSize: 4096\r
+ nULFftSize: 4096\r
+ nSSBPwr: 0\r
+ nSSBAbsFre: 0\r
+ nSSBPeriod: 4\r
+ nSSBSubcSpacing: 1\r
+ nSSBSubcOffset: 0\r
+ nSSBPrbOffset: 0\r
+ nMIB[0]: 255\r
+ nMIB[1]: 255\r
+ nMIB[2]: 255\r
+ nDLK0: 0\r
+ nULK0: 0\r
+ nSSBMask[0]: 0\r
+ nSSBMask[1]: 0\r
+ nNrOfTxAnt: 64\r
+ nNrOfRxAnt: 64\r
+ nNrOfDLPorts: 16\r
+ nNrOfULPorts: 8\r
+ nCarrierAggregationLevel: 2\r
+ nFrameDuplexType: 1\r
+ nSubcCommon: 1\r
+ nTddPeriod: 10 (TDD)\r
+ SlotConfig:\r
+ Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r
+ 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+ 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+\r
+ nPrachConfIdx: 100\r
+ nPrachSubcSpacing: 1\r
+ nPrachZeroCorrConf: 1\r
+ nPrachRestrictSet: 0\r
+ nPrachRootSeqIdx: 0\r
+ nPrachFreqStart: 100\r
+ nPrachFdm: 1\r
+ nPrachSsbRach: 0\r
+ nPrachNrofRxRU: 4\r
+ nCyclicPrefix: 0\r
+ nGroupHopFlag: 0\r
+ nSequenceHopFlag: 0\r
+ nHoppingId: 0\r
+ nUrllcCapable: 0\r
+ nUrllcMiniSlotMask: 1 (0x00000001)\r
+ read_table: File table/common/pss_table.bin of size 381 read_size: 381\r
+ read_table: File table/common/sss_table.bin of size 128016 read_size: 128016\r
+ read_table: File table/common/srs_zc_36_plus.bin of size 905916 read_size: 905916\r
+ read_table: File table/common/pucch_zc_36_plus.bin of size 383040 read_size: 383040\r
+ read_table: File table/common/srs_wiener_sinc_comb2.bin of size 81216 read_size: 81216\r
+ read_table: File table/common/srs_wiener_sinc_comb4.bin of size 81216 read_size: 81216\r
+ BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r
+ set_slot_type SlotPattern:\r
+ Slot: 0 1 2 3 4 5 6 7 8 9\r
+ 0 DL DL DL SP UL DL DL DL SP UL\r
+\r
+ PHYDI-INIT[from 2] PhyInstance: 0\r
+ Processing MSG_TYPE_PHY_CONFIG_REQ: 1\r
+ nr5g_gnb_mac2phy_api_proc_print_phy_init [1]:\r
+ nCarrierIdx: 1\r
+ nDMRSTypeAPos: 2\r
+ nPhyCellId: 50\r
+ nDLAbsFrePointA: 3500000\r
+ nULAbsFrePointA: 3500000\r
+ nDLBandwidth: 100\r
+ nULBandwidth: 100\r
+ nDLFftSize: 4096\r
+ nULFftSize: 4096\r
+ nSSBPwr: 0\r
+ nSSBAbsFre: 0\r
+ nSSBPeriod: 4\r
+ nSSBSubcSpacing: 1\r
+ nSSBSubcOffset: 0\r
+ nSSBPrbOffset: 0\r
+ nMIB[0]: 255\r
+ nMIB[1]: 255\r
+ nMIB[2]: 255\r
+ nDLK0: 0\r
+ nULK0: 0\r
+ nSSBMask[0]: 0\r
+ nSSBMask[1]: 0\r
+ nNrOfTxAnt: 64\r
+ nNrOfRxAnt: 64\r
+ nNrOfDLPorts: 16\r
+ nNrOfULPorts: 8\r
+ nCarrierAggregationLevel: 2\r
+ nFrameDuplexType: 1\r
+ nSubcCommon: 1\r
+ nTddPeriod: 10 (TDD)\r
+ SlotConfig:\r
+ Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r
+ 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+ 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+\r
+ nPrachConfIdx: 100\r
+ nPrachSubcSpacing: 1\r
+ nPrachZeroCorrConf: 1\r
+ nPrachRestrictSet: 0\r
+ nPrachRootSeqIdx: 0\r
+ nPrachFreqStart: 100\r
+ nPrachFdm: 1\r
+ nPrachSsbRach: 0\r
+ nPrachNrofRxRU: 4\r
+ nCyclicPrefix: 0\r
+ nGroupHopFlag: 0\r
+ nSequenceHopFlag: 0\r
+ nHoppingId: 0\r
+ nUrllcCapable: 0\r
+ nUrllcMiniSlotMask: 1 (0x00000001)\r
+ BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r
+ set_slot_type SlotPattern:\r
+ Slot: 0 1 2 3 4 5 6 7 8 9\r
+ 0 DL DL DL SP UL DL DL DL SP UL\r
+\r
+ PHYDI-INIT[from 2] PhyInstance: 1\r
+ Processing MSG_TYPE_PHY_CONFIG_REQ: 2\r
+ nr5g_gnb_mac2phy_api_proc_print_phy_init [2]:\r
+ nCarrierIdx: 2\r
+ nDMRSTypeAPos: 2\r
+ nPhyCellId: 50\r
+ nDLAbsFrePointA: 3500000\r
+ nULAbsFrePointA: 3500000\r
+ nDLBandwidth: 100\r
+ nULBandwidth: 100\r
+ nDLFftSize: 4096\r
+ nULFftSize: 4096\r
+ nSSBPwr: 0\r
+ nSSBAbsFre: 0\r
+ nSSBPeriod: 4\r
+ nSSBSubcSpacing: 1\r
+ nSSBSubcOffset: 0\r
+ nSSBPrbOffset: 0\r
+ nMIB[0]: 255\r
+ nMIB[1]: 255\r
+ nMIB[2]: 255\r
+ nDLK0: 0\r
+ nULK0: 0\r
+ nSSBMask[0]: 0\r
+ nSSBMask[1]: 0\r
+ nNrOfTxAnt: 64\r
+ nNrOfRxAnt: 64\r
+ nNrOfDLPorts: 16\r
+ nNrOfULPorts: 8\r
+ nCarrierAggregationLevel: 2\r
+ nFrameDuplexType: 1\r
+ nSubcCommon: 1\r
+ nTddPeriod: 10 (TDD)\r
+ SlotConfig:\r
+ Slot Sym 0 Sym 1 Sym 2 Sym 3 Sym 4 Sym 5 Sym 6 Sym 7 Sym 8 Sym 9 Sym10 Sym11 Sym12 Sym13\r
+ 0 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 1 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 2 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 3 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 4 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+ 5 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 6 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL\r
+ 8 DL DL DL DL DL DL DL DL DL DL GD GD UL UL\r
+ 9 UL UL UL UL UL UL UL UL UL UL UL UL UL UL\r
+\r
+ nPrachConfIdx: 100\r
+ nPrachSubcSpacing: 1\r
+ nPrachZeroCorrConf: 1\r
+ nPrachRestrictSet: 0\r
+ nPrachRootSeqIdx: 0\r
+ nPrachFreqStart: 100\r
+ nPrachFdm: 1\r
+ nPrachSsbRach: 0\r
+ nPrachNrofRxRU: 4\r
+ nCyclicPrefix: 0\r
+ nGroupHopFlag: 0\r
+ nSequenceHopFlag: 0\r
+ nHoppingId: 0\r
+ nUrllcCapable: 0\r
+ nUrllcMiniSlotMask: 1 (0x00000001)\r
+ BBU Pooling Info: maximum period length was configured, preMaxSF = 20480, postMasSF = 20480\r
+ set_slot_type SlotPattern:\r
+ Slot: 0 1 2 3 4 5 6 7 8 9\r
+ 0 DL DL DL SP UL DL DL DL SP UL\r
+\r
+ PHYDI-INIT[from 2] PhyInstance: 2\r
+\r
+ ---------------------------------------------------------\r
+ Global Variables:\r
+ ---------------------------------------------------------\r
+ gCarrierAggLevel: 3\r
+ gCarrierAggLevelInit: 3\r
+ gSupportedAVX2 1\r
+ ---------------------------------------------------------\r
+\r
+ Received MSG_TYPE_PHY_START_REQ: 0\r
+ Received MSG_TYPE_PHY_START_REQ: 1\r
+ Received MSG_TYPE_PHY_START_REQ: 2\r
+ Processing MSG_TYPE_PHY_START_REQ: 0\r
+ di_open port 0\r
+\r
+ xran_init_vfs_mapping: p 0 vf 0\r
+ xran_init_vfs_mapping: p 0 vf 1\r
+ XRAN_UP_VF: 0x0000\r
+ xran_timing_source_thread [CPU 22] [PID: 29437]\r
+ xran_open [CPU 2] [PID: 29437]\r
+ Waithing on Timing thread...\r
+ TTI interval 500 [us]\r
+ Start C-plane DL 71 us after TTI [trigger on sym 2]\r
+ Start C-plane UL 200 us after TTI [trigger on sym 6]\r
+ Start U-plane DL 196 us before OTA [offset in sym -5]\r
+ Start U-plane UL 75 us OTA [offset in sym 3]\r
+ C-plane to U-plane delay 125 us after TTI\r
+ Start Sym timer 35714 ns\r
+ di_open port 1\r
+\r
+ xran_init_vfs_mapping: p 1 vf 2\r
+ xran_init_vfs_mapping: p 1 vf 3\r
+ Start C-plane DL 71 us after TTI [trigger on sym 2]\r
+ Start C-plane UL 200 us after TTI [trigger on sym 6]\r
+ Start U-plane DL 196 us before OTA [offset in sym -5]\r
+ Start U-plane UL 75 us OTA [offset in sym 3]\r
+ C-plane to U-plane delay 125 us after TTI\r
+ Start Sym timer 35714 ns\r
+ xran_open [CPU 2] [PID: 29437]\r
+ Waithing on Timing thread...\r
+ di_open port 2\r
+\r
+ xran_init_vfs_mapping: p 2 vf 4\r
+ xran_init_vfs_mapping: p 2 vf 5\r
+ Start C-plane DL 71 us after TTI [trigger on sym 2]\r
+ Start C-plane UL 200 us after TTI [trigger on sym 6]\r
+ Start U-plane DL 196 us before OTA [offset in sym -5]\r
+ Start U-plane UL 75 us OTA [offset in sym 3]\r
+ C-plane to U-plane delay 125 us after TTI\r
+ Start Sym timer 35714 ns\r
+ O-XU 0\r
+ HW 1\r
+ Num cores 4\r
+ Num ports 3\r
+ O-RU Cat 1\r
+ O-RU CC 3\r
+ O-RU eAxC 16\r
+ p:0 XRAN_JOB_TYPE_CP_DL worker id 1\r
+ p:0 XRAN_JOB_TYPE_CP_UL worker id 1\r
+ p:1 XRAN_JOB_TYPE_CP_DL worker id 1\r
+ p:1 XRAN_JOB_TYPE_CP_UL worker id 1\r
+ p:2 XRAN_JOB_TYPE_CP_DL worker id 1\r
+ p:2 XRAN_JOB_TYPE_CP_UL worker id 1\r
+ p:1 XRAN_JOB_TYPE_CP_DL worker id 2\r
+ p:1 XRAN_JOB_TYPE_CP_UL worker id 2\r
+ p:2 XRAN_JOB_TYPE_CP_DL worker id 2\r
+ p:2 XRAN_JOB_TYPE_CP_UL worker id 2\r
+ xran_generic_worker_thread [CPU 23] [PID: 29437]\r
+ spawn worker 0 core 23\r
+ xran_generic_worker_thread [CPU 24] [PID: 29437]\r
+ spawn worker 1 core 24\r
+ xran_generic_worker_thread [CPU 25] [PID: 29437]\r
+ spawn worker 2 core 25\r
+ xran_open [CPU 2] [PID: 29437]\r
+ Waithing on Timing thread...\r
+ ----------------------------------------------------------------------------\r
+ mem_mgr_display_size:\r
+ Num Memory Alloc: 38,294\r
+ Total Memory Size: 20,049,968,118\r
+ ----------------------------------------------------------------------------\r
+\r
+\r
+ PHYDI-START[from 2] PhyInstance: 0, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r
+ PHYDI-START[from 2] PhyInstance: 1, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r
+ PHYDI-START[from 2] PhyInstance: 2, Mode: 4, Count: 100207, Period: 0, NumSlotPerSfn: 20\r
+ Setting nMultiCellModeDelay: 40000\r
+ nr5g_gnb_urllc_register_call_backs: nTimerMode[0] nUrllcMiniSlotMask[0]\r
+ port [0] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r
+ port 0 has 1 CCs\r
+ port 0 cc_id 0 is phy id 0\r
+ XRAN front haul xran_mm_init\r
+ xran_sector_get_instances [0]: CC 0 handle 0x7f6fe7383280\r
+ Handle: 0xee1c8e0 Instance: 0x7f6fe7383280\r
+ gnb_io_xran_start [0]: CC 0 handle 0x7f6fe7383280\r
+ Sucess xran_mm_init Instance 0x7f6fe7383280\r
+ nSectorNum 1\r
+ ru_0_cc_0_idx_0: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 0] mb pool 0x44c493480\r
+ ru_0_cc_0_idx_1: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 1] mb pool 0x444381640\r
+ ru_0_cc_0_idx_2: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 2] mb pool 0x443dff2c0\r
+ ru_0_cc_0_idx_3: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 3] mb pool 0x443c5cf40\r
+ ru_0_cc_0_idx_4: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 4] mb pool 0x443ababc0\r
+ ru_0_cc_0_idx_5: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 5] mb pool 0x443538840\r
+ ru_0_cc_0_idx_6: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 6] mb pool 0x4433964c0\r
+ ru_0_cc_0_idx_7: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 7] mb pool 0x4431f4140\r
+ ru_0_cc_0_idx_8: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 8] mb pool 0x442ff1dc0\r
+ ru_0_cc_0_idx_9: [ handle 0x7f6fe7383280 0 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383280 ru 0 cc_idx 0 ] [nPoolIndex 9] mb pool 0x441e6fa40\r
+ port [0] gnb_io_xran_init_cp\r
+ port [0] init xran successfully\r
+ port [1] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r
+ port 1 has 1 CCs\r
+ port 1 cc_id 0 is phy id 1\r
+ XRAN front haul xran_mm_init\r
+ xran_sector_get_instances [1]: CC 0 handle 0x7f6fe7383380\r
+ Handle: 0xee1c940 Instance: 0x7f6fe7383380\r
+ gnb_io_xran_start [1]: CC 0 handle 0x7f6fe7383380\r
+ Sucess xran_mm_init Instance 0x7f6fe7383280\r
+ nSectorNum 1\r
+ ru_1_cc_0_idx_0: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 0] mb pool 0x2a1525740\r
+ ru_1_cc_0_idx_1: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 1] mb pool 0x299413900\r
+ ru_1_cc_0_idx_2: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 2] mb pool 0x28f1112c0\r
+ ru_1_cc_0_idx_3: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 3] mb pool 0x287f4fb80\r
+ ru_1_cc_0_idx_4: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 4] mb pool 0x27fe3dd40\r
+ ru_1_cc_0_idx_5: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 5] mb pool 0x275b3b700\r
+ ru_1_cc_0_idx_6: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 6] mb pool 0x26e979fc0\r
+ ru_1_cc_0_idx_7: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 7] mb pool 0x269ce9980\r
+ ru_1_cc_0_idx_8: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r
+ O-DU: thread_run start time: 08/11/20 23:05:24.000000001 UTC [500]\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 8] mb pool 0x249d33b40\r
+ ru_1_cc_0_idx_9: [ handle 0x7f6fe7383380 1 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383380 ru 1 cc_idx 0 ] [nPoolIndex 9] mb pool 0x2215b1500\r
+ port [1] gnb_io_xran_init_cp\r
+ port [1] init xran successfully\r
+ port [2] gnb_io_xran_start: gGnbIoXranStarted[0] CC 3 Ant 16 AntElm 64 [Cell: nNrOfDLPorts 16 nNrOfULPorts 8]\r
+ port 2 has 1 CCs\r
+ port 2 cc_id 0 is phy id 2\r
+ XRAN front haul xran_mm_init\r
+ xran_sector_get_instances [2]: CC 0 handle 0x7f6fe7383440\r
+ Handle: 0xee1c9a0 Instance: 0x7f6fe7383440\r
+ gnb_io_xran_start [2]: CC 0 handle 0x7f6fe7383440\r
+ Sucess xran_mm_init Instance 0x7f6fe7383280\r
+ nSectorNum 1\r
+ ru_2_cc_0_idx_0: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 0] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 0] mb pool 0x203b7bdc0\r
+ ru_2_cc_0_idx_1: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 1] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 1] mb pool 0x1fba69f80\r
+ ru_2_cc_0_idx_2: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 2] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 2] mb pool 0x1f1767940\r
+ ru_2_cc_0_idx_3: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 3] nNumberOfBuffers 8960 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 3] mb pool 0x1ea5a6200\r
+ ru_2_cc_0_idx_4: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 4] nNumberOfBuffers 286720 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 4] mb pool 0x1e24943c0\r
+ ru_2_cc_0_idx_5: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 5] nNumberOfBuffers 8960 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 5] mb pool 0x1d8191d80\r
+ ru_2_cc_0_idx_6: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 6] nNumberOfBuffers 8960 nBufferSize 8192\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 6] mb pool 0x1d0fd0640\r
+ ru_2_cc_0_idx_7: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 7] nNumberOfBuffers 35840 nBufferSize 14432\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 7] mb pool 0x1cc340000\r
+ ru_2_cc_0_idx_8: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 8] nNumberOfBuffers 1146880 nBufferSize 32\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 8] mb pool 0x1ac38a1c0\r
+ ru_2_cc_0_idx_9: [ handle 0x7f6fe7383440 2 0 ] [nPoolIndex 9] nNumberOfBuffers 35840 nBufferSize 12560\r
+ CC:[ handle 0x7f6fe7383440 ru 2 cc_idx 0 ] [nPoolIndex 9] mb pool 0x183c07b80\r
+ port [2] gnb_io_xran_init_cp\r
+ port [2] init xran successfully\r
+ O-DU: XRAN start time: 08/11/20 23:05:24.384220762 UTC [500]\r
+ BBU Pooling: enter multicell Activate!\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 14 coreId 33 at 118352443946329 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 1 coreId 5 at 118352443939667 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 11 coreId 30 at 118352443942535 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 8 coreId 12 at 118352443944575 at sf=0 with queue 0 successfully\r
+ BBU Pooling: active result: Q_id = 0,currenSf = 0, curCellNum = 0, activesfn = 4, CellNumInActSfn = 3\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 2 coreId 6 at 118352443929961 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 15 coreId 34 at 118352443933301 at sf=0 with queue 0 successfully\r
+ BBU Pooling: multiCell Activate sucessfully!\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 13 coreId 32 at 118352443935245 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 4 coreId 8 at 118352443936745 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 6 coreId 10 at 118352443936883 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 3 coreId 7 at 118352443936747 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 12 coreId 31 at 118352443938019 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 5 coreId 9 at 118352443939937 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 9 coreId 28 at 118352443941217 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 16 coreId 35 at 118352443944465 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 17 coreId 36 at 118352443937701 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 0 coreId 4 at 118352443926969 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 10 coreId 29 at 118352443928691 at sf=0 with queue 0 successfully\r
+ BBU Pooling Info: bbupool rt thread start on CoreIdx 7 coreId 11 at 118352443931713 at sf=0 with queue 0 successfully\r
+ phy_bbupool_rx_handler: PhyId[0] nSfIdx[4] frame,slot[0,5] gNumSlotPerSfn[20]\r
+ ==== l1app Time: 5002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r
+ ==== [o-du0][rx 3807776 pps 761555 kbps 4744396][tx 10937607 pps 2187521 kbps 26031486] [on_time 3807776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3807776]\r
+ Pusch[ 439372 439372 439372 439372 439372 439372 439372 439372] SRS[ 292800]\r
+ ==== [o-du1][rx 1469469 pps 293893 kbps 2684928][tx 3649817 pps 729963 kbps 9156812] [on_time 1469469 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469469]\r
+ Pusch[ 146964 146956 146964 146956 146964 146956 146964 146956] SRS[ 293788]\r
+ ==== [o-du2][rx 1469463 pps 293892 kbps 2684960][tx 3648883 pps 729776 kbps 9152795] [on_time 1469463 early 0 late 0 corrupt 0 pkt_dupl 144 Total 1469463]\r
+ Pusch[ 146956 146956 146956 146956 146956 146956 146956 146956] SRS[ 293815]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 0 0 / 0 0.00%\r
+ 1 (Kbps) 0 0 / 0 0.00%\r
+ 2 (Kbps) 0 0 / 0 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 0 4 2 4 4 2 3 13 17 0 13 15 14 16 14 17 15 14 9.28\r
+ Xran Id: 22 23 24 25 Master Core Util: 85 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 10002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r
+ ==== [o-du0][rx 5472406 pps 332926 kbps 4744396][tx 21871698 pps 2186818 kbps 26038405] [on_time 5472406 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5472406]\r
+ Pusch[ 192084 192078 192078 192078 192078 192078 192078 192078] SRS[ 128000]\r
+ ==== [o-du1][rx 2109680 pps 128042 kbps 2684917][tx 7297930 pps 729622 kbps 9156922] [on_time 2109680 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109680]\r
+ Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128004]\r
+ ==== [o-du2][rx 2109682 pps 128043 kbps 2684993][tx 7296833 pps 729590 kbps 9156258] [on_time 2109682 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2109682]\r
+ Pusch[ 64026 64026 64026 64026 64026 64026 64026 64026] SRS[ 128011]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,894,368 576,420 / 576,492 0.00%\r
+ 1 (Kbps) 0 0 / 0 0.00%\r
+ 2 (Kbps) 0 0 / 0 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 15 30 34 29 26 28 26 46 50 0 40 40 43 42 44 42 48 50 35.17\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 15003 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [ 0.00.. 0.00.. 0.00] usces\r
+ ==== [o-du0][rx 7136544 pps 332827 kbps 4744396][tx 32806663 pps 2186993 kbps 26042173] [on_time 7136544 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7136544]\r
+ Pusch[ 192012 192018 192018 192018 192018 192018 192018 192018] SRS[ 128000]\r
+ ==== [o-du1][rx 2749728 pps 128009 kbps 2684895][tx 10945622 pps 729538 kbps 9155645] [on_time 2749728 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749728]\r
+ Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]\r
+ ==== [o-du2][rx 2749730 pps 128009 kbps 2684840][tx 10944272 pps 729487 kbps 9154660] [on_time 2749730 early 0 late 0 corrupt 0 pkt_dupl 144 Total 2749730]\r
+ Pusch[ 64006 64006 64006 64006 64006 64006 64006 64006] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r
+ 1 (Kbps) 539,740 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 0 0 / 0 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 27 33 40 38 38 35 34 56 56 26 50 47 48 47 51 48 57 57 43.78\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Setting MLogMask because nMLogDelay == 0\r
+ ==== l1app Time: 20002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [480.00..500.23..516.00] usces\r
+ ==== [o-du0][rx 8799776 pps 332646 kbps 4744396][tx 43740623 pps 2186792 kbps 26042944] [on_time 8799776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 8799776]\r
+ Pusch[ 191904 191904 191904 191904 191904 191904 191904 191904] SRS[ 128000]\r
+ ==== [o-du1][rx 3389472 pps 127948 kbps 2684982][tx 14591619 pps 729199 kbps 9154093] [on_time 3389472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389472]\r
+ Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]\r
+ ==== [o-du2][rx 3389474 pps 127948 kbps 2684873][tx 14589997 pps 729145 kbps 9152608] [on_time 3389474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 3389474]\r
+ Pusch[ 63968 63968 63968 63968 63968 63968 63968 63968] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 43 47 46 43 42 43 41 61 60 27 57 56 58 57 55 56 64 62 51.00\r
+ Xran Id: 22 23 24 25 Master Core Util: 96 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 25002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [442.00..500.12..562.00] usces\r
+ ==== [o-du0][rx 10463824 pps 332809 kbps 4744396][tx 54675513 pps 2186978 kbps 26044150] [on_time 10463824 early 0 late 0 corrupt 0 pkt_dupl 144 Total 10463824]\r
+ Pusch[ 192006 192006 192006 192006 192006 192006 192006 192006] SRS[ 128000]\r
+ ==== [o-du1][rx 4029487 pps 128003 kbps 2684928][tx 18237287 pps 729133 kbps 9150163] [on_time 4029487 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029487]\r
+ Pusch[ 64002 64002 64002 64002 64002 64002 64002 64001] SRS[ 128000]\r
+ ==== [o-du2][rx 4029474 pps 128000 kbps 2684873][tx 18235338 pps 729068 kbps 9148513] [on_time 4029474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4029474]\r
+ Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 44 48 46 46 44 41 43 62 61 27 58 59 55 56 56 58 61 62 51.50\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 30002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [435.00..500.12..562.00] usces\r
+ ==== [o-du0][rx 12127888 pps 332812 kbps 4744396][tx 65610457 pps 2186988 kbps 26044065] [on_time 12127888 early 0 late 0 corrupt 0 pkt_dupl 144 Total 12127888]\r
+ Pusch[ 192012 192006 192012 192006 192010 192006 192006 192006] SRS[ 128000]\r
+ ==== [o-du1][rx 4669504 pps 128003 kbps 2685058][tx 21883550 pps 729252 kbps 9152750] [on_time 4669504 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669504]\r
+ Pusch[ 64002 64002 64002 64002 64002 64002 64002 64003] SRS[ 128000]\r
+ ==== [o-du2][rx 4669498 pps 128004 kbps 2684993][tx 21881293 pps 729191 kbps 9151846] [on_time 4669498 early 0 late 0 corrupt 0 pkt_dupl 144 Total 4669498]\r
+ Pusch[ 64004 64004 64004 64004 64002 64002 64002 64002] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 577,069 / 577,069 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 44 47 45 47 43 43 42 63 63 27 56 56 56 55 58 55 65 62 51.50\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 35002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [434.00..500.12..554.00] usces\r
+ ==== [o-du0][rx 13792256 pps 332873 kbps 4744892][tx 76545521 pps 2187012 kbps 26042901] [on_time 13792256 early 0 late 0 corrupt 0 pkt_dupl 144 Total 13792256]\r
+ Pusch[ 192042 192048 192042 192048 192044 192048 192048 192048] SRS[ 128000]\r
+ ==== [o-du1][rx 5309632 pps 128025 kbps 2685102][tx 25528867 pps 729063 kbps 9151639] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632]\r
+ Pusch[ 64016 64016 64016 64016 64016 64016 64016 64016] SRS[ 128000]\r
+ ==== [o-du2][rx 5309632 pps 128026 kbps 2685102][tx 25526238 pps 728989 kbps 9150147] [on_time 5309632 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5309632]\r
+ Pusch[ 64016 64016 64016 64016 64018 64018 64017 64017] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 43 48 45 47 43 41 42 66 61 27 57 57 55 56 57 56 64 62 51.50\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 40002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [440.00..500.12..553.00] usces\r
+ ==== [o-du0][rx 15455740 pps 332696 kbps 4744396][tx 87479892 pps 2186874 kbps 26042995] [on_time 15455740 early 0 late 0 corrupt 0 pkt_dupl 144 Total 15455740]\r
+ Pusch[ 191940 191940 191940 191940 191940 191940 191940 191940] SRS[ 127964]\r
+ ==== [o-du1][rx 5949408 pps 127955 kbps 2684764][tx 29174424 pps 729111 kbps 9150009] [on_time 5949408 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949408]\r
+ Pusch[ 63980 63980 63980 63980 63980 63980 63980 63980] SRS[ 127936]\r
+ ==== [o-du2][rx 5949410 pps 127955 kbps 2684840][tx 29171380 pps 729028 kbps 9148386] [on_time 5949410 early 0 late 0 corrupt 0 pkt_dupl 144 Total 5949410]\r
+ Pusch[ 63980 63980 63980 63980 63980 63980 63981 63981] SRS[ 127936]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 44 48 44 45 42 42 43 63 63 27 57 56 55 58 56 56 64 62 51.39\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 45002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..556.00] usces\r
+ ==== [o-du0][rx 17119776 pps 332807 kbps 4743900][tx 98415119 pps 2187045 kbps 26043843] [on_time 17119776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 17119776]\r
+ Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128036]\r
+ ==== [o-du1][rx 6589472 pps 128012 kbps 2684753][tx 32820214 pps 729158 kbps 9154170] [on_time 6589472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589472]\r
+ Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]\r
+ ==== [o-du2][rx 6589474 pps 128012 kbps 2684753][tx 32816780 pps 729080 kbps 9152613] [on_time 6589474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 6589474]\r
+ Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128064]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,780 / 576,780 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 44 47 46 47 43 42 42 61 63 27 56 58 56 56 58 57 63 65 51.72\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ ==== l1app Time: 50002 ms NumCarrier: 3 NumBbuCores: 18. Tti2Tti Time: [436.00..500.12..551.00] usces\r
+ ==== [o-du0][rx 18783776 pps 332800 kbps 4744396][tx 109350065 pps 2186989 kbps 26043142] [on_time 18783776 early 0 late 0 corrupt 0 pkt_dupl 144 Total 18783776]\r
+ Pusch[ 192000 192000 192000 192000 192000 192000 192000 192000] SRS[ 128000]\r
+ ==== [o-du1][rx 7229472 pps 128000 kbps 2684928][tx 36466505 pps 729258 kbps 18302595] [on_time 7229472 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229472]\r
+ Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r
+ ==== [o-du2][rx 7229474 pps 128000 kbps 2684895][tx 36462749 pps 729193 kbps 9148265] [on_time 7229474 early 0 late 0 corrupt 0 pkt_dupl 144 Total 7229474]\r
+ Pusch[ 64000 64000 64000 64000 64000 64000 64000 64000] SRS[ 128000]\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Cell DL Tput UL Tput UL BLER\r
+ 0 (Kbps) 6,896,256 576,492 / 576,492 0.00%\r
+ 1 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ 2 (Kbps) 539,814 65,260 / 65,260 0.00%\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ Core Utilization [18 BBU core(s)]:\r
+ Core Id: 4 5 6 7 8 9 10 11 12 28 29 30 31 32 33 34 35 36 Avg\r
+ Util %: 43 47 45 47 43 41 41 62 63 27 57 55 57 56 55 57 62 66 51.33\r
+ Xran Id: 22 23 24 25 Master Core Util: 95 %\r
+ -------------------------------------------------------------------------------------------------------------------------------------------------------\r
+\r
+7. To execute testmac with O-DU functionality according to O-RAN Fronthaul specification, enter::\r
+\r
+ [root@xran flexran] cd ./bin/nr5g/gnb/testmac\r
+\r
+8. To execute test case type::\r
+\r
+ ./l2.sh --testfile=./cascade_lake-sp/csxsp_mu1_100mhz_mmimo_hton_xran.cfg\r
+\r
+where output corresponding to Test MAC::\r
+\r
+ root@icelake-scs1-1 testmac]# ./l2.sh --testfile=./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r
+ kernel.sched_rt_runtime_us = -1\r
+ kernel.shmmax = 2147483648\r
+ kernel.shmall = 2147483648\r
+ Note: Forwarding request to 'systemctl disable irqbalance.service'.\r
+ start 5GNR Test MAC\r
+ =========================\r
+ 5GNR Testmac Application\r
+ =========================\r
+ testmac_cfg_set_cfg_filename: Coult not find string 'cfgfile' in command line. Using default File: testmac_cfg.xml\r
+\r
+\r
+ ---------------------------\r
+ TestMacCfg.xml Version: 20.08\r
+ ---------------------------\r
+\r
+ --version=20.08\r
+ --wls_dev_name=wls0\r
+ --wlsMemorySize=0x3F600000\r
+ --dpdkIovaMode=0\r
+ --PhyStartMode=1\r
+ --PhyStartPeriod=40\r
+ --PhyStartCount=0\r
+ --MlogSubframes=128\r
+ --MlogCores=3\r
+ --MlogSize=2048\r
+ --latencyTest=0\r
+ --wlsRxThread=1, 90, 0\r
+ --systemThread=0, 0, 0\r
+ --runThread=0, 89, 0\r
+ --urllcThread=16, 90, 0\r
+\r
+ wls_dev_filename: wls0\r
+ sys_reg_signal_handler:[err] signal handler in NULL\r
+ sys_reg_signal_handler:[err] signal handler in NULL\r
+ timer_set_tsc_freq_from_clock: System clock (rdtsc) resolution 1496523032 [Hz]\r
+ Ticks per usec 1496\r
+ MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(3), mlogSize(2048)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1496526140 [Hz]\r
+ Ticks per us 1496\r
+ MLog Storage: 0x7f821905d100 -> 0x7f821911d920 [ 788512 bytes ]\r
+ localMLogFreqReg: 1496. Storing: 1496\r
+ Mlog Open successful\r
+\r
+ Calling rte_eal_init: testmac -c1 --proc-type=auto --file-prefix wls0 --iova-mode=pa\r
+ EAL: Detected 48 lcore(s)\r
+ EAL: Detected 1 NUMA nodes\r
+ EAL: Auto-detected process type: SECONDARY\r
+ EAL: Multi-process socket /var/run/dpdk/wls0/mp_socket_29473_6b9e031eaf8b\r
+ EAL: Selected IOVA mode 'PA'\r
+ EAL: Probing VFIO support...\r
+ EAL: PCI device 0000:01:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:1533 net_e1000_igb\r
+ EAL: PCI device 0000:18:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:1563 net_ixgbe\r
+ EAL: PCI device 0000:18:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:1563 net_ixgbe\r
+ EAL: PCI device 0000:8c:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:8c:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:90:00.0 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ EAL: PCI device 0000:90:00.1 on NUMA socket 0\r
+ EAL: probe driver: 8086:d58 net_i40e\r
+ wls_lib: Open wls0 (DPDK memzone)\r
+ wls_lib: WLS_Open 0x43f600000\r
+ wls_lib: link: 1 <-> 0\r
+ wls_lib: Mode 1\r
+ wls_lib: WLS shared management memzone: wls0\r
+ wls_lib: hugePageSize on the system is 1073741824\r
+ wls_lib: WLS_Alloc [1063256064] bytes\r
+ wls_lib: Connecting to remote peer ...\r
+ wls_lib: Connected to remote peer\r
+ wls_mac_create_mem_array: pMemArray[0xf354350] pMemArrayMemory[0x400000000] totalSize[1063256064] nBlockSize[262144] numBlocks[4056]\r
+ WLS_EnqueueBlock [1]\r
+ WLS inited ok [383]\r
+\r
+\r
+ ===========================================================================================================\r
+ TESTMAC VERSION\r
+ ===========================================================================================================\r
+\r
+ $Version: #DIRTY# $ (x86)\r
+ IMG-date: Aug 5 2020\r
+ IMG-time: 18:32:53\r
+ ===========================================================================================================\r
+\r
+\r
+ ===========================================================================================================\r
+ Testmac threads in application\r
+ ===========================================================================================================\r
+ testmac_run_thread: [PID: 29477] binding on [CPU 0] [PRIO: 89] [POLICY: 1]\r
+ wls_mac_rx_task: [PID: 29476] binding on [CPU 1] [PRIO: 90] [POLICY: 1]\r
+ ===========================================================================================================\r
+\r
+ testmac_set_phy_start: mode[1], period[40], count[0]\r
+\r
+ testmac_run_load_files:\r
+ Loading DL Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/dl/testmac_dl_mu3_100mhz.cfg\r
+ Loading UL Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_40mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/ul/testmac_ul_mu3_100mhz.cfg\r
+ Loading FD Config Files:\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_5mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_10mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu0_20mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_40mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu1_100mhz.cfg\r
+ testmac_run_parse_file Parsing config file: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/fd/testmac_fd_mu3_100mhz.cfg\r
+\r
+ TESTMAC DL TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[0] Bandwidth[20]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008\r
+ Numerology[1] Bandwidth[100]\r
+ 1200 1201 1202 1203 1204 1205 1206 1207 1210 1211\r
+ 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221\r
+ 1222 1223 1224 1225 1226 1227 1228 1229 1230 1241\r
+ 1242 1243 1244 1245 1250 1251 1252 1260 1261 1262\r
+ 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272\r
+ 1300 1301 1302 1303 1304 1305 1402 1404 1408 1416\r
+ 1500 1501 1502 1503 1504 1505 1506 2213 2214 2215\r
+ 2217 2218 2219 2223 2224 2225 2227 2228 2229 2500\r
+ 2501 2502 2503 2504 3213 3214 3215 3217 3218 3219\r
+ 3223 3224 3225 3227 3228 3229\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1003 1005 1006 1007 1008 1009 1010 1011\r
+ 1012 1013 1014 1015 1016 1017 1018 1019 1030 1031\r
+ 1032 1033 2001 2002 2003 2030 2033 3001 3002 3003\r
+ 3030\r
+\r
+ TESTMAC UL TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 1002 1003 1069 1070 1071 1072 1073 1074 1075\r
+ 1076 1077\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 1002 1069 1070 1071 1072 1073 1074 1075 1076\r
+ 1077\r
+ Numerology[0] Bandwidth[20]\r
+ 1001 1002 1003 1004 1005 1006 1007 1008 1069 1070\r
+ 1071 1072 1073 1074 1075 1076 1077\r
+ Numerology[1] Bandwidth[10]\r
+ 1069 1070 1071 1072 1073 1074 1075 1076 1077\r
+ Numerology[1] Bandwidth[20]\r
+ 1069 1070 1071 1072 1073 1074 1075 1076 1077\r
+ Numerology[1] Bandwidth[40]\r
+ 1069 1070 1071 1072 1073 1074 1075 1076 1077\r
+ Numerology[1] Bandwidth[100]\r
+ 1010 1030 1031 1032 1033 1034 1035 1036 1037 1038\r
+ 1039 1040 1041 1042 1043 1070 1071 1072 1073 1074\r
+ 1080 1081 1082 1083 1084 1085 1086 1087 1091 1092\r
+ 1093 1094 1095 1096 1100 1101 1102 1103 1104 1105\r
+ 1106 1107 1108 1110 1111 1113 1114 1115 1116 1117\r
+ 1118 1119 1120 1121 1122 1123 1124 1130 1131 1132\r
+ 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142\r
+ 1143 1150 1152 1153 1154 1155 1156 1157 1159 1160\r
+ 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170\r
+ 1171 1172 1173 1200 1201 1202 1203 1204 1205 1206\r
+ 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216\r
+ 1217 1218 1219 1220 1221 1222 1230 1231 1232 1233\r
+ 1234 1235 1236 1237 1402 1404 1408 1416 1420 1421\r
+ 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431\r
+ 1432 1433 1434 1435 1436 1437 1438 1500 1503 1504\r
+ 1505 1506 1507 1508 1512 1513 1514 1515 1516 1540\r
+ 1541 1542 1563 1564 1565 1566 1567 1568 1569 1570\r
+ 1571 1572 1573 1574 1575 1576 1577 1600 1601 1602\r
+ 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612\r
+ 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622\r
+ 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632\r
+ 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642\r
+ 1700 1701 1702 1969 1970 1971 1972 1973 1974 1975\r
+ 1976 1977 2236 2237 3236 3237\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1003 1004 1005 1006 1007 1010 1011 1012\r
+ 1013 1014 1015 1020 1021 1022 1023 1024 1025 1026\r
+ 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036\r
+ 1037 1040 1041 1042 1043 1044 1045 1046 1050 1051\r
+ 1052 1053 1054 1059 1060 1061 1062 1063 1064 1065\r
+ 1066 1067 1070 1071 1073 1074 1081 1082 1083 1084\r
+ 1085 1086 2001 2002 2003 3001 3002 3003\r
+\r
+ TESTMAC FD TESTS:\r
+ Numerology[0] Bandwidth[5]\r
+ 1001 6001 8001 10001 12001\r
+ Numerology[0] Bandwidth[10]\r
+ 1001 2001 4001 6001 8001 10001 12001 1002 2002 4002\r
+ 6002 8002 10002 12002 1003\r
+ Numerology[0] Bandwidth[20]\r
+ 1002 1004 1012 1014 1015 1016 1017 1018 1020 1021\r
+ 1022 1023 1024 1025 1030 1031 1032 1033 1200 1201\r
+ 1202 1206 1207 1208 1209 1210 1211 1212 1220 1221\r
+ 1222 1223 1224 1225 1226 1227 1228\r
+ Numerology[1] Bandwidth[40]\r
+ 1001 1002 1003\r
+ Numerology[1] Bandwidth[100]\r
+ 1001 1002 1200 1201 1202 1203 1204 1205 1206 1207\r
+ 1208 1209 1210 1300 1301 1302 1303 1304 1305 1306\r
+ 1307 1308 1350 1351 1352 1353 1354 1355 1356 1357\r
+ 1358 1359 1370 1371 1372 1373 1374 1375 1376 1377\r
+ 1378 1401 1402 1403 1404 1405 1406 1411 1412 1490\r
+ 1494 1500 1501 1502 1503 1504 1510 1511 1512 1513\r
+ 1514 1515 1520 1521 1522 1523 1524 1525 1526 1527\r
+ 1528 1529 1530 1531 1532 1540 1541 1700 1701 1702\r
+ 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529\r
+ 2530 2531 2532 3524 3525 3526 3527 3528 3529 3530\r
+ 3531 3532 4524 4525 4526 4527 4528 4529 4530 4531\r
+ 4532\r
+ Numerology[3] Bandwidth[100]\r
+ 1001 1002 1004 1005 1006 1007 1008 1009 1010 1011\r
+ 1012 1013 1014 1015 1061 1062 1063 1064 1065 1080\r
+ 1081 1082 2001 3001\r
+ testmac_run_parse_file Parsing config file: ./icelake-sp/icxsp_mu1_100mhz_mmimo_64x64_hton_xran.cfg\r
+ testmac_set_phy_start: mode[4], period[0], count[100200]\r
+ Adding setoption pdsch_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r
+ Adding setoption pdsch_dl_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r
+ Adding setoption pusch_chan_est_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r
+ Adding setoption pusch_mmse_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 4] [pMacOptions: 260 / 0x00000104]\r
+ Adding setoption pusch_llr_rx_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r
+ Adding setoption pusch_ul_weight_split [numTests: 0] [nCellMask: 0x00000001] [nOption: 2] [pMacOptions: 258 / 0x00000102]\r
+ Adding setoption timer_multi_cell [numTests: 0] [nCellMask: 0xffffffff] [nOption: 10000] [pMacOptions: 10000 / 0x00002710]\r
+ Adding setoption fec_dec_num_iter [numTests: 0] [nCellMask: 0xffffffff] [nOption: 3] [pMacOptions: -253 / 0xffffff03]\r
+ Adding SetCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[137170526192 / 0x0000001ff0001ff0]\r
+ Adding SetDlbeamCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[2016 / 0x00000000000007e0]\r
+ Adding SetSrsCoreMask[numTests: 0][setCoreCnt: 0]. CoreMask[268435472 / 0x0000000010000010]\r
+ Setting Testmac System Core: 2\r
+ Setting Testmac Run Core: 2\r
+ Setting Testmac Wls Core: 3\r
+ Adding Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/\r
+ Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg\r
+ Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r
+ Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r
+\r
+ testmac_set_multi_cell_timer: 10000\r
+\r
+\r
+\r
+\r
+ ----------------------------------------------------------------------------------------\r
+ Running Test[3370]. NumCarr[3], Current Directory: /home/vzakharc/master/../master_aux/flexran_l1_5g_test/\r
+ Carrier[0]: ConfigFile: fd/mu1_100mhz/376/fd_testconfig_tst376.cfg\r
+ Carrier[1]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r
+ Carrier[2]: ConfigFile: fd/mu1_100mhz/377/fd_testconfig_tst377.cfg\r
+ TESTMAC>welcome to application console\r
+\r
+ MLogRestart\r
+ MLogOpen: filename(testmac-mlog.bin) mlogSubframes (128), mlogCores(3), mlogSize(2048) mlog_mask (-1)\r
+ mlogSubframes (128), mlogCores(3), mlogSize(2048)\r
+ localMLogTimerInit\r
+ System clock (rdtsc) resolution 1496525908 [Hz]\r
+ Ticks per us 1496\r
+ MLog Storage: 0x7f8208000900 -> 0x7f82080c1120 [ 788512 bytes ]\r
+ localMLogFreqReg: 1496. Storing: 1496\r
+ Mlog Open successful\r
+\r
+ testmac_mac2phy_set_num_cells: Setting Max Cells: 3\r
+ testmac_config_parse: test_num[3370] test_type[2] numcarrier[3]\r
+ Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r
+ Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(1)\r
+ Queueing MSG_TYPE_PHY_UL_IQ_SAMPLES(2)\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES(0)\r
+ Queueing MSG_TYPE_PHY_CONFIG_REQ(0)\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES(1)\r
+ Queueing MSG_TYPE_PHY_CONFIG_REQ(1)\r
+ Received MSG_TYPE_PHY_UL_IQ_SAMPLES(2)\r
+ Queueing MSG_TYPE_PHY_CONFIG_REQ(2) and sending list\r
+ Received MSG_TYPE_PHY_CONFIG_RESP(0)\r
+ Queueing MSG_TYPE_PHY_START_REQ(0)\r
+ Received MSG_TYPE_PHY_CONFIG_RESP(1)\r
+ Queueing MSG_TYPE_PHY_START_REQ(1)\r
+ Received MSG_TYPE_PHY_CONFIG_RESP(2)\r
+ Queueing MSG_TYPE_PHY_START_REQ(2) and sending list\r
+ Received MSG_TYPE_PHY_START_RESP(0)\r
+ Received MSG_TYPE_PHY_START_RESP(1)\r
+ Received MSG_TYPE_PHY_START_RESP(2)\r
+ ==== testmac Time: 5000 ms NumCarrier: 3 Total Proc Time: [ 0.00.. 6.30.. 19.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 0.42%]\r
+ ==== testmac Time: 10000 ms NumCarrier: 3 Total Proc Time: [ 6.00..116.80..206.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 27.86%]\r
+ ==== testmac Time: 20000 ms NumCarrier: 3 Total Proc Time: [ 10.00..156.33..260.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.31%]\r
+ ==== testmac Time: 25000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.33..260.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.30%]\r
+ ==== testmac Time: 30000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.44..256.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.32%]\r
+ ==== testmac Time: 35000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.42..258.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.32%]\r
+ ==== testmac Time: 40000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.45..258.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.33%]\r
+ ==== testmac Time: 45000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.40..282.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.32%]\r
+\r
+ TESTMAC>==== testmac Time: 50000 ms NumCarrier: 3 Total Proc Time: [ 11.00..156.39..260.00] usces====\r
+ Core Utilization [Core: 3] [Util %: 32.31%]\r
+ Received MSG_TYPE_PHY_STOP_RESP(0)\r
+ Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(0)\r
+ Received MSG_TYPE_PHY_STOP_RESP(1)\r
+ Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(1)\r
+ Received MSG_TYPE_PHY_STOP_RESP(2)\r
+ Queueing MSG_TYPE_PHY_SHUTDOWN_REQ(2) and sending list\r
+ Received MSG_TYPE_PHY_SHUTDOWN_RESP(2)\r
+ Received MSG_TYPE_PHY_SHUTDOWN_RESP(0)\r
+ Received MSG_TYPE_PHY_SHUTDOWN_RESP(1)\r
+ MLogPrint: ext_filename((null).bin)\r
+ Opening MLog File: testmac-mlog-c0.bin\r
+ MLog file testmac-mlog-c0.bin closed\r
+ Mlog Print successful\r
+ Test[FD_mu1_100mhz_3370] Completed\r
+ wls_mac_free_list_all:\r
+ nTotalBlocks[4056] nAllocBlocks[1010] nFreeBlocks[3046]\r
+ nTotalAllocCnt[4538427] nTotalFreeCnt[4537417] Diff[1010]\r
+ nDlBufAllocCnt[3609068] nDlBufFreeCnt[3609068] Diff[0]\r
+ nUlBufAllocCnt[929359] nUlBufFreeCnt[928349] Diff[1010]\r
+\r
+ All Tests Completed, Total run 1 Tests, PASS 1 Tests, and FAIL 0 Tests\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-Transport Layer and ORAN Fronthaul Protocol Implementation
-==========================================================
-
-.. contents::
- :depth: 3
- :local:
-
-This chapter describes how the transport layer and ORAN Fronthaul
-protocol are implemented.
-
-.. _introduction-2:
-
-Introduction
-------------
-
-Figure 8 presents an overview of the ORAN Fronthaul process.
-
-.. image:: images/ORAN-Fronthaul-Process.jpg
- :width: 600
- :alt: Figure 8. ORAN Fronthaul Process
-
-Figure 8. ORAN Fronthaul Process
-
-The XRAN library provides support for transporting In-band and
-Quadrature (IQ) samples between the O-DU and O-RU within the xRAN
-architecture based on functional split 7.2x. The library defines the
-xRAN packet formats to be used to transport radio samples within Front
-Haul according to the ORAN Fronthaul specification. It provides
-functionality for generating xRAN packets, appending IQ samples in the
-packet payload, and extracting IQ samples from xRAN packets.
-
-Note: The Bronze release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment.
-
-Note: Regarding the clock model and synchronization topology, configurations
-C1 and C3 of the connection between O-DU and O-RU are the only
-configurations supported in this release of the xRAN implementation.
-
-Note: Quality of PTP synchronization with respect to S-plane of ORAN
-Fronthaul requirements as defined for O-RU is out of the scope of this
-document. PTP primary and PTP secondary configuration are expected to satisfy
-only the O-DU side of requirements and provide the “best-effort” PTP primary for
-O-RU. This may or may not be sufficient for achieving the end to end
-system requirements of S-plane. Specialized dedicated NIC card with
-additional HW functionality might be required to achieve PTP primary
-functionality to satisfy O-RU precision requirements for RAN deployments
-scenarios.
-
-.. image:: images/Configuration-C1.jpg
- :width: 600
- :alt: Figure 9. Configuration C1
-
-Figure 9. Configuration C1
-
-
-.. image:: images/Configuration-C3.jpg
- :width: 600
- :alt: Figure 10. Configuration C3
-
-Figure 10. Configuration C3
-
-Supported Feature Set
----------------------
-
-The ORAN Fronthaul specification defines a list of mandatory
-functionality. Not all features defined as Mandatory for O-DU are
-currently supported to fully extended. The following tables contain
-information on what is available and the level of validation performed
-for this release.
-
-Note. Cells with a red background are listed as mandatory in the
-specification but not supported in this implementation of xRAN.
-
-Table 7. ORAN Mandatory and Optional Feature Support
-
-+-----------------+-----------------+-----------+----------------+
-| Category | Feature | O-DU | Support |
-| | | Support | |
-+=================+=================+===========+================+
-| RU Category | Support for | Mandatory | Y |
-| | CAT-A RU (up to | | |
-| | 8 spatial | | |
-| | streams) | | |
-+-----------------+-----------------+-----------+----------------+
-| | Support for | | Y |
-| | CAT-A RU (> 8 | | |
-| | spatial | | |
-| | streams) | | |
-+-----------------+-----------------+-----------+----------------+
-| | Support for | Mandatory | Y |
-| | CAT-B RU | | |
-| | (precoding in | | |
-| | RU) | | |
-+-----------------+-----------------+-----------+----------------+
-| Beamforming | Beam Index | Mandatory | Y |
-| | based | | |
-+-----------------+-----------------+-----------+----------------+
-| | Real-time BF | Mandatory | Y |
-| | Weights | | |
-+-----------------+-----------------+-----------+----------------+
-| | Real-Time | | N |
-| | Beamforming | | |
-| | Attributes | | |
-+-----------------+-----------------+-----------+----------------+
-| | UE Channel Info | | N |
-+-----------------+-----------------+-----------+----------------+
-| Bandwidth | Programmable | Mandatory | Y |
-| Saving | static-bit-width| | |
-| | Fixed Point IQ | | |
-+-----------------+-----------------+-----------+----------------+
-| | Real-time | | Y |
-| | variable-bit | | |
-| | -width | | |
-+-----------------+-----------------+-----------+----------------+
-| | Compressed IQ | | Y |
-+-----------------+-----------------+-----------+----------------+
-| | Block floating | | Y |
-| | point | | |
-| | compression | | |
-+-----------------+-----------------+-----------+----------------+
-| | Block scaling | | N |
-| | compression | | |
-+-----------------+-----------------+-----------+----------------+
-| | u-law | | N |
-| | compression | | |
-+-----------------+-----------------+-----------+----------------+
-| | modulation | | N |
-| | compression | | |
-+-----------------+-----------------+-----------+----------------+
-| | beamspace | | N |
-| | compression | | |
-+-----------------+-----------------+-----------+----------------+
-| | Variable Bit | | Y |
-| | Width per | | |
-| | Channel (per | | |
-| | data section) | | |
-+-----------------+-----------------+-----------+----------------+
-| | Static | | N |
-| | configuration | | |
-| | of U-Plane IQ | | |
-| | format and | | |
-| | compression | | |
-| | header | | |
-+-----------------+-----------------+-----------+----------------+
-| | Use of “symInc” | | N |
-| | flag to allow | | |
-| | multiple | | |
-| | symbols in a | | |
-| | C-Plane section | | |
-+-----------------+-----------------+-----------+----------------+
-| Energy Saving | Transmission | | N |
-| | blanking | | |
-+-----------------+-----------------+-----------+----------------+
-| O-DU - RU | Pre-configured | Mandatory | Y |
-| Timing | Transport Delay | | |
-| | Method | | |
-+-----------------+-----------------+-----------+----------------+
-| | Measured | | N |
-| | Transport | | |
-| | Method (eCPRI | | |
-| | Msg 5) | | |
-+-----------------+-----------------+-----------+----------------+
-| Synchronization | G.8275.1 | Mandatory | Y (C3 only)|
-| | | | |
-+-----------------+-----------------+-----------+----------------+
-| | G.8275.2 | | N |
-+-----------------+-----------------+-----------+----------------+
-| | GNSS based sync | | N |
-+-----------------+-----------------+-----------+----------------+
-| | SyncE | | N |
-+-----------------+-----------------+-----------+----------------+
-| Transport | L2 : Ethernet | Mandatory | Y |
-| Features | | | |
-+-----------------+-----------------+-----------+----------------+
-| | L3 : IPv4, IPv6 | | N |
-| | (CUS Plane) | | |
-+-----------------+-----------------+-----------+----------------+
-| | QoS over | Mandatory | N |
-| | Fronthaul | | |
-+-----------------+-----------------+-----------+----------------+
-| | Prioritization | | N |
-| | of different | | |
-| | U-plane traffic | | |
-| | types | | |
-+-----------------+-----------------+-----------+----------------+
-| | Support of | | N |
-| | Jumbo Ethernet | | |
-| | frames | | |
-+-----------------+-----------------+-----------+----------------+
-| | eCPRI | Mandatory | Y |
-+-----------------+-----------------+-----------+----------------+
-| | support of | | N |
-| | eCPRI | | |
-| | concatenation | | |
-+-----------------+-----------------+-----------+----------------+
-| | IEEE 1914.3 | | N |
-+-----------------+-----------------+-----------+----------------+
-| | Application | Mandatory | Y |
-| | fragmentation | | |
-+-----------------+-----------------+-----------+----------------+
-| | Transport | | N |
-| | fragmentation | | |
-+-----------------+-----------------+-----------+----------------+
-| Other | LAA LBT O-DU | | N |
-| | Congestion | | |
-| | Window mgmt | | |
-+-----------------+-----------------+-----------+----------------+
-| | LAA LBT RU | | N |
-| | Congestion | | |
-| | Window mgmt | | |
-+-----------------+-----------------+-----------+----------------+
-
-Details on the subset of xRAN functionality implemented are shown in
-Table 8.
-
-Level of Validation Specified as:
-
-
-- C: Completed code implementation for xRAN Library
-
-- I: Integrated into Intel FlexRAN PHY
-
-- T: Tested end to end with O-RU
-
-Table 8. Levels of Validation
-
-+------------+------------+------------+------------+-----+-----+---+
-| Category | Item | Q4 (20.04) | | | | |
-+============+============+============+============+=====+=====+===+
-| | | Status | C | I | T | |
-+------------+------------+------------+------------+-----+-----+---+
-| General | Radio | NR | N/A | N/A | N/A | |
-| | access | | | | | |
-| | technology | | | | | |
-| | (LTE / NR) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Nominal | 15 | Y | Y | N | |
-| | s\ | /30/120KHz | | | | |
-| | ub-carrier | | | | | |
-| | spacing | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | FFT size | 512/1024 | Y | Y | N | |
-| | | /2048/4096 | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Channel | 5/10 | Y | Y | N | |
-| | bandwidth | /20/100Mhz | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Number of | 12 | Y | Y | N | |
-| | the | | | | | |
-| | channel | | | | | |
-| | (Component | | | | | |
-| | Carrier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | RU | A | Y | Y | N | |
-| | category | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | TDD Config | Supporte\ | Y | Y | N | |
-| | | d/Flexible | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | FDD | Supported | Y | Y | N | |
-| | Support | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Tx/Rx | Supported | Y | Y | N | |
-| | switching | | | | | |
-| | based on | | | | | |
-| | 'data | | | | | |
-| | Direction' | | | | | |
-| | field of | | | | | |
-| | C-plane | | | | | |
-| | message | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | IP version | N/A | N/A | N/A | N/A | |
-| | for | | | | | |
-| | Management | | | | | |
-| | traffic at | | | | | |
-| | fronthaul | | | | | |
-| | network | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| PRACH | One Type 3 | Supported | Y | Y | N | |
-| | message | | | | | |
-| | for all | | | | | |
-| | repeated | | | | | |
-| | PRACH | | | | | |
-| | preambles | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Type 3 | 1 | Y | Y | N | |
-| | message | | | | | |
-| | per | | | | | |
-| | repeated | | | | | |
-| | PRACH | | | | | |
-| | preambles | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | timeOffset | Supported | Y | Y | N | |
-| | including | | | | | |
-| | cpLength | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Supported | Supported | Y | Y | N | |
-+------------+------------+------------+------------+-----+-----+---+
-| | PRACH | Supported | Y | Y | N | |
-| | preamble | | | | | |
-| | format / | | | | | |
-| | index | | | | | |
-| | number | | | | | |
-| | (number of | | | | | |
-| | the | | | | | |
-| | occasion) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| Delay | Network | Supported | Y | Y | N | |
-| management | delay | | | | | |
-| | det\ | | | | | |
-| | ermination | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | lls-CU | Supported | Y | Y | N | |
-| | timing | | | | | |
-| | advance | | | | | |
-| | type | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Non-delay | Not | N | N | N | |
-| | managed | supported | | | | |
-| | U-plane | | | | | |
-| | traffic | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| C/U-plane | Transport | Ethernet | Y | Y | N | |
-| Transport | enc\ | | | | | |
-| | apsulation | | | | | |
-| | (Ethernet | | | | | |
-| | / IP) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Jumbo | Supported | Y | Y | N | |
-| | frames | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Transport | eCPRI | Y | Y | N | |
-| | header | | | | | |
-| | (eCPRI / | | | | | |
-| | RoE) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | IP version | N/A | N/A | N/A | N/A | |
-| | when | | | | | |
-| | Transport | | | | | |
-| | header is | | | | | |
-| | IP/UDP | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | eCPRI | Not | N | N | N | |
-| | Con\ | supported | | | | |
-| | catenation | | | | | |
-| | when | | | | | |
-| | Transport | | | | | |
-| | header is | | | | | |
-| | eCPRI | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | eAxC ID | 4 \* | Y | Y | N | |
-| | CU_Port_ID | | | | | |
-| | bitwidth | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | eAxC ID | 4 \* | Y | Y | N | |
-| | Ban\ | | | | | |
-| | dSector_ID | | | | | |
-| | bitwidth | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | eAxC ID | 4 \* | Y | Y | N | |
-| | CC_ID | | | | | |
-| | bitwidth | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | eAxC ID | 4 \* | Y | Y | N | |
-| | RU_Port_ID | | | | | |
-| | bitwidth | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Fra\ | Supported | Y | Y | N | |
-| | gmentation | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Transport | N/A | N | N | N | |
-| | prio\ | | | | | |
-| | ritization | | | | | |
-| | within | | | | | |
-| | U-plane | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Separation | Supported | Y | Y | N | |
-| | of | | | | | |
-| | C/U-plane | | | | | |
-| | and | | | | | |
-| | M-plane | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Separation | VLAN ID | Y | Y | N | |
-| | of C-plane | | | | | |
-| | and | | | | | |
-| | U-plane | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Max Number | 16 | Y | Y | N | |
-| | of VLAN | | | | | |
-| | per | | | | | |
-| | physical | | | | | |
-| | port | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| Reception | Rx_on_time | Supported | Y | Y | N | |
-| Window | | | | | | |
-| Monitoring | | | | | | |
-| (Counters) | | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Rx_early | Supported | N | N | N | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Rx_late | Supported | N | N | N | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Rx_corrupt | Supported | N | N | N | |
-+------------+------------+------------+------------+-----+-----+---+
-| | R\ | Supported | N | N | N | |
-| | x_pkt_dupl | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Total | Supported | Y | N | N | |
-| | _msgs_rcvd | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| B\ | RU | Index and | Y | Y | N | |
-| eamforming | b\ | weights | | | | |
-| | eamforming | | | | | |
-| | type | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | B\ | C-plane | Y | N | N | |
-| | eamforming | | | | | |
-| | control | | | | | |
-| | method | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Number of | No-re | Y | Y | N | |
-| | beams | strictions | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| IQ | U-plane | Supported | Y | Y | Y | |
-| c\ | data | | | | | |
-| ompression | c\ | | | | | |
-| | ompression | | | | | |
-| | method | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | U-plane | BFP: | Y | Y | Y | |
-| | data IQ | 8,9,12,14 | | | | |
-| | bitwidth | bits | | | | |
-| | (Before / | | | | | |
-| | After | | | | | |
-| | co | | | | | |
-| | mpression) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Static | Supported | N | N | N | |
-| | con\ | | | | | |
-| | figuration | | | | | |
-| | of U-plane | | | | | |
-| | IQ format | | | | | |
-| | and | | | | | |
-| | c\ | | | | | |
-| | ompression | | | | | |
-| | header | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| eCPRI | ec\ | 001b | Y | Y | Y | |
-| Header | priVersion | | | | | |
-| Format | | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | ecp\ | Supported | Y | Y | Y | |
-| | riReserved | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | ecpriCon\ | Not | N | N | N | |
-| | catenation | supported | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | ec\ | U-plane | Supported | Y | Y | Y |
-| | priMessage | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | C-plane | Supported | Y | Y | Y |
-+------------+------------+------------+------------+-----+-----+---+
-| | | Delay | Not | N | N | N |
-| | | m\ | supported | | | |
-| | | easurement | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | ec\ | Supported | Y | Y | Y | |
-| | priPayload | | | | | |
-| | (payload | | | | | |
-| | size in | | | | | |
-| | bytes) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | ecpriRtcid | Supported | Y | Y | Y | |
-| | /ecpriPcid | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | e\ | Supported | Y | Y | Y | |
-| | cpriSeqid: | | | | | |
-| | Sequence | | | | | |
-| | ID | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | e\ | Supported | Y | Y | Y | |
-| | cpriSeqid: | | | | | |
-| | E bit | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | e\ | Not | N | N | N | |
-| | cpriSeqid: | supported | | | | |
-| | S\ | | | | | |
-| | ubsequence | | | | | |
-| | ID | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| C-plane | Section | Not | N | N | N | |
-| Type | Type 0 | supported | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Section | Supported | Y | Y | Y | |
-| | Type 1 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Section | Supported | Y | Y | Y | |
-| | Type 3 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Section | Not | N | N | N | |
-| | Type 5 | supported | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Section | Not | N | N | N | |
-| | Type 6 | supported | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Section | Not | N | N | N | |
-| | Type 7 | supported | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| C-plane | *Coding of | dat\ | Supported | Y | Y | N |
-| Packet | I\ | aDirection | | | | |
-| Format | nformation | (data | | | | |
-| | Elements – | direction | | | | |
-| | A\ | (gNB | | | | |
-| | pplication | Tx/Rx)) | | | | |
-| | Layer, | | | | | |
-| | Common* | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | payl\ | 001b | Y | Y | N |
-| | | oadVersion | | | | |
-| | | (payload | | | | |
-| | | version) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | f\ | Supported | Y | Y | N |
-| | | ilterIndex | | | | |
-| | | (filter | | | | |
-| | | index) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | frameId | Supported | Y | Y | N |
-| | | (frame | | | | |
-| | | i\ | | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | subframeId | Supported | Y | Y | N |
-| | | (subframe | | | | |
-| | | i\ | | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | slotId | Supported | Y | Y | N |
-| | | (slot | | | | |
-| | | i\ | | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | sta\ | Supported | Y | Y | N |
-| | | rtSymbolid | | | | |
-| | | (start | | | | |
-| | | symbol | | | | |
-| | | i\ | | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | number | up to the | Y | Y | N |
-| | | Ofsections | maximum | | | |
-| | | (number of | number of | | | |
-| | | sections) | PRBs | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | s\ | 1 and 3 | Y | Y | N |
-| | | ectionType | | | | |
-| | | (section | | | | |
-| | | type) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | udCompHdr | Supported | Y | Y | N |
-| | | (user data | | | | |
-| | | c\ | | | | |
-| | | ompression | | | | |
-| | | header) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | n\ | Not | N | N | N |
-| | | umberOfUEs | supported | | | |
-| | | (number Of | | | | |
-| | | UEs) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | timeOffset | Supported | Y | Y | N |
-| | | (time | | | | |
-| | | offset) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | fram\ | mu=0,1,3 | Y | Y | N |
-| | | eStructure | | | | |
-| | | (frame | | | | |
-| | | structure) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | cpLength | Supported | Y | Y | N |
-| | | (cyclic | | | | |
-| | | prefix | | | | |
-| | | length) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | *Coding of | sectionId | Supported | Y | Y | N |
-| | I\ | (section | | | | |
-| | nformation | i\ | | | | |
-| | Elements – | dentifier) | | | | |
-| | A\ | | | | | |
-| | pplication | | | | | |
-| | Layer, | | | | | |
-| | Sections* | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | rb | 0 | Y | Y | N |
-| | | (resource | | | | |
-| | | block | | | | |
-| | | indicator) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | symInc | 0 or 1 | Y | Y | N |
-| | | (symbol | | | | |
-| | | number | | | | |
-| | | increment | | | | |
-| | | command) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | startPrbc | Supported | Y | Y | N |
-| | | (starting | | | | |
-| | | PRB of | | | | |
-| | | control | | | | |
-| | | section) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | reMask | Supported | Y | Y | N |
-| | | (resource | | | | |
-| | | element | | | | |
-| | | mask) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | numPrbc | Supported | Y | Y | N |
-| | | (number of | | | | |
-| | | contiguous | | | | |
-| | | PRBs per | | | | |
-| | | control | | | | |
-| | | section) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | numSymbol | Supported | Y | Y | N |
-| | | (number of | | | | |
-| | | symbols) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | ef | Supported | Y | Y | N |
-| | | (extension | | | | |
-| | | flag) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | beamId | Support | Y | Y | N |
-| | | (beam | | | | |
-| | | i\ | | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | ueId (UE | Not | N | N | N |
-| | | i\ | supported | | | |
-| | | dentifier) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | freqOffset | Supported | Y | Y | N |
-| | | (frequency | | | | |
-| | | offset) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | regulariza\| Not | N | N | N |
-| | | tionFactor | supported | | | |
-| | | (regu\ | | | | |
-| | | larization | | | | |
-| | | Factor) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | ciIsample, | Not | N | N | N |
-| | | ciQsample | supported | | | |
-| | | (channel | | | | |
-| | | i\ | | | | |
-| | | nformation | | | | |
-| | | I and Q | | | | |
-| | | values) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | laaMsgType | Not | N | N | N |
-| | | (LAA | supported | | | |
-| | | message | | | | |
-| | | type) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | laaMsgLen | Not | N | N | N |
-| | | (LAA | supported | | | |
-| | | message | | | | |
-| | | length) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtHandle | Not | N | N | N |
-| | | | supported | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtD\ | Not | N | N | N |
-| | | eferFactor | supported | | | |
-| | | (listen-b | | | | |
-| | | efore-talk | | | | |
-| | | defer | | | | |
-| | | factor) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtBack | Not | N | N | N |
-| | | offCounter | supported | | | |
-| | | (listen-b\ | | | | |
-| | | efore-talk | | | | |
-| | | backoff | | | | |
-| | | counter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtOffset | Not | N | N | N |
-| | | (listen-b\ | supported | | | |
-| | | efore-talk | | | | |
-| | | offset) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | MCOT | Not | N | N | N |
-| | | (maximum | supported | | | |
-| | | channel | | | | |
-| | | occupancy | | | | |
-| | | time) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtMode | Not | N | N | N |
-| | | (LBT Mode) | supported | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | l\ | Not | N | N | N |
-| | | btPdschRes | supported | | | |
-| | | (LBT PDSCH | | | | |
-| | | Result) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | sfStatus | Not | N | N | N |
-| | | (subframe | supported | | | |
-| | | status) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtDrsRes | Not | N | N | N |
-| | | (LBT DRS | supported | | | |
-| | | Result) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | initia\ | Not | N | N | N |
-| | | lPartialSF | supported | | | |
-| | | (Initial | | | | |
-| | | partial | | | | |
-| | | SF) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtBufErr | Not | N | N | N |
-| | | (LBT | supported | | | |
-| | | Buffer | | | | |
-| | | Error) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | sfnSf | Not | N | N | N |
-| | | (SFN/SF | supported | | | |
-| | | End) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbt | Not | N | N | N |
-| | | CWConfig_H | supported | | | |
-| | | (HARQ | | | | |
-| | | Parameters | | | | |
-| | | for | | | | |
-| | | Congestion | | | | |
-| | | Window | | | | |
-| | | m | | | | |
-| | | anagement) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbt | Not | N | N | N |
-| | | CWConfig_T | supported | | | |
-| | | (TB | | | | |
-| | | Parameters | | | | |
-| | | for | | | | |
-| | | Congestion | | | | |
-| | | Window | | | | |
-| | | m | | | | |
-| | | anagement) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtTr\ | Not | N | N | N |
-| | | afficClass | supported | | | |
-| | | (Traffic | | | | |
-| | | class | | | | |
-| | | priority | | | | |
-| | | for | | | | |
-| | | Congestion | | | | |
-| | | Window | | | | |
-| | | m | | | | |
-| | | anagement) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | lbtCWR_Rst | Not | N | N | N |
-| | | (No | supported | | | |
-| | | tification | | | | |
-| | | about | | | | |
-| | | packet | | | | |
-| | | reception | | | | |
-| | | successful | | | | |
-| | | or not) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | reserved | 0 | N | N | N |
-| | | (reserved | | | | |
-| | | for future | | | | |
-| | | use) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | *Section | | | | |
-| | | Extension | | | | |
-| | | Commands* | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | extType | Supported | Y | Y | N |
-| | | (extension | | | | |
-| | | type) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | ef | Supported | Y | Y | N |
-| | | (extension | | | | |
-| | | flag) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | extLen | Supported | Y | Y | N |
-| | | (extension | | | | |
-| | | length) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Coding of | | | | | |
-| | I\ | | | | | |
-| | nformation | | | | | |
-| | Elements – | | | | | |
-| | A\ | | | | | |
-| | pplication | | | | | |
-| | Layer, | | | | | |
-| | Section | | | | | |
-| | E\ | | | | | |
-| | xtensions | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | *ExtType=1:| bfwCompHdr | Supported | Y | Y | N |
-| | B\ | (beam\ | | | | |
-| | eamforming | forming | | | | |
-| | Weights | weight | | | | |
-| | Extension | c\ | | | | |
-| | Type* | ompression | | | | |
-| | | header) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bf | Supported | Y | Y | N |
-| | | wCompParam | | | | |
-| | | (b\ | | | | |
-| | | eamforming | | | | |
-| | | weight | | | | |
-| | | c\ | | | | |
-| | | ompression | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfwl | Supported | Y | Y | N |
-| | | (b\ | | | | |
-| | | eamforming | | | | |
-| | | weight | | | | |
-| | | in-phase | | | | |
-| | | value) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfwQ | Supported | Y | Y | N |
-| | | (b\ | | | | |
-| | | eamforming | | | | |
-| | | weight | | | | |
-| | | quadrature | | | | |
-| | | value) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfaCompHdr | Not | Y | N | N |
-| | *ExtType=2:| (b\ | supported | | | |
-| | B\ | eamforming | | | | |
-| | eamforming | attributes | | | | |
-| | Attributes | c\ | | | | |
-| | Extension | ompression | | | | |
-| | Type* | header) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfAzPt | Not | Y | N | N |
-| | | (b\ | supported | | | |
-| | | eamforming | | | | |
-| | | azimuth | | | | |
-| | | pointing | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfZePt | Not | Y | N | N |
-| | | (b\ | supported | | | |
-| | | eamforming | | | | |
-| | | zenith | | | | |
-| | | pointing | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfAz3dd | Not | Y | N | N |
-| | | (b | supported | | | |
-| | | eamforming | | | | |
-| | | azimuth | | | | |
-| | | beamwidth | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfZe3dd | Not | Y | N | N |
-| | | (b\ | supported | | | |
-| | | eamforming | | | | |
-| | | zenith | | | | |
-| | | beamwidth | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfAzSl | Not | Y | N | N |
-| | | (b\ | supported | | | |
-| | | eamforming | | | | |
-| | | azimuth | | | | |
-| | | sidelobe | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | bfZeSl | Not | Y | N | N |
-| | | (b\ | supported | | | |
-| | | eamforming | | | | |
-| | | zenith | | | | |
-| | | sidelobe | | | | |
-| | | parameter) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | ze\ | Not | Y | N | N |
-| | | ro-padding | supported | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | cod | Not | N | N | N |
-| | *ExtType=3:| ebookIndex | supported | | | |
-| | DL | (precoder | | | | |
-| | Precoding | codebook | | | | |
-| | Extension | used for | | | | |
-| | Type* | tra | | | | |
-| | | nsmission) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | layerID | Not | N | N | N |
-| | | (Layer ID | supported | | | |
-| | | for DL | | | | |
-| | | tra\ | | | | |
-| | | nsmission) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | txScheme | Not | N | N | N |
-| | | (tr | supported | | | |
-| | | ansmission | | | | |
-| | | scheme) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | numLayers | Not | N | N | N |
-| | | (number of | supported | | | |
-| | | layers | | | | |
-| | | used for | | | | |
-| | | DL | | | | |
-| | | tra\ | | | | |
-| | | nsmission) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | crsReMask | Not | N | N | N |
-| | | (CRS | supported | | | |
-| | | resource | | | | |
-| | | element | | | | |
-| | | mask) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | c | Not | N | N | N |
-| | | rsSyumINum | supported | | | |
-| | | (CRS | | | | |
-| | | symbol | | | | |
-| | | number | | | | |
-| | | i\ | | | | |
-| | | ndication) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | crsShift | Not | N | N | N |
-| | | (crsShift | supported | | | |
-| | | used for | | | | |
-| | | DL | | | | |
-| | | tra\ | | | | |
-| | | nsmission) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | beamIdAP1 | Not | N | N | N |
-| | | (beam id | supported | | | |
-| | | to be used | | | | |
-| | | for | | | | |
-| | | antenna | | | | |
-| | | port 1) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | beamIdAP2 | Not | N | N | N |
-| | | (beam id | supported | | | |
-| | | to be used | | | | |
-| | | for | | | | |
-| | | antenna | | | | |
-| | | port 2) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | beamIdAP3 | Not | N | N | N |
-| | | (beam id | supported | | | |
-| | | to be used | | | | |
-| | | for | | | | |
-| | | antenna | | | | |
-| | | port 3) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | csf | Not | Y | N | N |
-| | *ExtType=4:| (con\ | supported | | | |
-| | Modulation | stellation | | | | |
-| | C\ | shift | | | | |
-| | ompression | flag) | | | | |
-| | Parameters | | | | | |
-| | Extension | | | | | |
-| | Type* | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | mod | Not | Y | N | N |
-| | | CompScaler | supported | | | |
-| | | ( | | | | |
-| | | modulation | | | | |
-| | | c\ | | | | |
-| | | ompression | | | | |
-| | | scaler | | | | |
-| | | value) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | mcS\ | Not | Y | N | N |
-| | *ExtType=5:| caleReMask | supported | | | |
-| | Modulation | ( | | | | |
-| | C\ | modulation | | | | |
-| | ompression | c\ | | | | |
-| | Additional | ompression | | | | |
-| | Parameters | power | | | | |
-| | Extension | scale RE | | | | |
-| | Type* | mask) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | csf | Not | Y | N | N |
-| | | (con\ | supported | | | |
-| | | stellation | | | | |
-| | | shift | | | | |
-| | | flag) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | | mcS | Not | Y | N | N |
-| | | caleOffset | supported | | | |
-| | | (scaling | | | | |
-| | | value for | | | | |
-| | | modulation | | | | |
-| | | co\ | | | | |
-| | | mpression) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| U-plane | dat | Supported | Y | Y | Y | |
-| Packet | aDirection | | | | | |
-| Format | (data | | | | | |
-| | direction | | | | | |
-| | (gNB | | | | | |
-| | Tx/Rx)) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | payl\ | 001b | Y | Y | Y | |
-| | oadVersion | | | | | |
-| | (payload | | | | | |
-| | version) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | f\ | Supported | Y | Y | Y | |
-| | ilterIndex | | | | | |
-| | (filter | | | | | |
-| | index) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | frameId | Supported | Y | Y | Y | |
-| | (frame | | | | | |
-| | i\ | | | | | |
-| | dentifier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | subframeId | Supported | Y | Y | Y | |
-| | (subframe | | | | | |
-| | i\ | | | | | |
-| | dentifier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | slotId | Supported | Y | Y | Y | |
-| | (slot | | | | | |
-| | i | | | | | |
-| | dentifier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | symbolId | Supported | Y | Y | Y | |
-| | (symbol | | | | | |
-| | i\ | | | | | |
-| | dentifier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | sectionId | Supported | Y | Y | Y | |
-| | (section | | | | | |
-| | i\ | | | | | |
-| | dentifier) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | rb | 0 | Y | Y | Y | |
-| | (resource | | | | | |
-| | block | | | | | |
-| | indicator) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | symInc | 0 | Y | Y | Y | |
-| | (symbol | | | | | |
-| | number | | | | | |
-| | increment | | | | | |
-| | command) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | startPrbu | Supported | Y | Y | Y | |
-| | (s\ | | | | | |
-| | tartingPRB | | | | | |
-| | of user | | | | | |
-| | plane | | | | | |
-| | section) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | numPrbu | Supported | Y | Y | Y | |
-| | (number of | | | | | |
-| | PRBs per | | | | | |
-| | user plane | | | | | |
-| | section) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | udCompHdr | Supported | Y | Y | N | |
-| | (user data | | | | | |
-| | c\ | | | | | |
-| | ompression | | | | | |
-| | header) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | reserved | 0 | Y | Y | Y | |
-| | (reserved | | | | | |
-| | for future | | | | | |
-| | use) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | u\ | Supported | Y | Y | N | |
-| | dCompParam | | | | | |
-| | (user data | | | | | |
-| | c\ | | | | | |
-| | ompression | | | | | |
-| | parameter) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | iSample | 16 | Y | Y | Y | |
-| | (in-phase | | | | | |
-| | sample) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | qSample | 16 | Y | Y | Y | |
-| | ( | | | | | |
-| | quadrature | | | | | |
-| | sample) | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| S-plane | Topology | Supported | N | N | N | |
-| | conf\ | | | | | |
-| | iguration: | | | | | |
-| | C1 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Topology | Supported | N | N | N | |
-| | conf\ | | | | | |
-| | iguration: | | | | | |
-| | C2 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Topology | Supported | Y | Y | Y | |
-| | conf\ | | | | | |
-| | iguration: | | | | | |
-| | C3 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | Topology | Supported | N | N | N | |
-| | conf\ | | | | | |
-| | iguration: | | | | | |
-| | C4 | | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| | PTP | Full | Supported | Y | Y | N |
-| | | Timing | | | | |
-| | | Support | | | | |
-| | | (G.8275.1) | | | | |
-+------------+------------+------------+------------+-----+-----+---+
-| M-plane | | | Not | N | N | N |
-| | | | supported | | | |
-+------------+------------+------------+------------+-----+-----+---+
-
-\* The bit width of each component in eAxC ID can be configurable.
-
-Transport Layer
----------------
-
-ORAN Fronthaul data can be transported over Ethernet or IPv4/IPv6. In
-the current implementation, the xRAN library supports only Ethernet with
-VLAN.
-
-.. image:: images/Native-Ethernet-Frame-with-VLAN.jpg
- :width: 600
- :alt: Figure 11. Native Ethernet Frame with VLAN
-
-Figure 11. Native Ethernet Frame with VLAN
-
-
-Standard DPDK routines are used to perform Transport Layer
-functionality.
-
-VLAN tag functionality is offloaded to NIC as per the configuration of
-VF (refer to Appendix Appendix 1).
-
-The transport header is defined in the ORAN Fronthaul specification
-based on the eCPRI specification.
-
-.. image:: images/eCPRI-Header-Field-Definitions.jpg
- :width: 600
- :alt: Figure 12. eCPRI Header Field Definitions
-
-Figure 12. eCPRI Header Field Definitions
-
-Only ECPRI_IQ_DATA = 0x00 and ECPRI_RT_CONTROL_DATA= 0x02 message types
-are supported.
-
-Handling of ecpriRtcid/ecpriPcid Bit field size is configurable and can
-be defined on the initialization stage of the xRAN library.
-
-.. image:: images/Bit-Allocations-of-ecpriRtcid-ecpriPcid.jpg
- :width: 600
- :alt: Figure 13. Bit Allocations of ecpriRtcid/ecpriPcid
-
-Figure 13. Bit Allocations of ecpriRtcid/ecpriPcid
-
-For ecpriSeqid only, the support for a sequence number is implemented.
-The subsequent number is not supported.
-
-U-plane
--------
-
-The following diagrams show xRAN packet protocols’ headers and data
-arrangement with and without compression support.
-
-XRAN packet meant for traffic with compression enabled has the
-Compression Header added after each Application Header. According to
-ORAN Fronthaul's specification, the Compression Header is part of a
-repeated Section Application Header. In the xRAN library implementation,
-the header is implemented as a separate structure, following the
-Application Section Header. As a result, the Compression Header is not
-included in the xRAN packet, if compression is not used.
-
-Figure 14 shows the components of an xRAN packet.
-
-.. image:: images/xRAN-Packet-Components.jpg
- :width: 600
- :alt: Figure 14. xRAN Packet Components
-
-Figure 14. xRAN Packet Components
-
-Radio Application Header
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-The next header is a common header used for time reference.
-
-.. image:: images/Radio-Application-Header.jpg
- :width: 600
- :alt: Figure 15. Radio Application Header
-
-Figure 15. Radio Application Header
-
-The radio application header specific field values are implemented as
-follows:
-
-- filterIndex = 0
-
-- frameId = [0:99]
-
-- subframeId = [0:9]
-
-- slotId = [0:7]
-
-- symbolId = [0:13]
-
-Data Section Application Data Header
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The Common Radio Application Header is followed by the Application
-Header that is repeated for each Data Section within the eCPRI message.
-The relevant section of xRAN packet is shown in color.
-
-.. image:: images/Data-Section-Application-Data-Header.jpg
- :width: 600
- :alt: Figure 16. Data Section Application Data Header
-
-Figure 16. Data Section Application Data Header
-
-
-A single section is used per one Ethernet packet with IQ samples
-startPrbu is equal to 0 and numPrbu is wqual to the number of RBs used:
-
-- rb field is not used (value 0).
-
-- symInc is not used (value 0)
-
-Data Payload
-~~~~~~~~~~~~
-
-An xRAN packet data payload contains a number of PRBs. Each PRB is built
-of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour.
-
-.. image:: images/Data-Payload.jpg
- :width: 600
- :alt: Figure 17. Data Payload
-
-Figure 17. Data Payload
-
-C-plane
--------
-
-C-Plane messages are encapsulated using a two-layered header approach.
-The first layer consists of an eCPRI standard header, including
-corresponding fields used to indicate the message type, while the second
-layer is an application layer including necessary fields for control and
-synchronization. Within the application layer, a “section” defines the characteristics of U-plane data to be transferred or received from a
-beam with one pattern id. In general, the transport header,application
-header, and sections are all intended to be aligned on 4-byte boundaries
-and are transmitted in “network byte order” meaning the most significant
-byte of a multi-byte parameter is transmitted first.
-
-Table 9 is a list of sections currently supported.
-
-Table 9. Section Types
-
-+--------------+--------------------------+--------------------------+
-| Section Type | Target Scenario | Remarks |
-+--------------+--------------------------+--------------------------+
-| 0 | Unused Resource Blocks | Not supported |
-| | or symbols in Downlink | |
-| | or Uplink | |
-+--------------+--------------------------+--------------------------+
-| 1 | Most DL/UL radio | Supported |
-| | channels | |
-+--------------+--------------------------+--------------------------+
-| 2 | reserved for future use | N/A |
-+--------------+--------------------------+--------------------------+
-| 3 | PRACH and | Only PRACH is supported. |
-| | mixed-numerology | Mixed numerology is not |
-| | channels | supported. |
-+--------------+--------------------------+--------------------------+
-| 4 | Reserved for future use | Not supported |
-+--------------+--------------------------+--------------------------+
-| 5 | UE scheduling | Not supported |
-| | information (UE-ID | |
-| | assignment to section) | |
-+--------------+--------------------------+--------------------------+
-| 6 | Channel information | Not supported |
-+--------------+--------------------------+--------------------------+
-| 7 | LAA | Not supported |
-+--------------+--------------------------+--------------------------+
-| 8-255 | Reserved for future use | N/A |
-+--------------+--------------------------+--------------------------+
-
-Section extensions are not supported in this release.
-
-The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h
-and the fields are appropriately re-ordered in order to apply the
-conversion of network byte order after setting values.
-The comments in source code of xRAN lib can be used to see more information on
-implementation specifics of handling sections as well as particular fields.
-Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario.
-
-Ethernet Header
-~~~~~~~~~~~~~~~
-
-Refer to Figure 11.
-
-eCPRI Header
-~~~~~~~~~~~~
-
-Refer to Figure 12.
-
-This header is defined as the structure of xran_ecpri_hdr in
-lib/api/xran_pkt.h.
-
-Radio Application Common Header
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The Radio Application Common Header is used for time reference. Its
-structure is shown in Figure 18.
-
-.. image:: images/Radio-Application-Common-Header.jpg
- :width: 600
- :alt: Figure 18. Radio Application Common Header
-
-Figure 18. Radio Application Common Header
-
-This header is defined as the structure of
-xran_cp_radioapp_common_header in lib/api/xran_pkt_cp.h.
-
-Please note that the payload version in this header is fixed to
-XRAN_PAYLOAD_VER (defined as 1) in this release.
-
-Section Type 0 Structure
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Figure 19 describes the structure of Section Type 0.
-
-.. image:: images/Section-Type-0-Structure.jpg
- :width: 600
- :alt: Figure 19. Section Type 0 Structure
-
-Figure 19. Section Type 0 Structure
-
-In Figure 18 through Figure 22, the color yellow means it is a transport
-header; the color pink is the radio application header; others are
-repeated sections.
-
-Section Type 1 Structure
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Figure 20 describes the structure of Section Type 1.
-
-.. image:: images/Section-Type-1-Structure.jpg
- :width: 600
- :alt: Figure 20. Section Type 1 Structure
-
-Figure 20. Section Type 1 Structure
-
-Section Type 1 message has two additional parameters in addition to
-radio application common header:
-
-- udCompHdr : defined as the structure of xran_radioapp_udComp_header
-
-- reserved : fixed by zero
-
-Section type 1 is defined as the structure of xran_cp_radioapp_section1,
-and this part can be repeated to have multiple sections.
-
-Whole section type 1 message can be described in this summary:
-
-+----------------------------------+
-| xran_cp_radioapp_common_header |
-+==================================+
-| xran_cp_radioapp_section1_header |
-+----------------------------------+
-| xran_cp_radioapp_section1 |
-+----------------------------------+
-| …… |
-+----------------------------------+
-| xran_cp_radioapp_section1 |
-+----------------------------------+
-
-Section Type 3 Structure
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Figure 21 describes the structure of Section Type 3.
-
-.. image:: images/Section-Type-3-Structure.jpg
- :width: 600
- :alt: Figure 21. Section Type 3 Structure
-
-Figure 21. Section Type 3 Structure
-
-Section Type 3 message has below four additional parameters in addition
-to radio application common header.
-
-- timeOffset
-
-- frameStructure: defined as the structure of
- xran_cp_radioapp_frameStructure
-
-- cpLength
-
-- udCompHdr: defined as the structure of xran_radioapp_udComp_header
-
-Section Type 3 is defined as the structure of xran_cp_radioapp_section3
-and this part can be repeated to have multiple sections.
-
-Whole section type 3 message can be described in this summary:
-
-+----------------------------------+
-| xran_cp_radioapp_common_header |
-+==================================+
-| xran_cp_radioapp_section3_header |
-+----------------------------------+
-| xran_cp_radioapp_section3 |
-+----------------------------------+
-| …… |
-+----------------------------------+
-| xran_cp_radioapp_section3 |
-+----------------------------------+
-
-Section Type 5 Structure
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Figure 22 describes the structure of Section Type 5.
-
-.. image:: images/Section-Type-5-Structure.jpg
- :width: 600
- :alt: Figure 22. Section Type 5 Structure
-
-Figure 22. Section Type 5 Structure
-
-
-Section Type 6 Structure
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Figure 23 describes the structure of Section Type 6.
-
-.. image:: images/Section-Type-6-Structure.jpg
- :width: 600
- :alt: Figure 23. Section Type 6 Structure
-
-Figure 23. Section Type 6 Structure
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+.. |br| raw:: html\r
+\r
+ <br />\r
+\r
+Transport Layer and O-RAN Fronthaul Protocol Implementation\r
+===========================================================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+This chapter describes how the transport layer and O-RAN Fronthaul\r
+protocol are implemented.\r
+\r
+.. _introduction-2:\r
+\r
+Introduction\r
+------------\r
+\r
+Figure 8 presents an overview of the O-RAN Fronthaul process.\r
+\r
+.. image:: images/ORAN-Fronthaul-Process.jpg\r
+ :width: 600\r
+ :alt: Figure 8. O-RAN Fronthaul Process\r
+\r
+Figure 8. O-RAN Fronthaul Process\r
+\r
+The XRAN library provides support for transporting In-band and\r
+Quadrature (IQ) samples between the O-DU and O-RU within the xRAN\r
+architecture based on functional split 7.2x. The library defines the\r
+xRAN packet formats to be used to transport radio samples within Front\r
+Haul according to the O-RAN Fronthaul specification. It provides\r
+functionality for generating xRAN packets, appending IQ samples in the\r
+packet payload, and extracting IQ samples from xRAN packets. \r
+\r
+Note: The Bronze release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment.\r
+\r
+Note: Regarding the clock model and synchronization topology, configurations\r
+C1 and C3 of the connection between O-DU and O-RU are the only\r
+configurations supported in this release of the xRAN implementation.\r
+\r
+Note: Quality of PTP synchronization with respect to S-plane of O-RAN \r
+Fronthaul requirements as defined for O-RU is out of the scope of this\r
+document. PTP primary and PTP secondary configuration are expected to satisfy\r
+only the O-DU side of requirements and provide the “best-effort” PTP primary for\r
+O-RU. This may or may not be sufficient for achieving the end to end\r
+system requirements of S-plane. Specialized dedicated NIC card with\r
+additional HW functionality might be required to achieve PTP primary\r
+functionality to satisfy O-RU precision requirements for RAN deployments\r
+scenarios.\r
+\r
+.. image:: images/Configuration-C1.jpg\r
+ :width: 600\r
+ :alt: Figure 9. Configuration C1\r
+\r
+Figure 9. Configuration C1\r
+\r
+\r
+.. image:: images/Configuration-C3.jpg\r
+ :width: 600\r
+ :alt: Figure 10. Configuration C3\r
+\r
+Figure 10. Configuration C3\r
+\r
+Supported Feature Set\r
+---------------------\r
+\r
+The O-RAN Fronthaul specification defines a list of mandatory\r
+functionality. Not all features defined as Mandatory for O-DU are\r
+currently supported to fully extended. The following tables contain\r
+information on what is available and the level of validation performed\r
+for this release.\r
+\r
+Note. Cells with a red background are listed as mandatory in the\r
+specification but not supported in this implementation of xRAN.\r
+\r
+Table 7. ORAN Mandatory and Optional Feature Support\r
+\r
++-----------------+-----------------+-----------+----------------+\r
+| Category | Feature | O-DU | Support |\r
+| | | Support | |\r
++=================+=================+===========+================+\r
+| RU Category | Support for | Mandatory | Y |\r
+| | CAT-A RU (up to | | |\r
+| | 8 spatial | | |\r
+| | streams) | | |\r
+| +-----------------+-----------+----------------+\r
+| | Support for | | Y |\r
+| | CAT-A RU (> 8 | | |\r
+| | spatial | | |\r
+| | streams) | | |\r
+| +-----------------+-----------+----------------+\r
+| | Support for | Mandatory | Y |\r
+| | CAT-B RU | | |\r
+| | (precoding in | | |\r
+| | RU) | | |\r
++-----------------+-----------------+-----------+----------------+\r
+| Beamforming | Beam Index | Mandatory | Y |\r
+| | based | | |\r
+| +-----------------+-----------+----------------+\r
+| | Real-time BF | Mandatory | Y |\r
+| | Weights | | |\r
+| +-----------------+-----------+----------------+\r
+| | Real-Time | | N |\r
+| | Beamforming | | |\r
+| | Attributes | | |\r
+| +-----------------+-----------+----------------+\r
+| | UE Channel Info | | N |\r
++-----------------+-----------------+-----------+----------------+\r
+| Bandwidth | Programmable | Mandatory | Y |\r
+| Saving | static-bit-width| | |\r
+| | Fixed Point IQ | | |\r
+| +-----------------+-----------+----------------+\r
+| | Real-time | | Y |\r
+| | variable-bit | | |\r
+| | -width | | |\r
+| +-----------------+-----------+----------------+\r
+| | Compressed IQ | | Y |\r
+| +-----------------+-----------+----------------+\r
+| | Block floating | | Y |\r
+| | point | | |\r
+| | compression | | |\r
+| +-----------------+-----------+----------------+\r
+| | Block scaling | | N |\r
+| | compression | | |\r
+| +-----------------+-----------+----------------+\r
+| | u-law | | N |\r
+| | compression | | |\r
+| +-----------------+-----------+----------------+\r
+| | modulation | | Y |\r
+| | compression | | |\r
+| +-----------------+-----------+----------------+\r
+| | beamspace | | Y |\r
+| | compression | | |\r
+| +-----------------+-----------+----------------+\r
+| | Variable Bit | | Y |\r
+| | Width per | | |\r
+| | Channel (per | | |\r
+| | data section) | | |\r
+| +-----------------+-----------+----------------+\r
+| | Static | | N |\r
+| | configuration | | |\r
+| | of U-Plane IQ | | |\r
+| | format and | | |\r
+| | compression | | |\r
+| | header | | |\r
+| +-----------------+-----------+----------------+\r
+| | Use of “symInc” | | N |\r
+| | flag to allow | | |\r
+| | multiple | | |\r
+| | symbols in a | | |\r
+| | C-Plane section | | |\r
++-----------------+-----------------+-----------+----------------+\r
+| Energy Saving | Transmission | | N |\r
+| | blanking | | |\r
++-----------------+-----------------+-----------+----------------+\r
+| O-DU - RU | Pre-configured | Mandatory | Y |\r
+| Timing | Transport Delay | | |\r
+| | Method | | |\r
+| +-----------------+-----------+----------------+\r
+| | Measured | | N |\r
+| | Transport | | |\r
+| | Method (eCPRI | | |\r
+| | Msg 5) | | |\r
++-----------------+-----------------+-----------+----------------+\r
+| Synchronization | G.8275.1 | Mandatory | Y (C3 only)|\r
+| | | | |\r
+| +-----------------+-----------+----------------+\r
+| | G.8275.2 | | N |\r
+| +-----------------+-----------+----------------+\r
+| | GNSS based sync | | N |\r
+| +-----------------+-----------+----------------+\r
+| | SyncE | | N |\r
++-----------------+-----------------+-----------+----------------+\r
+| Transport | L2 : Ethernet | Mandatory | Y |\r
+| Features | | | |\r
+| +-----------------+-----------+----------------+\r
+| | L3 : IPv4, IPv6 | | N |\r
+| | (CUS Plane) | | |\r
+| +-----------------+-----------+----------------+\r
+| | QoS over | Mandatory | Y |\r
+| | Fronthaul | | |\r
+| +-----------------+-----------+----------------+\r
+| | Prioritization | | N |\r
+| | of different | | |\r
+| | U-plane traffic | | |\r
+| | types | | |\r
+| +-----------------+-----------+----------------+\r
+| | Support of | | N |\r
+| | Jumbo Ethernet | | |\r
+| | frames | | |\r
+| +-----------------+-----------+----------------+\r
+| | eCPRI | Mandatory | Y |\r
+| +-----------------+-----------+----------------+\r
+| | support of | | N |\r
+| | eCPRI | | |\r
+| | concatenation | | |\r
+| +-----------------+-----------+----------------+\r
+| | IEEE 1914.3 | | N |\r
+| +-----------------+-----------+----------------+\r
+| | Application | Mandatory | Y |\r
+| | fragmentation | | |\r
+| +-----------------+-----------+----------------+\r
+| | Transport | | N |\r
+| | fragmentation | | |\r
++-----------------+-----------------+-----------+----------------+\r
+| Other | LAA LBT O-DU | | N |\r
+| | Congestion | | |\r
+| | Window mgmt | | |\r
+| +-----------------+-----------+----------------+\r
+| | LAA LBT RU | | N |\r
+| | Congestion | | |\r
+| | Window mgmt | | |\r
++-----------------+-----------------+-----------+----------------+\r
+\r
+Details on the subset of O-RAN functionality implemented are shown in\r
+Table 8.\r
+\r
+Level of Validation Specified as:\r
+\r
+\r
+- C: Completed code implementation for xRAN Library\r
+\r
+- I: Integrated into Intel FlexRAN PHY\r
+\r
+- T: Tested end to end with O-RU\r
+\r
+Table 8. Levels of Validation\r
+\r
++------------+------------+------------+------------+-----+-----+-----+\r
+| Category | Item | Status | C | I | T |\r
++============+============+============+============+=====+=====+=====+\r
+| General | Radio | NR | N/A | N/A | N/A |\r
+| | access | | | | |\r
+| | technology | | | | |\r
+| | (LTE / NR) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | Nominal | 15 | Y | Y | N | \r
+| | s\ | /30/120KHz | | | | \r
+| | ub-carrier | | | | |\r
+| | spacing | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | FFT size | 512/1024 | Y | Y | N |\r
+| | | /2048/4096 | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | Channel | 5/10 | Y | Y | N |\r
+| | bandwidth | /20/100Mhz | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | Number of | 12 | Y | Y | N | \r
+| | the | | | | | \r
+| | channel | | | | |\r
+| | (Component | | | | |\r
+| | Carrier) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | RU | A | Y | Y | N |\r
+| | category | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | TDD Config | Supporte\ | Y | Y | N |\r
+| | | d/Flexible | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | FDD | Supported | Y | Y | N |\r
+| | Support | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | Tx/Rx | Supported | Y | Y | N | \r
+| | switching | | | | | \r
+| | based on | | | | |\r
+| | 'data | | | | |\r
+| | Direction' | | | | |\r
+| | field of | | | | |\r
+| | C-plane | | | | |\r
+| | message | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | IP version | N/A | N/A | N/A | N/A | \r
+| | for | | | | | \r
+| | Management | | | | | \r
+| | traffic at | | | | | \r
+| | fronthaul | | | | | \r
+| | network | | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| PRACH | One Type 3 | Supported | Y | Y | N | \r
+| | message | | | | | \r
+| | for all | | | | | \r
+| | repeated | | | | | \r
+| | PRACH | | | | | \r
+| | preambles | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Type 3 | 1 | Y | Y | N | \r
+| | message | | | | | \r
+| | per | | | | | \r
+| | repeated | | | | | \r
+| | PRACH | | | | | \r
+| | preambles | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | timeOffset | Supported | Y | Y | N | \r
+| | including | | | | | \r
+| | cpLength | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Supported | Supported | Y | Y | N | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | PRACH | Supported | Y | Y | N | \r
+| | preamble | | | | |\r
+| | format / | | | | |\r
+| | index | | | | |\r
+| | number | | | | |\r
+| | (number of | | | | |\r
+| | the | | | | |\r
+| | occasion) | | | | |\r
++------------+-------------------------+------------+-----+-----+-----+\r
+| Delay | Network | Supported | Y | Y | N | \r
+| management | delay | | | | | \r
+| | det\ | | | | | \r
+| | ermination | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | lls-CU | Supported | Y | Y | N | \r
+| | timing | | | | | \r
+| | advance | | | | | \r
+| | type | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Non-delay | Not | N | N | N | \r
+| | managed | supported | | | | \r
+| | U-plane | | | | | \r
+| | traffic | | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| C/U-plane | Transport | Ethernet | Y | Y | N |\r
+| Transport | enc\ | | | | | \r
+| | apsulation | | | | |\r
+| | (Ethernet | | | | |\r
+| | / IP) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Jumbo | Supported | Y | Y | N |\r
+| | frames | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Transport | eCPRI | Y | Y | N | \r
+| | header | | | | | \r
+| | (eCPRI / | | | | | \r
+| | RoE) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | IP version | N/A | N/A | N/A | N/A |\r
+| | when | | | | | \r
+| | Transport | | | | | \r
+| | header is | | | | |\r
+| | IP/UDP | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | eCPRI | Not | N | N | N | \r
+| | Con\ | supported | | | | \r
+| | catenation | | | | | \r
+| | when | | | | | \r
+| | Transport | | | | | \r
+| | header is | | | | | \r
+| | eCPRI | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | eAxC ID | 4 \* | Y | Y | N | \r
+| | CU_Port_ID | | | | | \r
+| | bitwidth | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | eAxC ID | 4 \* | Y | Y | N | \r
+| | Ban\ | | | | | \r
+| | dSector_ID | | | | | \r
+| | bitwidth | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | eAxC ID | 4 \* | Y | Y | N | \r
+| | CC_ID | | | | | \r
+| | bitwidth | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | eAxC ID | 4 \* | Y | Y | N | \r
+| | RU_Port_ID | | | | | \r
+| | bitwidth | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Fra\ | Supported | Y | Y | N | \r
+| | gmentation | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Transport | N/A | N | N | N | \r
+| | prio\ | | | | | \r
+| | ritization | | | | | \r
+| | within | | | | | \r
+| | U-plane | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Separation | Supported | Y | Y | N | \r
+| | of | | | | | \r
+| | C/U-plane | | | | | \r
+| | and | | | | | \r
+| | M-plane | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Separation | VLAN ID | Y | Y | N | \r
+| | of C-plane | | | | | \r
+| | and | | | | | \r
+| | U-plane | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Max Number | 16 | Y | Y | N | \r
+| | of VLAN | | | | | \r
+| | per | | | | | \r
+| | physical | | | | | \r
+| | port | | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| Reception | Rx_on_time | Supported | Y | Y | N | \r
+| Window | | | | | | \r
+| Monitoring | | | | | | \r
+| (Counters) | | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Rx_early | Supported | N | N | N | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Rx_late | Supported | N | N | N | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Rx_corrupt | Supported | N | N | N | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | R\ | Supported | N | N | N | \r
+| | x_pkt_dupl | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Total | Supported | Y | N | N | \r
+| | _msgs_rcvd | | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| B\ | RU | Index and | Y | Y | N | \r
+| eamforming | b\ | weights | | | | \r
+| | eamforming | | | | | \r
+| | type | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | B\ | C-plane | Y | N | N | \r
+| | eamforming | | | | | \r
+| | control | | | | | \r
+| | method | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Number of | No-re | Y | Y | N | \r
+| | beams | strictions | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| IQ | U-plane | Supported | Y | Y | Y | \r
+| c\ | data | | | | | \r
+| ompression | c\ | | | | | \r
+| | ompression | | | | | \r
+| | method | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | U-plane | BFP: | Y | Y | Y | \r
+| | data IQ | 8,9,12,14 | | | | \r
+| | bitwidth | bits | | | | \r
+| | (Before / | | | | | \r
+| | After | | | | | \r
+| | co | | | | | \r
+| | mpression) | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Static | Supported | N | N | N | \r
+| | con\ | | | | | \r
+| | figuration | | | | | \r
+| | of U-plane | | | | | \r
+| | IQ format | | | | | \r
+| | and | | | | | \r
+| | c\ | | | | | \r
+| | ompression | | | | | \r
+| | header | | | | | \r
++------------+-------------------------+------------+-----+-----+-----+\r
+| eCPRI | ec\ | 001b | Y | Y | Y |\r
+| Header | priVersion | | | | | \r
+| Format | | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | ecp\ | Supported | Y | Y | Y | \r
+| | riReserved | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | ecpriCon\ | Not | N | N | N | \r
+| | catenation | supported | | | | \r
+| +------------+------------+------------+-----+-----+-----+\r
+| | ec\ | U-plane | Supported | Y | Y | Y |\r
+| | priMessage | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | C-plane | Supported | Y | Y | Y |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | Delay | Supported | Y | Y | Y |\r
+| | | m\ | | | | |\r
+| | | easurement | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | ec\ | Supported | Y | Y | Y | \r
+| | priPayload | | | | | \r
+| | (payload | | | | | \r
+| | size in | | | | | \r
+| | bytes) | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | ecpriRtcid | Supported | Y | Y | Y |\r
+| | /ecpriPcid | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | e\ | Supported | Y | Y | Y | \r
+| | cpriSeqid: | | | | | \r
+| | Sequence | | | | |\r
+| | ID | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | e\ | Supported | Y | Y | Y | \r
+| | cpriSeqid: | | | | | \r
+| | E bit | | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | e\ | Not | N | N | N | \r
+| | cpriSeqid: | supported | | | | \r
+| | S\ | | | | | \r
+| | ubsequence | | | | | \r
+| | ID | | | | | \r
++------------+------------+------------+------------+-----+-----+-----+\r
+| C-plane | Section | Not | N | N | N |\r
+| Type | Type 0 | supported | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Section | Supported | Y | Y | Y |\r
+| | Type 1 | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Section | Supported | Y | Y | Y | \r
+| | Type 3 | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Section | Not | N | N | N |\r
+| | Type 5 | supported | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Section | Not | N | N | N | \r
+| | Type 6 | supported | | | | \r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Section | Not | N | N | N | \r
+| | Type 7 | supported | | | |\r
++------------+------------+------------+------------+-----+-----+-----+\r
+| C-plane | *Coding of | dat\ | Supported | Y | Y | N |\r
+| Packet | I\ | aDirection | | | | |\r
+| Format | nformation | (data | | | | |\r
+| | Elements – | direction | | | | |\r
+| | A\ | (gNB | | | | |\r
+| | pplication | Tx/Rx)) | | | | |\r
+| | Layer, | | | | | |\r
+| | Common* | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | payl\ | 001b | Y | Y | N |\r
+| | | oadVersion | | | | |\r
+| | | (payload | | | | |\r
+| | | version) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | f\ | Supported | Y | Y | N |\r
+| | | ilterIndex | | | | |\r
+| | | (filter | | | | |\r
+| | | index) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | frameId | Supported | Y | Y | N |\r
+| | | (frame | | | | |\r
+| | | i\ | | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | subframeId | Supported | Y | Y | N |\r
+| | | (subframe | | | | |\r
+| | | i\ | | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | slotId | Supported | Y | Y | N |\r
+| | | (slot | | | | |\r
+| | | i\ | | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | sta\ | Supported | Y | Y | N |\r
+| | | rtSymbolid | | | | |\r
+| | | (start | | | | |\r
+| | | symbol | | | | |\r
+| | | i\ | | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | number | up to the | Y | Y | N |\r
+| | | Ofsections | maximum | | | |\r
+| | | (number of | number of | | | | \r
+| | | sections) | PRBs | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | s\ | 1 and 3 | Y | Y | N |\r
+| | | ectionType | | | | |\r
+| | | (section | | | | |\r
+| | | type) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | udCompHdr | Supported | Y | Y | N |\r
+| | | (user data | | | | |\r
+| | | c\ | | | | |\r
+| | | ompression | | | | |\r
+| | | header) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | n\ | Not | N | N | N |\r
+| | | umberOfUEs | supported | | | |\r
+| | | (number Of | | | | |\r
+| | | UEs) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | timeOffset | Supported | Y | Y | N |\r
+| | | (time | | | | |\r
+| | | offset) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | fram\ | mu=0,1,3 | Y | Y | N |\r
+| | | eStructure | | | | |\r
+| | | (frame | | | | |\r
+| | | structure) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | cpLength | Supported | Y | Y | N |\r
+| | | (cyclic | | | | |\r
+| | | prefix | | | | |\r
+| | | length) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | *Coding of | sectionId | Supported | Y | Y | N |\r
+| | I\ | (section | | | | |\r
+| | nformation | i\ | | | | |\r
+| | Elements – | dentifier) | | | | |\r
+| | A\ | | | | | |\r
+| | pplication | | | | | |\r
+| | Layer, | | | | | |\r
+| | Sections* | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | rb | 0 | Y | Y | N |\r
+| | | (resource | | | | |\r
+| | | block | | | | |\r
+| | | indicator) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | symInc | 0 or 1 | Y | Y | N |\r
+| | | (symbol | | | | |\r
+| | | number | | | | |\r
+| | | increment | | | | |\r
+| | | command) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | startPrbc | Supported | Y | Y | N |\r
+| | | (starting | | | | |\r
+| | | PRB of | | | | |\r
+| | | control | | | | |\r
+| | | section) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | reMask | Supported | Y | Y | N |\r
+| | | (resource | | | | |\r
+| | | element | | | | |\r
+| | | mask) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | numPrbc | Supported | Y | Y | N |\r
+| | | (number of | | | | |\r
+| | | contiguous | | | | |\r
+| | | PRBs per | | | | |\r
+| | | control | | | | |\r
+| | | section) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | numSymbol | Supported | Y | Y | N |\r
+| | | (number of | | | | |\r
+| | | symbols) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | ef | Supported | Y | Y | N |\r
+| | | (extension | | | | |\r
+| | | flag) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | beamId | Support | Y | Y | N |\r
+| | | (beam | | | | |\r
+| | | i\ | | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | ueId (UE | Not | N | N | N |\r
+| | | i\ | supported | | | |\r
+| | | dentifier) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | freqOffset | Supported | Y | Y | N |\r
+| | | (frequency | | | | |\r
+| | | offset) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | regulariza\| Not | N | N | N |\r
+| | | tionFactor | supported | | | |\r
+| | | (regu\ | | | | |\r
+| | | larization | | | | |\r
+| | | Factor) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | ciIsample, | Not | N | N | N |\r
+| | | ciQsample | supported | | | |\r
+| | | (channel | | | | |\r
+| | | i\ | | | | |\r
+| | | nformation | | | | |\r
+| | | I and Q | | | | |\r
+| | | values) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | laaMsgType | Not | N | N | N |\r
+| | | (LAA | supported | | | |\r
+| | | message | | | | |\r
+| | | type) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | laaMsgLen | Not | N | N | N |\r
+| | | (LAA | supported | | | |\r
+| | | message | | | | |\r
+| | | length) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtHandle | Not | N | N | N |\r
+| | | | supported | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtD\ | Not | N | N | N |\r
+| | | eferFactor | supported | | | |\r
+| | | (listen-b | | | | |\r
+| | | efore-talk | | | | |\r
+| | | defer | | | | |\r
+| | | factor) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtBack | Not | N | N | N |\r
+| | | offCounter | supported | | | |\r
+| | | (listen-b\ | | | | |\r
+| | | efore-talk | | | | |\r
+| | | backoff | | | | |\r
+| | | counter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtOffset | Not | N | N | N |\r
+| | | (listen-b\ | supported | | | |\r
+| | | efore-talk | | | | |\r
+| | | offset) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | MCOT | Not | N | N | N |\r
+| | | (maximum | supported | | | |\r
+| | | channel | | | | |\r
+| | | occupancy | | | | |\r
+| | | time) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtMode | Not | N | N | N |\r
+| | | (LBT Mode) | supported | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | l\ | Not | N | N | N |\r
+| | | btPdschRes | supported | | | |\r
+| | | (LBT PDSCH | | | | |\r
+| | | Result) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | sfStatus | Not | N | N | N |\r
+| | | (subframe | supported | | | |\r
+| | | status) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtDrsRes | Not | N | N | N |\r
+| | | (LBT DRS | supported | | | |\r
+| | | Result) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | initia\ | Not | N | N | N |\r
+| | | lPartialSF | supported | | | |\r
+| | | (Initial | | | | |\r
+| | | partial | | | | |\r
+| | | SF) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtBufErr | Not | N | N | N |\r
+| | | (LBT | supported | | | |\r
+| | | Buffer | | | | |\r
+| | | Error) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | sfnSf | Not | N | N | N |\r
+| | | (SFN/SF | supported | | | |\r
+| | | End) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbt | Not | N | N | N |\r
+| | | CWConfig_H | supported | | | |\r
+| | | (HARQ | | | | |\r
+| | | Parameters | | | | |\r
+| | | for | | | | |\r
+| | | Congestion | | | | |\r
+| | | Window | | | | |\r
+| | | m | | | | |\r
+| | | anagement) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbt | Not | N | N | N |\r
+| | | CWConfig_T | supported | | | |\r
+| | | (TB | | | | |\r
+| | | Parameters | | | | |\r
+| | | for | | | | |\r
+| | | Congestion | | | | |\r
+| | | Window | | | | |\r
+| | | m | | | | |\r
+| | | anagement) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtTr\ | Not | N | N | N |\r
+| | | afficClass | supported | | | |\r
+| | | (Traffic | | | | |\r
+| | | class | | | | |\r
+| | | priority | | | | |\r
+| | | for | | | | |\r
+| | | Congestion | | | | |\r
+| | | Window | | | | |\r
+| | | m | | | | |\r
+| | | anagement) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | lbtCWR_Rst | Not | N | N | N |\r
+| | | (No | supported | | | |\r
+| | | tification | | | | |\r
+| | | about | | | | |\r
+| | | packet | | | | |\r
+| | | reception | | | | |\r
+| | | successful | | | | |\r
+| | | or not) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | reserved | 0 | N | N | N |\r
+| | | (reserved | | | | |\r
+| | | for future | | | | |\r
+| | | use) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | *Section | | | | |\r
+| | | Extension | | | | |\r
+| | | Commands* | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | extType | Supported | Y | Y | N |\r
+| | | (extension | | | | |\r
+| | | type) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | ef | Supported | Y | Y | N |\r
+| | | (extension | | | | |\r
+| | | flag) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | extLen | Supported | Y | Y | N |\r
+| | | (extension | | | | |\r
+| | | length) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | Coding of | | | | | |\r
+| | I\ | | | | | |\r
+| | nformation | | | | | |\r
+| | Elements – | | | | | |\r
+| | A\ | | | | | |\r
+| | pplication | | | | | |\r
+| | Layer, | | | | | |\r
+| | Section | | | | | |\r
+| | E\ | | | | | |\r
+| | xtensions | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | *ExtType=1:| bfwCompHdr | Supported | Y | Y | N |\r
+| | B\ | (beam\ | | | | |\r
+| | eamforming | forming | | | | |\r
+| | Weights | weight | | | | |\r
+| | Extension | c\ | | | | |\r
+| | Type* | ompression | | | | |\r
+| | | header) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bf | Supported | Y | Y | N |\r
+| | | wCompParam | | | | |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | weight | | | | |\r
+| | | c\ | | | | |\r
+| | | ompression | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfwl | Supported | Y | Y | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | weight | | | | |\r
+| | | in-phase | | | | |\r
+| | | value) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfwQ | Supported | Y | Y | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | weight | | | | |\r
+| | | quadrature | | | | |\r
+| | | value) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | | bfaCompHdr | Supported | Y | N | N |\r
+| | *ExtType=2:| (b\ | | | | |\r
+| | B\ | eamforming | | | | |\r
+| | eamforming | attributes | | | | |\r
+| | Attributes | c\ | | | | |\r
+| | Extension | ompression | | | | |\r
+| | Type* | header) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfAzPt | Supported | Y | N | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | azimuth | | | | |\r
+| | | pointing | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfZePt | Supported | Y | N | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | zenith | | | | |\r
+| | | pointing | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfAz3dd | Supported | Y | N | N |\r
+| | | (b | | | | |\r
+| | | eamforming | | | | |\r
+| | | azimuth | | | | |\r
+| | | beamwidth | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfZe3dd | Supported | Y | N | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | zenith | | | | |\r
+| | | beamwidth | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfAzSl | Supported | Y | N | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | azimuth | | | | |\r
+| | | sidelobe | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfZeSl | Supported | Y | N | N |\r
+| | | (b\ | | | | |\r
+| | | eamforming | | | | |\r
+| | | zenith | | | | |\r
+| | | sidelobe | | | | |\r
+| | | parameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | ze\ | Supported | Y | N | N |\r
+| | | ro-padding | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | | cod | Supported | Y | N | N |\r
+| | *ExtType=3:| ebookIndex | | | | |\r
+| | DL | (precoder | | | | |\r
+| | Precoding | codebook | | | | |\r
+| | Extension | used for | | | | |\r
+| | Type* | tra | | | | |\r
+| | | nsmission) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | layerID | Supported | Y | N | N |\r
+| | | (Layer ID | | | | |\r
+| | | for DL | | | | |\r
+| | | tra\ | | | | |\r
+| | | nsmission) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | txScheme | Supported | Y | N | N |\r
+| | | (tr | | | | |\r
+| | | ansmission | | | | |\r
+| | | scheme) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | numLayers | Supported | Y | N | N |\r
+| | | (number of | | | | |\r
+| | | layers | | | | |\r
+| | | used for | | | | |\r
+| | | DL | | | | |\r
+| | | tra\ | | | | |\r
+| | | nsmission) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | crsReMask | Supported | Y | N | N |\r
+| | | (CRS | | | | |\r
+| | | resource | | | | |\r
+| | | element | | | | |\r
+| | | mask) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | c | Supported | Y | N | N |\r
+| | | rsSyumINum | | | | |\r
+| | | (CRS | | | | |\r
+| | | symbol | | | | |\r
+| | | number | | | | |\r
+| | | i\ | | | | |\r
+| | | ndication) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | crsShift | Supported | Y | N | N |\r
+| | | (crsShift | | | | |\r
+| | | used for | | | | |\r
+| | | DL | | | | |\r
+| | | tra\ | | | | |\r
+| | | nsmission) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | beamIdAP1 | Supported | Y | N | N |\r
+| | | (beam id | | | | |\r
+| | | to be used | | | | |\r
+| | | for | | | | |\r
+| | | antenna | | | | |\r
+| | | port 1) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | beamIdAP2 | Supported | Y | N | N |\r
+| | | (beam id | | | | |\r
+| | | to be used | | | | |\r
+| | | for | | | | |\r
+| | | antenna | | | | |\r
+| | | port 2) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | beamIdAP3 | Supported | Y | N | N |\r
+| | | (beam id | | | | |\r
+| | | to be used | | | | |\r
+| | | for | | | | |\r
+| | | antenna | | | | |\r
+| | | port 3) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | | csf | Supported | Y | Y | N |\r
+| | *ExtType=4:| (con\ | | | | |\r
+| | Modulation | stellation | | | | |\r
+| | C\ | shift | | | | |\r
+| | ompression | flag) | | | | |\r
+| | Parameters | | | | | |\r
+| | Extension | | | | | |\r
+| | Type* | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | mod | Supported | Y | Y | N |\r
+| | | CompScaler | | | | |\r
+| | | ( | | | | |\r
+| | | modulation | | | | |\r
+| | | c\ | | | | |\r
+| | | ompression | | | | |\r
+| | | scaler | | | | |\r
+| | | value) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | | mcS\ | Supported | Y | N | N |\r
+| | *ExtType=5:| caleReMask | | | | |\r
+| | Modulation | ( | | | | |\r
+| | C\ | modulation | | | | |\r
+| | ompression | c\ | | | | |\r
+| | Additional | ompression | | | | |\r
+| | Parameters | power | | | | |\r
+| | Extension | scale RE | | | | |\r
+| | Type* | mask) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | csf | Supported | Y | N | N |\r
+| | | (con\ | | | | |\r
+| | | stellation | | | | |\r
+| | | shift | | | | |\r
+| | | flag) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | mcS | Supported | Y | N | N |\r
+| | | caleOffset | | | | |\r
+| | | (scaling | | | | |\r
+| | | value for | | | | |\r
+| | | modulation | | | | |\r
+| | | co\ | | | | |\r
+| | | mpression) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | *E | rbgSize | Supported | Y | N | N |\r
+| | xtType=6: | (resource | | | | |\r
+| | Non-c | block | | | | |\r
+| | ontiguous | group | | | | |\r
+| | PRB | size) | | | | |\r
+| | a | | | | | |\r
+| | llocation | | | | | |\r
+| | in time | | | | | |\r
+| | and | | | | | |\r
+| | frequency | | | | | |\r
+| | domain* | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | rbgMask | Supported | Y | N | N |\r
+| | | (resource | | | | |\r
+| | | block | | | | |\r
+| | | group bit | | | | |\r
+| | | mask) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | s | Supported | Y | N | N |\r
+| | | ymbolMask | | | | |\r
+| | | (symbol | | | | |\r
+| | | bit mask) | | | | |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | *Ex | beam | Supported | Y | N | N |\r
+| | tType=10: | GroupType | | | | |\r
+| | Section | | | | | |\r
+| | de | | | | | |\r
+| | scription | | | | | |\r
+| | for group | | | | | |\r
+| | conf | | | | | |\r
+| | iguration | | | | | |\r
+| | of | | | | | |\r
+| | multiple | | | | | |\r
+| | ports* | | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | numPortc | Supported | Y | N | N |\r
+| +------------+------------+------------+-----+-----+-----+\r
+| | *Ex | b | Supported | Y | Y | N |\r
+| | tType=11: | fwCompHdr | | | | |\r
+| | Flexible | (be | | | | |\r
+| | Be | amforming | | | | |\r
+| | amforming | weight | | | | |\r
+| | Weights | co | | | | |\r
+| | Extension | mpression | | | | |\r
+| | Type* | header) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfw | Supported | Y | Y | N |\r
+| | | CompParam | | | | |\r
+| | | for PRB | | | | |\r
+| | | bundle x | | | | |\r
+| | | (be | | | | |\r
+| | | amforming | | | | |\r
+| | | weight | | | | |\r
+| | | co | | | | |\r
+| | | mpression | | | | |\r
+| | | p | | | | |\r
+| | | arameter) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | n | Supported | Y | Y | N |\r
+| | | umBundPrb | | | | |\r
+| | | (Number | | | | |\r
+| | | of | | | | |\r
+| | | bundled | | | | |\r
+| | | PRBs per | | | | |\r
+| | | be | | | | |\r
+| | | amforming | | | | |\r
+| | | weights) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfwI | Supported | Y | Y | N |\r
+| | | (be | | | | |\r
+| | | amforming | | | | |\r
+| | | weight | | | | |\r
+| | | in-phase | | | | |\r
+| | | value) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | bfwQ | Supported | Y | Y | N |\r
+| | | (be | | | | |\r
+| | | amforming | | | | |\r
+| | | weight | | | | |\r
+| | | q | | | | |\r
+| | | uadrature | | | | |\r
+| | | value) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | di | Supported | Y | Y | N |\r
+| | | sableBFWs | | | | |\r
+| | | (disable | | | | |\r
+| | | be | | | | |\r
+| | | amforming | | | | |\r
+| | | weights) | | | | |\r
+| | +------------+------------+-----+-----+-----+\r
+| | | RAD | Supported | Y | Y | N |\r
+| | | (Reset | | | | |\r
+| | | After PRB | | | | |\r
+| | | Disco | | | | |\r
+| | | ntinuity) | | | | |\r
++------------+------------+------------+------------+-----+-----+-----+\r
+| U-plane | dat | Supported | Y | Y | Y | \r
+| Packet | aDirection | | | | |\r
+| Format | (data | | | | |\r
+| | direction | | | | | \r
+| | (gNB | | | | |\r
+| | Tx/Rx)) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | payl\ | 001b | Y | Y | Y | \r
+| | oadVersion | | | | |\r
+| | (payload | | | | |\r
+| | version) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | f\ | Supported | Y | Y | Y |\r
+| | ilterIndex | | | | |\r
+| | (filter | | | | |\r
+| | index) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | frameId | Supported | Y | Y | Y | \r
+| | (frame | | | | |\r
+| | i\ | | | | |\r
+| | dentifier) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | subframeId | Supported | Y | Y | Y | \r
+| | (subframe | | | | |\r
+| | i\ | | | | |\r
+| | dentifier) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | slotId | Supported | Y | Y | Y | \r
+| | (slot | | | | |\r
+| | i | | | | |\r
+| | dentifier) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | symbolId | Supported | Y | Y | Y | \r
+| | (symbol | | | | |\r
+| | i\ | | | | |\r
+| | dentifier) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | sectionId | Supported | Y | Y | Y | \r
+| | (section | | | | |\r
+| | i\ | | | | |\r
+| | dentifier) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | rb | 0 | Y | Y | Y | \r
+| | (resource | | | | |\r
+| | block | | | | |\r
+| | indicator) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | symInc | 0 | Y | Y | Y |\r
+| | (symbol | | | | |\r
+| | number | | | | |\r
+| | increment | | | | |\r
+| | command) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | startPrbu | Supported | Y | Y | Y | \r
+| | (s\ | | | | |\r
+| | tartingPRB | | | | |\r
+| | of user | | | | |\r
+| | plane | | | | |\r
+| | section) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | numPrbu | Supported | Y | Y | Y |\r
+| | (number of | | | | |\r
+| | PRBs per | | | | |\r
+| | user plane | | | | |\r
+| | section) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | udCompHdr | Supported | Y | Y | N |\r
+| | (user data | | | | |\r
+| | c\ | | | | |\r
+| | ompression | | | | |\r
+| | header) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | reserved | 0 | Y | Y | Y | \r
+| | (reserved | | | | |\r
+| | for future | | | | |\r
+| | use) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | u\ | Supported | Y | Y | N | \r
+| | dCompParam | | | | |\r
+| | (user data | | | | |\r
+| | c\ | | | | |\r
+| | ompression | | | | |\r
+| | parameter) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | iSample | 16 | Y | Y | Y | \r
+| | (in-phase | | | | |\r
+| | sample) | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | qSample | 16 | Y | Y | Y | \r
+| | ( | | | | |\r
+| | quadrature | | | | |\r
+| | sample) | | | | |\r
++------------+-------------------------+------------+-----+-----+-----+\r
+| S-plane | Topology | Supported | N | N | N | \r
+| | conf\ | | | | |\r
+| | iguration: | | | | |\r
+| | C1 | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Topology | Supported | N | N | N |\r
+| | conf\ | | | | |\r
+| | iguration: | | | | |\r
+| | C2 | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Topology | Supported | Y | Y | Y |\r
+| | conf\ | | | | |\r
+| | iguration: | | | | |\r
+| | C3 | | | | |\r
+| +-------------------------+------------+-----+-----+-----+\r
+| | Topology | Supported | N | N | N | \r
+| | conf\ | | | | |\r
+| | iguration: | | | | |\r
+| | C4 | | | | |\r
++------------+------------+------------+------------+-----+-----+-----+\r
+| | PTP | Full | Supported | Y | Y | N |\r
+| | | Timing | | | | |\r
+| | | Support | | | | |\r
+| | | (G.8275.1) | | | | |\r
++------------+------------+------------+------------+-----+-----+-----+\r
+| M-plane | | | Not | N | N | N |\r
+| | | | supported | | | |\r
++------------+------------+------------+------------+-----+-----+-----+\r
+\r
+\* The bit width of each component in eAxC ID can be configurable.\r
+\r
+Transport Layer\r
+---------------\r
+\r
+O-RAN Fronthaul data can be transported over Ethernet or IPv4/IPv6. In\r
+the current implementation, the xRAN library supports only Ethernet with\r
+VLAN.\r
+\r
+.. image:: images/Native-Ethernet-Frame-with-VLAN.jpg\r
+ :width: 600\r
+ :alt: Figure 11. Native Ethernet Frame with VLAN\r
+\r
+Figure 11. Native Ethernet Frame with VLAN\r
+\r
+\r
+Standard DPDK routines are used to perform Transport Layer\r
+functionality.\r
+\r
+VLAN tag functionality is offloaded to NIC as per the configuration of\r
+VF (refer to Setup Configuration).\r
+\r
+The transport header is defined in the ORAN Fronthaul specification\r
+based on the eCPRI specification.\r
+\r
+.. image:: images/eCPRI-Header-Field-Definitions.jpg\r
+ :width: 600\r
+ :alt: Figure 12. eCPRI Header Field Definitions\r
+\r
+Figure 12. eCPRI Header Field Definitions\r
+\r
+Only ECPRI_IQ_DATA = 0x00 and ECPRI_RT_CONTROL_DATA= 0x02 message types\r
+are supported.\r
+\r
+For one-way delay measurements the eCPRI Header Field Definitions are\r
+the same as above until the ecpriPayload. The one-delay measurement\r
+message format is shown in the next figure.\r
+\r
+.. image:: images/ecpri-one-way-delay-measurement-message.jpg\r
+ :width: 600\r
+ :alt: Figure 13. ecpri one-way delay measurement message\r
+\r
+Figure 13. ecpri one-way delay measurement message\r
+\r
+In addition, for the eCPRI one-delay measurement message there is a\r
+requirement of dummy bytes insertion so the overall ethernet frame has\r
+at least 64 bytes.\r
+\r
+The measurement ID is a one-byte value used by the sender of the request\r
+to distinguish the response received between different measurements.\r
+\r
+The action type is a one-byte value defined in Table 8 of the eCPRI\r
+Specification V2.0.\r
+\r
+Action Type 0x00 corresponds to a Request\r
+\r
+Action Type 0x01 corresponds to a Request with Follow Up\r
+\r
+Both values are used by an eCPRI node to initiate a one-way delay\r
+measurement in the direction of its own node to another node.\r
+\r
+Action Type 0x02 corresponds to a Response\r
+\r
+Action Type 0x03 is a Remote Request\r
+\r
+Action Type 0x04 is a Remote Request with Follow Up\r
+\r
+Values 0x03 and 0x04 are used when an eCPRI node needs to know the\r
+one-way delay from another node to itself.\r
+\r
+Action Type 0x05 is the Follow_Up message.\r
+\r
+The timestamp uses the IEEE-1588 Timestamp format with 8 bytes for the\r
+seconds part and 4 bytes for the nanoseconds part. The timestamp is a\r
+positive time with respect to the epoch.\r
+\r
+The compensation value is used with Action Types 0x00 (Request), 0x02\r
+(Response) or 0x05 (Follow_up) for all others this field contains zeros.\r
+This value is the compensation time measured in nanoseconds and\r
+multiplied by 2\ :sup:16 and follows the format for the\r
+correctionField in the common message header specified by the IEE\r
+1588-2008 clause 13.3.\r
+\r
+Handling of ecpriRtcid/ecpriPcid Bit field size is configurable and can\r
+be defined on the initialization stage of the xRAN library.\r
+\r
+.. image:: images/Bit-Allocations-of-ecpriRtcid-ecpriPcid.jpg\r
+ :width: 600\r
+ :alt: Figure 14. Bit Allocations of ecpriRtcid/ecpriPcid\r
+\r
+Figure 14. Bit Allocations of ecpriRtcid/ecpriPcid\r
+\r
+For ecpriSeqid only, the support for a sequence number is implemented.\r
+The subsequent number is not supported.\r
+\r
+U-plane\r
+-------\r
+\r
+The following diagrams show O-RAN packet protocols’ headers and data\r
+arrangement with and without compression support.\r
+\r
+XRAN packet meant for traffic with compression enabled has the\r
+Compression Header added after each Application Header. According to\r
+O-RAN Fronthaul's specification, the Compression Header is part of a\r
+repeated Section Application Header. In the xRAN library implementation,\r
+the header is implemented as a separate structure, following the\r
+Application Section Header. As a result, the Compression Header is not\r
+included in the O-RAN packet, if compression is not used.\r
+\r
+Figure 15 shows the components of an ORAN packet.\r
+\r
+.. image:: images/xRAN-Packet-Components.jpg\r
+ :width: 600\r
+ :alt: Figure 15. O-RAN Packet Components\r
+\r
+Figure 15. O-RAN Packet Components\r
+\r
+Radio Application Header\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The next header is a common header used for time reference.\r
+\r
+.. image:: images/Radio-Application-Header.jpg\r
+ :width: 600\r
+ :alt: Figure 16. Radio Application Header\r
+\r
+Figure 16. Radio Application Header\r
+\r
+The radio application header specific field values are implemented as\r
+follows:\r
+\r
+- filterIndex = 0\r
+\r
+- frameId = [0:99]\r
+\r
+- subframeId = [0:9]\r
+\r
+- slotId = [0:7]\r
+\r
+- symbolId = [0:13]\r
+\r
+Data Section Application Data Header\r
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The Common Radio Application Header is followed by the Application\r
+Header that is repeated for each Data Section within the eCPRI message.\r
+The relevant section of O-RAN packet is shown in color.\r
+\r
+.. image:: images/Data-Section-Application-Data-Header.jpg\r
+ :width: 600\r
+ :alt: Figure 17. Data Section Application Data Header\r
+\r
+Figure 17. Data Section Application Data Header\r
+\r
+\r
+A single section is used per one Ethernet packet with IQ samples\r
+startPrbu is equal to 0 and numPrbu is wqual to the number of RBs used:\r
+\r
+- rb field is not used (value 0).\r
+\r
+- symInc is not used (value 0)\r
+\r
+Data Payload\r
+~~~~~~~~~~~~\r
+\r
+An O-RAN packet data payload contains a number of PRBs. Each PRB is built\r
+of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour. \r
+\r
+.. image:: images/Data-Payload.jpg\r
+ :width: 600\r
+ :alt: Figure 17. Data Payload\r
+\r
+Figure 17. Data Payload\r
+\r
+C-plane\r
+-------\r
+\r
+C-Plane messages are encapsulated using a two-layered header approach.\r
+The first layer consists of an eCPRI standard header, including\r
+corresponding fields used to indicate the message type, while the second\r
+layer is an application layer including necessary fields for control and\r
+synchronization. Within the application layer, a “section” defines the characteristics of U-plane data to be transferred or received from a\r
+beam with one pattern id. In general, the transport header,application\r
+header, and sections are all intended to be aligned on 4-byte boundaries\r
+and are transmitted in “network byte order” meaning the most significant\r
+byte of a multi-byte parameter is transmitted first.\r
+\r
+Table 9 is a list of sections currently supported.\r
+\r
+Table 9. Section Types\r
+\r
++--------------+--------------------------+--------------------------+\r
+| Section Type | Target Scenario | Remarks |\r
++--------------+--------------------------+--------------------------+\r
+| 0 | Unused Resource Blocks | Not supported |\r
+| | or symbols in Downlink | |\r
+| | or Uplink | |\r
++--------------+--------------------------+--------------------------+\r
+| 1 | Most DL/UL radio | Supported |\r
+| | channels | |\r
++--------------+--------------------------+--------------------------+\r
+| 2 | reserved for future use | N/A |\r
++--------------+--------------------------+--------------------------+\r
+| 3 | PRACH and | Only PRACH is supported. |\r
+| | mixed-numerology | Mixed numerology is not |\r
+| | channels | supported. |\r
++--------------+--------------------------+--------------------------+\r
+| 4 | Reserved for future use | Not supported |\r
++--------------+--------------------------+--------------------------+\r
+| 5 | UE scheduling | Not supported |\r
+| | information (UE-ID | |\r
+| | assignment to section) | |\r
++--------------+--------------------------+--------------------------+\r
+| 6 | Channel information | Not supported |\r
++--------------+--------------------------+--------------------------+\r
+| 7 | LAA | Not supported |\r
++--------------+--------------------------+--------------------------+\r
+| 8-255 | Reserved for future use | N/A |\r
++--------------+--------------------------+--------------------------+\r
+\r
+Section extensions are not supported in this release.\r
+\r
+The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h\r
+and the fields are appropriately re-ordered in order to apply the\r
+conversion of network byte order after setting values.\r
+The comments in source code of xRAN lib can be used to see more information on \r
+implementation specifics of handling sections as well as particular fields. \r
+Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario.\r
+\r
+Ethernet Header\r
+~~~~~~~~~~~~~~~\r
+\r
+Refer to Figure 11.\r
+\r
+eCPRI Header\r
+~~~~~~~~~~~~\r
+\r
+Refer to Figure 12.\r
+\r
+This header is defined as the structure of xran_ecpri_hdr in\r
+lib/api/xran_pkt.h.\r
+\r
+Radio Application Common Header\r
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The Radio Application Common Header is used for time reference. Its\r
+structure is shown in Figure 18.\r
+\r
+.. image:: images/Radio-Application-Common-Header.jpg\r
+ :width: 600\r
+ :alt: Figure 19. Radio Application Common Header\r
+\r
+Figure 19. Radio Application Common Header\r
+\r
+This header is defined as the structure of\r
+xran_cp_radioapp_common_header in lib/api/xran_pkt_cp.h.\r
+\r
+Please note that the payload version in this header is fixed to\r
+XRAN_PAYLOAD_VER (defined as 1) in this release.\r
+\r
+Section Type 0 Structure\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+Figure 20 describes the structure of Section Type 0.\r
+\r
+.. image:: images/Section-Type-0-Structure.jpg\r
+ :width: 600\r
+ :alt: Figure 20. Section Type 0 Structure\r
+\r
+Figure 20. Section Type 0 Structure\r
+\r
+In Figure 19 through Figure 23, the color yellow means it is a transport\r
+header; the color pink is the radio application header; others are\r
+repeated sections.\r
+\r
+Section Type 1 Structure\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+Figure 21 describes the structure of Section Type 1.\r
+\r
+.. image:: images/Section-Type-1-Structure.jpg\r
+ :width: 600\r
+ :alt: Figure 21. Section Type 1 Structure\r
+\r
+Figure 21. Section Type 1 Structure\r
+\r
+Section Type 1 message has two additional parameters in addition to\r
+radio application common header:\r
+\r
+- udCompHdr : defined as the structure of xran_radioapp_udComp_header\r
+\r
+- reserved : fixed by zero\r
+\r
+Section type 1 is defined as the structure of xran_cp_radioapp_section1,\r
+and this part can be repeated to have multiple sections.\r
+\r
+Whole section type 1 message can be described in this summary:\r
+\r
++----------------------------------+\r
+| xran_cp_radioapp_common_header |\r
++==================================+\r
+| xran_cp_radioapp_section1_header |\r
++----------------------------------+\r
+| xran_cp_radioapp_section1 |\r
++----------------------------------+\r
+| …… |\r
++----------------------------------+\r
+| xran_cp_radioapp_section1 |\r
++----------------------------------+\r
+\r
+Section Type 3 Structure\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+Figure 22 describes the structure of Section Type 3.\r
+\r
+.. image:: images/Section-Type-3-Structure.jpg\r
+ :width: 600\r
+ :alt: Figure 22. Section Type 3 Structure\r
+\r
+Figure 22. Section Type 3 Structure\r
+\r
+Section Type 3 message has below four additional parameters in addition\r
+to radio application common header.\r
+\r
+- timeOffset\r
+\r
+- frameStructure: defined as the structure of\r
+ xran_cp_radioapp_frameStructure\r
+\r
+- cpLength\r
+\r
+- udCompHdr: defined as the structure of xran_radioapp_udComp_header\r
+\r
+Section Type 3 is defined as the structure of xran_cp_radioapp_section3\r
+and this part can be repeated to have multiple sections.\r
+\r
+Whole section type 3 message can be described in this summary:\r
+\r
++----------------------------------+\r
+| xran_cp_radioapp_common_header |\r
++==================================+\r
+| xran_cp_radioapp_section3_header |\r
++----------------------------------+\r
+| xran_cp_radioapp_section3 |\r
++----------------------------------+\r
+| …… |\r
++----------------------------------+\r
+| xran_cp_radioapp_section3 |\r
++----------------------------------+\r
+\r
+Section Type 5 Structure\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+Figure 23 describes the structure of Section Type 5.\r
+\r
+.. image:: images/Section-Type-5-Structure.jpg\r
+ :width: 600\r
+ :alt: Figure 23. Section Type 5 Structure\r
+\r
+Figure 23. Section Type 5 Structure\r
+\r
+\r
+Section Type 6 Structure\r
+~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+Figure 24 describes the structure of Section Type 6.\r
+\r
+.. image:: images/Section-Type-6-Structure.jpg\r
+ :width: 600\r
+ :alt: Figure 24. Section Type 6 Structure\r
+\r
+Figure 24. Section Type 6 Structure\r
+\r
--- /dev/null
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+\r
+eCPRI DDP Profile for Columbiaville (Experimental Feature)\r
+==========================================================\r
+\r
+.. _introduction-3:\r
+\r
+Introduction\r
+============\r
+\r
+The Intel® Ethernet 800 Series is the next generation of Intel® Ethernet\r
+Controllers and Network Adapters. The Intel® Ethernet 800 Series is\r
+designed with an enhanced programmable pipeline, allowing deeper and\r
+more diverse protocol header processing. This on-chip capability is\r
+called Dynamic Device Personalization (DDP). In the Intel® Ethernet 800\r
+Series, a DDP profile is loaded dynamically on driver load per device.\r
+\r
+A general-purpose DDP package is automatically installed with all\r
+supported Intel® Ethernet 800 Series drivers on Windows*, ESX*,\r
+FreeBSD*, and Linux\* operating systems, including those provided by the\r
+Data Plane Development Kit (DPDK). This general-purpose DDP package is\r
+known as the OS-default package.\r
+\r
+For more information on DDP technology in the Intel® Ethernet 800 Series\r
+products and the OS-default package, refer to the Intel® Ethernet\r
+Controller E810 Dynamic Device Personalization (DDP) Technology Guide,\r
+published here: https://cdrdv2.intel.com/v1/dl/getContent/617015.\r
+\r
+This document describes an optional DDP package targeted towards the\r
+needs of Wireless and Edge (Wireless Edge) customers. This Wireless Edge\r
+DDP package (v1.3.22.101) adds support for eCPRI protocols in addition\r
+to the protocols in the OS-default package. The Wireless Edge DDP\r
+package is supported by DPDK.\r
+\r
+Starting from DPDK 21.02 drivers and in the future will also be\r
+supported by the Intel® Ethernet 800 Series ice driver. on Linux\r
+operating systems. The Wireless DDP Package can be loaded on all Intel®\r
+Ethernet 800 Series devices, or different packages can be selected via\r
+serial number per device.\r
+\r
+Software/Firmware Requirements\r
+==============================\r
+\r
+The specific DDP package requires certain firmware and DPDK versions and\r
+Intel® Ethernet 800 Series firmware/NVM versions. Support for eCPRI DDP\r
+profile included starting from Columbiaville (CVL)release 2.4 or later.\r
+The required DPDK version contains the support of loading the specific\r
+Wireless Edge DDP package.\r
+\r
+- Intel® Ethernet 800 Series Linux Driver (ice) — 1.4.0 (or later)\r
+\r
+- Wireless Edge DDP Package version (ice_wireless_edge) — 1.3.22.101\r
+\r
+- Intel® Ethernet 800 Series firmware version — 1.5.4.2 (or later)\r
+\r
+- Intel® Ethernet 800 Series NVM version — 2.4 (or later)\r
+\r
+- DPDK version— 21.02 (or later)\r
+\r
+- For FlexRAN release 21.03, corresponding support of CVL 2.4 driver pack and DPDK 21.02 is “experimental” and subject to additional testing and potential changes.\r
+\r
+DDP Package Setup\r
+=================\r
+\r
+The Intel® Ethernet 800 Series Comms DDP package supports only\r
+Linux-based operating systems currently.\r
+\r
+Currently, the eCPRI is fully supported only by DPDK 21.02. It can be\r
+loaded either by DPDK or the Intel® Ethernet 800 Series Linux base\r
+driver.\r
+\r
+Wireless Edge DDP Package\r
+=========================\r
+\r
+For details on how to set up DPDK, refer to Intel® Ethernet Controller\r
+E810 Data Plane Development Kit (DPDK) Configuration Guide (Doc ID:\r
+633514).\r
+\r
+There are two methods where DDP package can be loaded and used under\r
+DPDK (see Section C.3.2 and\r
+Section C.3.2 ). For both methods, the\r
+user must obtain the ice_wireless_edge-1.3.22.101.pkg or later from\r
+Intel (please contact your Intel representative for more information)\r
+\r
+Option 1: *ice* Linux Base Driver\r
+=================================\r
+\r
+The first option is to have the ice Linux base driver load the package.\r
+\r
+The *ice* Linux base driver looks for the symbolic link\r
+*intel/ice/ddp/ice.pkg* under the default firmware search path, checking\r
+the following folders in order:\r
+\r
+- */lib/firmware/updates/*\r
+\r
+- */lib/firmware/*\r
+\r
+To install the Comms package, copy the extracted .pkg file and its\r
+symbolic link to */lib/firmware/updates/intel/ice/ddp* as follows, and\r
+reload the ice driver::\r
+\r
+ # cp /usr/tmp/ice_wireless_edge-1.3.22.101.pkg /lib/firmware/updates/intel/ice/ddp/\r
+ # ln -sf /lib/firmware/updates/intel/ice/ddp/ice_wireless_edge-1.3.22.101.pkg /lib/firmware/updates/intel/ice/ddp/ice.pkg\r
+ # modprobe -r irdma\r
+ # modprobe -r ice\r
+ # modprobe ice\r
+\r
+\r
+The kernel message log (*dmesg*) indicates status of package loading in\r
+the system. If the driver successfully finds and loads the DDP package,\r
+*dmesg* indicates that the DDP package successfully loaded. If not, the\r
+driver transitions to safe mode.\r
+\r
+Once the driver loads the package, the user can unbind the *ice* driver\r
+from a desired port on the device so that DPDK can utilize the port.\r
+\r
+The following example unbinds Port 0 and Port 1 of device on Bus 6,\r
+Device 0. Then, the port is bound to either igb_uio or vfio-pci. ::\r
+\r
+ # ifdown <interface>\r
+ # dpdk-devbind -u 06:00.0\r
+ # dpdk-devbind -u 06:00.1\r
+ # dpdk-devbind -b igb_uio 06:00.0 06:00.1\r
+\r
+Option 2: DPDK Driver Only\r
+==========================\r
+\r
+The second method is if the system does not have the *ice* driver\r
+installed. In this case, the user can download the DDP package from the\r
+Intel download center and extract the zip file to obtain the package\r
+(*.pkg*) file. Similar to the Linux base driver, the DPDK driver looks\r
+for the *intel/ddp/ice.pkg* symbolic link in the kernel default firmware\r
+search path */lib/firmware/updates and /lib/firmware/*.\r
+\r
+Copy the extracted DDP *.pkg* file and its symbolic link to\r
+*/lib/firmware/intel/ice/ddp*, as follows. ::\r
+\r
+ # cp /usr/tmp/ice_wireless_edge-1.3.22.101 /lib/firmware/intel/ice/ddp/\r
+ # cp /usr/tmp/ice.pkg /lib/firmware/intel/ice/ddp/\r
+\r
+When DPDK driver loads, it looks for *ice.pkg* to load. If the file\r
+exists, the driver downloads it into the device. If not, the driver\r
+transitions into safe mode.\r
+\r
+Loading DDP Package to a Specific Intel® Ethernet 800 Series Device\r
+===================================================================\r
+\r
+On a host system running with multiple Intel® Ethernet 800 Series\r
+devices, there is sometimes a need to load a specific DDP package on a\r
+selected device while loading a different package on the remaining\r
+devices.\r
+\r
+The Intel® Ethernet 800 Series Linux base driver and DPDK driver can\r
+both load a specific DDP package to a selected adapter based on the\r
+device's serial number. The driver does this by looking for a specific\r
+symbolic link package filename containing the selected device's serial\r
+number.\r
+\r
+The following example illustrates how a user can load a specific package\r
+(e.g., *ice_wireless_edge-1.3.22.101*) on the device of Bus 6.\r
+\r
+1. Find device serial number.\r
+\r
+..\r
+\r
+To view bus, device, and function of all Intel® Ethernet 800 Series\r
+Network Adapters in the system:::\r
+\r
+ # lspci | grep -i Ethernet | grep -i Intel\r
+ 06:00.0 Ethernet controller: Intel Corporation Ethernet Controller E810-C for QSFP (rev 01)\r
+ 06:00.1 Ethernet controller: Intel Corporation Ethernet Controller E810-C for QSFP (rev 01)\r
+ 82:00.0 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01)\r
+ 82:00.1 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01)\r
+ 82:00.2 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01)\r
+ 82:00.3 Ethernet controller: Intel Corporation Ethernet Controller E810-C for SFP (rev 01)\r
+\r
+Use the **lspci** command to obtain the selected device serial\r
+number:::\r
+\r
+ # lspci -vv -s 06:00.0 \| grep -i Serial\r
+ Capabilities: [150 v1] Device Serial Number 35-11-a0-ff-ff-ca-05-68\r
+\r
+Or, fully parsed without punctuation:::\r
+\r
+ # lspci -vv -s 06:00.0 \|grep Serial \|awk '{print $7}'|sed s/-//g\r
+ 3511a0ffffca0568\r
+\r
+2. Rename the package file with the device serial number in the name.\r
+\r
+..\r
+\r
+Copy the specific package over to /lib/firmware/updates/intel/ice/ddp\r
+(or /lib/firmware/intel/ice/ ddp) and create a symbolic link with the\r
+serial number linking to the package, as shown. The specific symbolic\r
+link filename starts with “ice-” followed by the device serial in\r
+lower case without dash ('-'). ::\r
+\r
+ # ln -s\r
+ /lib/firmware/updates/intel/ice/ddp/ice_wireless_edge-1.3.22.101.pkg\r
+ /lib/firmware/updates/intel/ice/ddp/ice-3511a0ffffca0568.pkg\r
+\r
+3. If using Linux kernel driver (*ice*), reload the base driver (not\r
+required if using only DPDK driver). ::\r
+\r
+ # rmmod ice\r
+ # modprobe ice\r
+\r
+The driver loads the specific package to the selected device and the\r
+OS-default package to the remaining Intel® Ethernet 800 Series\r
+devices in the system.\r
+\r
+4. Verify.\r
+\r
+For kernel driver:\r
+==================\r
+\r
+Example of output of successful load of Wireless Edge Package to all\r
+devices:::\r
+\r
+ # dmesg | grep -i "ddp \| safe"\r
+ [606960.921404] ice 0000:18:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101\r
+ [606961.672999] ice 0000:18:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+ [606962.439067] ice 0000:18:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+ [606963.198305] ice 0000:18:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+ [606964.252076] ice 0000:51:00.0: The DDP package was successfully loaded: ICE Wireless Edge Package version 1.3.22.101\r
+ [606965.017082] ice 0000:51:00.1: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+ [606965.802115] ice 0000:51:00.2: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+ [606966.576517] ice 0000:51:00.3: DDP package already present on device: ICE Wireless Edge Package version 1.3.22.101\r
+\r
+\r
+If using only DPDK driver:\r
+==========================\r
+\r
+Verify using DPDK's **testpmd** application to indicate the status\r
+And version of the loaded DDP package.\r
+\r
+Example of eCPRI config with dpdk-testpmd\r
+-----------------------------------------\r
+\r
+16 O-RAN eCPRI IQ streams mapped to 16 independent HW queues each.::\r
+\r
+ #./dpdk-testpmd -l 22-25 -n 4 -a 0000:af:01.0 -- -i --rxq=16 --txq=16 --cmdline-file=/home/flexran_xran/ddp.txt\r
+\r
+ cat /home/flexran_xran/ddp.txt\r
+ port stop 0\r
+ port config mtu 0 9600\r
+ port config 0 rx_offload vlan_strip on\r
+ port start 0\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0000 / end actions queue index 0 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0001 / end actions queue index 1 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0002 / end actions queue index 2 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0003 / end actions queue index 3 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0004 / end actions queue index 4 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0005 / end actions queue index 5 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0006 / end actions queue index 6 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0007 / end actions queue index 7 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0008 / end actions queue index 8 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x0009 / end actions queue index 9 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000a / end actions queue index 10 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000b / end actions queue index 11 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000c / end actions queue index 12 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000d / end actions queue index 13 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000e / end actions queue index 14 / mark / end\r
+ flow create 0 ingress pattern eth / ecpri common type iq_data pc_id is 0x000f / end actions queue index 15 / mark / end\r
+ set fwd rxonly\r
+ start\r
+ show fwd stats all\r
+\r
+\r
+O-RAN Front haul eCPRI\r
+======================\r
+\r
+Intel® Ethernet 800 Series DDP capabilities support several\r
+functionalities important for the O-RAN FH.\r
+\r
+- RSS for packet steering based on ecpriMessage\r
+\r
+- RSS for packet steering based on ecpriRtcid/ecpriPcid\r
+\r
+- Queue mapping based on ecpriRtcid/ecpriPcid\r
+\r
+- Queue mapping based on ecpriMessage\r
+\r
+.. image:: images/O-RAN-FH-VNF.jpg\r
+ :width: 400\r
+ :alt: Figure . O-RAN FH VNF\r
+\r
+Figure 30. O-RAN FH VNF\r
+\r
+Table 13. Patterns & Input Sets for Flow Director and RSS (DPDK 21.02)\r
+\r
+============================= ========================================\r
+Pattern Input Set\r
+============================= ========================================\r
+ETH / VLAN / eCPRI ecpriMessage \| ecpriRtcid/ecpriPcid\r
+ETH / VLAN /IPv4(6)/UDP/eCPRI ecpriMessage \| ecpriRtcid/ecpriPcid (*)\r
+============================= ========================================\r
+\r
+*Note:* \* IP/UDP is not used with FlexRAN\r
+\r
+Limitations\r
+===========\r
+\r
+DPDK 21.02 allows up to 1024 queues per VF and RSS across up to 64\r
+receive queues.\r
+\r
+RTE Flow API\r
+============\r
+\r
+The DPDK Generic flow API (rte_flow) will be used to the configure the\r
+Intel® Ethernet 800 Series to match specific ingress traffic and forward\r
+it to specified queues.\r
+\r
+For further information, please refer to section 11 of the DPDK\r
+Programmers\r
+guide <https://doc.dpdk.org/guides/prog_guide/rte_flow.html>.\r
+\r
+The specific ingress traffic is identified by a matching pattern which\r
+is composed of one or more Pattern items (represented by struct\r
+rte_flow_item). Once a match has been determined one or more associated\r
+Actions (represented by struct rte_flow_action) will be performed.\r
+\r
+A number of flow rules can be combined such that one rule directs\r
+traffic to a queue group based on *ecpriMessage/ ecpriRtcid/ecpriPcid*\r
+etc. and a second rule distributes matching packets within that queue\r
+group using RSS.\r
+\r
+The following subset of the RTE Flow API functions can be used to\r
+validate, create and destroy RTE Flow rules.\r
+\r
+RTE Flow Rule Validation\r
+========================\r
+\r
+A RTE Flow rule is created via a call to the function\r
+*rte_flow_validate*. This can be used to check the rule for correctness\r
+and whether it would be accepted by the device given sufficient\r
+resources.::\r
+\r
+ int rte_flow_validate(uint16_t port_id,\r
+ const struct rte_flow_attr *attr,\r
+ const struct rte_flow_item pattern[],\r
+ const struct rte_flow_action *actions[]\r
+ struct rte_flow_error *error);\r
+\r
+\r
+port_id : port identifier of Ethernet device\r
+\r
+attr : flow rule attributes(ingress/egress)\r
+\r
+pattern : pattern specification (list terminated by the END pattern\r
+item).\r
+\r
+action : associated actions (list terminated by the END action).\r
+\r
+error : perform verbose error reporting if not NULL.\r
+\r
+0 is returned upon success, negative errno otherwise.\r
+\r
+RTE Flow Rule Creation\r
+======================\r
+\r
+A RTE Flow rule is created via a call to the function *rte_flow_create*.::\r
+\r
+ struct rte_flow * rte_flow_create(uint16_t port_id,\r
+ const struct rte_flow_attr *attr,\r
+ const struct rte_flow_item pattern[],\r
+ const struct rte_flow_action *actions[]\r
+ struct rte_flow_error *error);\r
+\r
+port_id : port identifier of Ethernet device\r
+\r
+attr : flow rule attributes(ingress/egress)\r
+\r
+pattern : pattern specification (list terminated by the END pattern\r
+item).\r
+\r
+action : associated actions (list terminated by the END action).\r
+\r
+error : perform verbose error reporting if not NULL.\r
+\r
+A valid handle is returned upon success, NULL otherwise.\r
+\r
+RTE Flow Rule Destruction\r
+=========================\r
+\r
+A RTE Flow rule is destroyed via a call to the function\r
+*rte_flow_destroy*.::\r
+\r
+ int rte_flow_destroy(uint16_t port_id,\r
+ struct rte_flow \*flow,\r
+ struct rte_flow_error \*error);\r
+\r
+port_id : port identifier of Ethernet device\r
+\r
+flow : flow rule handle to destroy.\r
+\r
+error : perform verbose error reporting if not NULL.\r
+\r
+0 is returned upon success, negative errno otherwise.\r
+\r
+RTE Flow Flush\r
+==============\r
+\r
+All flow rule handles associated with a port can be released using\r
+*rte_flow_flush*. They are released as with successive calls to function\r
+*rte_flow_destroy*.::\r
+\r
+ int rte_flow_flush(uint16_t port_id,\r
+ struct rte_flow_error \*error);\r
+\r
+port_id : port identifier of Ethernet device\r
+\r
+error : perform verbose error reporting if not NULL.\r
+\r
+0 is returned upon success, negative errno otherwise.\r
+\r
+RTE Flow Query\r
+==============\r
+\r
+A RTE Flow rule is queried via a call to the function *rte_flow_query*.::\r
+\r
+ int rte_flow_query(uint16_t port_id,\r
+ struct rte_flow *flow,\r
+ const struct rte_flow_action *action,\r
+ void *data,\r
+ struct rte_flow_error *error);\r
+\r
+port_id : port identifier of Ethernet device\r
+\r
+flow : flow rule handle to query\r
+\r
+action : action to query, this must match prototype from flow rule.\r
+\r
+data : pointer to storage for the associated query data type\r
+\r
+error : perform verbose error reporting if not NULL.\r
+\r
+0 is returned upon success, negative errno otherwise.\r
+\r
+RTE Flow Rules\r
+==============\r
+\r
+A flow rule is the combination of attributes with a matching pattern and\r
+a list of actions. Each flow rules consists of:\r
+\r
+- **Attributes (represented by struct rte_flow_attr):** properties of a flow rule such as its direction (ingress or egress) and priority.\r
+\r
+- **Pattern Items (represented by struct rte_flow_item):** is part of a matching pattern that either matches specific packet data or traffic properties.\r
+\r
+- **Matching pattern:** traffic properties to look for, a combination of any number of items.\r
+\r
+- **Actions (represented by struct rte_flow_action):** operations to perform whenever a packet is matched by a pattern.\r
+\r
+Attributes\r
+==========\r
+\r
+Flow rule patterns apply to inbound and/or outbound traffic. For the\r
+purposes described in later sections the rules apply to ingress only.\r
+For further information, please refer to section 11 of the DPDK\r
+Programmers guide <https://doc.dpdk.org/guides/prog_guide/rte_flow.html>.::\r
+\r
+ *struct*\ rte_flow_attr <https://doc.dpdk.org/api/structrte__flow__attr.html>\ *{*\r
+ *uint32_t*\ group <https://doc.dpdk.org/api/structrte__flow__attr.html#a0d20c78ce80e301ed514bd4b4dec9ec0>\ *;*\r
+ *uint32_t*\ priority <https://doc.dpdk.org/api/structrte__flow__attr.html#a90249de64da5ae5d7acd34da7ea1b857>\ *;*\r
+ *uint32_t*\ ingress <https://doc.dpdk.org/api/structrte__flow__attr.html#ae4d19341d5298a2bc61f9eb941b1179c>\ *:1;*\r
+ *uint32_t*\ egress <https://doc.dpdk.org/api/structrte__flow__attr.html#a33bdc3cfc314d71f3187a8186bc570a9>\ *:1;*\r
+ *uint32_t*\ transfer <https://doc.dpdk.org/api/structrte__flow__attr.html#a9371183486f590ef35fef41dec806fef>\ *:1;*\r
+ *uint32_t*\ reserved <https://doc.dpdk.org/api/structrte__flow__attr.html#aa43c4c21b173ada1b6b7568956f0d650>\ *:29;*\r
+ *};*\r
+\r
+Pattern items\r
+=============\r
+\r
+For the purposes described in later sections Pattern items are primarily\r
+for matching protocol headers and packet data, usually associated with a\r
+specification structure. These must be stacked in the same order as the\r
+protocol layers to match inside packets, starting from the lowest.\r
+\r
+Item specification structures are used to match specific values among\r
+protocol fields (or item properties).\r
+\r
+Up to three structures of the same type can be set for a given item:\r
+\r
+- **spec:** values to match (e.g. a given IPv4 address).\r
+\r
+- **last:** upper bound for an inclusive range with corresponding fields in spec.\r
+\r
+- **mask:** bit-mask applied to both spec and last whose purpose is to distinguish the values to take into account and/or partially mask them out (e.g. in order to match an IPv4 address prefix).\r
+\r
+Table 14. Example RTE FLOW Item Types\r
+\r
++-------------+---------------------------------------+-------------------------+\r
+| Item Type\* | Description | Specification Structure |\r
++=============+=======================================+=========================+\r
+| END | End marker for item lists | None |\r
++-------------+---------------------------------------+-------------------------+\r
+| VOID | Used as a placeholder for convenience | None |\r
++-------------+---------------------------------------+-------------------------+\r
+| ETH | Matches an Ethernet header | rte_flow_item_eth |\r
++-------------+---------------------------------------+-------------------------+\r
+| VLAN | Matches an 802.1Q/ad VLAN tag. | rte_flow_item_vlan |\r
++-------------+---------------------------------------+-------------------------+\r
+| IPV4 | Matches an IPv4 header | rte_flow_item_ipv4 |\r
++-------------+---------------------------------------+-------------------------+\r
+| IPV6 | Matches an IPv6 header | rte_flow_item_ipv6 |\r
++-------------+---------------------------------------+-------------------------+\r
+| ICMP | Matches an ICMP header. | rte_flow_item_icmp |\r
++-------------+---------------------------------------+-------------------------+\r
+| UDP | Matches an UDP header. | rte_flow_item_udp |\r
++-------------+---------------------------------------+-------------------------+\r
+| TCP | Matches a TCP header. | rte_flow_item_tcp |\r
++-------------+---------------------------------------+-------------------------+\r
+| SCTP | Matches a SCTP header. | rte_flow_item_sctp |\r
++-------------+---------------------------------------+-------------------------+\r
+| VXLAN | Matches a VXLAN header. | rte_flow_item_vxlan |\r
++-------------+---------------------------------------+-------------------------+\r
+| NVGRE | Matches a NVGRE header. | rte_flow_item_nvgre |\r
++-------------+---------------------------------------+-------------------------+\r
+| ECPRI | Matches ECPRI Header | rte_flow_item_ecpri |\r
++-------------+---------------------------------------+-------------------------+\r
+\r
+::\r
+\r
+ RTE_FLOW_ITEM_TYPE_ETH\r
+\r
+ struct rte_flow_item_eth {\r
+ struct rte_ether_addr dst; /**< Destination MAC. */\r
+ struct rte_ether_addr src; /**< Source MAC. > */\r
+ rte_be16_t type; /**< EtherType or TPID.> */\r
+ };\r
+\r
+ struct rte_ether_addr {\r
+ uint8_t addr_bytes[RTE_ETHER_ADDR_LEN]; /**< Addr bytes in tx order */\r
+ }\r
+\r
+::\r
+\r
+ RTE_FLOW_ITEM_TYPE_IPV4 \r
+ \r
+ struct rte_flow_item_ipv4 {\r
+ struct rte_ipv4_hdr hdr; /**< IPv4 header definition. */\r
+ };\r
+\r
+ struct rte_ipv4_hdr {\r
+ uint8_t version_ihl; /**< version and header length */\r
+ uint8_t type_of_service; /**< type of service */\r
+ rte_be16_t total_length; /**< length of packet */\r
+ rte_be16_t packet_id; /**< packet ID */\r
+ rte_be16_t fragment_offset; /**< fragmentation offset */\r
+ uint8_t time_to_live; /**< time to live */\r
+ uint8_t next_proto_id; /**< protocol ID */\r
+ rte_be16_t hdr_checksum; /**< header checksum */\r
+ rte_be32_t src_addr; /**< source address */\r
+ rte_be32_t dst_addr; /**< destination address */\r
+ }\r
+\r
+ RTE_FLOW_ITEM_TYPE_UDP\r
+\r
+ struct rte_flow_item_udp {\r
+ struct rte_udp_hdr hdr; /**< UDP header definition. */\r
+ };\r
+\r
+ struct rte_udp_hdr {\r
+ rte_be16_t src_port; /**< UDP source port. */\r
+ rte_be16_t dst_port; /**< UDP destination port. */\r
+ rte_be16_t dgram_len; /**< UDP datagram length */\r
+ rte_be16_t dgram_cksum; /**< UDP datagram checksum */\r
+ }\r
+\r
+ RTE_FLOW_ITEM_TYPE_ECPRI \r
+ \r
+ struct rte_flow_item_ecpri {\r
+ struct rte_ecpri_combined_msg_hdr hdr;\r
+ };\r
+\r
+ struct rte_ecpri_combined_msg_hdr {\r
+ struct rte_ecpri_common_hdr common;\r
+ union {\r
+ struct rte_ecpri_msg_iq_data type0;\r
+ struct rte_ecpri_msg_bit_seq type1;\r
+ struct rte_ecpri_msg_rtc_ctrl type2;\r
+ struct rte_ecpri_msg_bit_seq type3;\r
+ struct rte_ecpri_msg_rm_access type4;\r
+ struct rte_ecpri_msg_delay_measure type5;\r
+ struct rte_ecpri_msg_remote_reset type6;\r
+ struct rte_ecpri_msg_event_ind type7;\r
+ rte_be32_t dummy[3];\r
+ };\r
+ };\r
+ struct rte_ecpri_common_hdr {\r
+ union {\r
+ rte_be32_t u32; /**< 4B common header in BE */\r
+ struct {\r
+ #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\r
+ uint32_t size:16; /**< Payload Size */\r
+ uint32_t type:8; /**< Message Type */\r
+ uint32_t c:1; /**< Concatenation Indicator */\r
+ uint32_t res:3; /**< Reserved */\r
+ uint32_t revision:4; /**< Protocol Revision */\r
+ #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN\r
+ uint32_t revision:4; /**< Protocol Revision */\r
+ uint32_t res:3; /**< Reserved */\r
+ uint32_t c:1; /**< Concatenation Indicator */\r
+ uint32_t type:8; /**< Message Type */\r
+ uint32_t size:16; /**< Payload Size */\r
+ #endif\r
+ };\r
+ };\r
+ };\r
+ /**\r
+ * eCPRI Message Header of Type #0: IQ Data\r
+ */\r
+ struct rte_ecpri_msg_iq_data {\r
+ rte_be16_t pc_id; /**< Physical channel ID */\r
+ rte_be16_t seq_id; /**< Sequence ID */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #1: Bit Sequence\r
+ */\r
+ struct rte_ecpri_msg_bit_seq {\r
+ rte_be16_t pc_id; /**< Physical channel ID */\r
+ rte_be16_t seq_id; /**< Sequence ID */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #2: Real-Time Control Data\r
+ */\r
+ struct rte_ecpri_msg_rtc_ctrl {\r
+ rte_be16_t rtc_id; /**< Real-Time Control Data ID */\r
+ rte_be16_t seq_id; /**< Sequence ID */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #3: Generic Data Transfer\r
+ */\r
+ struct rte_ecpri_msg_gen_data {\r
+ rte_be32_t pc_id; /**< Physical channel ID */\r
+ rte_be32_t seq_id; /**< Sequence ID */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #4: Remote Memory Access\r
+ */\r
+ RTE_STD_C11\r
+ struct rte_ecpri_msg_rm_access {\r
+ #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\r
+ uint32_t ele_id:16; /**< Element ID */\r
+ uint32_t rr:4; /**< Req/Resp */\r
+ uint32_t rw:4; /**< Read/Write */\r
+ uint32_t rma_id:8; /**< Remote Memory Access ID */\r
+ #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN\r
+ uint32_t rma_id:8; /**< Remote Memory Access ID */\r
+ uint32_t rw:4; /**< Read/Write */\r
+ uint32_t rr:4; /**< Req/Resp */\r
+ uint32_t ele_id:16; /**< Element ID */\r
+ #endif\r
+ uint8_t addr[6]; /**< 48-bits address */\r
+ rte_be16_t length; /**< number of bytes */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #5: One-Way Delay Measurement\r
+ */\r
+ struct rte_ecpri_msg_delay_measure {\r
+ uint8_t msr_id; /**< Measurement ID */\r
+ uint8_t act_type; /**< Action Type */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #6: Remote Reset\r
+ */\r
+ struct rte_ecpri_msg_remote_reset {\r
+ rte_be16_t rst_id; /**< Reset ID */\r
+ uint8_t rst_op; /**< Reset Code Op */\r
+ };\r
+\r
+ /**\r
+ * eCPRI Message Header of Type #7: Event Indication\r
+ */\r
+ struct rte_ecpri_msg_event_ind {\r
+ uint8_t evt_id; /**< Event ID */\r
+ uint8_t evt_type; /**< Event Type */\r
+ uint8_t seq; /**< Sequence Number */\r
+ uint8_t number; /**< Number of Faults/Notif */\r
+ };\r
+\r
+\r
+Matching Patterns\r
+=================\r
+\r
+A matching pattern is formed by stacking items starting from the lowest\r
+protocol layer to match. Patterns are terminated by END pattern item.\r
+\r
+Actions\r
+-------\r
+\r
+Each possible action is represented by a type. An action can have an\r
+associated configuration object. Actions are terminated by the END\r
+action.\r
+\r
+Table 15. RTE FLOW Actions\r
+\r
++----------+----------------------------+-------------------------+\r
+| Action\* | Description | Configuration Structure |\r
++==========+============================+=========================+\r
+| END | End marker for action | none |\r
+| | lists | |\r
++----------+----------------------------+-------------------------+\r
+| VOID | Used as a placeholder for | none |\r
+| | convenience | |\r
++----------+----------------------------+-------------------------+\r
+| PASSTHRU | Leaves traffic up for | none |\r
+| | additional processing by | |\r
+| | subsequent flow rules; | |\r
+| | makes a flow rule | |\r
+| | non-terminating. | |\r
++----------+----------------------------+-------------------------+\r
+| MARK | Attaches an integer value | rte_flow_action_mark |\r
+| | to packets and sets | |\r
+| | PKT_RX_FDIR and | |\r
+| | PKT_RX_FDIR_ID mbuf flags | |\r
++----------+----------------------------+-------------------------+\r
+| QUEUE | Assigns packets to a given | rte_flow_action_queue |\r
+| | queue index | |\r
++----------+----------------------------+-------------------------+\r
+| DROP | Drops packets | none |\r
++----------+----------------------------+-------------------------+\r
+| COUNT | Enables Counters for this | rte_flow_action_count |\r
+| | flow rule | |\r
++----------+----------------------------+-------------------------+\r
+| RSS | Similar to QUEUE, except | rte_flow_action_rss |\r
+| | RSS is additionally | |\r
+| | performed on packets to | |\r
+| | spread them among several | |\r
+| | queues according to the | |\r
+| | provided parameters. | |\r
++----------+----------------------------+-------------------------+\r
+| VF | Directs matching traffic | rte_flow_action_vf |\r
+| | to a given virtual | |\r
+| | function of the current | |\r
+| | device | |\r
++----------+----------------------------+-------------------------+\r
+\r
+Route to specific Queue id based on ecpriRtcid/ecpriPcid\r
+========================================================\r
+\r
+An RTE Flow Rule will be created to match an eCPRI packet with a\r
+specific pc_id value and route it to specified queues.\r
+\r
+.. _pattern-items-1:\r
+\r
+Pattern Items\r
+-------------\r
+\r
+Table 16. Pattern Items to match eCPRI packet with a Specific Physical\r
+Channel ID (pc_id)\r
+\r
++-------+----------+-----------------------+-----------------------+\r
+| Index | Item | Spec | Mask |\r
++=======+==========+=======================+=======================+\r
+| 0 | Ethernet | 0 | 0 |\r
++-------+----------+-----------------------+-----------------------+\r
+| 1 | eCPRI | hdr.common.type = | hdr.common.type = |\r
+| | | RTE_EC | 0xff; |\r
+| | | PRI_MSG_TYPE_IQ_DATA; | |\r
+| | | | hdr.type0.pc_id = |\r
+| | | hdr.type0.pc_id = | 0xffff; |\r
+| | | pc_id; | |\r
++-------+----------+-----------------------+-----------------------+\r
+| 2 | END | 0 | 0 |\r
++-------+----------+-----------------------+-----------------------+\r
+\r
+The following code sets up the *RTE_FLOW_ITEM_TYPE_ETH* and\r
+*RTE_FLOW_ITEM_TYPE_ECPRI* Pattern Items.\r
+\r
+The *RTE_FLOW_ITEM_TYPE_ECPRI* Pattern is configured to match on the\r
+pc_id value (in this case 8 converted to Big Endian byte order).\r
+\r
++--------------------------------------------------------------------------+\r
+| uint8_t pc_id_be = 0x0800; |\r
+| |\r
+| #define MAX_PATTERN_NUM 3 |\r
+| |\r
+| struct rte_flow_item pattern[MAX_PATTERN_NUM]; |\r
+| |\r
+| struct rte_flow_action action[MAX_ACTION_NUM]; |\r
+| |\r
+| struct rte_flow_item_ecpri ecpri_spec; |\r
+| |\r
+| struct rte_flow_item_ecpri ecpri_mask; |\r
+| |\r
+| /\* Ethernet \*/ |\r
+| |\r
+| patterns[0].type = RTE_FLOW_ITEM_TYPE_ETH; |\r
+| |\r
+| patterns[0].spec = 0; |\r
+| |\r
+| patterns[0].mask = 0; |\r
+| |\r
+| /\* ECPRI \*/ |\r
+| |\r
+| ecpri_spec.hdr.common.type = RTE_ECPRI_MSG_TYPE_IQ_DATA; |\r
+| |\r
+| ecpri_spec.hdr.type0.pc_id = pc_id_be; |\r
+| |\r
+| ecpri_mask.hdr.common.type = 0xff; |\r
+| |\r
+| ecpri_mask.hdr.type0.pc_id = 0xffff; |\r
+| |\r
+| ecpri_spec.hdr.common.u32 = rte_cpu_to_be_32(ecpri_spec.hdr.common.u32); |\r
+| |\r
+| pattern[1].type = RTE_FLOW_ITEM_TYPE_ECPRI; |\r
+| |\r
+| pattern[1].spec = &ecpri_spec; |\r
+| |\r
+| pattern[1].mask = &ecpri_mask; |\r
+| |\r
+| /\* END the pattern array \*/ |\r
+| |\r
+| patterns[2].type = RTE_FLOW_ITEM_TYPE_END |\r
++--------------------------------------------------------------------------+\r
+\r
+Action\r
+------\r
+\r
+Table 17. QUEUE action for given queue id\r
+\r
+===== ====== ====== ==================== ====================\r
+Index Action Fields Description Value\r
+===== ====== ====== ==================== ====================\r
+0 QUEUE index queue indices to use Must be 0,1,2,3, etc\r
+1 END\r
+===== ====== ====== ==================== ====================\r
+\r
+The following code sets up the action *RTE_FLOW_ACTION_TYPE_QUEUE* and\r
+calls the *rte_flow_create* function to create the RTE Flow rule.\r
+\r
++----------------------------------------------------------------------+\r
+| *#define MAX_ACTION_NUM 2* |\r
+| |\r
+| *uint16_t rx_q = 4;* |\r
+| |\r
+| *struct rte_flow_action_queue queue = { .index = rx_q };* |\r
+| |\r
+| *struct rte_flow \*handle;* |\r
+| |\r
+| *struct rte_flow_error err;* |\r
+| |\r
+| *struct rte_flow_action actions[MAX_ACTION_NUM];* |\r
+| |\r
+| *struct rte_flow_attr attributes = {.ingress = 1 };* |\r
+| |\r
+| *action[0].type = RTE_FLOW_ACTION_TYPE_QUEUE;* |\r
+| |\r
+| *action[0].conf = &queue;* |\r
+| |\r
+| *action[1].type = RTE_FLOW_ACTION_TYPE_END;* |\r
+| |\r
+| *handle = rte_flow_create (port_id, &attributes, patterns, actions, |\r
+| &err);* |\r
++----------------------------------------------------------------------+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-O-DU Low Project Introduction
-================================
-
-.. contents::
- :depth: 3
- :local:
-
-The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel Architecture. This 5GNR Reference PHY consists of a L1 binary \
-and three kinds of interfaces which are validated on a Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \
-5GNR L1 features. It implements the relevant functions described in [3GPP TS 38.211, 212, 213, 214 and 215].
-
-The L1 has three \
-interfaces to communicate with other network functions as described below:
-
-* Interface between L1 and Front Haul, it adopts the WG4 specification for the CUS plane communication.
-
-* Interface between O-DU Low and O-DU High, it adopts the FAPI interface according to the WG8 AAL specification.
-
-* Interface between O-DU Low and accelerator, DPDK BBDev was adopted as original contribution, it will follow the WG6 definition after the WG6 specification is finalized.
-
-The following figure shows the ORAN O-CU, O-DU and O-RU blocks for a gNB implemetation. The O-DU Low projects implements the FAPI interface by a 5G FAPI TM module, the OFH-U and OFH-C
-by means of the FHI Library and the functionality of the High-PHY and a test MAC are available through github in the form of a binary blob for the current release. For the details refer to the Running L1 and Testmac section of this document
-
-
-.. image:: images/ORAN_OCU_ODU_ORU.jpg
- :width: 600
- :alt: Figure1.Oran OCU ODU and ORU Block Diagram
-
-Scope
------
-
-In this O-DU Low document, the details on how the build the modules supporting each interface, how to run the L1 and associated components, the architecture for each
-interface implementation and the release notes that describe each component release details are provided.
-
-Intended Audience
--------------------
-
-The intended audience for this document are software engineers and system architects who design and develop |br|
-5G systems using the O-RAN Specifications.
-
-Terminology
--------------
-
-Table 1. Terminology
-
-+--------+------------------------------------------------------------+
-| Term | Description |
-+--------+------------------------------------------------------------+
-| 5G NR | Fifth Generation New Radio |
-+--------+------------------------------------------------------------+
-| BOM | Bill of Materials |
-+--------+------------------------------------------------------------+
-| CP | Cyclic Prefix |
-+--------+------------------------------------------------------------+
-| DPDK | Data Plane Development Kit |
-+--------+------------------------------------------------------------+
-| gNB | Next-generation NodeB also named as Base Station |
-+--------+------------------------------------------------------------+
-| HARQ | Hybrid Automatic Repeat Request |
-+--------+------------------------------------------------------------+
-| HW | Hardware |
-+--------+------------------------------------------------------------+
-| IOT | Inter-Operability Testing |
-+--------+------------------------------------------------------------+
-| IQ | In-band and Quadrature |
-+--------+------------------------------------------------------------+
-| NIC | Network Interface Controller |
-+--------+------------------------------------------------------------+
-| O-DU | O-RAN Distributed Unit: a logical node hosting |
-| | RLC/MAC/High-PHY layers based on a lower layer functional |
-| | split. |
-+--------+------------------------------------------------------------+
-| O-RU | O-RAN Radio Unit: a logical node hosting Low-PHY layer and |
-| | RF processing based on a lower layer functional split. |
-| | This is similar to 3GPP’s “TRP” or “RRH” but more specific |
-| | in including the Low-PHY layer (FFT/IFFT, PRACH |
-| | extraction). |
-+--------+------------------------------------------------------------+
-| PDCCH | Physical Downlink Control Channel |
-+--------+------------------------------------------------------------+
-| PDSCH | Physical Downlink Shared Channel |
-+--------+------------------------------------------------------------+
-| PRACH | Physical Random Access Channel |
-+--------+------------------------------------------------------------+
-| PUCCH | Physical Uplink Control Channel |
-+--------+------------------------------------------------------------+
-| PUSCH | Physical Uplink Shared Channel |
-+--------+------------------------------------------------------------+
-| PTP | Precision Time Protocol |
-+--------+------------------------------------------------------------+
-| RA | Random Access |
-+--------+------------------------------------------------------------+
-| RAN | Radio Access Network |
-+--------+------------------------------------------------------------+
-| RB | Resource Block |
-+--------+------------------------------------------------------------+
-| RE | Resource Element |
-+--------+------------------------------------------------------------+
-| RU | Radio Unit |
-+--------+------------------------------------------------------------+
-| SR-IOV | Single Root Input/Output Virtualization |
-+--------+------------------------------------------------------------+
-| SW | Software |
-+--------+------------------------------------------------------------+
-| ToS | Top of the Second |
-+--------+------------------------------------------------------------+
-| UE | User Equipment |
-+--------+------------------------------------------------------------+
-| UL | Uplink |
-+--------+------------------------------------------------------------+
-| VIM | Virtual Infrastructure Manager |
-+--------+------------------------------------------------------------+
-| VLAN | Virtual Local Area Network |
-+--------+------------------------------------------------------------+
-| xRAN | Extensible Radio Access Network |
-+--------+------------------------------------------------------------+
-
-Reference Documents
--------------------
-
-Table 2. Reference Documents
-
-+----------------------------------+--------------------------------------------------------------------------------+
-| Document or Reference | Document No./ |
-| | Location |
-+----------------------------------+--------------------------------------------------------------------------------+
-| 3GPP\* specification series | http://www.3gpp.org/DynaReport/38-series.htm |
-+----------------------------------+----------------------------------+---------------------------------------------+
-| Wolf Pass Server Documentation | https://ark.intel.com/products/codename/80739/Wolf-Pass |
-+----------------------------------+----------------------------------+---------------------------------------------+
-| *Intel® C++ Compiler | https://software.intel.com/en-us/system-studio/choose-download |
-| system Studio XE* | |
-+----------------------------------+--------------------------------------------------------------------------------+
-| DPDK documentation | http://dpdk.org/doc/guides/ |
-+----------------------------------+--------------------------------------------------------------------------------+
-| O-RAN Fronthaul Working Group | https://www.o-ran.org/specifications |
-| Control, User and | |
-| Synchronization Plane | |
-| Specification | |
-| (ORAN-WG4.CUS.0-v02.00) | |
-+----------------------------------+--------------------------------------------------------------------------------+
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+.. |br| raw:: html\r
+\r
+ <br />\r
+\r
+O-DU Low Project Introduction\r
+================================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel Architecture. This 5GNR Reference PHY consists of a L1 binary \\r
+and three kinds of interfaces which are validated on a Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \\r
+5GNR L1 features. It implements the relevant functions described in [3GPP TS 38.211, 212, 213, 214 and 215].\r
+ \r
+The L1 has three \ \r
+interfaces to communicate with other network functions as described below:\r
+\r
+* Interface between L1 and Front Haul, it adopts the WG4 specification for the CUS plane communication. \r
+\r
+* Interface between O-DU Low and O-DU High, it adopts the FAPI interface according to the WG8 AAL specification.\r
+\r
+* Interface between O-DU Low and accelerator, DPDK BBDev was adopted as original contribution, it will follow the WG6 definition after the WG6 specification is finalized. \r
+\r
+The following figure shows the ORAN O-CU, O-DU and O-RU blocks for a gNB implemetation. The O-DU Low projects implements the FAPI interface by a 5G FAPI TM module, the OFH-U and OFH-C\r
+by means of the FHI Library and the functionality of the High-PHY and a test MAC are available through github in the form of a binary blob for the current release. For the details refer to the Running L1 and Testmac section of this document \r
+\r
+\r
+.. image:: images/ORAN_OCU_ODU_ORU.jpg\r
+ :width: 600\r
+ :alt: Figure1.Oran OCU ODU and ORU Block Diagram\r
+ \r
+Scope\r
+-----\r
+\r
+In this O-DU Low document, the details on how the build the modules supporting each interface, how to run the L1 and associated components, the architecture for each\r
+interface implementation and the release notes that describe each component release details are provided.\r
+\r
+Intended Audience\r
+-------------------\r
+\r
+The intended audience for this document are software engineers and system architects who design and develop |br|\r
+5G systems using the O-RAN Specifications.\r
+\r
+Terminology\r
+-------------\r
+\r
+Table 1. Terminology\r
+\r
++---------+-----------------------------------------------------------+\r
+| Term | Description |\r
++=========+===========================================================+\r
+| 5G NR | Fifth Generation New Radio |\r
++---------+-----------------------------------------------------------+\r
+| ACS | Access Control system |\r
++---------+-----------------------------------------------------------+\r
+| API | Application Programming Interface |\r
++---------+-----------------------------------------------------------+\r
+| BOM | Bill of Materials |\r
++---------+-----------------------------------------------------------+\r
+| CP | Cyclic Prefix |\r
++---------+-----------------------------------------------------------+\r
+| DDP | Dynamic Device Personalization |\r
++---------+-----------------------------------------------------------+\r
+| DPDK | Data Plane Development Kit |\r
++---------+-----------------------------------------------------------+\r
+| eAxC | Extended Antenna Carrier |\r
++---------+-----------------------------------------------------------+\r
+| eCPRI | Enhanced Common Public Radio Interface |\r
++---------+-----------------------------------------------------------+\r
+| eNB | Enode B |\r
++---------+-----------------------------------------------------------+\r
+| ETH | Ethernet |\r
++---------+-----------------------------------------------------------+\r
+| FCS | Frame Check Sequence |\r
++---------+-----------------------------------------------------------+\r
+| FEC | Forward Error Correction |\r
++---------+-----------------------------------------------------------+\r
+| FFT | Fast Fourier Transform |\r
++---------+-----------------------------------------------------------+\r
+| FH | Front Haul |\r
++---------+-----------------------------------------------------------+\r
+| gNB | Next-generation NodeB also named as Base Station |\r
++---------+-----------------------------------------------------------+\r
+| GNSS | Global Navigation Satellite System |\r
++---------+-----------------------------------------------------------+\r
+| GPS | Global Positioning System |\r
++---------+-----------------------------------------------------------+\r
+| HARQ | Hybrid Automatic Repeat Request |\r
++---------+-----------------------------------------------------------+\r
+| HW | Hardware |\r
++---------+-----------------------------------------------------------+\r
+| IFG | Interframe Gap |\r
++---------+-----------------------------------------------------------+\r
+| IFFT | Inverse Fast Fourier Transform |\r
++---------+-----------------------------------------------------------+\r
+| IoT | Inter-Operability Testing |\r
++---------+-----------------------------------------------------------+\r
+| IQ | In-band and Quadrature |\r
++---------+-----------------------------------------------------------+\r
+| LAA | License Assisted Access |\r
++---------+-----------------------------------------------------------+\r
+| LTE | Long Term Evolution |\r
++---------+-----------------------------------------------------------+\r
+| MAC | Media Access Control |\r
++---------+-----------------------------------------------------------+\r
+| MEC | Mobile Edge Computing |\r
++---------+-----------------------------------------------------------+\r
+| M-Plane | Management Plane |\r
++---------+-----------------------------------------------------------+\r
+| mmWave | Millimeter Wave |\r
++---------+-----------------------------------------------------------+\r
+| NIC | Network Interface Controller |\r
++---------+-----------------------------------------------------------+\r
+| O-DU | O-RAN Distributed Unit: a logical node hosting |\r
+| | RLC/MAC/High-PHY layers based on a lower layer functional |\r
+| | split. |\r
++---------+-----------------------------------------------------------+\r
+| O-RU | O-RAN Radio Unit: a logical node hosting Low-PHY layer |\r
+| | and RF processing based on a lower layer functional |\r
+| | split. This is similar to 3GPP’s “TRP” or “RRH” but more |\r
+| | specific in including the Low-PHY layer (FFT/IFFT, PRACH |\r
+| | extraction). |\r
++---------+-----------------------------------------------------------+\r
+| OWD | One Way Delay |\r
++---------+-----------------------------------------------------------+\r
+| PDCCH | Physical Downlink Control Channel |\r
++---------+-----------------------------------------------------------+\r
+| PDSCH | Physical Downlink Shared Channel |\r
++---------+-----------------------------------------------------------+\r
+| PHC | Physical Hardware Clock |\r
++---------+-----------------------------------------------------------+\r
+| PHP | Hypetext Preprocessor |\r
++---------+-----------------------------------------------------------+\r
+| PMD | Poll Mode Driver |\r
++---------+-----------------------------------------------------------+\r
+| POSIX | Portable Operating System Interface |\r
++---------+-----------------------------------------------------------+\r
+| PRACH | Physical Random Access Channel |\r
++---------+-----------------------------------------------------------+\r
+| PRB | Physical Resource Block |\r
++---------+-----------------------------------------------------------+\r
+| PRTC | Protected Real Time Clock |\r
++---------+-----------------------------------------------------------+\r
+| PUCCH | Physical Uplink Control Channel |\r
++---------+-----------------------------------------------------------+\r
+| PUSCH | Physical Uplink Shared Channel |\r
++---------+-----------------------------------------------------------+\r
+| PTP | Precision Time Protocol |\r
++---------+-----------------------------------------------------------+\r
+| RA | Random Access |\r
++---------+-----------------------------------------------------------+\r
+| RAN | Radio Access Network |\r
++---------+-----------------------------------------------------------+\r
+| RB | Resource Block |\r
++---------+-----------------------------------------------------------+\r
+| RE | Resource Element |\r
++---------+-----------------------------------------------------------+\r
+| RLC | Radio Link Control |\r
++---------+-----------------------------------------------------------+\r
+| RoE | Radio over Ethernet |\r
++---------+-----------------------------------------------------------+\r
+| RT | Real Time |\r
++---------+-----------------------------------------------------------+\r
+| RTE | Real Time Environment |\r
++---------+-----------------------------------------------------------+\r
+| RSS | Receive Side Scaling |\r
++---------+-----------------------------------------------------------+\r
+| RU | Radio Unit |\r
++---------+-----------------------------------------------------------+\r
+| SR-IOV | Single Root Input/Output Virtualization |\r
++---------+-----------------------------------------------------------+\r
+| SW | Software |\r
++---------+-----------------------------------------------------------+\r
+| SyncE | Synchronous Ethernet |\r
++---------+-----------------------------------------------------------+\r
+| TDD | Time Division Duplex |\r
++---------+-----------------------------------------------------------+\r
+| ToS | Top of the Second |\r
++---------+-----------------------------------------------------------+\r
+| TSC | Time Stamp Counter |\r
++---------+-----------------------------------------------------------+\r
+| TTI | Transmission Time Interval |\r
++---------+-----------------------------------------------------------+\r
+| UE | User Equipment |\r
++---------+-----------------------------------------------------------+\r
+| UL | Uplink |\r
++---------+-----------------------------------------------------------+\r
+| VF | Virtual Function |\r
++---------+-----------------------------------------------------------+\r
+| VIM | Virtual Infrastructure Manager |\r
++---------+-----------------------------------------------------------+\r
+| VLAN | Virtual Local Area Network |\r
++---------+-----------------------------------------------------------+\r
+| VM | Virtual Machine |\r
++---------+-----------------------------------------------------------+\r
+| WLS | Wireless Subsystem Interface |\r
++---------+-----------------------------------------------------------+\r
+| xRAN | Extensible Radio Access Network |\r
++---------+-----------------------------------------------------------+\r
+\r
+Reference Documents\r
+-------------------\r
+\r
+Table 2. Reference Documents\r
+\r
++----------------------------------+----------------------------------+\r
+| Document | Document |\r
+| | No./Location |\r
++==================================+==================================+\r
+| *FlexRAN Reference Solution | 575822 |\r
+| Software Release Notes* | |\r
++----------------------------------+----------------------------------+\r
+| *FlexRAN Reference Solution L1 | 571741 |\r
+| XML Configuration User Guide* | |\r
++----------------------------------+----------------------------------+\r
+| *FlexRAN Reference Solution LTE | 571742 |\r
+| eNB L2-L1 Application | |\r
+| Programming Interface [API] | |\r
+| Specification* | |\r
++----------------------------------+----------------------------------+\r
+| *FlexRAN Reference Solution | 576423 |\r
+| L2-L1 nFAPI Specification* | |\r
++----------------------------------+----------------------------------+\r
+| *FlexRAN and Mobile Edge Compute | 575891 |\r
+| (MEC) Platform Setup Guide* | |\r
++----------------------------------+----------------------------------+\r
+| *FlexRAN 5G NR Reference | 603577 |\r
+| Solution RefPHY (Doxygen).* | |\r
++----------------------------------+----------------------------------+\r
+| *Intel® Ethernet Controller | 617015 |\r
+| E810* | |\r
+| | |\r
+| *Dynamic Device Personalization | |\r
+| (DDP)* | |\r
+| | |\r
+| *Technology Guide* | |\r
++----------------------------------+----------------------------------+\r
+| *3GPP\* specification series* | https://www.3gpp.org |\r
+| | dynareport/SpecList.htm |\r
+| | ?release=Rel-15&tech=3&ts=1&tr=1 |\r
++----------------------------------+----------------------------------+\r
+| *Wolf Pass Server Documentation* | https://ark.intel.com/products/ |\r
+| | codename/80739/Wolf-Pass |\r
++----------------------------------+----------------------------------+\r
+| *Intel® C++ Compiler in Intel® | https://software.intel.com/ |\r
+| Parallel Studio XE* | en-us/c-compilers/ipsxe |\r
++----------------------------------+----------------------------------+\r
+| *DPDK documentation* | http://dpdk.org/doc/guides/ |\r
++----------------------------------+----------------------------------+\r
+| *O-RAN Fronthaul Working Group | https://www.o-ran.org/ |\r
+| Control, User and | specifications |\r
+| Synchronization Plane | |\r
+| Specification | |\r
+| (ORAN-WG4.CUS.0-v04.00)* | |\r
++----------------------------------+----------------------------------+\r
+| *ORAN Specification* | https://www.o-ran.org/ |\r
+| | adopter-license |\r
++----------------------------------+----------------------------------+\r
+| *IEEE-1588-2008 IEEE Standard | https://standards.ieee.org/ |\r
+| for a Precision Clock | standard/1588-2008.html |\r
+| Synchronization Protocol for | |\r
+| Networked Measurement and | |\r
+| Control Systems* | |\r
++----------------------------------+----------------------------------+\r
+| *eCPRI Specification V2.0 | http://www.cpri.info/spec.html |\r
+| Interface Specification* | |\r
++----------------------------------+----------------------------------+\r
+\r
+\r
+\r
-.. Copyright (c) 2019 Intel
-..
-.. Licensed under the Apache License, Version 2.0 (the "License");
-.. you may not use this file except in compliance with the License.
-.. You may obtain a copy of the License at
-..
-.. http://www.apache.org/licenses/LICENSE-2.0
-..
-.. Unless required by applicable law or agreed to in writing, software
-.. distributed under the License is distributed on an "AS IS" BASIS,
-.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-.. See the License for the specific language governing permissions and
-.. limitations under the License.
-
-.. |br| raw:: html
-
- <br />
-
-xRAN Library Design
-===================
-
-.. contents::
- :depth: 3
- :local:
-
-The xRAN Library consists of multiple modules where different
-functionality is encapsulated. The complete list of all \*.c and \*.h
-files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is:
-
-├── app
-
-│ ├── dpdk.sh
-
-│ ├── gen_test.m
-
-│ ├── Makefile
-
-│ ├── src
-
-│ │ ├── common.c
-
-│ │ ├── common.h
-
-│ │ ├── config.c
-
-│ │ ├── config.h
-
-│ │ ├── debug.h
-
-│ │ ├── sample-app.c
-
-│ │ └── xran_mlog_task_id.h
-
-│ └── usecase
-
-│ ├── cat_b
-
-│ ├── lte_a
-
-│ ├── lte_b
-
-│ ├── mu0_10mhz
-
-│ ├── mu0_20mhz
-
-│ ├── mu0_5mhz
-
-│ ├── mu1_100mhz
-
-│ └── mu3_100mhz
-
-├── banner.txt
-
-├── build.sh
-
-├── lib
-
-│ ├── api
-
-│ │ ├── xran_compression.h
-
-│ │ ├── xran_compression.hpp
-
-│ │ ├── xran_cp_api.h
-
-│ │ ├── xran_fh_o_du.h
-
-│ │ ├── xran_mlog_lnx.h
-
-│ │ ├── xran_pkt_cp.h
-
-│ │ ├── xran_pkt.h
-
-│ │ ├── xran_pkt_up.h
-
-│ │ ├── xran_sync_api.h
-
-│ │ ├── xran_timer.h
-
-│ │ ├── xran_transport.h
-
-│ │ └── xran_up_api.h
-
-│ ├── ethernet
-
-│ │ ├── ethdi.c
-
-│ │ ├── ethdi.h
-
-│ │ ├── ethernet.c
-
-│ │ └── ethernet.h
-
-│ ├── Makefile
-
-│ └── src
-
-│ ├── xran_app_frag.c
-
-│ ├── xran_app_frag.h
-
-│ ├── xran_bfp_cplane16.cpp
-
-│ ├── xran_bfp_cplane32.cpp
-
-│ ├── xran_bfp_cplane64.cpp
-
-│ ├── xran_bfp_cplane8.cpp
-
-│ ├── xran_bfp_ref.cpp
-
-│ ├── xran_bfp_utils.hpp
-
-│ ├── xran_common.c
-
-│ ├── xran_common.h
-
-│ ├── xran_compression.cpp
-
-│ ├── xran_cp_api.c
-
-│ ├── xran_frame_struct.c
-
-│ ├── xran_frame_struct.h
-
-│ ├── xran_lib_mlog_tasks_id.h
-
-│ ├── xran_main.c
-
-│ ├── xran_printf.h
-
-│ ├── xran_sync_api.c
-
-│ ├── xran_timer.c
-
-│ ├── xran_transport.c
-
-│ ├── xran_ul_tables.c
-
-│ └── xran_up_api.c
-
-├── Licenses.txt
-
-├── readme.md
-
-└── test
-
- ├── common
-
- │ ├── common.cpp
-
- │ ├── common.hpp
-
- │ ├── common_typedef_xran.h
-
- │ ├── json.hpp
-
- │ ├── MIT_License.txt
-
- │ ├── xranlib_unit_test_main.cc
-
- │ └── xran_lib_wrap.hpp
-
- ├── master.py
-
- ├── readme.txt
-
- └── test_xran
-
- ├── chain_tests.cc
-
- ├── compander_functional.cc
-
- ├── conf.json
-
- ├── c_plane_tests.cc
-
- ├── init_sys_functional.cc
-
- ├── Makefile
-
- ├── prach_functional.cc
-
- ├── prach_performance.cc
-
- ├── unittests.cc
-
- └── u_plane_functional.cc
-
-
-General Introduction
---------------------
-
-The xRAN Library functionality is broken down into two main sections:
-
-- XRAN specific packet handling (src)
-
-- Ethernet and supporting functionality (Ethernet)
-
-External functions and structures are available via set of header files
-in the API folder.
-
-This library depends on DPDK primitives to perform Ethernet networking
-in userspace, including initialization and control of Ethernet ports.
-Ethernet ports are expected to be SRIOV virtual functions (VF) but also
-can be physical functions (PF) as well.
-
-This library is expected to be included in the project via
-xran_fh_o_du.h, statically compiled and linked with the L1 application
-as well as DPDK libraries. The xRAN packet processing-specific
-functionality is encapsulated into this library and not exposed to the
-rest of the 5G NR pipeline.
-
-This way, xRAN specific changes are decoupled from the 5G NR L1
-pipeline. As a result, the design and implementation of the 5G L1
-pipeline code and xRAN library can be done in parallel, provided the
-defined interface is not modified.
-
-Ethernet consists of two modules:
-
-- Ethernet implements xRAN specific HW Ethernet initialization, close,
- send and receive
-
-- ethdi provides Ethernet level software primitives to handle xRAN
- packet exchange
-
-The xRAN layer implements the next set of functionalities:
-
-- Common code specific for both C-plane and U-plane as well as TX and
- RX
-
-- Implementation of C-plane API available within the library and
- externally
-
-- The primary function where general library initialization and
- configuration performed
-
-- Module to provide the status of PTP synchronization
-
-- Timing module where system time is polled
-
-- eCPRI specific transport layer functions
-
-- APIs to handle U-plane packets
-
-- A set of utility modules for debugging (printf) and data tables are
- included as well.
-
-.. image:: images/Illustration-of-xRAN-Sublayers.jpg
- :width: 600
- :alt: Figure 24. Illustration of xRAN Sublayers
-
-Figure 24. Illustration of xRAN Sublayers
-
-A detailed description of functions and input/output arguments, as well
-as key data structures, can be found in the Doxygen file for the FlexRAN
-5G NR release. In this document supplemental information is provided
-with respect to the overall design and implementation assumptions.
-
-Initialization and Close
-------------------------
-
-An example of the initialization sequence can be found in the sample
-application code. It consists of the following steps:
-
-1.Setup structure struct xran_fh_init according to configuration.
-
-2.Call xran_init() to instantiate the xRAN lib memory model and
-threads. The function returns a pointer to xRAN handle which is used
-for consecutive configuration functions.
-
-3.Initialize memory buffers used for L1 and xRAN exchange of
-information.
-
-4.Assign callback functions for (one) TTI event and for the reception
-of half of the slot of symbols (7 symbols) and Full slot of symbols
-14 symbols).
-
-5.Call xran_open() to initialize PRACH configuration, initialize DPDK,
-and launch xRAN timing thread.
-
-6.Call xran_start() to start processing xRAN packets for DL and UL.
-
-After this is complete 5G L1 runs with xRAN Front haul interface. During
-run time for every TTI event, the corresponding call back is called. For
-packet reception on UL direction, the corresponding call back is called.
-OTA time information such as frame id, subframe id and slot id can be
-obtained as result synchronization of the L1 pipeline to GPS time is
-performed.
-
-To stop and close the interface, perform this sequence of steps:
-
-7.Call xran_stop() to stop the processing of DL and UL.
-
-8.Call xran_close() to remove usage of xRAN resources.
-
-9.Call xran_mm_destroy() to destroy memory management subsystem.
-
-After this session is complete, a restart of the full L1 application is
-required. The current version of the library does not support multiple
-sessions without a restart of the full L1 application.
-
-Configuration
-~~~~~~~~~~~~~
-
-The xRAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config.
-The sample application gives an example of a test configuration used for LTE and 5GNR mmWave and Sub 6. Sample application
-folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B)
-and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz).
-
-Some configuration options are not used in the Bronze Release and are reserved
-for future use.
-
-The following options are available:
-
-**Structure** struct xran_fh_init\ **:**
-
-- Number of CC and corresponding settings for each
-
-- Core allocation for xRAN
-
-- Ethernet port allocation
-
-- O-DU and RU Ethernet Mac address
-
-- Timing constraints of O-DU and 0-RU
-
-- Debug features
-
-**Structure** struct xran_fh_config\ **:**
-
-- Number of eAxC
-
-- TTI Callback function and parameters
-
-- PRACH 5G NR specific settings
-
-- TDD frame configuration
-
-- BBU specific configuration
-
-- RU specific configuration
-
-**From an implementation perspective:**
-
-xran_init() performs init of the xRAN library and interface according to
-struct xran_fh_init information as per the start of application
-configuration.:
-
-- Init DPDK with corresponding networking ports and core assignment
-
-- Init mbuf pools
-
-- Init DPDK timers and DPDK rings for internal packet processing
-
-- Instantiate ORAN FH thread doing
-
- - Timing processing (xran_timing_source_thread())
-
- - ETH PMD (process_dpdk_io())
-
- - IO XRAN-PHY exchange (ring_processing_func())
-
-**xran_open()** performs additional configuration as per run scenario:
-
-- PRACH configuration
-
-- C-plane initialization
-
-The Function **xran_close()** performs free of resources and allows potential
-restart of front haul interface with a different scenario.
-
-Start/Stop
-~~~~~~~~~~
-
-The Functions **xran_start()/xran_stop()** enable/disable packet processing for
-both DL and UL. This triggers execution of callbacks into the L1
-application.
-
-Data Exchange
-~~~~~~~~~~~~~
-
-Exchange of IQ samples, as well as C-plane specific information, is
-performed using a set of buffers allocated by xRAN library from DPDK
-memory and shared with the l1 application. Buffers are allocated as a
-standard mbuf structure and DPDK pools are used to manage the allocation
-and free resources. Shared buffers are allocated at the init stage and
-are expected to be reused within 80 TTIs (10 ms).
-
-The xRAN protocol requires U-plane IQ data to be transferred in network
-byte order, and the L1 application handles IQ sample data in CPU byte
-order, requiring a swap. The PHY BBU pooling tasks perform copy and byte
-order swap during packet processing.
-
-C-plane Information Settings
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The interface between the xRAN library and PHY is defined via struct
-xran_prb_map and similar to the data plane. The same mbuf memory is used
-to allocate memory map of PRBs for each TTI.
-
-/\* Beamforming waights for single stream for each PRBs given number of Antenna elements \*/
-struct xran_cp_bf_weight{
-
- int16_t nAntElmTRx; /\*< num TRX for this allocation \*/
- int8_t* p_ext_start; /\*< pointer to start of buffer for full C-plane packet \*/
- int8_t* p_ext_section; /\*< pointer to form extType \*/
- int16_t ext_section_sz; /\*< extType section size \*/
-
-/\* section descriptor for given number of PRBs used on U-plane packet creation \*/
-struct xran_section_desc {
-
- uint16_t section_id; /\*< section id used for this element \*/
-
- int16_t iq_buffer_offset; /\*< Offset in bytes for the content of IQs with in main symb buffer \*/
- int16_t iq_buffer_len; /\*< Length in bytes for the content of IQs with in main symb buffer \*/
-
- uint8_t \*pData; /\*< optional pointer to data buffer \*/
- void \*pCtrl; /\*< optional poitner to mbuf \*/
-
-};
-
-struct xran_prb_elm {
- int16_t nRBStart; /\*< start RB of RB allocation \*/
- int16_t nRBSize; /\*< number of RBs used \*/
- int16_t nStartSymb; /\*< start symbol ID \*/
- int16_t numSymb; /\\*< number of symbols \*/
- int16_t nBeamIndex; /\*< beam index for given PRB \*/
- int16_t bf_weight_update; /\* need to update beam weights or not \*/
- int16_t compMethod; /\*< compression index for given PRB \*/
- int16_t iqWidth; /\*< compression bit width for given PRB \*/
- int16_t BeamFormingType; /\*< index based, weights based or attribute based beam forming\*/
-
- struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /\*< section desctiptors to U-plane data given RBs \*/
- struct xran_cp_bf_weight bf_weight; /\*< beam forming information relevant for given RBs \*/
-
- union {
- struct xran_cp_bf_attribute bf_attribute;
- struct xran_cp_bf_precoding bf_precoding;
-
- };
-
-/\* PRB map structure \*/
-
-struct xran_prb_map {
- uint8_t dir; /\*< DL or UL direction \*/
- uint8_t xran_port; /\*< xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/
- uint16_t band_id; /\*< xran band id \*/
- uint16_t cc_id; /\*< componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)] \*/
- uint16_t ru_port_id; /\*< RU device antenna port id [0 - (XRAN_MAX_ANTENNA_NR-1) \*/
- uint16_t tti_id; /\*< xRAN slot id [0 - (max tti-1)] \*/
- uint8_t start_sym_id; /\*< start symbol Id [0-13] \*/
- uint32_t nPrbElm; /\*< total number of PRB elements for given map [0- (XRAN_MAX_PRBS-1)] \*/
- struct xran_prb_elm prbMap[XRAN_MAX_PRBS];
-
-};
-
-
-For the Bronze release C-plane sections are expected to be provided by L1
-pipeline. If 100% of RBs always allocated single element of RB map
-is expected to be allocated across all symbols. Dynamic RB allocation is
-performed base on C-plane configuration.
-
-The xRAN library will require that the content of the PRB map should be
-sorted in increasing order of PRB first and then symbols.
-
-Memory Management
------------------
-
-Memory used for the exchange of IQ data as well as control information,
-is controlled by the xRAN library. L1 application at the init stage
-performs:
-
-- init memory management subsystem
-
-- init buffer management subsystem (via DPDK pools)
-
-- allocate buffers (mbuf) for each CC, antenna, symbol, and direction \
- (DL, UL, PRACH) for XRAN_N_FE_BUF_LEN TTIs.
-
-- buffers are reused for every XRAN_N_FE_BUF_LEN TTIs
-
-After the session is completed, the application can free buffers and
-destroy the memory management subsystem.
-
-From an implementation perspective, the xRAN library uses a standard
-mbuf primitive and allocates a pool of buffers for each sector. This
-function is performed using rte_pktmbuf_pool_create(),
-rte_pktmbuf_alloc(), rte_pktmbuf_append() to allocate one buffer per
-symbol for the mmWave case. More information on mbuf and DPDK pools can
-be found in the DPDK documentation.
-
-In the current implementation, mbuf, the number of buffers shared with
-the L1 application is the same number of buffers used to send to and
-receive from the Ethernet port. Memory copy operations are not required
-if the packet size is smaller than or equal to MTU. Future versions of
-the xRAN library are required to remove the memory copy requirement for
-packets where the size larger than MTU.
-
-External Interface Memory
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The xRAN library header file defines a set of structures to simplify
-access to memory buffers used for IQ data.
-
-struct xran_flat_buffer {
-
-uint32_t nElementLenInBytes;
-
-uint32_t nNumberOfElements;
-
-uint32_t nOffsetInBytes;
-
-uint32_t nIsPhyAddr;
-
-uint8_t \*pData;
-
-void \*pCtrl;
-
-};
-
-struct xran_buffer_list {
-
-uint32_t nNumBuffers;
-
-struct xran_flat_buffer \*pBuffers;
-
-void \*pUserData;
-
-void \*pPrivateMetaData;
-
-};
-
-typedef struct {
-
-int32_t bValid ;
-
-int32_t nSegToBeGen;
-
-int32_t nSegGenerated;
-
-int32_t nSegTransferred;
-
-struct rte_mbuf \*pData[N_MAX_BUFFER_SEGMENT];
-
-struct xran_buffer_list sBufferList;
-
-} BbuIoBufCtrlStruct;
-
-There is no explicit requirement for user to organize a set of buffers
-in this particular way. From a compatibility |br|
-perspective it is useful to
-follow the existing design of the 5G NR l1app used for Front Haul FPGA
-and define structures shared between l1 and xRAN lib as shown:
-
-/\* io struct \*/
-
-BbuIoBufCtrlStruct
-sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR]\
-[XRAN_MAX_ANTENNA_NR];
-
-BbuIoBufCtrlStruct
-sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
-
-BbuIoBufCtrlStruct
-sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
-
-BbuIoBufCtrlStruct
-sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
-
-BbuIoBufCtrlStruct
-sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];
-
-/\* Cat B \*/
-
-BbuIoBufCtrlStruct
-sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];
-
-/\* buffers list \*/
-
-struct xran_flat_buffer
-sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
-
-struct xran_flat_buffer
-sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
-
-struct xran_flat_buffer
-sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
-
-struct xran_flat_buffer
-sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
-
-struct xran_flat_buffer
-sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];
-
-/\* Cat B SRS buffers \*/
-
-struct xran_flat_buffer
-sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];
-
-Doxygen file and xran_fh_o_du.h provide more details on the definition
-and usage of these structures.
-
-xRAN Specific Functionality
----------------------------
-
-Front haul interface implementation in the general case is abstracted
-away using the interface defined in xran_fh_o_du.h
-
-The L1 application is not required to access xRAN protocol primitives
-(eCPRI header, application header, and others) directly. It is
-recommended to use the interface to remove dependencies between
-different software modules such as the l1 pipeline and xRAN library.
-
-External API
-~~~~~~~~~~~~
-
-The U-plane and C-plane APIs can be used directly from the application
-if such an option is required. The set of header files can be exported
-and called directly.
-
-xran_fh_o_du.h – xRAN main header file for O-DU scenario
-
-xran_cp_api.h – Control plane functions
-
-xran_pkt_cp.h – xRAN control plane packet definition
-
-xran_pkt.h – xRAN packet definition
-
-xran_pkt_up.h – xRAN User plane packet definition
-
-xran_sync_api.h – api functions to check PTP status
-
-xran_timer.h – API for timing
-
-xran_transport.h – eCPRI transport layer definition and api
-
-xran_up_api.h – user plane functions and definitions
-
-xran_compression.h – interface to compression/decompression functions
-
-Doxygen files provide detailed information on functions and structures
-available.
-
-.. _c-plane-1:
-
-C-plane
-~~~~~~~
-
-Implementation of the C-plane set of functions is defined in
-xran_cp_api.c and is used to prepare the content of C-plane packets
-according to the given configuration. Users can enable/disable
-generation of C-plane messages using enableCP field in struct
-xran_fh_init structure during init of ORAN front haul. The time of
-generation of C-plane message for DL and UL is done “Slot-based,” and
-timing can be controlled using O-DU settings according to Table 4.
-
-The C-plane module contains:
-
-- initialization of C-plane database to keep track of allocation of
- resources
-
-- code to prepare C-plane packet for TX (O-DU)
-
-- eCPRI header
-
-- append radio application header
-
-- append control section header
-
-- append control section
-
-- parser of C-plane packet for RX (O-RU emulation)
-
-- parses and checks Section 1 and Section 3 packet content
-
-Sending and receiving packets is performed using xRAN ethdi sublayer
-functions.
-
-Creating a C-Plane Packet
-^^^^^^^^^^^^^^^^^^^^^^^^^
-
-API and Data Structures
-'''''''''''''''''''''''
-
-A C-Plane message can be composed using the following API:
-
-int xran_prepare_ctrl_pkt(struct rte_mbuf \*mbuf,
-
-struct xran_cp_gen_params \*params,
-
-uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id);
-
-mbuf is the pointer of a DPDK packet buffer, which is allocated from the
-caller.
-
-params are the pointer of the structure which has the parameters to
-create the message.
-
-CC_ID is the parameter to specify component carrier index, Ant_ID is the
-parameters to specify the antenna port index (RU port index).
-
-seq_id is the sequence index for the message.
-
-params, the parameters to create a C-Plane message are defined as the
-structure of xran_cp_gen_params with an |br|
-example given below:
-
-struct xran_cp_gen_params {
-
-uint8_t dir;
-
-uint8_t sectionType;
-
-uint16_t numSections;
-
-struct xran_cp_header_params hdr;
-
-struct xran_section_gen_info \*sections;
-
-};
-
-dir is the direction of the C-Plane message to be generated. Available
-parameters are defined as XRAN_DIR_UL and XRAN_DIR_DL.
-
-sectionType is the section type for C-Plane message to generate, as ORAN
-specification defines all sections in a C-Plane message shall have the
-same section type. If different section types are required, they shall
-be sent with separate C-Plane messages. Available types of sections are
-defined as XRAN_CP_SECTIONTYPE_x. Please refer to the Table 5-2 Section
-Types in chapter 5.4 of ORAN specification.
-
-numSections is the total number of sections to generate, i.e., the
-number of the array in sections (struct xran_section_gen_info).
-
-hdr is the structure to hold the information to generate the radio
-application and section header in the C-Plane message. It is defined as
-the structure of xran_cp_header_params. Not all parameters in this
-structure are used for the generation, and the required parameters are
-slightly different by the type of section, as described in Table 10 and
-Table 11.
-
-Table 10. struct xran_cp_header_params – Common Radio Application Header
-
-+------------+---------------------------------------------+---------+
-| | Description | Remarks |
-+============+=============================================+=========+
-| filterIdx | Filter Index. Available values are defined | 5.4.4.3 |
-| | as XRAN_FILTERINDEX_xxxxx. | |
-+------------+---------------------------------------------+---------+
-| frameId | Frame Index. It is modulo 256 of frame | 5.4.4.4 |
-| | number. | |
-+------------+---------------------------------------------+---------+
-| subframeId | Sub-frame Index. | 5.4.4.5 |
-+------------+---------------------------------------------+---------+
-| slotId | Slot Index. The maximum number is 15, as | 5.4.4.6 |
-| | defined in the specification. | |
-+------------+---------------------------------------------+---------+
-| startSymId | Start Symbol Index. | 5.4.4.7 |
-+------------+---------------------------------------------+---------+
-
-Table 11. struct xran_cp_header_params – Section Specific Parameters
-
-+----------+----------+----------+---------+---+---+---+---+----------+
-| | Des\ | Section | Remarks | | | | | |
-| | cription | Type | | | | | | |
-| | | ap\ | | | | | | |
-| | | plicable | | | | | | |
-+==========+==========+==========+=========+===+===+===+===+==========+
-| | | 0 | 1 | 3 | 5 | 6 | 7 | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| fftSize | FFT size | X | | X | | | | 5.4.4.13 |
-| | in frame | | | | | | | |
-| | st\ | | | | | | | |
-| | ructure. | | | | | | | |
-| | A\ | | | | | | | |
-| | vailable | | | | | | | |
-| | values | | | | | | | |
-| | are | | | | | | | |
-| | defined | | | | | | | |
-| | as | | | | | | | |
-| | X\ | | | | | | | |
-| | RAN_FFTS\| | | | | | | |
-| | IZE_xxxx | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| Scs | Su\ | X | | X | | | | 5.4.4.13 |
-| | bcarrier | | | | | | | |
-| | Spacing | | | | | | | |
-| | in the | | | | | | | |
-| | frame | | | | | | | |
-| | st\ | | | | | | | |
-| | ructure. | | | | | | | |
-| | A\ | | | | | | | |
-| | vailable | | | | | | | |
-| | values | | | | | | | |
-| | are | | | | | | | |
-| | defined | | | | | | | |
-| | as | | | | | | | |
-| | XRAN_SCS\| | | | | | | |
-| | _xxxx | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| iqWidth | I/Q bit | | X | X | X | | | 5.4.4.10 |
-| | width in | | | | | | | |
-| | user | | | | | | | 6.3.3.13 |
-| | data | | | | | | | |
-| | com\ | | | | | | | |
-| | pression | | | | | | | |
-| | header. | | | | | | | |
-| | Should | | | | | | | |
-| | be set | | | | | | | |
-| | by zero | | | | | | | |
-| | for | | | | | | | |
-| | 16bits | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| compMeth | Com\ | | X | X | X | | | 5.4.4.10 |
-| | pression | | | | | | | |
-| | Method | | | | | | | 6.3.3.13 |
-| | in user | | | | | | | |
-| | data | | | | | | | |
-| | com\ | | | | | | | |
-| | pression | | | | | | | |
-| | header. | | | | | | | |
-| | A\ | | | | | | | |
-| | vailable | | | | | | | |
-| | values | | | | | | | |
-| | are | | | | | | | |
-| | defined | | | | | | | |
-| | as | | | | | | | |
-| | XRAN\ | | | | | | | |
-| | _COMPMET\| | | | | | | |
-| | HOD_xxxx | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| numUEs | Number | | | | | X | | 5.4.4.11 |
-| | of UEs. | | | | | | | |
-| | Applies | | | | | | | |
-| | to | | | | | | | |
-| | section | | | | | | | |
-| | type 6 | | | | | | | |
-| | and not | | | | | | | |
-| | s\ | | | | | | | |
-| | upported | | | | | | | |
-| | in this | | | | | | | |
-| | release. | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| ti\ | Time | X | | X | | | | 5.4.4.12 |
-| meOffset | Offset. | | | | | | | |
-| | Time | | | | | | | |
-| | offset | | | | | | | |
-| | from the | | | | | | | |
-| | start of | | | | | | | |
-| | the slot | | | | | | | |
-| | to start | | | | | | | |
-| | of | | | | | | | |
-| | Cyclic | | | | | | | |
-| | Prefix. | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-| cpLength | Cyclic | X | | X | | | | 5.4.4.14 |
-| | Prefix | | | | | | | |
-| | Length. | | | | | | | |
-+----------+----------+----------+---------+---+---+---+---+----------+
-
-**Only sections types 1 and 3 are supported in the current release.**
-
-Sections are the pointer to the array of structure which has the
-parameters for section(s) and it is defined as below:
-
-struct xran_section_gen_info {
-
-struct xran_section_info info;
-
-uint32_t exDataSize;
-
-struct {
-
-uint16_t type;
-
-uint16_t len;
-
-void \*data;
-
-} exData[XRAN_MAX_NUM_EXTENSIONS];
-
-};
-
-info is the structure to hold the information to generate section and it
-is defined as the structure of xran_section_info. Like
-xran_cp_header_params, all parameters are not required to generate
-section and Table 12 describes which |br|
-parameters are required for each
-section.
-
-Table 12. Parameters for Sections
-
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| | D\ | Se\ | Re\ | | | | |
-| | escri\| ction | marks | | | | |
-| | ption | Type | | | | | |
-| | | appli\| | | | | |
-| | | cable | | | | | |
-+=======+=======+=======+=======+=======+=======+=======+=======+
-| | | 0 | 1 | 3 | 5 | 6 | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| Id | Se\ | **X** | **X** | **X** | **X** | **X** | 5.\ |
-| | ction | | | | | | 4.5.1 |
-| | I\ | | | | | | |
-| | denti\| | | | | | |
-| | fier. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| Rb | Res\ | **X** | **X** | **X** | **X** | **X** | 5.\ |
-| | ource | | | | | | 4.5.2 |
-| | Block\| | | | | | |
-| | Indic\| | | | | | |
-| | ator. | | | | | | |
-| | Avai\ | | | | | | |
-| | lable | | | | | | |
-| | v\ | | | | | | |
-| | alues | | | | | | |
-| | are | | | | | | |
-| | de\ | | | | | | |
-| | fined | | | | | | |
-| | as | | | | | | |
-| | XRAN\ | | | | | | |
-| | _\ | | | | | | |
-| | RBI\ | | | | | | |
-| | ND_xx\| | | | | | |
-| | xx. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| s\ | S\ | **X** | **X** | **X** | **X** | **X** | 5.\ |
-| ymInc | ymbol | | | | | | 4.5.3 |
-| | n\ | | | | | | |
-| | umber | | | | | | |
-| | Incr\ | | | | | | |
-| | ement | | | | | | |
-| | com\ | | | | | | |
-| | mand. | | | | | | |
-| | Avai\ | | | | | | |
-| | lable | | | | | | |
-| | v\ | | | | | | |
-| | alues | | | | | | |
-| | are | | | | | | |
-| | de\ | | | | | | |
-| | fined | | | | | | |
-| | as | | | | | | |
-| | XRA\ | | | | | | |
-| | N_SYM\| | | | | | |
-| | BOL\ | | | | | | |
-| | NUMBE\| | | | | | |
-| | R_xx\ | | | | | | |
-| | xx. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| star\ | Sta\ | **X** | **X** | **X** | **X** | **X** | 5.\ |
-| tPrbc | rting\| | | | | | 4.5.4 |
-| | PRB | | | | | | |
-| | of | | | | | | |
-| | data | | | | | | |
-| | se\ | | | | | | |
-| | ction | | | | | | |
-| | de\ | | | | | | |
-| | scrip\| | | | | | |
-| | tion. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| nu | The | **X** | **X** | **X** | **X** | **X** | 5.\ |
-| mPrbc | n\ | | | | | | 4.5.6 |
-| | umber | | | | | | |
-| | of | | | | | | |
-| | conti\| | | | | | |
-| | guous | | | | | | |
-| | PRBs | | | | | | |
-| | per | | | | | | |
-| | data | | | | | | |
-| | se\ | | | | | | |
-| | ction | | | | | | |
-| | de\ | | | | | | |
-| | scrip\| | | | | | |
-| | tion. | | | | | | |
-| | When | | | | | | |
-| | nu\ | | | | | | |
-| | mPrbc | | | | | | |
-| | is | | | | | | |
-| | gr\ | | | | | | |
-| | eater | | | | | | |
-| | than | | | | | | |
-| | 255, | | | | | | |
-| | it | | | | | | |
-| | will | | | | | | |
-| | be | | | | | | |
-| | conv\ | | | | | | |
-| | erted | | | | | | |
-| | to | | | | | | |
-| | zero | | | | | | |
-| | by | | | | | | |
-| | the | | | | | | |
-| | macro | | | | | | |
-| | (XR\ | | | | | | |
-| | AN_CO\| | | | | | |
-| | NVERT\| | | | | | |
-| | _NUMP\| | | | | | |
-| | RBC). | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| r\ | Res\ | **X** | **X** | **X** | **X** | | 5.\ |
-| eMask | ource\| | | | | | 4.5.5 |
-| | El\ | | | | | | |
-| | ement\| | | | | | |
-| | Mask. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| numS\ | N\ | **X** | **X** | **X** | **X** | | 5.\ |
-| ymbol | umber | | | | | | 4.5.7 |
-| | of | | | | | | |
-| | Sym\ | | | | | | |
-| | bols. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| b\ | Beam\ | | **X** | **X** | | | 5.\ |
-| eamId | I\ | | | | | | 4.5.9 |
-| | denti\| | | | | | |
-| | fier. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| freqO\| Freq\ | | | **X** | | | 5.4\ |
-| ffset | uency\| | | | | | .5.11 |
-| | Of\ | | | | | | |
-| | fset. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| ueId | UE\ | | | | **X** | **X** | 5.4\ |
-| | i\ | | | | | | .5.10 |
-| | denti\| | | | | | |
-| | fier. | | | | | | |
-| | Not | | | | | | |
-| | supp\ | | | | | | |
-| | orted | | | | | | |
-| | in | | | | | | |
-| | this | | | | | | |
-| | rel\ | | | | | | |
-| | ease. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| regF\ | Regu\ | | | | | **X** | 5.4\ |
-| actor | lariz\| | | | | | .5.12 |
-| | ation | | | | | | |
-| | Fa\ | | | | | | |
-| | ctor. | | | | | | |
-| | Not | | | | | | |
-| | supp\ | | | | | | |
-| | orted | | | | | | |
-| | in | | | | | | |
-| | this | | | | | | |
-| | re\ | | | | | | |
-| | lease | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-| Ef | Exte\ | | **X** | **X** | **X** | **X** | 5.\ |
-| | nsion | | | | | | 4.5.8 |
-| | Flag. | | | | | | |
-| | Not | | | | | | |
-| | supp\ | | | | | | |
-| | orted | | | | | | |
-| | in | | | | | | |
-| | this | | | | | | |
-| | rel\ | | | | | | |
-| | ease. | | | | | | |
-+-------+-------+-------+-------+-------+-------+-------+-------+
-
-**Only sections types 1 and 3 are supported in the current release.**
-
-**The xran_section_info has more parameters – type, startSymId, iqWidth,
-compMeth. These are the same parameters as those of radio application
-or section header but need to be copied into this structure again for
-the section data base.**
-
-exDataSize and exData are used to add section extensions for the
-section.
-
-exDataSize is the number of elements in the exData array. The maximum
-number of elements is defined as XRAN_MAX_NUM_EXTENSIONS and it is
-defined by four in this release with the assumption that four different
-types of section extensions can be added to a section (section extension
-type 3 is excluded since it is not supported). exData.type is the type
-of section extension and exData.len is the length of structure of
-section extension parameter in exData.data. exData.data is the pointer
-to the structure of section extensions and different structures are used
-by the type of section extensions like below.
-
-struct xran_sectionext1_info {
-
-uint16_t rbNumber; /* number RBs to ext1 chain \*/
-
-uint16_t bfwNumber; /* number of bf weights in this section \*/
-
-uint8_t bfwiqWidth;
-
-uint8_t bfwCompMeth;
-
-int16_t \*p_bfwIQ; /* pointer to formed section extention \*/
-
-int16_t bfwIQ_sz; /* size of buffer with section extention information
-\*/
-
-union {
-
-uint8_t exponent;
-
-uint8_t blockScaler;
-
-uint8_t compBitWidthShift;
-
-uint8_t activeBeamspaceCoeffMask[XRAN_MAX_BFW_N]; /\* ceil(N/8)*8,
-should be multiple of 8 \*/
-
-} bfwCompParam;
-
-};
-
-For section extension type 1, the structure of xran_sectionext1_info is
-used. Please note that the xRAN library will use bfwIQ (beamforming
-weight) as-is, i.e., xRAN library will not perform the compression, so
-the user should provide proper data to bfwIQ.
-
-struct xran_sectionext2_info {
-
-uint8_t bfAzPtWidth;
-
-uint8_t bfAzPt;
-
-uint8_t bfZePtWidth;
-
-uint8_t bfZePt;
-
-uint8_t bfAz3ddWidth;
-
-uint8_t bfAz3dd;
-
-uint8_t bfZe3ddWidth;
-
-uint8_t bfZe3dd;
-
-uint8_t bfAzSI;
-
-uint8_t bfZeSI;
-
-};
-
-For section extension type 2, the structure of xran_sectionext2_info is
-used. Each parameter will be packed as specified bit width.
-
-struct xran_sectionext4_info {
-
-uint8_t csf;
-
-uint8_t pad0;
-
-uint16_t modCompScaler;
-
-};
-
-For section extension type 4, the structure of xran_sectionext4_info is
-used.
-
-struct xran_sectionext5_info {
-
-uint8_t num_sets;
-
-struct {
-
-uint16_t csf;
-
-uint16_t mcScaleReMask;
-
-uint16_t mcScaleOffset;
-
-} mc[XRAN_MAX_MODCOMP_ADDPARMS];
-
-};
-
-For section extension type 5, the structure of xran_sectionext5_info is
-used. Please note that current implementation supports maximum two sets
-of additional parameters.
-
-**Section extensions type 3 is not supported since it is LTE specific.**
-
-Section Extensions are not fully verified in this release.
-
-Detail Procedures in API
-''''''''''''''''''''''''
-
-xran_prepare_ctrl_pkt() has several procedures to compose a C-Plane
-packet.
-
-1. Append transport header
-
-- Reserve eCPRI header space in the packet buffer
-
-- eCPRI version is fixed by XRAN_ECPRI_VER (0x0001)
-
-- Concatenation and transport layer fragmentation is not supported.
-
- ecpri_concat=0, ecpri_seq_id.sub_seq_id=0 and ecpri_seq_id.e_bit=1
-
-- The caller needs to provide a component carrier index, antenna index,
- and message identifier through function arguments.
-
- CC_ID, Ant_ID and seq_id
-
-- ecpriRtcid (ecpri_xtc_id) is composed with CC_ID and Ant_ID by
- xran_compose_cid.
-
-- DU port ID and band sector ID are fixed by zero in this release.
-
-- The output of xran_compose_cid is stored in network byte order.
-
-- The length of the payload is initialized by zero.
-
-2. Append radio application header:
-
-- xran_append_radioapp_header() checks the type of section through
- params->sectionType and determines proper function to append
- remaining header components.
-
-- Only section type 1 and 3 are supported, returns
- XRAN_STATUS_INVALID_PARAM for other types.
-
-- Each section uses a different function to compose the remaining
- header and size to calculate the total length in the transport
- header.
-
-For section type 1, xran_prepare_section1_hdr() and sizeof(struct
-xran_cp_radioapp_section1_header)
-
-For section type 3, xran_prepare_section3_hdr() and sizeof(struct
-xran_cp_radioapp_section3_header)
-
-- Reserves the space of common radio application header and composes
- header by xran_prepare_radioapp_common_header().
-
-- The header is stored in network byte order.
-
-- Appends remaining header components by the selected function above
-
-- The header is stored in network byte order
-
-3. Append section header and section
-
-- xran_append_control_section() determines proper size and function to
- append section header and contents.
-
-- For section type 1, xran_prepare_section1() and sizeof(struct
- xran_cp_radioapp_section1)
-
-- For section type 3, xran_prepare_section3() and sizeof(struct
- xran_cp_radioapp_section3)
-
-- Appends section header and section(s) by selected function above.
-
-- If multiple sections are configured, then those will be added.
-
-- Since fragmentation is not considered in this implementation, the
- total length of a single C-Plane message shall not exceed MTU
- size.
-
-- The header and section(s) are stored in network byte order.
-
-- Appends section extensions if it is set (ef=1)
-
-- xran_append_section_extensions() adds all configured extensions by
- its type.
-
-- xran_prepare_sectionext_x() (x = 1,2,4,5) will be called by the
- type from xran_append_section_extensions() and these functions
- will create extension field.
-
-**Example Usage of API**
-''''''''''''''''''''''''
-
-There are two reference usages of API to generate C-Plane message in
-lib/src/xran_common.c
-
-- generate_cpmsg_dlul()
-
-- generate_cpmsg_prach()
-
-generate_cpmsg_dlul() is to generate the C-Plane message with section
-type 1 for DL or UL symbol data scheduling.
-
-This function has hardcoded values for some parameters such as:
-
-- The filter index is fixed to XRAN_FILTERINDEX_STANDARD.
-
-- RB indicator is fixed to XRAN_RBIND_EVERY.
-
-- Symbol increment is not used (XRAN_SYMBOLNUMBER_NOTINC)
-
-- Resource Element Mask is fixed to 0xfff
-
-The extension is not used.
-
-After C-Plane message generation, API send_cpmsg() is called. This
-function also includes the implementation for these capabilities:
-
-- Send the generated packet to the TX ring after adding an Ethernet
- header.
-
-- Add section information of generated C-Plane packet to section
- database, to generate U-plane message by C-Plane configuration
-
-send_cpmsg_prach() is to generate the C-Plane message with section type
-3 for PRACH scheduling.
-
-This functions also has some hardcoded values for the following
-parameters:
-
-- RB indicator is fixed to XRAN_RBIND_EVERY.
-
-- Symbol increment is not used (XRAN_SYMBOLNUMBER_NOTINC).
-
-- Resource Element Mask is fixed to 0xfff.
-
-And similar to generate_cpmsg_dlul(), after this function generates the
-message, send_cpmsg() sends the generated packet to the TX ring and adds
-section information of the packet to the section database. Checking and
-parsing received PRACH symbol data by section information from the
-C-Plane are not implemented in this release.
-
-Example Configuration of C-Plane Messages
-'''''''''''''''''''''''''''''''''''''''''
-
-C-Plane messages can be composed through API, and the sample application
-shows several reference usages of the configuration for different
-numerologies.
-
-Below are the examples of C-Plane message configuration with a sample
-application for mmWave – numerology 3, 100 MHz bandwidth, TDD (DDDS)
-
-**C-Plane Message – downlink symbol data for a downlink slot**
-
-- Single CP message with the single section of section type 1
-
-- Configures single CP message for all consecutive downlink symbols
-
-- Configures whole RBs (66) for a symbol
-
-- Compression and beamforming are not used
-
-Common Header Fields::
-
-- dataDirection = XRAN_DIR_DL
-- payloadVersion = XRAN_PAYLOAD_VER
-- filterIndex = XRAN_FILTERINDEX_STANDARD
-- frameId = [0..99]
-- subframeId = [0..9]
-- slotID = [0..9]
-- startSymbolid = 0
-- numberOfsections = 1
-- sectionType = XRAN_CP_SECTIONTYPE_1
-- udCompHdr.idIqWidth = 0
-- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
-- reserved = 0
-
-Section Fields::
-
-- sectionId = [0..4095]
-- rb = XRAN_RBIND_EVERY
-- symInc = XRAN_SYMBOLNUMBER_NOTINC
-- startPrbc = 0
-- numPrbc = 66
-- reMask = 0xfff
-- numSymbol = 14
-- ef = 0
-- beamId = 0
-
-
-**C-Plane Message – uplink symbol data for uplink slot**
-
-- Single CP message with the single section of section type 1
-
-- Configures single CP message for all consecutive uplink symbols (UL
- symbol starts from 3)
-
-- Configures whole RBs (66) for a symbol
-
-- Compression and beamforming are not used
-
-Common Header Fields::
-
-- dataDirection = XRAN_DIR_UL
-- payloadVersion = XRAN_PAYLOAD_VER
-- filterIndex = XRAN_FILTERINDEX_STANDARD
-- frameId = [0..99]
-- subframeId = [0..9]
-- slotID = [0..9]
-- startSymbolid = 3
-- numberOfsections = 1
-- sectionType = XRAN_CP_SECTIONTYPE_1
-- udCompHdr.idIqWidth = 0
-- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
-- reserved = 0
-
-Section Fields::
-
-- sectionId = [0..4095]
-- rb = XRAN_RBIND_EVERY
-- symInc = XRAN_SYMBOLNUMBER_NOTINC
-- startPrbc = 0
-- numPrbc = 66
-- reMask = 0xfff
-- numSymbol = 11
-- ef = 0
-- beamId = 0
-
-
-**C-Plane Message – PRACH**
-
-- Single CP message with the single section of section type 3 including
- repetition
-
-- Configures PRACH format A3, config index 81, and detail parameters
- are:
-
-- Filter Index : 3
-
-- CP length : 0
-
-- Time offset : 2026
-
-- FFT size : 1024
-
-- Subcarrier spacing : 120KHz
-
-- Start symbol index : 7
-
-- Number of symbols : 6
-
-- Number of PRBCs : 12
-
-- Frequency offset : -792
-
-- Compression and beamforming are not used
-
-Common Header Fields::
-
-- dataDirection = XRAN_DIR_UL
-- payloadVersion = XRAN_PAYLOAD_VER
-- filterIndex = XRAN_FILTERINDEPRACH_ABC
-- frameId = [0,99]
-- subframeId = [0,3]
-- slotID = 3 or 7
-- startSymbolid = 7
-- numberOfSections = 1
-- sectionType = XRAN_CP_SECTIONTYPE_3
-- timeOffset = 2026
-- frameStructure.FFTSize = XRAN_FFTSIZE_1024
-- frameStructure.u = XRAN_SCS_120KHZ
-- cpLength = 0
-- udCompHdr.idIqWidth = 0
-- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
-
-Section Fields::
-
-- sectionId = [0..4095]
-- rb = XRAN_RBIND_EVERY
-- symInc = XRAN_SYMBOLNUMBER_NOTINC
-- startPrbc = 0
-- numPrbc = 12
-- reMask = 0xfff
-- numSymbol = 6
-- ef = 0
-- beamId = 0
-- frequencyOffset = -792
-- reserved
-
-
-Functions to Store/Retrieve Section Information
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-There are several functions to store/retrieve section information of
-C-Plane messages. Since U-plane messages must be generated by the
-information in the sections of a C-Plane message, it is required to
-store and retrieve section information.
-
-**APIs and Data Structure**
-'''''''''''''''''''''''''''
-
-APIs for initialization and release storage are:
-
-- int xran_cp_init_sectiondb(void \*pHandle);
-
-- int xran_cp_free_sectiondb(void \*pHandle);
-
-APIs to store and retrieve section information are:
-
-- int xran_cp_add_section_info(void \*pHandle, uint8_t dir, uint8_t
- cc_id, uint8_t ruport_id, uint8_t ctx_id, struct xran_section_info
- \*info);
-
-- int xran_cp_add_multisection_info(void \*pHandle, uint8_t cc_id,
- uint8_t ruport_id, uint8_t ctx_id, struct xran_cp_gen_params
- \*gen_info);
-
-- struct xran_section_info \*xran_cp_find_section_info(void \*pHandle,
- uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id,
- uint16_t section_id);
-
-- struct xran_section_info \*xran_cp_iterate_section_info(void
- \*pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t
- ctx_id, uint32_t \*next);
-
-- int xran_cp_getsize_section_info(void \*pHandle, uint8_t dir, uint8_t
- cc_id, uint8_t ruport_id, uint8_t ctx_id);
-
-APIs to reset the storage for a new slot are:
-
-- int xran_cp_reset_section_info(void \*pHandle, uint8_t dir, uint8_t
- cc_id, uint8_t ruport_id, uint8_t ctx_id);
-
-The structure of xran_section_info is used to store/retrieve
-information. This is the same structure used to generate a C-Plane
-message. Please refer to Section 5.4.2.1.1 for more details.
-
-The storage for section information is declared as a multi-dimensional
-array and declared as a local static variable to limit direct access.
-Each item is defined as the structure of xran_sectioninfo_db, and it has
-the number of stored section information items (cur_index) and the array
-of the information (list), as shown below.
-
-/*
-
-\* This structure to store the section information of C-Plane
-
-\* in order to generate and parse corresponding U-Plane \*/
-
-struct xran_sectioninfo_db {
-
-uint32_t cur_index; /* Current index to store for this eAXC \*/
-
-struct xran_section_info list[XRAN_MAX_NUM_SECTIONS]; /* The array of
-section information \*/
-
-};
-
-static struct xran_sectioninfo_db
-sectiondb[XRAN_MAX_SECTIONDB_CTX][XRAN_DIR_MAX][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR*2
-+ XRAN_MAX_ANT_ARRAY_ELM_NR];
-
-The maximum size of the array can be adjusted if required by system
-configuration. Since transmission and reception window of U-Plane can be
-overlapped with the start of new C-Plane for next slot, functions have
-context index to identify and protect the information. Currently the
-maximum number of context is defined by two and it can be adjusted if
-needed.
-
-Note. Since the context index is not managed by the library and APIs are
-expecting it from the caller as a parameter, the caller shall
-consider a proper method to manage it to avoid corruption. The
-current reference implementation uses a slot and subframe index to
-calculate the context index.
-
-**Example Usage of APIs**
-'''''''''''''''''''''''''
-
-There are references to show the usage of APIs as below.
-
-- Initialization and release:
-
-- xran_cp_init_sectiondb(): xran_open() in lib/src/xran_main.c
-
-- xran_cp_free_sectiondb(): xran_close() in lib/src/xran_main.c
-
-- Store section information:
-
-- xran_cp_add_section_info(): send_cpmsg_dlul() and
- send_cpmsg_prach()in lib/src/xran_main.c
-
-- Retrieve section information:
-
-- xran_cp_iterate_section_info(): xran_process_tx_sym() in
- lib/src/xran_main.c
-
-- xran_cp_getsize_section_info(): xran_process_tx_sym() in
- lib/src/xran_main.c
-
-- Reset the storage for a new slot:
-
-- xran_cp_reset_section_info(): tx_cp_dl_cb() and tx_cp_ul_cb() in
- lib/src/xran_main.c
-
-**Function for RU emulation and Debug**
-'''''''''''''''''''''''''''''''''''''''
-
-xran_parse_cp_pkt() is a function which can be utilized for RU emulation
-or debug. It is defined below:
-
-int xran_parse_cp_pkt(struct rte_mbuf \*mbuf,
-
-struct xran_cp_gen_params \*result,
-
-struct xran_recv_packet_info \*pkt_info);
-
-It parses a received C-Plane packet and retrieves the information from
-its headers and sections.
-
-The retrieved information is stored in the structures:
-
-struct xran_cp_gen_params: section information from received C-Plane
-packet
-
-struct xran_recv_packet_info: transport layer header information (eCPRI
-header)
-
-These functions can be utilized to debug or RU emulation purposes.
-
-.. _u-plane-1:
-
-U-plane
-~~~~~~~
-
-Single Section is the default mode of xRAN packet creation. It assumes
-that there is only one section per packet, and all IQ samples are
-attached to it. Compression is not supported.
-
-A message is built in mbuf space given as a parameter. The library
-builds eCPRI header filling structure fields by taking the IQ sample
-size and populating a particular packet length and sequence number.
-
-With compression, supported IQ bit widths are 8,9,10,12,14.
-
-Implementation of a U-plane set of functions is defined in xran_up_api.c
-and is used to prepare U-plane packet content according to the given
-configuration.
-
-The following list of functions is implemented for U-plane:
-
-- Build eCPRI header
-
-- Build application header
-
-- Build section header
-
-- Append IQ samples to packet
-
-- Prepare full symbol of xRAN data for single eAxC
-
-- Process RX packet per symbol.
-
-The time of generation of a U-plane message for DL and UL is
-“symbol-based” and can be controlled using O-DU settings (O-RU),
-according to Table 4.
-
-Supporting Code
----------------
-
-The xRAN library has a set of functions used to assist in packet
-processing and data exchange not directly used for xRAN packet
-processing.
-
-Timing
-~~~~~~
-
-The sense of time for the xRAN protocol is obtained from system time,
-where the system timer is synchronized to GPS time via PTP protocol
-using the Linux PHP package. On the software side, a simple polling loop
-is utilized to get time up to nanosecond precision and particular packet
-processing jobs are scheduled via the DPDK timer.
-
-long poll_next_tick(int interval)
-
-{
-
-struct timespec start_time;
-
-struct timespec cur_time;
-
-long target_time;
-
-long delta;
-
-clock_gettime(CLOCK_REALTIME, &start_time);
-
-target_time = (start_time.tv_sec \* NSEC_PER_SEC + start_time.tv_nsec +
-interval \* NSEC_PER_USEC) / (interval \* NSEC_PER_USEC) \* interval;
-
-while(1)
-
-{
-
-clock_gettime(CLOCK_REALTIME, &cur_time);
-
-delta = (cur_time.tv_sec \* NSEC_PER_SEC + cur_time.tv_nsec) -
-target_time \* NSEC_PER_USEC;
-
-if(delta > 0 \|\| (delta < 0 && abs(delta) < THRESHOLD))
-
-{
-
-break;
-
-}
-
-}
-
-return delta;
-
-}
-
-Polling is used to achieve the required precision of symbol time. For
-example, in the mmWave scenario, the symbol time is 125µs/14=~8.9µs.
-Small deterministic tasks can be executed within the polling interval
-provided. It’s smaller than the symbol interval time.
-
-DPDK Timers
-~~~~~~~~~~~
-
-DPDK provides sets of primitives (struct rte_rimer) and functions
-(rte_timer_reset_sync() rte_timer_manage()) to |br|
-schedule processing of
-function as timer. The timer is based on the TSC clock and is not
-synchronized to PTP time. As a |br|
-result, this timer cannot be used as a
-periodic timer because the TSC clock can drift substantially relative to
-the system timer which in turn is synchronized to PTP (GPS)
-
-Only single-shot timers are used to schedule processing based on
-events such as symbol time. The packet |br|
-processing function
-calls rte_timer_manage() in the loop, and the resulting execution of
-timer function happens right |br|
-after the timer was “armed”.
-
-xRAN Ethernet
-~~~~~~~~~~~~~
-
-xran_init_port() function performs initialization of DPDK ETH port.
-Standard port configuration is used as per reference example from DPDK.
-
-Jumbo Frames are used by default. Mbufs size is extended to support 9600
-bytes packets.
-
-Mac address and VLAN tag are expected to be configured by Infrastructure
-software. See Appendix A.4.
-
-From an implementation perspective, modules provide functions to handle:
-
-- Ethernet headers
-
-- VLAN tag
-
-- Send and Receive mbuf.
-
-xRAN Ethdi
-~~~~~~~~~~
-
-Ethdi provides functionality to work with the content of an Ethernet
-packet and dispatch processing to/from the xRAN layer. Ethdi
-instantiates a main PMD driver thread and dispatches packets between the
-ring and RX/TX using rte_eth_rx_burst() and rte_eth_tx_burst() DPDK
-functions.
-
-For received packets, it maintains a set of handlers for ethertype
-handlers and xRAN layer register one xRAN ethtype |br|
-0xAEFE, resulting in
-packets with this ethertype being routed to the xRAN processing
-function. This function checks the message type of the eCPRI header and
-dispatches packet to either C-plane processing or U-plane processing.
-
-Initialization of memory pools, allocation and freeing of mbuf for
-Ethernet packets occur in this layer.
-
-
-
-
-
+.. Copyright (c) 2019 Intel\r
+..\r
+.. Licensed under the Apache License, Version 2.0 (the "License");\r
+.. you may not use this file except in compliance with the License.\r
+.. You may obtain a copy of the License at\r
+..\r
+.. http://www.apache.org/licenses/LICENSE-2.0\r
+..\r
+.. Unless required by applicable law or agreed to in writing, software\r
+.. distributed under the License is distributed on an "AS IS" BASIS,\r
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+.. See the License for the specific language governing permissions and\r
+.. limitations under the License.\r
+\r
+.. |br| raw:: html\r
+\r
+ <br />\r
+\r
+xRAN Library Design\r
+===================\r
+\r
+.. contents::\r
+ :depth: 3\r
+ :local:\r
+\r
+The xRAN Library consists of multiple modules where different\r
+functionality is encapsulated. The complete list of all \*.c and \*.h\r
+files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is:\r
+\r
+├── app\r
+\r
+│ ├── dpdk.sh\r
+\r
+│ ├── gen_test.m\r
+\r
+│ ├── Makefile\r
+\r
+│ ├── src\r
+\r
+│ │ ├── common.c\r
+\r
+│ │ ├── common.h\r
+\r
+│ │ ├── config.c\r
+\r
+│ │ ├── config.h\r
+\r
+│ │ ├── debug.h\r
+\r
+│ │ ├── sample-app.c\r
+\r
+│ │ └── xran_mlog_task_id.h\r
+\r
+│ └── usecase\r
+\r
+│ ├── cat_b\r
+\r
+│ ├── lte_a\r
+\r
+│ ├── lte_b\r
+\r
+│ ├── mu0_10mhz\r
+\r
+│ ├── mu0_20mhz\r
+\r
+│ ├── mu0_5mhz\r
+\r
+│ ├── mu1_100mhz\r
+\r
+│ └── mu3_100mhz\r
+\r
+├── banner.txt\r
+\r
+├── build.sh\r
+\r
+├── lib\r
+\r
+│ ├── api\r
+\r
+│ │ ├── xran_compression.h\r
+\r
+│ │ ├── xran_compression.hpp\r
+\r
+│ │ ├── xran_cp_api.h\r
+\r
+│ │ ├── xran_fh_o_du.h\r
+\r
+│ │ ├── xran_mlog_lnx.h\r
+\r
+│ │ ├── xran_pkt_cp.h\r
+\r
+│ │ ├── xran_pkt.h\r
+\r
+│ │ ├── xran_pkt_up.h\r
+\r
+│ │ ├── xran_sync_api.h\r
+\r
+│ │ ├── xran_timer.h\r
+\r
+│ │ ├── xran_transport.h\r
+\r
+│ │ └── xran_up_api.h\r
+\r
+│ ├── ethernet\r
+\r
+│ │ ├── ethdi.c\r
+\r
+│ │ ├── ethdi.h\r
+\r
+│ │ ├── ethernet.c\r
+\r
+│ │ └── ethernet.h\r
+\r
+│ ├── Makefile\r
+\r
+│ └── src\r
+\r
+│ ├── xran_app_frag.c\r
+\r
+│ ├── xran_app_frag.h\r
+\r
+│ ├── xran_bfp_cplane16.cpp\r
+\r
+│ ├── xran_bfp_cplane32.cpp\r
+\r
+│ ├── xran_bfp_cplane64.cpp\r
+\r
+│ ├── xran_bfp_cplane8.cpp\r
+\r
+│ ├── xran_bfp_ref.cpp\r
+\r
+│ ├── xran_bfp_utils.hpp\r
+\r
+│ ├── xran_common.c\r
+\r
+│ ├── xran_common.h\r
+\r
+│ ├── xran_compression.cpp\r
+\r
+│ ├── xran_cp_api.c\r
+\r
+│ ├── xran_frame_struct.c\r
+\r
+│ ├── xran_frame_struct.h\r
+\r
+│ ├── xran_lib_mlog_tasks_id.h\r
+\r
+│ ├── xran_main.c\r
+\r
+│ ├── xran_printf.h\r
+\r
+│ ├── xran_sync_api.c\r
+\r
+│ ├── xran_timer.c\r
+\r
+│ ├── xran_transport.c\r
+\r
+│ ├── xran_ul_tables.c\r
+\r
+│ └── xran_up_api.c\r
+\r
+├── Licenses.txt\r
+\r
+├── readme.md\r
+\r
+└── test\r
+\r
+ ├── common\r
+ \r
+ │ ├── common.cpp\r
+ \r
+ │ ├── common.hpp\r
+ \r
+ │ ├── common_typedef_xran.h\r
+ \r
+ │ ├── json.hpp\r
+ \r
+ │ ├── MIT_License.txt\r
+ \r
+ │ ├── xranlib_unit_test_main.cc\r
+ \r
+ │ └── xran_lib_wrap.hpp\r
+ \r
+ ├── master.py\r
+ \r
+ ├── readme.txt\r
+ \r
+ └── test_xran\r
+ \r
+ ├── chain_tests.cc\r
+ \r
+ ├── compander_functional.cc\r
+ \r
+ ├── conf.json\r
+ \r
+ ├── c_plane_tests.cc\r
+ \r
+ ├── init_sys_functional.cc\r
+ \r
+ ├── Makefile\r
+ \r
+ ├── prach_functional.cc\r
+ \r
+ ├── prach_performance.cc\r
+ \r
+ ├── unittests.cc\r
+ \r
+ └── u_plane_functional.cc\r
+\r
+\r
+General Introduction\r
+--------------------\r
+\r
+The xRAN Library functionality is broken down into two main sections:\r
+\r
+- O-RAN specific packet handling (src)\r
+\r
+- Ethernet and supporting functionality (Ethernet)\r
+\r
+External functions and structures are available via set of header files\r
+in the API folder.\r
+\r
+This library depends on DPDK primitives to perform Ethernet networking\r
+in userspace, including initialization and control of Ethernet ports.\r
+Ethernet ports are expected to be SRIOV virtual functions (VF) but also\r
+can be physical functions (PF) as well.\r
+\r
+This library is expected to be included in the project via\r
+xran_fh_o_du.h, statically compiled and linked with the L1 application\r
+as well as DPDK libraries. The O-RAN packet processing-specific\r
+functionality is encapsulated into this library and not exposed to the\r
+rest of the 5G NR pipeline. \r
+\r
+This way, xRAN specific changes are decoupled from the 5G NR L1\r
+pipeline. As a result, the design and implementation of the 5G L1\r
+pipeline code and xRAN library can be done in parallel, provided the\r
+defined interface is not modified.\r
+\r
+Ethernet consists of two modules:\r
+\r
+- Ethernet implements xRAN specific HW Ethernet initialization, close,\r
+ send and receive\r
+\r
+- ethdi provides Ethernet level software primitives to handle xRAN\r
+ packet exchange\r
+\r
+The xRAN layer implements the next set of functionalities:\r
+\r
+- Common code specific for both C-plane and U-plane as well as TX and\r
+ RX\r
+\r
+- Implementation of C-plane API available within the library and\r
+ externally\r
+\r
+- The primary function where general library initialization and\r
+ configuration performed\r
+\r
+- Module to provide the status of PTP synchronization\r
+\r
+- Timing module where system time is polled\r
+\r
+- eCPRI specific transport layer functions\r
+\r
+- APIs to handle U-plane packets\r
+\r
+- A set of utility modules for debugging (printf) and data tables are\r
+ included as well.\r
+\r
+.. image:: images/Illustration-of-xRAN-Sublayers.jpg\r
+ :width: 600\r
+ :alt: Figure 25. Illustration of xRAN Sublayers\r
+\r
+Figure 25. Illustration of xRAN Sublayers\r
+\r
+A detailed description of functions and input/output arguments, as well\r
+as key data structures, can be found in the Doxygen file for the FlexRAN\r
+5G NR release. In this document supplemental information is provided\r
+with respect to the overall design and implementation assumptions.\r
+\r
+Initialization and Close\r
+------------------------\r
+\r
+An example of the initialization sequence can be found in the sample\r
+application code. It consists of the following steps:\r
+\r
+1.Setup structure struct xran_fh_init according to configuration.\r
+\r
+2.Call xran_init() to instantiate the xRAN lib memory model and\r
+threads. The function returns a pointer to xRAN handle which is used\r
+for consecutive configuration functions.\r
+\r
+3.Initialize memory buffers used for L1 and xRAN exchange of\r
+information.\r
+\r
+4.Assign callback functions for (one) TTI event and for the reception\r
+of half of the slot of symbols (7 symbols) and Full slot of symbols\r
+14 symbols).\r
+\r
+5.Call xran_open() to initialize PRACH configuration, initialize DPDK,\r
+and launch xRAN timing thread.\r
+\r
+6.Call xran_start() to start processing O-RAN packets for DL and UL.\r
+\r
+After this is complete 5G L1 runs with xRAN Front haul interface. During\r
+run time for every TTI event, the corresponding call back is called. For\r
+packet reception on UL direction, the corresponding call back is called.\r
+OTA time information such as frame id, subframe id and slot id can be\r
+obtained as result synchronization of the L1 pipeline to GPS time is\r
+performed.\r
+\r
+To stop and close the interface, perform this sequence of steps:\r
+\r
+7.Call xran_stop() to stop the processing of DL and UL.\r
+\r
+8.Call xran_close() to remove usage of xRAN resources.\r
+\r
+9.Call xran_mm_destroy() to destroy memory management subsystem.\r
+\r
+After this session is complete, a restart of the full L1 application is\r
+required. The current version of the library does not support multiple\r
+sessions without a restart of the full L1 application.\r
+\r
+Configuration\r
+~~~~~~~~~~~~~\r
+\r
+The xRAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config. \r
+The sample application gives an example of a test configuration used for LTE and 5GNR mmWave and Sub 6. Sample application\r
+folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B)\r
+and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz).\r
+\r
+Some configuration options are not used in the Bronze Release and are reserved\r
+for future use.\r
+\r
+The following options are available: \r
+\r
+**Structure** struct xran_fh_init\ **:**\r
+\r
+- Number of CC and corresponding settings for each\r
+\r
+- Core allocation for xRAN\r
+\r
+- Ethernet port allocation\r
+\r
+- O-DU and RU Ethernet Mac address\r
+\r
+- Timing constraints of O-DU and 0-RU\r
+\r
+- Debug features\r
+\r
+**Structure** struct xran_fh_config\ **:**\r
+\r
+- Number of eAxC\r
+\r
+- TTI Callback function and parameters\r
+\r
+- PRACH 5G NR specific settings\r
+\r
+- TDD frame configuration\r
+\r
+- BBU specific configuration\r
+\r
+- RU specific configuration\r
+\r
+**From an implementation perspective:**\r
+\r
+xran_init() performs init of the xRAN library and interface according to\r
+struct xran_fh_init information as per the start of application\r
+configuration.:\r
+\r
+- Init DPDK with corresponding networking ports and core assignment\r
+\r
+- Init mbuf pools\r
+\r
+- Init DPDK timers and DPDK rings for internal packet processing\r
+\r
+- Instantiate ORAN FH thread doing\r
+\r
+ - Timing processing (xran_timing_source_thread())\r
+\r
+ - ETH PMD (process_dpdk_io())\r
+\r
+ - IO XRAN-PHY exchange (ring_processing_func())\r
+\r
+**xran_open()** performs additional configuration as per run scenario:\r
+\r
+- PRACH configuration\r
+\r
+- C-plane initialization\r
+\r
+The Function **xran_close()** performs free of resources and allows potential\r
+restart of front haul interface with a different scenario.\r
+\r
+Start/Stop\r
+~~~~~~~~~~\r
+\r
+The Functions **xran_start()/xran_stop()** enable/disable packet processing for\r
+both DL and UL. This triggers execution of callbacks into the L1\r
+application.\r
+\r
+Data Exchange\r
+~~~~~~~~~~~~~\r
+\r
+Exchange of IQ samples, as well as C-plane specific information, is\r
+performed using a set of buffers allocated by xRAN library from DPDK\r
+memory and shared with the l1 application. Buffers are allocated as a\r
+standard mbuf structure and DPDK pools are used to manage the allocation\r
+and free resources. Shared buffers are allocated at the init stage and\r
+are expected to be reused within 80 TTIs (10 ms).\r
+\r
+The xRAN protocol requires U-plane IQ data to be transferred in network\r
+byte order, and the L1 application handles IQ sample data in CPU byte\r
+order, requiring a swap. The PHY BBU pooling tasks perform copy and byte\r
+order swap during packet processing.\r
+\r
+C-plane Information Settings\r
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The interface between the xRAN library and PHY is defined via struct\r
+xran_prb_map and similar to the data plane. The same mbuf memory is used\r
+to allocate memory map of PRBs for each TTI.::\r
+\r
+ /*\* Beamforming waights for single stream for each PRBs given number of\r
+ Antenna elements \*/\r
+ struct xran_cp_bf_weight{\r
+\r
+ int16_t nAntElmTRx; /**< num TRX for this allocation \*/\r
+\r
+ int16_t ext_section_sz; /**< extType section size \*/\r
+\r
+ int8_t\* p_ext_start; /**< pointer to start of buffer for full C-plane\r
+ packet \*/\r
+\r
+ int8_t\* p_ext_section; /**< pointer to form extType \*/\r
+\r
+ /\* For ext 11 \*/\r
+\r
+ uint8_t bfwCompMeth; /\* Compression Method for BFW \*/\r
+\r
+ uint8_t bfwIqWidth; /\* Bitwidth of BFW \*/\r
+\r
+ uint8_t numSetBFWs; /\* Total number of beam forming weights set (L) \*/\r
+\r
+ uint8_t numBundPrb; /\* The number of bundled PRBs, 0 means to use ext1\r
+ \*/\r
+\r
+ uint8_t RAD;\r
+\r
+ uint8_t disableBFWs;\r
+\r
+ int16_t maxExtBufSize; /\* Maximum space of external buffer \*/\r
+\r
+ struct xran_ext11_bfw_info bfw[XRAN_MAX_SET_BFWS]\r
+\r
+ };\r
+\r
+ /*\* PRB element structure \*/\r
+\r
+ struct xran_prb_elm {\r
+\r
+ int16_t nRBStart; /**< start RB of RB allocation \*/\r
+\r
+ int16_t nRBSize; /**< number of RBs used \*/\r
+\r
+ int16_t nStartSymb; /**< start symbol ID \*/\r
+\r
+ int16_t numSymb; /**< number of symbols \*/\r
+\r
+ int16_t nBeamIndex; /**< beam index for given PRB \*/\r
+\r
+ int16_t bf_weight_update; /*\* need to update beam weights or not \*/\r
+\r
+ int16_t compMethod; /**< compression index for given PRB \*/\r
+\r
+ int16_t iqWidth; /**< compression bit width for given PRB \*/\r
+\r
+ uint16_t ScaleFactor; /**< scale factor for modulation compression \*/\r
+\r
+ int16_t reMask; /**< 12-bit RE Mask for modulation compression \*/\r
+\r
+ int16_t BeamFormingType; /**< index based, weights based or attribute\r
+ based beam forming*/\r
+\r
+ int16_t nSecDesc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /**< number of section\r
+ descriptors per symbol \*/\r
+\r
+ struct xran_section_desc \*\r
+ p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT][XRAN_MAX_FRAGMENT]; /**< section\r
+ desctiptors to U-plane data given RBs \*/\r
+\r
+ struct xran_cp_bf_weight bf_weight; /**< beam forming information\r
+ relevant for given RBs \*/\r
+\r
+ union {\r
+\r
+ struct xran_cp_bf_attribute bf_attribute;\r
+\r
+ struct xran_cp_bf_precoding bf_precoding;\r
+\r
+ };\r
+\r
+ };\r
+\r
+ /*\* PRB map structure \*/\r
+\r
+ struct xran_prb_map {\r
+\r
+ uint8_t dir; /**< DL or UL direction \*/\r
+\r
+ uint8_t xran_port; /**< xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/\r
+\r
+ uint16_t band_id; /**< xran band id \*/\r
+\r
+ uint16_t cc_id; /**< component carrier id [0 - (XRAN_MAX_SECTOR_NR-1)]\r
+ \*/\r
+\r
+ uint16_t ru_port_id; /**< RU device antenna port id [0 -\r
+ (XRAN_MAX_ANTENNA_NR-1) \*/\r
+\r
+ uint16_t tti_id; /**< xRAN slot id [0 - (max tti-1)] \*/\r
+\r
+ uint8_t start_sym_id; /**< start symbol Id [0-13] \*/\r
+\r
+ uint32_t nPrbElm; /**< total number of PRB elements for given map [0-\r
+ (XRAN_MAX_SECTIONS_PER_SLOT-1)] \*/\r
+\r
+ struct xran_prb_elm prbMap[XRAN_MAX_SECTIONS_PER_SLOT];\r
+\r
+ };\r
+\r
+\r
+For the Bronze release C-plane sections are expected to be provided by L1\r
+pipeline. If 100% of RBs always allocated single element of RB map\r
+is expected to be allocated across all symbols. Dynamic RB allocation is\r
+performed base on C-plane configuration.\r
+\r
+The xRAN library will require that the content of the PRB map should be\r
+sorted in increasing order of PRB first and then symbols.\r
+\r
+Memory Management\r
+-----------------\r
+\r
+Memory used for the exchange of IQ data as well as control information,\r
+is controlled by the xRAN library. L1 application at the init stage\r
+performs:\r
+\r
+- init memory management subsystem\r
+\r
+- init buffer management subsystem (via DPDK pools)\r
+\r
+- allocate buffers (mbuf) for each CC, antenna, symbol, and direction \\r
+ (DL, UL, PRACH) for XRAN_N_FE_BUF_LEN TTIs.\r
+\r
+- buffers are reused for every XRAN_N_FE_BUF_LEN TTIs\r
+\r
+After the session is completed, the application can free buffers and\r
+destroy the memory management subsystem.\r
+\r
+From an implementation perspective, the xRAN library uses a standard\r
+mbuf primitive and allocates a pool of buffers for each sector. This\r
+function is performed using rte_pktmbuf_pool_create(),\r
+rte_pktmbuf_alloc(), rte_pktmbuf_append() to allocate one buffer per\r
+symbol for the mmWave case. More information on mbuf and DPDK pools can\r
+be found in the DPDK documentation.\r
+\r
+In the current implementation, mbuf, the number of buffers shared with\r
+the L1 application is the same number of buffers used to send to and\r
+receive from the Ethernet port. Memory copy operations are not required\r
+if the packet size is smaller than or equal to MTU. Future versions of\r
+the xRAN library are required to remove the memory copy requirement for\r
+packets where the size larger than MTU.\r
+\r
+External Interface Memory\r
+~~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The xRAN library header file defines a set of structures to simplify\r
+access to memory buffers used for IQ data.:::\r
+\r
+ struct xran_flat_buffer {\r
+\r
+ uint32_t nElementLenInBytes;\r
+\r
+ uint32_t nNumberOfElements;\r
+\r
+ uint32_t nOffsetInBytes;\r
+\r
+ uint32_t nIsPhyAddr;\r
+\r
+ uint8_t \*pData;\r
+\r
+ void \*pCtrl;\r
+\r
+ };\r
+\r
+ struct xran_buffer_list {\r
+\r
+ uint32_t nNumBuffers;\r
+\r
+ struct xran_flat_buffer \*pBuffers;\r
+\r
+ void \*pUserData;\r
+\r
+ void \*pPrivateMetaData;\r
+\r
+ };\r
+\r
+ struct xran_io_buf_ctrl {\r
+\r
+ /\* -1-this subframe is not used in current frame format\r
+\r
+ 0-this subframe can be transmitted, i.e., data is ready\r
+\r
+ 1-this subframe is waiting transmission, i.e., data is not ready\r
+\r
+ 10 - DL transmission missing deadline. When FE needs this subframe data\r
+ but bValid is still 1,\r
+\r
+ set bValid to 10.\r
+\r
+ \*/\r
+\r
+ int32_t bValid ; // when UL rx, it is subframe index.\r
+\r
+ int32_t nSegToBeGen;\r
+\r
+ int32_t nSegGenerated; // how many date segment are generated by DL LTE\r
+ processing or received from FE\r
+\r
+ // -1 means that DL packet to be transmitted is not ready in BS\r
+\r
+ int32_t nSegTransferred; // number of data segments has been transmitted\r
+ or received\r
+\r
+ struct rte_mbuf \*pData[N_MAX_BUFFER_SEGMENT]; // point to DPDK\r
+ allocated memory pool\r
+\r
+ struct xran_buffer_list sBufferList;\r
+\r
+ };\r
+\r
+There is no explicit requirement for user to organize a set of buffers\r
+in this particular way. From a compatibility |br|\r
+perspective it is useful to\r
+follow the existing design of the 5G NR l1app used for Front Haul FPGA\r
+and define structures shared between l1 and xRAN lib as shown: ::\r
+\r
+ struct bbu_xran_io_if {\r
+\r
+ void\* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; /**<\r
+ instance per O-RAN port per CC \*/\r
+\r
+ uint32_t\r
+ nBufPoolIndex[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR][MAX_SW_XRAN_INTERFACE_NUM];\r
+ /**< unique buffer pool \*/\r
+\r
+ uint16_t nInstanceNum[XRAN_PORTS_NUM]; /**< instance is equivalent to CC\r
+ \*/\r
+\r
+ uint16_t DynamicSectionEna;\r
+\r
+ uint32_t nPhaseCompFlag;\r
+\r
+ int32_t num_o_ru;\r
+\r
+ int32_t num_cc_per_port[XRAN_PORTS_NUM];\r
+\r
+ int32_t map_cell_id2port[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];\r
+\r
+ struct xran_io_shared_ctrl ioCtrl[XRAN_PORTS_NUM]; /**< for each O-RU\r
+ port \*/\r
+\r
+ struct xran_cb_tag RxCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];\r
+\r
+ struct xran_cb_tag PrachCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];\r
+\r
+ struct xran_cb_tag SrsCbTag[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR];\r
+\r
+ };\r
+\r
+ struct xran_io_shared_ctrl {\r
+\r
+ /\* io struct \*/\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ /\* Cat B \*/\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFHSrsRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];\r
+\r
+ struct xran_io_buf_ctrl\r
+ sFHSrsRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];\r
+\r
+ /\* buffers lists \*/\r
+\r
+ struct xran_flat_buffer\r
+ sFrontHaulTxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+\r
+ struct xran_flat_buffer\r
+ sFrontHaulTxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_flat_buffer\r
+ sFrontHaulRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+\r
+ struct xran_flat_buffer\r
+ sFrontHaulRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR];\r
+\r
+ struct xran_flat_buffer\r
+ sFHPrachRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR][XRAN_NUM_OF_SYMBOL_PER_SLOT];\r
+\r
+ /\* Cat B SRS buffers \*/\r
+\r
+ struct xran_flat_buffer\r
+ sFHSrsRxBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR][XRAN_MAX_NUM_OF_SRS_SYMBOL_PER_SLOT];\r
+\r
+ struct xran_flat_buffer\r
+ sFHSrsRxPrbMapBuffers[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANT_ARRAY_ELM_NR];\r
+\r
+ };\r
+\r
+Doxygen file and xran_fh_o_du.h provide more details on the definition\r
+and usage of these structures.\r
+\r
+xRAN Specific Functionality\r
+---------------------------\r
+\r
+Front haul interface implementation in the general case is abstracted\r
+away using the interface defined in xran_fh_o_du.h\r
+\r
+The L1 application is not required to access O-RAN protocol primitives\r
+(eCPRI header, application header, and others) directly. It is\r
+recommended to use the interface to remove dependencies between\r
+different software modules such as the l1 pipeline and xRAN library.\r
+\r
+External API\r
+~~~~~~~~~~~~\r
+\r
+The U-plane and C-plane APIs can be used directly from the application\r
+if such an option is required. The set of header files can be exported\r
+and called directly.::\r
+\r
+ xran_fh_o_du.h – xRAN main header file for O-DU scenario\r
+\r
+ xran_cp_api.h – Control plane functions\r
+\r
+ xran_pkt_cp.h – xRAN control plane packet definition\r
+\r
+ xran_pkt.h – xRAN packet definition\r
+\r
+ xran_pkt_up.h – xRAN User plane packet definition\r
+\r
+ xran_sync_api.h – api functions to check PTP status\r
+\r
+ xran_timer.h – API for timing\r
+\r
+ xran_transport.h – eCPRI transport layer definition and api\r
+\r
+ xran_up_api.h – user plane functions and definitions\r
+\r
+ xran_compression.h – interface to compression/decompression functions\r
+\r
+Doxygen files provide detailed information on functions and structures\r
+available.\r
+\r
+.. _c-plane-1:\r
+\r
+C-plane\r
+~~~~~~~\r
+\r
+Implementation of the C-plane set of functions is defined in\r
+xran_cp_api.c and is used to prepare the content of C-plane packets\r
+according to the given configuration. Users can enable/disable\r
+generation of C-plane messages using enableCP field in struct\r
+xran_fh_init structure during init of ORAN front haul. The time of\r
+generation of C-plane message for DL and UL is done “Slot-based,” and\r
+timing can be controlled using O-DU settings according to Table 4.\r
+\r
+The C-plane module contains:\r
+\r
+- initialization of C-plane database to keep track of allocation of\r
+ resources\r
+\r
+- code to prepare C-plane packet for TX (O-DU)\r
+ - eCPRI header\r
+ - append radio application header\r
+ - append control section header\r
+ - append control section\r
+\r
+- parser of C-plane packet for RX (O-RU emulation)\r
+\r
+- parses and checks Section 1 and Section 3 packet content\r
+\r
+Sending and receiving packets is performed using xRAN ethdi sublayer\r
+functions.\r
+\r
+Creating a C-Plane Packet\r
+^^^^^^^^^^^^^^^^^^^^^^^^^\r
+\r
+API and Data Structures\r
+'''''''''''''''''''''''\r
+\r
+A C-Plane message can be composed using the following API:::\r
+\r
+ int xran_prepare_ctrl_pkt(struct rte_mbuf \*mbuf,\r
+\r
+ struct xran_cp_gen_params \*params,\r
+\r
+ uint8_t CC_ID, uint8_t Ant_ID, uint8_t seq_id);\r
+\r
+mbuf is the pointer of a DPDK packet buffer, which is allocated from the\r
+caller.\r
+\r
+params are the pointer of the structure which has the parameters to\r
+create the message.\r
+\r
+CC_ID is the parameter to specify component carrier index, Ant_ID is the\r
+parameters to specify the antenna port index (RU port index).\r
+\r
+seq_id is the sequence index for the message.\r
+\r
+params, the parameters to create a C-Plane message are defined as the\r
+structure of xran_cp_gen_params with an |br|\r
+example given below:::\r
+\r
+ struct xran_cp_gen_params {\r
+\r
+ uint8_t dir;\r
+\r
+ uint8_t sectionType;\r
+\r
+ uint16_t numSections;\r
+\r
+ struct xran_cp_header_params hdr;\r
+\r
+ struct xran_section_gen_info \*sections;\r
+\r
+ };\r
+\r
+dir is the direction of the C-Plane message to be generated. Available\r
+parameters are defined as XRAN_DIR_UL and XRAN_DIR_DL.\r
+\r
+sectionType is the section type for C-Plane message to generate, as O-RAN\r
+specification defines all sections in a C-Plane message shall have the\r
+same section type. If different section types are required, they shall\r
+be sent with separate C-Plane messages. Available types of sections are\r
+defined as XRAN_CP_SECTIONTYPE_x. Please refer to the Table 5-2 Section\r
+Types in chapter 5.4 of ORAN specification.\r
+\r
+numSections is the total number of sections to generate, i.e., the\r
+number of the array in sections (struct xran_section_gen_info).\r
+\r
+hdr is the structure to hold the information to generate the radio\r
+application and section header in the C-Plane message. It is defined as\r
+the structure of xran_cp_header_params. Not all parameters in this\r
+structure are used for the generation, and the required parameters are\r
+slightly different by the type of section, as described in Table 10.\r
+\r
+Table 10. struct xran_cp_header_params – Common Radio Application Header\r
+\r
++------------+---------------------------------------------+---------+\r
+| | Description | Remarks |\r
++============+=============================================+=========+\r
+| filterIdx | Filter Index. Available values are defined | 5.4.4.3 |\r
+| | as XRAN_FILTERINDEX_xxxxx. | |\r
++------------+---------------------------------------------+---------+\r
+| frameId | Frame Index. It is modulo 256 of frame | 5.4.4.4 |\r
+| | number. | |\r
++------------+---------------------------------------------+---------+\r
+| subframeId | Sub-frame Index. | 5.4.4.5 |\r
++------------+---------------------------------------------+---------+\r
+| slotId | Slot Index. The maximum number is 15, as | 5.4.4.6 |\r
+| | defined in the specification. | |\r
++------------+---------------------------------------------+---------+\r
+| startSymId | Start Symbol Index. | 5.4.4.7 |\r
++------------+---------------------------------------------+---------+\r
+\r
+Table 11. struct xran_cp_header_params – Section Specific Parameters\r
+\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| | Des\ | Section | Remarks | | | | | |\r
+| | cription | Type | | | | | | |\r
+| | | ap\ | | | | | | |\r
+| | | plicable | | | | | | |\r
++==========+==========+==========+=========+===+===+===+===+==========+\r
+| | | 0 | 1 | 3 | 5 | 6 | 7 | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| fftSize | FFT size | X | | X | | | | 5.4.4.13 |\r
+| | in frame | | | | | | | |\r
+| | st\ | | | | | | | |\r
+| | ructure. | | | | | | | |\r
+| | A\ | | | | | | | |\r
+| | vailable | | | | | | | |\r
+| | values | | | | | | | |\r
+| | are | | | | | | | |\r
+| | defined | | | | | | | |\r
+| | as | | | | | | | |\r
+| | X\ | | | | | | | |\r
+| | RAN_FFTS\| | | | | | | |\r
+| | IZE_xxxx | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| Scs | Su\ | X | | X | | | | 5.4.4.13 |\r
+| | bcarrier | | | | | | | |\r
+| | Spacing | | | | | | | |\r
+| | in the | | | | | | | |\r
+| | frame | | | | | | | |\r
+| | st\ | | | | | | | |\r
+| | ructure. | | | | | | | |\r
+| | A\ | | | | | | | |\r
+| | vailable | | | | | | | |\r
+| | values | | | | | | | |\r
+| | are | | | | | | | |\r
+| | defined | | | | | | | |\r
+| | as | | | | | | | |\r
+| | XRAN_SCS\| | | | | | | | \r
+| | _xxxx | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| iqWidth | I/Q bit | | X | X | X | | | 5.4.4.10 |\r
+| | width in | | | | | | | |\r
+| | user | | | | | | | 6.3.3.13 |\r
+| | data | | | | | | | |\r
+| | com\ | | | | | | | |\r
+| | pression | | | | | | | |\r
+| | header. | | | | | | | |\r
+| | Should | | | | | | | |\r
+| | be set | | | | | | | |\r
+| | by zero | | | | | | | |\r
+| | for | | | | | | | |\r
+| | 16bits | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| compMeth | Com\ | | X | X | X | | | 5.4.4.10 |\r
+| | pression | | | | | | | |\r
+| | Method | | | | | | | 6.3.3.13 |\r
+| | in user | | | | | | | |\r
+| | data | | | | | | | |\r
+| | com\ | | | | | | | |\r
+| | pression | | | | | | | |\r
+| | header. | | | | | | | |\r
+| | A\ | | | | | | | |\r
+| | vailable | | | | | | | |\r
+| | values | | | | | | | |\r
+| | are | | | | | | | |\r
+| | defined | | | | | | | |\r
+| | as | | | | | | | |\r
+| | XRAN\ | | | | | | | |\r
+| | _COMPMET\| | | | | | | |\r
+| | HOD_xxxx | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| numUEs | Number | | | | | X | | 5.4.4.11 |\r
+| | of UEs. | | | | | | | |\r
+| | Applies | | | | | | | |\r
+| | to | | | | | | | |\r
+| | section | | | | | | | |\r
+| | type 6 | | | | | | | |\r
+| | and not | | | | | | | |\r
+| | s\ | | | | | | | |\r
+| | upported | | | | | | | |\r
+| | in this | | | | | | | |\r
+| | release. | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| ti\ | Time | X | | X | | | | 5.4.4.12 |\r
+| meOffset | Offset. | | | | | | | |\r
+| | Time | | | | | | | |\r
+| | offset | | | | | | | |\r
+| | from the | | | | | | | |\r
+| | start of | | | | | | | |\r
+| | the slot | | | | | | | |\r
+| | to start | | | | | | | |\r
+| | of | | | | | | | |\r
+| | Cyclic | | | | | | | |\r
+| | Prefix. | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+| cpLength | Cyclic | X | | X | | | | 5.4.4.14 |\r
+| | Prefix | | | | | | | |\r
+| | Length. | | | | | | | |\r
++----------+----------+----------+---------+---+---+---+---+----------+\r
+\r
+**Only sections types 1 and 3 are supported in the current release.**\r
+\r
+Sections are the pointer to the array of structure which has the\r
+parameters for section(s) and it is defined as below:::\r
+\r
+ struct xran_section_gen_info {\r
+\r
+ struct xran_section_info info;\r
+\r
+ uint32_t exDataSize;\r
+\r
+ struct {\r
+\r
+ uint16_t type;\r
+\r
+ uint16_t len;\r
+\r
+ void \*data;\r
+\r
+ } exData[XRAN_MAX_NUM_EXTENSIONS];\r
+\r
+ };\r
+\r
+info is the structure to hold the information to generate section and it\r
+is defined as the structure of xran_section_info. Like\r
+xran_cp_header_params, all parameters are not required to generate\r
+section and Table 12 describes which |br|\r
+parameters are required for each\r
+section.\r
+\r
+Table 12. Parameters for Sections\r
+\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| | D\ | Se\ | Re\ | | | | |\r
+| | escri\| ction | marks | | | | |\r
+| | ption | Type | | | | | |\r
+| | | appli\| | | | | |\r
+| | | cable | | | | | |\r
++=======+=======+=======+=======+=======+=======+=======+=======+\r
+| | | 0 | 1 | 3 | 5 | 6 | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| Id | Se\ | **X** | **X** | **X** | **X** | **X** | 5.\ |\r
+| | ction | | | | | | 4.5.1 |\r
+| | I\ | | | | | | |\r
+| | denti\| | | | | | |\r
+| | fier. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| Rb | Res\ | **X** | **X** | **X** | **X** | **X** | 5.\ |\r
+| | ource | | | | | | 4.5.2 |\r
+| | Block\| | | | | | |\r
+| | Indic\| | | | | | |\r
+| | ator. | | | | | | |\r
+| | Avai\ | | | | | | |\r
+| | lable | | | | | | |\r
+| | v\ | | | | | | |\r
+| | alues | | | | | | |\r
+| | are | | | | | | |\r
+| | de\ | | | | | | |\r
+| | fined | | | | | | |\r
+| | as | | | | | | |\r
+| | XRAN\ | | | | | | |\r
+| | _\ | | | | | | |\r
+| | RBI\ | | | | | | |\r
+| | ND_xx\| | | | | | |\r
+| | xx. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| s\ | S\ | **X** | **X** | **X** | **X** | **X** | 5.\ |\r
+| ymInc | ymbol | | | | | | 4.5.3 |\r
+| | n\ | | | | | | |\r
+| | umber | | | | | | |\r
+| | Incr\ | | | | | | |\r
+| | ement | | | | | | |\r
+| | com\ | | | | | | |\r
+| | mand. | | | | | | |\r
+| | Avai\ | | | | | | |\r
+| | lable | | | | | | |\r
+| | v\ | | | | | | |\r
+| | alues | | | | | | |\r
+| | are | | | | | | |\r
+| | de\ | | | | | | |\r
+| | fined | | | | | | |\r
+| | as | | | | | | |\r
+| | XRA\ | | | | | | |\r
+| | N_SYM\| | | | | | |\r
+| | BOL\ | | | | | | |\r
+| | NUMBE\| | | | | | |\r
+| | R_xx\ | | | | | | |\r
+| | xx. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| star\ | Sta\ | **X** | **X** | **X** | **X** | **X** | 5.\ |\r
+| tPrbc | rting\| | | | | | 4.5.4 |\r
+| | PRB | | | | | | |\r
+| | of | | | | | | |\r
+| | data | | | | | | |\r
+| | se\ | | | | | | |\r
+| | ction | | | | | | |\r
+| | de\ | | | | | | |\r
+| | scrip\| | | | | | |\r
+| | tion. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| nu | The | **X** | **X** | **X** | **X** | **X** | 5.\ |\r
+| mPrbc | n\ | | | | | | 4.5.6 |\r
+| | umber | | | | | | |\r
+| | of | | | | | | |\r
+| | conti\| | | | | | |\r
+| | guous | | | | | | |\r
+| | PRBs | | | | | | |\r
+| | per | | | | | | |\r
+| | data | | | | | | |\r
+| | se\ | | | | | | |\r
+| | ction | | | | | | |\r
+| | de\ | | | | | | |\r
+| | scrip\| | | | | | |\r
+| | tion. | | | | | | |\r
+| | When | | | | | | |\r
+| | nu\ | | | | | | |\r
+| | mPrbc | | | | | | |\r
+| | is | | | | | | |\r
+| | gr\ | | | | | | |\r
+| | eater | | | | | | |\r
+| | than | | | | | | |\r
+| | 255, | | | | | | |\r
+| | it | | | | | | |\r
+| | will | | | | | | |\r
+| | be | | | | | | |\r
+| | conv\ | | | | | | |\r
+| | erted | | | | | | |\r
+| | to | | | | | | |\r
+| | zero | | | | | | |\r
+| | by | | | | | | |\r
+| | the | | | | | | |\r
+| | macro | | | | | | |\r
+| | (XR\ | | | | | | |\r
+| | AN_CO\| | | | | | |\r
+| | NVERT\| | | | | | |\r
+| | _NUMP\| | | | | | |\r
+| | RBC). | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| r\ | Res\ | **X** | **X** | **X** | **X** | | 5.\ |\r
+| eMask | ource\| | | | | | 4.5.5 |\r
+| | El\ | | | | | | |\r
+| | ement\| | | | | | |\r
+| | Mask. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| numS\ | N\ | **X** | **X** | **X** | **X** | | 5.\ |\r
+| ymbol | umber | | | | | | 4.5.7 |\r
+| | of | | | | | | |\r
+| | Sym\ | | | | | | |\r
+| | bols. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| b\ | Beam\ | | **X** | **X** | | | 5.\ |\r
+| eamId | I\ | | | | | | 4.5.9 |\r
+| | denti\| | | | | | |\r
+| | fier. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| freqO\| Freq\ | | | **X** | | | 5.4\ |\r
+| ffset | uency\| | | | | | .5.11 |\r
+| | Of\ | | | | | | |\r
+| | fset. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| ueId | UE\ | | | | **X** | **X** | 5.4\ |\r
+| | i\ | | | | | | .5.10 |\r
+| | denti\| | | | | | |\r
+| | fier. | | | | | | |\r
+| | Not | | | | | | |\r
+| | supp\ | | | | | | |\r
+| | orted | | | | | | |\r
+| | in | | | | | | |\r
+| | this | | | | | | |\r
+| | rel\ | | | | | | |\r
+| | ease. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| regF\ | Regu\ | | | | | **X** | 5.4\ |\r
+| actor | lariz\| | | | | | .5.12 |\r
+| | ation | | | | | | |\r
+| | Fa\ | | | | | | |\r
+| | ctor. | | | | | | |\r
+| | Not | | | | | | |\r
+| | supp\ | | | | | | |\r
+| | orted | | | | | | |\r
+| | in | | | | | | |\r
+| | this | | | | | | |\r
+| | re\ | | | | | | |\r
+| | lease | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+| Ef | Exte\ | | **X** | **X** | **X** | **X** | 5.\ |\r
+| | nsion | | | | | | 4.5.8 |\r
+| | Flag. | | | | | | |\r
+| | Not | | | | | | |\r
+| | supp\ | | | | | | |\r
+| | orted | | | | | | |\r
+| | in | | | | | | |\r
+| | this | | | | | | |\r
+| | rel\ | | | | | | |\r
+| | ease. | | | | | | |\r
++-------+-------+-------+-------+-------+-------+-------+-------+\r
+\r
+**Only sections types 1 and 3 are supported in the current release.**\r
+\r
+**The xran_section_info has more parameters – type, startSymId, iqWidth,\r
+compMeth. These are the same parameters as those of radio application\r
+or section header but need to be copied into this structure again for\r
+the section data base.**\r
+\r
+exDataSize and exData are used to add section extensions for the\r
+section.\r
+\r
+exDataSize is the number of elements in the exData array. The maximum\r
+number of elements is defined as XRAN_MAX_NUM_EXTENSIONS and it is\r
+defined by four in this release with the assumption that four different\r
+types of section extensions can be added to a section (section extension\r
+type 3 is excluded since it is not supported). exData.type is the type\r
+of section extension and exData.len is the length of structure of\r
+section extension parameter in exData.data. exData.data is the pointer\r
+to the structure of section extensions and different structures are used\r
+by the type of section extensions like below.::\r
+\r
+ struct xran_sectionext1_info {\r
+\r
+ uint16_t rbNumber; /* number RBs to ext1 chain \*/\r
+\r
+ uint16_t bfwNumber; /* number of bf weights in this section \*/\r
+\r
+ uint8_t bfwiqWidth;\r
+\r
+ uint8_t bfwCompMeth;\r
+\r
+ int16_t \*p_bfwIQ; /* pointer to formed section extention \*/\r
+\r
+ int16_t bfwIQ_sz; /* size of buffer with section extention information\r
+ \*/\r
+\r
+ union {\r
+\r
+ uint8_t exponent;\r
+\r
+ uint8_t blockScaler;\r
+\r
+ uint8_t compBitWidthShift;\r
+\r
+ uint8_t activeBeamspaceCoeffMask[XRAN_MAX_BFW_N]; /\* ceil(N/8)*8,\r
+ should be multiple of 8 \*/\r
+\r
+ } bfwCompParam;\r
+\r
+ };\r
+\r
+For section extension type 1, the structure of xran_sectionext1_info is\r
+used. Please note that the xRAN library will use bfwIQ (beamforming\r
+weight) as-is, i.e., xRAN library will not perform the compression, so\r
+the user should provide proper data to bfwIQ.::\r
+\r
+ struct xran_sectionext2_info {\r
+\r
+ uint8_t bfAzPtWidth;\r
+\r
+ uint8_t bfAzPt;\r
+\r
+ uint8_t bfZePtWidth;\r
+\r
+ uint8_t bfZePt;\r
+\r
+ uint8_t bfAz3ddWidth;\r
+\r
+ uint8_t bfAz3dd;\r
+\r
+ uint8_t bfZe3ddWidth;\r
+\r
+ uint8_t bfZe3dd;\r
+\r
+ uint8_t bfAzSI;\r
+\r
+ uint8_t bfZeSI;\r
+\r
+ };\r
+\r
+For section extension type 2, the structure of xran_sectionext2_info is\r
+used. Each parameter will be packed as specified bit width.::\r
+\r
+ struct xran_sectionext4_info {\r
+\r
+ uint8_t csf;\r
+\r
+ uint8_t pad0;\r
+\r
+ uint16_t modCompScaler;\r
+\r
+ };\r
+\r
+For section extension type 4, the structure of xran_sectionext4_info is\r
+used.::\r
+\r
+ struct xran_sectionext5_info {\r
+\r
+ uint8_t num_sets;\r
+\r
+ struct {\r
+\r
+ uint16_t csf;\r
+\r
+ uint16_t mcScaleReMask;\r
+\r
+ uint16_t mcScaleOffset;\r
+\r
+ } mc[XRAN_MAX_MODCOMP_ADDPARMS];\r
+\r
+ };\r
+\r
+For section extension type 5, the structure of xran_sectionext5_info is\r
+used. Please note that current implementation supports maximum two sets\r
+of additional parameters.::\r
+\r
+ struct xran_sectionext6_info {\r
+\r
+ uint8_t rbgSize;\r
+\r
+ uint8_t pad;\r
+\r
+ uint16_t symbolMask;\r
+\r
+ uint32_t rbgMask;\r
+\r
+ };\r
+\r
+ For section extension type 6, the structure of xran_sectionext6_info is\r
+ used.\r
+\r
+ struct xran_sectionext10_info {\r
+\r
+ uint8_t numPortc;\r
+\r
+ uint8_t beamGrpType;\r
+\r
+ uint16_t beamID[XRAN_MAX_NUMPORTC_EXT10];\r
+\r
+ };\r
+\r
+For section extension type 10, the structure of xran_sectionext10_info\r
+is used.::\r
+\r
+ struct xran_sectionext11_info {\r
+\r
+ uint8_t RAD;\r
+\r
+ uint8_t disableBFWs;\r
+\r
+ uint8_t numBundPrb;\r
+\r
+ uint8_t numSetBFWs; /\* Total number of beam forming weights set (L) \*/\r
+\r
+ uint8_t bfwCompMeth;\r
+\r
+ uint8_t bfwIqWidth;\r
+\r
+ int totalBfwIQLen;\r
+\r
+ int maxExtBufSize; /\* Maximum space of external buffer \*/\r
+\r
+ uint8_t \*pExtBuf; /\* pointer to start of external buffer \*/\r
+\r
+ void \*pExtBufShinfo; /\* Pointer to rte_mbuf_ext_shared_info \*/\r
+\r
+ };\r
+\r
+For section extension type 11, the structure of xran_sectionext11_info\r
+is used.\r
+\r
+To minimize memory copy for beamforming weights, when section extension\r
+11 is required to send beamforming weights(BFWs), external flat buffer\r
+is being used in current release. If extension 11 is used, it will be\r
+used instead of mbufs that pre-allocated external buffers which BFWs\r
+have been prepared already. BFW can be prepared by\r
+xran_cp_prepare_ext11_bfws() and the example usage can be found from\r
+app_init_xran_iq_content() from sample-app.c.\r
+\r
+Detail Procedures in API\r
+''''''''''''''''''''''''\r
+\r
+xran_prepare_ctrl_pkt() has several procedures to compose a C-Plane\r
+packet.\r
+\r
+1. Append transport header\r
+\r
+- Reserve eCPRI header space in the packet buffer\r
+\r
+- eCPRI version is fixed by XRAN_ECPRI_VER (0x0001)\r
+\r
+- Concatenation and transport layer fragmentation is not supported.\r
+\r
+ ecpri_concat=0, ecpri_seq_id.sub_seq_id=0 and ecpri_seq_id.e_bit=1\r
+\r
+- The caller needs to provide a component carrier index, antenna index,\r
+ and message identifier through function arguments.\r
+\r
+ CC_ID, Ant_ID and seq_id\r
+\r
+- ecpriRtcid (ecpri_xtc_id) is composed with CC_ID and Ant_ID by\r
+ xran_compose_cid.\r
+\r
+- DU port ID and band sector ID are fixed by zero in this release.\r
+\r
+- The output of xran_compose_cid is stored in network byte order.\r
+\r
+- The length of the payload is initialized by zero.\r
+\r
+2. Append radio application header:\r
+\r
+- xran_append_radioapp_header() checks the type of section through\r
+ params->sectionType and determines proper function to append\r
+ remaining header components.\r
+\r
+- Only section type 1 and 3 are supported, returns\r
+ XRAN_STATUS_INVALID_PARAM for other types.\r
+\r
+- Each section uses a different function to compose the remaining\r
+ header and size to calculate the total length in the transport\r
+ header.\r
+\r
+For section type 1, xran_prepare_section1_hdr() and sizeof(struct\r
+xran_cp_radioapp_section1_header)\r
+\r
+For section type 3, xran_prepare_section3_hdr() and sizeof(struct\r
+xran_cp_radioapp_section3_header)\r
+\r
+- Reserves the space of common radio application header and composes\r
+ header by xran_prepare_radioapp_common_header().\r
+\r
+- The header is stored in network byte order.\r
+\r
+- Appends remaining header components by the selected function above\r
+\r
+- The header is stored in network byte order\r
+\r
+3. Append section header and section\r
+\r
+- xran_append_control_section() determines proper size and function to\r
+ append section header and contents.\r
+\r
+- For section type 1, xran_prepare_section1() and sizeof(struct\r
+ xran_cp_radioapp_section1)\r
+\r
+- For section type 3, xran_prepare_section3() and sizeof(struct\r
+ xran_cp_radioapp_section3)\r
+\r
+- Appends section header and section(s) by selected function above.\r
+\r
+- If multiple sections are configured, then those will be added.\r
+\r
+- Since fragmentation is not considered in this implementation, the\r
+ total length of a single C-Plane message shall not exceed MTU\r
+ size.\r
+\r
+- The header and section(s) are stored in network byte order.\r
+\r
+- Appends section extensions if it is set (ef=1)\r
+\r
+- xran_append_section_extensions() adds all configured extensions by\r
+ its type.\r
+\r
+- xran_prepare_sectionext_x() (x = 1,2,4,5) will be called by the\r
+ type from xran_append_section_extensions() and these functions\r
+ will create extension field.\r
+\r
+Example Usage of API\r
+''''''''''''''''''''\r
+\r
+There are two reference usages of API to generate C-Plane messages:\r
+\r
+- xran_cp_create_and_send_section() in xran_main.c\r
+\r
+- generate_cpmsg_prach() in xran_common.c\r
+\r
+The xran_cp_create_and_send_section() is to generate the C-Plane message\r
+with section type 1 for DL or UL symbol data scheduling.\r
+\r
+This function has hardcoded values for some parameters such as:\r
+\r
+- The filter index is fixed to XRAN_FILTERINDEX_STANDARD.\r
+\r
+- RB indicator is fixed to XRAN_RBIND_EVERY.\r
+\r
+- Symbol increment is not used (XRAN_SYMBOLNUMBER_NOTINC)\r
+\r
+- Resource Element Mask is fixed to 0xfff\r
+\r
+If section extensions include extension 1 or 11, direct mbuf will not be\r
+allocated/used and pre-allocated flat buffer will be attached to\r
+indirect mbuf. This external buffer will be used to compose C-Plane\r
+message and should have BFWs already by xran_cp_populate_section_ext_1()\r
+or xran_cp_prepare_ext11_bfws().\r
+\r
+Since current implementation uses single section single C-Plane message,\r
+if multi sections are present, this function will generate same amount\r
+of C-Plane messages with the number of sections.\r
+\r
+After C-Plane message generation, it will send generated packet to TX\r
+ring after adding an Ethernet header and also will add section\r
+information of generated C-Plane packet to section database, to generate\r
+U-plane message by C-Plane configuration.\r
+\r
+The generate_cpmsg_prach()is to generate the C-Plane message with\r
+section type 3 for PRACH scheduling.\r
+\r
+This functions also has some hardcoded values for the following\r
+parameters:\r
+\r
+- RB indicator is fixed to XRAN_RBIND_EVERY.\r
+\r
+- Symbol increment is not used (XRAN_SYMBOLNUMBER_NOTINC).\r
+\r
+- Resource Element Mask is fixed to 0xfff.\r
+\r
+This function does not send generated packet, send_cpmsg() should be\r
+called after this function call. The example can be found from\r
+tx_cp_ul_cb() in xran_main.c. Checking and parsing received PRACH symbol\r
+data by section information from the C-Plane are not implemented in this\r
+release.\r
+\r
+Example Configuration of C-Plane Messages\r
+'''''''''''''''''''''''''''''''''''''''''\r
+\r
+C-Plane messages can be composed through API, and the sample application\r
+shows several reference usages of the configuration for different\r
+numerologies.\r
+\r
+Below are the examples of C-Plane message configuration with a sample\r
+application for mmWave – numerology 3, 100 MHz bandwidth, TDD (DDDS)\r
+\r
+**C-Plane Message – downlink symbol data for a downlink slot**\r
+\r
+- Single CP message with the single section of section type 1\r
+\r
+- Configures single CP message for all consecutive downlink symbols\r
+\r
+- Configures whole RBs (66) for a symbol\r
+\r
+- Compression and beamforming are not used\r
+\r
+Common Header Fields::\r
+\r
+- dataDirection = XRAN_DIR_DL\r
+- payloadVersion = XRAN_PAYLOAD_VER\r
+- filterIndex = XRAN_FILTERINDEX_STANDARD\r
+- frameId = [0..99]\r
+- subframeId = [0..9]\r
+- slotID = [0..9]\r
+- startSymbolid = 0\r
+- numberOfsections = 1\r
+- sectionType = XRAN_CP_SECTIONTYPE_1\r
+- udCompHdr.idIqWidth = 0\r
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE\r
+- reserved = 0\r
+\r
+Section Fields::\r
+\r
+- sectionId = [0..4095]\r
+- rb = XRAN_RBIND_EVERY\r
+- symInc = XRAN_SYMBOLNUMBER_NOTINC \r
+- startPrbc = 0\r
+- numPrbc = 66\r
+- reMask = 0xfff\r
+- numSymbol = 14\r
+- ef = 0\r
+- beamId = 0\r
+\r
+\r
+**C-Plane Message – uplink symbol data for uplink slot**\r
+\r
+- Single CP message with the single section of section type 1\r
+\r
+- Configures single CP message for all consecutive uplink symbols (UL\r
+ symbol starts from 3)\r
+\r
+- Configures whole RBs (66) for a symbol\r
+\r
+- Compression and beamforming are not used\r
+\r
+Common Header Fields::\r
+\r
+- dataDirection = XRAN_DIR_UL\r
+- payloadVersion = XRAN_PAYLOAD_VER\r
+- filterIndex = XRAN_FILTERINDEX_STANDARD\r
+- frameId = [0..99]\r
+- subframeId = [0..9]\r
+- slotID = [0..9]\r
+- startSymbolid = 3\r
+- numberOfsections = 1\r
+- sectionType = XRAN_CP_SECTIONTYPE_1\r
+- udCompHdr.idIqWidth = 0\r
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE\r
+- reserved = 0\r
+\r
+Section Fields::\r
+\r
+- sectionId = [0..4095]\r
+- rb = XRAN_RBIND_EVERY\r
+- symInc = XRAN_SYMBOLNUMBER_NOTINC \r
+- startPrbc = 0\r
+- numPrbc = 66\r
+- reMask = 0xfff\r
+- numSymbol = 11\r
+- ef = 0\r
+- beamId = 0\r
+\r
+\r
+**C-Plane Message – PRACH**\r
+\r
+- Single CP message with the single section of section type 3 including\r
+ repetition\r
+\r
+- Configures PRACH format A3, config index 81, and detail parameters\r
+ are:\r
+\r
+- Filter Index : 3\r
+\r
+- CP length : 0\r
+\r
+- Time offset : 2026\r
+\r
+- FFT size : 1024\r
+\r
+- Subcarrier spacing : 120KHz\r
+\r
+- Start symbol index : 7\r
+\r
+- Number of symbols : 6\r
+\r
+- Number of PRBCs : 12\r
+\r
+- Frequency offset : -792\r
+\r
+- Compression and beamforming are not used\r
+\r
+Common Header Fields::\r
+\r
+- dataDirection = XRAN_DIR_UL\r
+- payloadVersion = XRAN_PAYLOAD_VER\r
+- filterIndex = XRAN_FILTERINDEPRACH_ABC\r
+- frameId = [0,99]\r
+- subframeId = [0,3]\r
+- slotID = 3 or 7\r
+- startSymbolid = 7\r
+- numberOfSections = 1\r
+- sectionType = XRAN_CP_SECTIONTYPE_3\r
+- timeOffset = 2026\r
+- frameStructure.FFTSize = XRAN_FFTSIZE_1024\r
+- frameStructure.u = XRAN_SCS_120KHZ\r
+- cpLength = 0\r
+- udCompHdr.idIqWidth = 0\r
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE\r
+\r
+Section Fields::\r
+\r
+- sectionId = [0..4095]\r
+- rb = XRAN_RBIND_EVERY\r
+- symInc = XRAN_SYMBOLNUMBER_NOTINC \r
+- startPrbc = 0\r
+- numPrbc = 12\r
+- reMask = 0xfff\r
+- numSymbol = 6\r
+- ef = 0\r
+- beamId = 0\r
+- frequencyOffset = -792\r
+- reserved\r
+\r
+\r
+Functions to Store/Retrieve Section Information\r
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\r
+\r
+There are several functions to store/retrieve section information of\r
+C-Plane messages. Since U-plane messages must be generated by the\r
+information in the sections of a C-Plane message, it is required to\r
+store and retrieve section information.\r
+\r
+**APIs and Data Structure**\r
+'''''''''''''''''''''''''''\r
+\r
+APIs for initialization and release storage are:\r
+\r
+- int xran_cp_init_sectiondb(void \*pHandle);\r
+\r
+- int xran_cp_free_sectiondb(void \*pHandle);\r
+\r
+APIs to store and retrieve section information are:\r
+\r
+- int xran_cp_add_section_info(void \*pHandle, uint8_t dir, uint8_t\r
+ cc_id, uint8_t ruport_id, uint8_t ctx_id, struct xran_section_info\r
+ \*info);\r
+\r
+- int xran_cp_add_multisection_info(void \*pHandle, uint8_t cc_id,\r
+ uint8_t ruport_id, uint8_t ctx_id, struct xran_cp_gen_params\r
+ \*gen_info);\r
+\r
+- struct xran_section_info \*xran_cp_find_section_info(void \*pHandle,\r
+ uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t ctx_id,\r
+ uint16_t section_id);\r
+\r
+- struct xran_section_info \*xran_cp_iterate_section_info(void\r
+ \*pHandle, uint8_t dir, uint8_t cc_id, uint8_t ruport_id, uint8_t\r
+ ctx_id, uint32_t \*next);\r
+\r
+- int xran_cp_getsize_section_info(void \*pHandle, uint8_t dir, uint8_t\r
+ cc_id, uint8_t ruport_id, uint8_t ctx_id);\r
+\r
+APIs to reset the storage for a new slot are:\r
+\r
+- int xran_cp_reset_section_info(void \*pHandle, uint8_t dir, uint8_t\r
+ cc_id, uint8_t ruport_id, uint8_t ctx_id);\r
+\r
+The structure of xran_section_info is used to store/retrieve\r
+information. This is the same structure used to generate a C-Plane\r
+message. Please refer to Section 5.4.2.1.1 for more details.\r
+\r
+The storage for section information is declared as a multi-dimensional\r
+array and declared as a local static variable to limit direct access.\r
+Each item is defined as the structure of xran_sectioninfo_db, and it has\r
+the number of stored section information items (cur_index) and the array\r
+of the information (list), as shown below.\r
+\r
+/*\r
+\r
+\* This structure to store the section information of C-Plane\r
+\r
+\* in order to generate and parse corresponding U-Plane \*/\r
+\r
+struct xran_sectioninfo_db {\r
+\r
+uint32_t cur_index; /* Current index to store for this eAXC \*/\r
+\r
+struct xran_section_info list[XRAN_MAX_NUM_SECTIONS]; /* The array of\r
+section information \*/\r
+\r
+};\r
+\r
+static struct xran_sectioninfo_db\r
+sectiondb[XRAN_MAX_SECTIONDB_CTX][XRAN_DIR_MAX][XRAN_COMPONENT_CARRIERS_MAX][XRAN_MAX_ANTENNA_NR*2\r
++ XRAN_MAX_ANT_ARRAY_ELM_NR];\r
+\r
+The maximum size of the array can be adjusted if required by system\r
+configuration. Since transmission and reception window of U-Plane can be\r
+overlapped with the start of new C-Plane for next slot, functions have\r
+context index to identify and protect the information. Currently the\r
+maximum number of context is defined by two and it can be adjusted if\r
+needed.\r
+\r
+Note. Since the context index is not managed by the library and APIs are\r
+expecting it from the caller as a parameter, the caller shall\r
+consider a proper method to manage it to avoid corruption. The\r
+current reference implementation uses a slot and subframe index to\r
+calculate the context index.\r
+\r
+**Example Usage of APIs**\r
+'''''''''''''''''''''''''\r
+\r
+There are references to show the usage of APIs as below.\r
+\r
+- Initialization and release:\r
+\r
+- xran_cp_init_sectiondb(): xran_open() in lib/src/xran_main.c\r
+\r
+- xran_cp_free_sectiondb(): xran_close() in lib/src/xran_main.c\r
+\r
+- Store section information:\r
+\r
+- xran_cp_add_section_info(): send_cpmsg_dlul() and\r
+ send_cpmsg_prach()in lib/src/xran_main.c\r
+\r
+- Retrieve section information:\r
+\r
+- xran_cp_iterate_section_info(): xran_process_tx_sym() in\r
+ lib/src/xran_main.c\r
+\r
+- xran_cp_getsize_section_info(): xran_process_tx_sym() in\r
+ lib/src/xran_main.c\r
+\r
+- Reset the storage for a new slot:\r
+\r
+- xran_cp_reset_section_info(): tx_cp_dl_cb() and tx_cp_ul_cb() in\r
+ lib/src/xran_main.c\r
+\r
+**Function for RU emulation and Debug**\r
+'''''''''''''''''''''''''''''''''''''''\r
+\r
+xran_parse_cp_pkt() is a function which can be utilized for RU emulation\r
+or debug. It is defined below:\r
+\r
+int xran_parse_cp_pkt(struct rte_mbuf \*mbuf,\r
+\r
+struct xran_cp_gen_params \*result,\r
+\r
+struct xran_recv_packet_info \*pkt_info);\r
+\r
+It parses a received C-Plane packet and retrieves the information from\r
+its headers and sections.\r
+\r
+The retrieved information is stored in the structures:\r
+\r
+struct xran_cp_gen_params: section information from received C-Plane\r
+packet\r
+\r
+struct xran_recv_packet_info: transport layer header information (eCPRI\r
+header)\r
+\r
+These functions can be utilized to debug or RU emulation purposes.\r
+\r
+.. _u-plane-1:\r
+\r
+U-plane\r
+~~~~~~~\r
+\r
+Single Section is the default mode of xRAN packet creation. It assumes\r
+that there is only one section per packet, and all IQ samples are\r
+attached to it. Compression is not supported.\r
+\r
+A message is built in mbuf space given as a parameter. The library\r
+builds eCPRI header filling structure fields by taking the IQ sample\r
+size and populating a particular packet length and sequence number.\r
+\r
+With compression, supported IQ bit widths are 8,9,10,12,14.\r
+\r
+Implementation of a U-plane set of functions is defined in xran_up_api.c\r
+and is used to prepare U-plane packet content according to the given\r
+configuration.\r
+\r
+The following list of functions is implemented for U-plane:\r
+\r
+- Build eCPRI header\r
+\r
+- Build application header\r
+\r
+- Build section header\r
+\r
+- Append IQ samples to packet\r
+\r
+- Prepare full symbol of xRAN data for single eAxC\r
+\r
+- Process RX packet per symbol.\r
+\r
+The time of generation of a U-plane message for DL and UL is\r
+“symbol-based” and can be controlled using O-DU settings (O-RU),\r
+according to Table 4.\r
+\r
+Supporting Code\r
+---------------\r
+\r
+The xRAN library has a set of functions used to assist in packet\r
+processing and data exchange not directly used for xRAN packet\r
+processing.\r
+\r
+Timing\r
+~~~~~~\r
+\r
+The sense of time for the xRAN protocol is obtained from system time,\r
+where the system timer is synchronized to GPS time via PTP protocol\r
+using the Linux PHP package. On the software side, a simple polling loop\r
+is utilized to get time up to nanosecond precision and particular packet\r
+processing jobs are scheduled via the DPDK timer.\r
+\r
+long poll_next_tick(int interval)\r
+\r
+{\r
+\r
+struct timespec start_time;\r
+\r
+struct timespec cur_time;\r
+\r
+long target_time;\r
+\r
+long delta;\r
+\r
+clock_gettime(CLOCK_REALTIME, &start_time);\r
+\r
+target_time = (start_time.tv_sec \* NSEC_PER_SEC + start_time.tv_nsec +\r
+interval \* NSEC_PER_USEC) / (interval \* NSEC_PER_USEC) \* interval;\r
+\r
+while(1)\r
+\r
+{\r
+\r
+clock_gettime(CLOCK_REALTIME, &cur_time);\r
+\r
+delta = (cur_time.tv_sec \* NSEC_PER_SEC + cur_time.tv_nsec) -\r
+target_time \* NSEC_PER_USEC;\r
+\r
+if(delta > 0 \|\| (delta < 0 && abs(delta) < THRESHOLD))\r
+\r
+{\r
+\r
+break;\r
+\r
+}\r
+\r
+}\r
+\r
+return delta;\r
+\r
+}\r
+\r
+Polling is used to achieve the required precision of symbol time. For\r
+example, in the mmWave scenario, the symbol time is 125µs/14=~8.9µs.\r
+Small deterministic tasks can be executed within the polling interval\r
+provided. It’s smaller than the symbol interval time.\r
+\r
+DPDK Timers\r
+~~~~~~~~~~~\r
+\r
+DPDK provides sets of primitives (struct rte_rimer) and functions\r
+(rte_timer_reset_sync() rte_timer_manage()) to |br|\r
+schedule processing of\r
+function as timer. The timer is based on the TSC clock and is not\r
+synchronized to PTP time. As a |br|\r
+result, this timer cannot be used as a\r
+periodic timer because the TSC clock can drift substantially relative to\r
+the system timer which in turn is synchronized to PTP (GPS)\r
+\r
+Only single-shot timers are used to schedule processing based on\r
+events such as symbol time. The packet |br|\r
+processing function\r
+calls rte_timer_manage() in the loop, and the resulting execution of\r
+timer function happens right |br|\r
+after the timer was “armed”.\r
+\r
+xRAN Ethernet\r
+~~~~~~~~~~~~~\r
+\r
+xran_init_port() function performs initialization of DPDK ETH port.\r
+Standard port configuration is used as per reference example from DPDK.\r
+\r
+Jumbo Frames are used by default. Mbufs size is extended to support 9600\r
+bytes packets.\r
+\r
+Mac address and VLAN tag are expected to be configured by Infrastructure\r
+software. See Appendix A.4.\r
+\r
+From an implementation perspective, modules provide functions to handle:\r
+\r
+- Ethernet headers\r
+\r
+- VLAN tag\r
+\r
+- Send and Receive mbuf.\r
+\r
+xRAN Ethdi\r
+~~~~~~~~~~\r
+\r
+Ethdi provides functionality to work with the content of an Ethernet\r
+packet and dispatch processing to/from the xRAN layer. Ethdi\r
+instantiates a main PMD driver thread and dispatches packets between the\r
+ring and RX/TX using rte_eth_rx_burst() and rte_eth_tx_burst() DPDK\r
+functions.\r
+\r
+For received packets, it maintains a set of handlers for ethertype\r
+handlers and xRAN layer register one xRAN ethtype |br|\r
+0xAEFE, resulting in\r
+packets with this ethertype being routed to the xRAN processing\r
+function. This function checks the message type of the eCPRI header and\r
+dispatches packet to either C-plane processing or U-plane processing.\r
+\r
+Initialization of memory pools, allocation and freeing of mbuf for\r
+Ethernet packets occur in this layer.\r
+\r
+\r
+O-RAN One Way Delay Measurements\r
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\r
+\r
+The support for the eCPRI one- way delay measurements which are specified by\r
+the O-RAN to be used with the Measured Transport support per Section 2.3.3.3\r
+of the O-RAN-WG4.CUS.0-v4.00 specification and section 3.2.4.6 of the eCPRI_v2.0\r
+specification is implemented in the file xran_delay_measurement.c. Structure\r
+definitions used by the owd measurement functions are in the file xran_fh_o_du.h\r
+for common data and port specific variables and parameters.\r
+\r
+The implementation of this feature has been done under the assumption that the requestor\r
+is the O-DU and the recipient is the O-RU. All of the action_types per the eCPRI 2.0 have\r
+been implemented. In the current version the timestamps are obtained using the linux\r
+function clock_gettime using CLOCK_REALTIME as the clock_id argument.\r
+\r
+The implementation supports both the O-RU and the O-DU side in order to do the unit test\r
+in loopback mode.\r
+\r
+The one-delay measurements are enabled at configuration time and run right after the\r
+xran_start() function is executed. The total number of consecutive measurements per port\r
+should be a power of 2 and in order to minimize the system startup it is advisable that\r
+the number is 16 or below. \r
+\r
+The following functions can be found in the xran_delay_measurement.c:\r
+\r
+xran_ecpri_one_way_delay_measurement_transmitter() which is invoked from the\r
+process_dpdk_io()function if the one-way delay measurements are enabled. This is\r
+the main function for the owd transmitter.\r
+\r
+xran_generate_delay_meas() is a general function used by the transmitter to send the appropriate\r
+messages based on actionType and filling up all the details for the ethernet and ecpri layers.\r
+\r
+Process_delay_meas() this function is invoked from the handle_ecpri_ethertype() function when\r
+the ecpri message type is ECPRI_DELAY_MEASUREMENT. This is the main owd receiver function.\r
+\r
+From the Process_delay_meas() and depending on the message received we can execute one\r
+of the following functions\r
+\r
+xran_process_delmeas_request() If we received a request message.\r
+\r
+xran_process_delmeas_request_w_fup() If we received a request with follow up message.\r
+\r
+xran_process_delmeas_response() If we received a response message.\r
+\r
+xran_process_delmeas_rem_request() If we received a remote request message\r
+\r
+\r
+xran_delmeas_rem_request_w_fup() If we received a remote request with follow up message.\r
+\r
+All of the receiver functions also can generate the appropriate send message by using\r
+the DPDK function rte_eth_tx_burst() to minimize the response delay.\r
+\r
+Additional utility functions used by the owd implementation for managing of timestamps\r
+and time measurements are:\r
+\r
+xran_ptp_ts_to_ns() that takes a TimeStamp argument from a received owd ecpri packet and\r
+places it in host order and returns the value in nanoseconds.\r
+\r
+xran_timespec_to_ns() that takes an argument in timespec format like the return value from the\r
+linux function clock_gettime() and returns a value in nanoseconds.\r
+\r
+xran_ns_to_timespec() that takes an argument in nanoseconds and returns a value by\r
+reference in timespec format.\r
+\r
+xran_compute_and_report_delay_estimate() This function takes an average of the computed one way\r
+delay measurements and prints out the average value to the console expressed in nanoseconds.\r
+Currently we exclude the first 2 measurements from the average.\r
+\r
+Utility functions in support of the owd ecpri packet formulation are:\r
+\r
+xran_build_owd_meas_ecpri_hdr() Builds the ecpri header with message type ECPRI_DELAY_MEASUREMENT\r
+and writes the payload size in network order.\r
+\r
+xran_add_at_and_measId_to_header() This function is used to write the action Type and\r
+MeasurementID to the eCPRI owd header.\r
+\r
+The current implementation of the one way delay measurements only supports a fixed\r
+message size. The message is defined in the xran_pkt.h in the structure xran_ecpri_delay_meas_pl.\r
+\r
+The one-way delay measurements have been tested with the sample-app for the Front Haul Interface\r
+Library and have not yet been integrated with the L1 Layer functions.
\ No newline at end of file
Code Review / o-du / phy.git / commitdiff
