[Epic-ID:ODUHIGH-557][Task-ID:ODUHIGH-638] RACH Fixes: num_rootSeq and Slot_Config...

Change-Id: I6329b70018f926e6f64b7895b4fbb47bf031a7a4
Signed-off-by: svaidhya <svaidhya@radisys.com>

diff --git a/build/config/tdd_odu_config.xml b/build/config/tdd_odu_config.xml
index 42a3329..4082c15 100644 (file)
--- a/build/config/tdd_odu_config.xml
+++ b/build/config/tdd_odu_config.xml
@@ -563,10 +563,10 @@
          <NUM_PRACH_FDM>1</NUM_PRACH_FDM>
          <FDM_LIST>
             <FDM_INFO>
-               <ROOT_SEQ_IDX>0</ROOT_SEQ_IDX>
+               <ROOT_SEQ_IDX>1</ROOT_SEQ_IDX>
                <NUM_ROOT_SEQ>1</NUM_ROOT_SEQ>
                <K1>0</K1>
-               <ZERO_CORR_ZONE_CFG>4</ZERO_CORR_ZONE_CFG>
+               <ZERO_CORR_ZONE_CFG>12</ZERO_CORR_ZONE_CFG>
             </FDM_INFO>
          </FDM_LIST>
          <PRACH_RESTRICTED_SET_CFG>0</PRACH_RESTRICTED_SET_CFG>
@@ -579,11 +579,11 @@
          <RA_RSP_WINDOW>10</RA_RSP_WINDOW>
       </PRACH_CFG>
       <TDD_CFG>
-         <TDD_PERIODICITY>6</TDD_PERIODICITY>
-         <NUM_DL_SLOTS>7</NUM_DL_SLOTS>
-         <NUM_DL_SYMBOLS>12</NUM_DL_SYMBOLS>
-         <NUM_UL_SLOTS>2</NUM_UL_SLOTS>
-         <NUM_UL_SYMBOLS>1</NUM_UL_SYMBOLS>
+         <TDD_PERIODICITY>5</TDD_PERIODICITY>
+         <NUM_DL_SLOTS>3</NUM_DL_SLOTS>
+         <NUM_DL_SYMBOLS>6</NUM_DL_SYMBOLS>
+         <NUM_UL_SLOTS>1</NUM_UL_SLOTS>
+         <NUM_UL_SYMBOLS>4</NUM_UL_SYMBOLS>
       </TDD_CFG>
       <PRE_CODE_CFG>
          <NUM_LAYERS>1</NUM_LAYERS>

diff --git a/src/5gnrmac/lwr_mac_fsm.c b/src/5gnrmac/lwr_mac_fsm.c
index d11ca4f..adb87e7 100644 (file)
--- a/src/5gnrmac/lwr_mac_fsm.c
+++ b/src/5gnrmac/lwr_mac_fsm.c
@@ -2806,8 +2806,8 @@ uint8_t buildAndSendOAIConfigReqToL1(void *msg)
          sizeof(uint8_t), macCfgParams.prachCfg.prachCfgIdx << TLV_ALIGN(8), &msgLen);
    fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG, \
          sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].rootSeqIdx << TLV_ALIGN(16), &msgLen);
-   //fillTlvs(&configReq->tlvs[index++], FAPI_NUM_ROOT_SEQUENCES_TAG,        \
-   sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numRootSeq, &msgLen);
+   fillTlvs(&configReq->tlvs[index++], FAPI_NUM_ROOT_SEQUENCES_TAG,        \
+   sizeof(uint8_t), macCfgParams.prachCfg.fdm[0].numRootSeq << TLV_ALIGN(8), &msgLen);
    fillTlvs(&configReq->tlvs[index++], FAPI_K1_TAG,                        \
          sizeof(uint16_t), macCfgParams.prachCfg.fdm[0].k1 << TLV_ALIGN(16), &msgLen);
    fillTlvs(&configReq->tlvs[index++], FAPI_PRACH_ZERO_CORR_CONF_TAG ,     \

diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c
index 1c1d316..49db8f5 100644 (file)
--- a/src/5gnrsch/sch.c
+++ b/src/5gnrsch/sch.c
@@ -300,7 +300,7 @@ void schFillSlotConfig(SchCellCb *cell, TDDCfg tddCfg)
 {
    uint8_t slotIdx = 0, symbolIdx = 0;
 
-   for(slotIdx =0 ;slotIdx < MAX_TDD_PERIODICITY_SLOTS; slotIdx++) 
+   for(slotIdx =0 ;slotIdx < cell->numSlotsInPeriodicity; slotIdx++) 
    {
       for(symbolIdx = 0; symbolIdx < MAX_SYMB_PER_SLOT; symbolIdx++)
       {
@@ -312,8 +312,8 @@ void schFillSlotConfig(SchCellCb *cell, TDDCfg tddCfg)
          }
 
          /*Fill Full-FLEXI SLOT and as well as Flexi Symbols in 1 slot preceding FULL-UL slot*/ 
-         else if(slotIdx < (MAX_TDD_PERIODICITY_SLOTS - tddCfg.nrOfUlSlots -1) ||  \
-               (slotIdx == (MAX_TDD_PERIODICITY_SLOTS - tddCfg.nrOfUlSlots -1) && \
+         else if(slotIdx < (cell->numSlotsInPeriodicity - tddCfg.nrOfUlSlots -1) ||  \
+               (slotIdx == (cell->numSlotsInPeriodicity - tddCfg.nrOfUlSlots -1) && \
                 symbolIdx < (MAX_SYMB_PER_SLOT - tddCfg.nrOfUlSymbols)))
          {
               cell->slotCfg[slotIdx][symbolIdx] = FLEXI_SYMBOL; 

diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c
index 5b8b42c..3ce6c74 100644 (file)
--- a/src/5gnrsch/sch_rach.c
+++ b/src/5gnrsch/sch_rach.c
@@ -89,6 +89,7 @@ bool schCheckPrachOcc(SchCellCb *cell, SlotTimingInfo prachOccasionTimingInfo)
             return FALSE;
          }
 #endif
+         DU_LOG("\nINFO   --> SCH : PrachCfgIdx %d support UL slot:%d", prachCfgIdx,prachOccasionTimingInfo.slot);
          return TRUE;
       }
    }