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[Epic-ID: ODUHIGH-475][Task-ID: ODUHIGH-572] Fix LWR_MAC creation during PHY as INTEL_L1
96/12596/1
author
svaidhya
<svaidhya@radisys.com>
Thu, 7 Mar 2024 07:24:17 +0000
(12:54 +0530)
committer
svaidhya
<svaidhya@radisys.com>
Thu, 7 Mar 2024 07:26:00 +0000
(12:56 +0530)
Change-Id: Iabcebcfe0d348729f638d5c9982fa96655577891
Signed-off-by: svaidhya <svaidhya@radisys.com>
src/mt/mt_ss.h
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diff --git
a/src/mt/mt_ss.h
b/src/mt/mt_ss.h
index
68c0213
..
e213b7d
100755
(executable)
--- a/
src/mt/mt_ss.h
+++ b/
src/mt/mt_ss.h
@@
-66,7
+66,7
@@
#ifndef INTEL_WLS_MEM
#define SS_MAX_STSKS 9
#else
-#define SS_MAX_STSKS
7
+#define SS_MAX_STSKS
8
#endif
#endif
#endif /* SS_MULTICORE_SUPPORT */