schCellCfg.phyCellId = macCellCfg->phyCellId;
schCellCfg.bandwidth = macCellCfg->dlCarrCfg.bw;
schCellCfg.dupMode = macCellCfg->dupType;
- schCellCfg.ssbPbchPwr = macCellCfg->ssbCfg.ssbPbchPwr;
- schCellCfg.scsCommon = macCellCfg->ssbCfg.scsCmn;
- schCellCfg.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;
- schCellCfg.ssbPeriod = macCellCfg->ssbCfg.ssbPeriod;
- schCellCfg.ssbSubcOffset = macCellCfg->ssbCfg.ssbScOffset;
+
+ /* fill ssb scheduler parameters */
+ schCellCfg.ssbSchCfg.ssbPbchPwr = macCellCfg->ssbCfg.ssbPbchPwr;
+ schCellCfg.ssbSchCfg.scsCommon = macCellCfg->ssbCfg.scsCmn;
+ schCellCfg.ssbSchCfg.ssbOffsetPointA = macCellCfg->ssbCfg.ssbOffsetPointA;
+ schCellCfg.ssbSchCfg.ssbPeriod = macCellCfg->ssbCfg.ssbPeriod;
+ schCellCfg.ssbSchCfg.ssbSubcOffset = macCellCfg->ssbCfg.ssbScOffset;
for(uint8_t idx=0; idx<SSB_MASK_SIZE; idx++)
{
- schCellCfg.nSSBMask[idx] = macCellCfg->ssbCfg.ssbMask[idx];
+ schCellCfg.ssbSchCfg.nSSBMask[idx] = macCellCfg->ssbCfg.ssbMask[idx];
}
+
+ /* fill SIB1 scheduler parameters */
+ schCellCfg.sib1SchCfg.sib1PduLen = macCellCfg->sib1Cfg.sib1PduLen;
+ schCellCfg.sib1SchCfg.sib1NewTxPeriod = macCellCfg->sib1Cfg.sib1NewTxPeriod;
+ schCellCfg.sib1SchCfg.sib1RepetitionPeriod = macCellCfg->sib1Cfg.sib1RepetitionPeriod;
+ schCellCfg.sib1SchCfg.coresetZeroIndex = macCellCfg->sib1Cfg.coresetZeroIndex;
+ schCellCfg.sib1SchCfg.searchSpaceZeroIndex = macCellCfg->sib1Cfg.searchSpaceZeroIndex;
+ schCellCfg.sib1SchCfg.sib1Mcs = macCellCfg->sib1Cfg.sib1Mcs;
+
cfgPst.srcProcId = pst->dstProcId;
cfgPst.dstProcId = pst->srcProcId;
cfgPst.srcEnt = ENTRG;
#include "du_app_mac_inf.h"
#include "mac_sch_interface.h"
#include "sch.h"
+#include "sch_utils.h"
#include "du_log.h"
extern SchCb schCb[SCH_MAX_INST];
+extern int8_t coresetIdxTable[MAX_CORESET_INDEX][4];
+extern int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4];
/* local defines */
SchCellCfgCfmFunc SchCellCfgCfmOpts[] =
{
packSchCellCfgCfm /* LWLC */
};
+
/**
* @brief Task Initiation function.
*
cell->cellId = schCellCfg->cellId;
cell->instIdx = inst;
- switch(schCellCfg->scsCommon)
+ switch(schCellCfg->ssbSchCfg.scsCommon)
{
case SCH_SCS_15KHZ:
{
}
break;
default:
- DU_LOG("\nSCS %d not supported", schCellCfg->scsCommon);
+ DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon);
}
for(uint8_t idx=0; idx<SCH_NUM_SLOTS; idx++)
return RFAILED;
}
- schDlAlloc->totalPrb = ((schCellCfg->bandwidth *
- 1000)/(schCellCfg->scsCommon))/SCH_NUM_SC_PRB;
+ schDlAlloc->totalPrb = MAX_NUM_RB;
+
for(uint8_t itr=0; itr<MAX_SSB_IDX; itr++)
{
schDlAlloc->assignedPrb[itr] = 0;
return ROK;
}
+void fillSib1SchCfg(
+Inst schInst,
+Sib1SchCfg *sib1SchCfg,
+uint8_t pci,
+uint8_t offsetPointA
+)
+{
+ uint8_t coreset0Idx = 0;
+ uint8_t searchSpace0Idx = 0;
+ uint8_t ssbMuxPattern = 0;
+ uint8_t numRbs = 0;
+ uint8_t numSymbols = 0;
+ uint8_t offset = 0;
+ uint8_t oValue = 0;
+ uint8_t numSearchSpacePerSlot = 0;
+ uint8_t mValue = 0;
+ uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */
+ uint8_t slotIndex = 0;
+ uint8_t FreqDomainResource[6] = {0};
+
+ Sib1PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg);
+ Sib1PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg);
+
+ coreset0Idx = sib1SchCfg->coresetZeroIndex;
+ searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex;
+
+ /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */
+ ssbMuxPattern = coresetIdxTable[coreset0Idx][0];
+ numRbs = coresetIdxTable[coreset0Idx][1];
+ numSymbols = coresetIdxTable[coreset0Idx][2];
+ offset = coresetIdxTable[coreset0Idx][3];
+
+ /* derive the search space params from table 13-11 spec 38.213 */
+ oValue = searchSpaceIdxTable[searchSpace0Idx][0];
+ numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1];
+ mValue = searchSpaceIdxTable[searchSpace0Idx][2];
+ firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3];
+
+ /* calculate the n0, need to add the formulae, as of now the value is 0
+ * Need to add the even and odd values of i during configuration
+ * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe
+ * assuming u = 0, i = 0, numSlotsPerSubframe = 10
+ * Also, from this configuration, coreset0 is only on even subframe */
+ slotIndex = ((oValue * 1) + (0 * mValue)) % 10;
+ sib1SchCfg->n0 = slotIndex;
+
+ /* calculate the PRBs */
+ freqDomResourceAlloc((offsetPointA-offset),numRbs,FreqDomainResource);
+
+ /* fill the PDCCH PDU */
+ pdcch->sib1PdcchBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
+ pdcch->sib1PdcchBwpCfg.BWPStart = 0;
+ pdcch->subcarrierSpacing = 0; /* 15Khz */
+ pdcch->cyclicPrefix = 0; /* normal */
+ pdcch->sib1Coreset0Cfg.startSymbolIndex = firstSymbol;
+ pdcch->sib1Coreset0Cfg.durationSymbols = numSymbols;
+ memcpy(pdcch->sib1Coreset0Cfg.freqDomainResource,FreqDomainResource,6);
+ pdcch->sib1Coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
+ pdcch->sib1Coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->sib1Coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */
+ pdcch->sib1Coreset0Cfg.coreSetType = 0;
+ pdcch->sib1Coreset0Cfg.shiftIndex = pci;
+ pdcch->sib1Coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */
+ pdcch->numDlDci = 1;
+ pdcch->sib1DlDci.rnti = 0xFFFF; /* SI-RNTI */
+ pdcch->sib1DlDci.scramblingId = pci;
+ pdcch->sib1DlDci.scramblingRnti = 0;
+ pdcch->sib1DlDci.cceIndex = 0;
+ pdcch->sib1DlDci.aggregLevel = 4;
+ pdcch->sib1DlDci.beamPdcchInfo.numPrgs = 1;
+ pdcch->sib1DlDci.beamPdcchInfo.prgSize = 1;
+ pdcch->sib1DlDci.beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->sib1DlDci.beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->sib1DlDci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->sib1DlDci.txPdcchPower.powerValue = 0;
+ pdcch->sib1DlDci.txPdcchPower.powerControlOffsetSS = 0;
+
+ /* fill the PDSCH PDU */
+ uint8_t cwCount = 0;
+ pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */
+ pdsch->rnti = 0xFFFF; /* SI-RNTI */
+ pdsch->pduIndex = 0;
+ pdsch->sib1PdschBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */
+ pdsch->sib1PdschBwpCfg.BWPStart = 0;
+ pdsch->numCodewords = 1;
+ for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++)
+ {
+ pdsch->codeword[cwCount].targetCodeRate = 308;
+ pdsch->codeword[cwCount].qamModOrder = 2;
+ pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs;
+ pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */
+ pdsch->codeword[cwCount].rvIndex = 0;
+ pdsch->codeword[cwCount].tbSize = 768;
+ }
+ pdsch->dataScramblingId = pci;
+ pdsch->numLayers = 1;
+ pdsch->transmissionScheme = 0;
+ pdsch->refPoint = 0;
+ pdsch->dmrs.dlDmrsSymbPos = 2;
+ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */
+ pdsch->dmrs.dlDmrsScramblingId = pci;
+ pdsch->dmrs.scid = 0;
+ pdsch->dmrs.numDmrsCdmGrpsNoData = 1;
+ pdsch->dmrs.dmrsPorts = 0;
+ pdsch->sib1FreqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */
+ pdsch->sib1FreqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */
+ /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 *
+ * Ninfo = Nre . R . Qm . v *
+ * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh *
+ * Nre = min(156,Nre') . nPrb */
+ pdsch->sib1FreqAlloc.rbSize = 10; /* This value is calculated from above formulae */
+ pdsch->sib1FreqAlloc.vrbPrbMapping = 0; /* non-interleaved */
+ pdsch->sib1TimeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */
+ pdsch->sib1TimeAlloc.numSymbols = 12;
+ pdsch->beamPdschInfo.numPrgs = 1;
+ pdsch->beamPdschInfo.prgSize = 1;
+ pdsch->beamPdschInfo.digBfInterfaces = 0;
+ pdsch->beamPdschInfo.prg[0].pmIdx = 0;
+ pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0;
+ pdsch->txPdschPower.powerControlOffset = 0;
+ pdsch->txPdschPower.powerControlOffsetSS = 0;
+
+}
+
/**
* @brief cell config from MAC to SCH.
*
Inst inst = pst->dstInst-1;
InitSchCellCb(inst, schCellCfg);
- cellCb = schCb[inst].cells[inst];
+ cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst
cellCb->macInst = pst->srcInst;
memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));
+ /* derive the SIB1 config parameters */
+ fillSib1SchCfg(
+ inst,
+ &(schCellCfg->sib1SchCfg),
+ schCellCfg->phyCellId,
+ schCellCfg->ssbSchCfg.ssbOffsetPointA);
+
memset(&rspPst, 0, sizeof(Pst));
SCH_FILL_RSP_PST(rspPst, inst);
rspPst.event = EVENT_SCH_CELL_CFG_CFM;
#define SCH_MAX_CELLS 1
#define SCH_MAX_INST 1
#define SCH_NUM_SLOTS 10 /*forcing this to 10 */
+#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
#define SCH_MIB_TRANS 80
#define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */
#define SCH_MAX_SSB_BEAM 4 /* since we are supporting only SCS=15KHz */
SchCb schCb[SCH_MAX_INST];
/* function declarations */
-int schCmnDlAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc);
-int schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
+uint8_t schCmnDlAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc);
+uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst inst);
* @param[in] DlBrdcstAlloc *dlBrdcstAlloc, DL brdcst allocation
* @return void
**/
-int schCmnDlAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc)
+uint8_t schCmnDlAlloc(SchCellCb *cell, DlBrdcstAlloc *dlBrdcstAlloc)
{
/* schedule SSB */
uint8_t scs, ssbStartPrb, ssbStartSymb, idx;
dlAlloc = cell->dlAlloc[cell->slotInfo.slot];
if(dlBrdcstAlloc->ssbTrans)
{
- scs = cell->cellCfg.scsCommon;
+ scs = cell->cellCfg.ssbSchCfg.scsCommon;
ssbStartPrb = \
- ((cell->cellCfg.ssbSubcOffset)-(cell->cellCfg.ssbOffsetPointA))/SCH_NUM_SC_PRB;
+ ((cell->cellCfg.ssbSchCfg.ssbSubcOffset)-(cell->cellCfg.ssbSchCfg.ssbOffsetPointA))/SCH_NUM_SC_PRB;
memset(ssbStartSymbArr, 0, SCH_MAX_SSB_BEAM);
ssbDlTdAlloc(scs, ssbStartSymbArr);
}
}
+
+ /* SIB1 allocation */
+ if(dlBrdcstAlloc->sib1Trans)
+ {
+ memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdcchCfg, &cell->cellCfg.sib1SchCfg.sib1PdcchCfg, sizeof(Sib1PdcchCfg));
+ memcpy(&dlBrdcstAlloc->sib1Alloc.sib1PdschCfg, &cell->cellCfg.sib1SchCfg.sib1PdschCfg, sizeof(Sib1PdschCfg));
+ }
return ROK;
}
* RFAILED - failure
*
* ****************************************************************/
-int schProcessSlotInd(SlotIndInfo *slotInd, Inst schInst)
+uint8_t schProcessSlotInd(SlotIndInfo *slotInd, Inst schInst)
{
int ret = ROK;
uint8_t ssb_rep;
DlBrdcstAlloc dlBrdcstAlloc;
dlBrdcstAlloc.ssbTrans = NO_SSB;
+ dlBrdcstAlloc.sib1Trans = NO_SIB1;
SchCellCb *cell;
#ifdef LTE_L2_MEAS
#endif
cell = schCb[schInst].cells[schInst];
- ssb_rep = cell->cellCfg.ssbPeriod;
+ ssb_rep = cell->cellCfg.ssbSchCfg.ssbPeriod;
memcpy(&cell->slotInfo, slotInd, sizeof(SlotIndInfo));
memcpy(&dlBrdcstAlloc.slotIndInfo, slotInd, sizeof(SlotIndInfo));
dlBrdcstAlloc.cellId = cell->cellId;
dlBrdcstAlloc.ssbIdxSupported = 1;
+ uint16_t sfnSlot = (slotInd->sfn * 10) + slotInd->slot;
+
/* Identify SSB ocassion*/
- if ((slotInd->sfn % SCH_MIB_TRANS == 0))// && (slotInd.slot == 0))
+ if (sfnSlot % SCH_MIB_TRANS == 0)
{
dlBrdcstAlloc.ssbTrans = SSB_TRANSMISSION;
}
- else if ((slotInd->sfn % ssb_rep == 0))// && (slotInd.slot == 0))
+ else if (sfnSlot % ssb_rep == 0)
{
dlBrdcstAlloc.ssbTrans = SSB_REPEAT;
}
else
{
- ;
+ /* not SSB occassion */
+ }
+
+ /* Identify SIB1 occasions */
+ if(sfnSlot % cell->cellCfg.sib1SchCfg.sib1NewTxPeriod == 0)
+ {
+ dlBrdcstAlloc.sib1Trans = SIB1_TRANSMISSION;
+ }
+ else if (sfnSlot % cell->cellCfg.sib1SchCfg.sib1RepetitionPeriod == 0)
+ {
+ dlBrdcstAlloc.sib1Trans = SIB1_REPITITION;
+ }
+ else
+ {
+ /* not SIB1 occassion */
}
- schCmnDlAlloc(cell, &dlBrdcstAlloc);
+
+ if(dlBrdcstAlloc.ssbTrans || dlBrdcstAlloc.sib1Trans)
+ {
+ ret = schCmnDlAlloc(cell, &dlBrdcstAlloc);
+ if(ret != ROK)
+ {
+ DU_LOG("\nschCmnDlAlloc failed");
+ RETVALUE(ret);
+ }
+ }
+
//send msg to MAC
ret = sendDlBrdcstAllocToMac(&dlBrdcstAlloc, schInst);
if(ret != ROK)
DU_LOG("\nSending DL Broadcast allocation from SCH to MAC failed");
RETVALUE(ret);
}
+
return ret;
}
--- /dev/null
+/*******************************************************************************
+################################################################################
+# Copyright (c) [2017-2019] [Radisys] #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+################################################################################
+*******************************************************************************/
+
+/************************************************************************
+
+ Name: sch_utils.c
+
+ Type: C source file
+
+ Desc: C source code for scheduler utilities
+
+ File: sch_utils.c
+
+**********************************************************************/
+
+/** @file sch_utils.c
+@brief This file implements the schedulers util functions.
+*/
+
+/* header files */
+#include "sch_utils.h"
+
+/* spec-38.213 Table 13-1 */
+int8_t coresetIdxTable[MAX_CORESET_INDEX][4] = {
+{ 1, 24, 2, 0}, /* index 0 */
+{ 1, 24, 2, 2}, /* index 1 */
+{ 1, 24, 2, 4}, /* index 2 */
+{ 1, 24, 3, 0}, /* index 3 */
+{ 1, 24, 3, 2}, /* index 4 */
+{ 1, 24, 3, 4}, /* index 5 */
+{ 1, 48, 1, 12}, /* index 6 */
+{ 1, 48, 1, 16}, /* index 7 */
+{ 1, 48, 2, 12}, /* index 8 */
+{ 1, 48, 2, 16}, /* index 9 */
+{ 1, 48, 3, 12}, /* index 10 */
+{ 1, 48, 3, 16}, /* index 11 */
+{ 1, 96, 1, 38}, /* index 12 */
+{ 1, 96, 2, 38}, /* index 13 */
+{ 1, 96, 3, 38}, /* index 14 */
+{ 0, 0, 0, 0}, /* index 15 */
+};
+
+/* spec-38.213 Table 13-11 */
+/* m value is scaled to 2, when using it in formula, divide by 2 */
+/* firstSymbol will vary depends on i, hence not filled */
+int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4] = {
+{ 0, 1, 2, 0}, /* index 0 */
+{ 0, 2, 1, 0}, /* index 1 */
+{ 2, 1, 2, 0}, /* index 2 */
+{ 2, 2, 1, 0}, /* index 3 */
+{ 5, 1, 2, 0}, /* index 4 */
+{ 5, 2, 1, 0}, /* index 5 */
+{ 7, 1, 2, 0}, /* index 6 */
+{ 7, 2, 1, 0}, /* index 7 */
+{ 0, 1, 4, 0}, /* index 8 */
+{ 5, 1, 4, 0}, /* index 9 */
+{ 0, 1, 2, 0}, /* index 10 */
+{ 0, 1, 2, 0}, /* index 11 */
+{ 2, 1, 2, 0}, /* index 12 */
+{ 2, 1, 2, 0}, /* index 13 */
+{ 5, 1, 2, 0}, /* index 14 */
+{ 5, 1, 2, 0}, /* index 15 */
+};
+/**
+ * @brief frequency domain allocation function.
+ *
+ * @details
+ *
+ * Function : freqDomResourceAlloc
+ *
+ * This function does allocation in frequency domain resource. using
+ * bitwise operator, the bits are set for the PRBs.
+ *
+ * @param[in] startPrb - start PRB from where the freq alloc starts.
+ * @param[in] prbSize - number of PRBs to be allocted.
+ * @param[in] freqDomain - 6 bytes of info, each bit represents a group of 6 PRB.
+ * @return void
+ **/
+void freqDomResourceAlloc(uint16_t startPrb, uint16_t prbSize, uint8_t *freqDomain)
+{
+ uint8_t remBits = prbSize/6; /* each bit represents 6 PRBs */
+ uint8_t firstByte = 1;
+ uint8_t numBits,startBit,byteCount = 0;
+
+ while(remBits)
+ {
+ /* when the startPrb is not in this byteCount */
+ if(startPrb/8)
+ {
+ startPrb -= 8;
+ byteCount++;
+ continue;
+ }
+
+ /* max bytecount is 6 nearly equal to 45 bits*/
+ if(byteCount >= 6)
+ break;
+
+ /* when we are filling the second byte, then the start should be equal to 0 */
+ if(firstByte)
+ startBit = startPrb;
+ else
+ startBit = 0;
+
+ /* calculate the number of bits to be set in this byte */
+ if((remBits+startPrb) <= 8)
+ numBits = remBits;
+ else
+ numBits = 8 - startBit;
+
+ /* bit operation to set the bits */
+ SET_BITS((startBit % 8),numBits,freqDomain[byteCount])
+ firstByte = 0;
+
+ /* the ramaining bits should be subtracted with the numBits set in this byte */
+ remBits -= numBits;
+ byteCount++;
+ }
+}
+
+/**********************************************************************
+ End of file
+**********************************************************************/
--- /dev/null
+/*******************************************************************************
+################################################################################
+# Copyright (c) [2017-2019] [Radisys] #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+################################################################################
+*******************************************************************************/
+
+#include <stdint.h>
+
+/* macros */
+#define MAX_CORESET_INDEX 16
+#define MAX_SEARCH_SPACE_INDEX 16
+
+#define SET_BITS(_startBit, _numBits, _byte) \
+{ \
+ _byte = (((~((~0)<<_numBits))<<_startBit)); \
+}
+
+/* functions declarations */
+void freqDomResourceAlloc(uint16_t startPrb, uint16_t prbSize, uint8_t *freqDomain);
+
+/**********************************************************************
+ End of file
+**********************************************************************/
#define SSB_REPEAT 2
#define MAX_SSB_IDX 1 /* forcing it as 1 for now. Right value is 64 */
+#define NO_SIB1 0
+#define SIB1_TRANSMISSION 1
+#define SIB1_REPITITION 2
+
+#define MAX_NUM_PRG 1 /* max value should be later 275 */
+#define MAX_DIG_BF_INTERFACES 0 /* max value should be later 255 */
+#define MAX_CODEWORDS 1 /* max should be 2 */
+
/*structures*/
RSP_NOK
}schMacRsp;
+typedef struct
+{
+ uint32_t ssbPbchPwr; /* SSB block power */
+ uint8_t scsCommon; /* subcarrier spacing for common [0-3]*/
+ uint8_t ssbOffsetPointA; /* SSB sub carrier offset from point A */
+ SSBPeriod ssbPeriod; /* SSB Periodicity in msec */
+ uint8_t ssbSubcOffset; /* Subcarrier Offset(Kssb) */
+ uint32_t nSSBMask[SSB_MASK_SIZE]; /* Bitmap for actually transmitted SSB. */
+} SsbSchCfg;
+
+/* SIB1 interface structure */
+typedef struct bwpCfg
+{
+ uint16_t BWPSize;
+ uint16_t BWPStart;
+}BwpCfg;
+
+typedef struct coresetCfg
+{
+ uint8_t startSymbolIndex;
+ uint8_t durationSymbols;
+ uint8_t freqDomainResource[6];
+ uint8_t cceRegMappingType;
+ uint8_t regBundleSize;
+ uint8_t interleaverSize;
+ uint8_t coreSetType;
+ uint16_t shiftIndex;
+ uint8_t precoderGranularity;
+ uint8_t cceIndex;
+ uint8_t aggregationLevel;
+} CoresetCfg;
+
+typedef struct prg
+{
+ uint16_t pmIdx;
+ uint16_t beamIdx[MAX_DIG_BF_INTERFACES];
+} Prg;
+
+typedef struct beamformingInfo
+{
+ uint16_t numPrgs;
+ uint16_t prgSize;
+ uint8_t digBfInterfaces;
+ Prg prg[MAX_NUM_PRG];
+} BeamformingInfo;
+
+typedef struct txPowerPdcchInfo
+{
+ uint8_t powerValue;
+ uint8_t powerControlOffsetSS;
+} TxPowerPdcchInfo;
+
+typedef struct dlDCI
+{
+ uint16_t rnti;
+ uint16_t scramblingId;
+ uint16_t scramblingRnti;
+ uint8_t cceIndex;
+ uint8_t aggregLevel;
+ BeamformingInfo beamPdcchInfo;
+ TxPowerPdcchInfo txPdcchPower;
+} DlDCI;
+
+typedef struct sib1PdcchCfg
+{
+ BwpCfg sib1PdcchBwpCfg;
+
+ uint8_t subcarrierSpacing;
+ uint8_t cyclicPrefix;
+
+ /* coreset-0 configuration */
+ CoresetCfg sib1Coreset0Cfg;
+
+ uint16_t numDlDci;
+ DlDCI sib1DlDci; /* as of now its only one DCI, later it will be numDlCi */
+} Sib1PdcchCfg;
+/* end of SIB1 PDCCH structures */
+
+/* SIB1 PDSCH structures */
+
+typedef struct codewordinfo
+{
+ uint16_t targetCodeRate;
+ uint8_t qamModOrder;
+ uint8_t mcsIndex;
+ uint8_t mcsTable;
+ uint8_t rvIndex;
+ uint32_t tbSize;
+} CodewordInfo;
+
+typedef struct dmrsInfo
+{
+ uint16_t dlDmrsSymbPos;
+ uint8_t dmrsConfigType;
+ uint16_t dlDmrsScramblingId;
+ uint8_t scid;
+ uint8_t numDmrsCdmGrpsNoData;
+ uint16_t dmrsPorts;
+} DmrsInfo;
+
+typedef struct pdschFreqAlloc
+{
+ uint8_t resourceAlloc;
+ /* since we are using type-1, hence rbBitmap excluded */
+ uint16_t rbStart;
+ uint16_t rbSize;
+ uint8_t vrbPrbMapping;
+} PdschFreqAlloc;
+
+typedef struct pdschTimeAlloc
+{
+ uint8_t startSymbolIndex;
+ uint8_t numSymbols;
+} PdschTimeAlloc;
+
+typedef struct txPowerPdschInfo
+{
+ uint8_t powerControlOffset;
+ uint8_t powerControlOffsetSS;
+} TxPowerPdschInfo;
+
+typedef struct sib1PdschCfg
+{
+ uint16_t pduBitmap;
+ uint16_t rnti;
+ uint16_t pduIndex;
+ BwpCfg sib1PdschBwpCfg;
+ uint8_t numCodewords;
+ CodewordInfo codeword[MAX_CODEWORDS];
+ uint16_t dataScramblingId;
+ uint8_t numLayers;
+ uint8_t transmissionScheme;
+ uint8_t refPoint;
+ DmrsInfo dmrs;
+ PdschFreqAlloc sib1FreqAlloc;
+ PdschTimeAlloc sib1TimeAlloc;
+ BeamformingInfo beamPdschInfo;
+ TxPowerPdschInfo txPdschPower;
+} Sib1PdschCfg;
+/* SIB1 PDSCH structures end */
+
+typedef struct
+{
+ /* parameters recieved from DU-APP */
+ uint16_t sib1PduLen;
+ uint16_t sib1NewTxPeriod;
+ uint16_t sib1RepetitionPeriod;
+ uint8_t coresetZeroIndex; /* derived from 4 LSB of pdcchSib1 present in MIB */
+ uint8_t searchSpaceZeroIndex; /* derived from 4 MSB of pdcchSib1 present in MIB */
+ uint16_t sib1Mcs;
+
+ /* parameters derived in scheduler */
+ uint8_t n0;
+ Sib1PdcchCfg sib1PdcchCfg;
+ Sib1PdschCfg sib1PdschCfg;
+} Sib1SchCfg;
+
typedef struct schCellCfg
{
U16 cellId; /* Cell Id */
U16 phyCellId; /* Physical cell id */
U8 bandwidth; /* Supported B/W */
DuplexMode dupMode; /* Duplex type: TDD/FDD */
- U32 ssbPbchPwr; /* SSB block power */
- U8 scsCommon; /* subcarrier spacing for common [0-3]*/
- U16 ssbOffsetPointA; /* SSB sub carrier offset from point A */
- SSBPeriod ssbPeriod; /* SSB Periodicity in msec */
- U8 ssbSubcOffset; /* Subcarrier Offset(Kssb) */
- U32 nSSBMask[SSB_MASK_SIZE]; /* Bitmap for actually transmitted SSB. */
+ SsbSchCfg ssbSchCfg;
+ Sib1SchCfg sib1SchCfg;
}SchCellCfg;
typedef struct schCellCfgCfm
FreqDomainAlloc fdAlloc; /* Freq domain allocation */
}SsbInfo;
+typedef struct sib1AllocInfo
+{
+ Sib1PdcchCfg sib1PdcchCfg;
+ Sib1PdschCfg sib1PdschCfg;
+} Sib1AllocInfo;
+
/* Interface structure signifying DL broadcast allocation for SSB, SIB1 */
typedef struct dlBrdcstAlloc
{
* 1 : SIB1 Transmission
* 2 : SIB1 Repetition */
U8 sib1Trans;
+ Sib1AllocInfo sib1Alloc;
}DlBrdcstAlloc;
/* function pointers */
Code Review / o-du / l2.git / commitdiff