--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+
+<DU_CFG_PARAMS xmlns = "urn:o-ran:odu:configuration">
+ <THREAD_AFFINITY>
+ <DU_APP_CORE>16</DU_APP_CORE>
+ <EGTP_CORE>27</EGTP_CORE>
+ <RLC_MAC_CORE>18</RLC_MAC_CORE>
+ <RLC_UL_CORE>22</RLC_UL_CORE>
+ <SCH_CORE>22</SCH_CORE>
+ <SCTP_CORE>25</SCTP_CORE>
+ <LOWER_MAC_CORE>21</LOWER_MAC_CORE>
+ </THREAD_AFFINITY>
+ <GNB_ID>1</GNB_ID>
+ <DU_ID>1</DU_ID>
+ <DU_NAME>ORAN OAM DU</DU_NAME>
+ <MAX_NUM_DRB>29</MAX_NUM_DRB>
+ <DU_IP_V4_ADDR>192.168.130.81</DU_IP_V4_ADDR>
+ <CU_IP_V4_ADDR>192.168.130.82</CU_IP_V4_ADDR>
+ <RIC_IP_V4_ADDR>192.168.130.80</RIC_IP_V4_ADDR>
+ <SCTP>
+ <F1_SCTP_PORT>38472</F1_SCTP_PORT>
+ <E2_SCTP_PORT>36421</E2_SCTP_PORT>
+ <MAX_DU_PORT>2</MAX_DU_PORT>
+ </SCTP>
+ <EGTP>
+ <LOCAL_F1_EGTP_PORT>2152</LOCAL_F1_EGTP_PORT>
+ <DEST_F1_EGTP_PORT>2152</DEST_F1_EGTP_PORT>
+ <MIN_TEID>1</MIN_TEID>
+ </EGTP>
+ <SIB1_PARAMS>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ <TAC>1</TAC>
+ <RANAC>1</RANAC>
+ <CELL_IDENTITY>1</CELL_IDENTITY>
+ <CELL_RESVD_OPUSE>1</CELL_RESVD_OPUSE>
+ <CONN_EST_FAIL_CNT>2</CONN_EST_FAIL_CNT>
+ <CONN_EST_FAIL_OFF_VALID>7</CONN_EST_FAIL_OFF_VALID>
+ <CONN_EST_FAIL_OFFSET>15</CONN_EST_FAIL_OFFSET>
+ <SI_SHED_INFO>
+ <WIN_LEN>0</WIN_LEN>
+ <BROADCAST_STATUS>0</BROADCAST_STATUS>
+ <PERIODICITY>0</PERIODICITY>
+ <SIB_TYPE>0</SIB_TYPE>
+ <SIB1_VALUE_TAG>10</SIB1_VALUE_TAG>
+ </SI_SHED_INFO>
+ <SRV_CELL_CFG_COM_SIB>
+ <NR_SCS>1</NR_SCS>
+ <SSB_POS_INBURST>192</SSB_POS_INBURST>
+ <SSB_PERIODICITY>20</SSB_PERIODICITY>
+ <SSB_PBCH_PWR>0</SSB_PBCH_PWR>
+ <DL_CFG_COMMON>
+ <NR_FREQ_BAND>1</NR_FREQ_BAND>
+ <OFFSET_TO_POINT_A>24</OFFSET_TO_POINT_A>
+ <FREQ_LOC_BW>28875</FREQ_LOC_BW>
+ <SCS_SPEC_CARRIER>
+ <SSB_SUBCARRIER_OFFSET>0</SSB_SUBCARRIER_OFFSET>
+ <NR_SCS>1</NR_SCS>
+ <SCS_BW>100</SCS_BW>
+ </SCS_SPEC_CARRIER>
+ <PDCCH_CFG_COMMON>
+ <PRESENT>2</PRESENT>
+ <CORESET_0_INDEX>0</CORESET_0_INDEX>
+ <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
+ <PDCCH_SEARCH_SPACE_ID>1</PDCCH_SEARCH_SPACE_ID>
+ <PDCCH_CTRL_RSRC_SET_ID>0</PDCCH_CTRL_RSRC_SET_ID>
+ <MONITOR_SLOT_PERIOD_OFFSET_PRESENT>1</MONITOR_SLOT_PERIOD_OFFSET_PRESENT>
+ <MONITOR_LIST>
+ <MONITOR_SYMBOL_IN_SLOT>128</MONITOR_SYMBOL_IN_SLOT>
+ <MONITOR_SYMBOL_IN_SLOT>0</MONITOR_SYMBOL_IN_SLOT>
+ </MONITOR_LIST>
+ <NUM_CANDIDATE_AGG_LVL_1>7</NUM_CANDIDATE_AGG_LVL_1>
+ <NUM_CANDIDATE_AGG_LVL_2>4</NUM_CANDIDATE_AGG_LVL_2>
+ <NUM_CANDIDATE_AGG_LVL_4>2</NUM_CANDIDATE_AGG_LVL_4>
+ <NUM_CANDIDATE_AGG_LVL_8>1</NUM_CANDIDATE_AGG_LVL_8>
+ <NUM_CANDIDATE_AGG_LVL_16>0</NUM_CANDIDATE_AGG_LVL_16>
+ <SEARCH_SPACE_TYPE>1</SEARCH_SPACE_TYPE>
+ <PDCCH_SEARCH_SPACE_DCI_FORMAT>0</PDCCH_SEARCH_SPACE_DCI_FORMAT>
+ <PDCCH_SEARCH_SPACE_ID_SIB1>1</PDCCH_SEARCH_SPACE_ID_SIB1>
+ <PDCCH_SEARCH_SPACE_ID_PAGING>1</PDCCH_SEARCH_SPACE_ID_PAGING>
+ <PDCCH_SEARCH_SPACE_ID_RA>1</PDCCH_SEARCH_SPACE_ID_RA>
+ </PDCCH_CFG_COMMON>
+ <PDSCH_CFG_COMMON>
+ <PRESENT>2</PRESENT>
+ <NUM_TIME_DOM_RSRS_ALLOC>2</NUM_TIME_DOM_RSRS_ALLOC>
+ <PDSCH_TIME_DOM_RSRC_ALLOC_LIST>
+ <PDSCH_TIME_DOM_RSRC_ALLOC>
+ <K0>0</K0>
+ <MAP_TYPE>0</MAP_TYPE>
+ <PDSCH_START_SYMBOL>3</PDSCH_START_SYMBOL>
+ <PDSCH_LENGTH_SYMBOL>11</PDSCH_LENGTH_SYMBOL>
+ </PDSCH_TIME_DOM_RSRC_ALLOC>
+ <PDSCH_TIME_DOM_RSRC_ALLOC>
+ <K0>1</K0>
+ <MAP_TYPE>0</MAP_TYPE>
+ <PDSCH_START_SYMBOL>3</PDSCH_START_SYMBOL>
+ <PDSCH_LENGTH_SYMBOL>11</PDSCH_LENGTH_SYMBOL>
+ </PDSCH_TIME_DOM_RSRC_ALLOC>
+ </PDSCH_TIME_DOM_RSRC_ALLOC_LIST>
+ </PDSCH_CFG_COMMON>
+ <BCCH_CFG>
+ <MOB_PRD_COEFF>3</MOB_PRD_COEFF>
+ </BCCH_CFG>
+ <PCCH_CFG>
+ <DEFAULT_PAGING_CYCLE>256</DEFAULT_PAGING_CYCLE>
+ <NAND_PAGING_FRAME_OFFSET>1</NAND_PAGING_FRAME_OFFSET>
+ <PAGE_FRAME_OFFSET>0</PAGE_FRAME_OFFSET>
+ <NS>1</NS>
+ <FIRST_PDCCH_MONITORING_TYPE>2</FIRST_PDCCH_MONITORING_TYPE>
+ <FIRST_PDCCH_LIST>
+ <FIRST_PDCCH_MONITORING_INFO>44</FIRST_PDCCH_MONITORING_INFO>
+ </FIRST_PDCCH_LIST>
+ </PCCH_CFG>
+ </DL_CFG_COMMON>
+ <UL_CFG_COMMON>
+ <NR_FREQ_BAND>1</NR_FREQ_BAND>
+ <UL_P_MAX>23</UL_P_MAX>
+ <FREQ_LOC_BW>28875</FREQ_LOC_BW>
+ <TIME_ALLIGN_TIMER_COMM>7</TIME_ALLIGN_TIMER_COMM>
+ <SCS_SPEC_CARRIER>
+ <SSB_SUBCARRIER_OFFSET>0</SSB_SUBCARRIER_OFFSET>
+ <NR_SCS>1</NR_SCS>
+ <SCS_BW>100</SCS_BW>
+ </SCS_SPEC_CARRIER>
+ <RACH_CFG_COMMON>
+ <PRESENT>2</PRESENT>
+ <PRACH_CONFIG_IDX>88</PRACH_CONFIG_IDX>
+ <MSG_1_FDM>0</MSG_1_FDM>
+ <MAX_NUM_RB>273</MAX_NUM_RB>
+ <PRACH_MAX_PRB>24</PRACH_MAX_PRB>
+ <ZERO_CORRELATION_ZONE_CFG>4</ZERO_CORRELATION_ZONE_CFG>
+ <PRACH_PREAMBLE_RCVD_TGT_PWR>-74</PRACH_PREAMBLE_RCVD_TGT_PWR>
+ <PREAMBLE_TRANS_MAX>10</PREAMBLE_TRANS_MAX>
+ <PWR_RAMPING_STEP>1</PWR_RAMPING_STEP>
+ <RA_RSP_WINDOW>4</RA_RSP_WINDOW>
+ <NUM_RA_PREAMBLE>63</NUM_RA_PREAMBLE>
+ <NUM_SSB_PER_RACH_OCC>4</NUM_SSB_PER_RACH_OCC>
+ <CB_PREAMBLE_PER_SSB>8</CB_PREAMBLE_PER_SSB>
+ <CONT_RES_TIMER>7</CONT_RES_TIMER>
+ <RSRP_THRESHOLD_SSB>31</RSRP_THRESHOLD_SSB>
+ <ROOT_SEQ_IDX_PRESENT>2</ROOT_SEQ_IDX_PRESENT>
+ <ROOT_SEQ_IDX>0</ROOT_SEQ_IDX>
+ <PRACH_SUBCARRIER_SPACING>0</PRACH_SUBCARRIER_SPACING>
+ <PRACH_RESTRICTED_SET_CFG>0</PRACH_RESTRICTED_SET_CFG>
+ </RACH_CFG_COMMON>
+ <PUSCH_CFG_COMMON>
+ <PUSCH_CFG_PRESENT>2</PUSCH_CFG_PRESENT>
+ <PUSCH_MSG3_DELTA_PREAMBLE>0</PUSCH_MSG3_DELTA_PREAMBLE>
+ <PUSCH_P0_NOMINAL_WITH_GRANT>-70</PUSCH_P0_NOMINAL_WITH_GRANT>
+ <NUM_TIME_DOM_RSRC_ALLOC>2</NUM_TIME_DOM_RSRC_ALLOC>
+ <PUSCH_TIME_DOM_RSRC_ALLOC_LIST>
+ <PUSCH_TIME_DOM_RSRC_ALLOC>
+ <K2>4</K2>
+ <MAP_TYPE>0</MAP_TYPE>
+ <PUSCH_START_SYMBOL>3</PUSCH_START_SYMBOL>
+ <PUSCH_LENGTH_SYMBOL>11</PUSCH_LENGTH_SYMBOL>
+ </PUSCH_TIME_DOM_RSRC_ALLOC>
+ <PUSCH_TIME_DOM_RSRC_ALLOC>
+ <K2>5</K2>
+ <MAP_TYPE>0</MAP_TYPE>
+ <PUSCH_START_SYMBOL>3</PUSCH_START_SYMBOL>
+ <PUSCH_LENGTH_SYMBOL>11</PUSCH_LENGTH_SYMBOL>
+ </PUSCH_TIME_DOM_RSRC_ALLOC>
+ </PUSCH_TIME_DOM_RSRC_ALLOC_LIST>
+ </PUSCH_CFG_COMMON>
+ <PUCCH_CFG_COMMON>
+ <PRESENT>2</PRESENT>
+ <PUCCH_RSRC_COMMON>0</PUCCH_RSRC_COMMON>
+ <GRP_HOP>0</GRP_HOP>
+ <PUCCH_P0_NOMINAL>-74</PUCCH_P0_NOMINAL>
+ </PUCCH_CFG_COMMON>
+ </UL_CFG_COMMON>
+ <TDD_UL_DL_CFG_COMMON>
+ <REF_SCS>1</REF_SCS>
+ <TX_PRD>6</TX_PRD>
+ <NUM_DL_SLOTS>7</NUM_DL_SLOTS>
+ <NUM_DL_SYMBOLS>12</NUM_DL_SYMBOLS>
+ <NUM_UL_SLOTS>2</NUM_UL_SLOTS>
+ <NUM_UL_SYMBOLS>1</NUM_UL_SYMBOLS>
+ </TDD_UL_DL_CFG_COMMON>
+ </SRV_CELL_CFG_COM_SIB>
+ </SIB1_PARAMS>
+ <F1_DU_SRVD_CELL_INFO>
+ <F1_DU_CELL_INFO>
+ <F1_CELL_INFO>
+ <NR_CGI>
+ <CELL_ID>1</CELL_ID>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ </NR_CGI>
+ <NR_PCI>1</NR_PCI>
+ <F1_SRVD_PLMN>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ <EXT_PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </EXT_PLMN>
+ <F1_SLICE_SUPP_LST>
+ <NUM_SUPPORT_SLICE>2</NUM_SUPPORT_SLICE>
+ <SNSSAI_LIST>
+ <SNSSAI>
+ <SST>1</SST>
+ <SD_SIZE>
+ <SD>2</SD>
+ <SD>3</SD>
+ <SD>4</SD>
+ </SD_SIZE>
+ </SNSSAI>
+ <SNSSAI>
+ <SST>5</SST>
+ <SD_SIZE>
+ <SD>6</SD>
+ <SD>7</SD>
+ <SD>8</SD>
+ </SD_SIZE>
+ </SNSSAI>
+ </SNSSAI_LIST>
+ </F1_SLICE_SUPP_LST>
+ </F1_SRVD_PLMN>
+ </F1_CELL_INFO>
+ <TAC>1</TAC>
+ <EPS_TAC>1</EPS_TAC>
+ <NR_MODE_INFO>
+ <NR_MODE>TDD</NR_MODE>
+ <F1_NR_FDD_INFO>
+ <F1_NR_FREQ_INFO_UL>
+ <NR_ARFCN>390000</NR_ARFCN>
+ <F1_SUL_INFO>
+ <SUL_ARFCN>100</SUL_ARFCN>
+ <F1_TX_BW>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>14</F1_NRB>
+ </F1_TX_BW>
+ </F1_SUL_INFO>
+ <MAX_NRCELL_BANDS>2</MAX_NRCELL_BANDS>
+ <F1_FREQ_BAND_LIST>
+ <F1_FREQ_BAND>
+ <NR_FREQ_BAND>1</NR_FREQ_BAND>
+ <SUL_BAND_LIST>
+ <SUL_BAND>2</SUL_BAND>
+ </SUL_BAND_LIST>
+ </F1_FREQ_BAND>
+ </F1_FREQ_BAND_LIST>
+ </F1_NR_FREQ_INFO_UL>
+ <F1_NR_FREQ_INFO_DL>
+ <NR_ARFCN>428000</NR_ARFCN>
+ <F1_SUL_INFO>
+ <SUL_ARFCN>100</SUL_ARFCN>
+ <F1_TX_BW>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>14</F1_NRB>
+ </F1_TX_BW>
+ </F1_SUL_INFO>
+ <MAX_NRCELL_BANDS>2</MAX_NRCELL_BANDS>
+ <F1_FREQ_BAND_LIST>
+ <F1_FREQ_BAND>
+ <NR_FREQ_BAND>1</NR_FREQ_BAND>
+ <SUL_BAND_LIST>
+ <SUL_BAND>2</SUL_BAND>
+ </SUL_BAND_LIST>
+ </F1_FREQ_BAND>
+ </F1_FREQ_BAND_LIST>
+ </F1_NR_FREQ_INFO_DL>
+ <F1_TX_BW_UL>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>14</F1_NRB>
+ </F1_TX_BW_UL>
+ <F1_TX_BW_DL>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>14</F1_NRB>
+ </F1_TX_BW_DL>
+ </F1_NR_FDD_INFO>
+ <F1_NR_TDD_INFO>
+ <F1_NR_FREQ_INFO>
+ <NR_ARFCN>623400</NR_ARFCN>
+ <F1_SUL_INFO>
+ <SUL_ARFCN>100</SUL_ARFCN>
+ <F1_TX_BW>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>28</F1_NRB>
+ </F1_TX_BW>
+ </F1_SUL_INFO>
+ <MAX_NRCELL_BANDS>2</MAX_NRCELL_BANDS>
+ <F1_FREQ_BAND_LIST>
+ <F1_FREQ_BAND>
+ <NR_FREQ_BAND>78</NR_FREQ_BAND>
+ <SUL_BAND_LIST>
+ <SUL_BAND>2</SUL_BAND>
+ </SUL_BAND_LIST>
+ </F1_FREQ_BAND>
+ </F1_FREQ_BAND_LIST>
+ </F1_NR_FREQ_INFO>
+ <F1_TX_BW>
+ <F1_NR_SCS>1</F1_NR_SCS>
+ <F1_NRB>28</F1_NRB>
+ </F1_TX_BW>
+ </F1_NR_TDD_INFO>
+ </NR_MODE_INFO>
+ <TIME_CFG>4</TIME_CFG>
+ <F1_CELL_DIR>2</F1_CELL_DIR>
+ <F1_CELL_TYPE>1</F1_CELL_TYPE>
+ <F1_BRDCST_PLMN_INFO>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ <EXT_PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </EXT_PLMN>
+ <TAC>1</TAC>
+ <NR_CELL_ID>1</NR_CELL_ID>
+ <NR_RANAC>150</NR_RANAC>
+ </F1_BRDCST_PLMN_INFO>
+ </F1_DU_CELL_INFO>
+ </F1_DU_SRVD_CELL_INFO>
+ <MIB_PARAMS>
+ <SYS_FRAME_NUM>0</SYS_FRAME_NUM>
+ <SUB_CARR_SPACE>0</SUB_CARR_SPACE>
+ <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
+ <DMRS_TYPEA_POSITION>0</DMRS_TYPEA_POSITION>
+ <CORESET_0_INDEX>0</CORESET_0_INDEX>
+ <SEARCHSPACE_0_INDEX>0</SEARCHSPACE_0_INDEX>
+ <CELL_BARRED>1</CELL_BARRED>
+ <INTRA_FREQ_RESELECT>1</INTRA_FREQ_RESELECT>
+ </MIB_PARAMS>
+ <MAC_CELL_CFG>
+ <CELL_ID>1</CELL_ID>
+ <CARRIER_CFG>
+ <DL_BW>100</DL_BW>
+ <NR_DL_ARFCN>623400</NR_DL_ARFCN>
+ <UL_BW>100</UL_BW>
+ <NR_UL_ARFCN>623400</NR_UL_ARFCN>
+ <NUM_TX_ANT>2</NUM_TX_ANT>
+ <NUM_RX_ANT>2</NUM_RX_ANT>
+ </CARRIER_CFG>
+ <CELL_CFG>
+ <MAC_OP_STATE>0</MAC_OP_STATE><!--OP_DISABLED-->
+ <MAC_ADMIN_STATE>1</MAC_ADMIN_STATE><!--ADMIN_UNLOCKED-->
+ <MAC_CELL_STATE>1</MAC_CELL_STATE><!--CELL_INACTIVE-->
+ <PLMN_INFO>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ <F1_SLICE_SUPP_LST>
+ <NUM_SUPPORT_SLICE>2</NUM_SUPPORT_SLICE>
+ <SNSSAI_LIST>
+ <SNSSAI>
+ <SST>1</SST>
+ <SD_SIZE>
+ <SD>2</SD>
+ <SD>3</SD>
+ <SD>4</SD>
+ </SD_SIZE>
+ </SNSSAI>
+ <SNSSAI>
+ <SST>5</SST>
+ <SD_SIZE>
+ <SD>6</SD>
+ <SD>7</SD>
+ <SD>8</SD>
+ </SD_SIZE>
+ </SNSSAI>
+ </SNSSAI_LIST>
+ </F1_SLICE_SUPP_LST>
+ </PLMN_INFO>
+ <NR_PCI>1</NR_PCI>
+ <TAC>1</TAC>
+ <SSB_FREQUENCY>3000000</SSB_FREQUENCY>
+ <NR_SCS>1</NR_SCS>
+ <DUPLEX_MODE>1</DUPLEX_MODE>
+ <SIB1_CELL_CFG>
+ <SCH_PAGE_CFG>
+ <NUM_PO>1</NUM_PO>
+ <PO_PRESENT>TRUE</PO_PRESENT>
+ <PAGING_OCC>44</PAGING_OCC>
+ </SCH_PAGE_CFG>
+ <PDCCH_CONFIG_SIB1>
+ <CORESET_ZERO_INDEX>0</CORESET_ZERO_INDEX>
+ <SEARCH_SPACE_ZERO_INDEX>0</SEARCH_SPACE_ZERO_INDEX>
+ </PDCCH_CONFIG_SIB1>
+ </SIB1_CELL_CFG>
+ <BWP_DL_CFG>
+ <BWP_PARAMS>
+ <FIRST_PRB>0</FIRST_PRB>
+ <NUM_PRB>273</NUM_PRB>
+ <NR_SCS>1</NR_SCS>
+ <NORMAL_CYCLIC_PREFIX>0</NORMAL_CYCLIC_PREFIX>
+ </BWP_PARAMS>
+ <PDCCH_CFG_COMMON>
+ <SEARCH_SPACE_CFG>
+ <SEARCHSPACE_1_INDEX>1</SEARCHSPACE_1_INDEX>
+ <CORESET_0_INDEX>0</CORESET_0_INDEX>
+ <SS_MONITORING_SLOT_SL1>0</SS_MONITORING_SLOT_SL1>
+ <DURATION>0</DURATION>
+ <SS_MONITORING_SYMBOL>8192</SS_MONITORING_SYMBOL>
+ <CANDIDATE_INFO>
+ <AGG_LEVEL1>8</AGG_LEVEL1>
+ <AGG_LEVEL2>4</AGG_LEVEL2>
+ <AGG_LEVEL4>2</AGG_LEVEL4>
+ <AGG_LEVEL8>1</AGG_LEVEL8>
+ <AGG_LEVEL16>0</AGG_LEVEL16>
+ </CANDIDATE_INFO>
+ </SEARCH_SPACE_CFG>
+ <RA_SEARCH_SPACE_INDEX>1</RA_SEARCH_SPACE_INDEX>
+ </PDCCH_CFG_COMMON>
+ <PDSCH_CFG_COMMON>
+ <NUM_TIME_DOM_RSRC_ALLOC>2</NUM_TIME_DOM_RSRC_ALLOC>
+ <PDSCH_COMM_TIME_ALLOC_LIST>
+ <PDSCH_COMM_TIME_ALLOC>
+ <PDSCH_K0_CFG>0</PDSCH_K0_CFG>
+ <PDSCH_MAPPING_TYPE>0</PDSCH_MAPPING_TYPE>
+ <PDSCH_START_SYMBOL>3</PDSCH_START_SYMBOL>
+ <PDSCH_LENGTH_SYMBOL>11</PDSCH_LENGTH_SYMBOL>
+ </PDSCH_COMM_TIME_ALLOC>
+ <PDSCH_COMM_TIME_ALLOC>
+ <PDSCH_K0_CFG>1</PDSCH_K0_CFG>
+ <PDSCH_MAPPING_TYPE>0</PDSCH_MAPPING_TYPE>
+ <PDSCH_START_SYMBOL>3</PDSCH_START_SYMBOL>
+ <PDSCH_LENGTH_SYMBOL>11</PDSCH_LENGTH_SYMBOL>
+ </PDSCH_COMM_TIME_ALLOC>
+ </PDSCH_COMM_TIME_ALLOC_LIST>
+ </PDSCH_CFG_COMMON>
+ </BWP_DL_CFG>
+ <BWP_UL_CFG>
+ <BWP_PARAMS>
+ <FIRST_PRB>0</FIRST_PRB>
+ <NUM_PRB>273</NUM_PRB>
+ <NR_SCS>1</NR_SCS>
+ <NORMAL_CYCLIC_PREFIX>0</NORMAL_CYCLIC_PREFIX>
+ </BWP_PARAMS>
+ <PUCCH_CFG_COMMON>
+ <PUCCH_RSRC_COMMON>0</PUCCH_RSRC_COMMON>
+ <PUCCH_GROUP_HOPPING>0</PUCCH_GROUP_HOPPING>
+ </PUCCH_CFG_COMMON>
+ <PUSCH_CFG_COMMON>
+ <NUM_TIME_DOM_RSRC_ALLOC>2</NUM_TIME_DOM_RSRC_ALLOC>
+ <PUSCH_COMM_TIME_ALLOC_LIST>
+ <PUSCH_COMM_TIME_ALLOC>
+ <PUSCH_K2_CFG>4</PUSCH_K2_CFG>
+ <PUSCH_MAPPING_TYPE>0</PUSCH_MAPPING_TYPE>
+ <PUSCH_START_SYMBOL>3</PUSCH_START_SYMBOL>
+ <PUSCH_LENGTH_SYMBOL>11</PUSCH_LENGTH_SYMBOL>
+ </PUSCH_COMM_TIME_ALLOC>
+ <PUSCH_COMM_TIME_ALLOC>
+ <PUSCH_K2_CFG>5</PUSCH_K2_CFG>
+ <PUSCH_MAPPING_TYPE>0</PUSCH_MAPPING_TYPE>
+ <PUSCH_START_SYMBOL>3</PUSCH_START_SYMBOL>
+ <PUSCH_LENGTH_SYMBOL>11</PUSCH_LENGTH_SYMBOL>
+ </PUSCH_COMM_TIME_ALLOC>
+ </PUSCH_COMM_TIME_ALLOC_LIST>
+ </PUSCH_CFG_COMMON>
+ </BWP_UL_CFG>
+ </CELL_CFG>
+ <SSB_CFG>
+ <SSB_PBSC_PWR>0</SSB_PBSC_PWR>
+ <SCS_CMN>0</SCS_CMN> <!--SCS_15-->
+ <SSB_OFFSET_PT_A>24</SSB_OFFSET_PT_A>
+ <SSB_PERIOD>2</SSB_PERIOD>
+ <SSB_SC_OFFSET>0</SSB_SC_OFFSET>
+ <SSB_MASK_LIST>
+ <SSB_MASK>1</SSB_MASK>
+ </SSB_MASK_LIST>
+ <BEAM_LIST>
+ <BEAM_ID>0</BEAM_ID>
+ </BEAM_LIST>
+ <BETA_PSS>0</BETA_PSS>
+ <BCH_PAYLOAD_FLAG>1</BCH_PAYLOAD_FLAG>
+ <DMRS_TYPE_A_POS>2</DMRS_TYPE_A_POS>
+ </SSB_CFG>
+ <CSIRS_CFG>
+ <CSIRS_FREQ>0</CSIRS_FREQ>
+ <CSIRS_PORTS>0</CSIRS_PORTS>
+ <CSIRS_OFDM_PORT>0</CSIRS_OFDM_PORT>
+ <CSIRS_OFDM_PORT_2>0</CSIRS_OFDM_PORT_2>
+ <CSIRS_DM_TYPE>0</CSIRS_DM_TYPE>
+ <CSIRS_DENSITY>0</CSIRS_DENSITY>
+ <CSIRS_DENSITY_DOT_5>0</CSIRS_DENSITY_DOT_5>
+ <POWER_CONTROL_OFFSET>0</POWER_CONTROL_OFFSET>
+ <POWER_CONTROL_OFFSET_SS>0</POWER_CONTROL_OFFSET_SS>
+ <PERIODICITY_OFFSET>0</PERIODICITY_OFFSET>
+ </CSIRS_CFG>
+ <PRACH_CFG>
+ <PRACH_SEQ_LEN>1</PRACH_SEQ_LEN>
+ <NR_SCS>30</NR_SCS>
+ <PRACH_CONFIG_IDX>88</PRACH_CONFIG_IDX>
+ <NUM_PRACH_FDM>1</NUM_PRACH_FDM>
+ <FDM_LIST>
+ <FDM_INFO>
+ <ROOT_SEQ_IDX>0</ROOT_SEQ_IDX>
+ <NUM_ROOT_SEQ>1</NUM_ROOT_SEQ>
+ <K1>0</K1>
+ <ZERO_CORR_ZONE_CFG>4</ZERO_CORR_ZONE_CFG>
+ </FDM_INFO>
+ </FDM_LIST>
+ <PRACH_RESTRICTED_SET_CFG>0</PRACH_RESTRICTED_SET_CFG>
+ <SSB_PER_RACH>1</SSB_PER_RACH>
+ <NUM_RA_PREAMBLE>63</NUM_RA_PREAMBLE>
+ <CB_PREAMBLE_PER_SSB>8</CB_PREAMBLE_PER_SSB>
+ <MAX_NUM_RB>273</MAX_NUM_RB>
+ <PRACH_MAX_PRB>24</PRACH_MAX_PRB>
+ <RSRP_THRESHOLD_SSB>31</RSRP_THRESHOLD_SSB>
+ <RA_RSP_WINDOW>10</RA_RSP_WINDOW>
+ </PRACH_CFG>
+ <TDD_CFG>
+ <TDD_PERIODICITY>6</TDD_PERIODICITY>
+ <NUM_DL_SLOTS>7</NUM_DL_SLOTS>
+ <NUM_DL_SYMBOLS>12</NUM_DL_SYMBOLS>
+ <NUM_UL_SLOTS>2</NUM_UL_SLOTS>
+ <NUM_UL_SYMBOLS>1</NUM_UL_SYMBOLS>
+ </TDD_CFG>
+ <PRE_CODE_CFG>
+ <NUM_LAYERS>1</NUM_LAYERS>
+ <NUM_ANT_PORTS>0</NUM_ANT_PORTS>
+ </PRE_CODE_CFG>
+ <BEAM_FORM_CFG>
+ <NUM_OF_BEAMS>0</NUM_OF_BEAMS>
+ <NUM_TX_RUS>0</NUM_TX_RUS>
+ <BEAM_IDX>0</BEAM_IDX>
+ <BEAM_TYPE>0</BEAM_TYPE>
+ <BEAM_AZIMUTH>0</BEAM_AZIMUTH>
+ <BEAM_TILT>0</BEAM_TILT>
+ <BEAM_HORIZ_WIDTH>0</BEAM_HORIZ_WIDTH>
+ <BEAM_VERT_WIDTH>0</BEAM_VERT_WIDTH>
+ <COVER_SHAPE>0</COVER_SHAPE>
+ <DIGI_TILT>0</DIGI_TILT>
+ <DIGI_AZIMUTH>0</DIGI_AZIMUTH>
+ </BEAM_FORM_CFG>
+ </MAC_CELL_CFG>
+ <SLICE_CFG>
+ <NUM_RRM_POLICY>1</NUM_RRM_POLICY>
+ <MAC_SLICE_RRM_POLICY>
+ <RESOURCE_TYPE>0</RESOURCE_TYPE>
+ <NUM_RRM_POLICY_MEMBER>1</NUM_RRM_POLICY_MEMBER>
+ <RRM_POLICY_MEMBER_LIST>
+ <PLMN>
+ <MCC>
+ <PLMN_MCC0>3</PLMN_MCC0>
+ <PLMN_MCC1>1</PLMN_MCC1>
+ <PLMN_MCC2>1</PLMN_MCC2>
+ </MCC>
+ <MNC>
+ <PLMN_MNC0>4</PLMN_MNC0>
+ <PLMN_MNC1>8</PLMN_MNC1>
+ <PLMN_MNC2>0</PLMN_MNC2>
+ </MNC>
+ </PLMN>
+ <SNSSAI>
+ <SST>1</SST>
+ <SD_SIZE>
+ <SD>2</SD>
+ <SD>3</SD>
+ <SD>4</SD>
+ </SD_SIZE>
+ </SNSSAI>
+ </RRM_POLICY_MEMBER_LIST>
+ <RRM_POLICY_RATIO>
+ <MAX_RATIO>90</MAX_RATIO>
+ <MIN_RATIO>30</MIN_RATIO>
+ <DEDICATED_RATIO>10</DEDICATED_RATIO>
+ </RRM_POLICY_RATIO>
+ </MAC_SLICE_RRM_POLICY>
+ </SLICE_CFG>
+ <DU_TIMER_INFO>
+ <TIMER_TQ_CP>
+ <TIMER_LEN>2</TIMER_LEN>
+ </TIMER_TQ_CP>
+ <TIMER_RESOLUTION>1</TIMER_RESOLUTION>
+ </DU_TIMER_INFO>
+ <E2AP_CFG>
+ <E2_NODE_ID>1</E2_NODE_ID>
+ <NUM_OF_TNL_ASSOC>1</NUM_OF_TNL_ASSOC>
+ <TNL_ASSOC_LIST>
+ <TNL_ASSOC>
+ <LOCAL_IP>192.168.130.81</LOCAL_IP>
+ <LOCAL_PORT>36421</LOCAL_PORT>
+ <DESTINATION_IP>192.168.130.80</DESTINATION_IP>
+ <DESTINATION_PORT>36421</DESTINATION_PORT>
+ <ASSOC_USAGE>2</ASSOC_USAGE>
+ </TNL_ASSOC>
+ </TNL_ASSOC_LIST>
+ <NUM_OF_RAN_FUNCTION>1</NUM_OF_RAN_FUNCTION>
+ <RAN_FUNCTION_LIST>
+ <RAN_FUNCTION>
+ <ID>1</ID>
+ <RAN_FUNCTION_NAME>
+ <SHORT_NAME>ORAN-E2SM-KPM</SHORT_NAME>
+ <SEVICE_MODEL_OID>1.3.6.1.4.1.53148.1.2.2.2</SEVICE_MODEL_OID>
+ <DESCRIPTION>KPM Monitor</DESCRIPTION>
+ </RAN_FUNCTION_NAME>
+ <REVISION_COUNTER>0</REVISION_COUNTER>
+ <NUM_OF_EVENT_TRIGGER_STYLE_SUPPORTED>1</NUM_OF_EVENT_TRIGGER_STYLE_SUPPORTED>
+ <EVENT_TRIGGERED_STYLE_LIST>
+ <EVENT_TRIGGERED_STYLE>
+ <STYLE_TYPE>1</STYLE_TYPE>
+ <NAME>Periodic Report</NAME>
+ <FORMAT_TYPE>1</FORMAT_TYPE>
+ </EVENT_TRIGGERED_STYLE>
+ </EVENT_TRIGGERED_STYLE_LIST>
+ <NUM_OF_REPORT_STYLE_SUPPORTED>1</NUM_OF_REPORT_STYLE_SUPPORTED>
+ <REPORT_STYLE_SUPPORTED_LIST>
+ <REPORT_STYLE>
+ <RIC_STYLE>
+ <STYLE_TYPE>1</STYLE_TYPE>
+ <NAME>E2 Node Measurement</NAME>
+ <FORMAT_TYPE>1</FORMAT_TYPE>
+ </RIC_STYLE>
+ <MEASUREMENT_INFO_LIST>
+ <MEASUREMENT_INFO>
+ <ID>1</ID>
+ <NAME>RRU.PrbTotDl</NAME>
+ </MEASUREMENT_INFO>
+ <MEASUREMENT_INFO>
+ <ID>2</ID>
+ <NAME>RRU.PrbTotUl</NAME>
+ </MEASUREMENT_INFO>
+ </MEASUREMENT_INFO_LIST>
+ </REPORT_STYLE>
+ </REPORT_STYLE_SUPPORTED_LIST>
+ <RIC_INDICATION_HEADER_FORMAT>1</RIC_INDICATION_HEADER_FORMAT>
+ <RIC_INDICATION_MESSAGE_FORMAT>1</RIC_INDICATION_MESSAGE_FORMAT>
+ </RAN_FUNCTION>
+ </RAN_FUNCTION_LIST>
+ </E2AP_CFG>
+ <GLOBAL_CFG>
+ <RADIO_FRAME_DURATION>10</RADIO_FRAME_DURATION>
+ <PHY_DELTA_DL>2</PHY_DELTA_DL>
+ <PHY_DELTA_UL>0</PHY_DELTA_UL>
+ <ODU_UE_THROUGHPUT_PRINT_TIME_INTERVAL>5</ODU_UE_THROUGHPUT_PRINT_TIME_INTERVAL>
+ <ODU_SNSSAI_THROUGHPUT_PRINT_TIME_INTERVAL>60000</ODU_SNSSAI_THROUGHPUT_PRINT_TIME_INTERVAL>
+<!--
+ <MAX_NUM_CELL>2</MAX_NUM_CELL>
+ <MAX_NUM_MU>4</MAX_NUM_MU>
+ <MAX_NUM_UE>3</MAX_NUM_UE>
+ <MAX_NUM_UE_PER_TTI>1</MAX_NUM_UE_PER_TTI>
+ <MAX_DRB_LCID>32</MAX_DRB_LCID>
+ <MAX_NUM_SRB>3</MAX_NUM_SRB>
+ <MAX_NUM_DRB>29</MAX_NUM_DRB>
+ <MAX_NUM_SSB>64</MAX_NUM_SSB>
+ <MAX_NUM_HARQ_PROC>16</MAX_NUM_HARQ_PROC>
+ <MAX_NUM_TB_PER_UE>2</MAX_NUM_TB_PER_UE>
+ <ODU_START_CRNTI>100</ODU_START_CRNTI>
+ <ODU_END_CRNTI>500</ODU_END_CRNTI>
+ <BANDWIDTH>20</BANDWIDTH>
+ <MAX_NUM_RB>106</MAX_NUM_RB>
+ <MAX_SLOTS>10</MAX_SLOTS>
+ <MAX_SFN>1024</MAX_SFN>
+ <MAX_SYMB_PER_SLOT>14</MAX_SYMB_PER_SLOT>
+ <MAX_NUM_STATS_GRP>5</MAX_NUM_STATS_GRP>
+ <MAX_NUM_STATS>10</MAX_NUM_STATS>
+ <MAX_TDD_PERIODICITY_SLOTS>100</MAX_TDD_PERIODICITY_SLOTS>
+-->
+ </GLOBAL_CFG>
+</DU_CFG_PARAMS>
+
+
return ROK;
}
-#ifdef NR_TDD
/*******************************************************************
*
* @brief Fill NR TDD Info
}
return ROK;
}
-#endif
/*******************************************************************
*
strcpy((char*)modeCfg, (char*)xmlNodeListGetString(doc, cur->xmlChildrenNode, 1));
}
-#ifndef NR_TDD
- if ((!xmlStrcmp(cur->name, (const xmlChar *)"F1_NR_FDD_INFO")) && (cur->ns == ns))
+ if(strcmp(modeCfg, "FDD") == 0)
{
- if(strcmp(modeCfg, "FDD") == 0)
+ if ((!xmlStrcmp(cur->name, (const xmlChar *)"F1_NR_FDD_INFO")) && (cur->ns == ns))
{
if(parseF1NrFddInfo(doc, ns, cur, &nrModeInfo->mode.fdd) != ROK)
{
}
}
}
-#else
- if ((!xmlStrcmp(cur->name, (const xmlChar *)"F1_NR_TDD_INFO")) && (cur->ns == ns))
+ else
{
- if(strcmp(modeCfg, "TDD") == 0)
+ if ((!xmlStrcmp(cur->name, (const xmlChar *)"F1_NR_TDD_INFO")) && (cur->ns == ns))
{
if(parseF1NrTddInfo(doc, ns, cur, &nrModeInfo->mode.tdd) != ROK)
{
}
}
-#endif
cur = cur -> next;
}
return ROK;
if ((!xmlStrcmp(cur->name, (const xmlChar *)"NR_DL_ARFCN")) && (cur->ns == ns))
{
- carrierCfg->arfcnDL = convertArfcnToFreqKhz(atoi((char *)xmlNodeListGetString(doc, cur->xmlChildrenNode, 1)));
+ carrierCfg->arfcnDL = atoi((char *)xmlNodeListGetString(doc, cur->xmlChildrenNode, 1));
}
if ((!xmlStrcmp(cur->name, (const xmlChar *)"UL_BW")) && (cur->ns == ns))
if ((!xmlStrcmp(cur->name, (const xmlChar *)"NR_UL_ARFCN")) && (cur->ns == ns))
{
- carrierCfg->arfcnUL = convertArfcnToFreqKhz(atoi((char *)xmlNodeListGetString(doc, cur->xmlChildrenNode, 1)));
+ carrierCfg->arfcnUL = atoi((char *)xmlNodeListGetString(doc, cur->xmlChildrenNode, 1));
}
#endif
return ROK;
}
+/*******************************************************************
+ *
+ * @brief Free the memory allocate for slice supported list
+ *
+ * @details
+ *
+ * Function : parseDuCfgParams
+ *
+ * Functionality: Free the memory allocate for slice supported list
+ *
+ * @return void
+ *
+ * ****************************************************************/
+void freeSliceSuppLst(SupportedSliceList *sliceSuppLst)
+{
+ uint8_t sliceIdx=0;
+
+ if(sliceSuppLst->numSupportedSlices&&sliceSuppLst->snssai)
+ {
+ for(sliceIdx=0;sliceIdx<sliceSuppLst->numSupportedSlices;sliceIdx++)
+ {
+ if(sliceSuppLst->snssai)
+ {
+ if(sliceSuppLst->snssai[sliceIdx])
+ {
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL, sliceSuppLst->snssai[sliceIdx], sizeof(Snssai));
+ }
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL, \
+ sliceSuppLst->snssai, (sliceSuppLst->numSupportedSlices) * sizeof(Snssai*));
+ }
+ }
+ }
+}
+
+/*******************************************************************
+ *
+ * @brief Free the memory allocate in parseDuCfgParams
+ *
+ * @details
+ *
+ * Function : parseDuCfgParams
+ *
+ * Functionality: Free the memory allocate in parseDuCfgParams
+ *
+ * @return void
+ *
+ * ****************************************************************/
+void freeDuCfgParams()
+{
+ uint8_t ranFuncIdx=0,reportStyleIdx=0;
+ uint8_t policyIdx = 0,memIdx=0;
+ MacSliceRrmPolicy *rrmPolicy =NULLP;
+ MacSliceCfgReq *macSliceCfgReq=NULLP;
+ F1DuSysInfo *sysInfo;
+ CsiRsCfg *csiRsCfg;
+ RanFunction *ranFunction;
+ RicReportStyle *ricReportStyle;
+ CmLListCp *measurementInfoList;
+ CmLList *measInfoNode = NULLP;
+
+ if(duCfgParam.duName)
+ {
+ DU_FREE(duCfgParam.duName, strlen(duCfgParam.duName));
+ }
+
+ freeSliceSuppLst(&duCfgParam.macCellCfg.cellCfg.plmnInfoList[0].suppSliceList);
+ csiRsCfg=&duCfgParam.macCellCfg.csiRsCfg;
+ if(csiRsCfg->csiFreqDomainAlloc)
+ {
+ DU_FREE(csiRsCfg->csiFreqDomainAlloc, sizeof(uint8_t));
+ }
+ if(duCfgParam.macCellCfg.cellCfg.sib1Cfg.sib1Pdu)
+ {
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL, \
+ duCfgParam.macCellCfg.cellCfg.sib1Cfg.sib1Pdu, duCfgParam.macCellCfg.cellCfg.sib1Cfg.sib1PduLen);
+ }
+
+ if(duCb.e2apDb.numOfRanFunction)
+ {
+ for(ranFuncIdx=0;ranFuncIdx<duCb.e2apDb.numOfRanFunction;ranFuncIdx++)
+ {
+ ranFunction=&duCb.e2apDb.ranFunction[ranFuncIdx];
+ for(reportStyleIdx=0;reportStyleIdx<ranFunction->numOfReportStyleSupported;reportStyleIdx++)
+ {
+ ricReportStyle=&ranFunction->reportStyleList[reportStyleIdx];
+ measurementInfoList=&ricReportStyle->measurementInfoList;
+ CM_LLIST_FIRST_NODE(measurementInfoList, measInfoNode);
+ while(measInfoNode)
+ {
+ MeasurementInfoForAction *measurementInfoForAction;
+ measurementInfoForAction= (MeasurementInfoForAction*)measInfoNode->node;
+ cmLListDelFrm(measurementInfoList, measInfoNode);
+ DU_FREE(measurementInfoForAction, sizeof(MeasurementInfoForAction));
+ DU_FREE(measInfoNode, sizeof(CmLList));
+ CM_LLIST_FIRST_NODE(measurementInfoList, measInfoNode);
+ }
+ }
+ }
+ }
+
+ freeSliceSuppLst(&duCfgParam.srvdCellLst[0].duCellInfo.cellInfo.srvdPlmn[0].taiSliceSuppLst);
+ sysInfo=&duCfgParam.srvdCellLst[0].duSysInfo;
+ if(sysInfo->mibMsg)
+ {
+ DU_FREE(sysInfo->mibMsg, sysInfo->mibLen);
+ }
+ if(sysInfo->sib1Msg)
+ {
+ DU_FREE(sysInfo->sib1Msg, sysInfo->sib1Len);
+ }
+
+ macSliceCfgReq=&duCfgParam.tempSliceCfg;
+ if(macSliceCfgReq->listOfRrmPolicy)
+ {
+ for(policyIdx = 0; policyIdx < macSliceCfgReq->numOfRrmPolicy; policyIdx++)
+ {
+ if (macSliceCfgReq->listOfRrmPolicy[policyIdx])
+ {
+ rrmPolicy=macSliceCfgReq->listOfRrmPolicy[policyIdx];
+ if(rrmPolicy->rRMPolicyMemberList)
+ {
+ for(memIdx = 0; memIdx < rrmPolicy->numOfRrmPolicyMem; memIdx++)
+ {
+ if (rrmPolicy->rRMPolicyMemberList[memIdx])
+ {
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL,\
+ rrmPolicy->rRMPolicyMemberList[memIdx], sizeof(RrmPolicyMemberList));
+ }
+ }
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL,rrmPolicy->rRMPolicyMemberList,\
+ rrmPolicy->numOfRrmPolicyMem * sizeof(RrmPolicyMemberList*));
+ }
+
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL, \
+ macSliceCfgReq->listOfRrmPolicy[policyIdx], sizeof(MacSliceRrmPolicy));
+ }
+ }
+ DU_FREE_SHRABL_BUF(DU_APP_MEM_REGION, DU_POOL, \
+ macSliceCfgReq->listOfRrmPolicy, macSliceCfgReq->numOfRrmPolicy * sizeof(MacSliceRrmPolicy*));
+ }
+}
+
+
/*******************************************************************
*
* @brief Fill DU Config Parmeters
* ****************************************************************/
uint8_t parseDuCfgParams(xmlDocPtr doc, xmlNsPtr ns, xmlNodePtr cur)
{
+ uint8_t ret=ROK;
char *tempDuName = "";
char *duIpV4Addr;
char *cuIpV4Addr;
#ifdef THREAD_AFFINITY
if(parseThreadAffinity(doc, ns, cur, &duCfgParam.threadInfo) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
#endif
}
if(!duCfgParam.duName)
{
DU_LOG("\nERROR --> DU_APP: %s: Memory allocation failed at line %d", __func__, __LINE__);
- return RFAILED;
+ ret = RFAILED;
+ break;
}
strcpy((char*)duCfgParam.duName, tempDuName);
}
{
if(parseSctpParams(doc, ns, cur, &duCfgParam.sctpParams) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
duCfgParam.sctpParams.duIpAddr.ipV4Pres = true;
duCfgParam.sctpParams.duIpAddr.ipV4Addr = duIp;
{
if(parseEgtpParams(doc, ns, cur, &duCfgParam.egtpParams) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
duCfgParam.egtpParams.localIp.ipV4Addr = duIp;
duCfgParam.egtpParams.localIp.ipV4Pres = true;
{
if(parseMibParams(doc, ns, cur, &duCfgParam.mibParams) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
{
if(parseSib1Params(doc, ns, cur, &duCfgParam.sib1Params) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
{
if(parseF1DuServedCellInfo(doc, ns, cur, &duCfgParam.srvdCellLst[0]) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
{
if(parseMacCellCfg(doc, ns, cur, &duCfgParam.macCellCfg) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
{
if(parseMacSliceCfgReq(doc, ns, cur, &duCfgParam.tempSliceCfg) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
#endif
{
if(parseDuTimerParams(doc, ns, cur, &duCb.duTimersInfo) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
{
if(parseE2ConfigParams(doc, ns, cur, &duCb.e2apDb) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
else
{
{
if(parseGlobalConfigParams(doc, ns, cur) != ROK)
{
- return RFAILED;
+ ret = RFAILED;
+ break;
}
}
cur = cur -> next;
}
- return ROK;
+
+ if(ret != ROK)
+ {
+ freeDuCfgParams();
+ }
+ return ret;
}
/*******************************************************************
* ****************************************************************/
uint8_t duReadCfg()
{
- const char *filename = "../build/config/odu_config.xml";
+#ifdef NR_TDD
+ const char *filename = "../build/config/tdd_odu_config.xml";
+#else
+ const char *filename = "../build/config/fdd_odu_config.xml";
+#endif
xmlDocPtr doc = NULLP;
xmlNodePtr cur = NULLP;
xmlNsPtr ns = NULLP;
Code Review / o-du / l2.git / commitdiff