# macro for output file name and makefile name
#
-PLTFRM_FLAGS= -UMSPD -DODU #-DEGTP_TEST -DWLS_MEM
+PLTFRM_FLAGS= -UMSPD -DODU #-DFAPI -DEGTP_TEST -DWLS_MEM
ifeq ($(MODE),TDD)
PLTFRM_FLAGS += -DMODE=TDD
+++ /dev/null
-/******************************************************************************\r
-* Copyright 2017 Cisco Systems, Inc.\r
-* Copyright (c) 2019 Intel.\r
-*\r
-* Licensed under the Apache License, Version 2.0 (the "License");\r
-* you may not use this file except in compliance with the License.\r
-* You may obtain a copy of the License at\r
-*\r
-* http://www.apache.org/licenses/LICENSE-2.0\r
-*\r
-* Unless required by applicable law or agreed to in writing, software\r
-* distributed under the License is distributed on an "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-* See the License for the specific language governing permissions and\r
-* limitations under the License.\r
-*\r
-*******************************************************************************/\r
-// This file has been modified by Intel in order to support 5G FAPI:PHY API Specification\r
-// Document 222.10.01 dated June 2019\r
-// Changes made by luis.farias@intel.com\r
-/**\r
- * @file\r
- * This file consist of FAPI configuration APIs macros, structure typedefs and\r
- * prototypes.\r
- *\r
- **/\r
-\r
-#ifndef _FAPI_H_\r
-#define _FAPI_H_\r
-\r
-#include <stdint.h>\r
-\r
-#include "fapi_interface.h"\r
-//#include "fapi_vendor_common_defs.h"\r
-\r
-#define RELEASE_15 0x0001\r
-\r
-// Datatypes typedefs - end\r
-\r
-typedef enum {\r
- FAPI_SUCCESS = 0,\r
- FAPI_FAILURE\r
-} fapiStatus_t;\r
-// Updated per 5G FAPI\r
-\r
-\r
-\r
-// Updated per 5G FAPI \r
-typedef enum {\r
- FAPI_UL_TTI_REQ_PRACH_PDU_TYPE = 0,\r
- FAPI_UL_TTI_REQ_PUSCH_PDU_TYPE,\r
- FAPI_UL_TTI_REQ_PUCCH_PDU_TYPE,\r
- FAPI_UL_TTI_REQ_SRS_PDU_TYPE\r
-}fapiULTtiReqPduType_e;\r
-// Updated per 5G FAPI\r
-typedef enum {\r
- FAPI_UCI_IND_ON_PUSCH_PDU_TYPE = 0,\r
- FAPI_UCI_IND_ON_PUCCH_FMT_0_1_PDU_TYPE,\r
- FAPI_UCI_IND_ON_PUCCH_FMT_2_3_4_PDU_TYPE\r
-}fapiUciIndPdu_Type_e;\r
- \r
-// CRC\r
-enum {\r
- FAPI_CRC_CORRECT = 0,\r
- FAPI_CRC_ERROR = 1\r
-};\r
-\r
-//------------------------------------------------------------------------------\r
-// Fapi Infra Declarations\r
-//------------------------------------------------------------------------------\r
-// Release/Features support\r
-typedef enum {\r
- FAPI_NOT_SUPPORTED = 0,\r
- FAPI_SUPPORTED,\r
-} fapiSupport_t;\r
-\r
-// FAPI States\r
-/**\r
- * FAPI state is maintained per fapi instance. If FAPI messages are received in\r
- * wrong state an ERROR.indication message will be sent by FAPI.\r
- */\r
-typedef enum fapiStates\r
-{\r
- FAPI_STATE_IDLE = 0,\r
- FAPI_STATE_CONFIGURED,\r
- FAPI_STATE_RUNNING\r
-} fapiStates_t;\r
-\r
-// Information of optional and mandatory status for a TLV\r
-typedef enum {\r
- FAPI_IDLE_STATE_ONLY_OPTIONAL = 0,\r
- FAPI_IDLE_STATE_ONLY_MANDATORY,\r
- FAPI_IDLE_AND_CONFIGURED_STATES_OPTIONAL,\r
- FAPI_IDLE_STATE_MANDATORY_CONFIGURED_STATE_OPTIONAL,\r
- FAPI_IDLE_CONFIGURED_AND_RUNNING_STATES_OPTIONAL,\r
- FAPI_IDLE_STATE_MANDATORY_CONFIGURED_AND_RUNNING_STATES_OPTIONAL\r
-} fapiTlvStatus_t;\r
-\r
-// PARAMETERS INFORMATION\r
-\r
-#define FAPI_NORMAL_CYCLIC_PREFIX_MASK 0x01\r
-#define FAPI_EXTENDED_CYCLIC_PREFIX_MASK 0x02\r
-\r
-// In 5G FAPI FrameDuplexType as part of Cell Configuration\r
-typedef enum\r
-{\r
- TDD_DUPLEX = 0,\r
- FDD_DUPLEX\r
-} modes; //Defined now\r
-\r
-// Subcarrier spacing information\r
-#define FAPI_15KHZ_MASK 0x01\r
-#define FAPI_30KHZ_MASK 0x02\r
-#define FAPI_60KHZ_MASK 0x04\r
-#define FAPI_120KHZ_MASK 0x08\r
-\r
-// Bandwitdth information\r
-#define FAPI_5MHZ_BW_MASK 0x0001\r
-#define FAPI_10MHZ_BW_MASK 0x0002\r
-#define FAPI_15MHZ_BW_MASK 0x0004\r
-#define FAPI_20MHZ_BW_MASK 0x0010\r
-#define FAPI_40MHZ_BW_MASK 0x0020\r
-#define FAPI_50MHZ_BW_MASK 0x0040\r
-#define FAPI_60MHZ_BW_MASK 0x0080\r
-#define FAPI_70MHZ_BW_MASK 0x0100\r
-#define FAPI_80MHZ_BW_MASK 0x0200\r
-#define FAPI_90MHZ_BW_MASK 0x0400\r
-#define FAPI_100MHZ_BW_MASK 0x0800\r
-#define FAPI_200MHZ_BW_MASK 0x1000\r
-#define FAPI_400MHZ_BW_MASK 0x2000\r
-\r
-\r
-// PDCCH Information\r
-#define FAPI_CCE_MAPPING_INTERLEAVED_MASK 0x01\r
-#define FAPI_CCE_MAPPING_NONINTERLVD_MASK 0x02\r
-// Upper Bound for PDCCH Channels per Slot\r
-#define FAPI_MAX_PDCCHS_PER_SLOT_MASK 0xff\r
-\r
-// PUCCH Information\r
-#define FAPI_FORMAT_0_MASK 0x01\r
-#define FAPI_FORMAT_1_MASK 0x02\r
-#define FAPI_FORMAT_2_MASK 0x04\r
-#define FAPI_FORMAT_3_MASK 0x08\r
-#define FAPI_FORMAT_4_MASK 0x10\r
-// Upper Bound for PUCCH Channels per Slot\r
-#define FAPI_MAX_PUCCHS_PER_SLOT_MASK 0xff\r
-\r
-// PDSCH Information\r
-#define FAPI_PDSCH_MAPPING_TYPE_A_MASK 0x01\r
-#define FAPI_PDSCH_MAPPING_TYPE_B_MASK 0x02\r
-#define FAPI_PDSCH_ALLOC_TYPE_0_MASK 0x01\r
-#define FAPI_PDSCH_ALLOC_TYPE_1_MASK 0x02\r
-#define FAPI_PDSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01\r
-#define FAPI_PDSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02\r
-#define FAPI_PDSCH_DMRS_CONFIG_TYPE_1_MASK 0x01\r
-#define FAPI_PDSCH_DMRS_CONFIG_TYPE_2_MASK 0x02\r
-#define FAPI_PDSCH_DMRS_MAX_LENGTH_1 0\r
-#define FAPI_PDSCH_DMRS_MAX_LENGTH_2 1\r
-#define FAPI_DMRS_ADDITIONAL_POS_0_MASK 0x01\r
-#define FAPI_DMRS_ADDITIONAL_POS_1_MASK 0x02\r
-#define FAPI_DMRS_ADDITIONAL_POS_2_MASK 0x04\r
-#define FAPI_DMRS_ADDITIONAL_POS_3_MASK 0x08\r
-//Upper Limit for PDSCHS TBs per Slot\r
-#define FAPI_MAX_PDSCHS_TBS_PER_SLOT_MASK 0xff\r
-#define FAPI_MAX_NUMBERMIMO_LAYERS_PDSCH 2\r
-\r
-typedef enum modulationOrder {\r
- FAPI_QPSK = 0,\r
- FAPI_16QAM,\r
- FAPI_64QAM,\r
- FAPI_256QAM\r
-} fapiModOrder_t;\r
-\r
-#define FAPI_MAX_MUMIMO_USERS_MASK 0xff\r
-\r
-\r
-// PUSCH Parameters\r
-\r
-#define FAPI_PUSCH_MAPPING_TYPE_A_MASK 0x01\r
-#define FAPI_PUSCH_MAPPING_TYPE_B_MASK 0x02\r
-#define FAPI_PUSCH_ALLOC_TYPE_0_MASK 0x01\r
-#define FAPI_PUSCH_ALLOC_TYPE_1_MASK 0x02\r
-#define FAPI_PUSCH_VRB_TO_PRB_MAP_NON_INTLV_MASK 0x01\r
-#define FAPI_PUSCH_VRB_TO_PRB_MAP_INTLVD_MASK 0x02\r
-#define FAPI_PUSCH_DMRS_CONFIG_TYPE_1_MASK 0x01\r
-#define FAPI_PUSCH_DMRS_CONFIG_TYPE_2_MASK 0x02\r
-#define FAPI_PUSCH_DMRS_MAX_LENGTH_1 0\r
-#define FAPI_PUSCH_DMRS_MAX_LENGTH_2 1\r
-// Upper limit for PUSCHMAXPTRSPORTS\r
-#define FAPI_PUSCH_MAX_PTRS_PORTS_UB 2\r
-//Upper Limit for PDSCHS TBs per Slot\r
-#define FAPI_MAX_PUSCHS_TBS_PER_SLOT_MASK 0xff\r
-\r
-typedef enum aggregationFactor\r
-{\r
- FAPI_PUSCH_AGG_FACTOR_1 = 0,\r
- FAPI_PUSCH_AGG_FACTOR_2,\r
- FAPI_PUSCH_AGG_FACTOR_4,\r
- FAPI_PUSCH_AGG_FACTOR_8\r
-} fapiPuschAggFactor_t;\r
-\r
-// PRACH Parameters\r
-#define FAPI_PRACH_LF_FORMAT_0_MASK 0x01\r
-#define FAPI_PRACH_LF_FORMAT_1_MASK 0x02\r
-#define FAPI_PRACH_LF_FORMAT_2_MASK 0x04\r
-#define FAPI_PRACH_LF_FORMAT_3_MASK 0x08\r
-\r
-#define FAPI_PRACH_SF_FORMAT_A1_MASK 0x01\r
-#define FAPI_PRACH_SF_FORMAT_A2_MASK 0x02\r
-#define FAPI_PRACH_SF_FORMAT_A3_MASK 0x04\r
-#define FAPI_PRACH_SF_FORMAT_B1_MASK 0x08\r
-#define FAPI_PRACH_SF_FORMAT_B2_MASK 0x10\r
-#define FAPI_PRACH_SF_FORMAT_B3_MASK 0x20\r
-#define FAPI_PRACH_SF_FORMAT_B4_MASK 0x40\r
-#define FAPI_PRACH_SF_FORMAT_C0_MASK 0x80\r
-#define FAPI_PRACH_SF_FORMAT_C2_MASK 0x100\r
-\r
-typedef enum {\r
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_1 = 0,\r
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_2,\r
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_4,\r
- FAPI_MAX_PRACH_FD_OCC_IN_A_SLOT_8\r
-} fapi_prachMaxFdOccasionsPerSlot_t; \r
-\r
-// Measurement Parameters\r
-#define FAPI_RSSI_REPORT_IN_DBM_MASK 0x01\r
-#define FAPI_RSSI_REPORT_IN_DBFS_MASK 0x02\r
-\r
-// CONFIGURATION INFORMATION\r
-// CARRIER CONFIGURATION\r
-// BANDWIDTH\r
-#define FAPI_BANDWIDTH_5_MHZ 5\r
-#define FAPI_BANDWIDTH_10_MHZ 10\r
-#define FAPI_BANDWIDTH_15_MHZ 15\r
-#define FAPI_BANDWIDTH_20_MHZ 20\r
-#define FAPI_BANDWIDTH_25_MHZ 25\r
-#define FAPI_BANDWIDTH_30_MHZ 30\r
-#define FAPI_BANDWIDTH_40_MHZ 40\r
-#define FAPI_BANDWIDTH_50_MHZ 50\r
-#define FAPI_BANDWIDTH_60_MHZ 60\r
-#define FAPI_BANDWIDTH_70_MHZ 70\r
-#define FAPI_BANDWIDTH_80_MHZ 80\r
-#define FAPI_BANDWIDTH_90_MHZ 90\r
-#define FAPI_BANDWIDTH_100_MHZ 100\r
-#define FAPI_BANDWIDTH_200_MHZ 200\r
-#define FAPI_BANDWIDTH_400_MHZ 400\r
-\r
-// Frequency needs to track 38.104 Section 5.2 and 38.211 Section 5.3.1\r
-// Lower Bound KHz\r
-#define FAPI_MIN_FREQUENCY_PT_A 450000\r
-// Upper Bound KHz\r
-#define FAPI_MAX_FREQUENCY_PT_A 52600000\r
-// dlk0, ulk0 per 38.211 Section 5.3.1\r
-// Upper Bound\r
-#define FAPI_K0_MAX 23699\r
-// dlGridSize, ulGridSize per 38.211 Section 4.4.2\r
-// Upper Bound\r
-#define FAPI_GRIDSIZE_MAX 275\r
-// Number of Transmit Antennas\r
-// Define upper mask based on variable type\r
-#define FAPI_NUM_ANT_MASK 0xffff\r
-\r
-// CELL CONFIGURATION\r
-// Physical Cell ID from 38.211 Section 7.4.2.1\r
-// Upper Bound\r
-#define FAPI_MAX_CELL_ID 1007\r
-\r
-// SSB CONFIGURATION\r
-// SSB POWER RANGE in dBm\r
-#define FAPI_SS_PBCH_LOWEST_POWER -60\r
-#define FAPI_SS_PBCH_MAX_POWER 50\r
-// BCH PAYLOAD for 5G the MAC always generates the BCH Payload\r
-#define FAPI_BCH_PAYLOAD_GEN_BY_MAC 0\r
-#define FAPI_BCH_PAYLOAD_WITH_PHY_GEN_TIMING 1\r
-#define FAPI_BCH_PAYLOAD_ENTIRELY_GEN_BY_PHY 2\r
-// ScsCommon\r
-#define FAPI_SCSCOMMON_MASK 0x03\r
-\r
-// PRACH CONFIGURATION\r
-#define FAPI_PRACH_LONG_SEQUENCE 0\r
-#define FAPI_PRACH_SHORT_SEQUENCE 1\r
-#define FAPI_PRACH_SUBC_SPACING_MAX 4\r
-// Restricted Set Configuration\r
-#define FAPI_PRACH_RESTRICTED_SET_UNRESTRICTED 0\r
-#define FAPI_PRACH_RESTRICTED_SET_TYPE_A 1\r
-#define FAPI_PRACH_RESTRICTED_SET_TYPE_B 2 \r
-// Root Sequence Index\r
-// Upper Bound\r
-#define FAPI_PRACH_ROOT_SEQ_INDEX_MAX 837 \r
-// k1\r
-// Upper Bound\r
-#define FAPI_K1_UPPER_BOUND 272\r
-// PRACH Zero Corr Configuration\r
-// Upper Bound\r
-#define FAPI_PRACHZEROCORRCONF_MASK 0x0f\r
-// Number of Unused Root Sequences Mask\r
-#define FAPI_UNUSEDROOTSEQUENCES_MASK 0x0f\r
-// SSBPERRACH\r
-typedef enum \r
-{\r
- FAPI_SSB_PER_RACH_1_OVER_8 = 0,\r
- FAPI_SSB_PER_RACH_1_OVER_4,\r
- FAPI_SSB_PER_RACH_1_OVER_2,\r
- FAPI_SSB_PER_RACH_1,\r
- FAPI_SSB_PER_RACH_2,\r
- FAPI_SSB_PER_RACH_4,\r
- FAPI_SSB_PER_RACH_8,\r
- FAPI_SSB_PER_RACH_16\r
-} fapiSsbPerRach_t; \r
-\r
-// SSB Table\r
-// Ssb Offset Point A max\r
-#define FAPI_SSB_OFFSET_POINTA_MAX 2199\r
-// betaPSS i.e. PSS EPRE to SSS EPRE in a SS/PBCH Block per 38.213 Section 4.1\r
-#define FAPI_BETAPSS_0_DB 0\r
-#define FAPI_BETAPSS_3_DB 1\r
-// SSB Period in ms\r
-#define FAPI_SSB_PERIOD_5_MS 0\r
-#define FAPI_SSB_PERIOD_10_MS 1\r
-#define FAPI_SSB_PERIOD_20_MS 2\r
-#define FAPI_SSB_PERIOD_40_MS 3\r
-#define FAPI_SSB_PERIOD_80_MS 4\r
-#define FAPI_SSB_PERIOD_160_MS 5\r
-\r
-// Ssb Subcarrier Offset per 38.211 Section 7.4.3.1\r
-// SsbSubcarrierOffset mask\r
-#define FAPI_SSB_SUBCARRIER_OFFSET_MASK 0x1f\r
-// MIB PAYLOAD MASK\r
-#define MIB_PAYLOAD_MASK 0xfff0\r
-// BEAM ID MASK\r
-#define FAPI_BEAM_ID_MASK 0x3f\r
-\r
-// TDD Table\r
-// TDD Period\r
-#define FAPI_TDD_PERIOD_0_P_5_MS 0\r
-#define FAPI_TDD_PERIOD_0_P_625_MS 1\r
-#define FAPI_TDD_PERIOD_1_MS 2\r
-#define FAPI_TDD_PERIOD_1_P_25_MS 3\r
-#define FAPI_TDD_PERIOD_2_MS 4\r
-#define FAPI_TDD_PERIOD_2_P_5_MS 5\r
-#define FAPI_TDD_PERIOD_5_MS 6\r
-#define FAPI_TDD_PERIOD_10_MS 7\r
-\r
-// Slot Configuration\r
-#define FAPI_DL_SLOT 0\r
-#define FAPI_UL_SLOT 1\r
-#define FAPI_GUARD_SLOT 2\r
-\r
-// Measurement configuration\r
-#define FAPI_NO_RSSI_REPORTING 0\r
-#define FAPI_RSSI_REPORTED_IN_DBM 1\r
-#define FAPI_RSSI_REPORTED_IN_DBFS 2\r
-\r
-// Error Indication\r
-#define FAPI_SFN_MASK 0x03ff\r
-\r
-// Status and Error Codes for either .response or ERROR.indication\r
-// Updated per 5g FAPI Table 3-31\r
-/*\r
-typedef enum {\r
- MSG_OK = 0,\r
- MSG_INVALID_STATE,\r
- MSG_INVALID_CONFIG,\r
- SFN_OUT_OF_SYNC,\r
- MSG_SLOT_ERR,\r
- MSG_BCH_MISSING,\r
- MSG_INVALID_SFN,\r
- MSG_UL_DCI_ERR, \r
- MSG_TX_ERR\r
- }fapiStatusAndErrorCodes_e;\r
-*/\r
- // Digital Beam Table (DBT) PDU\r
- // Number of Digital Beam Mask\r
- // Number of TX RUS Mask\r
- // Beam Index Mask\r
- // Digital Beam Index weights Real and Imaginary Mask\r
- \r
- // Precoding Matrix (PM) PDU\r
- // Precoding Matrix ID Mask\r
- // Number of Layers Mask\r
- // Number of Antenna Ports at the precoder output Mask\r
- // Precoder Weights Real and Imaginary Mask\r
- #define FAPI_U16_MASK 0xffff\r
- \r
- // Slot Indication\r
- \r
- #define FAPI_SLOT_MAX_VALUE 319\r
- \r
- // DL_TTI.request\r
- // nPDUS mask\r
- // nGroup mask\r
- #define FAPI_U8_MASK 0xff\r
- \r
- typedef enum {\r
- FAPI_DL_TTI_REQ_PDCCH_PDU_TYPE = 0,\r
- FAPI_DL_TTI_REQ_PDSCH_PDU_TYPE,\r
- FAPI_DL_TTI_REQ_CSI_RS_PDU_TYPE,\r
- FAPI_DL_TTI_REQ_SSB_PDU_TYPE\r
-}fapiDlTtiReqPduType_e; \r
-\r
-// nUe\r
-// Define Maximum number of Ues per Group\r
-#define FAPI_MAX_NUMBER_OF_UES_PER_GROUP 12\r
-\r
-// PDCCH PDU\r
-#define FAPI_BWPSIZE_MAX 275\r
-#define FAPI_BWPSIZE_START_MAX 274\r
-#define FAPI_SUBCARRIER_SPACING_MAX 4\r
-#define FAPI_CYCLIC_PREFIX_NORMAL 0\r
-#define FAPI_CYCLIC_PREFIX_EXTENDED 1\r
-#define FAPI_MAX_SYMBOL_START_INDEX 13\r
-\r
-#define FAPI_CORESET_DURATION_1_SYMBOL 1\r
-#define FAPI_CORESET_DURATION_2_SYMBOLS 2\r
-#define FAPI_CORESET_DURATION_3_SYMBOLS 3\r
-\r
-#define FAPI_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0\r
-#define FAPI_CCE_REG_MAPPING_TYPE_INTERLEAVED 1\r
-#define FAPI_REG_BUNDLE_SIZE_2 2\r
-#define FAPI_REG_BUNDLE_SIZE_3 3\r
-#define FAPI_REG_BUNDLE_SIZE_6 6\r
-\r
-#define FAPI_INTERLEAVER_SIZE_2 2\r
-#define FAPI_INTERLEAVER_SIZE_3 3\r
-#define FAPI_INTERLEAVER_SIZE_6 6\r
-\r
-#define FAPI_CORESET_TYPE_0_CONF_BY_PBCH_OR_SIB1 0\r
-#define FAPI_CORESET_TYPE_1 1\r
-\r
-#define FAPI_PREC_GRANULARITY_SAME_AS_REG_BUNDLE 0\r
-#define FAPI_PREC_GRANULARITY_ALL_CONTIG_RBS 1\r
-\r
-#define FAPI_CCE_INDEX_MAX 135\r
-#define FAPI_PDCCH_AGG_LEVEL_1 1\r
-#define FAPI_PDCCH_AGG_LEVEL_2 2\r
-#define FAPI_PDCCH_AGG_LEVEL_4 4\r
-#define FAPI_PDCCH_AGG_LEVEL_8 8\r
-#define FAPI_PDCCH_AGG_LEVEL_16 16\r
-\r
-#define FAPI_BETA_PDCCH_1_0_MAX 17\r
-\r
-#define FAPI_POWER_CTRL_OFF_SS_MINUS_3_DB 0\r
-#define FAPI_POWER_CTRL_OFF_SS_0_DB 1\r
-#define FAPI_POWER_CTRL_OFF_SS_3_DB 2\r
-#define FAPI_POWER_CTRL_OFF_SS_6_DB 3\r
-\r
-#define FAPI_MAX_NUMBER_OF_CODEWORDS 2\r
-\r
-#define FAPI_MAX_MCS_INDEX 31\r
-#define FAPI_MCS_INDEX_MASK 0x1f\r
-\r
-#define FAPI_MCS_TABLE_NOT_QAM_256 0\r
-#define FAPI_MCS_TABLE_QAM_256 1\r
-#define FAPI_MCS_TABLE_QAM_64_LOW_SE 2\r
-\r
-#define FAPI_REDUNDANCY_INDEX_MASK 0x03\r
-#define FAPI_MAX_DL_LAYERS 8\r
-\r
-#define FAPI_TRANSMISSION_SCHEME_1 1\r
-\r
-#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_PT_A 0\r
-#define FAPI_REF_POINT_FOR_PDSCH_DMRS_AT_LOWEST_ALLOC 1\r
-\r
-#define FAPI_DL_DMRS_SYMB_POS_MASK 0x3fff\r
-\r
-#define FAPI_MAX_DMRS_CDM_GRPS_WO_DATA 3\r
-\r
-#define FAPI_DMRS_PORTS_MASK 0x0fff\r
-\r
-#define FAPI_RES_ALLOC_TYPE_0 0\r
-#define FAPI_RES_ALLOC_TYPE_1 1\r
-\r
-#define FAPI_VRB_TO_PRB_MAP_NON_INTERLVD 0\r
-#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_2 1\r
-#define FAPI_VRB_TO_PRB_MAP_INTERLVD_RB_SIZE_4 2\r
-\r
-#define FAPI_MAX_START_SYMBOL_INDEX 13\r
-#define FAPI_MAX_NR_OF_SYMBOLS 14\r
-#define FAPI_PTRS_PORT_INDEX_MASK 0x3f\r
-#define FAPI_PTRS_TIME_DENSITY_1 0\r
-#define FAPI_PTRS_TIME_DENSITY_2 1\r
-#define FAPI_PTRS_TIME_DENSITY_4 2\r
-#define FAPI_PTRS_FREQ_DENSITY_2 0\r
-#define FAPI_PTRS_FREQ_DENSITY_4 1\r
-#define FAPI_PTRS_RE_OFFSET_MASK 0x03\r
-#define FAPI_EPRE_RATIO_PDSCH_PTRS_MASK 0x03\r
-// PDSCH Power Control Offset\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_8_DB 0\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_7_DB 1\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_6_DB 2\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_5_DB 3\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_4_DB 4\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_3_DB 5\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_2_DB 6\r
-#define FAPI_PWR_CTRL_OFFSET_MINUS_1_DB 7\r
-#define FAPI_PWR_CTRL_OFFSET_0_DB 8\r
-#define FAPI_PWR_CTRL_OFFSET_1_DB 9\r
-#define FAPI_PWR_CTRL_OFFSET_2_DB 10\r
-#define FAPI_PWR_CTRL_OFFSET_3_DB 11\r
-#define FAPI_PWR_CTRL_OFFSET_4_DB 12\r
-#define FAPI_PWR_CTRL_OFFSET_5_DB 13\r
-#define FAPI_PWR_CTRL_OFFSET_6_DB 14\r
-#define FAPI_PWR_CTRL_OFFSET_7_DB 15\r
-#define FAPI_PWR_CTRL_OFFSET_8_DB 16\r
-#define FAPI_PWR_CTRL_OFFSET_9_DB 17\r
-#define FAPI_PWR_CTRL_OFFSET_10_DB 18\r
-#define FAPI_PWR_CTRL_OFFSET_11_DB 19\r
-#define FAPI_PWR_CTRL_OFFSET_12_DB 20\r
-#define FAPI_PWR_CTRL_OFFSET_13_DB 21\r
-#define FAPI_PWR_CTRL_OFFSET_14_DB 22\r
-#define FAPI_PWR_CTRL_OFFSET_15_DB 23\r
-// Power Control Offset SS\r
-#define FAPI_PWR_CTRL_OFFSET_SS_MINUS_3_DB 0\r
-#define FAPI_PWR_CTRL_OFFSET_SS_0_DB 1\r
-#define FAPI_PWR_CTRL_OFFSET_SS_3_DB 2\r
-#define FAPI_PWR_CTRL_OFFSET_SS_6_DB 3\r
-// CSI Type\r
-#define FAPI_CSI_TRS 0\r
-#define FAPI_CSI_NON_ZERO_POWER 1\r
-#define FAPI_CSI_ZERO_POWER 2\r
-// Row entry into CSI Resource Location Table\r
-#define FAPI_CSIRLT_ROW_MAX_VALUE 18\r
-#define FAPI_CSI_FREQ_DOMAIN_MASK 0x0fff\r
-#define FAPI_CSI_SYMB_L1_MIN 2\r
-#define FAPI_CSI_SYMB_L1_MAX 12\r
-// CDM Type\r
-#define FAPI_CDM_TYPE_NO_CDM 0\r
-#define FAPI_CDM_TYPE_FD_CDM 1\r
-#define FAPI_CDM_TYPE_CDM4_FD2_TD2 2\r
-#define FAPI_CDM_TYPE_CDM8_FD2_TD4 3\r
-// Frequency Density\r
-#define FAPI_FD_DOT5_EVEN_RB 0\r
-#define FAPI_FD_DOT5_ODD_RB 1\r
-#define FAPI_FD_ONE 2\r
-#define FAPI_FD_THREE 3\r
-\r
-// SSB\r
-#define FAPI_SSB_BLOCK_INDEX_MASK 0x3f\r
-#define FAPI_SSB_SC_OFFSET_MASK 0x1f\r
-\r
-// UL TTI REQUEST\r
-#define FAPI_MAX_NUM_UE_GROUPS_INCLUDED 8\r
-#define FAPI__MAX_NUM_UE_IN_GROUP 6\r
-// PRACH PDU\r
-#define FAPI_MAX_NUM_PRACH_OCAS 7\r
-// PRACH FORMAT\r
-#define FAPI_PRACH_FORMAT_A1 0\r
-#define FAPI_PRACH_FORMAT_A2 1\r
-#define FAPI_PRACH_FORMAT_A3 2\r
-#define FAPI_PRACH_FORMAT_B1 3\r
-#define FAPI_PRACH_FORMAT_B2 4\r
-#define FAPI_PRACH_FORMAT_B3 5\r
-#define FAPI_PRACH_FORMAT_B4 6\r
-#define FAPI_PRACH_FORMAT_C0 7\r
-#define FAPI_PRACH_FORMAT_C2 8\r
-\r
-#define FAPI_MAX_PRACH_FD_OCCASION_INDEX 7\r
-#define FAPI_MAX_ZC_ZONE_CONFIG_NUMBER 419\r
-\r
-// PUSCH PDU\r
-#define FAPI_PUSCH_BIT_DATA_PRESENT_MASK 0x0001\r
-#define FAPI_PUSCH_UCI_DATA_PRESENT_MASK 0x0002\r
-#define FAPI_PUSCH_PTRS_INCLUDED_FR2_MASK 0x0004\r
-#define FAPI_PUSCH_DFTS_OFDM_TX_MASK 0x0008\r
-\r
-#define FAPI_MAX_QAM_MOD_ORDER 8\r
-#define FAPI_MCS_INDEX_MASK 0x1f\r
-\r
-#define FAPI_MCS_TABLE_NOT_QAM256 0\r
-#define FAPI_MCS_TABLE_QAM256 1\r
-#define FAPI_MCS_TABLE_QAM64_LOWSE 2\r
-#define FAPI_MCS_TABLE_NOT_QAM256_W_XFRM_PRECOD 3\r
-#define FAPI_MCS_TABLE_QAM64_LOWSE_W_XFRM_PRECOD 4\r
-#define FAPI_PUSCH_MAX_NUM_LAYERS 4\r
-// DMRS\r
-#define FAPI_UL_DMRS_SYMB_POS_MASK 0x3fff\r
-#define FAPI_UL_DMRS_CONFIG_TYPE_1 0\r
-#define FAPI_UL_DMRS_CONFIG_TYPE_2 1\r
-#define FAPI_MAX_DMRS_CDM_GRPS_NO_DATA 3\r
-#define FAPI_UL_DMRS_PORTS_MASK 0x07ff\r
-#define FAPI_UL_TX_DIRECT_CURR_LOCATION_MAX 3299\r
-#define FAPI_UL_TX_DIRECT_CURR_LOC_OUTSIDE_CARRIER 3300\r
-#define FAPI_UL_TX_DIRECT_CURR_LOC_UNDETERMINED 3301\r
-// PUSCH DATA\r
-#define FAPI_RV_INDEX_MASK 0x03\r
-#define FAPI_HARQ_PROCESS_ID_MASK 0x0f\r
-// PUSCH UCI INFO\r
-#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_SMALL_BLOCK_MAX 11\r
-#define FAPI_HARQ_ACK_CSI_PX_BIT_LEN_POLAR_MAX 1706\r
-// ALPHA SCALING\r
-#define FAPI_ALPHA_SCALE_0_5 0\r
-#define FAPI_ALPHA_SCALE_0_65 1\r
-#define FAPI_ALPHA_SCALE_0_8 2\r
-#define FAPI_ALPHA_SCALE_1_0 3\r
-// BETA OFFSET HARQ ACK\r
-#define FAPI_BETA_OFFSET_HARQ_ACK_MAX 15\r
-#define FAPI_BETA_OFFSET_CSIX_MAX 18\r
-\r
-// PUSCH PTRS INFORMATION 38.212 Section 7.3.1.1.2\r
-#define FAPI_MAX_NUMBER_PTRS_PORT_INDEX 11 // 0..11\r
-// UL PTRS POWER 5G FAPI Table 3-49\r
-#define FAPI_UL_PTRS_PWR_0_DB 0\r
-#define FAPI_UL_PTRS_PWR_3_DB 1\r
-#define FAPI_UL_PTRS_PWR_4_77_DB 2\r
-#define FAPI_UL_PTRS_PWR_6_DB 3\r
-// DFTSOFDM INFO 5g FAPI Table 3-50\r
-#define FAPI_MAX_LOW_PAPR_GROUP_NUMBER 29 // 0..29\r
-#define FAPI_MAX_LOW_PAPR_SEQ_NUMBER 87 // 3*LOW_PAPR_GRP_NUM\r
-#define FAPI_MAX_UL PTRS_SAMP_DENSITY 8\r
-#define FAPI_MAX_UL_PTRS_TD_XFRM_PRECOD 4\r
-\r
-// PUCCH PDU Table 3-51\r
-#define FAPI_MAX_PUCCH_FORMAT_TYPE 4\r
-#define FAPI_MULTI_SLOT_TX_IND_NO_MULTI_SLOT 0\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_START 1\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_CONT 2\r
-#define FAPI_MULTI_SLOT_TX_IND_TX_END 3\r
-#define FAPI_MAX_NUM_PRB_FOR_A_PUCCH 16\r
-#define FAPI_MAX_PUCCH_DUR_F0_AND_F2 2\r
-#define FAPI_MIN_PUCCH_DUR_F1_F3_F4 4\r
-#define FAPI_MAX_PUCCH_DUR_F1_F3_F4 14\r
-#define FAPI_MAX_INIT_CYCLIC_SHIFT_F0_F1_F3_F4 11\r
-#define FAPI_MAX_OCC_INDEX_F1 6\r
-#define FAPI_MAX_PRE_DFT_OCC_IDX_F4 3\r
-#define FAPI_MAX_PRE_DFT_OCC_LEN_F4 4\r
-#define FAPI_MAX_DMRS_CYC_SHIFT_F4 9\r
-#define FAPI_BIT_LEN_HARQ_PL_ZERO 0\r
-#define FAPI_BIT_LEN_HARQ_PL_F0_F1_2_BITS 1\r
-#define FAPI_BIT_LEN_HARQ_PL_F2_F3_F4_1706_BITS 2\r
-#define FAPI_BIT_LEN_CSI_PX_PL_NO_CSI 0\r
-#define FAPI_BIT_LEN_CSI_PX_PL_1706_BITS 1\r
-\r
-// SRS PDU\r
-#define FAPI_1_SRS_ANT_PORT 0\r
-#define FAPI_2_SRS_ANT_PORTS 1\r
-#define FAPI_4_SRS_ANT_PORTS 2\r
-#define FAPI_SRS_NO_REPETITIONS 0\r
-#define FAPI_SRS_2_REPETITIONS 2\r
-#define FAPI_SRS_4_REPETITIONS 4\r
-#define FAPI_SRS_CONFIG_INDEX_MASK 0x3f\r
-#define FAPI_SRS_BW_INDEX_MASK 0x03\r
-#define FAPI_TX_COMB_SIZE_2 0\r
-#define FAPI_TX_COMB_SIZE_4 1\r
-#define FAPI_MAX_SRS_FREQ_POSITION 67\r
-#define FAPI_MAX_SRS_FD_SHIFT 268\r
-#define FAPI_SRS_FREQ_HOPPING_MASK 0x03\r
-#define FAPI_SRS_NO_HOPPING 0\r
-#define FAPI_SRS_GRP_OR_SEQ_HOPPING 1\r
-#define FAPI_SRS_SEQ_HOPPING 2\r
-#define FAPI_SRS_RES_ALLOC_APERIODIC 0\r
-#define FAPI_SRS_RES_ALLOC_SEMI_PERSISTENT 1\r
-#define FAPI_SRS_RES_ALLOC_PERIODIC 2\r
-#define FAPI_MAX_LSOT_OFFSET_VALUE 2559\r
-\r
-// RX_DATA Indication\r
-#define FAPI_UL_CQI_INVALID 255\r
-#define FAPI_TIMING_ADVANCE_INVALID 0xffff\r
-#define FAPI_MAX_TIMING_ADVANCE 63\r
-#define FAPI_MAX_RSSI 1280\r
-\r
-\r
-// RACH Indication\r
-#define FAPI_RACH_FREQ_INDEX_MAX 7\r
-#define FAPI_RACH_DETECTED_PREAMBLES_MASK 0x3f\r
-#define FAPI_RACH_TIMING_ADVANCE_MAX 3846\r
-#define FAPI_RACH_PREAMBLE_POWER_INVALID 0xffffffff\r
-#define FAPI_RACH_PREAMBLE_TIMING_ADVANCE_INVALID 0xffff\r
-#define FAPI_RACH_PREAMBLE_POWER_MAX 170000\r
-\r
-// SR, HARQ, and CSI Part 1/2 PDUs Table 3-66\r
-#define FAPI_SR_MASK 0x01\r
-#define FAPI_HARQ_MASK 0x02\r
-#define FAPI_CSI_PART1 0x04\r
-#define FAPI_CSI_PART2 0x08\r
-#define FAPI_PUCCH_FORMAT2 0\r
-#define FAPI_PUCCH_FORMAT3 1\r
-#define FAPI_PUCCH_FORMAT4 2\r
-#define FAPI_PUCCH_FORMAT_MASK 0x03\r
-\r
-// SR PDU For Format 0 or 1 Table 3-67\r
-#define FAPI_SR_CONFIDENCE_LEVEL_GOOD 0\r
-#define FAPI_SR_CONFIDENCE_LEVEL_BAD 1\r
-#define FAPI_SR_CONFIDENCE_LEVEL_INVALID 0xff\r
-\r
-// HARQ PDU for Format 0 or 1 Table 3-68\r
-#define FAPI_HARQ_VALUE_PASS 0\r
-#define FAPI_HARQ_VALUE_FAIL 1\r
-#define FAPI_HARQ_VALUE_NOT_PRESENT 2\r
-\r
-// SR PDU for Format 2,3 or 4 Table 3-69\r
-#define FAPI_SR_PAYLOAD_MAX 1\r
-\r
-// HARQ PDU for Format 2,3 or 4 Table 3-70\r
-#define FAPI_HARQ_CRC_PASS 0\r
-#define FAPI_HARQ_CRC_FAIL 1\r
-#define FAPI_HARQ_CRC_NOT_PRESENT 2\r
-#define FAPI_HARQ_PAYLOAD_MAX 214\r
-\r
-\r
-// CSI Part 1 PDU Table 3-71 and 3-72\r
-#define FAPI_CSI_PARTX_CRC_PASS 0\r
-#define FAPI_CSI_PARTX_CRC_FAIL 1\r
-#define FAPI_CSI_PARTX_CRC_NOT_PRESENT 2\r
-#define FAPI_CSI_PARTX_PAYLOAD_MAX 214\r
-\r
-#if 0\r
-//------------------------------------------------------------------------------\r
-// FAPI callback functions to be implemented by the user\r
-//------------------------------------------------------------------------------\r
-/**\r
- * fapi callback structure is passed as part of ``fapi_create``. FAPI will call\r
- * these functions in response to any received request message.\r
- *\r
- * *Note: vendor specific callbacks are only valid in TIMER_MODE. Must be set\r
- * to NULL in RADIO mode.*\r
- */\r
-typedef struct {\r
- void (*fapi_param_response) (fapiInstanceHdl_t fapiHdl,\r
- pfapiParamResp_t resp);\r
- void (*fapi_config_response) (fapiInstanceHdl_t fapiHdl,\r
- pfapiConfigResp_t resp);\r
- void (*fapi_stop_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiStopInd_t resp);\r
- void (*fapi_error_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiErrorInd_t ind);\r
- void (*fapi_subframe_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiSubframeInd_t ind);\r
- void (*fapi_harq_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiHarqInd_t ind);\r
- void (*fapi_crc_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiCrcInd_t ind);\r
- void (*fapi_rx_ulsch_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiRxUlschInd_t ind);\r
- void (*fapi_rx_cqi_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiRxCqiInd_t ind);\r
- void (*fapi_rx_sr_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiRxSrInd_t ind);\r
- void (*fapi_rach_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiRachInd_t ind);\r
- void (*fapi_srs_ind) (fapiInstanceHdl_t fapiHdl,\r
- pfapiSrsInd_t ind);\r
-//------------------------------------------------------------------------------\r
-// Vendor Specific Callbacks\r
-//------------------------------------------------------------------------------\r
- void (*fapi_rip_measurement) (fapiInstanceHdl_t fapiHdl,\r
- pfapiMeasReport_t pMeasReport);\r
- void (*fapi_start_phy_shutdown) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
- void (*fapi_shutdown_resp) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
- void (*fapi_start_cnf) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
- void (*fapi_ul_iq_samples) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
- void (*fapi_dl_iq_samples) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
- void (*fapi_ul_copy_results_ind) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
-\r
- void (*fapi_endof_phy2mac_processing) (fapiInstanceHdl_t fapiHdl,\r
- void *pMsgInd);\r
-} fapiCb_t, *pfapiCb_t;\r
-\r
-//------------------------------------------------------------------------------\r
-\r
-fapiStatus_t fapi_init(pfapiInitConfig_t pinitConfig);\r
-fapiStatus_t fapi_destroy(void);\r
-fapiInstanceHdl_t fapi_create(pfapiCb_t callbacks,\r
- pfapiCreateConfig_t pCreateConfig);\r
-fapiStatus_t fapi_delete(fapiInstanceHdl_t fapiHdl);\r
-\r
-//------------------------------------------------------------------------------\r
-// Fapi P5 Messages\r
-//------------------------------------------------------------------------------\r
-fapiStatus_t fapi_param_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiParamReq_t req);\r
-fapiStatus_t fapi_config_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiConfigReq_t req);\r
-fapiStatus_t fapi_start_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiStartReq_t req);\r
-fapiStatus_t fapi_stop_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiStopReq_t req);\r
-//------------------------------------------------------------------------------\r
-// Fapi P7 Messages\r
-//------------------------------------------------------------------------------\r
-fapiStatus_t fapi_dl_config_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiDlConfigReq_t req);\r
-fapiStatus_t fapi_ul_config_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiUlConfigReq_t req);\r
-fapiStatus_t fapi_hi_dci0_request(fapiInstanceHdl_t fapiHdl,\r
- pfapiHiDci0Req_t req);\r
-fapiStatus_t fapi_tx_request(fapiInstanceHdl_t fapiHdl, pfapiTxReq_t\r
- req);\r
-#endif\r
-#endif //_FAPI_H_\r
-\r
+++ /dev/null
-/******************************************************************************\r
-* Copyright 2017 Cisco Systems, Inc.\r
-* Copyright (c) 2019 Intel.\r
-*\r
-* Licensed under the Apache License, Version 2.0 (the "License");\r
-* you may not use this file except in compliance with the License.\r
-* You may obtain a copy of the License at\r
-*\r
-* http://www.apache.org/licenses/LICENSE-2.0\r
-*\r
-* Unless required by applicable law or agreed to in writing, software\r
-* distributed under the License is distributed on an "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-* See the License for the specific language governing permissions and\r
-* limitations under the License.\r
-*\r
-*******************************************************************************/\r
-// This file has been modified by Intel in order to support 5G FAPI:PHY API Specification\r
-// Document 222.10.01 dated June 2019\r
-// Changes made by luis.farias@intel.com\r
-\r
-#ifndef _FAPI_INTERFACE_H_\r
-#define _FAPI_INTERFACE_H_\r
-\r
-#if defined(__cplusplus)\r
-extern "C" {\r
-#endif\r
-\r
-typedef signed char int8_t;\r
-typedef unsigned char uint8_t;\r
-typedef int16_t int16_t;\r
-typedef uint16_t uint16_t;\r
-typedef int32_t int32_t;\r
-typedef uint32_t uint32_t;\r
-\r
-// Update for 5G FAPI\r
-#define FAPI_PARAM_REQUEST 0x00\r
-#define FAPI_PARAM_RESPONSE 0x01\r
-#define FAPI_CONFIG_REQUEST 0x02\r
-#define FAPI_CONFIG_RESPONSE 0x03\r
-#define FAPI_START_REQUEST 0x04\r
-#define FAPI_STOP_REQUEST 0x05\r
-#define FAPI_STOP_INDICATION 0x06\r
-#define FAPI_ERROR_INDICATION 0x07\r
-// Reserved 0x08 - 0x7f\r
-#define FAPI_DL_TTI_REQUEST 0x80\r
-#define FAPI_UL_TTI_REQUEST 0x81\r
-#define FAPI_SLOT_INDICATION 0x82\r
-#define FAPI_UL_DCI_REQUEST 0x83\r
-#define FAPI_TX_DATA_REQUEST 0x84\r
-#define FAPI_RX_DATA_INDICATION 0x85\r
-#define FAPI_CRC_INDICATION 0x86\r
-#define FAPI_UCI_INDICATION 0x87\r
-#define FAPI_SRS_INDICATION 0x88\r
-#define FAPI_RACH_INDICATION 0x89\r
-// Reserved 0x8a -0xff\r
-\r
-\r
-\r
-// Tags per 5G FAPI\r
-// Cell Parameters\r
-#define FAPI_RELEASE_CAPABILITY_TAG 0x0001\r
-#define FAPI_PHY_STATE_TAG 0x0002\r
-#define FAPI_SKIP_BLANK_DL_CONFIG_TAG 0x0003\r
-#define FAPI_SKIP_BLANK_UL_CONFIG_TAG 0x0004\r
-#define FAPI_NUM_CONFIG_TLVS_TO_REPORT_TYPE_TAG 0x0005\r
-#define FAPI_CYCLIC_PREFIX_TAG 0x0006\r
-// PDCCH Parameters\r
-#define FAPI_SUPPORTED_SUBCARRIER_SPACING_DL_TAG 0x0007\r
-#define FAPI_SUPPORTED_BANDWIDTH_DL_TAG 0x0008\r
-#define FAPI_SUPPORTED_SUBCARRIER_SPACING_UL_TAG 0x0009\r
-#define FAPI_SUPPORTED_BANDWIDTH_UL_TAG 0x000A\r
-#define FAPI_CCE_MAPPING_TYPE_TAG 0x000B\r
-#define FAPI_CORESET_OUTSIDE_FIRST_3_OFDM_SYMS_OF_SLOT_TAG 0x000c \r
-#define FAPI_PRECODER_GRANULARITY_CORESET_TAG 0x000d\r
-#define FAPI_PDCCH_MU_MIMO_TAG 0x000e\r
-#define FAPI_PDCCH_PRECODER_CYCLING_TAG 0x000f\r
-#define FAPI_MAX_PDCCHS_PER_SLOT_TAG 0x0010\r
-// PUCCH Parameters\r
-#define FAPI_PUCCH_FORMATS_TAG 0x0011\r
-#define FAPI_MAX_PUCCHS_PER_SLOT_TAG 0x0012\r
-// PDSCH Parameters\r
-#define FAPI_PDSCH_MAPPING_TYPE_TAG 0x0013\r
-#define FAPI_PDSCH_ALLOCATION_TYPES_TAG 0x0014\r
-#define FAPI_PDSCH_VRB_TO_PRB_MAPPING_TAG 0x0015\r
-#define FAPI_PDSCH_CBG_TAG 0x0016\r
-#define FAPI_PDSCH_DMRS_CONFIG_TYPES_TAG 0x0017\r
-#define FAPI_PDSCH_DMRS_MAX_LENGTH_TAG 0x0018\r
-#define FAPI_PDSCH_DMRS_ADDITIONAL_POS_TAG 0x0019\r
-#define FAPI_MAX_PDSCHS_TBS_PER_SLOT_TAG 0x001a\r
-#define FAPI_MAX_NUMBER_MIMO_LAYERS_PDSCH_TAG 0x001b\r
-#define FAPI_SUPPORTED_MAX_MODULATION_ORDER_DL_TAG 0x001c \r
-#define FAPI_MAX_MU_MIMO_USERS_DL_TAG 0x001d\r
-#define FAPI_PDSCH_DATA_IN_DMRS_SYMBOLS_TAG 0x001e\r
-#define FAPI_PREMPTIONSUPPORT_TAG 0x001f\r
-#define FAPI_PDSCH_NON_SLOT_SUPPORT_TAG 0x0020\r
-// PUSCH Parameters\r
-#define FAPI_UCI_MUX_ULSCH_IN_PUSCH_TAG 0x0021\r
-#define FAPI_UCI_ONLY_PUSCH_TAG 0x0022\r
-#define FAPI_PUSCH_FREQUENCY_HOPPING_TAG 0x0023\r
-#define FAPI_PUSCH_DMRS_CONFIG_TYPES_TAG 0x0024\r
-#define FAPI_PUSCH_DMRS_MAX_LEN_TAG 0x0025\r
-#define FAPI_PUSCH_DMRS_ADDITIONAL_POS_TAG 0x0026\r
-#define FAPI_PUSCH_CBG_TAG 0x0027\r
-#define FAPI_PUSCH_MAPPING_TYPE_TAG 0x0028\r
-#define FAPI_PUSCH_ALLOCATION_TYPES_TAG 0x0029\r
-#define FAPI_PUSCH_VRB_TO_PRB_MAPPING_TAG 0x002a\r
-#define FAPI_PUSCH_MAX_PTRS_PORTS_TAG 0x002b\r
-#define FAPI_MAX_PDUSCHS_TBS_PER_SLOT_TAG 0x002c\r
-#define FAPI_MAX_NUMBER_MIMO_LAYERS_NON_CB_PUSCH_TAG 0x002d\r
-#define FAPI_SUPPORTED_MODULATION_ORDER_UL_TAG 0x002e\r
-#define FAPI_MAX_MU_MIMO_USERS_UL_TAG 0x002f\r
-#define FAPI_DFTS_OFDM_SUPPORT_TAG 0x0030\r
-#define FAPI_PUSCH_AGGREGATION_FACTOR_TAG 0x0031\r
-// PRACH Parameters\r
-#define FAPI_PRACH_LONG_FORMATS_TAG 0x0032\r
-#define FAPI_PRACH_SHORT_FORMATS_TAG 0x0033\r
-#define FAPI_PRACH_RESTRICTED_SETS_TAG 0x0034\r
-#define FAPI_MAX_PRACH_FD_OCCASIONS_IN_A_SLOT_TAG 0x0035\r
-// Measurement Parameters\r
-#define FAPI_RSSI_MEASUREMENT_SUPPORT_TAG 0x0036\r
-\r
-// CONFIG TLV TAGS per 5G FAPI\r
-// Carrier Configuration\r
-#define FAPI_DL_BANDWIDTH_TAG 0x1001\r
-#define FAPI_DL_FREQUENCY_TAG 0x1002\r
-#define FAPI_DL_K0_TAG 0x1003\r
-#define FAPI_DL_GRIDSIZE_TAG 0x1004\r
-#define FAPI_NUM_TX_ANT_TAG 0x1005\r
-#define FAPI_UPLINK_BANDWIDTH_TAG 0x1006\r
-#define FAPI_UPLINK_FREQUENCY_TAG 0x1007\r
-#define FAPI_UL_K0_TAG 0x1008\r
-#define FAPI_UL_GRID_SIZE_TAG 0x1009\r
-#define FAPI_NUM_RX_ANT_TAG 0x100a\r
-#define FAPI_FREQUENCY_SHIFT_7P5_KHZ_TAG 0x100b\r
-// Cell Configuration\r
-#define FAPI_PHY_CELL_ID_TAG 0x100c\r
-#define FAPI_FRAME_DUPLEX_TYPE_TAG 0x100d\r
-// SSB Configuration\r
-#define FAPI_SS_PBCH_POWER_TAG 0x100e\r
-#define FAPI_BCH_PAYLOAD_TAG 0x100f\r
-#define FAPI_SCS_COMMON_TAG 0x1010\r
-// PRACH Configuration\r
-#define FAPI_PRACH_SEQUENCE_LENGTH_TAG 0x1011\r
-#define FAPI_PRACH_SUBC_SPACING_TAG 0x1012\r
-#define FAPI_RESTRICTED_SET_CONFIG_TAG 0x1013\r
-#define FAPI_NUM_PRACH_FD_OCCASIONS_TAG 0x1014\r
-#define FAPI_PRACH_ROOT_SEQUENCE_INDEX_TAG 0x1015\r
-#define FAPI_NUM_ROOT_SEQUENCES_TAG 0x1016\r
-#define FAPI_K1_TAG 0x1017\r
-#define FAPI_PRACH_ZERO_CORR_CONF_TAG 0x1018\r
-#define FAPI_NUM_UNUSED_ROOT_SEQUENCES_TAG 0x1019\r
-#define FAPI_UNUSED_ROOT_SEQUENCES_TAG 0x101a\r
-#define FAPI_SSB_PER_RACH_TAG 0x101b\r
-#define FAPI_PRACH_MULTIPLE_CARRIERS_IN_A_BAND_TAG 0x101c\r
-// SSB Table\r
-#define FAPI_SSB_OFFSET_POINT_A_TAG 0x101d\r
-#define FAPI_BETA_PSS_TAG 0x101e\r
-#define FAPI_SSB_PERIOD_TAG 0x101f\r
-#define FAPI_SSB_SUBCARRIER_OFFSET_TAG 0x1020\r
-#define FAPI_MIB_TAG 0x1021\r
-#define FAPI_SSB_MASK_TAG 0x1022\r
-#define FAPI_BEAM_ID_TAG 0x1023\r
-#define FAPI_SS_PBCH_MULTIPLE_CARRIERS_IN_A_BAND_TAG 0x1024\r
-#define FAPI_MULTIPLE_CELLS_SS_PBCH_IN_A_CARRIER_TAG 0x1025\r
-// TDD Table\r
-#define FAPI_TDD_PERIOD_TAG 0x1026\r
-#define FAPI_SLOT_CONFIG_TAG 0x1027\r
-// Measurement Configuration\r
-#define FAPI_RSSI_MESUREMENT_TAG 0x1028\r
-\r
-// Error Codes updated per 5G FAPI Table 3-31\r
-#define FAPI_MSG_OK 0x0\r
-#define FAPI_MSG_INVALID_STATE 0x1\r
-#define FAPI_MSG_INVALID_CONFIG 0x2\r
-#define FAPI_MSG_SFN_OUT_OF_SYNC 0x3\r
-#define FAPI_MSG_SLOT_ERR 0x4\r
-#define FAPI_MSG_BCH_MISSING 0x5\r
-#define FAPI_MSG_INVALID_SFN 0x6\r
-#define FAPI_MSG_UL_DCI_ERR 0x7\r
-#define FAPI_MSG_TX_ERR 0x8\r
-\r
-\r
-// TODO : Work out what the correct maximums should be// Needs Review for 5G\r
-#if 0\r
-// Number of UL/DL configurations, I, as defined by 36.212 section 5.3.3.1.4\r
-// todo : work out what the max is\r
-#define FAPI_MAX_UL_DL_CONFIGURATIONS 4\r
-#define FAPI_MAX_NUM_PHYSICAL_ANTENNAS 4\r
-#define FAPI_MAX_NUM_SCHEDULED_UES 8\r
-#define FAPI_MAX_NUM_SUBBANDS 8\r
-#define FAPI_MAX_ANTENNA_PORT_COUNT 2\r
-#endif\r
-\r
-// 5G FAPI Definitions\r
-#define NUMEROLOGIES 5\r
-#define MAX_NUM_UNUSED_ROOT_SEQUENCES 63 // 38.331 page 383\r
-#define MAX_NUM_PRACH_FD_OCCASIONS 64 // 38.331 page 383\r
-#define MAX_NUM_OF_SYMBOLS_PER_SLOT 14\r
-#define MAX_TDD_PERIODICITY 160// 38.212 11.1 for u=4 and P=10 ms\r
-#define MAX_NUMBER_TX_RUS 4 // m=p*q with p number of panels and q number of TxRU/RxRU per panel, depends on\r
- // the RF configuration, currently n=m=4, q=1, p=4 and k=21 (number of beams per pannel). n number of antenna ports\r
-#define MAX_NUMBER_OF_BEAMS 64 // Intel API Page 27\r
-#define MAX_NUM_ANT_PORTS 8 // Based on current RF\r
-#define MAX_NUM_LAYERS 8 // 38.211 Table 7.3.1.3-1\r
-#define MAX_NUM_TLVS_CELL_CONFIG 2 // 5G FAPI Table 3-9 (A)\r
-#define MAX_NUM_TLVS_CARRIER_CONFIG 27 // 5G FAPI Table 3-10 (B)\r
-#define MAX_NUM_TLVS_PDCCH_CONFIG 6 // 5G FAPI Table 3-11 (C)\r
-#define MAX_NUM_TLVS_PUCCH_CONFIG 2 // 5G FAPI Table 3-12 (D)\r
-#define MAX_NUM_TLVS_PDSCH_CONFIG 14 // 5G FAPI Table 3-13 (E)\r
-#define MAX_NUM_TLVS_PUSCH_CONFIG 17 // 5G FAPI Table 3-14 (F)\r
-#define MAX_NUM_TLVS_PRACH_CONFIG 4 // 5G FAPI Table 3-15 (G)\r
-#define MAX_NUM_TLVS_MEAS_CONFIG 1 // 5G FAPI Table 3-16 (H)\r
-#define MAX_NUM_TLVS_CONFIG 74 // A+B+C+D+E+F+G+H + Padding\r
-#define MAX_NUMBER_UNSUPPORTED_TLVS 74 \r
-#define MAX_NUMBER_OF_INVALID_IDLE_ONLY_TLVS 74\r
-#define MAX_NUMBER_OF_INVALID_RUNNING_ONLY_TLVS 74\r
-#define MAX_NUMBER_OF_MISSING_TLVS 74\r
-#define MAX_NUM_DIGBFINTERFACES 4 // Based on RF, 5G FAPI says {0,255} \r
-#define MAX_NUM_PRGS_PER_TTI 4 // Based on 38.214 5.1.2.3\r
-#define DCI_PAYLOAD_BYTE_LEN 32 // Based on Intel API MAX_DCI_BIT_BYTE_LEN \r
-#define MAX_NUMBER_DL_DCI 32 // Based on Intel API MAX_NUM_PDCCH \r
-#define MAX_NUMBER_OF_CODEWORDS_PER_PDU 2 // Based on MAX_DL_CODEWORD\r
-#define MAX_NUMBER_DL_PDUS_PER_TTI 129 // Based on (MAX_NUM_PDSCH*MAX_DL_CODEWORD + MAX_NUM_PDCCH + MAX_NUM_SRS + 1 PBCH/SLOT) \r
-#define MAX_NUMBER_OF_UES_PER_TTI 16 // Per common_ran_parameters.h \r
-#define MAX_NUM_CB_PER_TTI_IN_BYTES 192 // Based on Max Tb size of 1376264 bits + 24 crc over (8848-24) and O/H\r
-#define MAX_NUM_PTRS_PORTS 12 // Per 3GPP 38.212 Table 7.3.1.1.2-21\r
-#define MAX_NUMBER_OF_GROUPS_PER_TTI 8 // FlexRAN API Table 33\r
-#define MAX_NUMBER_UL_PDUS_PER_TTI 328 // (MAX_NUM_PUSCH+MAX_NUM_PUCCH+MAX_NUM_SRS+MAX_NUM_PRACH_DET)\r
-#define MAX_NUMBER_DCI_PDUS_PER_TTI 32 // Based on MAX_NUM_PDCCH\r
-#define MAX_NUMBER_OF_TLVS_PER_PDU 32 // Based on FAPI/nFAPI implementation\r
-#define MAX_NUMBER_TX_PDUS_PER_TTI 129 // Same as MAX_NUMBER_DL_PDUS_PER_TTI\r
-#define MAX_PDU_LENGTH 172096 // Based on 38.214 5.1.3.4, the TBS is 1376264 bits and divided by 8 and aligned to 64 bytes\r
-#define MAX_NUMBER_OF_PDUS_PER_TTI 129 // Same as MAX_NUMBER_DL_PDUS_PER_TTI\r
-#define MAX_NUMBER_OF_ULSCH_PDUS_PER_TTI 64 // NUM_PUSCH_CHAN*MAX_NUMBER_OF_CODEWORDS_PER_PDU\r
-#define MAX_NUMBER_OF_CRCS_PER_SLOT 32 // Based on MAX_NUM_UL_CHAN \r
-#define MAX_HARQ_INFO_LEN_BYTES 214 // Based on 5G FAPI Table 3-70\r
-#define MAX_CSI_PART1_DATA_BYTES 214 // Based on 5G FAPI Table 3-71\r
-#define MAX_CSI_PART2_DATA_BYTES 214 // Based on 5G FAPI Table 3-72\r
-#define MAX_NUMBER_OF_HARQS_PER_IND 2 // Based on 5G FAPI Table 3-68\r
-#define MAX_SR_PAYLOAD_SIZE 1 // Based on 5G FAPI Table 3-69\r
-#define MAX_HARQ_PAYLOAD_SIZE 214 // Based on 5G FAPI Table 3-70\r
-#define MAX_NUMBER_UCI_PDUS_PER_SLOT 200 // Based on MAX_NUM_PUCCH\r
-#define MAX_NUMBER_RBS 273 // Based on MAX_NUM_OF_PRB_IN_FULL_BAND\r
-#define MAX_NUMBER_OF_REP_SYMBOLS 4 // Based on 5g FAPI Table 3-73\r
-#define MAX_NUMBER_SRS_PDUS_PER_SLOT 32 // Based on MAX_NUM_SRS\r
-#define MAX_NUM_PREAMBLES_PER_SLOT 64 // Based on MAX_NUM_PRACH_DET\r
-#define MAX_NUMBER_RACH_PDUS_PER_SLOT 64 // Based on MAX_NUM_PRACH_DET\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t numberOfMessagesIncluded;\r
- uint8_t handle; // Can be used for Phy Id or Carrier Id\r
-} fapi_msg_header_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t message_type_id;\r
- uint32_t length; // Length of the message body in bytes\r
-} fapi_msg_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t tag;\r
- uint16_t length;\r
-} fapi_tl_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_tl_t tl;\r
- uint8_t value;\r
-} fapi_uint8_tlv_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_tl_t tl;\r
- uint16_t value;\r
-} fapi_uint16_tlv_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_tl_t tl;\r
- int16_t value;\r
-} fapi_int16_tlv_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_tl_t tl;\r
- uint32_t value;\r
-} fapi_uint32_tlv_t;\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t tag; // In 5G FAPI for Cell Params\r
- uint8_t length;\r
- uint8_t value;\r
-} fapi_config_tlv_t;\r
- \r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; // For PARAM.req message length in fapi_msg_t is zero\r
-} fapi_param_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint16_tlv_t releaseCapability;\r
- fapi_uint16_tlv_t phyState;\r
- fapi_uint8_tlv_t skipBlankDlConfig;\r
- fapi_uint8_tlv_t skipBlankUlConfig;\r
- fapi_uint16_tlv_t numTlvsToReport;\r
- //fapi_param_tlv_t tlvStatus[MAX_NUMBER_OF_CONFIG_PARMS]; // Need to define this value based on 5G FAPI\r
-} fapi_cell_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t cyclicPrefix;\r
- fapi_uint8_tlv_t supportedSubcarrierSpacingDl;\r
- fapi_uint16_tlv_t supportedBandwidthDl;\r
- fapi_uint8_tlv_t supportedSubcarrierSpecingsUl;\r
- fapi_uint16_tlv_t supportedBandwidthUl;\r
-} fapi_carrier_parms_t;\r
-\r
-// Updated per 5G FAPI \r
-typedef struct {\r
- fapi_uint8_tlv_t cceMappingType;\r
- fapi_uint8_tlv_t coresetOutsideFirst3OfdmSymsOfSlot;\r
- fapi_uint8_tlv_t precoderGranularityCoreset;\r
- fapi_uint8_tlv_t pdcchMuMimo;\r
- fapi_uint8_tlv_t pdcchPrecoderCycling;\r
- fapi_uint8_tlv_t maxPdcchsPerSlot;\r
-} fapi_pdcch_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t pucchFormats;\r
- fapi_uint8_tlv_t maxPucchsPerSlot;\r
-} fapi_pucch_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t pdschMappingType;\r
- fapi_uint8_tlv_t pdschAllocationTypes;\r
- fapi_uint8_tlv_t pdschVrbToPrbMapping;\r
- fapi_uint8_tlv_t pdschCbg;\r
- fapi_uint8_tlv_t pdschDmrsConfigTypes;\r
- fapi_uint8_tlv_t pdschDmrsMaxLength;\r
- fapi_uint8_tlv_t pdschDmrsAdditionalPos;\r
- fapi_uint8_tlv_t maxPdschsTBsPerSlot;\r
- fapi_uint8_tlv_t maxNumberMimoLayersPdsch;\r
- fapi_uint8_tlv_t supportedMaxModulationOrderDl;\r
- fapi_uint8_tlv_t maxMuMimoUsersDl;\r
- fapi_uint8_tlv_t pdschDataInDmrsSymbols;\r
- fapi_uint8_tlv_t premptionSupport;\r
- fapi_uint8_tlv_t pdschNonSlotSupport;\r
-} fapi_pdsch_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t uciMuxUlschInPusch;\r
- fapi_uint8_tlv_t uciOnlyPusch;\r
- fapi_uint8_tlv_t puschFrequencyHopping;\r
- fapi_uint8_tlv_t puschDmrsConfigTypes;\r
- fapi_uint8_tlv_t puschDmrsMaxLen;\r
- fapi_uint8_tlv_t puschDmrsAditionalPos;\r
- fapi_uint8_tlv_t puschCbg;\r
- fapi_uint8_tlv_t puschMappingType; \r
- fapi_uint8_tlv_t puschAllocationTypes;\r
- fapi_uint8_tlv_t puschVrbToPrbMapping;\r
- fapi_uint8_tlv_t puschMaxPtrsPorts;\r
- fapi_uint8_tlv_t maxPduschsTBsPerSlot;\r
- fapi_uint8_tlv_t maxNumberMimoLayersnonCbPusch;\r
- fapi_uint8_tlv_t supportedModulationOrderUl;\r
- fapi_uint8_tlv_t maxMuMimoUsersUl;\r
- fapi_uint8_tlv_t dftsOfdmSupport;\r
- fapi_uint8_tlv_t puschAggregationFactor;\r
-} fapi_pusch_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t prachLongFormats;\r
- fapi_uint8_tlv_t prachShortFormats;\r
- fapi_uint8_tlv_t prachRestrictedSets;\r
- fapi_uint8_tlv_t maxPrachFdOccasionsInASlot;\r
-} fapi_prach_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t rssiMeasurementSupport;\r
-} fapi_meas_parms_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_cell_parms_t cell_parms;\r
- fapi_carrier_parms_t carr_parms;\r
- fapi_pdcch_parms_t pdcch_parms;\r
- fapi_pucch_parms_t pucch_parms;\r
- fapi_pdsch_parms_t pdsch_parms;\r
- fapi_pusch_parms_t pusch_parms;\r
- fapi_prach_parms_t prach_parms;\r
- fapi_meas_parms_t meas_parms;\r
-} fapi_params_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint8_t error_code;\r
- uint8_t number_of_tlvs;\r
- fapi_uint16_tlv_t tlvs[MAX_NUM_TLVS_CONFIG];\r
-} fapi_param_resp_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint16_tlv_t dlBandwidth;\r
- fapi_uint32_tlv_t dlFrequency;\r
- fapi_uint16_tlv_t dlk0[NUMEROLOGIES];\r
- fapi_uint16_tlv_t dlGridSize[NUMEROLOGIES];\r
- fapi_uint16_tlv_t numTxAnt;\r
- fapi_uint16_tlv_t uplinkBandwidth;\r
- fapi_uint32_tlv_t uplinkFrequency;\r
- fapi_uint16_tlv_t ulk0[NUMEROLOGIES];\r
- fapi_uint16_tlv_t ulGridSize[NUMEROLOGIES];\r
- fapi_uint16_tlv_t numRxAnt;\r
- fapi_uint8_tlv_t frequencyShift7p5KHz;\r
-} fapi_carrier_config_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t phyCellId;\r
- fapi_uint8_tlv_t frameDuplexType;\r
-} fapi_cell_config_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint32_tlv_t ssPbchPower;\r
- fapi_uint8_tlv_t bchPayload;\r
- fapi_uint8_tlv_t scsCommon;\r
-} fapi_ssb_config_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint16_tlv_t prachRootSequenceIndex;\r
- fapi_uint8_tlv_t numRootSequences;\r
- fapi_uint8_tlv_t unusedRootSequences[MAX_NUM_UNUSED_ROOT_SEQUENCES];\r
-} fapi_prachFdOccasion_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t prachSequenceLength;\r
- fapi_uint8_tlv_t prachSubCSpacing;\r
- fapi_uint8_tlv_t restrictedSetConfig;\r
- fapi_prachFdOccasion_t prachFdOccasion[MAX_NUM_PRACH_FD_OCCASIONS];\r
- fapi_uint8_tlv_t ssbPerRach;\r
- fapi_uint8_tlv_t prachMultipleCarriersInABand;\r
-} fapi_prach_configuration_t;\r
-\r
-//Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint16_tlv_t ssbOffsetPointA;\r
- fapi_uint8_tlv_t betaPss;\r
- fapi_uint8_tlv_t ssbPeriod;\r
- fapi_uint8_tlv_t ssbSubCarrierOffset;\r
- fapi_uint32_tlv_t mib;\r
- fapi_uint32_tlv_t ssbMask[2];\r
- fapi_uint8_tlv_t beamId[64];\r
- fapi_uint8_tlv_t ssPbchMultipleCarriersInABand;\r
- fapi_uint8_tlv_t multipleCellsSsPbchInACarrier;\r
-} fapi_ssb_table_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t slotConfig[MAX_NUM_OF_SYMBOLS_PER_SLOT];\r
-} fapi_slotconfig_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t tddPeriod;\r
- fapi_slotconfig_t slotConfig[MAX_TDD_PERIODICITY];\r
-} fapi_tdd_table_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_uint8_tlv_t rssiMeasurement;\r
-} fapi_meas_config_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- int16_t digBeamWeightRe;\r
- int16_t digBeamWeightIm;\r
-} fapi_dig_beam_weight_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t beamIdx;\r
- fapi_dig_beam_weight_t digBeamWeight[MAX_NUMBER_TX_RUS];\r
-} fapi_dig_beam_config_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t numDigBeams;\r
- uint16_t numTxRus;\r
- fapi_dig_beam_config_t digBeam[MAX_NUMBER_OF_BEAMS];\r
-} fapi_beamforming_table_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- int16_t preCoderWeightRe;\r
- int16_t preCoderWeightIm;\r
-} fapi_precoderWeight_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_precoderWeight_t precoder_weight[MAX_NUM_ANT_PORTS];\r
-} fapi_precoder_weight_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pmIdx;\r
- uint16_t numLayers;\r
- uint16_t numAntPorts;\r
- fapi_precoder_weight_t precoderWeight[MAX_NUM_LAYERS];\r
-} fapi_precoding_table_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_carrier_config_t carrierConfig;\r
- fapi_cell_config_t cellConfig;\r
- fapi_ssb_config_t ssbConfig; \r
- //fapi_prach_config_t prachConfig; //To be defined\r
- fapi_ssb_table_t ssbTable;\r
- fapi_tdd_table_t tddTable;\r
- fapi_meas_config_t measConfig;\r
- fapi_beamforming_table_t beamformingTable;\r
- fapi_precoding_table_t precodingTable;\r
- } fapi_config_t;\r
-\r
-// Updated per 5G FAPI \r
-typedef struct {\r
- fapi_msg_t header;\r
- uint8_t number_of_tlvs;\r
- fapi_uint16_tlv_t tlvs[MAX_NUM_TLVS_CONFIG];\r
-} fapi_config_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint8_t error_code;\r
- uint8_t number_of_invalid_tlvs;\r
- uint8_t number_of_inv_tlvs_idle_only;\r
- uint8_t number_of_missing_tlvs;\r
- fapi_uint16_tlv_t tlvs[4*MAX_NUM_TLVS_CONFIG];\r
- // fapi_uint16_tlv_t unsupported_or_invalid_tlvs[MAX_NUMBER_UNSUPPORTED_TLVS];\r
- // fapi_uint16_tlv_t invalid_idle_only_tlvs[MAX_NUMBER_OF_INVALID_IDLE_ONLY_TLVS];\r
- // fapi_uint16_tlv_t invalid_running_only_tlvs[MAX_NUMBER_OF_INVALID_RUNNING_ONLY_TLVS];\r
- // fapi_uint16_tlv_t missing_tlvs[MAX_NUMBER_OF_MISSING_TLVS];\r
-} fapi_config_resp_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; // Message Length is zero for START.request\r
-} fapi_start_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; // Message Length is zero for STOP.request\r
-} fapi_stop_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; // Message Length is zero for STOP.indication\r
-} fapi_stop_ind_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t message_id;\r
- uint8_t error_code;\r
-} fapi_error_ind_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
-} fapi_slot_ind_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t beamidx;\r
-} fapi_bmi_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pmIdx;\r
- fapi_bmi_t beamIdx[MAX_NUM_DIGBFINTERFACES];\r
-} fapi_pmi_bfi_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint16_t numPrgs;\r
- uint16_t prgSize;\r
- uint8_t digBfInterfaces;\r
- fapi_pmi_bfi_t pmi_bfi[MAX_NUM_PRGS_PER_TTI];\r
-} fapi_precoding_bmform_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t rnti;\r
- uint16_t scramblingId; \r
- uint16_t scramblingRnti;\r
- uint8_t cceIndex;\r
- uint8_t aggregationLevel;\r
- fapi_precoding_bmform_t pc_and_bform;\r
- uint8_t beta_pdcch_1_0;\r
- uint8_t powerControlOfssetSS;\r
- uint16_t payloadSizeBits;\r
- uint8_t payload[DCI_PAYLOAD_BYTE_LEN];\r
-} fapi_dl_dci_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t bwpSize;\r
- uint16_t bwpPart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix;\r
- uint8_t startSymbolIndex;\r
- uint8_t durationSymbols;\r
- uint8_t freqDomainResource[6];\r
- uint8_t cceRegMappingType;\r
- uint8_t regBundleSize;\r
- uint8_t interleaverSize;\r
- uint8_t coreSetSize;\r
- uint16_t shiftIndex; \r
- uint8_t precoderGranularity;\r
- uint16_t numDlDci;\r
- fapi_dl_dci_t* dlDci;\r
- } fapi_dl_pddch_pdu_t;\r
- \r
- // Updated per 5G FAPI\r
- typedef struct {\r
- uint16_t targetCodeRate; \r
- uint8_t qamModOrder;\r
- uint8_t mcsIndex;\r
- uint8_t mcsTable;\r
- uint8_t rvIndex;\r
- uint32_t tbSize;\r
- } fapi_codeword_pdu_t;\r
- \r
- // Updated per 5G FAPI\r
- typedef struct {\r
- uint16_t pduBitMap; \r
- uint16_t rnti;\r
- uint16_t pduIndex;\r
- uint16_t bwpSize;\r
- uint16_t bwpStart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix; \r
- uint8_t nrOfCodeWords;\r
- fapi_codeword_pdu_t cwInfo[MAX_NUMBER_OF_CODEWORDS_PER_PDU]; \r
- uint16_t dataScramblingId; \r
- uint8_t nrOfLayers;\r
- uint8_t transmissionScheme;\r
- uint8_t refPoint;\r
- uint16_t dlDmrsSymbPos;\r
- uint8_t dmrsConfigType;\r
- uint16_t dlDmrsScramblingId;\r
- uint8_t scid;\r
- uint8_t numDmrsCdmGrpsNoData;\r
- uint16_t dmrsPorts;\r
- uint8_t resourceAlloc;\r
- uint8_t rbBitmap;\r
- uint16_t rbStart;\r
- uint16_t rbSize;\r
- uint8_t vrbToPrbMapping;\r
- uint8_t startSymbIndex;\r
- uint8_t nrOfSymbols;\r
- uint8_t ptrsPortIndex;\r
- uint8_t ptrsTimeDensity;\r
- uint8_t ptrsFreqDensity;\r
- uint8_t ptrsReOffset;\r
- uint8_t nEpreRatioOfPdschToPtrs;\r
- fapi_precoding_bmform_t preCodingAndBeamforming;\r
- uint8_t powerControlOffset; \r
- uint8_t powerControlOffsetSS;\r
- uint8_t isLastCbPresent;\r
- uint8_t isInlineTbCrc;\r
- uint32_t dlTbCrc;\r
- } fapi_dl_pdsch_pdu_t;\r
- \r
- // Updated per 5G FAPI\r
- typedef struct {\r
- uint16_t bwpSize;\r
- uint16_t bwpStart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix;\r
- uint16_t startRb;\r
- uint16_t nrOfRbs;\r
- uint8_t csiType;\r
- uint8_t row;\r
- uint16_t freqDomain;\r
- uint8_t symbL0;\r
- uint8_t symbL1;\r
- uint8_t cdmType; \r
- uint8_t freqDensity;\r
- uint16_t scramId;\r
- uint8_t powerControlOffset;\r
- uint8_t powerControlOffsetSs;\r
- fapi_precoding_bmform_t preCodingAndBeamforming;\r
- } fapi_dl_csi_rs_pdu_t;\r
-\r
-// Updated per 5G FAPI \r
- typedef struct {\r
- uint8_t dmrsTypeAPosition;\r
- uint8_t pdcchConfigSib1;\r
- uint8_t cellBarred;\r
- uint8_t intraFreqReselction;\r
- } fapi_phy_mib_pdu_t;\r
-\r
-// Updated per 5G FAPI \r
- typedef struct {\r
- union\r
- {\r
- uint32_t bchPayload;\r
- fapi_phy_mib_pdu_t phyMibPdu;\r
- }v;\r
- } fapi_bch_payload_t;\r
- \r
- // Updated per 5G FAPI\r
- typedef struct {\r
- \r
- uint16_t physCellId;\r
- uint8_t betaPss;\r
- uint8_t ssbBlockIndex;\r
- uint16_t ssbSubCarrierOffset;\r
- uint8_t ssbOffsetPointA;\r
- uint8_t bchPayloadFlag;\r
- fapi_bch_payload_t bchPayload;\r
- fapi_precoding_bmform_t preCodingAndBeamforming;\r
- } fapi_dl_ssb_pdu_t;\r
- \r
-// Updated per 5G FAPI\r
- typedef struct {\r
- uint16_t pduType;\r
- uint16_t pduSize;\r
- union\r
- {\r
- fapi_dl_pddch_pdu_t pdcch_pdu;\r
- fapi_dl_pdsch_pdu_t pdsch_pdu;\r
- fapi_dl_csi_rs_pdu_t csi_rs_pdu;\r
- fapi_dl_ssb_pdu_t ssb_pdu;\r
- }u;\r
-} fapi_dl_tti_req_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t nPdus;\r
- uint8_t nGroup;\r
- fapi_dl_tti_req_pdu_t* pdus;\r
-} fapi_dl_tti_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint8_t physCellId;\r
- uint8_t numPrachOcas;\r
- uint8_t prachFormat;\r
- uint8_t numRa;\r
- uint8_t prachStartSymbol;\r
- uint8_t numCs;\r
- fapi_precoding_bmform_t beamforming;\r
-} fapi_ul_prach_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t nUe;\r
- uint8_t pduIdx[MAX_NUMBER_OF_UES_PER_TTI];\r
-} fapi_ue_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t rvIndex;\r
- uint8_t harqProcessId;\r
- uint8_t newDataIndicator;\r
- uint32_t tbSize;\r
- uint16_t numCb;\r
- uint8_t cbPresentAndPosition[MAX_NUM_CB_PER_TTI_IN_BYTES];\r
-}fapi_pusch_data_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t harqAckBitLength;\r
- uint16_t csiPart1BitLength;\r
- uint16_t csiPart2BitLength;\r
- uint8_t alphaScaling;\r
- uint8_t betaOffsetHarqAck;\r
- uint8_t betaOffsetCsi1;\r
- uint8_t betaOffsetCsi2;\r
-} fapi_pusch_uci_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t ptrsPortIndex;\r
- uint8_t ptrsDmrsPort;\r
- uint8_t ptrsReOffset;\r
-} fapi_ptrs_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t numPtrsPorts;\r
- fapi_ptrs_info_t ptrsInfo[MAX_NUM_PTRS_PORTS];\r
- uint8_t ptrsTimeDensity;\r
- uint8_t ptrsFreqDensity;\r
- uint8_t ulPtrsPower;\r
-} fapi_pusch_ptrs_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t lowPaprGroupNumber;\r
- uint16_t lowPaprSequenceNumber; \r
- uint8_t ulPtrsSampleDensity;\r
- uint8_t ulPtrsTimeDensityTransformPrecoding;\r
-} fapi_dfts_ofdm_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint16_t pduBitMap;\r
- uint16_t rnti;\r
- uint32_t handle;\r
- uint16_t bwpSize;\r
- uint16_t bwpStart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix;\r
- uint16_t targetCodeRate;\r
- uint8_t qamModOrder;\r
- uint8_t mcsIndex;\r
- uint8_t mcsTable;\r
- uint8_t transformPrecoding;\r
- uint16_t dataScramblingId;\r
- uint8_t nrOfLayers;\r
- uint16_t ulDmrsSymbPos;\r
- uint8_t dmrsConfigType;\r
- uint16_t ulDmrsScramblingId;\r
- uint8_t scid;\r
- uint8_t numDmrsCdmGrpsNoData;\r
- uint16_t dmrsPorts;\r
- uint8_t resourceAlloc;\r
- uint8_t rbBitmap[36];\r
- uint16_t rbStart;\r
- uint16_t rbSize;\r
- uint8_t vrbToPrbMapping;\r
- uint8_t frequencyHopping;\r
- uint16_t txDirectCurrentLocation;\r
- uint8_t uplinkFrequencyShift7p5khz;\r
- uint8_t startSymbIndex;\r
- uint8_t nrOfSymbols;\r
- fapi_pusch_data_t puschData;\r
- fapi_pusch_uci_t puschUci;\r
- fapi_pusch_ptrs_t puschPtrs;\r
- fapi_dfts_ofdm_t dftsOfdm;\r
- fapi_precoding_bmform_t beamforming;\r
-} fapi_ul_pusch_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint16_t rnti;\r
- uint32_t handle;\r
- uint16_t bwpSize;\r
- uint16_t bwpStart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix;\r
- uint8_t formatType;\r
- uint8_t multiSlotTxIndicator;\r
- uint8_t pi2Bpsk;\r
- uint16_t prbStart;\r
- uint16_t prbSize;\r
- uint8_t startSymbolIndex;\r
- uint8_t nrOfSymbols;\r
- uint8_t freqHopFlag;\r
- uint16_t secondHopPrb;\r
- uint8_t groupHopFlag; \r
- uint8_t sequenceHopFlag;\r
- uint16_t hoppingId;\r
- uint16_t initialCyclicShift;\r
- uint16_t dataScramblingId;\r
- uint8_t timeDomainOccIdx;\r
- uint8_t preDftOccIdx;\r
- uint8_t preDftOccLen;\r
- uint8_t addDmrsFlag;\r
- uint16_t dmrsScramblingId;\r
- uint8_t dmrsCyclicShift;\r
- uint8_t srFlag;\r
- uint8_t bitLenHarq;\r
- uint16_t bitLenCsiPart1;\r
- uint16_t bitLenCsiPart2;\r
- fapi_precoding_bmform_t beamforming;\r
-} fapi_ul_pucch_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t rnti;\r
- uint32_t handle;\r
- uint16_t bwpsize;\r
- uint16_t bwpstart;\r
- uint8_t subCarrierSpacing;\r
- uint8_t cyclicPrefix;\r
- uint8_t numAntPorts;\r
- uint8_t numSymbols;\r
- uint8_t numRepetitions;\r
- uint8_t timeStartPosition;\r
- uint8_t configIndex;\r
- uint16_t sequenceId;\r
- uint8_t bandwidthIndex;\r
- uint8_t combSize; \r
- uint8_t combOffset;\r
- uint8_t cyclicShift;\r
- uint8_t frequencyPosition;\r
- uint8_t frequencyShift;\r
- uint8_t frequencyHopping;\r
- uint8_t groupOrSequenceHopping;\r
- uint8_t resourceType;\r
- uint16_t tSrs;\r
- uint16_t tOffset;\r
- fapi_precoding_bmform_t beamforming;\r
-} fapi_ul_srs_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pduType;\r
- uint16_t pduSize;\r
- union\r
- {\r
- fapi_ul_prach_pdu_t prach_pdu;\r
- fapi_ul_pusch_pdu_t pusch_pdu;\r
- fapi_ul_pucch_pdu_t pucch_pdu;\r
- fapi_ul_srs_pdu_t srs_pdu;\r
- //fapi_ul_rx_bmform_pdu_t rx_beamforming_pdu; //To be defined\r
- };\r
- fapi_ue_info_t ueGrpInfo[MAX_NUMBER_OF_GROUPS_PER_TTI];\r
-} fapi_ul_tti_req_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t nPdus;\r
- uint8_t rachPresent;\r
- uint8_t nUlsch;\r
- uint8_t nUlcch;\r
- uint8_t nGroup;\r
- fapi_ul_tti_req_pdu_t* pdus;\r
-} fapi_ul_tti_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pduType;\r
- uint16_t pduSize;\r
- //fapi_dl_pdcch_pdu_t pdcchPduConfig; //To be defined\r
- } fapi_dci_pdu_t; \r
-\r
- // Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t numPdus;\r
- fapi_dci_pdu_t* pdus;\r
-} fapi_ul_dci_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pduLength;\r
- uint16_t pduIndex;\r
- uint32_t numTlvs;\r
- fapi_uint32_tlv_t tlvs[MAX_NUMBER_OF_TLVS_PER_PDU];\r
-} fapi_tx_pdu_desc_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; \r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint16_t numPdus;\r
- fapi_tx_pdu_desc_t* pduDesc;\r
-} fapi_tx_data_req_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint32_t handle;\r
- uint16_t rnti;\r
- uint8_t harqId;\r
- uint16_t pduLength;\r
- uint8_t ul_cqi;\r
- uint16_t timingAdvance;\r
- uint16_t rssi;\r
- void* pduData;\r
-} fapi_pdu_ind_info_t;\r
- \r
- // Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint16_t numPdus;\r
- fapi_pdu_ind_info_t pdus[MAX_NUMBER_OF_ULSCH_PDUS_PER_TTI];\r
-} fapi_rx_data_indication_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint32_t handle;\r
- uint16_t rnti;\r
- uint8_t harqId;\r
- uint8_t tbCrcStatus;\r
- uint16_t numCb;\r
- uint8_t cbCrcStatus[MAX_NUM_CB_PER_TTI_IN_BYTES];\r
- uint8_t ul_cqi;\r
- uint16_t timingAdvance;\r
- uint16_t rssi;\r
-} fapi_crc_ind_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header; \r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint16_t numCrcs;\r
- fapi_crc_ind_info_t crc[MAX_NUMBER_OF_CRCS_PER_SLOT];\r
-} fapi_crc_ind_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t harqCrc;\r
- uint16_t harqBitLen;\r
- uint8_t harqPayload[MAX_HARQ_INFO_LEN_BYTES];\r
-} fapi_harq_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t csiPart1Crc;\r
- uint16_t csiPart1BitLen;\r
- uint8_t csiPart1Payload[MAX_CSI_PART1_DATA_BYTES];\r
-} fapi_csi_p1_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t csiPart2Crc;\r
- uint16_t csiPart2BitLen;\r
- uint8_t csiPart2Payload[MAX_CSI_PART2_DATA_BYTES];\r
-} fapi_csi_p2_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t pduBitmap;\r
- uint32_t handle;\r
- uint16_t rnti; \r
- uint8_t ul_cqi;\r
- uint16_t timingAdvance; \r
- uint16_t rssi;\r
-// fapi_harq_info_t harqInfo; // This is included if indicated by the pduBitmap\r
-// fapi_csi_p1_info_t csiPart1info; // This is included if indicated by the pduBitmap\r
-// fapi_csi_p2_info_t csiPart2info; // This is included if indicated by the pduBitmap\r
-} fapi_uci_o_pusch_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t srIndication;\r
- uint8_t srConfidenceLevel;\r
-} fapi_sr_f0f1_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t numHarq;\r
- uint8_t harqConfidenceLevel;\r
- uint8_t harqValue[MAX_NUMBER_OF_HARQS_PER_IND];\r
-} fapi_harq_f0f1_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t srBitlen;\r
- uint8_t srPayload[MAX_SR_PAYLOAD_SIZE];\r
-} fapi_sr_f2f3f4_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t harqCrc;\r
- uint16_t harqBitLen;\r
- uint8_t harqPayload[MAX_HARQ_PAYLOAD_SIZE];\r
-} fapi_harq_f2f3f4_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint8_t pduBitmap;\r
- uint32_t handle;\r
- uint16_t rnti;\r
- uint8_t pucchFormat;\r
- uint8_t ul_cqi;\r
- uint16_t timingAdvance;\r
- uint16_t rssi;\r
- // fapi_sr_f2f3f4_info_t srInfo; // This is included if indicated by the pduBitmap\r
- // fapi_harq_f2f3f4_info_t harqInfo; // This is included if indicated by the pduBitmap\r
- // fapi_csi_p1_info_t csiPart1Info; // This is included if indicated by the pduBitmap\r
- // fapi_csi_p2_info_t csiPart2Info; // This is included if indicated by the pduBitmap\r
-} fapi_uci_o_pucch_f2f3f4_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t pduBitmap;\r
- uint32_t handle;\r
- uint16_t rnti;\r
- uint8_t pucchFormat;\r
- uint8_t ul_cqi;\r
- uint16_t timingAdvance;\r
- uint16_t rssi;\r
- // fapi_sr_f0f1_info_t srInfo; // This is included if indicated by the pduBitmap\r
- // fapi_harq_f0f1_info_t harqInfo; // This is included if indicated by the pduBitmap\r
-} fapi_uci_o_pucch_f0f1_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t pduType;\r
- uint16_t pduSize;\r
- union \r
- {\r
- fapi_uci_o_pusch_t uciPusch;\r
- fapi_uci_o_pucch_f0f1_t uciPucchF0F1;\r
- fapi_uci_o_pucch_f2f3f4_t uciPucchF2F3F4;\r
- };\r
-} fapi_uci_pdu_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint16_t numUcis;\r
- fapi_uci_pdu_info_t uciPdu[MAX_NUMBER_UCI_PDUS_PER_SLOT];\r
-} fapi_uci_indication_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint16_t numRbs;\r
- uint8_t rbSNR[MAX_NUMBER_RBS];\r
-} fapi_symb_snr_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint32_t handle;\r
- uint16_t rnti;\r
- uint16_t timingAdvance;\r
- uint8_t numSymbols;\r
- uint8_t wideBandSnr;\r
- uint8_t numReportedSymbols;\r
- fapi_symb_snr_t symbSnr[MAX_NUMBER_OF_REP_SYMBOLS];\r
-} fapi_srs_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t numPdus;\r
- fapi_srs_pdu_t srsPdus[MAX_NUMBER_SRS_PDUS_PER_SLOT];\r
-} fapi_srs_indication_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- uint8_t preambleIndex;\r
- uint16_t timingAdvance;\r
- uint32_t premblePwr;\r
-} fapi_preamble_info_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct { \r
- uint16_t physCellId;\r
- uint8_t symbolIndex;\r
- uint8_t slotIndex;\r
- uint8_t freqIndex;\r
- uint8_t avgRssi;\r
- uint8_t avgSnr;\r
- uint8_t numPreamble;\r
- fapi_preamble_info_t preambleInfo[MAX_NUM_PREAMBLES_PER_SLOT]; \r
-} fapi_rach_pdu_t;\r
-\r
-// Updated per 5G FAPI\r
-typedef struct {\r
- fapi_msg_t header;\r
- uint16_t sfn;\r
- uint16_t slot;\r
- uint8_t numPdus;\r
- fapi_rach_pdu_t rachPdu[MAX_NUMBER_RACH_PDUS_PER_SLOT];\r
-} fapi_rach_indication_t;\r
-\r
-\r
-//------------------------------------------------------------------------------\r
-\r
-#if defined(__cplusplus)\r
-}\r
-#endif\r
-\r
-#endif\r
#include "gen.h"
#include "ssi.h"
#include "cm_hash.h"
+#include "cm_lte.h"
#include "gen.x"
#include "ssi.x"
#include "cm_hash.x"
+#include "cm_lte.x"
#include "cm_lib.x"
#include "du_app_mac_inf.h"
FAPI_CONFIG_REQUEST,
FAPI_CONFIG_RESPONSE,
FAPI_START_REQUEST,
+ FAPI_STOP_REQUEST,
MAX_EVENT
}EventState;
# limitations under the License. #
################################################################################
*******************************************************************************/
+
#include <stdlib.h>
#include <stdint.h>
RETVALUE(ROK);
}
+#ifdef FAPI
/*******************************************************************
*
* @brief Fills FAPI message header
return RFAILED;
}
}
+#endif /* FAPI */
/*******************************************************************
*
* @brief Sends FAPI Param req to PHY
S16 lwr_mac_handleParamReqEvt(void *msg)
{
+#ifdef FAPI
/* startGuardTimer(); */
uint32_t msgLen; //Length of message Body
msgLen = 0;
DU_LOG("\nLOWER MAC: Failed to allocate memory for Param Request");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
/*******************************************************************
S16 lwr_mac_handleParamRspEvt(void *msg)
{
+#ifdef FAPI
/* stopGuardTimer(); */
uint8_t index;
uint32_t encodedVal;
DU_LOG("\nLOWER MAC: Param Response received from PHY is NULL");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
/*******************************************************************
S16 lwr_mac_handleConfigReqEvt(void *msg)
{
+#ifdef FAPI
uint8_t index = 0;
uint32_t msgLen = 0;
uint32_t configReqSize;
DU_LOG("\nLOWER_MAC: Failed to allocate memory for config Request");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
S16 lwr_mac_handleConfigRspEvt(void *msg)
{
+#ifdef FAPI
fapi_config_resp_t *configRsp;
configRsp = (fapi_config_resp_t *)msg;
DU_LOG("\nLOWER MAC: Received EVENT[%d] at STATE[%d]", clGlobalCp.event, clGlobalCp.phyState);
DU_LOG("\nLOWER_MAC: Config Response received from PHY is NULL");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
S16 lwr_mac_handleStartReqEvt(void *msg)
{
+#ifdef FAPi
uint32_t msgLen = 0;
fapi_start_req_t *startReq;
MAC_ALLOC(startReq, sizeof(fapi_start_req_t));
DU_LOG("\nLOWER MAC: Failed to allocate memory for Start Request");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
S16 lwr_mac_handleStopReqEvt(void *msg)
{
+#ifdef FAPI
/* stop TX and RX operation return PHy to configured State
send stop.indication to l2/l3 */
+#else
RETVALUE(ROK);
+#endif
}
/*******************************************************************
DU_LOG("\nLOWER MAC: value filled %x", *val);
}
+#ifdef FAPI
/*******************************************************************
*
* @brief fills SSB PDU required for DL TTI info in MAC
return RFAILED;
}
}
-
+#endif
/*******************************************************************
*
* @brief Sends DL TTI Request to PHY
* ****************************************************************/
S16 handleDlTtiReq(CmLteTimingInfo *dlTtiReqtimingInfo)
{
+#ifdef FAPI
uint32_t msgLen;
fapi_dl_tti_req_t *dlTtiReq;
fapi_dl_tti_req_pdu_t *dlTtiReqPdu;
DU_LOG("\nLOWER MAC: Current TTI Info is NULL");
return RFAILED;
}
+#else
+ return ROK;
+#endif
}
lwrMacFsmHdlr fapiEvtHdlr[MAX_STATE][MAX_EVENT] =
clGlobalCp.event = msgType;
fapiEvtHdlr[clGlobalCp.phyState][clGlobalCp.event](msg);
}
-
/**********************************************************************
End of file
**********************************************************************/
# limitations under the License. #
################################################################################
*******************************************************************************/
+
#ifndef _LWR_MAC_FSM_H_
#define _LWR_MAC_FSM_H_
+
#define FAPI_UINT_8 1
#define FAPI_UINT_16 2
#define FAPI_UINT_32 4
#include "lwr_mac.h"
#include "rg_cl_phy.h"
+
+#ifdef FAPI
#include "fapi.h"
+#endif
S16 lwr_mac_handleInvalidEvt(void *msg);
S16 lwr_mac_handleParamReqEvt(void *msg);
S16 lwr_mac_handleStartReqEvt(void *msg);
S16 lwr_mac_handleStopReqEvt(void *msg);
void sendToLowerMac(U16, U32, void *);
+S16 handleDlTtiReq(CmLteTimingInfo *dlTtiReqtimingInfo);
typedef S16 (*lwrMacFsmHdlr)(void *);
#endif
+/*******************************************************************************
+################################################################################
+# Copyright (c) [2017-2019] [Radisys] #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+################################################################################
+*******************************************************************************/
/* header include files (.h) */
#include "envopt.h" /* environment options */
#include "cm_mblk.h" /* Common LTE Defines */
#include "tfu.h" /* RGU Interface defines */
//#include "rg.h"
+#ifdef FAPI
#include "fapi.h"
+#endif
/* header/extern include files (.x) */
#include "gen.x" /* general */
#include "tfu.x" /* RGU Interface includes */
//#include "rg.x"
+#ifdef FAPI
/* function pointers for packing macCellCfg Request */
typedef S16 (*packSlotIndMsg) ARGS((
Pst *pst,
return (*packSlotIndOpts[pst.selector])(&pst, &slotInd);
}
+#endif
void handlePhyMessages(void *msg)
{
+#ifdef FAPI
/* extract the header */
fapi_msg_t *header;
header = (fapi_msg_t *)msg;
break;
}
}
+#endif
}
+
+/**********************************************************************
+ End of file
+**********************************************************************/
*******************************************************************************/
/* This file contains APIs to send/receive messages from PHY */
+
#include <stdio.h>
#include <stdint.h>
#include "ssi.h"
#include "rg_cl_phy.h"
+#ifdef FAPI
#include "fapi.h"
-
+#endif
EXTERN S16 rgClHndlCfgReq ARGS((void *msg));
EXTERN void processFapiRequest ARGS((uint8_t msgType, uint32_t msgLen, void *msg));
#include "crg.h"
#include "rg.h"
#include "du_log.h"
+#include "lwr_mac.h"
/* header/extern include files (.x) */
#include "gen.x" /* general layer typedefs */
#include "rg_prg.x"
#include "du_app_mac_inf.h"
#include "rg.x"
-#include "fapi_interface.h"
/* This file contains message handling functionality for MAC */
uint16_t MacHdlCellStartReq(Pst *pst, MacCellStartInfo *cellStartInfo)
{
DU_LOG("\nMAC : Handling cell start request");
- //sendToLowerMac(START_REQ, 0, cellStartInfo);
+ sendToLowerMac(FAPI_START_REQUEST, 0, cellStartInfo);
MAC_FREE_MEM(pst->region, pst->pool, cellStartInfo, \
sizeof(MacCellStartInfo));
uint16_t MacHdlCellStopReq(Pst *pst, MacCellStopInfo *cellStopInfo)
{
DU_LOG("\nMAC : Handling cell start request");
- //sendToLowerMac(STOP_REQ, 0, cellStopInfo);
+ sendToLowerMac(FAPI_STOP_REQUEST, 0, cellStopInfo);
MAC_FREE_MEM(pst->region, pst->pool, cellStopInfo, \
sizeof(MacCellStopInfo));
#include "du_app_mac_inf.h"
#include "mac.h"
#include "rg.x" /* typedefs for MAC */
-
+#include "lwr_mac_fsm.h"
#ifdef MAC_RLC_UL_RBUF
#include "ss_rbuf.h"
#include "ss_rbuf.x"
*******************************************************************************/
/*This file contains stub for PHY to handle messages to/from MAC CL */
+
#include <stdint.h>
#include "envdep.h"
#include "rg_cl_phy.h"
#include "lwr_mac.h"
+#ifdef FAPI
#include "fapi.h"
+#endif
#include "lphy_stub.h"
#define MAX_SLOT_VALUE 9
uint16_t sfnValue = 0;
uint16_t slotValue = 0;
EXTERN void phyToMac ARGS((uint16_t msgType, uint32_t msgLen,void *msg));
+#ifdef FAPI
EXTERN void fillTlvs ARGS((fapi_uint16_tlv_t *tlv, uint16_t tag, uint16_t
length, uint16_t value, uint32_t *msgLen));
EXTERN void fillMsgHeader ARGS((fapi_msg_t *hdr, uint16_t msgType, uint16_t msgLen));
+#endif
EXTERN void sendToLowerMac ARGS((uint16_t msgType, uint32_t msgLen,void *msg));
EXTERN void handlePhyMessages ARGS((void *msg));
+
/*******************************************************************
*
* @brief Builds and sends param response to MAC CL
* RFAILED - failure
*
* ****************************************************************/
-S16 l1BldAndSndParamRsp(fapi_param_resp_t *fapiParamRsp)
+S16 l1BldAndSndParamRsp(void *msg)
{
+#ifdef FAPI
uint8_t index = 0;
uint32_t msgLen = 0;
+ fapi_param_resp_t *fapiParamRsp = (fapi_param_resp_t *)msg;
/* Cell Params */
fillTlvs(&fapiParamRsp->tlvs[index++], FAPI_RELEASE_CAPABILITY_TAG, sizeof(uint16_t), 1, &msgLen);
fapiParamRsp->error_code = MSG_OK;
printf("\nPHY_STUB: Sending Param Request to Lower Mac");
sendToLowerMac(fapiParamRsp->header.message_type_id, sizeof(fapi_param_resp_t), (void *)fapiParamRsp);
+#endif
return ROK;
}
*
* ****************************************************************/
-S16 l1BldAndSndConfigRsp(fapi_config_resp_t *fapiConfigRsp)
+S16 l1BldAndSndConfigRsp(void *msg)
{
+#ifdef FAPI
uint8_t index = 0;
uint32_t msgLen = 0;
+ fapi_config_resp_t *fapiConfigRsp = (fapi_config_resp_t *)msg;
if(fapiConfigRsp != NULL)
{
sendToLowerMac(fapiConfigRsp->header.message_type_id, sizeof(fapi_config_resp_t), (void *)fapiConfigRsp);
return ROK;
}
+#else
+ return ROK;
+#endif
}
-
/*******************************************************************
*
* @brief Handles param request received from MAC
PUBLIC void l1HdlParamReq(uint32_t msgLen, void *msg)
{
printf("\nPHY_STUB: Received Param Request in PHY");
-
/* Handling PARAM RESPONSE */
if(l1BldAndSndParamRsp(msg)!= ROK)
{
* ****************************************************************/
PUBLIC void buildAndSendSlotIndication()
{
+#ifdef FAPI
fapi_slot_ind_t *slotIndMsg;
if(SGetSBuf(0, 0, (Data **)&slotIndMsg, sizeof(slotIndMsg)) != ROK)
{
handlePhyMessages((void*)slotIndMsg);
SPutSBuf(0, 0, (Data *)slotIndMsg, sizeof(slotIndMsg));
}
+#endif
}
/*******************************************************************
if(clGlobalCp.phyState == PHY_STATE_CONFIGURED)
{
duStartSlotIndicaion();
+#ifdef FAPI
SPutSBuf(0, 0, (Data *)msg, sizeof(fapi_start_req_t));
-
+#endif
return ROK;
}
else
PUBLIC void l1HdlDlTtiReq(uint16_t msgLen, void *msg)
{
+#ifdef FAPI
fapi_dl_tti_req_t *dlTtiReq;
dlTtiReq = (fapi_dl_tti_req_t *)msg;
printf("\nPHY_STUB: Received DL TTI Request in PHY");
printf("\nPHY_STUB: bchPayload %x", dlTtiReq->pdus->u.ssb_pdu.bchPayload);
SPutSBuf(0, 0, (Data *)dlTtiReq, sizeof(fapi_dl_tti_req_t));
+#endif
return ROK;
}
/*******************************************************************
{
switch(msgType)
{
+#ifdef FAPI
case FAPI_PARAM_REQUEST:
l1HdlParamReq(msgLen, msg);
break;
default:
printf("\nPHY_STUB: Invalid message type[%x] received at PHY", msgType);
break;
+#endif
}
}
/**********************************************************************
-/* This file handles TTI genertion */
+/*******************************************************************************
+################################################################################
+# Copyright (c) [2017-2019] [Radisys] #
+# #
+# Licensed under the Apache License, Version 2.0 (the "License"); #
+# you may not use this file except in compliance with the License. #
+# You may obtain a copy of the License at #
+# #
+# http://www.apache.org/licenses/LICENSE-2.0 #
+# #
+# Unless required by applicable law or agreed to in writing, software #
+# distributed under the License is distributed on an "AS IS" BASIS, #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. #
+# See the License for the specific language governing permissions and #
+# limitations under the License. #
+################################################################################
+*******************************************************************************/
+
+/* This file handles slot indication */
+
#include <stdio.h>
#include <unistd.h>
#include <pthread.h>
}
}
-
+/**********************************************************************
+ End of file
+**********************************************************************/
Code Review / o-du / l2.git / commitdiff