X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2Fdu_app%2Fdu_cfg.h;h=8ee553a55d0aea96fc8b993691f7a13463370809;hb=2bd852089c3226f721d83b30f816b90f803237f6;hp=d48d774767953a8e5f29b1a4d9573ea9adc5e80c;hpb=b5a77f556b20a2acd7d653367fdcac030461f85b;p=o-du%2Fl2.git

diff --git a/src/du_app/du_cfg.h b/src/du_app/du_cfg.h
index d48d77476..8ee553a55 100644
--- a/src/du_app/du_cfg.h
+++ b/src/du_app/du_cfg.h
@@ -28,7 +28,6 @@
 #define DU_ID 1
 
 #ifndef O1_ENABLE
-
 #define DU_IP_V4_ADDR "192.168.130.81"
 #define CU_IP_V4_ADDR "192.168.130.82"
 #define RIC_IP_V4_ADDR "192.168.130.80"
@@ -38,7 +37,7 @@
 #endif
 
 #define DU_EGTP_PORT  39001
-#define CU_EGTP_PORT  39002
+#define CU_EGTP_PORT  39003
 #define NR_PCI 1
 #define NR_CELL_ID 1
 
@@ -88,12 +87,7 @@
 #define NORMAL_CYCLIC_PREFIX 0
 #define OFFSET_TO_POINT_A 24                     /* PRB Offset to Point A */
 #define BETA_PSS BETA_PSS_0DB  
-#define SSB_PERIODICITY_5MS   5
-#define SSB_PERIODICITY_10MS  10
-#define SSB_PERIODICITY_20MS  20
-#define SSB_PERIODICITY_40MS  40
-#define SSB_PERIODICITY_80MS  80
-#define SSB_PERIODICITY_160MS 160
+#define SSB_PERIODICITY 20
 #define SSB_SUBCARRIER_OFFSET 0               
 #define SSB_MULT_CARRIER_BAND FALSE
 #define MULT_CELL_CARRIER FALSE
@@ -118,6 +112,7 @@
 #define NUM_UNUSED_ROOT_SEQ 0
 #define UNUSED_ROOT_SEQ 1
 #define SSB_PER_RACH 1
+#define CB_PREAMBLE_PER_SSB 8
 #define PRACH_MULT_CARRIER_BAND FALSE
 #define PRACH_PREAMBLE_RCVD_TGT_PWR  -74   
 #define NUM_RA_PREAMBLE  63
@@ -240,7 +235,7 @@
 #define SPARE 0
 #define SSB_SC_OFFSET 0
 #define DU_RANAC 1
-#define CELL_IDENTITY 16
+#define CELL_IDENTITY 1
 
 /* Macro definitions for DUtoCuRrcContainer */
 #define CELL_GRP_ID 0
@@ -301,6 +296,24 @@
 #define DEDICATED_RATIO  10
 #define NUM_OF_SUPPORTED_SLICE  2
 
+#ifdef NR_DRX
+/* Macros for Drx configuration */
+#define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
+#define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 1
+#define DRX_INACTIVITY_TIMER 2
+#define DRX_HARQ_RTT_TIMER_DL 56
+#define DRX_HARQ_RTT_TIMER_UL 56
+#define DRX_RETRANSMISSION_TIMER_DL 4
+#define DRX_RETRANSMISSION_TIMER_UL 4
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 20
+#define DRX_LONG_CYCLE_START_OFFSET_VAL 8
+#define DRX_SHORT_CYCLE_PRESENT true
+#define DRX_SHORT_CYCLE 2
+#define DRX_SHORT_CYCLE_TIMER 2
+#define DRX_SLOT_OFFSET 0
+#endif
+
 typedef enum
 {
    GNBDU,
@@ -1149,8 +1162,8 @@ typedef struct rachCfgCommon
    long   pwrRampingStep;    /* Power ramping steps for PRACH */
    long   raRspWindow;       /* RA response window */
    long   numRaPreamble;     /* Total num of preamble used in random access */
-   uint8_t ssbPerRachOccPresent;
    long   numSsbPerRachOcc;  /* Numer of SSBs per RACH Occassion */
+   long   numCbPreamblePerSsb; /* Number of Contention-Based preamble per SSB */
    long   contResTimer;      /* Contention resolution timer */
    long   rsrpThreshSsb;
    uint8_t rootSeqIdxPresent;
@@ -1185,6 +1198,7 @@ typedef struct pucchCfgCommon
 
 typedef struct ulCfgCommon
 {
+   long   freqBandInd;  /* Uplink frequency band indicator */
    long   pMax;         /* Max UL transmission power that UE applies */
    long   locAndBw;     /* Frequency location and bandwidth */
    ScsSpecCarrier   ulScsCarrier; /* SCS Specific carrier */
@@ -1206,6 +1220,7 @@ typedef struct tddUlDlCfgCommon
 
 typedef struct srvCellCfgCommSib
 { 
+   long               scs;
    DlCfgCommon        dlCfg;
    UlCfgCommon        ulCfg;
    uint8_t            ssbPosInBurst;