X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2Fcu_stub%2Fcu_f1ap_msg_hdl.c;h=435f2a24293e89b96607332197abe5519c5fef7c;hb=41eaaec52d3fe0d5c003e6c0676e9a18fc8ba37a;hp=3b8ac6ef5d1916199681ea23e964b42abbe67221;hpb=2bd852089c3226f721d83b30f816b90f803237f6;p=o-du%2Fl2.git diff --git a/src/cu_stub/cu_f1ap_msg_hdl.c b/src/cu_stub/cu_f1ap_msg_hdl.c index 3b8ac6ef5..435f2a242 100644 --- a/src/cu_stub/cu_f1ap_msg_hdl.c +++ b/src/cu_stub/cu_f1ap_msg_hdl.c @@ -1514,8 +1514,27 @@ uint8_t BuildDLRRCContainer(CuUeCb *ueCb, uint8_t rrcMsgType, RRCContainer_t *rr } else if(rrcMsgType == RRC_SETUP_COMPLETE) { - DU_LOG("\nINFO --> F1AP : Sending Security mode command"); - char secModeBuf[9]={0x00, 0x02, 0x22, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}; + DU_LOG("\nINFO --> F1AP : Sending NAS Security mode command"); + char secModeBuf[30]={0x00, 0x02, 0x2e, 0x82, 0xaf, 0xc0, 0x7d, 0x1c, 0x4e, 0xfc, 0x80, 0x0f, 0xc0, + 0x0b, 0xa0, 0x20, 0x40, 0x9e, 0x0e, 0x1e, 0x0e, 0x1c, 0x26, 0xc0, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00}; + bufLen =30; + rrcContainer->size = bufLen; + CU_ALLOC(rrcContainer->buf, rrcContainer->size); + if(rrcContainer->buf != NULLP) + { + memset(rrcContainer->buf, 0, bufLen); + memcpy(rrcContainer->buf, secModeBuf, bufLen); + } + else + { + DU_LOG("\nERROR --> F1AP : Memory allocation failure for RRC Container buffer"); + ret = RFAILED; + } + } + else if(rrcMsgType == NAS_SECURITY_MODE_COMPLETE) + { + DU_LOG("\nINFO --> F1AP : Sending RRC Security mode command"); + char secModeBuf[9]={0x00, 0x03, 0x22, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}; bufLen =9; rrcContainer->size = bufLen; CU_ALLOC(rrcContainer->buf, rrcContainer->size); @@ -1530,11 +1549,11 @@ uint8_t BuildDLRRCContainer(CuUeCb *ueCb, uint8_t rrcMsgType, RRCContainer_t *rr ret = RFAILED; } } - else if(rrcMsgType == SECURITY_MODE_COMPLETE) + else if(rrcMsgType == RRC_SECURITY_MODE_COMPLETE) { /*Hardcoded RRC Container from reference logs*/ DU_LOG("\nINFO --> F1AP : Sending Registration accept"); - char buf[14] ={0x00, 0x03, 0x2a, 0x80, 0xaf, 0xc0, 0x08, 0x40, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00}; + char buf[14] ={0x00, 0x04, 0x2a, 0x80, 0xaf, 0xc0, 0x08, 0x40, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00}; bufLen =14; rrcContainer->size = bufLen; CU_ALLOC(rrcContainer->buf, rrcContainer->size); @@ -1768,8 +1787,11 @@ uint8_t setDlRRCMsgType(CuUeCb *ueCb) case RRC_SETUP_COMPLETE: rrcMsgType = RRC_SETUP_COMPLETE; break; - case SECURITY_MODE_COMPLETE: - rrcMsgType = SECURITY_MODE_COMPLETE; + case NAS_SECURITY_MODE_COMPLETE: + rrcMsgType = NAS_SECURITY_MODE_COMPLETE; + break; + case RRC_SECURITY_MODE_COMPLETE: + rrcMsgType = RRC_SECURITY_MODE_COMPLETE; break; case REGISTRATION_COMPLETE: rrcMsgType = REGISTRATION_COMPLETE; @@ -1804,108 +1826,108 @@ uint8_t setDlRRCMsgType(CuUeCb *ueCb) * RFAILED - failure * * ****************************************************************/ -void fillLongCycleOffsetValue(DrxLongCycleStartOffset *drxLongCycleStartOffset, struct DRX_ConfigRrc__recvedLongCycleOffsetVal *recvedLongCycleOffsetVal) +void fillLongCycleOffsetValue(DrxLongCycleStartOffset *drxLongCycleStartOffset, struct DRX_ConfigRrc__drx_LongCycleStartOffset *recvedLongCycleOffsetVal) { drxLongCycleStartOffset->drxLongCycleStartOffsetChoice = recvedLongCycleOffsetVal->present; switch(recvedLongCycleOffsetVal->present) { - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms10: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms10: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms10; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms20: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms20: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms20; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms32: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms32: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms32; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms40: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms40: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms40; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms60: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms60: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms60; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms64: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms64: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms64; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms70: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms70: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms70; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms80: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms80: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms80; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms128: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms128: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms128; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms160: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms160: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms160; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms256: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms256: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms256; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms320: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms320: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms320; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms512: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms512: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms512; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms640: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms640: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms640; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms1024: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms1024: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms1024; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms1280: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms1280: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms1280; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms2048: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms2048: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms2048; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms2560: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms2560: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms2560; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms5120: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms5120: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms5120; break; } - case DRX_ConfigRrc__recvedLongCycleOffsetVal_PR_ms10240: + case DRX_ConfigRrc__drx_LongCycleStartOffset_PR_ms10240: { drxLongCycleStartOffset->drxLongCycleStartOffsetVal = recvedLongCycleOffsetVal->choice.ms10240; break; @@ -1932,25 +1954,22 @@ void fillLongCycleOffsetValue(DrxLongCycleStartOffset *drxLongCycleStartOffset, * ****************************************************************/ void storeDrxCfgInUeCb(struct DRX_ConfigRrc *drxSetup, DrxCfg *drxCfg) { - if(drxSetup) + switch(drxSetup->drx_onDurationTimer.present) { - switch(drxSetup->drx_onDurationTimer.present) - { - case DRX_ConfigRrc__drx_onDurationTimer_PR_NOTHING: + case DRX_ConfigRrc__drx_onDurationTimer_PR_NOTHING: + break; + case DRX_ConfigRrc__drx_onDurationTimer_PR_milliSeconds: + { + drxCfg->drxOnDurationTimer.onDurationTimerValInMs = true; + drxCfg->drxOnDurationTimer.onDurationtimerValue.milliSeconds=drxSetup->drx_onDurationTimer.choice.milliSeconds; break; - case DRX_ConfigRrc__drx_onDurationTimer_PR_milliSeconds: - { - drxCfg->drxOnDurationTimer.onDurationTimerValInMs = true; - drxCfg->drxOnDurationTimer.onDurationtimerValue.milliSeconds=drxSetup->drx_onDurationTimer.choice.milliSeconds; - break; - } - case DRX_ConfigRrc__drx_onDurationTimer_PR_subMilliSeconds: - { - drxCfg->drxOnDurationTimer.onDurationTimerValInMs = false; - drxCfg->drxOnDurationTimer.onDurationtimerValue.subMilliSeconds = drxSetup->drx_onDurationTimer.choice.subMilliSeconds; - break; - } - } + } + case DRX_ConfigRrc__drx_onDurationTimer_PR_subMilliSeconds: + { + drxCfg->drxOnDurationTimer.onDurationTimerValInMs = false; + drxCfg->drxOnDurationTimer.onDurationtimerValue.subMilliSeconds = drxSetup->drx_onDurationTimer.choice.subMilliSeconds; + break; + } } fillLongCycleOffsetValue(&drxCfg->drxLongCycleStartOffset, &drxSetup->drx_LongCycleStartOffset); drxCfg->drxInactivityTimer = drxSetup->drx_InactivityTimer; @@ -2027,7 +2046,11 @@ uint8_t extractCellGroupConfig(CuUeCb *ueCb, CellGroupConfigRrc_t *cellGrpCfg) case MAC_CellGroupConfig__drx_ConfigRrc_PR_setup: { - storeDrxCfgInUeCb(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc->choice.setup, &ueCb->drxCfg); + if(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc->choice.setup) + { + ueCb->drxCfgPresent = true; + storeDrxCfgInUeCb(cellGrpCfg->mac_CellGroupConfig->drx_ConfigRrc->choice.setup, &ueCb->drxCfg); + } break; } @@ -9772,10 +9795,15 @@ uint8_t procUlRrcMsg(uint32_t duId, F1AP_PDU_t *f1apMsg) rrcMsgType = setDlRRCMsgType(ueCb); if(rrcMsgType == RRC_SETUP_COMPLETE) { - DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for Security Mode Command"); + DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for NAS Security Mode Command"); + ret = BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType); + } + if(rrcMsgType == NAS_SECURITY_MODE_COMPLETE) + { + DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for RRC Security Mode Command"); ret = BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType); } - else if(rrcMsgType == SECURITY_MODE_COMPLETE) + else if(rrcMsgType == RRC_SECURITY_MODE_COMPLETE) { DU_LOG("\nINFO --> F1AP: Sending DL RRC MSG for RRC Registration Accept"); BuildAndSendDLRRCMessageTransfer(duId, ueCb, srbId, rrcMsgType); @@ -10917,7 +10945,11 @@ uint8_t BuildAndSendUeContextModificationReq(uint32_t duId, void *cuUeCb, UeCtxt elementCnt = 3; else if((action == STOP_DATA_TX) || (action == RESTART_DATA_TX)) elementCnt = 5; - + +#ifdef NR_DRX + if(DRX_TO_BE_RELEASE && ueCb->drxCfgPresent) + elementCnt++; +#endif ueContextModifyReq->protocolIEs.list.count = elementCnt; ueContextModifyReq->protocolIEs.list.size = elementCnt*sizeof(UEContextModificationRequest_t *); @@ -11043,6 +11075,20 @@ uint8_t BuildAndSendUeContextModificationReq(uint32_t duId, void *cuUeCb, UeCtxt ueContextModifyReq->protocolIEs.list.array[ieIdx]->value.choice.RRCDeliveryStatusRequest = RRCDeliveryStatusRequest_true; } +#ifdef NR_DRX + if(DRX_TO_BE_RELEASE && ueCb->drxCfgPresent) + { + /* DRX Configuration Indicator */ + ieIdx++; + ueContextModifyReq->protocolIEs.list.array[ieIdx]->id = ProtocolIE_ID_id_DRXConfigurationIndicator; + ueContextModifyReq->protocolIEs.list.array[ieIdx]->criticality = Criticality_ignore; + ueContextModifyReq->protocolIEs.list.array[ieIdx]->value.present = UEContextModificationRequestIEs__value_PR_DRXConfigurationIndicator; + ueContextModifyReq->protocolIEs.list.array[ieIdx]->value.choice.DRXConfigurationIndicator = DRXConfigurationIndicator_release; + ueCb->drxCfgPresent = false; + memset(&ueCb->drxCfg, 0, sizeof(DrxCfg)); + } +#endif + xer_fprint(stdout, &asn_DEF_F1AP_PDU, f1apMsg); /* Encode the F1SetupRequest type as APER */