X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2Fcm%2Frgr.x;h=58552aa17f666114902d5c563690ce94b1c64890;hb=112672aee2b176d420e1474b13a5655c3d1e92b4;hp=7987f8c6a30f251197e516c171ef5d864de0dbc2;hpb=5625a52ad68f6ad93684e68bbbdbaef0d462cf9a;p=o-du%2Fl2.git diff --git a/src/cm/rgr.x b/src/cm/rgr.x index 7987f8c6a..58552aa17 100755 --- a/src/cm/rgr.x +++ b/src/cm/rgr.x @@ -247,7 +247,7 @@ typedef enum _rgrSiPerd RGR_SI_PERD_512 = 512 /**< SI Periodicity 512 RF */ } RgrSiPeriodicity; -/*rgr_x_001.main_11 ccpu00115364 ADD changed U8 to enum for modPrd*/ +/*rgr_x_001.main_11 ccpu00115364 ADD changed uint8_t to enum for modPrd*/ /*modification period = (modificationPeriodCoeff * defaultPagingCycle)%m*/ /*where modificationPeriodCoeff={2,4,8,16} defaultPagingCycle={32,64,128,256}*/ /** @@ -404,16 +404,16 @@ typedef enum rgrSchFrmt1b3TypEnum /** @brief Transaction ID between MAC and RRM */ typedef struct rgrCfgTransId { - U8 trans[RGR_CFG_TRANSID_SIZE]; /*!< RRM Transaction ID */ + uint8_t trans[RGR_CFG_TRANSID_SIZE]; /*!< RRM Transaction ID */ } RgrCfgTransId; /** @brief Downlink HARQ configuration per Cell */ typedef struct rgrDlHqCfg { - U8 maxDlHqTx; /*!< Maximum number of DL HARQ Transmissions. + uint8_t maxDlHqTx; /*!< Maximum number of DL HARQ Transmissions. Minimum value is 1, maximum can be defined by the user */ - U8 maxMsg4HqTx; /*!< Maximum msg4(Random Access) HARQ Transmissions + uint8_t maxMsg4HqTx; /*!< Maximum msg4(Random Access) HARQ Transmissions Minimum value is 1, Maximum can be defined by the user */ } RgrDlHqCfg; @@ -422,21 +422,21 @@ typedef struct rgrDlHqCfg typedef struct rgrRntiCfg { CmLteRnti startRnti; /*!< Start RNTI for the range managed by MAC */ - U16 size; /*!< Indicates contiguous range of RNTI managed by + uint16_t size; /*!< Indicates contiguous range of RNTI managed by MAC */ } RgrRntiCfg; /** @brief Downlink common channel code rate configuration per cell */ typedef struct rgrDlCmnCodeRateCfg { - U16 bcchPchRaCodeRate; /*!< BCCH on DLSCH, PCH and RARsp coding rate. + uint16_t bcchPchRaCodeRate; /*!< BCCH on DLSCH, PCH and RARsp coding rate. * This defines the actual number of bits per 1024 * physical layer bits */ - U16 pdcchCodeRate; /*!< PDCCH code rate defines actual number of bits + uint16_t pdcchCodeRate; /*!< PDCCH code rate defines actual number of bits * per 1024 physical layer bits. This is used to * calculate aggregation level for PDCCH meant * for broadcasting RNTIs */ - U8 ccchCqi; /*!< Default CQI to be used for Msg4 in case where + uint8_t ccchCqi; /*!< Default CQI to be used for Msg4 in case where * no CQI is available for the UE. ccchCqi ranges * from 1 to 15.*/ } RgrDlCmnCodeRateCfg; @@ -444,22 +444,22 @@ typedef struct rgrDlCmnCodeRateCfg /** @brief Control Format Indicator (CFI) configuration per cell */ typedef struct rgrCfiCfg { - U8 cfi; /*!< CFI for PDCCH: a value in set {1,2,3} */ + uint8_t cfi; /*!< CFI for PDCCH: a value in set {1,2,3} */ } RgrCfiCfg; /** @brief PUSCH sub-band configuration per cell */ typedef struct rgrPuschSubBandCfg { - U8 subbandStart; /*!< Sub-band start */ - U8 numSubbands; /*!< Number of equal sized sub-bands */ - U8 size; /*!< Size of a sub-band */ - U8 dmrs[RGR_MAX_SUBBANDS]; /*!< DMRS information per sub-band */ + uint8_t subbandStart; /*!< Sub-band start */ + uint8_t numSubbands; /*!< Number of equal sized sub-bands */ + uint8_t size; /*!< Size of a sub-band */ + uint8_t dmrs[RGR_MAX_SUBBANDS]; /*!< DMRS information per sub-band */ } RgrPuschSubBandCfg; /** @brief Uplink common channel code rate configuration per cell */ typedef struct rgrUlCmnCodeRateCfg { - U8 ccchCqi; /*!< CCCH CQI index, also used as default + uint8_t ccchCqi; /*!< CCCH CQI index, also used as default * initial CQI for UEs */ } RgrUlCmnCodeRateCfg; @@ -468,15 +468,15 @@ typedef struct rgrUlCmnCodeRateCfg /** @brief Target Uplink CQI to achieve through group power control configured per cell */ typedef struct rgrUlTrgCqiCfg { - U8 trgCqi; /*!< Target UL CQI to be achieved through power + uint8_t trgCqi; /*!< Target UL CQI to be achieved through power control.Range is defined is between 1 to 15 */ } RgrUlTrgCqiCfg; /** @brief Bandwidth configuration per cell */ typedef struct rgrBwCfg { - U8 dlTotalBw; /*!< Total Dowlink Bandwidth */ - U8 ulTotalBw; /*!< Total Uplink Bandwidth */ + uint8_t dlTotalBw; /*!< Total Dowlink Bandwidth */ + uint8_t ulTotalBw; /*!< Total Uplink Bandwidth */ } RgrBwCfg; /** @@ -491,12 +491,12 @@ typedef struct rgrPhichCfg @brief PUCCH configuration per cell */ typedef struct rgrPucchCfg { - U8 resourceSize; /*!< PUCCH resource-size or N^(2)_RB (in RBs) */ - U16 n1PucchAn; /*!< N^(1)_PUCCH */ - U8 deltaShift; /*!< Delta Shift for PUCCH: a value in set {1,2,3} */ - U8 cyclicShift; /*!< Cyclic Shift for PUCCH (N^(1)_CS): a value in + uint8_t resourceSize; /*!< PUCCH resource-size or N^(2)_RB (in RBs) */ + uint16_t n1PucchAn; /*!< N^(1)_PUCCH */ + uint8_t deltaShift; /*!< Delta Shift for PUCCH: a value in set {1,2,3} */ + uint8_t cyclicShift; /*!< Cyclic Shift for PUCCH (N^(1)_CS): a value in range [0-7] */ - U8 maxPucchRb; /*!< The max number of RBs for PUCCH. This will be + uint8_t maxPucchRb; /*!< The max number of RBs for PUCCH. This will be used to limit the max CFI value when dynamic CFI feature is enabled. If there is no limitation on the max PUCCH RBs, this variable @@ -511,32 +511,32 @@ typedef struct rgrSrsCfg RgrSrsCfgPrd srsCfgPrdEnum; /*!< SRS configuration period (in subframes).*/ RgrSrsBwCfg srsBwEnum; /*!< SRS Bandwidth configuration per cell. Range - [0-7] */ - U8 srsSubFrameCfg;/*!< SRS subframe configuration index per cell. + uint8_t srsSubFrameCfg;/*!< SRS subframe configuration index per cell. Range - [0-15] */ } RgrSrsCfg; /** @brief RACH configuration per cell */ typedef struct rgrRachCfg { - U8 preambleFormat; /*!< RACH Preamble format: a value in set {0,1,2,3} */ - U8 raWinSize; /*!< RA Window size */ + uint8_t preambleFormat; /*!< RACH Preamble format: a value in set {0,1,2,3} */ + uint8_t raWinSize; /*!< RA Window size */ /** @brief Ocassion at Which Random Access Is Expected */ struct raOccasionS { - U8 size; /*!< Number of subframe numbers */ + uint8_t size; /*!< Number of subframe numbers */ RgrRaSfn sfnEnum; /*!< System Frame Number */ - U8 subFrameNum[RGR_MAX_SUBFRAME_NUM]; /*!< Subframe numbers */ + uint8_t subFrameNum[RGR_MAX_SUBFRAME_NUM]; /*!< Subframe numbers */ } raOccasion; /*!< Random access occasions */ - U8 maxMsg3Tx; /*!< Maximum number of message 3 transmissions */ - U8 numRaPreamble; /*!< Number of RA Preambles */ - U8 sizeRaPreambleGrpA; /*!< Size of RA Preamble in Group A */ - U16 msgSizeGrpA; /*!< MESSAGE_SIZE_GROUP_A */ - U8 prachResource; /*!< N^RA_PRB: PRACH resource for random access */ + uint8_t maxMsg3Tx; /*!< Maximum number of message 3 transmissions */ + uint8_t numRaPreamble; /*!< Number of RA Preambles */ + uint8_t sizeRaPreambleGrpA; /*!< Size of RA Preamble in Group A */ + uint16_t msgSizeGrpA; /*!< MESSAGE_SIZE_GROUP_A */ + uint8_t prachResource; /*!< N^RA_PRB: PRACH resource for random access */ /**@name RGR_V1 */ /**@{ */ #ifdef RGR_V1 /* rgr_x_001.main_7: [ccpu00112372] Added contention resolution timer */ - U8 contResTmr; /*!< Contention resolution timer */ + uint8_t contResTmr; /*!< Contention resolution timer */ #endif /**@} */ } RgrRachCfg; @@ -546,17 +546,17 @@ typedef struct rgrRachCfg */ typedef struct rgrSiCfg { - U8 siWinSize; /*!< SI window size */ - U8 retxCnt; /*!< Retransmission count */ + uint8_t siWinSize; /*!< SI window size */ + uint8_t retxCnt; /*!< Retransmission count */ /* rgr_x_001.main_5-ADD-Added for SI Enhancement. */ /**@name RGR_SI_SCH */ /**@{ */ #ifdef RGR_SI_SCH -/*rgr_x_001.main_11 ccpu00115364 MOD changed U8 to enum for modPrd*/ +/*rgr_x_001.main_11 ccpu00115364 MOD changed uint8_t to enum for modPrd*/ RgrModPeriodicity modPrd; /*!< Modificiation Period for SI */ - U8 numSi; /*! 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + uint16_t pcchTxPwrOffset; /*!< Tx Pwr Offset for PCCH tx. + Offset to the reference signal + power. Value: 0 -> 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + uint16_t rarTxPwrOffset; /*!< Tx Pwr Offset for RAR tx. + Offset to the reference signal + power. Value: 0 -> 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + uint8_t nrMu; /*! 6Ghz)*/ + RgrType0PdcchCSSCfg type0PdcchCSSCfg; /*!< Type 0 CSS Config params */ + RgrFreqInfoDlCfg freqInfoDlCfg; /*!< DL Frequency information + config */ + RgrSulCellCfg sulCellCfg; /*!< SUL Cell config */ + RgrUlCfgCmn ulCmnCfg; /*!< initial UL Bwp and Ul freq + information */ +#endif + Bool initDlBwpPres; /*!< intial common + DL BWP is present or not */ + RgrBwpDlCmn initDlBwp; /*! 10000, representing -6 dB to 4 dB in 0.001 dB steps */ - U16 pcchTxPwrOffset; /*!< Tx Pwr Offset for PCCH tx. + uint16_t pcchTxPwrOffset; /*!< Tx Pwr Offset for PCCH tx. Offset to the reference signal power. Value: 0 -> 10000, representing -6 dB to 4 dB in 0.001 dB steps */ - U16 rarTxPwrOffset; /*!< Tx Pwr Offset for RAR tx. + uint16_t rarTxPwrOffset; /*!< Tx Pwr Offset for RAR tx. Offset to the reference signal power. Value: 0 -> 10000, representing -6 dB to 4 dB in 0.001 dB steps */ /* ccpu00138898 - Added Tx pwr offset for PHICH Tx*/ - U16 phichTxPwrOffset; /*!< Tx Pwr Offset for PHICH tx. + uint16_t phichTxPwrOffset; /*!< Tx Pwr Offset for PHICH tx. Offset to the reference signal power. Value: 0 -> 10000, representing -6 dB to 4 dB in 0.001 @@ -1216,6 +1335,7 @@ typedef struct rgrCellCfg #ifdef RG_5GTF Rgr5gtfCellCfg Cell5gtfCfg; #endif +#endif } RgrCellCfg; /** @brief Downlink Aperiodic CQI reporting related configuration per UE */ @@ -1226,8 +1346,8 @@ typedef struct rgrUeAprdDlCqiCfg RgrAprdCqiMode aprdModeEnum; /*!< Aperiodic CQI reporting mode */ /* These two fields are only valid for Pcell*/ #ifdef LTE_ADV - U8 triggerSet1; /*!< Trigger set one*/ - U8 triggerSet2; /*!< Trigger set two*/ + uint8_t triggerSet1; /*!< Trigger set one*/ + uint8_t triggerSet2; /*!< Trigger set two*/ #endif } RgrUeAprdDlCqiCfg; @@ -1242,12 +1362,12 @@ typedef struct rgrUePrdDlCqiCfg RgrPrdCqiMode prdModeEnum; /*!< Peiodic CQI reporting mode. */ RgrCqiPrdicity prdicityEnum; /*!< Periodicity values for CQI. Currently, this is unused parameter. */ - U8 subframeOffst; /*!< Subframe offset. + uint8_t subframeOffst; /*!< Subframe offset. Currently, this is unused parameter. */ S8 cqiOffst; /*!< Delta^cqi_offset: (actual_value*10). Currently, this is unused parameter. */ - U8 k; /*!< k value: range [1-4] */ - U16 cqiPmiCfgIdx; /*!< CQI-PMI configuration index. */ + uint8_t k; /*!< k value: range [1-4] */ + uint16_t cqiPmiCfgIdx; /*!< CQI-PMI configuration index. */ } RgrUePrdDlCqiCfg; #else /* TFU_UPGRADE */ @@ -1258,13 +1378,13 @@ typedef struct rgrUePrdDlCqiCfg /* Reference: 36.313: CQI-ReportPeriodic */ typedef struct rgrUeDlPCqiSetup { - U16 cqiPResIdx; /*!< cqi-PUCCH-ResourceIndex (0.. 1185) */ - U16 cqiPCfgIdx; /*!< cqi-pmi-ConfigIndex (0..1023) */ - U8 cqiRepType; /*!< Wideband CQI = 1 Subband CQI =2 */ - U8 k; /*!< Ref: 36.213 [23, 7.2.2] (1..4). + uint16_t cqiPResIdx; /*!< cqi-PUCCH-ResourceIndex (0.. 1185) */ + uint16_t cqiPCfgIdx; /*!< cqi-pmi-ConfigIndex (0..1023) */ + uint8_t cqiRepType; /*!< Wideband CQI = 1 Subband CQI =2 */ + uint8_t k; /*!< Ref: 36.213 [23, 7.2.2] (1..4). Valid only for Subband CQI */ - U8 riEna; /*!< Rand Indicator is Enabled TRUE(1) FALSE(0) */ - U16 riCfgIdx; /*!< ri-ConfigIndex (0..1023) */ + uint8_t riEna; /*!< Rand Indicator is Enabled TRUE(1) FALSE(0) */ + uint16_t riCfgIdx; /*!< ri-ConfigIndex (0..1023) */ Bool sANCQI; /*!< simultaneousAckNackAndCQI TRUE(1) FALSE(0) */ RgrPrdCqiMode prdModeEnum; /*!< Peiodic CQI reporting mode */ }RgrUeDlPCqiSetup; @@ -1275,7 +1395,7 @@ typedef struct rgrUeDlPCqiSetup */ typedef struct rgrUeDlPCqiCfg { - U8 type; /*!< Setup(1) or Release(0) */ + uint8_t type; /*!< Setup(1) or Release(0) */ RgrUeDlPCqiSetup cqiSetup; /*!< Periodic CQI Setup */ } RgrUePrdDlCqiCfg; @@ -1330,7 +1450,7 @@ typedef enum rgrUlSrsCycShiftInfo */ typedef struct rgrUeUlSrsSetupCfg { - U16 srsCfgIdx; /*!< SRS Configuration Index ISRS + uint16_t srsCfgIdx; /*!< SRS Configuration Index ISRS Ref: 36.213: Table 8.2-1; Range: 0-636*/ RgrUlSrsBwInfo srsBw; /*!< SRS Bandwidth */ RgrUlSrsHoBwInfo srsHopBw; /*!< SRS Hoping Bandwidth */ @@ -1345,8 +1465,8 @@ typedef struct rgrUeUlSrsSetupCfg same value for all the UEs configured for the same cell. */ /* rgr_x_001.main_13 - DEL - Removed the redeclaration of sANSrs and added the proper comment termination above */ - U8 txComb; /*!< Tranmission Comb: 0..1 */ - U8 fDomPosi; /*!< Frequency Domain Position */ + uint8_t txComb; /*!< Tranmission Comb: 0..1 */ + uint8_t fDomPosi; /*!< Frequency Domain Position */ }RgrUeUlSrsSetupCfg; @@ -1368,8 +1488,8 @@ typedef enum rgrUeDsrTransMax */ typedef struct rgrUeSrSetupCfg { - U16 srResIdx; /*!< Range: 0-2047; Reference: SchedulingRequestConfig */ - U8 srCfgIdx; /*!< Range: 0 -155; Reference: SchedulingRequestConfig */ + uint16_t srResIdx; /*!< Range: 0-2047; Reference: SchedulingRequestConfig */ + uint8_t srCfgIdx; /*!< Range: 0 -155; Reference: SchedulingRequestConfig */ /*ccpu00131601:DEL - dTMax will not be required by scheduler */ }RgrUeSrSetupCfg; @@ -1387,7 +1507,7 @@ typedef struct rgrUeSrCfg */ typedef struct rgrUeUlSrsCfg { - U8 type; /*!< Release=0 Setup =1 */ + uint8_t type; /*!< Release=0 Setup =1 */ RgrUeUlSrsSetupCfg srsSetup; /*!< SRS Setup Configuration */ }RgrUeUlSrsCfg; @@ -1397,17 +1517,17 @@ typedef struct rgrUeUlSrsCfg #ifdef LTE_ADV/* Sprint 3*/ typedef struct rgrUePucchFormat3Cfg { - U8 sCellAckN3ResAntP0Count; - U8 sCellAckN3ResAntP1Count; - U16 sCellAckN3ResAntP0[4]; - U16 sCellAckN3ResAntP1[4]; + uint8_t sCellAckN3ResAntP0Count; + uint8_t sCellAckN3ResAntP1Count; + uint16_t sCellAckN3ResAntP0[4]; + uint16_t sCellAckN3ResAntP1[4]; }RgrUePucchFormat3Cfg; typedef struct rgrUePucchFormat1BCSCfg { - U8 sCellAckN1ResTb1Count; /* !< num of N1 res for TB1 */ - U8 sCellAckN1ResTb2Count; /* !< num of N1 res for TB2 */ - U16 sCellAckN1ResTb1[4]; /*!< TB1 N1 resources */ - U16 sCellAckN1ResTb2[4]; /* !< TB2 N1 resources */ + uint8_t sCellAckN1ResTb1Count; /* !< num of N1 res for TB1 */ + uint8_t sCellAckN1ResTb2Count; /* !< num of N1 res for TB2 */ + uint16_t sCellAckN1ResTb1[4]; /*!< TB1 N1 resources */ + uint16_t sCellAckN1ResTb2[4]; /* !< TB2 N1 resources */ }RgrUePucchFormat1BCSCfg; typedef struct rgrUeSCellAckPucchCfg { @@ -1429,9 +1549,9 @@ typedef struct rgrUeSCellAckPucchCfg typedef struct rgrUePuschDedCfg { Bool pres; /*! Prsent TRUE(1)/FALSE(0) */ - U8 bACKIdx; /*! betaOffset-ACK-Index (0..15) */ - U8 bRIIdx; /*! betaOffset-RI-Index (0..15) */ - U8 bCQIIdx; /*! betaOffset-CQI-Index (0..15) */ + uint8_t bACKIdx; /*! betaOffset-ACK-Index (0..15) */ + uint8_t bRIIdx; /*! betaOffset-RI-Index (0..15) */ + uint8_t bCQIIdx; /*! betaOffset-CQI-Index (0..15) */ }RgrUePuschDedCfg; /** * @brief Downlink CQI reporting related configuration per UE @@ -1447,15 +1567,15 @@ typedef struct rgrUeDlCqiCfg typedef struct rgrUeMeasGapCfg { Bool isMesGapEnabled; /*!< Is Measuremnet Gap enabled or disabled */ - U8 gapPrd; /*!< Gap period 40ms/80ms */ - U8 gapOffst; /*!< Gap offset - Vaue is 0 to 1*/ + uint8_t gapPrd; /*!< Gap period 40ms/80ms */ + uint8_t gapOffst; /*!< Gap offset - Vaue is 0 to 1*/ } RgrUeMeasGapCfg; /** @brief DRX Long Cycle Offset */ typedef struct rgrDrxLongCycleOffst { - U16 longDrxCycle; /*!< DRX Long Cycle value in subframes*/ - U16 drxStartOffst; /*!< DRX Long Cycle offset value in subframes*/ + uint16_t longDrxCycle; /*!< DRX Long Cycle value in subframes*/ + uint16_t drxStartOffst; /*!< DRX Long Cycle offset value in subframes*/ } RgrDrxLongCycleOffst; /** @@ -1463,8 +1583,8 @@ typedef struct rgrDrxLongCycleOffst typedef struct rgrDrxShortDrx { Bool pres; /*!< Short cycle is configured or not */ - U16 shortDrxCycle; /*!< DRX Short Cycle value in sub-frames*/ - U8 drxShortCycleTmr; /*!< Value in multiples of Short DRX Cycles*/ + uint16_t shortDrxCycle; /*!< DRX Short Cycle value in sub-frames*/ + uint8_t drxShortCycleTmr; /*!< Value in multiples of Short DRX Cycles*/ } RgrDrxShortDrx; /** @@ -1483,16 +1603,16 @@ typedef struct rgrUeDrxCfg only a enum SETUP*/ #endif /** @} */ - U16 drxOnDurTmr; /*!< DRX On-duration Timer value in + uint16_t drxOnDurTmr; /*!< DRX On-duration Timer value in PDCCH subframes */ - U16 drxInactvTmr; /*!< DRX Inactivity Timer value in + uint16_t drxInactvTmr; /*!< DRX Inactivity Timer value in PDCCH subframes */ - U16 drxRetxTmr; /*!< DRX Retransmission Timer value in PDCCH + uint16_t drxRetxTmr; /*!< DRX Retransmission Timer value in PDCCH subframes */ RgrDrxLongCycleOffst drxLongCycleOffst; /*!< DRX Long cycle and offset, values in subframes */ RgrDrxShortDrx drxShortDrx; /*!< DRX Short cycle value and offset */ #ifdef EMTC_ENABLE - U16 emtcDrxUlRetxTmr; /*Rel13 Drx Ul Retx Timer */ + uint16_t emtcDrxUlRetxTmr; /*Rel13 Drx Ul Retx Timer */ Bool isEmtcUe; Bool drxOnDurTmrR13Pres; Bool drxRetxTmrR13Pres; @@ -1503,7 +1623,7 @@ typedef struct rgrUeDrxCfg * @brief UE capability Configuration */ typedef struct rgrUeCapCfg { - U8 pwrClass; /*!< Power class per UE */ + uint8_t pwrClass; /*!< Power class per UE */ Bool intraSfFeqHop; /*!< Intra subframe frequency hopping for PUSCH */ Bool resAloocType1; /*!< Resource allocation type 1 for PDSCH */ Bool simCqiAckNack; /*!< Simultaneous CQI and ACK/NACK on PUCCH */ @@ -1519,7 +1639,7 @@ typedef struct rgrUeAckNackRepCfg variable can be used in reconfiguration also to stop/release the ACK/NACK Repetition */ - U16 pucchAckNackRep; /*!< n1PUCCH-AN-Rep */ + uint16_t pucchAckNackRep; /*!< n1PUCCH-AN-Rep */ RgrAckNackRepFactor ackNackRepFactor; /*!< ACK/NACK Repetition factor */ } RgrUeAckNackRepCfg; @@ -1536,8 +1656,8 @@ typedef struct rgrUeTxModeCfg @brief Uplink HARQ configuration per UE */ typedef struct rgrUeUlHqCfg { - U8 maxUlHqTx; /*!< Maximum number of UL HARQ transmissions */ - U8 deltaHqOffst; /*!< Delta HARQ offset + uint8_t maxUlHqTx; /*!< Maximum number of UL HARQ transmissions */ + uint8_t deltaHqOffst; /*!< Delta HARQ offset Currently this is unused parameter */ } RgrUeUlHqCfg; /** @@ -1546,7 +1666,7 @@ typedef struct rgrUeGrpPwrCfg { Bool pres; /*!< Indicates presence of UE PUCCH/PUSCH group power configuration */ CmLteRnti tpcRnti; /*!< TPC PUCCH/PUSCH RNTI for UE */ - U8 idx; /*!< Index for format 3/3A */ + uint8_t idx; /*!< Index for format 3/3A */ } RgrUeGrpPwrCfg; /** @brief Uplink power configuration per UE */ @@ -1558,9 +1678,9 @@ typedef struct rgrUeUlPwrCfg Bool isDeltaMCSEnabled; /*!< To indicate Delta MCS Enabled */ S8 p0UePusch; /*!< P_0UE_PUSCH*/ S8 p0UePucch; /*!< P_0_PUCCH*/ - U8 pSRSOffset; /*!< P_SRS_OFFSET + uint8_t pSRSOffset; /*!< P_SRS_OFFSET Currently this is unused parameter */ - U8 trgCqi; /*!< CQI to aim for during PUSCH power + uint8_t trgCqi; /*!< CQI to aim for during PUSCH power * control. Zero indicates absence, where * cell-wide trgCqi is used */ } RgrUeUlPwrCfg; @@ -1569,15 +1689,15 @@ typedef struct rgrUeUlPwrCfg typedef struct rgrUeQosCfg { Bool ambrPres; /*!< Indicates presence of AMBR */ - U32 dlAmbr; /*!< DL AMBR value for UE (bytes/sec): Optional */ - U32 ueBr; /*!< UL Byte Rate value for UE (bytes/sec): Optional */ + uint32_t dlAmbr; /*!< DL AMBR value for UE (bytes/sec): Optional */ + uint32_t ueBr; /*!< UL Byte Rate value for UE (bytes/sec): Optional */ } RgrUeQosCfg; /** @brief Time Alignment timer configuration per UE */ typedef struct rgrUeTaTmrCfg { Bool pres; /*!< rgr_x_001.main_7: Pres=NOTPRSNT indicates taTmr INFINITY */ - U16 taTmr; /*!< Timer configuration (in subframes) */ + uint16_t taTmr; /*!< Timer configuration (in subframes) */ } RgrUeTaTmrCfg; /** @name RGR_V1 */ /** @{ */ @@ -1590,10 +1710,10 @@ typedef struct rgrUeBsrTmrCfg { Bool isPrdBsrTmrPres; /*!< Indicates if periodic BSR timer is present */ - U16 prdBsrTmr; /*!< periodicBSR-Timer configuration + uint16_t prdBsrTmr; /*!< periodicBSR-Timer configuration (in subframes): Value 0xFFFF indicates 'Infinity' */ - U16 retxBsrTmr; /*!< retxBSR-Timer configuration (in subframes) + uint16_t retxBsrTmr; /*!< retxBSR-Timer configuration (in subframes) : Mandatory parameter */ } RgrUeBsrTmrCfg; #endif @@ -1605,19 +1725,19 @@ typedef struct rgrUeBsrTmrCfg typedef struct rgrUeSpsDlCfg { Bool isDlSpsEnabled; /*!< Bool indicating if DL SPS is enabled */ - U8 numSpsHqProc; /*!< Number of SPS harq Proc: Value in set + uint8_t numSpsHqProc; /*!< Number of SPS harq Proc: Value in set [1..8] */ - U8 numPucchVal; /*!< Count for configured PUCCH values */ - U32 n1PucchVal[4]; /*!< Array of n1Pucch values */ + uint8_t numPucchVal; /*!< Count for configured PUCCH values */ + uint32_t n1PucchVal[4]; /*!< Array of n1Pucch values */ RgrSpsPrd dlSpsPrdctyEnum; /*!< Periodicity for DL SPS */ - U16 explicitRelCnt; /*!< Number of SPS ocassions with BO = 0 after + uint16_t explicitRelCnt; /*!< Number of SPS ocassions with BO = 0 after which SPS is released */ } RgrUeSpsDlCfg; typedef struct rgrUlSpsLcInfo { Bool isSpsEnabled; - U8 lcId; + uint8_t lcId; }RgrUlSpsLcInfo; /** @@ -1640,7 +1760,7 @@ typedef struct rgrUeSpsUlCfg S8 p0UePuschVal; /*!< Value in range [-8....7] */ } pwrCfg; RgrSpsPrd ulSpsPrdctyEnum; /*!< Periodicity for UL SPS */ - U8 lcCnt; /*!< Number of logical channels */ + uint8_t lcCnt; /*!< Number of logical channels */ RgrUlSpsLcInfo spsLcInfo[RGR_MAX_SPS_LC];/*!< Array of SPS logical channels - All these are assumed to be mapped onto SPS lcg with ID=1 */ @@ -1684,7 +1804,7 @@ typedef struct rgrUeTxAntSelCfg @brief PUSH n CQI Reporting related configuration for an UE*/ typedef struct rgrUeCqiReptCfg { - U8 numColltdCqiRept; /*!< Number of CQI reports to be sent in PUSH n + uint8_t numColltdCqiRept; /*!< Number of CQI reports to be sent in PUSH n Reporting */ }RgrUeCqiReptCfg; @@ -1692,8 +1812,8 @@ typedef struct rgrUeCqiReptCfg @brief CQI for subband number subBandIdx */ typedef struct rgrSubBandCqiInfo { - U8 cqi[2]; /*!< Subband CQI for two codewords */ - U8 subBandIdx; /*!< Index of the subband starting from 0, + uint8_t cqi[2]; /*!< Subband CQI for two codewords */ + uint8_t subBandIdx; /*!< Index of the subband starting from 0, in ascending order of frequency */ } RgrSubBandCqiInfo; @@ -1702,10 +1822,10 @@ typedef struct rgrSubBandCqiInfo @brief A CQI Report used in PUSH n Reporting*/ typedef struct rgrUeCqiRept { - U8 cqi[2]; /*!< Wideband CQI Value for two codewords*/ - U8 cqiMode; /*!< Reporting mode by which CQI was reported */ + uint8_t cqi[2]; /*!< Wideband CQI Value for two codewords*/ + uint8_t cqiMode; /*!< Reporting mode by which CQI was reported */ RgrSubBandCqiInfo sbCqiInfo[RGR_MAX_DL_CQI_SUBBAND]; - U8 numSubBand;/*!< Number of Subbands for which CQI is + uint8_t numSubBand;/*!< Number of Subbands for which CQI is being reported */ } RgrUeCqiRept; @@ -1715,7 +1835,7 @@ typedef struct rgrUeCqiRept typedef struct RgrUeCqiInfo { RgrUeCqiRept cqiRept[RGR_CQIRPTS_MAXN]; /*!< CQI reports */ - U8 numCqiRept; /*!< Number of CQI reports present */ + uint8_t numCqiRept; /*!< Number of CQI reports present */ } RgrUeCqiInfo; /*rgr_x_001.main_11 ADD added changes for CQI management*/ @@ -1735,12 +1855,12 @@ typedef struct rgrStaIndInfo typedef struct rgrLoadInfIndInfo { CmLteCellId cellId; /*!< Cell ID */ - U16 bw; /*!< Bandwidth */ - U32 type; + uint16_t bw; /*!< Bandwidth */ + uint32_t type; union { TknStrOSXL rntpInfo; /*!< RNTP Info */ - U32 absLoadInfo[RGR_ABS_PATTERN_LEN]; + uint32_t absLoadInfo[RGR_ABS_PATTERN_LEN]; } u; }RgrLoadInfIndInfo; /* LTE_ADV_FLAG_REMOVED_END */ @@ -1771,7 +1891,7 @@ typedef struct rgrUePdschDedCfg /* @brief UE Configuration for LTE Adv feature */ typedef struct rgrLteAdvancedUeConfig { - U32 pres; + uint32_t pres; Bool isUeCellEdge; /*! Flag to indicate UE is cell edge or cell center */ Bool isAbsUe; /*! Flag to indicate ABS UE or Not */ } RgrLteAdvancedUeConfig; @@ -1795,40 +1915,40 @@ typedef enum RgrAccessStratumRls typedef struct rgrExtaddgrp2 { Bool pres; - U8 csiNumRep;// MAPPING - U8 mpddchPdschHop; - U8 mpdcchStartUESSFDD;// MAPPING - U16 mpdcchNumRep;// MAPPING - U32 mpddchNB;//1.. maxAvailNarrowBands-r13 + uint8_t csiNumRep;// MAPPING + uint8_t mpddchPdschHop; + uint8_t mpdcchStartUESSFDD;// MAPPING + uint16_t mpdcchNumRep;// MAPPING + uint32_t mpddchNB;//1.. maxAvailNarrowBands-r13 }RgrExtaddgrp2; typedef struct rgrRbAssignment { - U8 numPRBpairs; // MAPPING - U8 rbAssignment[5]; + uint8_t numPRBpairs; // MAPPING + uint8_t rbAssignment[5]; }RgrRbAssignment; typedef struct rgrEpdcchAddModLst { - U8 setConfigId; - U8 transmissionType; + uint8_t setConfigId; + uint8_t transmissionType; RgrRbAssignment resBlkAssignment; - U32 dmrsScrambSeq; - U32 pucchResStartoffset; - TknU32 pdschRemapQLcfgId; - TknU8 mpdcchNumPRBpair; // MAPPING + uint32_t dmrsScrambSeq; + uint32_t pucchResStartoffset; + TknUInt32 pdschRemapQLcfgId; + TknUInt8 mpdcchNumPRBpair; // MAPPING RgrExtaddgrp2 extaddgrp2; }RgrEpdcchAddModLst; typedef struct rgrSubFrmPatCfg { Bool pres; - U8 measSfPatFDD[5]; + uint8_t measSfPatFDD[5]; }RgrSubFrmPatCfg; typedef struct rgrEpdcchConfigRel11 { Bool pres; RgrSubFrmPatCfg sfPtn; - TknU32 startSymbolr11; + TknUInt32 startSymbolr11; RgrEpdcchAddModLst epdcchAddModLst[RGR_MAX_EPDCCH_SET]; }RgrEpdcchConfigRel11; @@ -1839,8 +1959,8 @@ typedef struct rgrUeEmtcRecfg typedef struct rgrPucchRepCfgRel13 { Bool isPucchRepPres; - U8 modeANumPucchRepFormat1; - U8 modeANumPucchRepFormat2; + uint8_t modeANumPucchRepFormat1; + uint8_t modeANumPucchRepFormat2; }RgrPucchRepCfgRel13; @@ -1850,18 +1970,18 @@ typedef struct rgrUeEmtcCfg Bool pres; RgrEpdcchConfigRel11 emtcEpdcchCfg; RgrPucchRepCfgRel13 emtcPucchRepCfg; - U8 pdschReptLevModeA; + uint8_t pdschReptLevModeA; }RgrUeEmtcCfg; #endif #ifdef RG_5GTF typedef struct rgrUe5gtfCfg { - U8 grpId; - U8 BeamId; - U8 numCC; - U8 mcs; - U8 maxPrb; + uint8_t grpId; + uint8_t BeamId; + uint8_t numCC; + uint8_t mcs; + uint8_t maxPrb; }RgrUe5gtfCfg; #endif @@ -1898,7 +2018,7 @@ typedef struct rgrUeCfg RgrUeCapCfg ueCapCfg; /*!< UE Capabilty reconfiguration */ RgrCodeBookRstCfg ueCodeBookRstCfg; /*!< Number of bits in code book for transmission modes */ - TknU8 dedPreambleId; /*!< If present, then mapping exists at + TknUInt8 dedPreambleId; /*!< If present, then mapping exists at RGR user with CRNTI */ /** @name LTE_TDD */ /** @{ */ @@ -1953,7 +2073,7 @@ typedef struct rgrUeCfg RgrLteAdvancedUeConfig ueLteAdvCfg; /*!< LTE Adv configuration per UE */ /* LTE_ADV_FLAG_REMOVED_END */ RgrAccessStratumRls accessStratumRls; /*!< UE Access Stratum Release */ - U8 csgMmbrSta; /* CSG Membership status, refer RgrUeCsgMbrStatus */ + uint8_t csgMmbrSta; /* CSG Membership status, refer RgrUeCsgMbrStatus */ #ifdef EMTC_ENABLE RgrUeEmtcCfg emtcUeCfg; #endif @@ -1965,10 +2085,10 @@ typedef struct rgrUeCfg @brief QCI, GBR, and MBR configuration for dedicated logical channels */ typedef struct rgrLchQosCfg { - U8 qci; /*!< QCI for the logical channel. + uint8_t qci; /*!< QCI for the logical channel. Valid Range:[0-255] (Actual QCI - 1). */ - U32 gbr; /*!< GBR value for a logical channel (bytes/sec). */ - U32 mbr; /*!< MBR value for a logical channel (bytes/sec). */ + uint32_t gbr; /*!< GBR value for a logical channel (bytes/sec). */ + uint32_t mbr; /*!< MBR value for a logical channel (bytes/sec). */ } RgrLchQosCfg; /*rgr_x_001.main_9 - Added support for SPS*/ /** @@ -1991,7 +2111,7 @@ typedef struct rgrDlLchCfg RgrLchQosCfg dlQos; /*!< DL QoS parameters: Only for dedicated channels */ /*rgr_x_001.main_9 - Added support for SPS*/ RgrLchSpsCfg dlSpsCfg; /*!< SPS configuration for DL logical channel */ - U8 rlcReorderTmr; /*!< RLC reordering timer required for LAA*/ + uint8_t rlcReorderTmr; /*!< RLC reordering timer required for LAA*/ } RgrDlLchCfg; /** @@ -1999,21 +2119,21 @@ typedef struct rgrDlLchCfg typedef struct rgrUlLchCfg { CmLteLcId lcId; /*!< LC ID for uplink logical channel*/ - U8 qci; /*!< QCI associated with LC ID */ + uint8_t qci; /*!< QCI associated with LC ID */ } RgrUlLchCfg; /** @brief Logical channel group configuration information for uplink logical channels */ typedef struct rgrUlLcgCfg { - U8 lcgId; /*!< Logical channel group ID */ + uint8_t lcgId; /*!< Logical channel group ID */ /*rgr_x_001.main_11 ADD added changes for L2 measurements*/ #ifdef LTE_L2_MEAS - U8 numLch; /*!< Number of LC's for this group in Uplink */ + uint8_t numLch; /*!< Number of LC's for this group in Uplink */ RgrUlLchCfg lchUlCfg[RGR_MAX_LC_PER_LCG]; /*!< Logical Channel details for this LCG*/ #endif /*LTE_L2_MEAS */ - U32 gbr; /*!< Commulative UL GBR of all LC mapping to this LCG */ - U32 mbr; /*!< Commulative UL MBR of all LC mapping to this LCG */ + uint32_t gbr; /*!< Commulative UL GBR of all LC mapping to this LCG */ + uint32_t mbr; /*!< Commulative UL MBR of all LC mapping to this LCG */ } RgrUlLcgCfg; /** @@ -2021,8 +2141,8 @@ typedef struct rgrUlLcgCfg typedef struct rgrUlLchQciCfg { CmLteLcId lcId; /*!< Logical channel ID */ - U8 qci; /*!< Qci */ - U8 lcgId; /*!< Logical channel group ID */ + uint8_t qci; /*!< Qci */ + uint8_t lcgId; /*!< Logical channel group ID */ }RgrUlLchQciCfg; /** @@ -2041,7 +2161,7 @@ typedef struct rgrLchCfg CM_LTE_LCH_DTCH */ RgrDlLchCfg dlInfo; /*!< Downlink logical channel configuration information */ RgrUlLchQciCfg ulLchQciInfo; /*!< Uplink logical channel configuration information */ - U8 lcgId; /*!< Logical channel group ID */ + uint8_t lcgId; /*!< Logical channel group ID */ } RgrLchCfg; /** @brief Set of parameters for logical channelgroup Configuration */ @@ -2056,14 +2176,15 @@ typedef struct rgrLcgCfg /** @brief Basic configuration structure at RRM */ typedef struct rgrCfg { - U8 cfgType; /*!< Indicates configuration type */ + uint8_t cfgType; /*!< Indicates configuration type */ union /*!< cfgType is selector */ { RgrCellCfg cellCfg; /*!< Cell configuration */ RgrUeCfg ueCfg; /*!< UE configuration */ RgrLchCfg lchCfg; /*!< Dedicated logical channel configuration */ RgrLcgCfg lcgCfg; /*!< Dedicated logical channel Group configuration */ - RgrSchedEnbCfg schedEnbCfg; /*!< EnodeB Sched Configurations */ + RgrSchedEnbCfg schedEnbCfg; /*!< EnodeB Sched Configurations */ //TODO:remove this + MacSchedGnbCfg schedGnbCfg; /*!< gNB Sched Configurations */ } u; } RgrCfg; @@ -2080,7 +2201,7 @@ typedef struct rgrActvTime typedef struct rgrCellRecfg { CmLteCellId cellId; /*!< Cell ID */ - U32 recfgTypes; /*!< Bitmask indicating reconfiguration types */ + uint32_t recfgTypes; /*!< Bitmask indicating reconfiguration types */ RgrActvTime recfgActvTime; /*!< Activation Time for cell reconfiguration */ RgrDlHqCfg dlHqRecfg; /*!< DL HARQ related reconfiguration */ RgrCfiCfg cfiRecfg; /*!< CFI reconfiguration for PDCCH */ @@ -2101,7 +2222,7 @@ typedef struct rgrCellRecfg #ifdef RGR_SI_SCH RgrSiCfg siReCfg; /*!