X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2Fcm%2Frgr.x;h=2eba088ba1ffe2499f4af65e04b190f880d97159;hb=3235ecfc7414aa0b72d0ad50db63ae8b5626045b;hp=7987f8c6a30f251197e516c171ef5d864de0dbc2;hpb=997e3f26d55352586a1d4d0c46c41a98452af88a;p=o-du%2Fl2.git diff --git a/src/cm/rgr.x b/src/cm/rgr.x index 7987f8c6a..2eba088ba 100755 --- a/src/cm/rgr.x +++ b/src/cm/rgr.x @@ -830,6 +830,22 @@ typedef struct rgrCellCntrlCmdCfg } RgrCellCntrlCmdCfg; +/** + * @brief + * eNB level Scheduler Configurations + * along with other PFS config Parameters + */ +typedef struct macSchedGnbCfg +{ + U8 numTxAntPorts; /*!< Number of Tx antenna ports */ + U8 ulSchdType; /*!< Indicates which UL scheduler to use, range + * is 0..(number of schedulers - 1) */ + U8 dlSchdType; /*!< Indicates which DL scheduler to use, range + * is 0..(number of schedulers - 1) */ + U8 numCells; /*!< Max number of cells */ + U8 maxUlUePerTti; /*!< Max number of UE in UL per TTI */ + U8 maxDlUePerTti; /*!< Max number of UE in DL per TTI */ +}MacSchedGnbCfg; /** * @brief * eNB level Scheduler Configurations @@ -1049,10 +1065,113 @@ typedef struct rgr5gtfCellCfg }Rgr5gtfCellCfg; #endif +/** @brief This enum defines dl ul transmission periodicity as per spec 38.331 + * servingCellConfigCommon */ +typedef enum rgrDlUlTxPrdcty +{ + RGR_DLULTXPRDCTY_MS0DOT5 = 0, /*! 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + U16 pcchTxPwrOffset; /*!< Tx Pwr Offset for PCCH tx. + Offset to the reference signal + power. Value: 0 -> 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + U16 rarTxPwrOffset; /*!< Tx Pwr Offset for RAR tx. + Offset to the reference signal + power. Value: 0 -> 10000, + representing -6 dB to 4 dB in 0.001 + dB steps */ + U8 nrMu; /*! 6Ghz)*/ + RgrType0PdcchCSSCfg type0PdcchCSSCfg; /*!< Type 0 CSS Config params */ + RgrFreqInfoDlCfg freqInfoDlCfg; /*!< DL Frequency information + config */ + RgrSulCellCfg sulCellCfg; /*!< SUL Cell config */ + RgrUlCfgCmn ulCmnCfg; /*!< initial UL Bwp and Ul freq + information */ +#endif + Bool initDlBwpPres; /*!< intial common + DL BWP is present or not */ + RgrBwpDlCmn initDlBwp; /*!