X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.h;h=8bb6311ef99a96ed4687f70708e2cfbad5d9588f;hb=8582e5ba1e60662fcfc37a74a68492bec1cb263f;hp=3793761f5dfa364cee92b3efebc19a4eaaae2649;hpb=0bb62f25ad9d8f9ff8724572f96e51a898937f0c;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 3793761f5..8bb6311ef 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -59,9 +59,38 @@ #define PRB_BITMAP_IDX_LEN 64 #define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN) +#define SCH_MAX_NUM_UL_HQ_PROC 16 +#define SCH_MAX_NUM_DL_HQ_PROC 16 +#define SCH_MAX_NUM_MSG3_TX 2 +#define SCH_MAX_NUM_DL_HQ_TX 3 +#define SCH_MAX_NUM_UL_HQ_TX 3 +#define SCH_MAX_NUM_MSG4_TX 2 +#define HQ_ACK 0 +#define HQ_NACK 1 +#define HQ_DTX 2 + +#ifdef NR_DRX +/* As per 38.331 the largest offset which can be used in of size 10240. + * But using this much size of array can cause memory related issue so thats why + * taking this size which are a multiple of the larger size */ +#define MAX_DRX_SIZE 512 +#endif + +#define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/ + +typedef struct schDlHqProcCb SchDlHqProcCb; +typedef struct schUlHqEnt SchUlHqEnt; +typedef struct schRaReq SchRaReq; +typedef struct schDlHqEnt SchDlHqEnt; typedef struct schCellCb SchCellCb; typedef struct schUeCb SchUeCb; +typedef enum +{ + SCH_FCFS, + SCH_SLICE_BASED +}SchType; + typedef enum { SCH_NUMEROLOGY_0, @@ -78,6 +107,14 @@ typedef enum SCH_UE_HANDIN_IN_PROGRESS }SchUeState; +typedef enum +{ + SCH_RA_STATE_MSG2_HANDLE, + SCH_RA_STATE_MSG3_PENDING, + SCH_RA_STATE_MSG4_PENDING, + SCH_RA_STATE_MSG4_DONE +}SchRaState; + typedef enum { SCH_LC_STATE_INACTIVE, @@ -91,6 +128,133 @@ typedef enum WINDOW_EXPIRED }RaRspWindowStatus; +typedef enum +{ + HQ_TB_ACKED=0, + HQ_TB_NACKED, + HQ_TB_WAITING +}SchHqTbState; + +/*Following structures to keep record and estimations of PRB allocated for each + * LC taking into consideration the RRM policies*/ +typedef struct lcInfo +{ + uint8_t lcId; /*LCID for which BO are getting recorded*/ + uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/ + uint32_t allocBO; /*TBS/BO Size which is actually allocated*/ + uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/ +}LcInfo; + +typedef struct schUlHqTbCb +{ + uint32_t tbSzReq; + uint32_t tbSzAllc; + uint8_t ndi; + uint8_t rv; + uint8_t rvIdx; + uint8_t qamOrder; + SchMcsTable mcsTable; + uint8_t iMcs; + uint8_t iMcsInDci; + uint8_t numLyrs; + uint8_t txCntr; + SchHqTbState state; + uint8_t cntrRetxAllocFail; + uint8_t statsBitmap; +}SchUlHqTbCb; + +typedef struct schDlHqTbCb +{ + uint8_t tbIdx; + Bool isEnabled; + uint32_t tbSzReq; + uint8_t txCntr; + uint8_t ndi; + uint8_t rv; + uint8_t rvIdx; + uint8_t iMcs; + uint8_t iMcsInDci; + uint8_t numLyrs; + SchHqTbState state; + uint8_t isAckNackDtx; + uint8_t cntrRetxAllocFail; + //InfUeTbInfo tbCompInfo; + uint8_t statsBitmap; +}SchDlHqTbCb; + +#ifdef NR_DRX +typedef struct schDrxHarqCb +{ + uint32_t rttExpIndex; + CmLList *rttExpNode; + uint32_t retxStrtIndex; + CmLList *retxStrtNode; + uint32_t retxExpIndex; + CmLList *retxExpNode; +}SchDrxHarqCb; +#endif + +typedef struct schUlHqProcCb +{ + uint8_t procId; /*!< HARQ Process ID */ + SchUlHqEnt *hqEnt; + uint8_t maxHqTxPerHqP; + SchUlHqTbCb tbInfo; + CmLList ulHqEntLnk; + CmLList ulSlotLnk; + uint8_t strtSymbl; + uint8_t numSymbl; + void *schSpcUlHqProcCb; /*!< Scheduler specific HARQ Proc CB */ + CmLList ulHqProcLink; + uint8_t puschResType; /*!< Resource allocation type */ + uint16_t puschStartPrb; + uint16_t puschNumPrb; + uint8_t dmrsMappingType; + uint8_t nrOfDmrsSymbols; + uint8_t dmrsAddPos; + SlotTimingInfo puschTime; +#ifdef NR_DRX + SchDrxHarqCb ulDrxHarqCb; +#endif +}SchUlHqProcCb; + +struct schDlHqProcCb +{ + uint8_t procId; /*!< HARQ Process ID */ + SchDlHqEnt *hqEnt; + uint8_t maxHqTxPerHqP; + CmLList dlHqEntLnk; + CmLList ulSlotLnk; + SchDlHqTbCb tbInfo[2]; + uint8_t k1; + void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */ + CmLList dlHqProcLink; + SlotTimingInfo pucchTime; +#ifdef NR_DRX + SchDrxHarqCb dlDrxHarqCb; +#endif +}; +struct schUlHqEnt +{ + SchCellCb *cell; /*!< Contains the pointer to cell*/ + SchUeCb *ue; /*!< Contains the pointer to ue*/ + CmLListCp free; /*!< List of free HARQ processes */ + CmLListCp inUse; /*!< List of in-use HARQ processes */ + uint8_t maxHqTx; /*!< Maximum number of harq re-transmissions */ + uint8_t numHqPrcs; /*!< Number of HARQ Processes */ + SchUlHqProcCb procs[SCH_MAX_NUM_UL_HQ_PROC]; /*!< Uplink harq process info */ +}; +struct schDlHqEnt +{ + SchCellCb *cell; /*!< Contains the pointer to cell */ + SchUeCb *ue; /*!< Contains the pointer to UE */ + CmLListCp free; /*!< List of free HARQ processes */ + CmLListCp inUse; /*!< List of in-use HARQ processes */ + uint8_t maxHqTx; /*!< Maximum number of harq transmissions */ + uint8_t numHqPrcs; /*!< Number of HARQ Processes */ + SchDlHqProcCb procs[SCH_MAX_NUM_DL_HQ_PROC];/*!< Downlink harq processes */ +}; + /** * @brief * Structure holding LTE MAC's General Configuration information. @@ -144,9 +308,15 @@ typedef struct schDlSlotInfo typedef struct schRaCb { + uint8_t ueId; bool msg4recvd; uint16_t tcrnti; uint16_t dlMsgPduLen; + SchUlHqProcCb msg3HqProc; + SchUlHqProcCb *retxMsg3HqProc; + SchRaState raState; + SchCellCb *cell; + SchRaReq *raReq; }SchRaCb; /** @@ -184,6 +354,7 @@ typedef struct schLcCtxt uint16_t pduSessionId; /*Pdu Session Id*/ Snssai *snssai; /*S-NSSAI assoc with LCID*/ bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/ + uint16_t rsvdDedicatedPRB; }SchDlLcCtxt; typedef struct schDlCb @@ -194,7 +365,7 @@ typedef struct schDlCb typedef struct schUlLcCtxt { SchLcState lcState; - uint8_t lcId; + uint8_t lcId; uint8_t priority; uint8_t lcGroup; uint8_t schReqId; @@ -203,6 +374,7 @@ typedef struct schUlLcCtxt uint16_t pduSessionId; /*Pdu Session Id*/ Snssai *snssai; /*S-NSSAI assoc with LCID*/ bool isDedicated; /*Flag containing Dedicated S-NSSAI or not*/ + uint16_t rsvdDedicatedPRB; }SchUlLcCtxt; typedef struct schUlCb @@ -220,43 +392,59 @@ typedef struct schUeCfgCb bool phyCellGrpCfgPres; SchPhyCellGrpCfg phyCellGrpCfg; bool spCellCfgPres; - SchSpCellCfg spCellCfg; + SchSpCellRecfg spCellCfg; SchAmbrCfg *ambrCfg; SchModulationInfo dlModInfo; SchModulationInfo ulModInfo; SchDataTransmission dataTransmissionAction; }SchUeCfgCb; -/*Following structures to keep record and estimations of PRB allocated for each - * LC taking into consideration the RRM policies*/ -typedef struct lcInfo +typedef struct schHqDlMap { - uint8_t lcId; /*LCID for which BO are getting recorded*/ - uint32_t reqBO; /*Size of the BO requested/to be allocated for this LC*/ - uint32_t allocBO; /*TBS/BO Size which is actually allocated*/ - uint8_t allocPRB; /*PRB count which is allocated based on RRM policy/FreePRB*/ -}LcInfo; + CmLListCp hqList; +}SchHqDlMap; -typedef struct dedicatedLCInfo +typedef struct schHqUlMap { - CmLListCp dedLcList; /*Linklist of LC assoc with RRMPolicyMemberList*/ - uint16_t rsvdDedicatedPRB; /*Number of PRB reserved for this Dedicated S-NSSAI*/ -}DedicatedLCInfo; + CmLListCp hqList; +}SchHqUlMap; -typedef struct schLcPrbEstimate +#ifdef NR_DRX +typedef struct schDrxUeCb { - /* TODO: For Multiple RRMPolicies, Make DedicatedLcInfo as array/Double Pointer - * and have separate DedLCInfo for each RRMPolcyMemberList*/ - /* Dedicated LC List will be allocated, if any available*/ - DedicatedLCInfo *dedLcInfo; /*Contain LCInfo per RRMPolicy*/ - - CmLListCp defLcList; /*Linklist of LC assoc with Default S-NSSAI(s)*/ - - /* SharedPRB number can be used by any LC. - * Need to calculate in every Slot based on PRB availability*/ - uint16_t sharedNumPrb; -}SchLcPrbEstimate; - + bool drxDlUeActiveStatus; /* Final Dl Ue status which is marked as true if drxDlUeActiveMask or drxDlUeActiveMaskForHarq is present */ + bool drxUlUeActiveStatus; /* Final Ul Ue status which is marked as true if drxUlUeActiveMask or drxUlUeActiveMaskForHarq is present */ + uint32_t drxDlUeActiveMask; /* variable is used to store the status about downlink active status of Ue for On-duration, inactive timer*/ + uint32_t drxUlUeActiveMask; /* variable is used to store the status about uplink active status for on-duration inactive timer*/ + uint32_t drxDlUeActiveMaskForHarq; /* variable is used to store the status about downlink active status for harq*/ + uint32_t drxUlUeActiveMaskForHarq; /* variable is used to store the status about uplink active status for harq */ + uint32_t onDurationLen; /* length of on duration which is received from ue cfg/recfg in form of ms and subms, informs about after how many slots on duration gets expire */ + uint32_t inActvTimerLen; /* length of inActvTimer value received from ue cfg/recfg in form of ms, informs about after how many slots in active gets expire */ + uint8_t harqRttDlTimerLen; /* length of harqRttDlTimer received from ue cfg/recfg in form of symbols, inform about after how many slots on the harq drx-HARQ-RTT-TimerDL expire */ + uint8_t harqRttUlTimerLen; /* length of harqRttUlTimer received from ue cfg/recfg in form of symbols,informs about after how many slots on harq drx-HARQ-RTT-TimerUL expire*/ + uint32_t retransDlTimerLen; /* length of retransDlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer dl timer expire*/ + uint32_t retransUlTimerLen; /* length of retransUlTimer received from ue cfg/recfg in form of slot, informs about after how many slots on harq RetransmissionTimer ul timer expire*/ + uint32_t longCycleLen; /* length of long Cycle value received from ue cfg/recfg in form of ms*/ + bool longCycleToBeUsed; /* long cycle should be used once the short cycle gets expires */ + uint32_t drxStartOffset; /* length of drxStartOffset value received from ue cfg/recfg in form of ms, which helps in getting on duration start point*/ + bool shortCyclePresent; /* set this value if shortCycle is Present */ + uint32_t shortCycleLen; /* length of short Cycle value received from ue cfg/recfg in form of ms*/ + uint32_t shortCycleTmrLen; /* value shortCycleTmr is the multiple of shortCycle which is received from ue cfg/recfg in form of integer*/ + uint32_t drxSlotOffset; /* drxSlotOffset value received from ue cfg/recfg which is used to delay before starting the drx-onDuration*/ + uint32_t onDurationStartIndex; /* Index at which UE is stored in onDuration starts list */ + uint32_t onDurationExpiryIndex; /* Index at which UE is stored in onDuration expires in the list */ + uint32_t inActvExpiryIndex; /* Index at which UE is stored in inActvTimer expires in the list */ + uint32_t shortCycleExpiryIndex; /* Index at which UE is stored in shortCycle expires in the list */ + int32_t shortCycleDistance; /* Distance after how many slot short cycle tmr gets expire */ + int32_t onDurationStartDistance;/* Distance after how many slot on Duration Start tmr gets expire */ + int32_t onDurationExpiryDistance;/* Distance after how many slot on Duration tmr gets expire */ + int32_t inActiveTmrExpiryDistance;/* Distance after how many slot inActive tmr gets expire */ + CmLList *onDurationStartNodeInfo; /* Node present in on duration start list*/ + CmLList *onDurationExpiryNodeInfo;/* Node present in on duration exp list*/ + CmLList *inActvTimerExpiryNodeInfo; /* Node present in in active exp list*/ + CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/ +}SchDrxUeCb; +#endif /** * @brief * UE control block @@ -274,8 +462,17 @@ typedef struct schUeCb BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS]; SchUlCb ulInfo; SchDlCb dlInfo; - SchLcPrbEstimate dlLcPrbEst; /*DL PRB Alloc Estimate among different LC*/ - SchLcPrbEstimate ulLcPrbEst; /*UL PRB Alloc Estimate among different LC*/ + SchUlHqEnt ulHqEnt; + SchDlHqEnt dlHqEnt; + SchDlHqProcCb *msg4HqProc; + SchDlHqProcCb *retxMsg4HqProc; + SchHqDlMap **hqDlmap; + SchHqUlMap **hqUlmap; + void *schSpcUeCb; +#ifdef NR_DRX + bool ueDrxInfoPres; + SchDrxUeCb drxUeCb; +#endif }SchUeCb; /** @@ -314,6 +511,57 @@ typedef struct schPageCb SchPagingOcc pagMonOcc[MAX_PO_PER_PF]; /*Paging Occasion Slot/FrameOffset are stored*/ }SchPageCb; +#ifdef NR_DRX +typedef struct schDrxCb +{ + CmLListCp onDurationStartList; /*!< Tracks the start of onDuration Timer. */ + CmLListCp onDurationExpiryList; /*!< Tracks the Expiry of onDuration Timer. */ + CmLListCp inActvTmrExpiryList; /*!< Tracks the Expiry of drx-InactivityTimer. */ + CmLListCp shortCycleExpiryList; /*!< Tracks the Expiry of DRX Short Cycle. */ + CmLListCp dlHarqRttExpiryList; /*!< Tracks the Expiry of DL HARQ RTT timer. */ + CmLListCp dlRetransExpiryList; /*!< Tracks the Expiry of DL Re-Transmission timer. */ + CmLListCp ulHarqRttExpiryList; /*!< Tracks the Expiry of UL HARQ RTT timer. */ + CmLListCp ulRetransExpiryList; /*!< Tracks the Expiry of UL Re-Transmission timer. */ + CmLListCp dlRetransTmrStartList; /*!< It has list of DL harq procs for */ + CmLListCp ulRetransTmrStartList; /*!< It has list of UL harq procs for */ +}SchDrxCb; +#endif + +typedef struct schAllApis +{ + uint8_t (* SchCellCfgReq)(SchCellCb *cellCb); + void (* SchCellDeleteReq)(SchCellCb *cellCb); + uint8_t (* SchAddUeConfigReq)(SchUeCb *ueCb); + void (* SchModUeConfigReq)(SchUeCb *ueCb); + void (* SchUeDeleteReq)(SchUeCb *ueCb); + void (* SchDlHarqInd)(); + void (* SchPagingInd)(); + void (* SchRachRsrcReq)(); + void (* SchRachRsrcRel)(); + void (* SchCrcInd)(SchCellCb *cellCb, uint16_t ueId); + void (* SchRachInd)(SchCellCb *cellCb, uint16_t ueId); + void (* SchDlRlcBoInfo)(SchCellCb *cellCb, uint16_t ueId); + void (* SchSrUciInd)(SchCellCb *cellCb, uint16_t ueId); + void (* SchBsr)(SchCellCb *cellCb, uint16_t ueId); + void (* SchHandleLcList)(void *ptr, CmLList *node, ActionTypeLL action); + void (* SchAddToDlHqRetxList)(SchDlHqProcCb *hqP); + void (* SchAddToUlHqRetxList)(SchUlHqProcCb *hqP); + void (* SchRemoveFrmDlHqRetxList)(SchUeCb *ueCb, CmLList *node); + void (* SchRemoveFrmUlHqRetxList)(SchUeCb *ueCb, CmLList *node); + uint8_t (* SchAddUeToSchedule)(SchCellCb *cellCb, uint16_t ueId); + void (* SchRemoveUeFrmScheduleLst)(SchCellCb *cell, CmLList *node); + uint8_t (* SchInitDlHqProcCb)(SchDlHqProcCb *hqP); + uint8_t (* SchInitUlHqProcCb)(SchUlHqProcCb *hqP); + void (* SchFreeDlHqProcCb)(SchDlHqProcCb *hqP); + void (* SchFreeUlHqProcCb)(SchUlHqProcCb *hqP); + void (* SchDeleteDlHqProcCb)(SchDlHqProcCb *hqP); + void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP); + void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst); + uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \ + bool isRetx, SchDlHqProcCb **hqP); + uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \ + uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP); +}SchAllApis; /** * @brief * Cell Control block per cell. @@ -323,7 +571,7 @@ typedef struct schCellCb uint16_t cellId; /*!< Cell ID */ Inst instIdx; /*!< Index of the scheduler instance */ Inst macInst; /*!< Index of the MAC instance */ - uint8_t numSlots; /*!< Number of slots in current frame */ + uint16_t numSlots; /*!< Number of slots in current frame */ SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/ SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */ @@ -338,20 +586,25 @@ typedef struct schCellCb uint32_t actvUeBitMap; /*!< Bit map to find active UEs */ uint32_t boIndBitMap; /*!< Bit map to indicate UEs that have recevied BO */ SchUeCb ueCb[MAX_NUM_UE]; /*!< Pointer to UE contexts of this cell */ - CmLListCp ueToBeScheduled; /*!< Linked list to store UEs pending to be scheduled, */ SchPageCb pageCb; /*!< Page Record at Schedular*/ #ifdef NR_TDD uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */ uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */ uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */ #endif +#ifdef NR_DRX + SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/ +#endif + SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/ + SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/ + void *schSpcCell; /*Ref of Scheduler specific structure*/ }SchCellCb; typedef struct schSliceCfg { uint8_t numOfSliceConfigured; - SchRrmPolicyOfSlice **listOfConfirguration; + SchRrmPolicyOfSlice **listOfSlices; }SchSliceCfg; /** @@ -360,12 +613,13 @@ typedef struct schSliceCfg */ typedef struct schCb { - TskInit schInit; /*!< Task Init info */ - SchGenCb genCfg; /*!< General Config info */ - CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ - CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ - SchCellCb *cells[MAX_NUM_CELL]; /* Array to store cellCb ptr */ - SchSliceCfg sliceCfg; + TskInit schInit; /*!< Task Init info */ + SchGenCb genCfg; /*!< General Config info */ + CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ + CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ + SchAllApis allApis[NUM_SCH_TYPE]; /*!