X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.h;h=81fbc042b01f3b1d2abe1dc1571d68477c55d992;hb=e96cb439cd4a7a6f55e3fab7caed978e38bd62b4;hp=89c633a5d760d5a29cb4f6c92d8803f6854f39c9;hpb=913519063008692a8245dd502002676cf1ee9290;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 89c633a5d..81fbc042b 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -17,8 +17,6 @@ *******************************************************************************/ /* macros */ -#define SCH_INST_START 1 -#define SCH_MAX_INST 1 #define SCH_MU0_NUM_SLOTS 10 #define SCH_MU1_NUM_SLOTS 20 #define SCH_MU2_NUM_SLOTS 30 @@ -47,7 +45,6 @@ #define NUM_DMRS_SYMBOLS 1 #define DMRS_ADDITIONAL_POS 0 #define SCH_DEFAULT_K1 1 -#define SCH_TQ_SIZE 10 #define SSB_IDX_SUPPORTED 1 #define CRC_FAILED 0 @@ -80,6 +77,19 @@ #define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/ +#define SCH_TQ_SIZE 10 + +/*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/ +#define NUM_PRBS_PER_RBG 6 + +/*3GPP 38.214 Table 5.2.2.1-2*/ +#define MAX_NUM_CQI_IDX 16 + +/*3GPP 38.211 Table 7.3.2.1-1*/ +#define MAX_NUM_AGG_LVL 5 + +#define PUCCH_RES_IND 0 + typedef struct schDlHqProcCb SchDlHqProcCb; typedef struct schUlHqEnt SchUlHqEnt; typedef struct schRaReq SchRaReq; @@ -242,7 +252,7 @@ struct schDlHqProcCb SchDlHqEnt *hqEnt; uint8_t maxHqTxPerHqP; CmLList dlHqEntLnk; - CmLList ulSlotLnk; + CmLList dlSlotLnk; SchDlHqTbCb tbInfo[2]; uint8_t k1; void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */ @@ -279,7 +289,6 @@ struct schDlHqEnt */ typedef struct schGenCb { - uint8_t tmrRes; /*!< Timer resolution */ uint8_t startCellId; /*!< Starting Cell Id */ #ifdef LTE_ADV bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling @@ -304,8 +313,18 @@ typedef struct schPrbAlloc { CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */ uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */ + uint16_t numPrbAlloc; }SchPrbAlloc; + +typedef struct schPdcchAllocInfo +{ + uint8_t cRSetId; + uint8_t ssId; + uint8_t aggLvl; + uint16_t cceIndex; +}SchPdcchAllocInfo; + /** * @brief * scheduler allocationsfor DL per cell. @@ -317,8 +336,7 @@ typedef struct schDlSlotInfo uint8_t ssbIdxSupported; /*!< Max SSB index */ SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */ bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */ - uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */ - uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */ + uint8_t pdcchUe; /*!< UE for which PDCCH Common is scheduled in this slot */ RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/ DciInfo *ulGrant; DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/ @@ -344,13 +362,10 @@ typedef struct schRaCb typedef struct schUlSlotInfo { SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */ - uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */ - bool puschPres; /*!< PUSCH presence field */ - SchPuschInfo *schPuschInfo; /*!< PUSCH info */ - bool pucchPres; /*!< PUCCH presence field */ - SchPucchInfo schPucchInfo; /*!< PUCCH info */ - uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */ - uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */ + bool puschPres; + SchPuschInfo *schPuschInfo[MAX_NUM_UE]; /*!< PUSCH info */ + bool pucchPres; + SchPucchInfo schPucchInfo[MAX_NUM_UE]; /*!< PUCCH info */ }SchUlSlotInfo; /** @@ -463,6 +478,18 @@ typedef struct schDrxUeCb CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/ }SchDrxUeCb; #endif + +typedef struct schPdcchInfo +{ + SchControlRsrcSet *cRSetRef; /*Coreset Cfg reference from SchUeCfgCb*/ + SchSearchSpace *ssRef; /*SearchSpace Cfg reference from SchUeCfgCb*/ + uint16_t totalPrbs; /*Total PRBs configured for this CORESET*/ + uint8_t nrOfPRBPerCce; /*CCE Size*/ + uint8_t totalCceCount; /*Count of CCE in this CORESET*/ + uint8_t cqiIndxAggLvlMap[MAX_NUM_CQI_IDX];/*Agg Level to be used for each CQI Index*/ + uint32_t *y; /*Coefficient variable to calculate CCE Index as per 3gpp Spec 38.213 Sec 10.1*/ +}SchPdcchInfo; + /** * @brief * UE control block @@ -491,6 +518,11 @@ typedef struct schUeCb bool ueDrxInfoPres; SchDrxUeCb drxUeCb; #endif + bool k0K1TblPrsnt; + SchK0K1TimingInfoTbl k0K1InfoTbl; + bool k2TblPrsnt; + SchK2TimingInfoTbl k2InfoTbl; + SchPdcchInfo pdcchInfo[MAX_NUM_CRSET]; }SchUeCb; /** @@ -597,6 +629,40 @@ typedef struct PdschCfg sib1PdschCfg; }SchSib1Cfg; +typedef struct dlTotalPrbUsage +{ + uint16_t numPrbUsedForTx; + uint16_t totalPrbAvailForTx; +}TotalPrbUsage; + +typedef struct +{ + TotalPrbUsage *dlTotalPrbUsage; + TotalPrbUsage *ulTotalPrbUsage; +}SchKpiSupported; + +typedef struct +{ + CmLListCp dlTotPrbUseList; + CmLListCp ulTotPrbUseList; +}SchKpiActive; + +typedef struct schStatsGrp +{ + Inst schInst; + uint64_t subscriptionId; + uint8_t groupId; + uint16_t periodicity; /* In milliseconds */ + CmTimer periodTimer; + SchKpiSupported kpiStats; +}SchStatsGrp; + +typedef struct schStatistics +{ + CmLListCp statsGrpList; + SchKpiActive activeKpiList; +}SchStatistics; + /** * @brief * Cell Control block per cell. @@ -611,6 +677,7 @@ typedef struct schCellCb SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */ SchCellCfg cellCfg; /*!< Cell ocnfiguration */ + uint8_t numerology; bool firstSsbTransmitted; bool firstSib1Transmitted; uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */ @@ -641,12 +708,12 @@ typedef struct schCellCb uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/ }SchCellCb; - -typedef struct schSliceCfg +typedef struct schTimer { - uint8_t numOfSliceConfigured; - SchRrmPolicyOfSlice **listOfSlices; -}SchSliceCfg; + CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ + CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ + uint8_t tmrRes; /*!< Timer resolution */ +}SchTimer; /** * @brief @@ -656,11 +723,11 @@ typedef struct schCb { TskInit schInit; /*!< Task Init info */ SchGenCb genCfg; /*!< General Config info */ - CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ - CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ + SchTimer schTimersInfo; /*!< Sch timer queues and resolution */ SchAllApis allApis[NUM_SCH_TYPE]; /*!