X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.h;h=81fbc042b01f3b1d2abe1dc1571d68477c55d992;hb=e96cb439cd4a7a6f55e3fab7caed978e38bd62b4;hp=5b2da404594101737ff1213efefcb1972a8d151c;hpb=fa6899dae4aee415bbcfd00760b6e2b312ddceec;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 5b2da4045..81fbc042b 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -17,8 +17,6 @@ *******************************************************************************/ /* macros */ -#define SCH_INST_START 1 -#define SCH_MAX_INST 1 #define SCH_MU0_NUM_SLOTS 10 #define SCH_MU1_NUM_SLOTS 20 #define SCH_MU2_NUM_SLOTS 30 @@ -47,7 +45,6 @@ #define NUM_DMRS_SYMBOLS 1 #define DMRS_ADDITIONAL_POS 0 #define SCH_DEFAULT_K1 1 -#define SCH_TQ_SIZE 10 #define SSB_IDX_SUPPORTED 1 #define CRC_FAILED 0 @@ -68,6 +65,8 @@ #define HQ_ACK 0 #define HQ_NACK 1 #define HQ_DTX 2 +#define ROOT_SEQ_LEN_1 139 +#define ROOT_SEQ_LEN_2 839 #ifdef NR_DRX /* As per 38.331 the largest offset which can be used in of size 10240. @@ -76,7 +75,20 @@ #define MAX_DRX_SIZE 512 #endif -#define NUM_SCH_TYPE 1 /*Supported number of Scheduler Algorithm types*/ +#define NUM_SCH_TYPE 2 /*Supported number of Scheduler Algorithm types*/ + +#define SCH_TQ_SIZE 10 + +/*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/ +#define NUM_PRBS_PER_RBG 6 + +/*3GPP 38.214 Table 5.2.2.1-2*/ +#define MAX_NUM_CQI_IDX 16 + +/*3GPP 38.211 Table 7.3.2.1-1*/ +#define MAX_NUM_AGG_LVL 5 + +#define PUCCH_RES_IND 0 typedef struct schDlHqProcCb SchDlHqProcCb; typedef struct schUlHqEnt SchUlHqEnt; @@ -87,7 +99,8 @@ typedef struct schUeCb SchUeCb; typedef enum { - SCH_FCFS + SCH_FCFS, + SCH_SLICE_BASED }SchType; typedef enum @@ -134,6 +147,22 @@ typedef enum HQ_TB_WAITING }SchHqTbState; +#ifdef NR_TDD +typedef enum +{ + DL_SLOT, + UL_SLOT, + FLEXI_SLOT +}SlotConfig; + +typedef enum +{ + DL_SYMBOL, + UL_SYMBOL, + FLEXI_SYMBOL +}SchSymbolConfig; +#endif + /*Following structures to keep record and estimations of PRB allocated for each * LC taking into consideration the RRM policies*/ typedef struct lcInfo @@ -223,7 +252,7 @@ struct schDlHqProcCb SchDlHqEnt *hqEnt; uint8_t maxHqTxPerHqP; CmLList dlHqEntLnk; - CmLList ulSlotLnk; + CmLList dlSlotLnk; SchDlHqTbCb tbInfo[2]; uint8_t k1; void *schSpcDlHqProcCb; /*!< Scheduler specific HARQ Proc CB */ @@ -260,7 +289,6 @@ struct schDlHqEnt */ typedef struct schGenCb { - uint8_t tmrRes; /*!< Timer resolution */ uint8_t startCellId; /*!< Starting Cell Id */ #ifdef LTE_ADV bool forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling @@ -285,8 +313,18 @@ typedef struct schPrbAlloc { CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */ uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */ + uint16_t numPrbAlloc; }SchPrbAlloc; + +typedef struct schPdcchAllocInfo +{ + uint8_t cRSetId; + uint8_t ssId; + uint8_t aggLvl; + uint16_t cceIndex; +}SchPdcchAllocInfo; + /** * @brief * scheduler allocationsfor DL per cell. @@ -298,11 +336,10 @@ typedef struct schDlSlotInfo uint8_t ssbIdxSupported; /*!< Max SSB index */ SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */ bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */ - uint8_t pdcchUe; /*!< UE for which PDCCH is scheduled in this slot */ - uint8_t pdschUe; /*!< UE for which PDSCH is scheduled in this slot */ + uint8_t pdcchUe; /*!< UE for which PDCCH Common is scheduled in this slot */ RarAlloc *rarAlloc[MAX_NUM_UE]; /*!< RAR allocation per UE*/ DciInfo *ulGrant; - DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/ + DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE]; /*!< Dl msg allocation per UE*/ }SchDlSlotInfo; typedef struct schRaCb @@ -325,13 +362,10 @@ typedef struct schRaCb typedef struct schUlSlotInfo { SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */ - uint8_t puschCurrentPrb; /*!< Current PRB for PUSCH allocation */ - bool puschPres; /*!< PUSCH presence field */ - SchPuschInfo *schPuschInfo; /*!< PUSCH info */ - bool pucchPres; /*!< PUCCH presence field */ - SchPucchInfo schPucchInfo; /*!< PUCCH info */ - uint8_t pucchUe; /*!< Store UE id for which PUCCH is scheduled */ - uint8_t puschUe; /*!< Store UE id for which PUSCH is scheduled */ + bool puschPres; + SchPuschInfo *schPuschInfo[MAX_NUM_UE]; /*!< PUSCH info */ + bool pucchPres; + SchPucchInfo schPucchInfo[MAX_NUM_UE]; /*!< PUCCH info */ }SchUlSlotInfo; /** @@ -444,6 +478,18 @@ typedef struct schDrxUeCb CmLList *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/ }SchDrxUeCb; #endif + +typedef struct schPdcchInfo +{ + SchControlRsrcSet *cRSetRef; /*Coreset Cfg reference from SchUeCfgCb*/ + SchSearchSpace *ssRef; /*SearchSpace Cfg reference from SchUeCfgCb*/ + uint16_t totalPrbs; /*Total PRBs configured for this CORESET*/ + uint8_t nrOfPRBPerCce; /*CCE Size*/ + uint8_t totalCceCount; /*Count of CCE in this CORESET*/ + uint8_t cqiIndxAggLvlMap[MAX_NUM_CQI_IDX];/*Agg Level to be used for each CQI Index*/ + uint32_t *y; /*Coefficient variable to calculate CCE Index as per 3gpp Spec 38.213 Sec 10.1*/ +}SchPdcchInfo; + /** * @brief * UE control block @@ -472,6 +518,11 @@ typedef struct schUeCb bool ueDrxInfoPres; SchDrxUeCb drxUeCb; #endif + bool k0K1TblPrsnt; + SchK0K1TimingInfoTbl k0K1InfoTbl; + bool k2TblPrsnt; + SchK2TimingInfoTbl k2InfoTbl; + SchPdcchInfo pdcchInfo[MAX_NUM_CRSET]; }SchUeCb; /** @@ -557,10 +608,61 @@ typedef struct schAllApis void (* SchDeleteUlHqProcCb)(SchUlHqProcCb *hqP); void (* SchScheduleSlot)(SchCellCb *cell, SlotTimingInfo *slotInd, Inst schInst); uint32_t (* SchScheduleDlLc)(SlotTimingInfo pdcchTime, SlotTimingInfo pdschTime, uint8_t pdschNumSymbols, \ - bool isRetx, SchDlHqProcCb **hqP); + uint16_t *startPrb, bool isRetx, SchDlHqProcCb **hqP); uint8_t (* SchScheduleUlLc)(SlotTimingInfo dciTime, SlotTimingInfo puschTime, uint8_t startStmb, \ uint8_t symbLen, bool isRetx, SchUlHqProcCb **hqP); }SchAllApis; + +typedef struct schHqCfgParam +{ + uint8_t maxDlDataHqTx; + uint8_t maxMsg4HqTx; + uint8_t maxUlDataHqTx; +}SchHqCfg; + +typedef struct +{ + /* parameters derived in scheduler */ + uint8_t n0; + BwpCfg bwp; + PdcchCfg sib1PdcchCfg; + PdschCfg sib1PdschCfg; +}SchSib1Cfg; + +typedef struct dlTotalPrbUsage +{ + uint16_t numPrbUsedForTx; + uint16_t totalPrbAvailForTx; +}TotalPrbUsage; + +typedef struct +{ + TotalPrbUsage *dlTotalPrbUsage; + TotalPrbUsage *ulTotalPrbUsage; +}SchKpiSupported; + +typedef struct +{ + CmLListCp dlTotPrbUseList; + CmLListCp ulTotPrbUseList; +}SchKpiActive; + +typedef struct schStatsGrp +{ + Inst schInst; + uint64_t subscriptionId; + uint8_t groupId; + uint16_t periodicity; /* In milliseconds */ + CmTimer periodTimer; + SchKpiSupported kpiStats; +}SchStatsGrp; + +typedef struct schStatistics +{ + CmLListCp statsGrpList; + SchKpiActive activeKpiList; +}SchStatistics; + /** * @brief * Cell Control block per cell. @@ -575,6 +677,7 @@ typedef struct schCellCb SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */ SchCellCfg cellCfg; /*!< Cell ocnfiguration */ + uint8_t numerology; bool firstSsbTransmitted; bool firstSib1Transmitted; uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */ @@ -589,7 +692,7 @@ typedef struct schCellCb #ifdef NR_TDD uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */ uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */ - uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */ + SchSymbolConfig slotCfg[MAX_TDD_PERIODICITY_SLOTS][MAX_SYMB_PER_SLOT]; #endif #ifdef NR_DRX SchDrxCb drxCb[MAX_DRX_SIZE]; /*!< Drx cb*/ @@ -597,14 +700,20 @@ typedef struct schCellCb SchType schAlgoType; /*!< The scheduler type which the cell is configured with.*/ SchAllApis *api; /*!< Reference of sch APIs for this cell based on the SchType*/ void *schSpcCell; /*Ref of Scheduler specific structure*/ + SchHqCfg schHqCfg; + SchK0K1TimingInfoTbl k0K1InfoTbl; + SchK2TimingInfoTbl msg3K2InfoTbl; + SchK2TimingInfoTbl k2InfoTbl; + SchSib1Cfg sib1SchCfg; /* SIB1 config */ + uint8_t maxMsg3Tx; /* MAximum num of msg3 tx*/ }SchCellCb; - -typedef struct schSliceCfg +typedef struct schTimer { - uint8_t numOfSliceConfigured; - SchRrmPolicyOfSlice **listOfSlices; -}SchSliceCfg; + CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ + CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ + uint8_t tmrRes; /*!< Timer resolution */ +}SchTimer; /** * @brief @@ -614,11 +723,11 @@ typedef struct schCb { TskInit schInit; /*!< Task Init info */ SchGenCb genCfg; /*!< General Config info */ - CmTqCp tmrTqCp; /*!< Timer Task Queue Cntrl Point */ - CmTqType tmrTq[SCH_TQ_SIZE]; /*!< Timer Task Queue */ + SchTimer schTimersInfo; /*!< Sch timer queues and resolution */ SchAllApis allApis[NUM_SCH_TYPE]; /*!