X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.h;h=50aae091835e446bc0e9c7a15628ad86b267393a;hb=67b89506e1d6a7a775d5095f390d5dcb610deb86;hp=8734f65cf2ee2d5b84b60e5ca47d05cb45978855;hpb=cad4905437d02b16c3916903a42f501eb8f7b1ac;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h index 8734f65cf..50aae0918 100644 --- a/src/5gnrsch/sch.h +++ b/src/5gnrsch/sch.h @@ -25,33 +25,45 @@ #define SCH_MU3_NUM_SLOTS 40 #define SCH_MU4_NUM_SLOTS 50 #define SCH_MAX_SFN 1024 -#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */ -#define SCH_MIB_TRANS 80 +#ifdef NR_TDD +#define MAX_NUM_RB 275 /* value for numerology 1, 100 MHz */ +#else +#define MAX_NUM_RB 106 /* value for numerology 0, 20 MHz */ +#endif +#define SCH_MIB_TRANS 8 /* MIB transmission as per 38.331 is every 80 ms */ +#define SCH_SIB1_TRANS 16 /* SIB1 transmission as per 38.331 is every 160 ms */ #define SCH_NUM_SC_PRB 12 /* number of SCs in a PRB */ -#define SCH_MAX_SSB_BEAM 4 /* since we are supporting only SCS=15KHz */ -#define SCH_SCS_15KHZ 0 /* numerology 0 and 15Khz */ -#define SCH_SYMBOL_PER_SLOT 14 +#define SCH_MAX_SSB_BEAM 8 /* since we are supporting only SCS=15KHz and 30KHz */ #define SCH_SSB_NUM_SYMB 4 -#define SCH_SSB_NUM_PRB 20 +#define SCH_SSB_NUM_PRB 21 /* One extra PRB as buffer */ #define SCHED_DELTA 1 #define BO_DELTA 1 #define RAR_DELAY 2 #define MSG4_DELAY 1 +#define PDSCH_START_RB 10 +/* Considering pdsch region from 3 to 13, DMRS exclued. + * Overlapping of PDSCH DRMS and PDSCH not supported by Intel L1 */ +#define NUM_PDSCH_SYMBOL 11 #define PUSCH_START_RB 15 -#define PUCCH_NUM_PRB_FORMAT_0 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */ +#define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */ #define SI_RNTI 0xFFFF #define P_RNTI 0xFFFE #define DMRS_MAP_TYPE_A 1 -#define NUM_DMRS_SYMBOLS 12 -#define DMRS_ADDITIONAL_POS 2 +#define NUM_DMRS_SYMBOLS 1 +#define DMRS_ADDITIONAL_POS 0 +#define SCH_DEFAULT_K1 1 +#define SCH_TQ_SIZE 10 +#define SSB_IDX_SUPPORTED 1 #define CRC_FAILED 0 #define CRC_PASSED 1 -#define RLC_HDR_SIZE 3 /* 3 bytes of RLC Header size */ #define MAC_HDR_SIZE 3 /* 3 bytes of MAC Header */ #define UL_GRANT_SIZE 224 +#define PRB_BITMAP_IDX_LEN 64 +#define PRB_BITMAP_MAX_IDX ((MAX_NUM_RB + PRB_BITMAP_IDX_LEN-1) / PRB_BITMAP_IDX_LEN) + typedef struct schCellCb SchCellCb; typedef struct schUeCb SchUeCb; @@ -76,6 +88,13 @@ typedef enum SCH_LC_STATE_ACTIVE }SchLcState; +typedef enum +{ + WINDOW_YET_TO_START, + WITHIN_WINDOW, + WINDOW_EXPIRED +}RaRspWindowStatus; + /** * @brief * Structure holding LTE MAC's General Configuration information. @@ -92,20 +111,36 @@ typedef struct schGenCb #endif }SchGenCb; +typedef struct freePrbBlock +{ + uint16_t numFreePrb; + uint16_t startPrb; + uint16_t endPrb; +}FreePrbBlock; + +/** + * @brief + * PRB allocations for a symbol within a slot + */ +typedef struct schPrbAlloc +{ + CmLListCp freePrbBlockList; /*!< List of continuous blocks for available PRB */ + uint64_t prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX]; /*!< BitMap to store the allocated PRBs */ +}SchPrbAlloc; + /** * @brief * scheduler allocationsfor DL per cell. */ typedef struct schDlSlotInfo { - uint16_t totalPrb; /*!< Number of RBs in the cell */ - uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */ - bool ssbPres; /*!< Flag to determine if SSB is present in this slot */ - uint8_t ssbIdxSupported; /*!< Max SSB index */ - SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */ - bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */ - RarInfo *rarInfo; /*!< RAR info */ - DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */ + SchPrbAlloc prbAlloc; /*!< PRB allocated/available in this slot */ + bool ssbPres; /*!< Flag to determine if SSB is present in this slot */ + uint8_t ssbIdxSupported; /*!< Max SSB index */ + SsbInfo ssbInfo[MAX_SSB_IDX]; /*!< SSB info */ + bool sib1Pres; /*!< Flag to determine if SIB1 is present in this slot */ + RarAlloc *rarAlloc; /*!< RAR allocation */ + DlMsgInfo *dlMsgInfo; /*!< DL dedicated Msg info */ }SchDlSlotInfo; typedef struct schRaCb @@ -119,13 +154,12 @@ typedef struct schRaCb */ typedef struct schUlSlotInfo { - uint16_t totalPrb; /*!< Number of RBs in the cell */ - uint16_t assignedPrb[SCH_SYMBOL_PER_SLOT]; /*!< Num RBs and corresponding symbols allocated */ - uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */ - bool puschPres; /*!< PUSCH presence field */ - SchPuschInfo *schPuschInfo; /*!< PUSCH info */ - bool pucchPres; /*!< PUCCH presence field */ - SchPucchInfo schPucchInfo; /*!< PUCCH info */ + SchPrbAlloc prbAlloc; /*!< PRB allocated/available per symbol */ + uint8_t puschCurrentPrb; /* Current PRB for PUSCH allocation */ + bool puschPres; /*!< PUSCH presence field */ + SchPuschInfo *schPuschInfo; /*!< PUSCH info */ + bool pucchPres; /*!< PUCCH presence field */ + SchPucchInfo schPucchInfo; /*!< PUCCH info */ }SchUlSlotInfo; /** @@ -143,7 +177,9 @@ typedef struct schLcCtxt uint8_t lcId; // logical Channel ID uint8_t lcp; // logical Channel Prioritization SchLcState lcState; - uint16_t bo; + uint32_t bo; + uint16_t pduSessionId; /*Pdu Session Id*/ + Snssai *snssai; /*S-NSSAI assoc with LCID*/ }SchDlLcCtxt; typedef struct schDlCb @@ -161,6 +197,8 @@ typedef struct schUlLcCtxt uint8_t schReqId; uint8_t pbr; // prioritisedBitRate uint8_t bsd; // bucketSizeDuration + uint16_t pduSessionId; /*Pdu Session Id*/ + Snssai *snssai; /*S-NSSAI assoc with LCID*/ }SchUlLcCtxt; typedef struct schUlCb @@ -169,6 +207,21 @@ typedef struct schUlCb SchUlLcCtxt ulLcCtxt[MAX_NUM_LC]; }SchUlCb; +typedef struct schUeCfgCb +{ + uint16_t cellId; + uint16_t crnti; + bool macCellGrpCfgPres; + SchMacCellGrpCfg macCellGrpCfg; + bool phyCellGrpCfgPres; + SchPhyCellGrpCfg phyCellGrpCfg; + bool spCellCfgPres; + SchSpCellCfg spCellCfg; + SchAmbrCfg *ambrCfg; + SchModulationInfo dlModInfo; + SchModulationInfo ulModInfo; +}SchUeCfgCb; + /** * @brief * UE control block @@ -177,7 +230,7 @@ typedef struct schUeCb { uint16_t ueIdx; uint16_t crnti; - SchUeCfg ueCfg; + SchUeCfgCb ueCfg; SchUeState state; SchCellCb *cellCb; bool srRcvd; @@ -186,6 +239,18 @@ typedef struct schUeCb SchDlCb dlInfo; }SchUeCb; +/** + * @brief + * RA Request Info + */ +typedef struct schRaReq +{ + uint32_t raRnti; + RachIndInfo *rachInd; + SlotTimingInfo winStartTime; + SlotTimingInfo winEndTime; +}SchRaReq; + /** * @brief * Cell Control block per cell. @@ -196,16 +261,24 @@ typedef struct schCellCb Inst instIdx; /*!< Index of the scheduler instance */ Inst macInst; /*!< Index of the MAC instance */ uint8_t numSlots; /*!< Number of slots in current frame */ - SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/ + SlotTimingInfo slotInfo; /*!< SFN, Slot info being processed*/ SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */ SchCellCfg cellCfg; /*!< Cell ocnfiguration */ + bool firstSsbTransmitted; + bool firstSib1Transmitted; uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!