X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.h;h=39aa04249ae2a234045fbe9dc17f09279c096833;hb=73da3ffdd36c5ade0c1cccbe7d2ad4d457897b2f;hp=9184ed99126b676a27a2ad131ce9a17be6075768;hpb=3fcf32e0ea0cbb4e83cbd3ece7a16e692fedcedd;p=o-du%2Fl2.git

diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h
index 9184ed991..39aa04249 100644
--- a/src/5gnrsch/sch.h
+++ b/src/5gnrsch/sch.h
@@ -17,8 +17,6 @@
  *******************************************************************************/
 
 /* macros */
-#define SCH_INST_START 1
-#define SCH_MAX_INST 1
 #define SCH_MU0_NUM_SLOTS 10 
 #define SCH_MU1_NUM_SLOTS 20 
 #define SCH_MU2_NUM_SLOTS 30 
@@ -47,7 +45,6 @@
 #define NUM_DMRS_SYMBOLS 1
 #define DMRS_ADDITIONAL_POS 0
 #define SCH_DEFAULT_K1 1
-#define SCH_TQ_SIZE 10
 #define SSB_IDX_SUPPORTED 1
 
 #define CRC_FAILED 0
@@ -80,6 +77,17 @@
 
 #define NUM_SCH_TYPE 2  /*Supported number of Scheduler Algorithm types*/
 
+#define SCH_TQ_SIZE 10
+
+/*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/
+#define NUM_PRBS_PER_RBG 6 
+
+/*3GPP 38.214 Table 5.2.2.1-2*/
+#define MAX_NUM_CQI_IDX 16
+
+/*3GPP 38.211 Table 7.3.2.1-1*/
+#define MAX_NUM_AGG_LVL 5
+
 typedef struct schDlHqProcCb SchDlHqProcCb;
 typedef struct schUlHqEnt SchUlHqEnt;
 typedef struct schRaReq SchRaReq;
@@ -279,7 +287,6 @@ struct schDlHqEnt
  */
 typedef struct schGenCb
 {
-   uint8_t         tmrRes;           /*!< Timer resolution */
    uint8_t         startCellId;      /*!< Starting Cell Id */
 #ifdef LTE_ADV
    bool            forceCntrlSrbBoOnPCel; /*!< value 1 means force scheduling
@@ -304,6 +311,7 @@ typedef struct schPrbAlloc
 {
    CmLListCp freePrbBlockList;           /*!< List of continuous blocks for available PRB */
    uint64_t  prbBitMap[ MAX_SYMB_PER_SLOT][PRB_BITMAP_MAX_IDX];  /*!< BitMap to store the allocated PRBs */
+   uint16_t  numPrbAlloc;
 }SchPrbAlloc;
 
 /**
@@ -317,8 +325,7 @@ typedef struct schDlSlotInfo
    uint8_t      ssbIdxSupported;          /*!< Max SSB index */
    SsbInfo      ssbInfo[MAX_SSB_IDX];     /*!< SSB info */
    bool         sib1Pres;                 /*!< Flag to determine if SIB1 is present in this slot */
-   uint8_t      pdcchUe;                  /*!< UE for which PDCCH is scheduled in this slot */
-   uint8_t      pdschUe;                  /*!< UE for which PDSCH is scheduled in this slot */
+   uint8_t      pdcchUe;                  /*!< UE for which PDCCH Common is scheduled in this slot */
    RarAlloc     *rarAlloc[MAX_NUM_UE];    /*!< RAR allocation per UE*/
    DciInfo      *ulGrant;
    DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE];  /*!< Dl msg allocation per UE*/
@@ -463,6 +470,18 @@ typedef struct  schDrxUeCb
    CmLList   *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
 }SchDrxUeCb;
 #endif
+
+typedef struct schPdcchInfo
+{
+   SchControlRsrcSet *cRSetRef; /*Coreset Cfg reference from SchUeCfgCb*/
+   SchSearchSpace    *ssRef;    /*SearchSpace Cfg reference from SchUeCfgCb*/
+   uint16_t          totalPrbs; /*Total PRBs configured for this CORESET*/
+   uint8_t           nrOfPRBPerCce; /*CCE Size*/
+   uint8_t           totalCceCount; /*Count of CCE in this CORESET*/
+   uint8_t           cqiIndxAggLvlMap[MAX_NUM_CQI_IDX];/*Agg Level to be used for each CQI Index*/
+   uint32_t          *y; /*Coefficient variable to calculate CCE Index as per 3gpp Spec 38.213 Sec 10.1*/
+}SchPdcchInfo;
+
 /**
  * @brief
  * UE control block
@@ -495,6 +514,7 @@ typedef struct schUeCb
    SchK0K1TimingInfoTbl k0K1InfoTbl;
    bool                 k2TblPrsnt;
    SchK2TimingInfoTbl   k2InfoTbl;
+   SchPdcchInfo         pdcchInfo[MAX_NUM_CRSET];
 }SchUeCb;
 
 /**
@@ -601,6 +621,40 @@ typedef struct
    PdschCfg  sib1PdschCfg;
 }SchSib1Cfg;
 
+typedef struct dlTotalPrbUsage
+{
+   uint16_t numPrbUsedForTx;
+   uint16_t totalPrbAvailForTx;
+}TotalPrbUsage;
+
+typedef struct 
+{
+   TotalPrbUsage *dlTotalPrbUsage;
+   TotalPrbUsage *ulTotalPrbUsage;
+}SchKpiSupported;
+
+typedef struct
+{
+   CmLListCp  dlTotPrbUseList;
+   CmLListCp  ulTotPrbUseList;
+}SchKpiActive;
+
+typedef struct schStatsGrp
+{
+   Inst       schInst;
+   uint64_t   subscriptionId;
+   uint8_t    groupId;
+   uint16_t   periodicity;  /* In milliseconds */
+   CmTimer    periodTimer;
+   SchKpiSupported kpiStats;
+}SchStatsGrp;
+
+typedef struct schStatistics
+{
+   CmLListCp     statsGrpList;
+   SchKpiActive  activeKpiList;
+}SchStatistics;
+
 /**
  * @brief
  * Cell Control block per cell.
@@ -615,6 +669,7 @@ typedef struct schCellCb
    SchDlSlotInfo **schDlSlotInfo;                   /*!< SCH resource allocations in DL */
    SchUlSlotInfo **schUlSlotInfo;                   /*!< SCH resource allocations in UL */
    SchCellCfg    cellCfg;                           /*!< Cell ocnfiguration */
+   uint8_t       numerology;
    bool          firstSsbTransmitted;
    bool          firstSib1Transmitted;
    uint8_t       ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!< start symbol per SSB beam */
@@ -645,6 +700,12 @@ typedef struct schCellCb
    uint8_t              maxMsg3Tx;         /* MAximum num of msg3 tx*/
 }SchCellCb;
 
+typedef struct schTimer
+{
+   CmTqCp       tmrTqCp;               /*!< Timer Task Queue Cntrl Point */
+   CmTqType     tmrTq[SCH_TQ_SIZE];    /*!< Timer Task Queue */
+   uint8_t      tmrRes;              /*!< Timer resolution */
+}SchTimer;
 
 /**
  * @brief
@@ -654,11 +715,11 @@ typedef struct schCb
 {
    TskInit                schInit;               /*!< Task Init info */
    SchGenCb               genCfg;                /*!< General Config info */
-   CmTqCp                 tmrTqCp;               /*!< Timer Task Queue Cntrl Point */
-   CmTqType               tmrTq[SCH_TQ_SIZE];    /*!< Timer Task Queue */
+   SchTimer               schTimersInfo;         /*!< Sch timer queues and resolution */
    SchAllApis             allApis[NUM_SCH_TYPE]; /*!<List of All Scheduler Type dependent Function pointers*/
    SchCellCb              *cells[MAX_NUM_CELL];  /* Array to store cellCb ptr */
    CmLListCp              sliceCfg;              /* Linklist to Store Slice configuration */
+   SchStatistics          statistics;            /* Statistics configuration and calculated values */
 }SchCb;
 
 /* Declaration for scheduler control blocks */
@@ -741,6 +802,8 @@ LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
                       uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
+uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue);
+bool schDlCandidateSelection(SchUeCb *ue,  SlotTimingInfo slotTime);
 
 /*Paging Functions*/
 void schProcPagingCfg(SchCellCb *cell);
@@ -772,6 +835,14 @@ void schUpdateHarqFdbk(SchUeCb *ueCb, uint8_t numHarq, uint8_t *harqPayload,Slot
 uint8_t schFillUlDciForMsg3Retx(SchRaCb *raCb, SchPuschInfo *puschInfo, DciInfo *dciInfo);
 bool schGetMsg3K2(SchCellCb *cell, SchUlHqProcCb* msg3HqProc, uint16_t dlTime, SlotTimingInfo *msg3Time, bool isRetx);
 void schMsg4Complete(SchUeCb *ueCb);
+
+/* Statistics Function */
+uint8_t SchProcStatsReq(Pst *pst, SchStatsReq *statsReq);
+uint8_t SchSendStatsIndToMac(Inst inst, SchStatsInd  *statsInd);
+uint8_t schCalcAndSendGrpStats(SchStatsGrp *grpInfo);
+uint8_t SchProcStatsDeleteReq(Pst *pst, SchStatsDeleteReq *statsDeleteReq);
+uint8_t SchProcStatsModificationReq(Pst *pst, SchStatsModificationReq *statsModificationReq);
+void deleteStatsGrpInfo(Inst inst, SchStatsGrp *statsGrpInfo);
 /**********************************************************************
   End of file
  **********************************************************************/