X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.c;h=ebdab07f65b4d5e4771eb577bd8f53b78375c8dc;hb=e44180890b286bf1f78cd8f3867092f0914cccec;hp=1b1daed427922e2c4b9f9c1a69cbcb089a786ce5;hpb=0381f5c0027b27b357afa0c02f157fc1de85f2a8;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 1b1daed42..ebdab07f6 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -123,7 +123,7 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) uint16_t ret = LCM_REASON_NOT_APPL; Inst inst = (dInst - SCH_INST_START); - printf("\nEntered SchInstCfg()"); + DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()"); /* Check if Instance Configuration is done already */ if (schCb[inst].schInit.cfgDone == TRUE) { @@ -149,26 +149,26 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable; #endif schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId; -#if 0 + /* Initialzie the timer queue */ - memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE); + memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE); /* Initialize the timer control point */ memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp)); schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE; /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */ - /* Timer Registration request to SSI */ + /* Timer Registration request to system services */ if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst, (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK) { - RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to " + DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to " "register timer."); return (LCM_REASON_MEM_NOAVAIL); } -#endif + /* Set Config done in TskInit */ schCb[inst].schInit.cfgDone = TRUE; - printf("\nScheduler gen config done"); + DU_LOG("\nINFO --> SCH : Scheduler gen config done"); return ret; } @@ -200,12 +200,12 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) if(pst->dstInst < SCH_INST_START) { - DU_LOG("\nInvalid inst ID"); - DU_LOG("\nSchProcGenCfgReq(): " + DU_LOG("\nERROR --> SCH : Invalid inst ID"); + DU_LOG("\nERROR --> SCH : SchProcGenCfgReq(): " "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START); return ROK; } - printf("\nReceived scheduler gen config"); + DU_LOG("\nINFO --> SCH : Received scheduler gen config"); /* Fill the post structure for sending the confirmation */ memset(&cfmPst, 0 , sizeof(Pst)); SchFillCfmPst(pst, &cfmPst, cfg); @@ -226,7 +226,7 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) default: ret = LCM_PRIM_NOK; reason = LCM_REASON_INVALID_ELMNT; - DU_LOG("\nInvalid Elmnt=%d", cfg->hdr.elmId.elmnt); + DU_LOG("\nERROR --> SCH : Invalid Elmnt=%d", cfg->hdr.elmId.elmnt); break; } @@ -288,7 +288,7 @@ uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd) uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd) { Inst inst = pst->dstInst-SCH_INST_START; - DU_LOG("\nSCH : Received Rach indication"); + DU_LOG("\nINFO --> SCH : Received Rach indication"); schProcessRachInd(rachInd, inst); return ROK; } @@ -315,21 +315,235 @@ uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd) switch(crcInd->crcInd[0]) { case CRC_FAILED: - DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]"); + DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [FAILURE]"); break; case CRC_PASSED: - DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]"); + DU_LOG("\nDEBUG --> SCH : Received CRC indication. CRC Status [PASS]"); break; default: - DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]); + DU_LOG("\nDEBUG --> SCH : Invalid CRC state %d", crcInd->crcInd[0]); return RFAILED; } return ROK; } +#ifdef NR_TDD +/** + *@brief Returns TDD periodicity in micro seconds + * + * @details + * + * Function : schGetPeriodicityInMsec + * + * This API retunrs TDD periodicity in micro seconds + * + * @param[in] DlUlTxPeriodicity + * @return periodicityInMsec + * **/ + +uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod) +{ + uint16_t periodicityInMsec = 0; + switch(tddPeriod) + { + case TX_PRDCTY_MS_0P5: + { + periodicityInMsec = 500; + break; + } + case TX_PRDCTY_MS_0P625: + { + periodicityInMsec = 625; + break; + } + case TX_PRDCTY_MS_1: + { + periodicityInMsec = 1000; + break; + } + case TX_PRDCTY_MS_1P25: + { + periodicityInMsec = 1250; + break; + } + case TX_PRDCTY_MS_2: + { + periodicityInMsec = 2000; + break; + } + case TX_PRDCTY_MS_2P5: + { + periodicityInMsec = 2500; + break; + } + case TX_PRDCTY_MS_5: + { + periodicityInMsec = 5000; + break; + } + case TX_PRDCTY_MS_10: + { + periodicityInMsec = 10000; + break; + } + default: + { + DU_LOG("\nERROR --> SCH : Invalid DlUlTxPeriodicity:%d", tddPeriod); + } + } + + return periodicityInMsec; +} + + +/** + * @brief init TDD slot config + * + * @details + * + * Function : schInitTddSlotCfg + * + * This API is invoked after receiving schCellCfg + * + * @param[in] schCellCb *cell + * @param[in] SchCellCfg *schCellCfg + * @return void + **/ +void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg) +{ + uint16_t periodicityInMicroSec = 0; + int8_t slotIdx, symbIdx; + + periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod); + cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000; + cell->slotFrmtBitMap = 0; + cell->symbFrmtBitMap = 0; + for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--) + { + symbIdx = 0; + /* If the first and last symbol are the same, the entire slot is the same type */ + if((schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] == schCellCfg->tddCfg.slotCfg[slotIdx][MAX_SYMB_PER_SLOT-1]) && + schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx] != FLEXI_SLOT) + { + switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx]) + { + case DL_SLOT: + { + /*BitMap to be set to 00 */ + cell->slotFrmtBitMap = (cell->slotFrmtBitMap<<2); + break; + } + case UL_SLOT: + { + /*BitMap to be set to 01 */ + cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT)); + break; + } + default: + DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg"); + } + continue; + } + /* slot config is flexible. First set slotBitMap to 10 */ + cell->slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT)); + + /* Now set symbol bitmap */ + for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--) + { + switch(schCellCfg->tddCfg.slotCfg[slotIdx][symbIdx]) + { + case DL_SLOT: + { + /*symbol BitMap to be set to 00 */ + cell->symbFrmtBitMap = (cell->symbFrmtBitMap<<2); + break; + } + case UL_SLOT: + { + /*symbol BitMap to be set to 01 */ + cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT)); + break; + } + case FLEXI_SLOT: + { + /*symbol BitMap to be set to 10 */ + cell->symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT)); + break; + } + default: + DU_LOG("\nERROR --> SCH : Invalid slot Config in schInitTddSlotCfg"); + } + } + } +} +#endif /** - * @brief inti cellCb based on cellCfg + * @brief Fill SSB start symbol + * + * @details + * + * Function : fillSsbStartSymb + * + * This API stores SSB start index per beam + * + * @param[in] SchCellCb *cellCb + * @return int + * -# ROK + * -# RFAILED + **/ +void fillSsbStartSymb(SchCellCb *cellCb) +{ + uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM]; + + scs = cellCb->cellCfg.ssbSchCfg.scsCommon; + + memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + symbIdx = 0; + /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ + switch(scs) + { + case SCS_15KHZ: + { + if(cellCb->cellCfg.dlFreq <= 300000) + cnt = 2;/* n = 0, 1 */ + else + cnt = 4; /* n = 0, 1, 2, 3 */ + for(uint8_t idx=0; idxcellCfg.dlFreq <= 300000) + cnt = 1;/* n = 0 */ + else + cnt = 2; /* n = 0, 1 */ + for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); + } + memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); + +} + + +/** + * @brief init cellCb based on cellCfg * * @details * @@ -345,28 +559,65 @@ uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd) **/ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) { - SchCellCb *cell; + SchCellCb *cell= NULLP; SCH_ALLOC(cell, sizeof(SchCellCb)); if(!cell) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } cell->cellId = schCellCfg->cellId; cell->instIdx = inst; - switch(schCellCfg->ssbSchCfg.scsCommon) + switch(schCellCfg->numerology) { - case SCH_SCS_15KHZ: + case SCH_NUMEROLOGY_0: + { + cell->numSlots = SCH_MU0_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_1: + { + cell->numSlots = SCH_MU1_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_2: { - cell->numSlots = SCH_NUM_SLOTS; + cell->numSlots = SCH_MU2_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_3: + { + cell->numSlots = SCH_MU3_NUM_SLOTS; + } + break; + case SCH_NUMEROLOGY_4: + { + cell->numSlots = SCH_MU4_NUM_SLOTS; } break; default: - DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon); + DU_LOG("\nERROR --> SCH : Numerology %d not supported", schCellCfg->numerology); } +#ifdef NR_TDD + schInitTddSlotCfg(cell, schCellCfg); +#endif - for(uint8_t idx=0; idxschDlSlotInfo, cell->numSlots * sizeof(SchDlSlotInfo*)); + if(!cell->schDlSlotInfo) + { + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schDlSlotInfo"); + return RFAILED; + } + + SCH_ALLOC(cell->schUlSlotInfo, cell->numSlots * sizeof(SchUlSlotInfo*)); + if(!cell->schUlSlotInfo) + { + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb for schUlSlotInfo"); + return RFAILED; + } + + for(uint8_t idx=0; idxnumSlots; idx++) { SchDlSlotInfo *schDlSlotInfo; SchUlSlotInfo *schUlSlotInfo; @@ -375,7 +626,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) SCH_ALLOC(schDlSlotInfo, sizeof(SchDlSlotInfo)); if(!schDlSlotInfo) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } @@ -383,7 +634,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) SCH_ALLOC(schUlSlotInfo, sizeof(SchUlSlotInfo)); if(!schUlSlotInfo) { - DU_LOG("\nMemory allocation failed in schInitCellCb"); + DU_LOG("\nERROR --> SCH : Memory allocation failed in schInitCellCb"); return RFAILED; } @@ -394,9 +645,12 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) cell->schUlSlotInfo[idx] = schUlSlotInfo; } + cell->firstSsbTransmitted = false; + cell->firstSib1Transmitted = false; + fillSsbStartSymb(cell); schCb[inst].cells[inst] = cell; - DU_LOG("\nCell init completed for cellId:%d", cell->cellId); + DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId); return ROK; } @@ -410,14 +664,14 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) * * Fill SIB1 configuration * - * @param[in] Inst schInst : scheduler instance + * @param[in] uint8_t bandwidth : total available bandwidth + * uint8_t numSlots : total slots per SFN * SchSib1Cfg *sib1SchCfg : cfg to be filled * uint16_t pci : physical cell Id * uint8_t offsetPointA : offset * @return void **/ -void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ - uint8_t offsetPointA) +void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; @@ -432,7 +686,8 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ uint8_t slotIndex = 0; uint8_t FreqDomainResource[6] = {0}; uint16_t tbSize = 0; - uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ + uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */ + uint8_t ssbIdx = 0; PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); @@ -458,14 +713,29 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe * assuming u = 0, i = 0, numSlotsPerSubframe = 10 * Also, from this configuration, coreset0 is only on even subframe */ - slotIndex = ((oValue * 1) + (0 * mValue)) % 10; + slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots; sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); /* fill BWP */ - bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */ + switch(bandwidth) + { + case BANDWIDTH_20MHZ: + { + bwp->freqAlloc.numPrb = TOTAL_PRB_20MHZ_MU0; + } + break; + case BANDWIDTH_100MHZ: + { + bwp->freqAlloc.numPrb = TOTAL_PRB_100MHZ_MU1; + } + break; + default: + DU_LOG("\nERROR --> SCH : Bandwidth %d not supported", bandwidth); + + } bwp->freqAlloc.startPrb = 0; bwp->subcarrierSpacing = 0; /* 15Khz */ bwp->cyclicPrefix = 0; /* normal */ @@ -511,14 +781,14 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs; pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */ pdsch->codeword[cwCount].rvIndex = 0; - tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen); + tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN); pdsch->codeword[cwCount].tbSize = tbSize; } pdsch->dataScramblingId = pci; pdsch->numLayers = 1; pdsch->transmissionScheme = 0; pdsch->refPoint = 0; - pdsch->dmrs.dlDmrsSymbPos = 2; + pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */ pdsch->dmrs.dlDmrsScramblingId = pci; pdsch->dmrs.scid = 0; @@ -529,12 +799,13 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pdsch->pdschTimeAlloc.rowIndex = 1; - pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */ + /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */ + pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols; pdsch->beamPdschInfo.numPrgs = 1; pdsch->beamPdschInfo.prgSize = 1; @@ -546,51 +817,6 @@ void fillSchSib1Cfg(Inst schInst, SchSib1Cfg *sib1SchCfg, uint16_t pci, \ } -/** - * @brief Fill SSB start symbol - * - * @details - * - * Function : fillSsbStartSymb - * - * This API stores SSB start index per beam - * - * @param[in] SchCellCb *cellCb - * @return int - * -# ROK - * -# RFAILED - **/ -void fillSsbStartSymb(SchCellCb *cellCb) -{ - uint8_t cnt, scs; - - scs = cellCb->cellCfg.ssbSchCfg.scsCommon; - uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; - - memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ - switch(scs) - { - case SCH_SCS_15KHZ: - { - uint8_t symbIdx=0; - cnt = 2;/* n = 0, 1 for SCS = 15KHz */ - for(uint8_t idx=0; idxssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); - -} - /** * @brief cell config from MAC to SCH. * @@ -619,10 +845,8 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg( - inst, - &(schCellCfg->sib1SchCfg), - schCellCfg->phyCellId, + fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, + &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); @@ -665,40 +889,68 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) uint8_t lcId = 0; uint16_t ueIdx = 0; uint16_t slot; +#ifdef NR_TDD + uint16_t slotIdx = 0; +#endif SchUeCb *ueCb = NULLP; SchCellCb *cell = NULLP; SchDlSlotInfo *schDlSlotInfo = NULLP; Inst inst = pst->dstInst-SCH_INST_START; - DU_LOG("\nSCH : Received RLC BO Status indication"); + DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication"); cell = schCb[inst].cells[inst]; + if(cell == NULLP) + { + DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): Cell does not exists"); + return RFAILED; + } + GET_UE_IDX(dlBoInfo->crnti, ueIdx); ueCb = &cell->ueCb[ueIdx-1]; lcId = dlBoInfo->lcId; if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \ - (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID)) + (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID)) { SET_ONE_BIT(ueIdx, cell->boIndBitMap); ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume; } else if(lcId != SRB0_LCID) { - DU_LOG("\nSCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId); + DU_LOG("\nERROR --> SCH : Invalid LC Id %d in MacSchDlRlcBoInfo", lcId); return RFAILED; } - slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % SCH_NUM_SLOTS; + slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots; +#ifdef NR_TDD + while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT) + { + slot = (slot + 1)%cell->numSlots; + slotIdx++; + if(slotIdx==cell->numSlots) + { + DU_LOG("\nERROR --> SCH : No DL Slot available"); + return RFAILED; + } + } +#endif + schDlSlotInfo = cell->schDlSlotInfo[slot]; + if(schDlSlotInfo == NULLP) + { + DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): schDlSlotInfo does not exists"); + return RFAILED; + } SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo)); - if(!schDlSlotInfo->dlMsgInfo) + if(schDlSlotInfo->dlMsgInfo == NULLP) { - DU_LOG("\nSCH : Memory allocation failed for dlMsgInfo"); + DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo"); schDlSlotInfo = NULL; return RFAILED; } + schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti; schDlSlotInfo->dlMsgInfo->ndi = 1; schDlSlotInfo->dlMsgInfo->harqProcNum = 0; @@ -708,8 +960,10 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0; schDlSlotInfo->dlMsgInfo->dciFormatId = 1; if(lcId == SRB0_LCID) + { schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true; - + schDlSlotInfo->dlMsgInfo->dlMsgPduLen = dlBoInfo->dataVolume; + } return ROK; } @@ -737,7 +991,7 @@ uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd) SchUeCb *ueCb = NULLP; uint8_t lcgIdx; - DU_LOG("\nSCH : Received BSR"); + DU_LOG("\nDEBUG --> SCH : Received BSR"); cellCb = schCb[schInst].cells[schInst]; ueCb = schGetUeCb(cellCb, bsrInd->crnti); @@ -774,7 +1028,7 @@ uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd) SchUeCb *ueCb; SchCellCb *cellCb = schCb[inst].cells[inst]; - DU_LOG("\nSCH : Received SR"); + DU_LOG("\nDEBUG --> SCH : Received SR"); ueCb = schGetUeCb(cellCb, uciInd->crnti);