X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.c;h=5c8d88993c7c0143c3ea676a78849033dfabd9fe;hb=d74291a3d7dadc783460e134b0e24f2b9ae07b2a;hp=16495af9d7e6f34a77ee6d79ca26470b6ee74926;hpb=0bdf00d1edf579ee8b5841e1a80d48d9bb91c7e8;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 16495af9d..5c8d88993 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -149,15 +149,15 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable; #endif schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId; -#if 0 + /* Initialzie the timer queue */ - memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE); + memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE); /* Initialize the timer control point */ memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp)); schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE; /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */ - /* Timer Registration request to SSI */ + /* Timer Registration request to system services */ if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst, (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK) { @@ -165,7 +165,7 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) "register timer."); return (LCM_REASON_MEM_NOAVAIL); } -#endif + /* Set Config done in TskInit */ schCb[inst].schInit.cfgDone = TRUE; DU_LOG("\nINFO --> SCH : Scheduler gen config done"); @@ -407,9 +407,7 @@ uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod) * * @param[in] schCellCb *cell * @param[in] SchCellCfg *schCellCfg - * @return int - * -# ROK - * -# RFAILED + * @return void **/ void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg) { @@ -418,7 +416,6 @@ void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg) int8_t slotIdx, symbIdx; periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod); - schCellCfg->numerology = 1; //TODO: Remove this cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000; cell->slotFrmtBitMap = 0; cell->symbFrmtBitMap = 0; @@ -514,6 +511,69 @@ cell->slotFrmtBitMap = 0; } #endif +/** + * @brief Fill SSB start symbol + * + * @details + * + * Function : fillSsbStartSymb + * + * This API stores SSB start index per beam + * + * @param[in] SchCellCb *cellCb + * @return int + * -# ROK + * -# RFAILED + **/ +void fillSsbStartSymb(SchCellCb *cellCb) +{ + uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM]; + + scs = cellCb->cellCfg.ssbSchCfg.scsCommon; + + memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + symbIdx = 0; + /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ + switch(scs) + { + case SCS_15KHZ: + { + if(cellCb->cellCfg.dlFreq <= 300000) + cnt = 2;/* n = 0, 1 */ + else + cnt = 4; /* n = 0, 1, 2, 3 */ + for(uint8_t idx=0; idxcellCfg.dlFreq <= 300000) + cnt = 1;/* n = 0 */ + else + cnt = 2; /* n = 0, 1 */ + for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); + } + memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); + +} + /** * @brief init cellCb based on cellCfg @@ -618,6 +678,9 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) cell->schUlSlotInfo[idx] = schUlSlotInfo; } + cell->firstSsbTransmitted = false; + cell->firstSib1Transmitted = false; + fillSsbStartSymb(cell); schCb[inst].cells[inst] = cell; DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId); @@ -641,7 +704,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) * uint8_t offsetPointA : offset * @return void **/ -void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) +void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; @@ -657,6 +720,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint8_t FreqDomainResource[6] = {0}; uint16_t tbSize = 0; uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ + uint8_t ssbIdx = 0; PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); @@ -682,7 +746,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe * assuming u = 0, i = 0, numSlotsPerSubframe = 10 * Also, from this configuration, coreset0 is only on even subframe */ - slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots; + slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots; sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ @@ -768,7 +832,7 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ @@ -785,51 +849,6 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, } -/** - * @brief Fill SSB start symbol - * - * @details - * - * Function : fillSsbStartSymb - * - * This API stores SSB start index per beam - * - * @param[in] SchCellCb *cellCb - * @return int - * -# ROK - * -# RFAILED - **/ -void fillSsbStartSymb(SchCellCb *cellCb) -{ - uint8_t cnt, scs; - - scs = cellCb->cellCfg.ssbSchCfg.scsCommon; - uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; - - memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ - switch(scs) - { - case SCH_SCS_15KHZ: - { - uint8_t symbIdx=0; - cnt = 2;/* n = 0, 1 for SCS = 15KHz */ - for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); - } - memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); - -} - /** * @brief cell config from MAC to SCH. * @@ -858,7 +877,7 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots, + fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg));