X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.c;h=27ed26cf77eee70f1a8a28de7c03d9577b0a70fa;hb=55295b31a7e2765d934d238e9530342a7ffec602;hp=ce9bdb1a2528ff05288b32d6e4ecf4a265601662;hpb=5ea4c59cb4dd37164953218b0bd355284e11d22c;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index ce9bdb1a2..27ed26cf7 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -63,9 +63,12 @@ #include "du_app_mac_inf.h" #include "mac_sch_interface.h" #include "sch.h" +#include "sch_utils.h" #include "du_log.h" +#include "common_def.h" extern SchCb schCb[SCH_MAX_INST]; +void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm); /* local defines */ SchCellCfgCfmFunc SchCellCfgCfmOpts[] = { @@ -74,6 +77,7 @@ SchCellCfgCfmFunc SchCellCfgCfmOpts[] = packSchCellCfgCfm /* LWLC */ }; + /** * @brief Task Initiation function. * @@ -302,6 +306,65 @@ SlotIndInfo *slotInd RETVALUE(ROK); } /* macSchSlotInd */ +/******************************************************************* + * + * @brief Processes Rach indication from MAC + * + * @details + * + * Function : macSchRachInd + * + * Functionality: + * Processes Rach indication from MAC + * + * @params[in] + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +int macSchRachInd(Pst *pst, RachIndInfo *rachInd) +{ + Inst inst = pst->dstInst-SCH_INST_START; + DU_LOG("\nSCH : Received Rach indication"); + schProcessRachInd(rachInd, inst); + return ROK; +} + +/******************************************************************* + * + * @brief Processes CRC indication from MAC + * + * @details + * + * Function : macSchCrcInd + * + * Functionality: + * Processes CRC indication from MAC + * + * @params[in] Post structure + * Crc Indication + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +int macSchCrcInd(Pst *pst, CrcIndInfo *crcInd) +{ + switch(crcInd->crcInd[0]) + { + case CRC_FAILED: + DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]"); + break; + case CRC_PASSED: + DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]"); + break; + default: + DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]); + return RFAILED; + } + return ROK; +} + + /** * @brief inti cellCb based on cellCfg * @@ -329,7 +392,7 @@ int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg) cell->cellId = schCellCfg->cellId; cell->instIdx = inst; - switch(schCellCfg->scsCommon) + switch(schCellCfg->ssbSchCfg.scsCommon) { case SCH_SCS_15KHZ: { @@ -337,39 +400,233 @@ int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg) } break; default: - DU_LOG("\nSCS %d not supported", schCellCfg->scsCommon); + DU_LOG("\nSCS %d not supported", schCellCfg->ssbSchCfg.scsCommon); } for(uint8_t idx=0; idxtotalPrb = ((schCellCfg->bandwidth * - 1000)/(schCellCfg->scsCommon))/SCH_NUM_SC_PRB; - for(uint8_t itr=0; itrtotalPrb = schUlSlotInfo->totalPrb = MAX_NUM_RB; + + for(uint8_t itr=0; itrassignedPrb[itr] = 0; + schDlSlotInfo->assignedPrb[itr] = 0; + schUlSlotInfo->assignedPrb[itr] = 0; } + schUlSlotInfo->schPuschInfo = NULLP; + for(uint8_t itr=0; itrssbInfo[itr], 0, sizeof(SsbInfo)); + memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo)); } - cell->dlAlloc[idx] = schDlAlloc; + cell->schDlSlotInfo[idx] = schDlSlotInfo; + cell->schUlSlotInfo[idx] = schUlSlotInfo; + } - schCb[inst].cells[inst] = cell; //Sphoorthi TODO: check if this works + schCb[inst].cells[inst] = cell; DU_LOG("\nCell init completed for cellId:%d", cell->cellId); return ROK; } +void fillSchSib1Cfg( +Inst schInst, +SchSib1Cfg *sib1SchCfg, +uint16_t pci, +uint8_t offsetPointA +) +{ + uint8_t coreset0Idx = 0; + uint8_t searchSpace0Idx = 0; + //uint8_t ssbMuxPattern = 0; + uint8_t numRbs = 0; + uint8_t numSymbols = 0; + uint8_t offset = 0; + uint8_t oValue = 0; + //uint8_t numSearchSpacePerSlot = 0; + uint8_t mValue = 0; + uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */ + uint8_t slotIndex = 0; + uint8_t FreqDomainResource[6] = {0}; + uint16_t tbSize = 0; + uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ + + PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); + PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); + BwpCfg *bwp = &(sib1SchCfg->bwp); + + coreset0Idx = sib1SchCfg->coresetZeroIndex; + searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex; + + /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */ + //ssbMuxPattern = coresetIdxTable[coreset0Idx][0]; + numRbs = coresetIdxTable[coreset0Idx][1]; + numSymbols = coresetIdxTable[coreset0Idx][2]; + offset = coresetIdxTable[coreset0Idx][3]; + + /* derive the search space params from table 13-11 spec 38.213 */ + oValue = searchSpaceIdxTable[searchSpace0Idx][0]; + //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1]; + mValue = searchSpaceIdxTable[searchSpace0Idx][2]; + firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3]; + + /* calculate the n0, need to add the formulae, as of now the value is 0 + * Need to add the even and odd values of i during configuration + * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe + * assuming u = 0, i = 0, numSlotsPerSubframe = 10 + * Also, from this configuration, coreset0 is only on even subframe */ + slotIndex = ((oValue * 1) + (0 * mValue)) % 10; + sib1SchCfg->n0 = slotIndex; + + /* calculate the PRBs */ + schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); + + /* fill BWP */ + bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */ + bwp->freqAlloc.startPrb = 0; + bwp->subcarrierSpacing = 0; /* 15Khz */ + bwp->cyclicPrefix = 0; /* normal */ + + /* fill the PDCCH PDU */ + pdcch->coreset0Cfg.coreSet0Size = numRbs; + pdcch->coreset0Cfg.startSymbolIndex = firstSymbol; + pdcch->coreset0Cfg.durationSymbols = numSymbols; + memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6); + pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */ + pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */ + pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */ + pdcch->coreset0Cfg.coreSetType = 0; + pdcch->coreset0Cfg.shiftIndex = pci; + pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */ + pdcch->numDlDci = 1; + pdcch->dci.rnti = SI_RNTI; + pdcch->dci.scramblingId = pci; + pdcch->dci.scramblingRnti = 0; + pdcch->dci.cceIndex = 0; + pdcch->dci.aggregLevel = 4; + pdcch->dci.beamPdcchInfo.numPrgs = 1; + pdcch->dci.beamPdcchInfo.prgSize = 1; + pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; + /* Storing pdschCfg pointer here. Required to access pdsch config while + fillig up pdcch pdu */ + pdcch->dci.pdschCfg = pdsch; + + /* fill the PDSCH PDU */ + uint8_t cwCount = 0; + pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */ + pdsch->rnti = 0xFFFF; /* SI-RNTI */ + pdsch->pduIndex = 0; + pdsch->numCodewords = 1; + for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++) + { + pdsch->codeword[cwCount].targetCodeRate = 308; + pdsch->codeword[cwCount].qamModOrder = 2; + pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs; + pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */ + pdsch->codeword[cwCount].rvIndex = 0; + tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen); + pdsch->codeword[cwCount].tbSize = tbSize; + } + pdsch->dataScramblingId = pci; + pdsch->numLayers = 1; + pdsch->transmissionScheme = 0; + pdsch->refPoint = 0; + pdsch->dmrs.dlDmrsSymbPos = 2; + pdsch->dmrs.dmrsConfigType = 0; /* type-1 */ + pdsch->dmrs.dlDmrsScramblingId = pci; + pdsch->dmrs.scid = 0; + pdsch->dmrs.numDmrsCdmGrpsNoData = 1; + pdsch->dmrs.dmrsPorts = 0; + pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + and PDSCH is always above SSB */ + pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); + pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ + pdsch->pdschTimeAlloc.rowIndex = 1; + pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */ + pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols; + pdsch->beamPdschInfo.numPrgs = 1; + pdsch->beamPdschInfo.prgSize = 1; + pdsch->beamPdschInfo.digBfInterfaces = 0; + pdsch->beamPdschInfo.prg[0].pmIdx = 0; + pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0; + pdsch->txPdschPower.powerControlOffset = 0; + pdsch->txPdschPower.powerControlOffsetSS = 0; + +} + +/** + * @brief Fill SSB start symbol + * + * @details + * + * Function : fillSsbStartSymb + * + * This API stores SSB start index per beam + * + * @param[in] SchCellCb *cellCb + * @return int + * -# ROK + * -# RFAILED + **/ +void fillSsbStartSymb(SchCellCb *cellCb) +{ + uint8_t cnt, scs; + + scs = cellCb->cellCfg.ssbSchCfg.scsCommon; + uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; + + memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ + switch(scs) + { + case SCH_SCS_15KHZ: + { + uint8_t symbIdx=0; + cnt = 2;/* n = 0, 1 for SCS = 15KHz */ + for(uint8_t idx=0; idxssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); + +} + /** * @brief cell config from MAC to SCH. * @@ -398,8 +655,15 @@ SchCellCfg *schCellCfg Inst inst = pst->dstInst-1; InitSchCellCb(inst, schCellCfg); - cellCb = schCb[inst].cells[inst]; + cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst cellCb->macInst = pst->srcInst; + + /* derive the SIB1 config parameters */ + fillSchSib1Cfg( + inst, + &(schCellCfg->sib1SchCfg), + schCellCfg->phyCellId, + schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); memset(&rspPst, 0, sizeof(Pst)); @@ -413,6 +677,57 @@ SchCellCfg *schCellCfg } +/******************************************************************* + * + * @brief Processes DL RLC BO info from MAC + * + * @details + * + * Function : macSchDlRlcBoInfo + * + * Functionality: + * Processes DL RLC BO info from MAC + * + * @params[in] + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +uint8_t macSchDlRlcBoInfo(Pst *pst, DlRlcBOInfo *dlBoInfo) +{ + uint16_t lcIdx; + Inst inst = pst->dstInst-SCH_INST_START; + DU_LOG("\nSCH : Received RLC BO Status indication"); + + SchCellCb *cell = schCb[inst].cells[inst]; + SchDlSlotInfo *schDlSlotInfo = \ + cell->schDlSlotInfo[(cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + MSG4_DELAY) % SCH_NUM_SLOTS]; + + for(lcIdx = 0; lcIdx < dlBoInfo->numLc; lcIdx++) + { + if(dlBoInfo->boInfo[lcIdx].lcId == CCCH_LCID) + { + SCH_ALLOC(schDlSlotInfo->msg4Info, sizeof(Msg4Info)); + if(!schDlSlotInfo->msg4Info) + { + DU_LOG("\nSCH : Memory allocation failed for msg4Info"); + schDlSlotInfo = NULL; + return RFAILED; + } + schDlSlotInfo->msg4Info->crnti = dlBoInfo->crnti; + schDlSlotInfo->msg4Info->ndi = 1; + schDlSlotInfo->msg4Info->harqProcNum = 0; + schDlSlotInfo->msg4Info->dlAssignIdx = 0; + schDlSlotInfo->msg4Info->pucchTpc = 0; + schDlSlotInfo->msg4Info->pucchResInd = 0; + schDlSlotInfo->msg4Info->harqFeedbackInd = 0; + schDlSlotInfo->msg4Info->dciFormatId = 1; + } + } + + return ROK; +} + /********************************************************************** End of file **********************************************************************/