X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.c;h=27ed26cf77eee70f1a8a28de7c03d9577b0a70fa;hb=51bd2af5867794ba058365581a7ad3c2eba0d1c3;hp=4d43895622094ad48428dfa956b8344b5cf18a47;hpb=deeae2741b8520edcd37ecb20a40f1de821ceadf;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 4d4389562..27ed26cf7 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -65,9 +65,9 @@ #include "sch.h" #include "sch_utils.h" #include "du_log.h" +#include "common_def.h" + extern SchCb schCb[SCH_MAX_INST]; -extern int8_t coresetIdxTable[MAX_CORESET_INDEX][4]; -extern int8_t searchSpaceIdxTable[MAX_SEARCH_SPACE_INDEX][4]; void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm); /* local defines */ SchCellCfgCfmFunc SchCellCfgCfmOpts[] = @@ -306,6 +306,65 @@ SlotIndInfo *slotInd RETVALUE(ROK); } /* macSchSlotInd */ +/******************************************************************* + * + * @brief Processes Rach indication from MAC + * + * @details + * + * Function : macSchRachInd + * + * Functionality: + * Processes Rach indication from MAC + * + * @params[in] + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +int macSchRachInd(Pst *pst, RachIndInfo *rachInd) +{ + Inst inst = pst->dstInst-SCH_INST_START; + DU_LOG("\nSCH : Received Rach indication"); + schProcessRachInd(rachInd, inst); + return ROK; +} + +/******************************************************************* + * + * @brief Processes CRC indication from MAC + * + * @details + * + * Function : macSchCrcInd + * + * Functionality: + * Processes CRC indication from MAC + * + * @params[in] Post structure + * Crc Indication + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +int macSchCrcInd(Pst *pst, CrcIndInfo *crcInd) +{ + switch(crcInd->crcInd[0]) + { + case CRC_FAILED: + DU_LOG("\nSCH : Received CRC indication. CRC Status [FAILURE]"); + break; + case CRC_PASSED: + DU_LOG("\nSCH : Received CRC indication. CRC Status [PASS]"); + break; + default: + DU_LOG("\nSCH : Invalid CRC state %d", crcInd->crcInd[0]); + return RFAILED; + } + return ROK; +} + + /** * @brief inti cellCb based on cellCfg * @@ -346,40 +405,44 @@ int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg) for(uint8_t idx=0; idxtotalPrb = schUlAlloc->totalPrb = MAX_NUM_RB; + memset(schDlSlotInfo, 0, sizeof(SchDlSlotInfo)); + memset(schUlSlotInfo, 0, sizeof(SchUlSlotInfo)); + + schDlSlotInfo->totalPrb = schUlSlotInfo->totalPrb = MAX_NUM_RB; for(uint8_t itr=0; itrassignedPrb[itr] = 0; - schUlAlloc->assignedPrb[itr] = 0; + schDlSlotInfo->assignedPrb[itr] = 0; + schUlSlotInfo->assignedPrb[itr] = 0; } + schUlSlotInfo->schPuschInfo = NULLP; for(uint8_t itr=0; itrssbInfo[itr], 0, sizeof(SsbInfo)); + memset(&schDlSlotInfo->ssbInfo[itr], 0, sizeof(SsbInfo)); } - cell->dlAlloc[idx] = schDlAlloc; - cell->ulAlloc[idx] = schUlAlloc; + cell->schDlSlotInfo[idx] = schDlSlotInfo; + cell->schUlSlotInfo[idx] = schUlSlotInfo; } schCb[inst].cells[inst] = cell; @@ -392,38 +455,41 @@ int InitSchCellCb(Inst inst, SchCellCfg *schCellCfg) void fillSchSib1Cfg( Inst schInst, SchSib1Cfg *sib1SchCfg, -uint8_t pci, +uint16_t pci, uint8_t offsetPointA ) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; - uint8_t ssbMuxPattern = 0; + //uint8_t ssbMuxPattern = 0; uint8_t numRbs = 0; uint8_t numSymbols = 0; uint8_t offset = 0; uint8_t oValue = 0; - uint8_t numSearchSpacePerSlot = 0; + //uint8_t numSearchSpacePerSlot = 0; uint8_t mValue = 0; uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */ uint8_t slotIndex = 0; uint8_t FreqDomainResource[6] = {0}; + uint16_t tbSize = 0; + uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ - Sib1PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); - Sib1PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); + PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); + PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); + BwpCfg *bwp = &(sib1SchCfg->bwp); coreset0Idx = sib1SchCfg->coresetZeroIndex; searchSpace0Idx = sib1SchCfg->searchSpaceZeroIndex; /* derive the sib1 coreset0 params from table 13-1 spec 38.213 */ - ssbMuxPattern = coresetIdxTable[coreset0Idx][0]; + //ssbMuxPattern = coresetIdxTable[coreset0Idx][0]; numRbs = coresetIdxTable[coreset0Idx][1]; numSymbols = coresetIdxTable[coreset0Idx][2]; offset = coresetIdxTable[coreset0Idx][3]; /* derive the search space params from table 13-11 spec 38.213 */ oValue = searchSpaceIdxTable[searchSpace0Idx][0]; - numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1]; + //numSearchSpacePerSlot = searchSpaceIdxTable[searchSpace0Idx][1]; mValue = searchSpaceIdxTable[searchSpace0Idx][2]; firstSymbol = searchSpaceIdxTable[searchSpace0Idx][3]; @@ -436,47 +502,47 @@ uint8_t offsetPointA sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ - freqDomResourceAlloc( ((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); + schAllocFreqDomRscType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); + + /* fill BWP */ + bwp->freqAlloc.numPrb = MAX_NUM_RB; /* whole of BW */ + bwp->freqAlloc.startPrb = 0; + bwp->subcarrierSpacing = 0; /* 15Khz */ + bwp->cyclicPrefix = 0; /* normal */ /* fill the PDCCH PDU */ - pdcch->sib1PdcchBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */ - pdcch->sib1PdcchBwpCfg.BWPStart = 0; - pdcch->sib1PdcchBwpCfg.subcarrierSpacing = 0; /* 15Khz */ - pdcch->sib1PdcchBwpCfg.cyclicPrefix = 0; /* normal */ - pdcch->sib1Coreset0Cfg.coreSet0Size = numRbs; - pdcch->sib1Coreset0Cfg.startSymbolIndex = firstSymbol; - pdcch->sib1Coreset0Cfg.durationSymbols = numSymbols; - memcpy(pdcch->sib1Coreset0Cfg.freqDomainResource,FreqDomainResource,6); - pdcch->sib1Coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */ - pdcch->sib1Coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */ - pdcch->sib1Coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */ - pdcch->sib1Coreset0Cfg.coreSetType = 0; - pdcch->sib1Coreset0Cfg.shiftIndex = pci; - pdcch->sib1Coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */ + pdcch->coreset0Cfg.coreSet0Size = numRbs; + pdcch->coreset0Cfg.startSymbolIndex = firstSymbol; + pdcch->coreset0Cfg.durationSymbols = numSymbols; + memcpy(pdcch->coreset0Cfg.freqDomainResource,FreqDomainResource,6); + pdcch->coreset0Cfg.cceRegMappingType = 1; /* coreset0 is always interleaved */ + pdcch->coreset0Cfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */ + pdcch->coreset0Cfg.interleaverSize = 2; /* spec-38.211 sec 7.3.2.2 */ + pdcch->coreset0Cfg.coreSetType = 0; + pdcch->coreset0Cfg.shiftIndex = pci; + pdcch->coreset0Cfg.precoderGranularity = 0; /* sameAsRegBundle */ pdcch->numDlDci = 1; - pdcch->sib1DlDci.rnti = 0xFFFF; /* SI-RNTI */ - pdcch->sib1DlDci.scramblingId = pci; - pdcch->sib1DlDci.scramblingRnti = 0; - pdcch->sib1DlDci.cceIndex = 0; - pdcch->sib1DlDci.aggregLevel = 4; - pdcch->sib1DlDci.beamPdcchInfo.numPrgs = 1; - pdcch->sib1DlDci.beamPdcchInfo.prgSize = 1; - pdcch->sib1DlDci.beamPdcchInfo.digBfInterfaces = 0; - pdcch->sib1DlDci.beamPdcchInfo.prg[0].pmIdx = 0; - pdcch->sib1DlDci.beamPdcchInfo.prg[0].beamIdx[0] = 0; - pdcch->sib1DlDci.txPdcchPower.powerValue = 0; - pdcch->sib1DlDci.txPdcchPower.powerControlOffsetSS = 0; + pdcch->dci.rnti = SI_RNTI; + pdcch->dci.scramblingId = pci; + pdcch->dci.scramblingRnti = 0; + pdcch->dci.cceIndex = 0; + pdcch->dci.aggregLevel = 4; + pdcch->dci.beamPdcchInfo.numPrgs = 1; + pdcch->dci.beamPdcchInfo.prgSize = 1; + pdcch->dci.beamPdcchInfo.digBfInterfaces = 0; + pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0; + pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0; + pdcch->dci.txPdcchPower.powerValue = 0; + pdcch->dci.txPdcchPower.powerControlOffsetSS = 0; /* Storing pdschCfg pointer here. Required to access pdsch config while fillig up pdcch pdu */ - pdcch->sib1DlDci.pdschCfg = pdsch; + pdcch->dci.pdschCfg = pdsch; /* fill the PDSCH PDU */ uint8_t cwCount = 0; pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */ pdsch->rnti = 0xFFFF; /* SI-RNTI */ pdsch->pduIndex = 0; - pdsch->sib1PdschBwpCfg.BWPSize = MAX_NUM_RB; /* whole of BW */ - pdsch->sib1PdschBwpCfg.BWPStart = 0; pdsch->numCodewords = 1; for(cwCount = 0; cwCount < pdsch->numCodewords; cwCount++) { @@ -485,36 +551,79 @@ uint8_t offsetPointA pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs; pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */ pdsch->codeword[cwCount].rvIndex = 0; - pdsch->codeword[cwCount].tbSize = 768; + tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen); + pdsch->codeword[cwCount].tbSize = tbSize; } - pdsch->dataScramblingId = pci; - pdsch->numLayers = 1; - pdsch->transmissionScheme = 0; - pdsch->refPoint = 0; - pdsch->dmrs.dlDmrsSymbPos = 2; - pdsch->dmrs.dmrsConfigType = 0; /* type-1 */ - pdsch->dmrs.dlDmrsScramblingId = pci; - pdsch->dmrs.scid = 0; - pdsch->dmrs.numDmrsCdmGrpsNoData = 1; - pdsch->dmrs.dmrsPorts = 0; - pdsch->sib1FreqAlloc.resourceAlloc = 1; /* RAT type-1 RIV format */ - pdsch->sib1FreqAlloc.rbStart = offset + SCH_SSB_PRB_DURATION; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ - /* formula used for calculation of rbSize, 38.213 section 5.1.3.2 * - * Ninfo = Nre . R . Qm . v * - * Nre' = Nsc . NsymPdsch - NdmrsSymb - Noh * - * Nre = min(156,Nre') . nPrb */ - pdsch->sib1FreqAlloc.rbSize = 10; /* This value is calculated from above formulae */ - pdsch->sib1FreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ - pdsch->sib1TimeAlloc.rowIndex = 1; - pdsch->sib1TimeAlloc.startSymbolIndex = 2; /* spec-38.214, Table 5.1.2.1-1 */ - pdsch->sib1TimeAlloc.numSymbols = 12; - pdsch->beamPdschInfo.numPrgs = 1; - pdsch->beamPdschInfo.prgSize = 1; - pdsch->beamPdschInfo.digBfInterfaces = 0; - pdsch->beamPdschInfo.prg[0].pmIdx = 0; - pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0; - pdsch->txPdschPower.powerControlOffset = 0; - pdsch->txPdschPower.powerControlOffsetSS = 0; + pdsch->dataScramblingId = pci; + pdsch->numLayers = 1; + pdsch->transmissionScheme = 0; + pdsch->refPoint = 0; + pdsch->dmrs.dlDmrsSymbPos = 2; + pdsch->dmrs.dmrsConfigType = 0; /* type-1 */ + pdsch->dmrs.dlDmrsScramblingId = pci; + pdsch->dmrs.scid = 0; + pdsch->dmrs.numDmrsCdmGrpsNoData = 1; + pdsch->dmrs.dmrsPorts = 0; + pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + and PDSCH is always above SSB */ + pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); + pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ + pdsch->pdschTimeAlloc.rowIndex = 1; + pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */ + pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols; + pdsch->beamPdschInfo.numPrgs = 1; + pdsch->beamPdschInfo.prgSize = 1; + pdsch->beamPdschInfo.digBfInterfaces = 0; + pdsch->beamPdschInfo.prg[0].pmIdx = 0; + pdsch->beamPdschInfo.prg[0].beamIdx[0] = 0; + pdsch->txPdschPower.powerControlOffset = 0; + pdsch->txPdschPower.powerControlOffsetSS = 0; + +} + +/** + * @brief Fill SSB start symbol + * + * @details + * + * Function : fillSsbStartSymb + * + * This API stores SSB start index per beam + * + * @param[in] SchCellCb *cellCb + * @return int + * -# ROK + * -# RFAILED + **/ +void fillSsbStartSymb(SchCellCb *cellCb) +{ + uint8_t cnt, scs; + + scs = cellCb->cellCfg.ssbSchCfg.scsCommon; + uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; + + memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ + switch(scs) + { + case SCH_SCS_15KHZ: + { + uint8_t symbIdx=0; + cnt = 2;/* n = 0, 1 for SCS = 15KHz */ + for(uint8_t idx=0; idxssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); } @@ -568,6 +677,57 @@ SchCellCfg *schCellCfg } +/******************************************************************* + * + * @brief Processes DL RLC BO info from MAC + * + * @details + * + * Function : macSchDlRlcBoInfo + * + * Functionality: + * Processes DL RLC BO info from MAC + * + * @params[in] + * @return ROK - success + * RFAILED - failure + * + * ****************************************************************/ +uint8_t macSchDlRlcBoInfo(Pst *pst, DlRlcBOInfo *dlBoInfo) +{ + uint16_t lcIdx; + Inst inst = pst->dstInst-SCH_INST_START; + DU_LOG("\nSCH : Received RLC BO Status indication"); + + SchCellCb *cell = schCb[inst].cells[inst]; + SchDlSlotInfo *schDlSlotInfo = \ + cell->schDlSlotInfo[(cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + MSG4_DELAY) % SCH_NUM_SLOTS]; + + for(lcIdx = 0; lcIdx < dlBoInfo->numLc; lcIdx++) + { + if(dlBoInfo->boInfo[lcIdx].lcId == CCCH_LCID) + { + SCH_ALLOC(schDlSlotInfo->msg4Info, sizeof(Msg4Info)); + if(!schDlSlotInfo->msg4Info) + { + DU_LOG("\nSCH : Memory allocation failed for msg4Info"); + schDlSlotInfo = NULL; + return RFAILED; + } + schDlSlotInfo->msg4Info->crnti = dlBoInfo->crnti; + schDlSlotInfo->msg4Info->ndi = 1; + schDlSlotInfo->msg4Info->harqProcNum = 0; + schDlSlotInfo->msg4Info->dlAssignIdx = 0; + schDlSlotInfo->msg4Info->pucchTpc = 0; + schDlSlotInfo->msg4Info->pucchResInd = 0; + schDlSlotInfo->msg4Info->harqFeedbackInd = 0; + schDlSlotInfo->msg4Info->dciFormatId = 1; + } + } + + return ROK; +} + /********************************************************************** End of file **********************************************************************/