X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrsch%2Fsch.c;h=056842fb1d918b49aa44ebe419f5226e0f01bf1a;hb=eae02ffcdfa215eb3ad990e2b0718d7a62eaa84a;hp=0cc841d59b45bad8e0b9435956e700fcbcaeac2c;hpb=dcf40f0b1856cf1fad8209661067cf6e0aa9837a;p=o-du%2Fl2.git diff --git a/src/5gnrsch/sch.c b/src/5gnrsch/sch.c index 0cc841d59..056842fb1 100644 --- a/src/5gnrsch/sch.c +++ b/src/5gnrsch/sch.c @@ -50,7 +50,6 @@ SchCb schCb[SCH_MAX_INST]; void SchFillCfmPst(Pst *reqPst,Pst *cfmPst,RgMngmt *cfm); - /* local defines */ SchCellCfgCfmFunc SchCellCfgCfmOpts[] = { @@ -123,7 +122,7 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) uint16_t ret = LCM_REASON_NOT_APPL; Inst inst = (dInst - SCH_INST_START); - printf("\nEntered SchInstCfg()"); + DU_LOG("\nDEBUG --> SCH : Entered SchInstCfg()"); /* Check if Instance Configuration is done already */ if (schCb[inst].schInit.cfgDone == TRUE) { @@ -149,26 +148,26 @@ uint8_t SchInstCfg(RgCfg *cfg, Inst dInst) schCb[inst].genCfg.isSCellActDeactAlgoEnable = cfg->s.schInstCfg.genCfg.isSCellActDeactAlgoEnable; #endif schCb[inst].genCfg.startCellId = cfg->s.schInstCfg.genCfg.startCellId; -#if 0 + /* Initialzie the timer queue */ - memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType)*RGSCH_TQ_SIZE); + memset(&schCb[inst].tmrTq, 0, sizeof(CmTqType) * SCH_TQ_SIZE); /* Initialize the timer control point */ memset(&schCb[inst].tmrTqCp, 0, sizeof(CmTqCp)); schCb[inst].tmrTqCp.tmrLen = RGSCH_TQ_SIZE; /* SS_MT_TMR needs to be enabled as schActvTmr needs instance information */ - /* Timer Registration request to SSI */ + /* Timer Registration request to system services */ if (ODU_REG_TMR_MT(schCb[inst].schInit.ent, dInst, (int)schCb[inst].genCfg.tmrRes, schActvTmr) != ROK) { - RLOG_ARG0(L_ERROR,DBG_INSTID,inst, "SchInstCfg(): Failed to " + DU_LOG("\nERROR --> SCH : SchInstCfg(): Failed to " "register timer."); return (LCM_REASON_MEM_NOAVAIL); } -#endif + /* Set Config done in TskInit */ schCb[inst].schInit.cfgDone = TRUE; - printf("\nScheduler gen config done"); + DU_LOG("\nINFO --> SCH : Scheduler gen config done"); return ret; } @@ -198,6 +197,10 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) RgMngmt cfm; Pst cfmPst; +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : GENERAL_CFG_REQ\n"); +#endif + if(pst->dstInst < SCH_INST_START) { DU_LOG("\nERROR --> SCH : Invalid inst ID"); @@ -205,7 +208,7 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) "pst->dstInst=%d SCH_INST_START=%d", pst->dstInst,SCH_INST_START); return ROK; } - printf("\nSCH : Received scheduler gen config"); + DU_LOG("\nINFO --> SCH : Received scheduler gen config"); /* Fill the post structure for sending the confirmation */ memset(&cfmPst, 0 , sizeof(Pst)); SchFillCfmPst(pst, &cfmPst, cfg); @@ -239,7 +242,7 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) cfm.cfm.reason = reason; SchSendCfgCfm(&cfmPst, &cfm); - /* SPutSBuf(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */ + /* SCH_FREE(pst->region, pst->pool, (Data *)cfg, sizeof(RgMngmt)); */ return ROK; }/*-- SchProcGenCfgReq --*/ @@ -255,15 +258,19 @@ uint8_t SchProcGenCfgReq(Pst *pst, RgMngmt *cfg) * a cell. * * @param[in] Pst *pst - * @param[in] SlotIndInfo *slotInd + * @param[in] SlotTimingInfo *slotInd * @return S16 * -# ROK * -# RFAILED **/ -uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd) +uint8_t MacSchSlotInd(Pst *pst, SlotTimingInfo *slotInd) { Inst inst = pst->dstInst-SCH_INST_START; +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SLOT_IND_TO_SCH\n"); +#endif + schProcessSlotInd(slotInd, inst); return ROK; @@ -288,6 +295,11 @@ uint8_t MacSchSlotInd(Pst *pst, SlotIndInfo *slotInd) uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd) { Inst inst = pst->dstInst-SCH_INST_START; + +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_RACH_IND_TO_SCH\n"); +#endif + DU_LOG("\nINFO --> SCH : Received Rach indication"); schProcessRachInd(rachInd, inst); return ROK; @@ -312,6 +324,10 @@ uint8_t MacSchRachInd(Pst *pst, RachIndInfo *rachInd) * ****************************************************************/ uint8_t MacSchCrcInd(Pst *pst, CrcIndInfo *crcInd) { +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_CRC_IND_TO_SCH\n"); +#endif + switch(crcInd->crcInd[0]) { case CRC_FAILED: @@ -407,23 +423,17 @@ uint16_t schGetPeriodicityInMsec(DlUlTxPeriodicity tddPeriod) * * @param[in] schCellCb *cell * @param[in] SchCellCfg *schCellCfg - * @return int - * -# ROK - * -# RFAILED + * @return void **/ void schInitTddSlotCfg(SchCellCb *cell, SchCellCfg *schCellCfg) { uint16_t periodicityInMicroSec = 0; - uint32_t slotBitPos, symbBitPos, bitMask; int8_t slotIdx, symbIdx; periodicityInMicroSec = schGetPeriodicityInMsec(schCellCfg->tddCfg.tddPeriod); - schCellCfg->numerology = 1; //TODO: Remove this cell->numSlotsInPeriodicity = (periodicityInMicroSec * pow(2, schCellCfg->numerology))/1000; -cell->slotFrmtBitMap = 0; + cell->slotFrmtBitMap = 0; cell->symbFrmtBitMap = 0; - slotBitPos = (cell->numSlotsInPeriodicity*2)-1; /* considering 2 bits to represent a slot */ - symbBitPos = (MAX_SYMB_PER_SLOT*2)-1; /* considering 2 bits to represent a symbol */ for(slotIdx = cell->numSlotsInPeriodicity-1; slotIdx >= 0; slotIdx--) { symbIdx = 0; @@ -436,23 +446,13 @@ cell->slotFrmtBitMap = 0; case DL_SLOT: { /*BitMap to be set to 00 */ - bitMask = 1<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<slotFrmtBitMap = (cell->slotFrmtBitMap<<2); break; } case UL_SLOT: { /*BitMap to be set to 01 */ - bitMask = 1<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((1<slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (UL_SLOT)); break; } default: @@ -461,12 +461,8 @@ cell->slotFrmtBitMap = 0; continue; } /* slot config is flexible. First set slotBitMap to 10 */ - bitMask = 1<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((1<slotFrmtBitMap = (cell->slotFrmtBitMap & ~(bitMask)) | ((0<slotFrmtBitMap = ((cell->slotFrmtBitMap<<2) | (FLEXI_SLOT)); + /* Now set symbol bitmap */ for(symbIdx = MAX_SYMB_PER_SLOT-1; symbIdx >= 0; symbIdx--) { @@ -475,34 +471,19 @@ cell->slotFrmtBitMap = 0; case DL_SLOT: { /*symbol BitMap to be set to 00 */ - bitMask = 1<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<symbFrmtBitMap = (cell->symbFrmtBitMap<<2); break; } case UL_SLOT: { /*symbol BitMap to be set to 01 */ - bitMask = 1<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((1<symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (UL_SLOT)); break; } case FLEXI_SLOT: { /*symbol BitMap to be set to 10 */ - bitMask = 1<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((1<symbFrmtBitMap = (cell->symbFrmtBitMap & ~(bitMask)) | ((0<symbFrmtBitMap = ((cell->symbFrmtBitMap<<2) | (FLEXI_SLOT)); break; } default: @@ -510,10 +491,72 @@ cell->slotFrmtBitMap = 0; } } } - } #endif +/** + * @brief Fill SSB start symbol + * + * @details + * + * Function : fillSsbStartSymb + * + * This API stores SSB start index per beam + * + * @param[in] SchCellCb *cellCb + * @return int + * -# ROK + * -# RFAILED + **/ +void fillSsbStartSymb(SchCellCb *cellCb) +{ + uint8_t cnt, scs, symbIdx, ssbStartSymbArr[SCH_MAX_SSB_BEAM]; + + scs = cellCb->cellCfg.ssbSchCfg.scsCommon; + + memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + symbIdx = 0; + /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ + switch(scs) + { + case SCS_15KHZ: + { + if(cellCb->cellCfg.dlFreq <= 300000) + cnt = 2;/* n = 0, 1 */ + else + cnt = 4; /* n = 0, 1, 2, 3 */ + for(uint8_t idx=0; idxcellCfg.dlFreq <= 300000) + cnt = 1;/* n = 0 */ + else + cnt = 2; /* n = 0, 1 */ + for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); + } + memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); + memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); + +} + /** * @brief init cellCb based on cellCfg @@ -618,6 +661,9 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) cell->schUlSlotInfo[idx] = schUlSlotInfo; } + cell->firstSsbTransmitted = false; + cell->firstSib1Transmitted = false; + fillSsbStartSymb(cell); schCb[inst].cells[inst] = cell; DU_LOG("\nINFO --> SCH : Cell init completed for cellId:%d", cell->cellId); @@ -641,7 +687,7 @@ uint8_t schInitCellCb(Inst inst, SchCellCfg *schCellCfg) * uint8_t offsetPointA : offset * @return void **/ -void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) +void fillSchSib1Cfg(uint8_t mu, uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint16_t pci, uint8_t offsetPointA) { uint8_t coreset0Idx = 0; uint8_t searchSpace0Idx = 0; @@ -654,9 +700,11 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, uint8_t mValue = 0; uint8_t firstSymbol = 0; /* need to calculate using formula mentioned in 38.213 */ uint8_t slotIndex = 0; - uint8_t FreqDomainResource[6] = {0}; + /* TODO : This should be filled through freqDomRscAllocType0() */ + uint8_t FreqDomainResource[6] = {15, 0, 0, 0, 0, 0}; uint16_t tbSize = 0; - uint8_t numPdschSymbols = 12; /* considering pdsch region from 2 to 13 */ + uint8_t numPdschSymbols = 11; /* considering pdsch region from symbols 3 to 13 */ + uint8_t ssbIdx = 0; PdcchCfg *pdcch = &(sib1SchCfg->sib1PdcchCfg); PdschCfg *pdsch = &(sib1SchCfg->sib1PdschCfg); @@ -682,11 +730,11 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, * [(O . 2^u + i . M ) ] mod numSlotsPerSubframe * assuming u = 0, i = 0, numSlotsPerSubframe = 10 * Also, from this configuration, coreset0 is only on even subframe */ - slotIndex = ((oValue * 1) + (0 * mValue)) % numSlots; + slotIndex = (int)((oValue*pow(2, mu)) + floor(ssbIdx*mValue))%numSlots; sib1SchCfg->n0 = slotIndex; /* calculate the PRBs */ - freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); + //freqDomRscAllocType0(((offsetPointA-offset)/6), (numRbs/6), FreqDomainResource); /* fill BWP */ switch(bandwidth) @@ -750,30 +798,31 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, pdsch->codeword[cwCount].mcsIndex = sib1SchCfg->sib1Mcs; pdsch->codeword[cwCount].mcsTable = 0; /* notqam256 */ pdsch->codeword[cwCount].rvIndex = 0; - tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen); + tbSize = schCalcTbSize(sib1SchCfg->sib1PduLen + TX_PAYLOAD_HDR_LEN); pdsch->codeword[cwCount].tbSize = tbSize; } pdsch->dataScramblingId = pci; pdsch->numLayers = 1; pdsch->transmissionScheme = 0; pdsch->refPoint = 0; - pdsch->dmrs.dlDmrsSymbPos = 2; + pdsch->dmrs.dlDmrsSymbPos = 4; /* Bitmap value 00000000000100 i.e. using 3rd symbol for PDSCH DMRS */ pdsch->dmrs.dmrsConfigType = 0; /* type-1 */ pdsch->dmrs.dlDmrsScramblingId = pci; pdsch->dmrs.scid = 0; pdsch->dmrs.numDmrsCdmGrpsNoData = 1; - pdsch->dmrs.dmrsPorts = 0; + pdsch->dmrs.dmrsPorts = 0x0001; pdsch->dmrs.mappingType = DMRS_MAP_TYPE_A; /* Type-A */ pdsch->dmrs.nrOfDmrsSymbols = NUM_DMRS_SYMBOLS; pdsch->dmrs.dmrsAddPos = DMRS_ADDITIONAL_POS; pdsch->pdschFreqAlloc.resourceAllocType = 1; /* RAT type-1 RIV format */ - pdsch->pdschFreqAlloc.freqAlloc.startPrb = offset + SCH_SSB_NUM_PRB; /* the RB numbering starts from coreset0, + pdsch->pdschFreqAlloc.freqAlloc.startPrb = offsetPointA + SCH_SSB_NUM_PRB + 1; /* the RB numbering starts from coreset0, and PDSCH is always above SSB */ pdsch->pdschFreqAlloc.freqAlloc.numPrb = schCalcNumPrb(tbSize,sib1SchCfg->sib1Mcs,numPdschSymbols); pdsch->pdschFreqAlloc.vrbPrbMapping = 0; /* non-interleaved */ pdsch->pdschTimeAlloc.rowIndex = 1; - pdsch->pdschTimeAlloc.timeAlloc.startSymb = 2; /* spec-38.214, Table 5.1.2.1-1 */ + /* This is Intel's requirement. PDSCH should start after PDSCH DRMS symbol */ + pdsch->pdschTimeAlloc.timeAlloc.startSymb = 3; /* spec-38.214, Table 5.1.2.1-1 */ pdsch->pdschTimeAlloc.timeAlloc.numSymb = numPdschSymbols; pdsch->beamPdschInfo.numPrgs = 1; pdsch->beamPdschInfo.prgSize = 1; @@ -785,51 +834,6 @@ void fillSchSib1Cfg(uint8_t bandwidth, uint8_t numSlots, SchSib1Cfg *sib1SchCfg, } -/** - * @brief Fill SSB start symbol - * - * @details - * - * Function : fillSsbStartSymb - * - * This API stores SSB start index per beam - * - * @param[in] SchCellCb *cellCb - * @return int - * -# ROK - * -# RFAILED - **/ -void fillSsbStartSymb(SchCellCb *cellCb) -{ - uint8_t cnt, scs; - - scs = cellCb->cellCfg.ssbSchCfg.scsCommon; - uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; - - memset(ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - /* Determine value of "n" based on Section 4.1 of 3GPP TS 38.213 */ - switch(scs) - { - case SCH_SCS_15KHZ: - { - uint8_t symbIdx=0; - cnt = 2;/* n = 0, 1 for SCS = 15KHz */ - for(uint8_t idx=0; idx SCH : SCS %d is currently not supported", scs); - } - memset(cellCb->ssbStartSymbArr, 0, sizeof(SCH_MAX_SSB_BEAM)); - memcpy(cellCb->ssbStartSymbArr, ssbStartSymbArr, SCH_MAX_SSB_BEAM); - -} - /** * @brief cell config from MAC to SCH. * @@ -852,17 +856,29 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) SchCellCfgCfm schCellCfgCfm; Pst rspPst; Inst inst = pst->dstInst-1; + SchPdschConfig pdschCfg; + +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SCH_CELL_CFG\n"); +#endif schInitCellCb(inst, schCellCfg); cellCb = schCb[inst].cells[inst]; //cells is of MAX_CELLS, why inst cellCb->macInst = pst->srcInst; /* derive the SIB1 config parameters */ - fillSchSib1Cfg(schCellCfg->bandwidth, cellCb->numSlots, + fillSchSib1Cfg(schCellCfg->numerology, schCellCfg->bandwidth, cellCb->numSlots, &(schCellCfg->sib1SchCfg), schCellCfg->phyCellId, schCellCfg->ssbSchCfg.ssbOffsetPointA); memcpy(&cellCb->cellCfg, schCellCfg, sizeof(SchCellCfg)); + /* Fill K0 - K1 table for common cfg*/ + BuildK0K1Table(cellCb, &cellCb->cellCfg.schInitialDlBwp.k0K1InfoTbl, true, cellCb->cellCfg.schInitialDlBwp.pdschCommon, + pdschCfg, DEFAULT_UL_ACK_LIST_COUNT, defaultUlAckTbl); + + BuildK2InfoTable(cellCb, cellCb->cellCfg.schInitialUlBwp.puschCommon.timeDomRsrcAllocList,\ + cellCb->cellCfg.schInitialUlBwp.puschCommon.numTimeDomRsrcAlloc, &cellCb->cellCfg.schInitialUlBwp.msg3K2InfoTbl, \ + &cellCb->cellCfg.schInitialUlBwp.k2InfoTbl); /* Initializing global variables */ cellCb->actvUeBitMap = 0; cellCb->boIndBitMap = 0; @@ -876,7 +892,6 @@ uint8_t SchHdlCellCfgReq(Pst *pst, SchCellCfg *schCellCfg) schCellCfgCfm.rsp = RSP_OK; ret = (*SchCellCfgCfmOpts[rspPst.selector])(&rspPst, &schCellCfgCfm); - return ret; } @@ -902,20 +917,33 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) uint8_t lcId = 0; uint16_t ueIdx = 0; uint16_t slot; +#ifdef NR_TDD + uint16_t slotIdx = 0; +#endif SchUeCb *ueCb = NULLP; SchCellCb *cell = NULLP; SchDlSlotInfo *schDlSlotInfo = NULLP; - Inst inst = pst->dstInst-SCH_INST_START; + +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_DL_RLC_BO_INFO_TO_SCH\n"); +#endif + DU_LOG("\nDEBUG --> SCH : Received RLC BO Status indication"); cell = schCb[inst].cells[inst]; + if(cell == NULLP) + { + DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): Cell does not exists"); + return RFAILED; + } + GET_UE_IDX(dlBoInfo->crnti, ueIdx); ueCb = &cell->ueCb[ueIdx-1]; lcId = dlBoInfo->lcId; if(lcId == SRB1_LCID || lcId == SRB2_LCID || lcId == SRB3_LCID || \ - (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID)) + (lcId >= MIN_DRB_LCID && lcId <= MAX_DRB_LCID)) { SET_ONE_BIT(ueIdx, cell->boIndBitMap); ueCb->dlInfo.dlLcCtxt[lcId].bo = dlBoInfo->dataVolume; @@ -926,16 +954,35 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) return RFAILED; } - slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA + BO_DELTA) % cell->numSlots; + slot = (cell->slotInfo.slot + SCHED_DELTA + PHY_DELTA_DL + BO_DELTA) % cell->numSlots; +#ifdef NR_TDD + while(schGetSlotSymbFrmt(cell->slotFrmtBitMap, slot) != DL_SLOT) + { + slot = (slot + 1)%cell->numSlots; + slotIdx++; + if(slotIdx==cell->numSlots) + { + DU_LOG("\nERROR --> SCH : No DL Slot available"); + return RFAILED; + } + } +#endif + schDlSlotInfo = cell->schDlSlotInfo[slot]; + if(schDlSlotInfo == NULLP) + { + DU_LOG("\nERROR --> SCH : MacSchDlRlcBoInfo(): schDlSlotInfo does not exists"); + return RFAILED; + } SCH_ALLOC(schDlSlotInfo->dlMsgInfo, sizeof(DlMsgInfo)); - if(!schDlSlotInfo->dlMsgInfo) + if(schDlSlotInfo->dlMsgInfo == NULLP) { DU_LOG("\nERROR --> SCH : Memory allocation failed for dlMsgInfo"); schDlSlotInfo = NULL; return RFAILED; } + schDlSlotInfo->dlMsgInfo->crnti = dlBoInfo->crnti; schDlSlotInfo->dlMsgInfo->ndi = 1; schDlSlotInfo->dlMsgInfo->harqProcNum = 0; @@ -945,8 +992,10 @@ uint8_t MacSchDlRlcBoInfo(Pst *pst, DlRlcBoInfo *dlBoInfo) schDlSlotInfo->dlMsgInfo->harqFeedbackInd = 0; schDlSlotInfo->dlMsgInfo->dciFormatId = 1; if(lcId == SRB0_LCID) + { schDlSlotInfo->dlMsgInfo->isMsg4Pdu = true; - + schDlSlotInfo->dlMsgInfo->dlMsgPduLen = dlBoInfo->dataVolume; + } return ROK; } @@ -974,6 +1023,10 @@ uint8_t MacSchBsr(Pst *pst, UlBufferStatusRptInd *bsrInd) SchUeCb *ueCb = NULLP; uint8_t lcgIdx; +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_SHORT_BSR\n"); +#endif + DU_LOG("\nDEBUG --> SCH : Received BSR"); cellCb = schCb[schInst].cells[schInst]; ueCb = schGetUeCb(cellCb, bsrInd->crnti); @@ -1011,6 +1064,10 @@ uint8_t MacSchSrUciInd(Pst *pst, SrUciIndInfo *uciInd) SchUeCb *ueCb; SchCellCb *cellCb = schCb[inst].cells[inst]; +#ifdef CALL_FLOW_DEBUG_LOG + DU_LOG("\nCall Flow: ENTMAC -> ENTSCH : EVENT_UCI_IND_TO_SCH\n"); +#endif + DU_LOG("\nDEBUG --> SCH : Received SR"); ueCb = schGetUeCb(cellCb, uciInd->crnti);