X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=src%2F5gnrmac%2Fmac.h;h=e64cba274b5e5101b5cc6f3c0c0947d0e7d8836a;hb=e44180890b286bf1f78cd8f3867092f0914cccec;hp=88eeb87257ea8134de41a4ecf12b7c67997d279a;hpb=6b44407d464a5a4e060999255233a7cfe78bb0fa;p=o-du%2Fl2.git

diff --git a/src/5gnrmac/mac.h b/src/5gnrmac/mac.h
index 88eeb8725..e64cba274 100644
--- a/src/5gnrmac/mac.h
+++ b/src/5gnrmac/mac.h
@@ -21,51 +21,16 @@
 /* MAX values */
 #define MAX_MAC_CE 6
 #define MAX_CRI_SIZE 6
-#define MAX_MAC_DL_PDU 10
+#define MAX_MAC_DL_PDU 16
 #define MAX_NUM_HARQ_PROC  16
-#define MAX_SLOT_SUPPORTED    10 /* numerology 0 15Khz */
 #define MAX_ZERO_CORR_CFG_IDX 16 /* max zero correlation config index */
+#define MAC_TQ_SIZE    10        /* Timing Queue Size */
+#define MAX_NUM_TIMER  1         /* MAX number of MAC timers */
 
 #define DEFAULT_CELLS 1
 #define SI_RNTI 0xFFFF
 #define P_RNTI 0xFFFE
 
-#define PERIODIC_BSR_TMR_1MS    1
-#define PERIODIC_BSR_TMR_5MS    5
-#define PERIODIC_BSR_TMR_10MS   10
-#define PERIODIC_BSR_TMR_16MS   16
-#define PERIODIC_BSR_TMR_20MS   20
-#define PERIODIC_BSR_TMR_32MS   32
-#define PERIODIC_BSR_TMR_40MS   40
-#define PERIODIC_BSR_TMR_60MS   60
-#define PERIODIC_BSR_TMR_80MS   80
-#define PERIODIC_BSR_TMR_128MS   128
-#define PERIODIC_BSR_TMR_160MS   160
-#define PERIODIC_BSR_TMR_320MS   320
-#define PERIODIC_BSR_TMR_640MS   640
-#define PERIODIC_BSR_TMR_1280MS  1280
-#define PERIODIC_BSR_TMR_2560MS  2560
-
-#define RETX_BSR_TMR_10MS    10
-#define RETX_BSR_TMR_20MS    20
-#define RETX_BSR_TMR_40MS    40
-#define RETX_BSR_TMR_80MS    80
-#define RETX_BSR_TMR_160MS   160
-#define RETX_BSR_TMR_320MS   320
-#define RETX_BSR_TMR_640MS   640
-#define RETX_BSR_TMR_1280MS   1280
-#define RETX_BSR_TMR_2560MS   2560
-#define RETX_BSR_TMR_5120MS   5120
-#define RETX_BSR_TMR_10240MS  10240
-
-#define SR_DELAY_TMR_20MS     20
-#define SR_DELAY_TMR_40MS     40
-#define SR_DELAY_TMR_64MS     64
-#define SR_DELAY_TMR_128MS    128
-#define SR_DELAY_TMR_512MS    512
-#define SR_DELAY_TMR_1024MS   1024
-#define SR_DELAY_TMR_2560MS   2560
-
 #define MAC_LCID_CCCH              0
 #define MAC_LCID_MIN               1
 #define MAC_LCID_MAX               32
@@ -95,9 +60,9 @@ typedef enum
 
 typedef enum
 {
-   LC_STATE_INACTIVE,
-   LC_STATE_ACTIVE
-}LcState;
+   MAC_LC_STATE_INACTIVE,
+   MAC_LC_STATE_ACTIVE
+}MacLcState;
 
 typedef struct macDlSlot
 {
@@ -164,14 +129,14 @@ typedef struct ulLcCb
 {
    uint8_t   lcId;      /* Logical Channel Id */
    uint8_t   lcGrpId;   /* Logical Channel group */
-   LcState   lcActive;  /* Is LC active ? */
+   MacLcState lcActive;  /* Is LC active ? */
 }UlLcCb;
 
 /* Downlink dedicated logical channel info */
 typedef struct dlLcCb
 {
    uint8_t   lcId;      /* Logical channel Id */ 
-   LcState   lcState;  /* Is LC active ? */
+   MacLcState   lcState;  /* Is LC active ? */
 }DlLcCb;
 
 /* BSR Information */
@@ -187,7 +152,7 @@ typedef struct ueUlCb
 {
    uint8_t    maxReTx;     /* MAX HARQ retransmission */
    uint8_t    numUlLc;     /* Number of uplink logical channels */       
-   UlLcCb     lcCb[MAX_NUM_LOGICAL_CHANNELS];    /* Uplink dedicated logocal channels */
+   UlLcCb     lcCb[MAX_NUM_LC];    /* Uplink dedicated logocal channels */
 }UeUlCb;
 
 /* UE specific DL Info */
@@ -195,7 +160,7 @@ typedef struct ueDlCb
 {
    DlHarqEnt  dlHarqEnt;      /* DL HARQ entity */
    uint8_t    numDlLc;        /* Number of downlink logical channels */
-   DlLcCb     lcCb[MAX_NUM_LOGICAL_CHANNELS];  /* Downlink dedicated logical channels */
+   DlLcCb     lcCb[MAX_NUM_LC];  /* Downlink dedicated logical channels */
 }UeDlCb;
 
 /* UE Cb */
@@ -214,10 +179,12 @@ typedef struct macUeCb
 struct macCellCb
 {
    uint16_t    cellId;
+   uint8_t     crntiMap;
    MacRaCbInfo macRaCb[MAX_NUM_UE];
-   MacDlSlot   dlSlot[MAX_SLOT_SUPPORTED];
-   MacUlSlot   ulSlot[MAX_SLOT_SUPPORTED];
+   MacDlSlot   dlSlot[MAX_SLOTS];
+   MacUlSlot   ulSlot[MAX_SLOTS];
    uint16_t    numActvUe;
+   MacUeCfg    *ueCfgTmpData[MAX_NUM_UE];
    MacUeCb     ueCb[MAX_NUM_UE];
    MacCellCfg  macCellCfg;
    SlotIndInfo currTime;
@@ -227,23 +194,31 @@ typedef struct macCb
 {
    Inst       macInst;
    ProcId     procId;
+   uint8_t    tmrRes;                    /*!< Timer resolution */
+   CmTqCp     tmrTqCp;                   /*!< Timer Task Queue Cntrl Point */
+   CmTqType   tmrTq[MAC_TQ_SIZE];        /*!< Timer Task Queue */
+   CmTimer    tmrBlk[MAX_NUM_TIMER];     /*!< Timer Block */
    MacCellCb  *macCell[MAX_NUM_CELL];
 }MacCb;
 
 /* global variable */
 MacCb macCb;
+
+/* Function declarations */
+short int macActvTmr(Ent ent,Inst inst);
 void fillRarPdu(RarInfo *rarInfo);
-void createMacRaCb(uint16_t cellId, uint16_t crnti);
-void fillMsg4DlData(uint16_t cellId, MacDlData *dlData, uint8_t *msg4Pdu);
+void createMacRaCb(RachIndInfo *rachIndInfo);
+void fillMsg4DlData(MacDlData *dlData, uint16_t msg4PduLen, uint8_t *msg4Pdu);
 void fillMacCe(MacCeInfo  *macCeData, uint8_t *msg3Pdu);
 void macMuxPdu(MacDlData *dlData, MacCeInfo *macCeData, uint8_t *msg4TxPdu, uint16_t tbSize);
 uint8_t unpackRxData(uint16_t cellId, SlotIndInfo slotInfo, RxDataIndPdu *rxDataIndPdu);
-void fillMg4Pdu(Msg4Alloc *msg4Alloc);
+void fillMg4Pdu(DlMsgAlloc *msg4Alloc);
 void buildAndSendMuxPdu(SlotIndInfo currTimingInfo);
 uint8_t macProcUlCcchInd(uint16_t cellId, uint16_t crnti, uint16_t rrcContSize, uint8_t *rrcContainer);
 uint8_t macProcShortBsr(uint16_t cellId, uint16_t crnti, uint8_t lcgId, uint32_t bufferSize);
 uint8_t macProcUlData(uint16_t cellId, uint16_t rnti, SlotIndInfo slotInfo, \
    uint8_t lcId, uint16_t pduLen, uint8_t *pdu);
+uint8_t sendSchedRptToRlc(DlSchedInfo dlInfo, SlotIndInfo slotInfo);
 #endif
 /**********************************************************************
   End of file