X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=fhi_lib%2Ftest%2Ftest_xran%2Fu_plane_functional.cc;h=599819b02db57e92b817f8c72eafe63d9fb3f3e5;hb=892daba4c616407f16506415d5a69549519ef11d;hp=5bc1588192e0c3760c360f126a65ee5e876fab5b;hpb=70d9d920dd4e575f085f1f1a9050fefd1c10e127;p=o-du%2Fphy.git diff --git a/fhi_lib/test/test_xran/u_plane_functional.cc b/fhi_lib/test/test_xran/u_plane_functional.cc index 5bc1588..599819b 100644 --- a/fhi_lib/test/test_xran/u_plane_functional.cc +++ b/fhi_lib/test/test_xran/u_plane_functional.cc @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (c) 2019 Intel. +* Copyright (c) 2020 Intel. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -61,6 +61,7 @@ TEST_P(U_planeCheck, Test_DLUL) { enum xran_pkt_dir direction = XRAN_DIR_DL; uint16_t section_id = 7; + uint16_t num_sections = 1; enum xran_input_byte_order iq_buf_byte_order = XRAN_CPU_LE_BYTE_ORDER; uint8_t frame_id = 99; uint8_t subframe_id = 9; @@ -73,6 +74,7 @@ TEST_P(U_planeCheck, Test_DLUL) uint8_t seq_id =0; uint32_t do_copy = 0; uint8_t compMeth = 0; + enum xran_comp_hdr_type staticEn = XRAN_COMP_HDR_TYPE_DYNAMIC; uint8_t iqWidth = 16; int32_t prep_bytes; @@ -87,7 +89,7 @@ TEST_P(U_planeCheck, Test_DLUL) prep_bytes = prepare_symbol_ex(direction, section_id, test_buffer, - (struct rb_map *)iq_offset, + (uint8_t *)iq_offset, compMeth, iqWidth, iq_buf_byte_order, @@ -100,7 +102,10 @@ TEST_P(U_planeCheck, Test_DLUL) CC_ID, RU_Port_ID, seq_id, - do_copy); + do_copy, + staticEn, + num_sections, + 0); ASSERT_EQ(prep_bytes, 3168); @@ -113,11 +118,11 @@ TEST_P(U_planeCheck, Test_DLUL) sizeof (struct xran_ecpri_hdr) + sizeof(struct radio_app_common_hdr)); - ASSERT_EQ (ecpri_hdr->cmnhdr.ecpri_mesg_type, ECPRI_IQ_DATA); - payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.ecpri_payl_size); + ASSERT_EQ (ecpri_hdr->cmnhdr.bits.ecpri_mesg_type, ECPRI_IQ_DATA); + payl_size = rte_be_to_cpu_16(ecpri_hdr->cmnhdr.bits.ecpri_payl_size); ASSERT_EQ (payl_size, 3180); - ASSERT_EQ(app_hdr->data_direction, direction); + ASSERT_EQ(app_hdr->data_feature.data_direction, direction); ASSERT_EQ(app_hdr->frame_id, frame_id); res_sect.fields.all_bits = rte_be_to_cpu_32(section_hdr->fields.all_bits); @@ -127,7 +132,7 @@ TEST_P(U_planeCheck, Test_DLUL) { /* UL direction */ void *iq_samp_buf; - struct ecpri_seq_id seq; + union ecpri_seq_id seq; int num_bytes = 0; uint8_t CC_ID = 0; @@ -167,6 +172,7 @@ TEST_P(U_planeCheck, Test_DLUL) &rb, §_id, 0, + XRAN_COMP_HDR_TYPE_DYNAMIC, &compMeth, &iqWidth);