X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=fhi_lib%2Fapp%2Fusecase%2Fcat_b%2Fmu1_100mhz%2F105%2Fconfig_file_o_ru.dat;h=34f3a00caa2330c1fda191b751155e8ba1ef75a7;hb=refs%2Fheads%2Fmaster;hp=c3b4f7879bf6a0fc533f9bb4a2d55a906fbdbbbf;hpb=70d9d920dd4e575f085f1f1a9050fefd1c10e127;p=o-du%2Fphy.git

diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat
index c3b4f78..34f3a00 100644
--- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat
+++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/105/config_file_o_ru.dat
@@ -77,7 +77,7 @@ ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
 duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
 ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
 
-numSlots=10 #number of slots per IQ files
+numSlots=20 #number of slots per IQ files
 antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC0
 antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC0
 antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin   #CC0
@@ -112,11 +112,14 @@ antPrachC13=./usecase/cat_b/mu1_100mhz/ant_5.bin  #CC3
 antPrachC14=./usecase/cat_b/mu1_100mhz/ant_6.bin  #CC3
 antPrachC15=./usecase/cat_b/mu1_100mhz/ant_7.bin  #CC3
 
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
 prachConfigIndex=189
 
-srsEanble=1 # Enable (1)| disable (0) SRS 
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3           # scheduled SRS slot within TDD period
+srsNdmOffset=3      # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4  # TX duration for NDM SRTS U-Plane (numberof of symbols)
 
 antSrsC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   
 antSrsC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   
@@ -203,6 +206,9 @@ PrbElemUl0=0,30,0,14,0,1,1,9,1
 PrbElemUl1=30,30,0,14,1,1,1,9,1
 PrbElemUl2=60,30,0,14,2,1,1,9,1
 
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
+
 ###########################################################
 
 ## control of IQ byte order