X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;f=fhi_lib%2Fapp%2Fusecase%2Fcat_b%2Fmu1_100mhz%2F102%2Fconfig_file_o_du.dat;h=eb40204e5d8047efa1083ecba6ef23f99a72ff40;hb=HEAD;hp=90e5fb9c78473c28fbb803151f91eb9e4f029ab9;hpb=2fbf70096f64af622da983e88c5a64e90ad9bdbd;p=o-du%2Fphy.git

diff --git a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat
index 90e5fb9..eb40204 100644
--- a/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat
+++ b/fhi_lib/app/usecase/cat_b/mu1_100mhz/102/config_file_o_du.dat
@@ -63,19 +63,26 @@ MTUSize=9600 #maximum transmission unit (MTU) is the size of the largest protoco
 Gps_Alpha=0	#alpha and beta value as in section 9.7.2 of ORAN spec
 Gps_Beta=0
 
-ioCore=5
-systemCore=5
-pktProcCore=5
-pktAuxCore=5
-timingCore=6
-llsCUMac=00:11:22:33:44:66 # asigned MAC of O-DU VF
-ruMac=00:11:22:33:44:55    # O-RU VF for O-RU app
-
-numSlots=10 #number of slots per IQ files
-antC0=./usecase/cat_b/mu1_100mhz/ant_0.bin   #CC0
-antC1=./usecase/cat_b/mu1_100mhz/ant_1.bin   #CC0
-antC2=./usecase/cat_b/mu1_100mhz/ant_2.bin   #CC0
-antC3=./usecase/cat_b/mu1_100mhz/ant_3.bin   #CC0
+ioCore=5           # core id 
+ioWorker=0x2000000 # mask [0- no workers]
+
+# Eth 0
+duMac0=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac0=00:11:22:33:44:55 # O-RU VF for O-RU app
+duMac1=00:11:22:33:44:66 # asigned MAC of O-DU VF
+ruMac1=00:11:22:33:44:55 # O-RU VF for O-RU app
+
+# Eth 1
+duMac2=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac2=00:11:22:33:44:44 # O-RU VF for O-RU app
+duMac3=00:11:22:33:44:77 # asigned MAC of O-DU VF
+ruMac3=00:11:22:33:44:44 # O-RU VF for O-RU app
+
+numSlots=20 #number of slots per IQ files
+antC0=./usecase/cat_b/mu1_100mhz/16qam_ant_0.bin   #CC0
+antC1=./usecase/cat_b/mu1_100mhz/16qam_ant_1.bin   #CC0
+antC2=./usecase/cat_b/mu1_100mhz/16qam_ant_2.bin   #CC0
+antC3=./usecase/cat_b/mu1_100mhz/16qam_ant_3.bin   #CC0
 antC4=./usecase/cat_b/mu1_100mhz/ant_4.bin   #CC1
 antC5=./usecase/cat_b/mu1_100mhz/ant_5.bin   #CC1
 antC6=./usecase/cat_b/mu1_100mhz/ant_6.bin   #CC1
@@ -109,25 +116,41 @@ UlBfwUe5=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_5.bin   #UE5 weights for TRX anten
 UlBfwUe6=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_6.bin   #UE6 weights for TRX antennas [antElmTRx x numRBs x slot points]
 UlBfwUe7=./usecase/cat_b/mu1_100mhz/ul_bfw_ue_7.bin   #UE7 weights for TRX antennas [antElmTRx x numRBs x slot points]
 
-rachEanble=0 # Enable (1)| disable (0) PRACH configuration
+rachEnable=0 # Enable (1)| disable (0) PRACH configuration
 prachConfigIndex=189
 
-srsEanble=1 # Enable (1)| disable (0) SRS 
-srsSym=8192 # (1<<13) symbol used for SRS (def: sym 13)
+srsEnable=1 # Enable (1)| disable (0) SRS
+srsSym=4 # deprecated
+srsSlot=3           # scheduled SRS slot within TDD period
+srsNdmOffset=3      # delay offset to start NDM SRS U-Plane
+srsNdmTxDuration=4  # TX duration for NDM SRTS U-Plane (numberof of symbols)
 
 ###########################################################
 ##Section Settings
 DynamicSectionEna=1 # 1 - enable dynamic section allocation 0 - static sections all RBs are used 
 
-nPrbElemDl=1
-#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
+nPrbElemDl=2
+#nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType, Scalefactor, REMask
 # weight base beams 
-PrbElemDl0=0,90,0,14,1,1,1,9,1
-
-nPrbElemUl=1
+PrbElemDl0=0,64,0,14,0,1,4,2,1,10360,4095
+PrbElemDl1=64,26,0,14,1,1,4,2,1,10360,4095
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwDl0=32,2,0,0,9,1
+ExtBfwDl1=13,2,0,0,9,1
+
+nPrbElemUl=2
 #nRBStart, nRBSize, nStartSymb, numSymb, nBeamIndex, bf_weight_update, compMethod, iqWidth, BeamFormingType
 # weight base beams 
-PrbElemUl0=0,90,0,14,1,1,1,9,1
+PrbElemUl0=0,64,0,14,0,1,1,9,1
+PrbElemUl1=64,26,0,14,1,1,1,9,1
+# Extension Parameters for Beamforming weights
+# numBundPrb, numSetBFW, RAD, disableBFW, bfwIqWidth, bfwCompMeth
+ExtBfwUl0=64,2,0,0,9,1
+ExtBfwUl1=13,2,0,0,9,1
+
+nPrbElemSrs=1
+PrbElemSrs0=0,273,13,1,0,0,1,9,0
 
 ###########################################################