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init_sys_functional.cc
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1 /******************************************************************************
2 *
3 * Copyright (c) 2019 Intel.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *******************************************************************************/
18 
19 
20 #include "common.hpp"
21 #include "xran_fh_o_du.h"
22 #include "xran_cp_api.h"
23 #include "xran_lib_wrap.hpp"
24 #include "xran_common.h"
25 #include "ethdi.h"
26 
27 #include <stdint.h>
28 #include <iostream>
29 #include <vector>
30 #include <string>
31 
32 
33 
34 using namespace std;
35 const std::string module_name = "init_sys_functional";
36 
38 
39 void physide_sym_call_back(void * param)
40 {
41  rte_pause();
42  return;
43 }
44 
45 int physide_dl_tti_call_back(void * param)
46 {
47  rte_pause();
48  return 0;
49 }
50 
52 {
53  rte_pause();
54  return 0;
55 }
56 
58 {
59  rte_pause();
60  return 0;
61 }
62 
63 void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
64 {
65  rte_pause();
66  return;
67 }
68 
69 void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
70 {
71 
72  rte_pause();
73 }
74 
76 {
77 protected:
78 
79  void SetUp() override
80  {
81  xranlib->Init();
82  xranlib->Open(nullptr, nullptr, (void *)xran_fh_rx_callback, (void *)xran_fh_rx_prach_callback);
83  }
84 
85  /* It's called after an execution of the each test case.*/
86  void TearDown() override
87  {
88  xranlib->Close();
89  xranlib->Cleanup();
90  }
91 
92 public:
93 
99 
100  /* buffers lists */
106 
107  void* nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]; // instance per sector
109  uint16_t nInstanceNum;
110 };
111 
112 TEST_P(Init_Sys_Check, Test_Open_Close)
113 {
114  struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
115  /* check stat of lib */
116  ASSERT_EQ(1, p_xran_dev_ctx->enableCP);
117  ASSERT_EQ(1, p_xran_dev_ctx->xran2phy_mem_ready);
118 }
119 
120 TEST_P(Init_Sys_Check, Test_xran_mm_init)
121 {
122  int16_t ret = 0;
124  ASSERT_EQ(0, ret);
125 }
126 
127 /* this case cannot be tested since memory cannot be initialized twice */
128 /* memory initialization is moved to the wrapper class */
129 #if 0
130 TEST_P(Init_Sys_Check, Test_xran_bm_init_alloc_free)
131 {
132  int16_t ret = 0;
133  void *ptr;
134  void *mb;
135  uint32_t nSW_ToFpga_FTH_TxBufferLen = 13168; /* 273*12*4 + 64*/
136  int16_t k = 0;
137 
138 
144 
146 
147  for (k = 0; k < XRAN_PORTS_NUM; k++) {
149  ASSERT_EQ(0, ret);
150  ASSERT_EQ(1, Init_Sys_Check::nInstanceNum);
151  }
152 
153 
157  ASSERT_EQ(0, ret);
158 
160  ASSERT_EQ(0, ret);
161  ASSERT_NE(ptr, nullptr);
162  ASSERT_NE(mb, nullptr);
163 
165  ASSERT_EQ(0, ret);
166 
167 
168 
169  for(int i=0; i< xranlib->get_num_cc(); i++)
170  {
171  for(int j=0; j<XRAN_N_FE_BUF_LEN; j++)
172  {
173  for(int z = 0; z < XRAN_MAX_ANTENNA_NR; z++){
174  pFthTxBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulTxBbuIoBufCtrl[j][i][z].sBufferList);
175  pFthTxPrbMapBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulTxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
176  pFthRxBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxBbuIoBufCtrl[j][i][z].sBufferList);
177  pFthRxPrbMapBuffer[i][z][j] = &(Init_Sys_Check::sFrontHaulRxPrbMapBbuIoBufCtrl[j][i][z].sBufferList);
178  pFthRxRachBuffer[i][z][j] = &(Init_Sys_Check::sFHPrachRxBbuIoBufCtrl[j][i][z].sBufferList);
179  }
180  }
181  }
182 
183  if(NULL != Init_Sys_Check::nInstanceHandle[0])
184  {
185  for (int i = 0; i < xranlib->get_num_cc(); i++)
186  {
188  pFthTxBuffer[i],
189  pFthTxPrbMapBuffer[i],
190  pFthRxBuffer[i],
191  pFthRxPrbMapBuffer[i],
192  xran_fh_rx_callback, &pFthRxBuffer[i][0]);
193 
194  ASSERT_EQ(0, ret);
195  }
196 
197  // add prach callback here
198  for (int i = 0; i < xranlib->get_num_cc(); i++)
199  {
200  ret = xran_5g_prach_req(Init_Sys_Check::nInstanceHandle[0][i], pFthRxRachBuffer[i],
201  xran_fh_rx_prach_callback,&pFthRxRachBuffer[i][0]);
202  ASSERT_EQ(0, ret);
203  }
204  }
205 
206 
207 }
208 #endif
209 
210 TEST_P(Init_Sys_Check, Test_xran_get_common_counters)
211 {
212  int16_t ret = 0;
213  struct xran_common_counters x_counters;
214 
215  ret = xran_get_common_counters(xranlib->get_xranhandle(), &x_counters);
216 
217  ASSERT_EQ(0, ret);
218  ASSERT_EQ(0, x_counters.Rx_on_time);
219  ASSERT_EQ(0, x_counters.Rx_early);
220  ASSERT_EQ(0, x_counters.Rx_late);
221  ASSERT_EQ(0, x_counters.Rx_corrupt);
222  ASSERT_EQ(0, x_counters.Rx_pkt_dupl);
223  ASSERT_EQ(0, x_counters.Total_msgs_rcvd);
224 }
225 
226 TEST_P(Init_Sys_Check, Test_xran_get_slot_idx)
227 {
228 #define NUM_OF_SUBFRAME_PER_FRAME 10
229  int32_t nNrOfSlotInSf = 1;
230  int32_t nSfIdx = -1;
231  uint32_t nFrameIdx;
232  uint32_t nSubframeIdx;
233  uint32_t nSlotIdx;
234  uint64_t nSecond;
235 
236  uint32_t nXranTime = xran_get_slot_idx(&nFrameIdx, &nSubframeIdx, &nSlotIdx, &nSecond);
237  nSfIdx = nFrameIdx*NUM_OF_SUBFRAME_PER_FRAME*nNrOfSlotInSf
238  + nSubframeIdx*nNrOfSlotInSf
239  + nSlotIdx;
240 
241  ASSERT_EQ(0, nSfIdx);
242 }
243 
244 TEST_P(Init_Sys_Check, Test_xran_reg_physide_cb)
245 {
246  struct xran_device_ctx * p_xran_dev_ctx = xran_dev_get_ctx();
247  int16_t ret = 0;
249  ASSERT_EQ(0,ret);
250  ASSERT_EQ(physide_dl_tti_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_TTI]);
251  ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_TTI]);
252  ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_TTI]);
253 
255  ASSERT_EQ(0,ret);
256  ASSERT_EQ(physide_ul_half_slot_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_HALF_SLOT_RX]);
257  ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_HALF_SLOT_RX]);
258  ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_HALF_SLOT_RX]);
259 
261  ASSERT_EQ(0,ret);
262  ASSERT_EQ(physide_ul_full_slot_call_back, p_xran_dev_ctx->ttiCb[XRAN_CB_FULL_SLOT_RX]);
263  ASSERT_EQ(NULL, p_xran_dev_ctx->TtiCbParam[XRAN_CB_FULL_SLOT_RX]);
264  ASSERT_EQ(10, p_xran_dev_ctx->SkipTti[XRAN_CB_FULL_SLOT_RX]);
265 
266 }
267 
268 TEST_P(Init_Sys_Check, Test_xran_reg_sym_cb){
269  int16_t ret = 0;
271  ASSERT_EQ(-1,ret);
272 }
273 
274 TEST_P(Init_Sys_Check, Test_xran_mm_destroy){
275  int16_t ret = 0;
277  ASSERT_EQ(-1,ret);
278 }
279 
280 TEST_P(Init_Sys_Check, Test_xran_start_stop){
281  int16_t ret = 0;
283  ret = xranlib->Start();
284  ASSERT_EQ(0,ret);
286  ret = xranlib->Stop();
287  ASSERT_EQ(0,ret);
289 }
290 
292  testing::ValuesIn(get_sequence(Init_Sys_Check::get_number_of_cases("init_sys_functional"))));
293 
294 
295 
int32_t xran_get_common_counters(void *pXranLayerHandle, struct xran_common_counters *pStats)
Definition: xran_main.c:3074
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enum xran_if_state xran_if_current_state
Definition: ethdi.c:75
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void * TtiCbParam[XRAN_CB_MAX]
Definition: xran_common.h:253
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#define XRAN_N_FE_BUF_LEN
Definition: xran_fh_o_du.h:109
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void SetUp() override
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void xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
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BbuIoBufCtrlStruct sFrontHaulRxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
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int32_t xran_reg_sym_cb(void *pHandle, xran_callback_sym_fn symCb, void *symCbParam, uint8_t symb, uint8_t ant)
Definition: xran_main.c:2888
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static unsigned get_number_of_cases(const std::string &type)
Definition: common.hpp:190
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int32_t xran_mm_init(void *pHandle, uint64_t nMemorySize, uint32_t nMemorySegmentSize)
Definition: xran_main.c:2447
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TEST_P(Init_Sys_Check, Test_Open_Close)
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const std::string module_name
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void * nInstanceHandle[XRAN_PORTS_NUM][XRAN_MAX_SECTOR_NR]
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int32_t xran_bm_init(void *pHandle, uint32_t *pPoolIndex, uint32_t nNumberOfBuffers, uint32_t nBufferSize)
Definition: xran_main.c:2454
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#define XRAN_MAX_SECTOR_NR
Definition: xran_fh_o_du.h:110
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int32_t xran_get_slot_idx(uint32_t *nFrameIdx, uint32_t *nSubframeIdx, uint32_t *nSlotIdx, uint64_t *nSecond)
Definition: xran_main.c:2936
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Definition: json.hpp:12898
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#define XRAN_MAX_ANTENNA_NR
Definition: xran_fh_o_du.h:111
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int physide_ul_full_slot_call_back(void *param)
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#define XRAN_PORTS_NUM
Definition: xran_fh_o_du.h:108
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xran_fh_tti_callback_fn ttiCb[XRAN_CB_MAX]
Definition: xran_common.h:252
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int32_t xran_5g_prach_req(void *pHandle, struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag)
Definition: xran_main.c:2636
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BbuIoBufCtrlStruct sFHPrachRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
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struct xran_device_ctx * xran_dev_get_ctx(void)
Definition: xran_main.c:223
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int32_t xran_mm_destroy(void *pHandle)
Definition: xran_main.c:2877
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uint32_t enableCP
Definition: xran_common.h:213
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void xran_fh_rx_prach_callback(void *pCallbackTag, xran_status_t status)
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uint32_t nSW_ToFpga_FTH_TxBufferLen
Definition: sample-app.c:73
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xran_if_state
Definition: xran_fh_o_du.h:189
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int physide_ul_half_slot_call_back(void *param)
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#define SW_FPGA_FH_TOTAL_BUFFER_LEN
Definition: sample-app.c:51
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#define SW_FPGA_SEGMENT_BUFFER_LEN
Definition: sample-app.c:50
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int32_t xran_bm_allocate_buffer(void *pHandle, uint32_t nPoolIndex, void **ppData, void **ppCtrl)
Definition: xran_main.c:2499
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This file has all definitions for the Ethernet Data Interface Layer.
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int32_t xran_bm_free_buffer(void *pHandle, void *pData, void *pCtrl)
Definition: xran_main.c:2541
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uint32_t SkipTti[XRAN_CB_MAX]
Definition: xran_common.h:254
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BbuIoBufCtrlStruct sFrontHaulRxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
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void TearDown() override
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XRAN layer common functionality for both lls-CU and RU as well as C-plane and U-plane.
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INSTANTIATE_TEST_CASE_P(UnitTest, Init_Sys_Check, testing::ValuesIn(get_sequence(Init_Sys_Check::get_number_of_cases("init_sys_functional"))))
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BbuIoBufCtrlStruct sFrontHaulTxBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
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#define XRAN_NUM_OF_SYMBOL_PER_SLOT
Definition: xran_fh_o_du.h:122
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void physide_sym_call_back(void *param)
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This file provides public interface to xRAN Front Haul layer implementation as defined in the ORAN-WG...
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int32_t xran_sector_get_instances(void *pHandle, uint16_t nNumInstances, xran_cc_handle_t *pSectorInstanceHandles)
Definition: xran_main.c:2408
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struct xran_buffer_list sBufferList
Definition: sample-app.c:129
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int Init(struct xran_fh_config *pCfg=nullptr)
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BbuIoBufCtrlStruct sFrontHaulTxPrbMapBbuIoBufCtrl[XRAN_N_FE_BUF_LEN][XRAN_MAX_SECTOR_NR][XRAN_MAX_ANTENNA_NR]
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void Open(xran_ethdi_mbuf_send_fn send_cp, xran_ethdi_mbuf_send_fn send_up, void *fh_rx_callback, void *fh_rx_prach_callback)
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#define NUM_OF_SUBFRAME_PER_FRAME
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xranLibWraper * xranlib
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uint32_t nBufPoolIndex[XRAN_MAX_SECTOR_NR][xranLibWraper::MAX_SW_XRAN_INTERFACE_NUM]
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std::vector< unsigned > get_sequence(const unsigned number)
For a given number return sequence of number from 0 to number - 1.
Definition: common.cpp:78
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void * get_xranhandle()
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This file provides the definitions for Control Plane Messages APIs.
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int32_t xran_reg_physide_cb(void *pHandle, xran_fh_tti_callback_fn Cb, void *cbParam, int skipTtiNum, enum callback_to_phy_id)
Definition: xran_main.c:2900
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int physide_dl_tti_call_back(void *param)
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int32_t xran_5g_fronthault_config(void *pHandle, struct xran_buffer_list *pSrcBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pSrcCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pDstBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], struct xran_buffer_list *pDstCpBuffer[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN], xran_transport_callback_fn pCallback, void *pCallbackTag)
Definition: xran_main.c:2551
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int32_t xran_status_t
Definition: xran_fh_o_du.h:236
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