X-Git-Url: https://gerrit.o-ran-sc.org/r/gitweb?a=blobdiff_plain;ds=sidebyside;f=src%2F5gnrsch%2Fsch_rach.c;h=c07a7261a920044e2f5b61b5cd6273b67e3a70f4;hb=42e50f5a3e46d7ca3afe97907b39d2a0c79a21c2;hp=c002ea744cd999486af212014d0dd3e1b9a72047;hpb=73da3ffdd36c5ade0c1cccbe7d2ad4d457897b2f;p=o-du%2Fl2.git

diff --git a/src/5gnrsch/sch_rach.c b/src/5gnrsch/sch_rach.c
index c002ea744..c07a7261a 100644
--- a/src/5gnrsch/sch_rach.c
+++ b/src/5gnrsch/sch_rach.c
@@ -540,7 +540,7 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin
    uint8_t   k0TblIdx = 0, k1TblIdx = 0, k2TblIdx = 0;
    uint8_t   k0Index = 0, k1Index = 0, k2Index = 0;
    uint8_t   k0 = 0, k1 = 0, k2 = 0;
-   uint8_t   numK1 = 0;
+   uint8_t   numK1 = 0, ret = OK;
    uint8_t   puschMu = 0;
    uint8_t   msg3Delta = 0, msg3MinSchTime = 0;
 #ifdef NR_TDD
@@ -697,10 +697,20 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin
       if(cell->raReq[ueId-1]->isCFRA)
       {
          /* Allocate resources for PUCCH */
-         schAllocPucchResource(cell, pucchTime, cell->raReq[ueId-1]->rachInd->crnti,NULLP, FALSE, NULLP);
+         cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
+         ret = schAllocPucchResource(cell, pucchTime, NULLP, NULLP, NULLP);
+         if(ret == RFAILED)
+         {
+            SCH_FREE(dciSlotAlloc, sizeof(RarAlloc));
+            cell->schDlSlotInfo[dciSlot]->rarAlloc[ueId-1] = NULLP;
+            DU_LOG("\nERROR  -->  SCH : Resource allocation for PUCCH failed for CFRA!");
+            return false;
+            
+         }
       }
       else
       {
+         cell->schUlSlotInfo[msg3Time.slot]->puschUe = ueId;
          /* Allocate resources for msg3 */
          msg3PuschInfo = schAllocMsg3Pusch(schInst, cell->raReq[ueId-1]->rachInd->crnti, k2Index, msg3Time, &(cell->raCb[ueId-1].msg3HqProc), FALSE);
          if(msg3PuschInfo)
@@ -727,7 +737,7 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin
          SCH_ALLOC(dciSlotAlloc->rarPdschCfg, sizeof(PdschCfg));
          if(dciSlotAlloc->rarPdschCfg)
          {
-             memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg, sizeof(PdschCfg));
+             memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg));
          }
          else
          {
@@ -762,7 +772,7 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin
          SCH_ALLOC(rarSlotAlloc->rarPdschCfg, sizeof(PdschCfg));
          if(rarSlotAlloc->rarPdschCfg)
          {
-            memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg,sizeof(PdschCfg));
+            memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg,sizeof(PdschCfg));
          }
          else
          {
@@ -780,10 +790,6 @@ bool schProcessRaReq(Inst schInst, SchCellCb *cell, SlotTimingInfo currTime, uin
       }
 
       cell->schDlSlotInfo[dciSlot]->pdcchUe = ueId;
-      if(cell->raReq[ueId-1]->isCFRA)
-         cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
-      else
-         cell->schUlSlotInfo[msg3Time.slot]->puschUe = ueId;
 
       /* Create raCb at SCH */
       createSchRaCb(ueId, cell->raReq[ueId-1], schInst);
@@ -940,20 +946,20 @@ uint8_t schFillRar(SchCellCb *cell, SlotTimingInfo rarTime, uint16_t ueId, RarAl
    pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
    pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
    pdcch->numDlDci = 1;
-   pdcch->dci.rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */
-   pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
-   pdcch->dci.scramblingRnti = 0;
-   pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
-   pdcch->dci.aggregLevel = 4;
-   pdcch->dci.beamPdcchInfo.numPrgs = 1;
-   pdcch->dci.beamPdcchInfo.prgSize = 1;
-   pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
-   pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
-   pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
-   pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0;
-   pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
-
-   pdsch = &pdcch->dci.pdschCfg;
+   pdcch->dci[0].rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */
+   pdcch->dci[0].scramblingId = cell->cellCfg.phyCellId;
+   pdcch->dci[0].scramblingRnti = 0;
+   pdcch->dci[0].cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
+   pdcch->dci[0].aggregLevel = 4;
+   pdcch->dci[0].beamPdcchInfo.numPrgs = 1;
+   pdcch->dci[0].beamPdcchInfo.prgSize = 1;
+   pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0;
+   pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0;
+   pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0;
+   pdcch->dci[0].txPdcchPower.beta_pdcch_1_0 = 0;
+   pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0;
+
+   pdsch = &pdcch->dci[0].pdschCfg;
    /* fill the PDSCH PDU */
    uint8_t cwCount = 0;
    pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */