#define SS_MAX_TTSKS 100
#ifndef SS_MULTICORE_SUPPORT
-#define SS_MAX_STSKS 6
+#define SS_MAX_STSKS 7
#else
/* mt001.301 : Additions */
#ifdef SPLIT_RLC_DL_TASK
#define SS_MAX_STSKS 5
#endif
#else
-#define SS_MAX_STSKS 6
+#ifndef INTEL_WLS_MEM
+#define SS_MAX_STSKS 9
+#else
+#define SS_MAX_STSKS 7
+#endif
#endif
#endif /* SS_MULTICORE_SUPPORT */
#else /* SS_MULTIPLE_PROCS */
#define SS_MAX_TTSKS 1000
-#define SS_MAX_STSKS 6
+#define SS_MAX_STSKS 7
#endif /* SS_MULTIPLE_PROCS */
#ifdef SS_DRVR_SUPPORT
#ifdef SS_MULTICORE_SUPPORT
#define SS_MAX_REGS SS_MAX_STSKS
#else
-#define SS_MAX_REGS 6
+#define SS_MAX_REGS 8
#endif
#ifdef CMM_MAX_BKT_ENT
#endif
#define MT_BKT_4_DSIZE 65000
-#define MT_BKT_4_NUMBLKS 1000
+#define MT_BKT_4_NUMBLKS 2000
/* For Non-Sharable regions/static regions */
#ifdef XEON_SPECIFIC_CHANGES