/* MACROS */
#define DU_INST 0
#define DU_ID 1
+
+#ifndef O1_ENABLE
+
#define DU_IP_V4_ADDR "192.168.130.81"
#define CU_IP_V4_ADDR "192.168.130.82"
#define RIC_IP_V4_ADDR "192.168.130.80"
#define DU_PORT 38472
#define CU_PORT 38472
-#define RIC_PORT 36422 /* using X2 port since E2 port not defined */
+#define RIC_PORT 36421
+#endif
+
#define DU_EGTP_PORT 39001
#define CU_EGTP_PORT 39002
#define NR_PCI 1
#define NR_CELL_ID 1
+
#define DU_NAME "ORAN_OAM_DU"
#define CELL_TYPE SMALL
+
+//TODO: while testing for TDD, Mu1 and 100 MHz, this flag must be enabled
+#ifdef NR_TDD
+#define DUPLEX_MODE DUP_MODE_TDD
+#define NR_NUMEROLOGY 1
+#define NR_DL_ARFCN 623400
+#define NR_UL_ARFCN 623400
+#define NR_FREQ_BAND 78
+#else
#define DUPLEX_MODE DUP_MODE_FDD
+#define NR_NUMEROLOGY 0
+#define NR_DL_ARFCN 428000
+#define NR_UL_ARFCN 390000
+#define NR_FREQ_BAND 1
+#endif
+
#define DU_TAC 1
#define PLMN_MCC0 3
#define PLMN_MCC1 1
#define PLMN_MNC1 8
#define PLMN_MNC2 0
#define PLMN_SIZE 3
-#define NR_DL_ARFCN 385627
-#define NR_UL_ARFCN 386687
+
+/* Spec 38.104 Table 5.4.2.3-1:Applicable NR-ARFCN per operating band in FR1 */
#define SUL_ARFCN 100
-#define NR_FREQ_BAND 257
-#define NR_FREQ_BAND_IND 78
#define SUL_BAND 2
+
+
+
#define TIME_CFG 0
#define CARRIER_IDX 1
#define NUM_TX_ANT 2
#define NUM_RX_ANT 2
#define FREQ_SHIFT_7P5KHZ FALSE
-#define SSB_PBCH_PWR -5
-#define BCH_PAYLOAD MAC_GEN_FULL_PBCH_PAYLD
-#define TOTAL_PRB_BW 106
-#define SUBCARRIER_SPACING 0
+#define SSB_PBCH_PWR 0
+#define BCH_PAYLOAD PHY_GEN_TIMING_PBCH_BIT
#define NORMAL_CYCLIC_PREFIX 0
-#define SCS_CARRIER_BANDWIDTH 273 /* Subcarrier spacing- carrier bandwidth */
#define OFFSET_TO_POINT_A 24 /* PRB Offset to Point A */
#define BETA_PSS BETA_PSS_0DB
#define SSB_PERIODICITY_5MS 5
#define SSB_SUBCARRIER_OFFSET 0
#define SSB_MULT_CARRIER_BAND FALSE
#define MULT_CELL_CARRIER FALSE
-#define FREQ_LOC_BW 1099 /* DL frequency location and bandwidth */
+#define FREQ_LOC_BW 28875 /* DL frequency location and bandwidth. Spec 38.508 Table 4.3.1.0B-1*/
#define UL_P_MAX 23
-#define BANDWIDTH 20
#define DMRS_TYPE_A_POS 2
#define NUM_SYMBOLS_PER_SLOT 14 /* Number of symbols within a slot */
#define CORESET0_END_PRB 48
#define PRACH_CONFIG_IDX 88
#define PRACH_FREQ_START 0
#define PRACH_SEQ_LEN SHORT_SEQUENCE
-#define PRACH_SUBCARRIER_SPACING 1
+#define PRACH_SUBCARRIER_SPACING 0
#define PRACH_RESTRICTED_SET_CFG 0
#define NUM_PRACH_FDM 1
-#define ROOT_SEQ_IDX 24
+#define ROOT_SEQ_IDX 0
#define NUM_ROOT_SEQ 1
-#define ZERO_CORRELATION_ZONE_CFG 6
+#define ZERO_CORRELATION_ZONE_CFG 4
#define NUM_UNUSED_ROOT_SEQ 0
#define UNUSED_ROOT_SEQ 1
#define SSB_PER_RACH 1
#define PRACH_PREAMBLE_RCVD_TGT_PWR -74
#define NUM_RA_PREAMBLE 63
#define RSRP_THRESHOLD_SSB 31
-#define TDD_PERIODICITY TX_PRDCTY_MS_2P5
+
+#ifdef NR_TDD
+#define TDD_PERIODICITY TX_PRDCTY_MS_5
+#endif
+
#define RSS_MEASUREMENT_UNIT DONT_REPORT_RSSI
#define RA_CONT_RES_TIMER 64
#define RA_RSP_WINDOW 180
#define ROOT_SEQ_LEN 139
/* MACRCO Ddefine for PDCCH Configuration */
-#define PDCCH_CTRL_RSRC_SET_ZERO 13 /* Control resouce set zero */
-#define PDCCH_SEARCH_SPACE_ZERO 0 /* Search space zero */
#define PDCCH_SEARCH_SPACE_ID 1 /* Common search space id */
#define PDCCH_CTRL_RSRC_SET_ID 0 /* Control resource set id */
-#define PDCCH_SEARCH_SPACE_ID_SIB1 0 /* Search space id for sib1 */
+#define PDCCH_SEARCH_SPACE_ID_SIB1 1 /* Search space id for sib1 */
#define PDCCH_SEARCH_SPACE_ID_PAGING 1 /* Search space id for paging */
#define PDCCH_SEARCH_SPACE_ID_RA 1 /* Search spaced id for random access */
#define PDCCH_SERACH_SPACE_DCI_FORMAT 0
#define SIB1_VALUE_TAG 10
/* MACRO Ddefine for PDSCH Configuration */
-#define PDSCH_K0 0
-#define PDSCH_START_SYMBOL 2
-#define PDSCH_LENGTH_SYMBOL 12
+#define PDSCH_K0_CFG1 0
+#define PDSCH_K0_CFG2 1
+#define PDSCH_START_SYMBOL 3
+#define PDSCH_LENGTH_SYMBOL 11
#define PDSCH_RES_ALLOC_TYPE 1 /* Resource allocation type */
#define PDSCH_MAX_CODEWORD_SCH_BY_DCI 0 /* Max num of codewords scheduled by DCI */
#define PDSCH_RBG_SIZE 0 /* 0: config1 */
#define PDSCH_NUM_HARQ_PROC 5
/* MACRO Define for PUSCH Configuration */
-#define PUSCH_K2 3
-#define PUSCH_START_SYMBOL 0
-#define PUSCH_LENGTH_SYMBOL 14
+#define MAX_UL_ALLOC 16
+#define PUSCH_K2_CFG1 3
+#define PUSCH_K2_CFG2 4
+#define PUSCH_START_SYMBOL 3
+#define PUSCH_LENGTH_SYMBOL 11
#define PUSCH_MSG3_DELTA_PREAMBLE 0
#define PUSCH_P0_NOMINAL_WITH_GRANT -70
#define PUCCH_P0_NOMINAL -74
/* MACRO defines for TDD DL-UL Configuration */
-#define NUM_DL_SLOTS 3
-#define NUM_DL_SYMBOLS 12
-#define NUM_UL_SLOTS 1
-#define NUM_UL_SYMBOLS 0
+#define NUM_DL_SLOTS 7
+#define NUM_DL_SYMBOLS 12
+#define NUM_UL_SLOTS 2
+#define NUM_UL_SYMBOLS 1
+#define GUARD_SLOT_IDX 7
/* MACRO defines for SRC config */
#define SRS_RSRC_ID 1
/* Macro definitions for MIB/SIB1 */
#define SYS_FRAME_NUM 0
#define SPARE 0
-#define SSB_SC_OFFSET 8
-#define CORESET_ZERO 1
-#define SEARCH_SPACE_ZERO 8
+#define SSB_SC_OFFSET 0
#define DU_RANAC 1
#define CELL_IDENTITY 32
#define PHR_PWR_FACTOR_CHANGE 3
#define PHR_MODE_OTHER_CG 0
#define SN_FIELD_LEN 0
-#define T_POLL_RETRANSMIT 8
-#define POLL_PDU 0
-#define POLL_BYTE 43
-#define MAX_RETX_THRESHOLD 5
-#define T_REASSEMBLY 8
-#define T_STATUS_PROHIBHIT 7
+#define T_POLL_RETRANSMIT 8 /* Enum for 45ms */
+#define T_POLL_RETRANSMIT_VAL 45 /* Value in ms */
+#define POLL_PDU 0 /* Enum for 4 pdus */
+#define POLL_PDU_VAL 4 /* Value of poll pdu */
+#define POLL_BYTE 43 /* Enum for infinite poll bytes */
+#define POLL_BYTE_VAL -1 /* Value for infinite poll byte */
+#define MAX_RETX_THRESHOLD 5 /* Enum for 8 retransmissions */
+#define MAX_RETX_THRESHOLD_VAL 8 /* Value for 8 retransmissions */
+#define T_REASSEMBLY 8 /* enum for RE_ASM_40MS */
+#define T_REASSEMBLY_VAL 40 /* default re assembly timer */
+#define T_STATUS_PROHIBHIT 7 /* enum for PROH_35MS */
+#define T_STATUS_PROHIBHIT_VAL 35 /* default status prohibit timer */
#define MAC_LC_PRIORITY 1
#define PRIORTISIED_BIT_RATE 15
#define BUCKET_SIZE_DURATION 5
#define LC_ID 1
#endif
+/* MACRO definitions for modulcation order */
+#define MOD_ORDER_QPSK 2
+#define MOD_ORDER_QAM16 4
+#define MOD_ORDER_QAM64 6
+#define MOD_ORDER_QAM256 8
+#define PDSCH_MCS_INDEX 20 /* For 64QAM, valid mcs index: 17-28 in 38.214 - Table 5.1.3.1-1*/
+#define PUSCH_MCS_INDEX 10 /* For 16QAM, valid mcs index: 10-16 in 38.214 - Table 5.1.3.1-1*/
+
typedef enum
{
GNBDU,
GNBCU
}F1Entity;
+typedef enum
+{
+ SERV_CELL_TO_MODIFY,
+ SERV_CELL_TO_DELETE
+}ServCellAction;
+
typedef enum
{
UNSPECIFIED,
long raSearchSpc; /* Id of search space for Random Access proc */
}PdcchCfgCommon;
-typedef struct pdschCfgCommon
+typedef struct pdschTimeDomainRsrcAlloc
{
- uint8_t present;
long k0;
long mapType; /* Mapping Type */
uint16_t sliv;
+}PdschTimeDomainRsrcAlloc;
+
+typedef struct pdschCfgCommon
+{
+ uint8_t present;
+ uint8_t numTimeDomRsrcAlloc;
+ PdschTimeDomainRsrcAlloc timeDomAlloc[MAX_NUM_DL_ALLOC];
}PdschCfgCommon;
typedef struct bcchCfg
long restrictedSetCfg; /* Restricted set configuration */
}RachCfgCommon;
-typedef struct puschCfgCommon
+typedef struct puschCfgCmnTimeDomAlloc
{
- uint8_t present;
long k2;
long mapType;
uint16_t sliv;
+}PuschCfgCmnTimeDomAlloc;
+
+typedef struct puschCfgCommon
+{
+ uint8_t puschCfgPresent;
+ uint8_t numTimeDomRsrcAlloc;
+ PuschCfgCmnTimeDomAlloc timeDomAllocList[MAX_UL_ALLOC];
long msg3DeltaPreamble;
long p0NominalWithGrant;
}PuschCfgCommon;
Code Review / o-du / l2.git / blobdiff