[Issue-ID : ODUHIGH-486] SCTP Port fix at F1 and E2 interface

[o-du/l2.git] / src / du_app / du_cfg.h

diff --git a/src/du_app/du_cfg.h b/src/du_app/du_cfg.h
index ff91158..2d197b5 100644 (file)
--- a/src/du_app/du_cfg.h
+++ b/src/du_app/du_cfg.h
@@ -31,9 +31,9 @@
 #define DU_IP_V4_ADDR "192.168.130.81"
 #define CU_IP_V4_ADDR "192.168.130.82"
 #define RIC_IP_V4_ADDR "192.168.130.80"
-#define DU_PORT 38472
-#define CU_PORT 38472
-#define RIC_PORT 36421
+
+#define F1_SCTP_PORT 38472
+#define E2_SCTP_PORT 36421
 #endif
 
 #define DU_EGTP_PORT  39001
@@ -41,7 +41,7 @@
 #define NR_PCI 1
 #define NR_CELL_ID 1
 
-#define DU_NAME "ORAN_OAM_DU"
+#define DU_NAME "ORAN OAM DU"
 #define CELL_TYPE SMALL
 
 //TODO: while testing for TDD, Mu1 and 100 MHz, this flag must be enabled
@@ -99,7 +99,11 @@
 #define CORESET1_NUM_PRB   24
 
 /* MACRO defines for PRACH Configuration */
+#ifndef NR_TDD
+#define PRACH_CONFIG_IDX   16
+#else
 #define PRACH_CONFIG_IDX   88
+#endif
 #define PRACH_MAX_PRB  24  /* As per (spec 38.211-Table 6.3.3.2-1), max allocated PRBs can go upto 24 */
 #define PRACH_FREQ_START  (MAX_NUM_RB - PRACH_MAX_PRB) /* In order to allocate PRACH from end of the resource grid */
 #define PRACH_SEQ_LEN SHORT_SEQUENCE
@@ -296,6 +300,24 @@
 #define DEDICATED_RATIO  10
 #define NUM_OF_SUPPORTED_SLICE  2
 
+#ifdef NR_DRX
+/* Macros for Drx configuration */
+#define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
+#define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 10
+#define DRX_INACTIVITY_TIMER 2
+#define DRX_HARQ_RTT_TIMER_DL 56
+#define DRX_HARQ_RTT_TIMER_UL 56
+#define DRX_RETRANSMISSION_TIMER_DL 4
+#define DRX_RETRANSMISSION_TIMER_UL 4
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 40
+#define DRX_LONG_CYCLE_START_OFFSET_VAL 8
+#define DRX_SHORT_CYCLE_PRESENT true
+#define DRX_SHORT_CYCLE 2
+#define DRX_SHORT_CYCLE_TIMER 2
+#define DRX_SLOT_OFFSET 0
+#endif
+
 typedef enum
 {
    GNBDU,