[Issue-ID : ODUHIGH-486] SCTP Port fix at F1 and E2 interface

[o-du/l2.git] / src / du_app / du_cfg.h

diff --git a/src/du_app/du_cfg.h b/src/du_app/du_cfg.h
index bfda5a5..2d197b5 100644 (file)
--- a/src/du_app/du_cfg.h
+++ b/src/du_app/du_cfg.h
@@ -31,9 +31,9 @@
 #define DU_IP_V4_ADDR "192.168.130.81"
 #define CU_IP_V4_ADDR "192.168.130.82"
 #define RIC_IP_V4_ADDR "192.168.130.80"
-#define DU_PORT 38472
-#define CU_PORT 38472
-#define RIC_PORT 36421
+
+#define F1_SCTP_PORT 38472
+#define E2_SCTP_PORT 36421
 #endif
 
 #define DU_EGTP_PORT  39001
@@ -41,7 +41,7 @@
 #define NR_PCI 1
 #define NR_CELL_ID 1
 
-#define DU_NAME "ORAN_OAM_DU"
+#define DU_NAME "ORAN OAM DU"
 #define CELL_TYPE SMALL
 
 //TODO: while testing for TDD, Mu1 and 100 MHz, this flag must be enabled
@@ -304,13 +304,13 @@
 /* Macros for Drx configuration */
 #define DRX_ONDURATION_TIMER_VALUE_PRESENT_IN_MS true
 #define DRX_ONDURATION_TIMER_VALUE_IN_SUBMS 32
-#define DRX_ONDURATION_TIMER_VALUE_IN_MS 1
+#define DRX_ONDURATION_TIMER_VALUE_IN_MS 10
 #define DRX_INACTIVITY_TIMER 2
 #define DRX_HARQ_RTT_TIMER_DL 56
 #define DRX_HARQ_RTT_TIMER_UL 56
 #define DRX_RETRANSMISSION_TIMER_DL 4
 #define DRX_RETRANSMISSION_TIMER_UL 4
-#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 20
+#define DRX_LONG_CYCLE_START_OFFSET_CHOICE 40
 #define DRX_LONG_CYCLE_START_OFFSET_VAL 8
 #define DRX_SHORT_CYCLE_PRESENT true
 #define DRX_SHORT_CYCLE 2