#define EVENT_UE_DELETE_RSP_TO_MAC 16
#define EVENT_CELL_DELETE_REQ_TO_SCH 17
#define EVENT_CELL_DELETE_RSP_TO_MAC 18
+#define EVENT_LONG_BSR 19
/*macros*/
#define RAR_PAYLOAD_SIZE 10 /* As per spec 38.321, sections 6.1.5 and 6.2.3, RAR PDU is 8 bytes long and 2 bytes of padding */
#define TX_PAYLOAD_HDR_LEN 32 /* Intel L1 requires adding a 32 byte header to transmitted payload */
+#define UL_TX_BUFFER_SIZE 5
#define MAX_NUM_CONFIG_SLOTS 160 /*Max number of slots as per the numerology*/
#define MAX_NUM_K0_IDX 16 /* Max number of pdsch time domain downlink allocation */
uint32_t schBytes; /* Number of scheduled bytes */
}LcSchInfo;
-typedef struct dlMsgAlloc
+typedef struct dlMsgSchedInfo
{
- uint16_t crnti;
uint8_t numLc;
LcSchInfo lcSchInfo[MAX_NUM_LC]; /* Scheduled LC info */
BwpCfg bwp;
DlPduType pduPres;
uint8_t pdschSlot;
DlMsgInfo dlMsgInfo;
+}DlMsgSchInfo;
+
+typedef struct dlMsgAlloc
+{
+ uint16_t crnti;
+ uint8_t numSchedInfo;
+ DlMsgSchInfo dlMsgSchedInfo[2];
}DlMsgAlloc;
typedef struct schSlotValue
DciInfo *ulGrant;
/* Allocation from dedicated DL msg */
- DlMsgAlloc *dlMsgAlloc;
+ DlMsgAlloc *dlMsgAlloc[MAX_NUM_UE];
}DlSchedInfo;
SchPdcchConfig pdcchCfg;
bool pdschCfgPres;
SchPdschConfig pdschCfg;
+ bool k0K1TblPrsnt;
SchK0K1TimingInfoTbl k0K1InfoTbl;
}SchInitalDlBwp;
SchPucchCfg pucchCfg;
bool puschCfgPres;
SchPuschCfg puschCfg;
+ bool k2TblPrsnt;
SchK2TimingInfoTbl k2InfoTbl;
}SchInitialUlBwp;