}
/* fill bwp cfg */
- dciInfo->bwpCfg.subcarrierSpacing = cellCb->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
- dciInfo->bwpCfg.cyclicPrefix = cellCb->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
- dciInfo->bwpCfg.freqAlloc.startPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.startPrb;
- dciInfo->bwpCfg.freqAlloc.numPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.numPrb;
+ dciInfo->bwpCfg.subcarrierSpacing = cellCb->sib1SchCfg.bwp.subcarrierSpacing;
+ dciInfo->bwpCfg.cyclicPrefix = cellCb->sib1SchCfg.bwp.cyclicPrefix;
+ dciInfo->bwpCfg.freqAlloc.startPrb = cellCb->cellCfg.dlCfgCommon.schInitialDlBwp.bwp.freqAlloc.startPrb;
+ dciInfo->bwpCfg.freqAlloc.numPrb = cellCb->cellCfg.dlCfgCommon.schInitialDlBwp.bwp.freqAlloc.numPrb;
/*fill coreset cfg */
//Considering number of RBs in coreset1 is same as coreset0
//Considering coreset1 also starts from same symbol as coreset0
dciInfo->coresetCfg.startSymbolIndex = searchSpaceIdxTable[0][3];
dciInfo->coresetCfg.durationSymbols = coresetIdxTable[0][2];
- memcpy(dciInfo->coresetCfg.freqDomainResource, cellCb->cellCfg.schInitialDlBwp.pdcchCommon.commonSearchSpace.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
+ memcpy(dciInfo->coresetCfg.freqDomainResource, cellCb->cellCfg.dlCfgCommon.schInitialDlBwp.pdcchCommon.commonSearchSpace.freqDomainRsrc, FREQ_DOM_RSRC_SIZE);
dciInfo->coresetCfg.cceRegMappingType = 1; /* coreset0 is always interleaved */
dciInfo->coresetCfg.regBundleSize = 6; /* spec-38.211 sec 7.3.2.2 */
dciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0] = 0;
dciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0 = 0;
dciInfo->dciInfo.txPdcchPower.powerControlOffsetSS = 0;
- dciInfo->dciInfo.pdschCfg = NULL; /* No DL data being sent */
+ memset(&dciInfo->dciInfo.pdschCfg, 0, sizeof(PdschCfg));
msg3HqProc->tbInfo.txCntr++;
puschInfo->harqProcId = msg3HqProc->procId;
dciInfo->crnti = ueCb->crnti;
/* fill bwp cfg */
- dciInfo->bwpCfg.subcarrierSpacing = cellCb->cellCfg.sib1SchCfg.bwp.subcarrierSpacing;
- dciInfo->bwpCfg.cyclicPrefix = cellCb->cellCfg.sib1SchCfg.bwp.cyclicPrefix;
- dciInfo->bwpCfg.freqAlloc.startPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.startPrb;
- dciInfo->bwpCfg.freqAlloc.numPrb = cellCb->cellCfg.schInitialDlBwp.bwp.freqAlloc.numPrb;
+ dciInfo->bwpCfg.subcarrierSpacing = cellCb->sib1SchCfg.bwp.subcarrierSpacing;
+ dciInfo->bwpCfg.cyclicPrefix = cellCb->sib1SchCfg.bwp.cyclicPrefix;
+ dciInfo->bwpCfg.freqAlloc.startPrb = cellCb->cellCfg.dlCfgCommon.schInitialDlBwp.bwp.freqAlloc.startPrb;
+ dciInfo->bwpCfg.freqAlloc.numPrb = cellCb->cellCfg.dlCfgCommon.schInitialDlBwp.bwp.freqAlloc.numPrb;
/*fill coreset cfg */
//Considering number of RBs in coreset1 is same as coreset0
dciInfo->dciInfo.beamPdcchInfo.prg[0].beamIdx[0] = 0;
dciInfo->dciInfo.txPdcchPower.beta_pdcch_1_0 = 0;
dciInfo->dciInfo.txPdcchPower.powerControlOffsetSS = 0;
- dciInfo->dciInfo.pdschCfg = NULL; /* No DL data being sent */
+ memset(&dciInfo->dciInfo.pdschCfg, 0, sizeof(PdschCfg));
return ROK;
}