#include "du_app_mac_inf.h"
#include "mac_sch_interface.h"
#include "sch.h"
+#include "sch_tmr.h"
#include "sch_utils.h"
/**
uint8_t k0TblIdx = 0, k1TblIdx = 0, k2TblIdx = 0;
uint8_t k0Index = 0, k1Index = 0, k2Index = 0;
uint8_t k0 = 0, k1 = 0, k2 = 0;
- uint8_t numK1 = 0;
+ uint8_t numK1 = 0, ret = OK;
uint8_t puschMu = 0;
uint8_t msg3Delta = 0, msg3MinSchTime = 0;
#ifdef NR_TDD
}
/* Calculating time frame to send DCI for RAR */
- ADD_DELTA_TO_TIME(currTime, dciTime, PHY_DELTA_DL + SCHED_DELTA, cell->numSlots);
+ ADD_DELTA_TO_TIME(currTime, dciTime, gConfigInfo.gPhyDeltaDl + SCHED_DELTA, cell->numSlots);
dciSlot = dciTime.slot;
#ifdef NR_TDD
/* Consider this slot for sending DCI, only if it is a DL slot */
ADD_DELTA_TO_TIME(dciTime, rarTime, k0, cell->numSlots);
rarSlot = rarTime.slot;
- /* If PDSCH is already scheduled on this slot, cannot schedule PDSCH for another UE here. */
- if(cell->schDlSlotInfo[rarSlot]->pdschUe != 0)
- continue;
-
/* If Contention-FREE RA is in progress, allocate resources for
* PUCCH for next UL message */
if(cell->raReq[ueId-1]->isCFRA)
if(cell->raReq[ueId-1]->isCFRA)
{
/* Allocate resources for PUCCH */
- schAllocPucchResource(cell, pucchTime, cell->raReq[ueId-1]->rachInd->crnti,NULLP, FALSE, NULLP);
+ cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
+ ret = schAllocPucchResource(cell, pucchTime, NULLP, NULLP, NULLP);
+ if(ret == RFAILED)
+ {
+ SCH_FREE(dciSlotAlloc, sizeof(RarAlloc));
+ cell->schDlSlotInfo[dciSlot]->rarAlloc[ueId-1] = NULLP;
+ DU_LOG("\nERROR --> SCH : Resource allocation for PUCCH failed for CFRA!");
+ return false;
+
+ }
}
else
{
+ cell->schUlSlotInfo[msg3Time.slot]->puschUe = ueId;
/* Allocate resources for msg3 */
msg3PuschInfo = schAllocMsg3Pusch(schInst, cell->raReq[ueId-1]->rachInd->crnti, k2Index, msg3Time, &(cell->raCb[ueId-1].msg3HqProc), FALSE);
if(msg3PuschInfo)
SCH_ALLOC(dciSlotAlloc->rarPdschCfg, sizeof(PdschCfg));
if(dciSlotAlloc->rarPdschCfg)
{
- memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg, sizeof(PdschCfg));
+ memcpy(dciSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg, sizeof(PdschCfg));
}
else
{
SCH_ALLOC(rarSlotAlloc->rarPdschCfg, sizeof(PdschCfg));
if(rarSlotAlloc->rarPdschCfg)
{
- memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci.pdschCfg,sizeof(PdschCfg));
+ memcpy(rarSlotAlloc->rarPdschCfg, &dciSlotAlloc->rarPdcchCfg->dci[0].pdschCfg,sizeof(PdschCfg));
}
else
{
}
cell->schDlSlotInfo[dciSlot]->pdcchUe = ueId;
- cell->schDlSlotInfo[rarSlot]->pdschUe = ueId;
- if(cell->raReq[ueId-1]->isCFRA)
- cell->schUlSlotInfo[pucchTime.slot]->pucchUe = ueId;
- else
- cell->schUlSlotInfo[msg3Time.slot]->puschUe = ueId;
/* Create raCb at SCH */
createSchRaCb(ueId, cell->raReq[ueId-1], schInst);
pdcch->coresetCfg.shiftIndex = cell->cellCfg.phyCellId;
pdcch->coresetCfg.precoderGranularity = 0; /* sameAsRegBundle */
pdcch->numDlDci = 1;
- pdcch->dci.rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */
- pdcch->dci.scramblingId = cell->cellCfg.phyCellId;
- pdcch->dci.scramblingRnti = 0;
- pdcch->dci.cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
- pdcch->dci.aggregLevel = 4;
- pdcch->dci.beamPdcchInfo.numPrgs = 1;
- pdcch->dci.beamPdcchInfo.prgSize = 1;
- pdcch->dci.beamPdcchInfo.digBfInterfaces = 0;
- pdcch->dci.beamPdcchInfo.prg[0].pmIdx = 0;
- pdcch->dci.beamPdcchInfo.prg[0].beamIdx[0] = 0;
- pdcch->dci.txPdcchPower.beta_pdcch_1_0 = 0;
- pdcch->dci.txPdcchPower.powerControlOffsetSS = 0;
-
- pdsch = &pdcch->dci.pdschCfg;
+ pdcch->dci[0].rnti = cell->raReq[ueId-1]->raRnti; /* RA-RNTI */
+ pdcch->dci[0].scramblingId = cell->cellCfg.phyCellId;
+ pdcch->dci[0].scramblingRnti = 0;
+ pdcch->dci[0].cceIndex = 4; /* considering SIB1 is sent at cce 0-1-2-3 */
+ pdcch->dci[0].aggregLevel = 4;
+ pdcch->dci[0].beamPdcchInfo.numPrgs = 1;
+ pdcch->dci[0].beamPdcchInfo.prgSize = 1;
+ pdcch->dci[0].beamPdcchInfo.digBfInterfaces = 0;
+ pdcch->dci[0].beamPdcchInfo.prg[0].pmIdx = 0;
+ pdcch->dci[0].beamPdcchInfo.prg[0].beamIdx[0] = 0;
+ pdcch->dci[0].txPdcchPower.beta_pdcch_1_0 = 0;
+ pdcch->dci[0].txPdcchPower.powerControlOffsetSS = 0;
+
+ pdsch = &pdcch->dci[0].pdschCfg;
/* fill the PDSCH PDU */
uint8_t cwCount = 0;
pdsch->pduBitmap = 0; /* PTRS and CBG params are excluded */