/* macros */
#define SCH_INST_START 1
#define SCH_MAX_INST 1
-#define SCH_NUM_SLOTS 10 /*forcing this to 10 */
+#define SCH_MU0_NUM_SLOTS 10
+#define SCH_MU1_NUM_SLOTS 20
+#define SCH_MU2_NUM_SLOTS 30
+#define SCH_MU3_NUM_SLOTS 40
+#define SCH_MU4_NUM_SLOTS 50
#define SCH_MAX_SFN 1024
#define MAX_NUM_RB 106 /* value for numerology 0 15Khz */
#define SCH_MIB_TRANS 80
#define RAR_DELAY 2
#define MSG4_DELAY 1
#define PUSCH_START_RB 15
-#define PUCCH_NUM_PRB_FORMAT_0 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
+#define PUCCH_NUM_PRB_FORMAT_0_1_4 1 /* number of PRBs in freq domain, spec 38.213 - 9.2.1 */
#define SI_RNTI 0xFFFF
#define P_RNTI 0xFFFE
#define DMRS_MAP_TYPE_A 1
#define NUM_DMRS_SYMBOLS 12
#define DMRS_ADDITIONAL_POS 2
+#define SCH_DEFAULT_K1 1
#define CRC_FAILED 0
#define CRC_PASSED 1
typedef struct schCellCb SchCellCb;
typedef struct schUeCb SchUeCb;
+typedef enum
+{
+ SCH_NUMEROLOGY_0,
+ SCH_NUMEROLOGY_1,
+ SCH_NUMEROLOGY_2,
+ SCH_NUMEROLOGY_3,
+ SCH_NUMEROLOGY_4
+}SchNumerology;
+
typedef enum
{
SCH_UE_STATE_INACTIVE,
typedef struct schLcCtxt
{
+ uint8_t lcId; // logical Channel ID
uint8_t lcp; // logical Channel Prioritization
SchLcState lcState;
uint16_t bo;
}SchDlLcCtxt;
+typedef struct schDlCb
+{
+ uint8_t numDlLc;
+ SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
+}SchDlCb;
+
typedef struct schUlLcCtxt
{
- SchLcState lcState;
+ SchLcState lcState;
+ uint8_t lcId;
uint8_t priority;
uint8_t lcGroup;
uint8_t schReqId;
uint8_t bsd; // bucketSizeDuration
}SchUlLcCtxt;
+typedef struct schUlCb
+{
+ uint8_t numUlLc;
+ SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
+}SchUlCb;
+
/**
* @brief
* UE control block
SchCellCb *cellCb;
bool srRcvd;
BsrInfo bsrInfo[MAX_NUM_LOGICAL_CHANNEL_GROUPS];
- uint8_t numUlLc;
- SchUlLcCtxt ulLcCtxt[MAX_NUM_LC];
- uint8_t numDlLc;
- SchDlLcCtxt dlLcCtxt[MAX_NUM_LC];
+ SchUlCb ulInfo;
+ SchDlCb dlInfo;
}SchUeCb;
/**
Inst macInst; /*!< Index of the MAC instance */
uint8_t numSlots; /*!< Number of slots in current frame */
SlotIndInfo slotInfo; /*!< SFN, Slot info being processed*/
- SchDlSlotInfo *schDlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in DL */
- SchUlSlotInfo *schUlSlotInfo[SCH_NUM_SLOTS]; /*!< SCH resource allocations in UL */
+ SchDlSlotInfo **schDlSlotInfo; /*!< SCH resource allocations in DL */
+ SchUlSlotInfo **schUlSlotInfo; /*!< SCH resource allocations in UL */
SchCellCfg cellCfg; /*!< Cell ocnfiguration */
uint8_t ssbStartSymbArr[SCH_MAX_SSB_BEAM]; /*!<start symbol per SSB beam */
SchRaCb raCb[MAX_NUM_UE]; /*!< Rach Cb */
- uint16_t numActvUe;
- uint32_t actvUeBitMap;
- uint32_t boIndBitMap;
- SchUeCb ueCb[MAX_NUM_UE];
+ uint16_t numActvUe; /*!<Number of active UEs */
+ uint32_t actvUeBitMap; /*!<Bit map to find active UEs */
+ uint32_t boIndBitMap; /*!<Bit map to indicate UEs that have recevied BO */
+ SchUeCb ueCb[MAX_NUM_UE]; /*!<Pointer to UE contexts of this cell */
+#ifdef NR_TDD
+ uint8_t numSlotsInPeriodicity; /*!< number of slots in configured periodicity and SCS */
+ uint32_t slotFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S slots. 00-D, 01-U, 10-S */
+ uint32_t symbFrmtBitMap; /*!< 2 bits must be read together to determine D/U/S symbols. 00-D, 01-U, 10-S */
+#endif
}SchCellCb;
/**