[Epic-ID: ODUHIGH-517][Task-ID: ODUHIGH-540][SubTask-Id: ODUHIGH-549] Multi PDSCH...

[o-du/l2.git] / src / 5gnrsch / sch.h

diff --git a/src/5gnrsch/sch.h b/src/5gnrsch/sch.h
index 3d5e9f1..39aa042 100644 (file)
--- a/src/5gnrsch/sch.h
+++ b/src/5gnrsch/sch.h
@@ -79,6 +79,15 @@
 
 #define SCH_TQ_SIZE 10
 
+/*3GPP 38.331,'frequencyDomainResources' :Number of PRBs per Resource Block Group*/
+#define NUM_PRBS_PER_RBG 6 
+
+/*3GPP 38.214 Table 5.2.2.1-2*/
+#define MAX_NUM_CQI_IDX 16
+
+/*3GPP 38.211 Table 7.3.2.1-1*/
+#define MAX_NUM_AGG_LVL 5
+
 typedef struct schDlHqProcCb SchDlHqProcCb;
 typedef struct schUlHqEnt SchUlHqEnt;
 typedef struct schRaReq SchRaReq;
@@ -316,8 +325,7 @@ typedef struct schDlSlotInfo
    uint8_t      ssbIdxSupported;          /*!< Max SSB index */
    SsbInfo      ssbInfo[MAX_SSB_IDX];     /*!< SSB info */
    bool         sib1Pres;                 /*!< Flag to determine if SIB1 is present in this slot */
-   uint8_t      pdcchUe;                  /*!< UE for which PDCCH is scheduled in this slot */
-   uint8_t      pdschUe;                  /*!< UE for which PDSCH is scheduled in this slot */
+   uint8_t      pdcchUe;                  /*!< UE for which PDCCH Common is scheduled in this slot */
    RarAlloc     *rarAlloc[MAX_NUM_UE];    /*!< RAR allocation per UE*/
    DciInfo      *ulGrant;
    DlMsgSchInfo *dlMsgAlloc[MAX_NUM_UE];  /*!< Dl msg allocation per UE*/
@@ -462,6 +470,18 @@ typedef struct  schDrxUeCb
    CmLList   *shortCycleTmrExpiryNodeInfo; /* Node present in short cycle exp list*/
 }SchDrxUeCb;
 #endif
+
+typedef struct schPdcchInfo
+{
+   SchControlRsrcSet *cRSetRef; /*Coreset Cfg reference from SchUeCfgCb*/
+   SchSearchSpace    *ssRef;    /*SearchSpace Cfg reference from SchUeCfgCb*/
+   uint16_t          totalPrbs; /*Total PRBs configured for this CORESET*/
+   uint8_t           nrOfPRBPerCce; /*CCE Size*/
+   uint8_t           totalCceCount; /*Count of CCE in this CORESET*/
+   uint8_t           cqiIndxAggLvlMap[MAX_NUM_CQI_IDX];/*Agg Level to be used for each CQI Index*/
+   uint32_t          *y; /*Coefficient variable to calculate CCE Index as per 3gpp Spec 38.213 Sec 10.1*/
+}SchPdcchInfo;
+
 /**
  * @brief
  * UE control block
@@ -494,6 +514,7 @@ typedef struct schUeCb
    SchK0K1TimingInfoTbl k0K1InfoTbl;
    bool                 k2TblPrsnt;
    SchK2TimingInfoTbl   k2InfoTbl;
+   SchPdcchInfo         pdcchInfo[MAX_NUM_CRSET];
 }SchUeCb;
 
 /**
@@ -781,6 +802,8 @@ LcInfo* handleLcLList(CmLListCp *lcLL, uint8_t lcId, ActionTypeLL action);
 void prbAllocUsingRRMPolicy(CmLListCp *lcLL, bool dedicatedPRB, uint16_t mcsIdx,uint8_t numSymbols,\
                       uint16_t *sharedPRB, uint16_t *reservedPRB, bool *isTxPayloadLenAdded, bool *srRcvd);
 void updateBsrAndLcList(CmLListCp *lcLL, BsrInfo *bsrInfo, uint8_t status);
+uint8_t fillUeCoresetAndSsInfo(SchUeCb *ue);
+bool schDlCandidateSelection(SchUeCb *ue,  SlotTimingInfo slotTime);
 
 /*Paging Functions*/
 void schProcPagingCfg(SchCellCb *cell);